q3 training update

Author: ThorKn

Chapter_03_Verilog/c03_lecture.md

@@ -532,11 +532,6 @@ module regfile (input clk,
 endmodule
 ```
 
-### Synthesis result of the register file
-The synthesis result is then a little more confusing:
-
-**TODO: Picture here**
-
 ## Selected feature: Parameterized counter
 The newer variants of Verilog offer an improved version of the parameter feature:
 
@@ -605,7 +600,7 @@ endmodule
 
 ### Synthesis result of the parameterized counter
 
-**TODO: Picture here**
+![Parameterized counter](pics_lecture/parameter_counter.png)
 
 ### An alternative version
 Verilog still offers a (older) possibility for the parameterization of a design:

Chapter_03_Verilog/c03_training_advanced.md

@@ -0,0 +1,34 @@
+---
+title: "Chapter 03 Training"
+author: "Course authors (Git file)"
+aspectratio: 169
+theme: "CambridgeUS"
+colortheme: "rose"
+fonttheme: "professionalfonts"
+urlcolor: red
+linkstyle: bold
+logo: icons/advanced.jpg
+date:
+section-titles: false
+toc: true
+---
+
+# Chapter 3 - Verilog - TRAINING - Advanced
+
+## LSFR
+### Analyse parts of the Verilog source
+
+Find combinational and synchronous parts in
+
+* Code 
+* Schematic
+
+### Generate schematic and JSON
+
+Generate
+* Schematic
+* JSON
+
+### yosys  file
+
+Read the .ys file

Chapter_03_Verilog/c03_training_common.md

@@ -15,23 +15,29 @@ toc: true
 
 # Chapter 3 - Verilog - TRAINING - Common
 
-## LSFR
-### Analyse parts of the Verilog source
+## ORFS examples
 
-Find combinational and synchronous parts in
+### GDC example
 
-* Code 
-* Schematic
+- Find the Verilog file of the gdc example in ORSF
+- Open the Verilog file with an editor
 
-### Generate schematic and JSON
+Questions about the code:
+- What are the port definitions
+- How many inputs and outputs will the chip have?
+- Can you identify other parts of the code?
 
-Generate
-* Schematic
-* JSON
+### IBEX example
+
+- Find the top level Verilog file of the ibex example in ORSF
+- Open the top level Verilog file with an editor
+
+Questions about the code:
+- What are the port definitions?
+- How many inputs and outputs has the top level module?
+- Can you identify other parts of the code?
 
-### yosys  file
 
-Read the .ys file
 
 
 

Chapter_03_Verilog/pics_lecture/parameter_counter.pdf

@@ -15,10 +15,20 @@ toc: true
 
 # Chapter 04 - OpenROAD first run
 
-## Openroad GUI
-```
-openroad -gui
-```
+## Doing this chapter
+
+- This chapter is mostly a training.
+- We will try to get our first results.
+- Example projects are available.
+
+## Basic ORFS
+
+### Find the flow directory
+
+### Checking the tools
+
+### 
+
 
 ## Example pick