diff --git a/README.md b/README.md
index 65086ff..d867a38 100644
--- a/README.md
+++ b/README.md
@@ -41,6 +41,7 @@ Functional Simulation:
       (The path of cshrc could vary depending on the installation destination)
       
 	After this you can see the window like below 
+<img width="1606" height="940" alt="Screenshot 2025-11-21 192343" src="https://github.com/user-attachments/assets/66be87ac-22e6-4521-973b-7112a514ae27" />
 
 
 ## Fig 2: Invoke the Cadence Environment
@@ -74,12 +75,14 @@ Functional Simulation:
 	linux:/> nclaunch&                 // On subsequent calls to NCVERILOG
 
 It will invoke the nclaunch window for functional simulation we can compile,elaborate and simulate it using Multiple step
+<img width="1920" height="1200" alt="Screenshot 2025-11-21 180422" src="https://github.com/user-attachments/assets/0737e78c-b76c-47bd-a297-60644dba0f28" />
 
 ## Fig 3: Setting Multi-step simulation
 
 Select Multiple Step and then select “Create cds.lib File” as shown in below figure
 
 Click the cds.lib file and save the file by clicking on Save option
+<img width="1920" height="1200" alt="2" src="https://github.com/user-attachments/assets/d44a41eb-0a65-4bf8-abb3-2a6fe8ee3461" />
 
 ## Fig 4: cds.lib file Creation
 
@@ -88,6 +91,7 @@ Click the cds.lib file and save the file by clicking on Save option
 	Select “Don’t include any libraries (verilog design)” from “New cds.lib file” and click on “OK” as in below figure
 
 	We are simulating verilog design without using any libraries
+<img width="1920" height="1200" alt="2" src="https://github.com/user-attachments/assets/311ce6fc-6b21-4c78-9bbc-01e36be109b5" />
 
 ## Fig 5: Selection of Don’t include any libraries
 
@@ -98,6 +102,7 @@ Click the cds.lib file and save the file by clicking on Save option
 	Left side you can see the HDL files. Right side of the window has worklib and snapshots directories listed.
 
 	Worklib is the directory where all the compiled codes are stored while Snapshot will have output of elaboration which in turn goes for simulation
+<img width="1108" height="912" alt="image" src="https://github.com/user-attachments/assets/29901d31-28d1-445a-9abc-8b8dc2ca9227" />
 
 ## Fig 6: Nclaunch Window
 
@@ -122,6 +127,7 @@ i.e Cadence IES command for compile: ncverilog +access+rwc -compile fa.v
 Left side select the file and in Tools : launch verilog compiler with current selection will get enable. Click it to compile the code 
 
 Worklib is the directory where all the compiled codes are stored while Snapshot will have output of elaboration which in turn goes for simulation 
+<img width="1108" height="912" alt="image" src="https://github.com/user-attachments/assets/4dd7ad59-1f43-470e-8009-b7f24e645bdb" />
 
 ## Fig 7: Compiled database in worklib
 
@@ -151,8 +157,10 @@ It contains statements that map logical library names to their physical director
 9.	It also establishes net connectivity and prepares all of this for simulation
     
 	After elaboration the file will come under snapshot. Select the test bench and simulate it. 
+<img width="1920" height="1200" alt="3,4" src="https://github.com/user-attachments/assets/e000646f-71cb-425b-9144-2263f7f08ab6" />
 
 ## Fig 8: Elaboration Launch Option
+<img width="1920" height="1200" alt="3,4" src="https://github.com/user-attachments/assets/a833b31c-d8eb-4b73-9e5e-f0d15d702729" />
 
 ### Step 3: Simulation: – Simulate with the given test vectors over a period of time to observe the output behaviour. 
 
@@ -165,10 +173,11 @@ It contains statements that map logical library names to their physical director
 	Steps for simulation – Run the simulation command with simulator options
 
 ## Fig 9: Design Browser window for simulation
+<img width="1280" height="636" alt="image" src="https://github.com/user-attachments/assets/d112d774-870f-46e0-a391-0e9acfe8f88e" />
 
 ## Fig 10: Simulation Waveform Window
+<img width="1280" height="636" alt="image" src="https://github.com/user-attachments/assets/e6337209-8f25-4115-90e2-d96b516f9e0e" />
 
-## Fig 11: Simulation Waveform Window
 
 ### Result