diff --git a/README.md b/README.md
index 3a59407..7b735cf 100644
--- a/README.md
+++ b/README.md
@@ -1,3 +1,5 @@
+# Name : ALTRIN CETRICK
+# Reg No : 212222060015
 # EXP1: 4 Bit Adder functionality verification
 
 ## Aim:
@@ -71,18 +73,26 @@ Developed by: Register Number*/
       (The path of cshrc could vary depending on the installation destination)
       
 	After this you can see the window like below 
+![Screenshot 2024-10-03 164035](https://github.com/user-attachments/assets/00d90163-a7cb-496d-a70b-2bc4f8e4af41)
+
 
 ### Fig 3:Invoke the Cadence Environment
 
 	To Launch Simulation tool 
-
-•	linux:/> nclaunch -new& // “-new” option is used for invoking NCVERILOG for the first time for any design 
+```bash
+•	linux:/> nclaunch -new& // “-new” option is used for invoking NCVERILOG for the first time for any design
+```
 
 or
+```bash
 
-•	linux:/> nclaunch& // On subsequent calls to NCVERILOG 
+•	linux:/> nclaunch& // On subsequent calls to NCVERILOG
+```
 
 	It will invoke the nclaunch window for functional simulation we can compile,elaborate and simulate it using Multiple Step .
+![Screenshot 2024-10-04 155944](https://github.com/user-attachments/assets/64936a8b-105b-41c4-ac3d-ea83063fe16b)
+
+
 
 ### Fig 4:Setting Multi-step simulation
 
@@ -90,6 +100,10 @@ or
 
 	Click the cds.lib file and save the file by clicking on Save option 
 
+![Screenshot 2024-10-03 164107](https://github.com/user-attachments/assets/df7662f9-1604-43b3-9c64-b4d701a1cf55)
+
+
+
 ### Fig 5:cds.lib file Creation
 
 	Save cds.lib file and select the correct option for cds.lib file format based on the HDL Language and Libraries used. 
@@ -112,7 +126,12 @@ or
 
 	To perform the function simulation, the following three steps are involved Compilation, Elaboration and Simulation. 
 
+
+
 ### Fig 7: Nclaunch Window
+![Screenshot 2024-10-03 164140](https://github.com/user-attachments/assets/65594e35-66b1-4bab-a1a2-653e589b6ab2)
+
+
 
 ## Step 1: Compilation:– Process to check the correct Verilog language syntax and usage 
 
@@ -138,6 +157,8 @@ i.e Cadence IES command for compile: ncverilog +access+rwc -compile fa.v
 	Select the test bench and compile it. It will come under worklib. Under Worklib you can see the module and test-bench. 
 
 	The cds.lib file is an ASCII text file. It defines which libraries are accessible and where they are located. It contains statements that map logical library names to their physical directory paths. For this Design, you will define a library called “worklib”
+![Screenshot 2024-10-03 164233](https://github.com/user-attachments/assets/14aae49e-8529-4e11-a53c-b189872a22ab)
+
 
 ## Step 2: Elaboration:– To check the port connections in hierarchical design 
 	Inputs: Top level design / test bench Verilog codes 
@@ -155,6 +176,9 @@ i.e Cadence IES command for compile: ncverilog +access+rwc -compile fa.v
 	After elaboration the file will come under snapshot. Select the test bench and elaborate it.
 
 ### Fig 9: Elaboration Launch Option
+![Screenshot 2024-10-03 164158](https://github.com/user-attachments/assets/9b1f90a9-8700-4c42-afd0-b53a4c4baf5c)
+
+
 
 ## Step 3: Simulation: – Simulate with the given test vectors over a period of time to observe the output behaviour. 
 
@@ -168,9 +192,15 @@ i.e Cadence IES command for compile: ncverilog +access+rwc -compile fa.v
 
 ### Fig 10: Design Browser window for simulation
 
+![Screenshot 2024-10-03 164233](https://github.com/user-attachments/assets/178357e0-e7c3-40f3-ba44-aa76eaa9db93)
+
+
 ### Fig 11: Launching Simulation Waveform WindowSimulation Waveform Window
 
+![Screenshot 2024-10-03 164250](https://github.com/user-attachments/assets/34bc2871-e02e-416f-b9fa-b500dc6b0162)
+
 ### Fig 12: Simulation Waveform Window
+![Screenshot 2024-10-03 164256](https://github.com/user-attachments/assets/4be4c3f9-c221-403b-bd36-924db495656d)