diff --git a/Ghidra/Processors/HCS08/data/languages/HCS_HC.sinc b/Ghidra/Processors/HCS08/data/languages/HCS_HC.sinc
index 3e6d10db34e..9072d64f233 100644
--- a/Ghidra/Processors/HCS08/data/languages/HCS_HC.sinc
+++ b/Ghidra/Processors/HCS08/data/languages/HCS_HC.sinc
@@ -114,15 +114,15 @@ oprx8_16_SP: imm8,SP is imm8 & SP { address:2 = SP + imm8; export *:2 addres
# X or HIX addressing
@if defined(HC05)
-oprx8_8_X: imm8,X is imm8 & X { address:2 = zext(X) + imm8; export *:1 address; }
-oprx16_8_X: imm16,X is imm16 & X { address:2 = zext(X) + imm16; export *:1 address; }
-comma_X: ","X is X { address:2 = zext(X); export *:1 address; }
+oprx8_8_X: imm8,X is imm8 & X { address:2 = zext(X) + imm8; export address; }
+oprx16_8_X: imm16,X is imm16 & X { address:2 = zext(X) + imm16; export address; }
+comma_X: ","X is X { address:2 = zext(X); export address; }
@endif
@if defined(HCS08) || defined(HC08)
-oprx8_8_X: imm8,X is imm8 & X { address:2 = HIX + imm8; export *:1 address; }
-oprx16_8_X: imm16,X is imm16 & X { address:2 = HIX + imm16; export *:1 address; }
-comma_X: ","X is X { address:2 = HIX; export *:1 address; }
+oprx8_8_X: imm8,X is imm8 & X { address:2 = HIX + imm8; export address; }
+oprx16_8_X: imm16,X is imm16 & X { address:2 = HIX + imm16; export address; }
+comma_X: ","X is X { address:2 = HIX; export address; }
@endif
@if defined(HCS08)
@@ -136,9 +136,9 @@ oprx16_16_X: imm16,X is imm16 & X { address:2 = HIX + imm16; export *:2 a
OP1: iopr8i is op4_6=2; iopr8i { export iopr8i; }
OP1: opr8a_8 is op4_6=3; opr8a_8 { export opr8a_8; }
OP1: opr16a_8 is op4_6=4; opr16a_8 { export opr16a_8; }
-OP1: oprx16_8_X is op4_6=5; oprx16_8_X { export oprx16_8_X; }
-OP1: oprx8_8_X is op4_6=6; oprx8_8_X { export oprx8_8_X; }
-OP1: comma_X is op4_6=7 & comma_X { export comma_X; }
+OP1: oprx16_8_X is op4_6=5; oprx16_8_X { export *:1 oprx16_8_X; }
+OP1: oprx8_8_X is op4_6=6; oprx8_8_X { export *:1 oprx8_8_X; }
+OP1: comma_X is op4_6=7 & comma_X { export *:1 comma_X; }
@if defined(HCS08) || defined(HC08)
op2_opr8a: imm8 is imm8 { export *:1 imm8; }
@@ -2074,4 +2074,3 @@ macro Push2(operand) {
wait();
}
@endif
-
diff --git a/Ghidra/Processors/MC6800/data/languages/6805.slaspec b/Ghidra/Processors/MC6800/data/languages/6805.slaspec
index 7edef3f4951..f314c0a3116 100644
--- a/Ghidra/Processors/MC6800/data/languages/6805.slaspec
+++ b/Ghidra/Processors/MC6800/data/languages/6805.slaspec
@@ -42,13 +42,13 @@ OP1: imm8 is op4_6=3; imm8 { export *:1 imm8; }
OP1: imm16 is op4_6=4; imm16 { export *:1 imm16; }
OP1: imm16,X is op4_6=5 & X; imm16 { tmp:2 = imm16 + zext(X); export *:1 tmp; }
OP1: imm8,X is op4_6=6 & X; imm8 { tmp:2 = imm8 + zext(X); export *:1 tmp; }
-OP1: X is op4_6=7 & X { tmp:2 = zext(X); export *:1 tmp; }
+OP1: ","X is op4_6=7 & X { tmp:2 = zext(X); export *:1 tmp; }
ADDR: imm8 is op4_6=3; imm8 { export *:1 imm8; }
ADDR: imm16 is op4_6=4; imm16 { export *:1 imm16; }
-ADDRI: imm16,X is op4_6=5 & X; imm16 { tmp:2 = imm16 + zext(X); export tmp; }
-ADDRI: imm8,X is op4_6=6 & X; imm8 { tmp:2 = imm8 + zext(X); export tmp; }
-ADDRI: X is op4_6=7 & X { tmp:2 = zext(X); export tmp; }
+ADDRI: imm16,X is op4_6=5 & X; imm16 { tmp:2 = imm16 + zext(X); export *:1 tmp; }
+ADDRI: imm8,X is op4_6=6 & X; imm8 { tmp:2 = imm8 + zext(X); export *:1 tmp; }
+ADDRI: ","X is op4_6=7 & X { tmp:2 = zext(X); export *:1 tmp; }
DIRECT: imm8 is imm8 { export *:1 imm8; }
@@ -666,4 +666,3 @@ DIRECT: imm8 is imm8 { export *:1 imm8; }
{
I = 0;
}
-