diff --git a/.gitignore b/.gitignore index c399ac859..7a93fe248 100644 --- a/.gitignore +++ b/.gitignore @@ -5,6 +5,7 @@ *.o *.ko *.obj +*.objdump #*.elf # Linker output diff --git a/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwerr.vhd b/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwerr.vhd index 3ad602e4d..03ffa099f 100644 --- a/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwerr.vhd +++ b/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwerr.vhd @@ -89,7 +89,7 @@ architecture spwerr_arch of spwerr is begin -- Combinatorial process - process(r, err_usr_i, err_link_i) is + process(r, rst, err_usr_i, err_link_i) is variable v : regs_type; begin v := r; @@ -319,16 +319,25 @@ begin end if; end if; + -- Reset + if rst = '1' then + v := regs_reset; + err_usr_o.err_stat_o <= stby; + err_link_o.err_disc_o <= '0'; + err_link_o.err_par_o <= '0'; + err_link_o.err_esc_o <= '0'; + err_link_o.err_credit_o <= '0'; + err_link_o.err_ch_seq_o <= '0'; + end if; + -- Update future state regs. rin <= v; end process; - -- Sequential process - rst, update regs. - process(clk, rst) is + -- Sequential process - update regs. + process(clk) is begin - if (rst = '1') then - r <= regs_reset; - elsif rising_edge(clk) then + if rising_edge(clk) then r <= rin; end if; end process; diff --git a/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwlink.vhd b/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwlink.vhd index 8670ffd27..307ed77ed 100644 --- a/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwlink.vhd +++ b/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwlink.vhd @@ -12,324 +12,320 @@ use work.spwpkg.all; entity spwlink is - generic( - -- Reset time expressed in system clock cycles. - -- Should be 6.4 us (5.82 us .. 7.2 us) according to the standard. - reset_time : integer - ); - - port( - -- System clock. - clk : in std_logic; - -- Synchronous reset (active-high). - -- Disconnects, resets error conditions, puts the link state machine - -- in state ErrorReset. - rst : in std_logic; - -- Link level inputs. - linki : in spw_link_in_type; - -- Link level outputs. - linko : out spw_link_out_type; - -- Receiver enable signal to spwrecv. - rxen : out std_logic; - -- Output signals from spwrecv. - recvo : in spw_recv_out_type; - -- Input signals for spwxmit. - xmiti : out spw_xmit_in_type; - -- Output signals from spwxmit. - xmito : in spw_xmit_out_type - ); + generic( + -- Reset time expressed in system clock cycles. + -- Should be 6.4 us (5.82 us .. 7.2 us) according to the standard. + reset_time : integer + ); + + port( + -- System clock. + clk : in std_logic; + -- Synchronous reset (active-high). + -- Disconnects, resets error conditions, puts the link state machine + -- in state ErrorReset. + rst : in std_logic; + -- Link level inputs. + linki : in spw_link_in_type; + -- Link level outputs. + linko : out spw_link_out_type; + -- Receiver enable signal to spwrecv. + rxen : out std_logic; + -- Output signals from spwrecv. + recvo : in spw_recv_out_type; + -- Input signals for spwxmit. + xmiti : out spw_xmit_in_type; + -- Output signals from spwxmit. + xmito : in spw_xmit_out_type + ); end entity spwlink; architecture spwlink_arch of spwlink is - -- Convert boolean to std_logic. - type bool_to_logic_type is array (boolean) of std_ulogic; - constant bool_to_logic : bool_to_logic_type := (false => '0', true => '1'); - - -- State machine. - type state_type is ( - S_ErrorReset, S_ErrorWait, S_Ready, S_Started, S_Connecting, S_Run); - - -- Registers - type regs_type is record - -- state machine - state : state_type; - -- credit accounting - tx_credit : unsigned(5 downto 0); - rx_credit : unsigned(5 downto 0); - errcred : std_ulogic; - -- reset timer - timercnt : unsigned(10 downto 0); - timerdone : std_ulogic; - -- signal to transmitter - xmit_fct_in : std_ulogic; - end record; - - -- Initial state - constant regs_reset : regs_type := ( - state => S_ErrorReset, - tx_credit => "000000", - rx_credit => "000000", - errcred => '0', - timercnt => to_unsigned(reset_time, 11), - timerdone => '0', - xmit_fct_in => '0'); - - signal r : regs_type := regs_reset; - signal rin : regs_type; - - -- Internal interface - spwerr <-> spwlink - signal link_to_err : spwerr_from_link_type; - signal err_to_link : spwerr_to_link_type; + -- Convert boolean to std_logic. + type bool_to_logic_type is array (boolean) of std_ulogic; + constant bool_to_logic : bool_to_logic_type := (false => '0', true => '1'); + + -- State machine. + type state_type is ( + S_ErrorReset, S_ErrorWait, S_Ready, S_Started, S_Connecting, S_Run); + + -- Registers + type regs_type is record + -- state machine + state : state_type; + -- credit accounting + tx_credit : unsigned(5 downto 0); + rx_credit : unsigned(5 downto 0); + errcred : std_ulogic; + -- reset timer + timercnt : unsigned(10 downto 0); + timerdone : std_ulogic; + -- signal to transmitter + xmit_fct_in : std_ulogic; + end record; + + -- Initial state + constant regs_reset : regs_type := ( + state => S_ErrorReset, + tx_credit => "000000", + rx_credit => "000000", + errcred => '0', + timercnt => to_unsigned(reset_time, 11), + timerdone => '0', + xmit_fct_in => '0'); + + signal r : regs_type := regs_reset; + signal rin : regs_type; + + -- Internal interface - spwerr <-> spwlink + signal link_to_err : spwerr_from_link_type; + signal err_to_link : spwerr_to_link_type; begin - -- Instantiate error controller. - err_inst : spwerr - port map( - clk => clk, - rst => rst, - err_link_i => link_to_err, - err_link_o => err_to_link, - err_usr_i => linki.err_usr_i, - err_usr_o => linko.err_usr_o - ); - - -- Combinatorial process - process(r, rst, linki, recvo, xmito, err_to_link) is - variable v : regs_type; - variable v_timerrst : std_logic; - variable v_xmiti : spw_xmit_in_type; - begin - v := r; - v_timerrst := '0'; - - -- State machine. - case r.state is - - when S_ErrorReset => - -- Wait for timer. - if r.timercnt = 0 then - v.state := S_ErrorWait; - v_timerrst := '1'; - end if; - v.errcred := '0'; - v.xmit_fct_in := '0'; - - when S_ErrorWait => - -- Wait for 2 timer periods. - if ((recvo.errdisc or recvo.errpar or recvo.erresc) = '1') or - ((recvo.gotfct or recvo.tick_out or recvo.rxchar) = '1') then - -- Note: spwrecv will never issue errpar, erresc, gotfct, - -- tick_out or rxchar before the first NULL has been seen. - -- Therefore it's ok here to bail on those conditions - -- without explicitly testing got_null. - v.state := S_ErrorReset; -- error, go back to reset - v_timerrst := '1'; - elsif r.timercnt = 0 then - if r.timerdone = '1' then - v.state := S_Ready; - v_timerrst := '1'; - end if; - end if; - - when S_Ready => - -- Wait for link start. - if ((recvo.errdisc or recvo.errpar or recvo.erresc) = '1') or - ((recvo.gotfct or recvo.tick_out or recvo.rxchar) = '1') then - v.state := S_ErrorReset; -- error, go back to reset - v_timerrst := '1'; - elsif (linki.linkdis = '0') and (r.xmit_fct_in = '1') and - ((linki.linkstart or (linki.autostart and recvo.gotnull)) = '1') then - v.state := S_Started; -- link enabled; start sending NULL - v_timerrst := '1'; - end if; - - when S_Started => - -- Wait for NULL. - if ((recvo.errdisc or recvo.errpar or recvo.erresc) = '1') or - ((recvo.gotfct or recvo.tick_out or recvo.rxchar) = '1') or - ((r.timercnt = 0) and r.timerdone = '1') then - v.state := S_ErrorReset; -- error, go back to reset - v_timerrst := '1'; - elsif recvo.gotnull = '1' then - v.state := S_Connecting; -- received null, continue - v_timerrst := '1'; - end if; - - when S_Connecting => - -- Wait for FCT. - if ((recvo.errdisc or recvo.errpar or recvo.erresc) = '1') or - ((recvo.tick_out or recvo.rxchar) = '1') or - ((r.timercnt = 0) and r.timerdone = '1') then - v.state := S_ErrorReset; -- error, go back to reset - v_timerrst := '1'; - elsif recvo.gotfct = '1' then - v.state := S_Run; -- got FCT, init completed - end if; - - when S_Run => - -- All is well. - if ((recvo.errdisc or recvo.errpar or recvo.erresc) = '1') or (r.errcred = '1') or - -- Spwerr can cause a disconnetion by forcing link disable - ((linki.linkdis or err_to_link.err_disc_o) = '1') then - v.state := S_ErrorReset; -- error, go back to reset - v_timerrst := '1'; - end if; - - end case; - - -- Update credit counters. - if r.state = S_ErrorReset then - - -- reset credit - v.tx_credit := to_unsigned(0, v.tx_credit'length); - v.rx_credit := to_unsigned(0, v.rx_credit'length); - - else - - -- update TX credit - if recvo.gotfct = '1' then - -- just received a FCT token - v.tx_credit := v.tx_credit + to_unsigned(8, v.tx_credit'length); - if r.tx_credit > 48 then - -- received too many FCT tokens - v.errcred := '1'; - end if; - end if; - -- Only decrements tx_credit without char sequence error injection - if (err_to_link.err_ch_seq_o = '0') then - if xmito.txack = '1' then - -- just sent one byte - v.tx_credit := v.tx_credit - to_unsigned(1, v.tx_credit'length); - end if; - end if; - - -- Only increments rx_credit without credit error injection - if (err_to_link.err_credit_o = '0') then - -- update RX credit after sending FCT - if xmito.fctack = '1' then - -- just sent a FCT token - v.rx_credit := v.rx_credit + to_unsigned(8, v.rx_credit'length); - end if; - end if; - - -- decide about sending FCT tokens - v.xmit_fct_in := bool_to_logic((v.rx_credit <= 48) and (v.rx_credit + to_unsigned(8, v.rx_credit'length) <= unsigned(linki.rxroom))); - - -- update RX credit after receiving character - if recvo.rxchar = '1' then - -- just received a character - v.rx_credit := v.rx_credit - to_unsigned(1, v.rx_credit'length); - if r.rx_credit = 0 then - -- remote transmitter violated its credit - v.errcred := '1'; - end if; - end if; - - end if; - - -- Update the initializaton reset timer. - if v_timerrst = '1' then - v.timercnt := to_unsigned(reset_time, v.timercnt'length); - v.timerdone := '0'; - else - if r.timercnt = 0 then - v.timercnt := to_unsigned(reset_time, v.timercnt'length); - v.timerdone := '1'; - else - v.timercnt := r.timercnt - 1; - end if; - end if; - - -- Reset - if rst = '1' then - v := regs_reset; - end if; - - -- Drive link level outputs. - linko.started <= bool_to_logic(r.state = S_Started); - linko.connecting <= bool_to_logic(r.state = S_Connecting); - linko.running <= bool_to_logic(r.state = S_Run); - linko.errdisc <= recvo.errdisc and bool_to_logic(r.state = S_Run); - linko.errpar <= recvo.errpar and bool_to_logic(r.state = S_Run); - linko.erresc <= recvo.erresc and bool_to_logic(r.state = S_Run); - linko.errcred <= r.errcred; - linko.txack <= xmito.txack; - linko.tick_out <= recvo.tick_out and bool_to_logic(r.state = S_Run); - linko.ctrl_out <= recvo.ctrl_out; - linko.time_out <= recvo.time_out; - linko.rxchar <= recvo.rxchar and bool_to_logic(r.state = S_Run); - linko.rxflag <= recvo.rxflag; - linko.rxdata <= recvo.rxdata; - - -- Drive receiver inputs. - rxen <= bool_to_logic(r.state /= S_ErrorReset); - - -- Drive transmitter input signals. - -- v_xmiti intercepts signals - v_xmiti.txen := bool_to_logic(r.state = S_Started or r.state = S_Connecting or r.state = S_Run); - v_xmiti.stnull := bool_to_logic(r.state = S_Started); - v_xmiti.stfct := bool_to_logic(r.state = S_Connecting); - v_xmiti.fct_in := r.xmit_fct_in; - v_xmiti.tick_in := linki.tick_in and bool_to_logic(r.state = S_Run); - v_xmiti.ctrl_in := linki.ctrl_in; - v_xmiti.time_in := linki.time_in; - v_xmiti.txwrite := linki.txwrite and bool_to_logic(r.tx_credit /= 0); - v_xmiti.txflag := linki.txflag; - v_xmiti.txdata := linki.txdata; - - -- Logic for parity, escape, charactere sequence and credit errors: update v_xmiti. - if ((err_to_link.err_par_o or err_to_link.err_esc_o) = '1') then - -- For parity and escape errors (treated directly by xmiti unity), send only null condition is a must. - v_xmiti.stnull := '1'; - elsif (err_to_link.err_credit_o = '1') then - -- Prepare conditions to send 8 x fct - -- No need to use counter or fsm, because err_credit_o pulse is long enough. - v_xmiti.tick_in := '0'; - v_xmiti.fct_in := '1'; - elsif (err_to_link.err_ch_seq_o = '1') then - -- Prepare conditions to send a N-char outside run state - v_xmiti.fct_in := '0'; - -- Send EOP outside run state - v_xmiti.txflag := '1'; - v_xmiti.txdata := "00000000"; - v_xmiti.txwrite := '1'; - end if; - - -- Write back to xmiti inputs. - -- If there is no error injection request, it is a simple bypass. - xmiti.txen <= v_xmiti.txen; - xmiti.stnull <= v_xmiti.stnull; - xmiti.stfct <= v_xmiti.stfct; - xmiti.fct_in <= v_xmiti.fct_in; - xmiti.tick_in <= v_xmiti.tick_in; - xmiti.ctrl_in <= v_xmiti.ctrl_in; - xmiti.time_in <= v_xmiti.time_in; - xmiti.txwrite <= v_xmiti.txwrite; - xmiti.txflag <= v_xmiti.txflag; - xmiti.txdata <= v_xmiti.txdata; - -- Parity, escape, char sequence, and credit error injection must also be treated directly by xmit unity - xmiti.err_inj_par <= err_to_link.err_par_o; - xmiti.err_inj_esc <= err_to_link.err_esc_o; - xmiti.err_inj_ch_seq <= err_to_link.err_ch_seq_o; - xmiti.err_inj_credit <= err_to_link.err_credit_o; - - -- Drive spwerr inputs. - link_to_err.run_state <= bool_to_logic(r.state = S_Run); - link_to_err.start_or_conn_state <= bool_to_logic(r.state = S_Started or r.state = S_Connecting); - - -- Update registers. - rin <= v; - end process; - - -- Update registers. - process(clk) is - begin - if rising_edge(clk) then - r <= rin; - end if; - end process; + -- Instantiate error controller. + err_inst : spwerr + port map( + clk => clk, + rst => rst, + err_link_i => link_to_err, + err_link_o => err_to_link, + err_usr_i => linki.err_usr_i, + err_usr_o => linko.err_usr_o + ); + + -- Combinatorial process + process(r, rst, linki, recvo, xmito, err_to_link) is + variable v : regs_type; + variable v_timerrst : std_logic; + variable v_xmiti : spw_xmit_in_type; + begin + v := r; + v_timerrst := '0'; + + -- State machine. + case r.state is + + when S_ErrorReset => + -- Wait for timer. + if r.timercnt = 0 then + v.state := S_ErrorWait; + v_timerrst := '1'; + end if; + v.errcred := '0'; + v.xmit_fct_in := '0'; + + when S_ErrorWait => + -- Wait for 2 timer periods. + if ((recvo.errdisc or recvo.errpar or recvo.erresc) = '1') or ((recvo.gotfct or recvo.tick_out or recvo.rxchar) = '1') then + -- Note: spwrecv will never issue errpar, erresc, gotfct, + -- tick_out or rxchar before the first NULL has been seen. + -- Therefore it's ok here to bail on those conditions + -- without explicitly testing got_null. + v.state := S_ErrorReset; -- error, go back to reset + v_timerrst := '1'; + elsif r.timercnt = 0 then + if r.timerdone = '1' then + v.state := S_Ready; + v_timerrst := '1'; + end if; + end if; + + when S_Ready => + -- Wait for link start. + if ((recvo.errdisc or recvo.errpar or recvo.erresc) = '1') or ((recvo.gotfct or recvo.tick_out or recvo.rxchar) = '1') then + v.state := S_ErrorReset; -- error, go back to reset + v_timerrst := '1'; + elsif (linki.linkdis = '0') and (r.xmit_fct_in = '1') and ((linki.linkstart or (linki.autostart and recvo.gotnull)) = '1') then + v.state := S_Started; -- link enabled; start sending NULL + v_timerrst := '1'; + end if; + + when S_Started => + -- Wait for NULL. + if ((recvo.errdisc or recvo.errpar or recvo.erresc) = '1') or ((recvo.gotfct or recvo.tick_out or recvo.rxchar) = '1') or ((r.timercnt = 0) and r.timerdone = '1') then + v.state := S_ErrorReset; -- error, go back to reset + v_timerrst := '1'; + elsif recvo.gotnull = '1' then + v.state := S_Connecting; -- received null, continue + v_timerrst := '1'; + end if; + + when S_Connecting => + -- Wait for FCT. + if ((recvo.errdisc or recvo.errpar or recvo.erresc) = '1') or ((recvo.tick_out or recvo.rxchar) = '1') or ((r.timercnt = 0) and r.timerdone = '1') then + v.state := S_ErrorReset; -- error, go back to reset + v_timerrst := '1'; + elsif recvo.gotfct = '1' then + v.state := S_Run; -- got FCT, init completed + end if; + + when S_Run => + -- All is well. + if ((recvo.errdisc or recvo.errpar or recvo.erresc) = '1') or (r.errcred = '1') or -- Spwerr can cause a disconnetion by forcing link disable + ((linki.linkdis or err_to_link.err_disc_o) = '1') then + v.state := S_ErrorReset; -- error, go back to reset + v_timerrst := '1'; + end if; + + when others => + v.state := S_ErrorReset; -- recover from invalid state + v_timerrst := '1'; + + end case; + + -- Update credit counters. + if r.state = S_ErrorReset then + + -- reset credit + v.tx_credit := to_unsigned(0, v.tx_credit'length); + v.rx_credit := to_unsigned(0, v.rx_credit'length); + + else + + -- update TX credit + if recvo.gotfct = '1' then + -- just received a FCT token + v.tx_credit := v.tx_credit + to_unsigned(8, v.tx_credit'length); + if r.tx_credit > 48 then + -- received too many FCT tokens + v.errcred := '1'; + end if; + end if; + -- Only decrements tx_credit without char sequence error injection + if (err_to_link.err_ch_seq_o = '0') then + if xmito.txack = '1' then + -- just sent one byte + v.tx_credit := v.tx_credit - to_unsigned(1, v.tx_credit'length); + end if; + end if; + + -- Only increments rx_credit without credit error injection + if (err_to_link.err_credit_o = '0') then + -- update RX credit after sending FCT + if xmito.fctack = '1' then + -- just sent a FCT token + v.rx_credit := v.rx_credit + to_unsigned(8, v.rx_credit'length); + end if; + end if; + + -- decide about sending FCT tokens + v.xmit_fct_in := bool_to_logic((v.rx_credit <= 48) and (v.rx_credit + to_unsigned(8, v.rx_credit'length) <= unsigned(linki.rxroom))); + + -- update RX credit after receiving character + if recvo.rxchar = '1' then + -- just received a character + v.rx_credit := v.rx_credit - to_unsigned(1, v.rx_credit'length); + if r.rx_credit = 0 then + -- remote transmitter violated its credit + v.errcred := '1'; + end if; + end if; + + end if; + + -- Update the initializaton reset timer. + if v_timerrst = '1' then + v.timercnt := to_unsigned(reset_time, v.timercnt'length); + v.timerdone := '0'; + else + if r.timercnt = 0 then + v.timercnt := to_unsigned(reset_time, v.timercnt'length); + v.timerdone := '1'; + else + v.timercnt := r.timercnt - 1; + end if; + end if; + + -- Reset + if rst = '1' then + v := regs_reset; + end if; + + -- Drive link level outputs. + linko.started <= bool_to_logic(r.state = S_Started); + linko.connecting <= bool_to_logic(r.state = S_Connecting); + linko.running <= bool_to_logic(r.state = S_Run); + linko.errdisc <= recvo.errdisc and bool_to_logic(r.state = S_Run); + linko.errpar <= recvo.errpar and bool_to_logic(r.state = S_Run); + linko.erresc <= recvo.erresc and bool_to_logic(r.state = S_Run); + linko.errcred <= r.errcred; + linko.txack <= xmito.txack; + linko.tick_out <= recvo.tick_out and bool_to_logic(r.state = S_Run); + linko.ctrl_out <= recvo.ctrl_out; + linko.time_out <= recvo.time_out; + linko.rxchar <= recvo.rxchar and bool_to_logic(r.state = S_Run); + linko.rxflag <= recvo.rxflag; + linko.rxdata <= recvo.rxdata; + + -- Drive receiver inputs. + rxen <= bool_to_logic(r.state /= S_ErrorReset); + + -- Drive transmitter input signals. + -- v_xmiti intercepts signals + v_xmiti.txen := bool_to_logic(r.state = S_Started or r.state = S_Connecting or r.state = S_Run); + v_xmiti.stnull := bool_to_logic(r.state = S_Started); + v_xmiti.stfct := bool_to_logic(r.state = S_Connecting); + v_xmiti.fct_in := r.xmit_fct_in; + v_xmiti.tick_in := linki.tick_in and bool_to_logic(r.state = S_Run); + v_xmiti.ctrl_in := linki.ctrl_in; + v_xmiti.time_in := linki.time_in; + v_xmiti.txwrite := linki.txwrite and bool_to_logic(r.tx_credit /= 0); + v_xmiti.txflag := linki.txflag; + v_xmiti.txdata := linki.txdata; + + -- Logic for parity, escape, charactere sequence and credit errors: update v_xmiti. + if ((err_to_link.err_par_o or err_to_link.err_esc_o) = '1') then + -- For parity and escape errors (treated directly by xmiti unity), send only null condition is a must. + v_xmiti.stnull := '1'; + elsif (err_to_link.err_credit_o = '1') then + -- Prepare conditions to send 8 x fct + -- No need to use counter or fsm, because err_credit_o pulse is long enough. + v_xmiti.tick_in := '0'; + v_xmiti.fct_in := '1'; + elsif (err_to_link.err_ch_seq_o = '1') then + -- Prepare conditions to send a N-char outside run state + v_xmiti.fct_in := '0'; + -- Send EOP outside run state + v_xmiti.txflag := '1'; + v_xmiti.txdata := "00000000"; + v_xmiti.txwrite := '1'; + end if; + + -- Write back to xmiti inputs. + -- If there is no error injection request, it is a simple bypass. + xmiti.txen <= v_xmiti.txen; + xmiti.stnull <= v_xmiti.stnull; + xmiti.stfct <= v_xmiti.stfct; + xmiti.fct_in <= v_xmiti.fct_in; + xmiti.tick_in <= v_xmiti.tick_in; + xmiti.ctrl_in <= v_xmiti.ctrl_in; + xmiti.time_in <= v_xmiti.time_in; + xmiti.txwrite <= v_xmiti.txwrite; + xmiti.txflag <= v_xmiti.txflag; + xmiti.txdata <= v_xmiti.txdata; + -- Parity, escape, char sequence, and credit error injection must also be treated directly by xmit unity + xmiti.err_inj_par <= err_to_link.err_par_o; + xmiti.err_inj_esc <= err_to_link.err_esc_o; + xmiti.err_inj_ch_seq <= err_to_link.err_ch_seq_o; + xmiti.err_inj_credit <= err_to_link.err_credit_o; + + -- Drive spwerr inputs. + link_to_err.run_state <= bool_to_logic(r.state = S_Run); + link_to_err.start_or_conn_state <= bool_to_logic(r.state = S_Started or r.state = S_Connecting); + + -- Update registers. + rin <= v; + end process; + + -- Update registers. + process(clk) is + begin + if rising_edge(clk) then + r <= rin; + end if; + end process; end architecture spwlink_arch; diff --git a/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwpkg.vhd b/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwpkg.vhd index b4fe8ffdc..6c2ad076f 100644 --- a/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwpkg.vhd +++ b/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwpkg.vhd @@ -7,454 +7,456 @@ use ieee.std_logic_1164.all; package spwpkg is - -- Indicates a platform-specific implementation. - type spw_implementation_type is (impl_generic, impl_fast); + -- Indicates a platform-specific implementation. + type spw_implementation_type is (impl_generic, impl_fast); - -- Enumerated type for spwerr error selection values - -- Obs.: esc_eop, esc_eep: future implementation - type t_spw_err_sel is (disconnection, parity, esc_eop, esc_eep, esc_esc, credit, ch_seq, reserved); + -- Enumerated type for spwerr error selection values + -- Obs.: esc_eop, esc_eep: future implementation + type t_spw_err_sel is (disconnection, parity, esc_eop, esc_eep, esc_esc, credit, ch_seq, reserved); - -- Enumerated type for spwerr error status values - type t_spw_err_stat is (stby, accepted, invalid, inconsistent, ended_ok, reserved); + -- Enumerated type for spwerr error status values + type t_spw_err_stat is (stby, accepted, invalid, inconsistent, ended_ok, reserved); - -- Input signals from toplevel to spwerr. - type spwerr_from_usr_type is record + -- Input signals from toplevel to spwerr. + type spwerr_from_usr_type is record - err_inj_i : std_logic; - err_sel_i : t_spw_err_sel; - end record; + err_inj_i : std_logic; + err_sel_i : t_spw_err_sel; + end record; - -- Output signals from spwerr to toplevel - type spwerr_to_usr_type is record + -- Output signals from spwerr to toplevel + type spwerr_to_usr_type is record - err_stat_o : t_spw_err_stat; - end record; + err_stat_o : t_spw_err_stat; + end record; - -- Input signals from spwlink to spwerr. - type spwerr_from_link_type is record + -- Input signals from spwlink to spwerr. + type spwerr_from_link_type is record - run_state : std_logic; - start_or_conn_state: std_logic; - end record; + run_state : std_logic; + start_or_conn_state : std_logic; + end record; - -- Output signals from spwerr to spwlink - type spwerr_to_link_type is record + -- Output signals from spwerr to spwlink + type spwerr_to_link_type is record - err_disc_o : std_logic; - err_par_o : std_logic; - err_esc_o : std_logic; - err_credit_o : std_logic; - err_ch_seq_o : std_logic; - end record; + err_disc_o : std_logic; + err_par_o : std_logic; + err_esc_o : std_logic; + err_credit_o : std_logic; + err_ch_seq_o : std_logic; + end record; - -- Input signals to spwlink. - type spw_link_in_type is record + -- Input signals to spwlink. + type spw_link_in_type is record - -- Enables automatic link start on receipt of a NULL character. - autostart : std_logic; + -- Enables automatic link start on receipt of a NULL character. + autostart : std_logic; - -- Enables link start once the Ready state is reached. - -- Without either "autostart" or "linkstart", the link remains in - -- state Ready. - linkstart : std_logic; + -- Enables link start once the Ready state is reached. + -- Without either "autostart" or "linkstart", the link remains in + -- state Ready. + linkstart : std_logic; - -- Do not start link (overrides "linkstart" and "autostart") and/or - -- disconnect the currently running link. - linkdis : std_logic; + -- Do not start link (overrides "linkstart" and "autostart") and/or + -- disconnect the currently running link. + linkdis : std_logic; - -- Number of bytes available in the receive buffer. Used to for - -- flow-control operation. At least 8 bytes must be available - -- initially, otherwise the link can not start. Values larger than 63 - -- are irrelevant and may be presented as 63. The available room may - -- decrease by one byte due to the reception of an N-Char; in that case - -- the "rxroom" signal must be updated on the clock following the clock - -- on which "rxchar" is high. Under no other circumstances may "rxroom" - -- be decreased. - rxroom : std_logic_vector(5 downto 0); + -- Number of bytes available in the receive buffer. Used to for + -- flow-control operation. At least 8 bytes must be available + -- initially, otherwise the link can not start. Values larger than 63 + -- are irrelevant and may be presented as 63. The available room may + -- decrease by one byte due to the reception of an N-Char; in that case + -- the "rxroom" signal must be updated on the clock following the clock + -- on which "rxchar" is high. Under no other circumstances may "rxroom" + -- be decreased. + rxroom : std_logic_vector(5 downto 0); - -- High for one clock cycle to request transmission of a TimeCode. - -- The request is registered inside spwxmit until it can be processed. - tick_in : std_logic; + -- High for one clock cycle to request transmission of a TimeCode. + -- The request is registered inside spwxmit until it can be processed. + tick_in : std_logic; - -- Control bits of the TimeCode to be sent. - -- Must be valid while tick_in is high. - ctrl_in : std_logic_vector(1 downto 0); + -- Control bits of the TimeCode to be sent. + -- Must be valid while tick_in is high. + ctrl_in : std_logic_vector(1 downto 0); - -- Counter value of the TimeCode to be sent. - -- Must be valid while tick_in is high. - time_in : std_logic_vector(5 downto 0); + -- Counter value of the TimeCode to be sent. + -- Must be valid while tick_in is high. + time_in : std_logic_vector(5 downto 0); - -- Requests transmission of an N-Char. - -- Keep this signal high until confirmed by "txack". - txwrite : std_logic; + -- Requests transmission of an N-Char. + -- Keep this signal high until confirmed by "txack". + txwrite : std_logic; - -- Control flag to be sent with the next N-Char. - -- Must be valid while "txwrite" is high. - txflag : std_logic; + -- Control flag to be sent with the next N-Char. + -- Must be valid while "txwrite" is high. + txflag : std_logic; - -- Byte to be sent, or "00000000" for EOP or "00000001" for EEP. - -- Must be valid while "txwrite" is high. - txdata : std_logic_vector(7 downto 0); + -- Byte to be sent, or "00000000" for EOP or "00000001" for EEP. + -- Must be valid while "txwrite" is high. + txdata : std_logic_vector(7 downto 0); - -- Spwerr interface in - toplevel - err_usr_i : spwerr_from_usr_type; - end record; + -- Spwerr interface in - toplevel + err_usr_i : spwerr_from_usr_type; + end record; - -- Output signals from spwlink. - type spw_link_out_type is record + -- Output signals from spwlink. + type spw_link_out_type is record - -- High if the link state machine is currently in state Started. - started : std_logic; + -- High if the link state machine is currently in state Started. + started : std_logic; - -- High if the link state machine is currently in state Connecting. - connecting : std_logic; + -- High if the link state machine is currently in state Connecting. + connecting : std_logic; - -- High if the link state machine is currently in state Run. - running : std_logic; + -- High if the link state machine is currently in state Run. + running : std_logic; - -- Disconnect detected in state Run. Triggers a reset and reconnect. - -- This indication is auto-clearing. - errdisc : std_logic; + -- Disconnect detected in state Run. Triggers a reset and reconnect. + -- This indication is auto-clearing. + errdisc : std_logic; - -- Parity error detected in state Run. Triggers a reset and reconnect. - -- This indication is auto-clearing. - errpar : std_logic; + -- Parity error detected in state Run. Triggers a reset and reconnect. + -- This indication is auto-clearing. + errpar : std_logic; - -- Invalid escape sequence detected in state Run. - -- Triggers a reset and reconnect; auto-clearing. - erresc : std_logic; + -- Invalid escape sequence detected in state Run. + -- Triggers a reset and reconnect; auto-clearing. + erresc : std_logic; - -- Credit error detected. Triggers a reset and reconnect. - -- This indication is auto-clearing. - errcred : std_logic; + -- Credit error detected. Triggers a reset and reconnect. + -- This indication is auto-clearing. + errcred : std_logic; - -- High to confirm the transmission of an N-Char. - -- This is a Wishbone-style handshake signal. It has a combinatorial - -- dependency on "txwrite". - txack : std_logic; + -- High to confirm the transmission of an N-Char. + -- This is a Wishbone-style handshake signal. It has a combinatorial + -- dependency on "txwrite". + txack : std_logic; - -- High for one clock cycle if a TimeCode was just received. - -- Verification of the TimeCode as described in 8.12.2 of ECSS-E-50 - -- is not implemented; all received timecodes are reported. - tick_out : std_logic; + -- High for one clock cycle if a TimeCode was just received. + -- Verification of the TimeCode as described in 8.12.2 of ECSS-E-50 + -- is not implemented; all received timecodes are reported. + tick_out : std_logic; - -- Control bits of last received TimeCode. - ctrl_out : std_logic_vector(1 downto 0); + -- Control bits of last received TimeCode. + ctrl_out : std_logic_vector(1 downto 0); - -- Counter value of last received TimeCode. - time_out : std_logic_vector(5 downto 0); + -- Counter value of last received TimeCode. + time_out : std_logic_vector(5 downto 0); - -- High for one clock cycle if an N-Char (data byte or EOP or EEP) was - -- just received. The data bits must be accepted immediately from - -- "rxflag" and "rxdata". - rxchar : std_logic; + -- High for one clock cycle if an N-Char (data byte or EOP or EEP) was + -- just received. The data bits must be accepted immediately from + -- "rxflag" and "rxdata". + rxchar : std_logic; - -- High if the received character is EOP or EEP, low if it is a data - -- byte. Valid when "rxchar" is high. - rxflag : std_logic; + -- High if the received character is EOP or EEP, low if it is a data + -- byte. Valid when "rxchar" is high. + rxflag : std_logic; - -- Received byte, or "00000000" for EOP or "00000001" for EEP. - -- Valid when "rxchar" is high. - rxdata : std_logic_vector(7 downto 0); + -- Received byte, or "00000000" for EOP or "00000001" for EEP. + -- Valid when "rxchar" is high. + rxdata : std_logic_vector(7 downto 0); - -- Spwerr interface out - toplevel - err_usr_o : spwerr_to_usr_type; - end record; + -- Spwerr interface out - toplevel + err_usr_o : spwerr_to_usr_type; + end record; - -- Output signals from spwrecv to spwlink. - type spw_recv_out_type is record + -- Output signals from spwrecv to spwlink. + type spw_recv_out_type is record - -- High if at least one signal change was seen since enable. - -- Resets to low when rxen is low. - gotbit : std_logic; + -- High if at least one signal change was seen since enable. + -- Resets to low when rxen is low. + gotbit : std_logic; - -- High if at least one valid NULL pattern was detected since enable. - -- Resets to low when rxen is low. - gotnull : std_logic; + -- High if at least one valid NULL pattern was detected since enable. + -- Resets to low when rxen is low. + gotnull : std_logic; - -- High for one clock cycle if an FCT token was just received. - gotfct : std_logic; + -- High for one clock cycle if an FCT token was just received. + gotfct : std_logic; - -- High for one clock cycle if a TimeCode was just received. - tick_out : std_logic; + -- High for one clock cycle if a TimeCode was just received. + tick_out : std_logic; - -- Control bits of last received TimeCode. - ctrl_out : std_logic_vector(1 downto 0); + -- Control bits of last received TimeCode. + ctrl_out : std_logic_vector(1 downto 0); - -- Counter value of last received TimeCode. - time_out : std_logic_vector(5 downto 0); + -- Counter value of last received TimeCode. + time_out : std_logic_vector(5 downto 0); - -- High for one clock cycle if an N-Char (data byte or EOP/EEP) was just received. - rxchar : std_logic; + -- High for one clock cycle if an N-Char (data byte or EOP/EEP) was just received. + rxchar : std_logic; - -- High if rxchar is high and the received character is EOP or EEP. - -- Low if rxchar is high and the received character is a data byte. - rxflag : std_logic; - - -- Received byte, or "00000000" for EOP or "00000001" for EEP. - -- Valid when "rxchar" is high. - rxdata : std_logic_vector(7 downto 0); - - -- Disconnect detected (after a signal change was seen). - -- Resets to low when rxen is low or when a signal change is seen. - errdisc : std_logic; - - -- Parity error detected (after a valid NULL pattern was seen). - -- Sticky; resets to low when rxen is low. - errpar : std_logic; - - -- Escape sequence error detected (after a valid NULL pattern was seen). - -- Sticky; resets to low when rxen is low. - erresc : std_logic; - end record; - - -- Input signals to spwxmit from spwlink. - type spw_xmit_in_type is record - - -- High to enable transmitter; low to disable and reset transmitter. - txen : std_logic; - - -- Indicates that only NULL characters may be transmitted. - stnull : std_logic; - - -- Indicates that only NULL and/or FCT characters may be transmitted. - stfct : std_logic; - - -- Requests transmission of an FCT character. - -- Keep this signal high until confirmed by "fctack". - fct_in : std_logic; - - -- High for one clock cycle to request transmission of a TimeCode. - -- The request is registered inside spwxmit until it can be processed. - tick_in : std_logic; - - -- Control bits of the TimeCode to be sent. - -- Must be valid while "tick_in" is high. - ctrl_in : std_logic_vector(1 downto 0); - - -- Counter value of the TimeCode to be sent. - -- Must be valid while "tick_in" is high. - time_in : std_logic_vector(5 downto 0); - - -- Request transmission of an N-Char. - -- Keep this signal high until confirmed by "txack". - txwrite : std_logic; - - -- Control flag to be sent with the next N-Char. - -- Must be valid while "txwrite" is high. - txflag : std_logic; - - -- Byte to send, or "00000000" for EOP or "00000001" for EEP. - -- Must be valid while "txwrite" is high. - txdata : std_logic_vector(7 downto 0); - - -- Parity error injection control bit (from spwerr: internal to link) - err_inj_par: std_logic; - - -- Escape error injection control bit (from spwerr: internal to link) - err_inj_esc: std_logic; - - -- Char sequence error injection control bit (from spwerr: internal to link) - err_inj_ch_seq: std_logic; - - -- Credit error injection control bit (from spwerr: internal to link) - err_inj_credit: std_logic; - - end record; - - -- Output signals from spwxmit to spwlink. - type spw_xmit_out_type is record - - -- High to confirm transmission on an FCT character. - -- This is a Wishbone-style handshaking signal; it is combinatorially - -- dependent on "fct_in". - fctack : std_logic; - - -- High to confirm transmission of an N-Char. - -- This is a Wishbone-style handshaking signal; it is combinatorially - -- dependent on both "fct_in" and "txwrite". - txack : std_logic; - end record; - - -- Character-stream interface - component spwstream is - generic( - sysfreq : real; -- clk freq in Hz - txclkfreq : real := 0.0; -- txclk freq in Hz - rximpl : spw_implementation_type := impl_generic; - rxchunk : integer range 1 to 4 := 1; -- max bits per clk - tximpl : spw_implementation_type := impl_generic; - rxfifosize_bits : integer range 6 to 14 := 11; -- rx fifo size - txfifosize_bits : integer range 2 to 14 := 11 -- tx fifo size - ); - port( - clk : in std_logic; -- system clock - rxclk : in std_logic; -- receiver sample clock - txclk : in std_logic; -- transmit clock - rst : in std_logic; -- synchronous reset - autostart : in std_logic; -- automatic link start - linkstart : in std_logic; -- forced link start - linkdis : in std_logic; -- stop link - txdivcnt : in std_logic_vector(7 downto 0); -- tx scale factor - tick_in : in std_logic; -- request timecode xmit - ctrl_in : in std_logic_vector(1 downto 0); - time_in : in std_logic_vector(5 downto 0); - txwrite : in std_logic; -- request character xmit - txflag : in std_logic; -- control flag of tx char - txdata : in std_logic_vector(7 downto 0); - txrdy : out std_logic; -- room in tx fifo - txhalff : out std_logic; -- tx fifo half full - tick_out : out std_logic; -- timecode received - ctrl_out : out std_logic_vector(1 downto 0); - time_out : out std_logic_vector(5 downto 0); - rxvalid : out std_logic; -- rx fifo not empty - rxhalff : out std_logic; -- rx fifo half full - rxflag : out std_logic; -- control flag of rx char - rxdata : out std_logic_vector(7 downto 0); - rxread : in std_logic; -- accept rx character - started : out std_logic; -- link in Started state - connecting : out std_logic; -- link in Connecting state - running : out std_logic; -- link in Run state - errdisc : out std_logic; -- disconnect error - errpar : out std_logic; -- parity error - erresc : out std_logic; -- escape error - errcred : out std_logic; -- credit error - spw_di : in std_logic; - spw_si : in std_logic; - spw_do : out std_logic; - spw_so : out std_logic; - -- spwerr user interface - err_inj_i : in std_logic; - err_sel_i : in t_spw_err_sel; - err_stat_o : out t_spw_err_stat - ); - end component spwstream; - - -- Link Level Interface - component spwlink is - generic( - reset_time : integer -- reset time in clocks (6.4 us) - ); - port( - clk : in std_logic; -- system clock - rst : in std_logic; -- synchronous reset (active-high) - linki : in spw_link_in_type; - linko : out spw_link_out_type; - rxen : out std_logic; - recvo : in spw_recv_out_type; - xmiti : out spw_xmit_in_type; - xmito : in spw_xmit_out_type - ); - end component spwlink; - - -- Receiver - component spwrecv is - generic( - disconnect_time : integer range 1 to 255; -- disconnect period in system clock cycles - rxchunk : integer range 1 to 4 -- nr of bits per system clock - ); - port( - clk : in std_logic; -- system clock - rxen : in std_logic; -- receiver enabled - recvo : out spw_recv_out_type; - inact : in std_logic; - inbvalid : in std_logic; - inbits : in std_logic_vector(rxchunk - 1 downto 0) - ); - end component spwrecv; - - -- Transmitter (generic implementation) - component spwxmit is - port( - clk : in std_logic; -- system clock - rst : in std_logic; -- synchronous reset (active-high) - divcnt : in std_logic_vector(7 downto 0); - xmiti : in spw_xmit_in_type; - xmito : out spw_xmit_out_type; - spw_do : out std_logic; -- tx data to SPW bus - spw_so : out std_logic -- tx strobe to SPW bus - ); - end component spwxmit; - - -- Transmitter (separate tx clock domain) - component spwxmit_fast is - port( - clk : in std_logic; -- system clock - txclk : in std_logic; -- transmit clock - rst : in std_logic; -- synchronous reset (active-high) - divcnt : in std_logic_vector(7 downto 0); - xmiti : in spw_xmit_in_type; - xmito : out spw_xmit_out_type; - spw_do : out std_logic; -- tx data to SPW bus - spw_so : out std_logic -- tx strobe to SPW bus - ); - end component spwxmit_fast; - - -- Front-end for SpaceWire Receiver (generic implementation) - component spwrecvfront_generic is - port( - clk : in std_logic; -- system clock - rxen : in std_logic; -- high to enable receiver - inact : out std_logic; -- high if activity on input - inbvalid : out std_logic; -- high if inbits contains a valid received bit - inbits : out std_logic_vector(0 downto 0); -- received bit - spw_di : in std_logic; -- Data In signal from SpaceWire bus - spw_si : in std_logic -- Strobe In signal from SpaceWire bus - ); - end component spwrecvfront_generic; - - -- Front-end for SpaceWire Receiver (separate rx clock domain) - component spwrecvfront_fast is - generic( - rxchunk : integer range 1 to 4 -- max number of bits per system clock - ); - port( - clk : in std_logic; -- system clock - rxclk : in std_logic; -- sample clock (DDR) - rxen : in std_logic; -- high to enable receiver - inact : out std_logic; -- high if activity on input - inbvalid : out std_logic; -- high if inbits contains a valid group of received bits - inbits : out std_logic_vector(rxchunk - 1 downto 0); -- received bits - spw_di : in std_logic; -- Data In signal from SpaceWire bus - spw_si : in std_logic -- Strobe In signal from SpaceWire bus - ); - end component spwrecvfront_fast; - - -- Synchronous two-port memory. - component spwram is - generic( - abits : integer; - dbits : integer); - port( - rclk : in std_logic; - wclk : in std_logic; - ren : in std_logic; - raddr : in std_logic_vector(abits - 1 downto 0); - rdata : out std_logic_vector(dbits - 1 downto 0); - wen : in std_logic; - waddr : in std_logic_vector(abits - 1 downto 0); - wdata : in std_logic_vector(dbits - 1 downto 0)); - end component spwram; - - -- Double flip-flop synchronizer. - component syncdff is - port( - clk : in std_logic; -- clock (destination domain) - rst : in std_logic; -- asynchronous reset, active-high - di : in std_logic; -- input data - do : out std_logic); -- output data - end component syncdff; - - -- Spwerr Interface - component spwerr is - port( - clk : in std_logic; -- system clock - rst : in std_logic; -- asynchronous reset (active-high) - err_link_i : in spwerr_from_link_type; - err_link_o : out spwerr_to_link_type; - err_usr_i : in spwerr_from_usr_type; - err_usr_o : out spwerr_to_usr_type - ); - end component spwerr; + -- High if rxchar is high and the received character is EOP or EEP. + -- Low if rxchar is high and the received character is a data byte. + rxflag : std_logic; + + -- Received byte, or "00000000" for EOP or "00000001" for EEP. + -- Valid when "rxchar" is high. + rxdata : std_logic_vector(7 downto 0); + + -- Disconnect detected (after a signal change was seen). + -- Resets to low when rxen is low or when a signal change is seen. + errdisc : std_logic; + + -- Parity error detected (after a valid NULL pattern was seen). + -- Sticky; resets to low when rxen is low. + errpar : std_logic; + + -- Escape sequence error detected (after a valid NULL pattern was seen). + -- Sticky; resets to low when rxen is low. + erresc : std_logic; + end record; + + -- Input signals to spwxmit from spwlink. + type spw_xmit_in_type is record + + -- High to enable transmitter; low to disable and reset transmitter. + txen : std_logic; + + -- Indicates that only NULL characters may be transmitted. + stnull : std_logic; + + -- Indicates that only NULL and/or FCT characters may be transmitted. + stfct : std_logic; + + -- Requests transmission of an FCT character. + -- Keep this signal high until confirmed by "fctack". + fct_in : std_logic; + + -- High for one clock cycle to request transmission of a TimeCode. + -- The request is registered inside spwxmit until it can be processed. + tick_in : std_logic; + + -- Control bits of the TimeCode to be sent. + -- Must be valid while "tick_in" is high. + ctrl_in : std_logic_vector(1 downto 0); + + -- Counter value of the TimeCode to be sent. + -- Must be valid while "tick_in" is high. + time_in : std_logic_vector(5 downto 0); + + -- Request transmission of an N-Char. + -- Keep this signal high until confirmed by "txack". + txwrite : std_logic; + + -- Control flag to be sent with the next N-Char. + -- Must be valid while "txwrite" is high. + txflag : std_logic; + + -- Byte to send, or "00000000" for EOP or "00000001" for EEP. + -- Must be valid while "txwrite" is high. + txdata : std_logic_vector(7 downto 0); + + -- Parity error injection control bit (from spwerr: internal to link) + err_inj_par : std_logic; + + -- Escape error injection control bit (from spwerr: internal to link) + err_inj_esc : std_logic; + + -- Char sequence error injection control bit (from spwerr: internal to link) + err_inj_ch_seq : std_logic; + + -- Credit error injection control bit (from spwerr: internal to link) + err_inj_credit : std_logic; + + end record; + + -- Output signals from spwxmit to spwlink. + type spw_xmit_out_type is record + + -- High to confirm transmission on an FCT character. + -- This is a Wishbone-style handshaking signal; it is combinatorially + -- dependent on "fct_in". + fctack : std_logic; + + -- High to confirm transmission of an N-Char. + -- This is a Wishbone-style handshaking signal; it is combinatorially + -- dependent on both "fct_in" and "txwrite". + txack : std_logic; + end record; + + -- Character-stream interface + component spwstream is + generic( + sysfreq : real; -- clk freq in Hz + txclkfreq : real := 0.0; -- txclk freq in Hz + rximpl : spw_implementation_type := impl_generic; + rxchunk : integer range 1 to 4 := 1; -- max bits per clk + tximpl : spw_implementation_type := impl_generic; + rxfifosize_bits : integer range 6 to 14 := 11; -- rx fifo size + txfifosize_bits : integer range 2 to 14 := 11 -- tx fifo size + ); + port( + clk : in std_logic; -- system clock + rxclk : in std_logic; -- receiver sample clock + txclk : in std_logic; -- transmit clock + rst : in std_logic; -- synchronous reset + autostart : in std_logic; -- automatic link start + linkstart : in std_logic; -- forced link start + linkdis : in std_logic; -- stop link + txdivcnt : in std_logic_vector(7 downto 0); -- tx scale factor + tick_in : in std_logic; -- request timecode xmit + ctrl_in : in std_logic_vector(1 downto 0); + time_in : in std_logic_vector(5 downto 0); + txwrite : in std_logic; -- request character xmit + txflag : in std_logic; -- control flag of tx char + txdata : in std_logic_vector(7 downto 0); + txrdy : out std_logic; -- room in tx fifo + txhalff : out std_logic; -- tx fifo half full + tick_out : out std_logic; -- timecode received + ctrl_out : out std_logic_vector(1 downto 0); + time_out : out std_logic_vector(5 downto 0); + rxvalid : out std_logic; -- rx fifo not empty + rxhalff : out std_logic; -- rx fifo half full + rxflag : out std_logic; -- control flag of rx char + rxdata : out std_logic_vector(7 downto 0); + rxread : in std_logic; -- accept rx character + started : out std_logic; -- link in Started state + connecting : out std_logic; -- link in Connecting state + running : out std_logic; -- link in Run state + errdisc : out std_logic; -- disconnect error + errpar : out std_logic; -- parity error + erresc : out std_logic; -- escape error + errcred : out std_logic; -- credit error + spw_di : in std_logic; + spw_si : in std_logic; + spw_do : out std_logic; + spw_so : out std_logic; + -- spwerr user interface + err_inj_i : in std_logic; + err_sel_i : in t_spw_err_sel; + err_stat_o : out t_spw_err_stat + ); + end component spwstream; + + -- Link Level Interface + component spwlink is + generic( + reset_time : integer -- reset time in clocks (6.4 us) + ); + port( + clk : in std_logic; -- system clock + rst : in std_logic; -- synchronous reset (active-high) + linki : in spw_link_in_type; + linko : out spw_link_out_type; + rxen : out std_logic; + recvo : in spw_recv_out_type; + xmiti : out spw_xmit_in_type; + xmito : in spw_xmit_out_type + ); + end component spwlink; + + -- Receiver + component spwrecv is + generic( + disconnect_time : integer range 1 to 255; -- disconnect period in system clock cycles + rxchunk : integer range 1 to 4 -- nr of bits per system clock + ); + port( + clk : in std_logic; -- system clock + rxen : in std_logic; -- receiver enabled + recvo : out spw_recv_out_type; + inact : in std_logic; + inbvalid : in std_logic; + inbits : in std_logic_vector(rxchunk - 1 downto 0); + invalid_transition : in std_logic -- high if invalid transition detected + ); + end component spwrecv; + + -- Transmitter (generic implementation) + component spwxmit is + port( + clk : in std_logic; -- system clock + rst : in std_logic; -- synchronous reset (active-high) + divcnt : in std_logic_vector(7 downto 0); + xmiti : in spw_xmit_in_type; + xmito : out spw_xmit_out_type; + spw_do : out std_logic; -- tx data to SPW bus + spw_so : out std_logic -- tx strobe to SPW bus + ); + end component spwxmit; + + -- Transmitter (separate tx clock domain) + component spwxmit_fast is + port( + clk : in std_logic; -- system clock + txclk : in std_logic; -- transmit clock + rst : in std_logic; -- synchronous reset (active-high) + divcnt : in std_logic_vector(7 downto 0); + xmiti : in spw_xmit_in_type; + xmito : out spw_xmit_out_type; + spw_do : out std_logic; -- tx data to SPW bus + spw_so : out std_logic -- tx strobe to SPW bus + ); + end component spwxmit_fast; + + -- Front-end for SpaceWire Receiver (generic implementation) + component spwrecvfront_generic is + port( + clk : in std_logic; -- system clock + rxen : in std_logic; -- high to enable receiver + inact : out std_logic; -- high if activity on input + inbvalid : out std_logic; -- high if inbits contains a valid received bit + inbits : out std_logic_vector(0 downto 0); -- received bit + invalid_transition : out std_logic; -- high if invalid transition detected + spw_di : in std_logic; -- Data In signal from SpaceWire bus + spw_si : in std_logic -- Strobe In signal from SpaceWire bus + ); + end component spwrecvfront_generic; + + -- Front-end for SpaceWire Receiver (separate rx clock domain) + component spwrecvfront_fast is + generic( + rxchunk : integer range 1 to 4 -- max number of bits per system clock + ); + port( + clk : in std_logic; -- system clock + rxclk : in std_logic; -- sample clock (DDR) + rxen : in std_logic; -- high to enable receiver + inact : out std_logic; -- high if activity on input + inbvalid : out std_logic; -- high if inbits contains a valid group of received bits + inbits : out std_logic_vector(rxchunk - 1 downto 0); -- received bits + spw_di : in std_logic; -- Data In signal from SpaceWire bus + spw_si : in std_logic -- Strobe In signal from SpaceWire bus + ); + end component spwrecvfront_fast; + + -- Synchronous two-port memory. + component spwram is + generic( + abits : integer; + dbits : integer); + port( + rclk : in std_logic; + wclk : in std_logic; + ren : in std_logic; + raddr : in std_logic_vector(abits - 1 downto 0); + rdata : out std_logic_vector(dbits - 1 downto 0); + wen : in std_logic; + waddr : in std_logic_vector(abits - 1 downto 0); + wdata : in std_logic_vector(dbits - 1 downto 0)); + end component spwram; + + -- Double flip-flop synchronizer. + component syncdff is + port( + clk : in std_logic; -- clock (destination domain) + rst : in std_logic; -- asynchronous reset, active-high + di : in std_logic; -- input data + do : out std_logic); -- output data + end component syncdff; + + -- Spwerr Interface + component spwerr is + port( + clk : in std_logic; -- system clock + rst : in std_logic; -- asynchronous reset (active-high) + err_link_i : in spwerr_from_link_type; + err_link_o : out spwerr_to_link_type; + err_usr_i : in spwerr_from_usr_type; + err_usr_o : out spwerr_to_usr_type + ); + end component spwerr; end package; diff --git a/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwram.vhd b/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwram.vhd index cee9e8df7..06e1578d1 100644 --- a/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwram.vhd +++ b/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwram.vhd @@ -9,33 +9,32 @@ use ieee.numeric_std.all; entity spwram is - generic ( - abits: integer; - dbits: integer ); - - port ( - rclk: in std_logic; - wclk: in std_logic; - ren: in std_logic; - raddr: in std_logic_vector(abits-1 downto 0); - rdata: out std_logic_vector(dbits-1 downto 0); - wen: in std_logic; - waddr: in std_logic_vector(abits-1 downto 0); - wdata: in std_logic_vector(dbits-1 downto 0) ); + generic( + abits : integer; + dbits : integer); + + port( + rclk : in std_logic; + wclk : in std_logic; + ren : in std_logic; + raddr : in std_logic_vector(abits - 1 downto 0); + rdata : out std_logic_vector(dbits - 1 downto 0); + wen : in std_logic; + waddr : in std_logic_vector(abits - 1 downto 0); + wdata : in std_logic_vector(dbits - 1 downto 0)); end entity spwram; architecture spwram_arch of spwram is - type mem_type is array(0 to (2**abits - 1)) of - std_logic_vector(dbits-1 downto 0); + type mem_type is array (0 to (2**abits - 1)) of std_logic_vector(dbits - 1 downto 0); - signal s_mem: mem_type; + signal s_mem : mem_type; begin -- read process - process (rclk) is + process(rclk) is begin if rising_edge(rclk) then if ren = '1' then @@ -45,7 +44,7 @@ begin end process; -- write process - process (wclk) is + process(wclk) is begin if rising_edge(wclk) then if wen = '1' then diff --git a/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecv.vhd b/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecv.vhd index 98c7a2919..c5d58c457 100644 --- a/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecv.vhd +++ b/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecv.vhd @@ -15,33 +15,29 @@ use work.spwpkg.all; entity spwrecv is - generic ( + generic( -- Disconnect timeout, expressed in system clock cycles. -- Should be 850 ns (727 ns .. 1000 ns) according to the standard. - disconnect_time: integer range 1 to 255; - + disconnect_time : integer range 1 to 255; -- Nr of bits sampled per system clock. - rxchunk: integer range 1 to 4 + rxchunk : integer range 1 to 4 ); - port ( + port( -- System clock. - clk: in std_logic; - + clk : in std_logic; -- High to enable receiver; low to disable and reset receiver. - rxen: in std_logic; - + rxen : in std_logic; -- Output signals to spwlink. - recvo: out spw_recv_out_type; - + recvo : out spw_recv_out_type; -- High if there has been recent activity on the input lines. - inact: in std_logic; - + inact : in std_logic; -- High if inbits contains a valid group of received bits. - inbvalid: in std_logic; - + inbvalid : in std_logic; -- Received bits from receiver front-end. - inbits: in std_logic_vector(rxchunk-1 downto 0) + inbits : in std_logic_vector(rxchunk - 1 downto 0); + -- High if invalid transition detected + invalid_transition : in std_logic ); end entity spwrecv; @@ -51,151 +47,151 @@ architecture spwrecv_arch of spwrecv is -- registers type regs_type is record -- receiver state - bit_seen: std_ulogic; -- got a bit transition - null_seen: std_ulogic; -- got a NULL token + bit_seen : std_ulogic; -- got a bit transition + null_seen : std_ulogic; -- got a NULL token -- input shift register - bitshift: std_logic_vector(8 downto 0); - bitcnt: std_logic_vector(9 downto 0); -- one-hot counter + bitshift : std_logic_vector(8 downto 0); + bitcnt : std_logic_vector(9 downto 0); -- one-hot counter -- parity flag - parity: std_ulogic; + parity : std_ulogic; -- decoding - control: std_ulogic; -- next code is control code - escaped: std_ulogic; -- last code was ESC + control : std_ulogic; -- next code is control code + escaped : std_ulogic; -- last code was ESC -- output registers - gotfct: std_ulogic; - tick_out: std_ulogic; - rxchar: std_ulogic; - rxflag: std_ulogic; - timereg: std_logic_vector(7 downto 0); - datareg: std_logic_vector(7 downto 0); + gotfct : std_ulogic; + tick_out : std_ulogic; + rxchar : std_ulogic; + rxflag : std_ulogic; + timereg : std_logic_vector(7 downto 0); + datareg : std_logic_vector(7 downto 0); -- disconnect timer - disccnt: unsigned(7 downto 0); + disccnt : unsigned(7 downto 0); -- error flags - errpar: std_ulogic; - erresc: std_ulogic; + errpar : std_ulogic; + erresc : std_ulogic; end record; -- Initial state - constant regs_reset: regs_type := ( - bit_seen => '0', - null_seen => '0', - bitshift => (others => '1'), - bitcnt => (others => '0'), - parity => '0', - control => '0', - escaped => '0', - gotfct => '0', - tick_out => '0', - rxchar => '0', - rxflag => '0', - timereg => (others => '0'), - datareg => (others => '0'), - disccnt => "00000000", - errpar => '0', - erresc => '0' ); + constant regs_reset : regs_type := ( + bit_seen => '0', + null_seen => '0', + bitshift => (others => '1'), + bitcnt => (others => '0'), + parity => '0', + control => '0', + escaped => '0', + gotfct => '0', + tick_out => '0', + rxchar => '0', + rxflag => '0', + timereg => (others => '0'), + datareg => (others => '0'), + disccnt => "00000000", + errpar => '0', + erresc => '0'); -- registers - signal r: regs_type := regs_reset; - signal rin: regs_type; + signal r : regs_type := regs_reset; + signal rin : regs_type; begin -- combinatorial process - process (r, rxen, inact, inbvalid, inbits) - variable v: regs_type; - variable v_inbit: std_ulogic; + process(r, rxen, inact, inbvalid, inbits, invalid_transition) + variable v : regs_type; + variable v_inbit : std_ulogic; begin - v := r; - v_inbit := '0'; + v := r; + v_inbit := '0'; -- disconnect timer if inact = '1' then -- activity on input; reset timer - v.disccnt := to_unsigned(disconnect_time, v.disccnt'length); + v.disccnt := to_unsigned(disconnect_time, v.disccnt'length); elsif r.disccnt /= 0 then -- count down - v.disccnt := r.disccnt - 1; + v.disccnt := r.disccnt - 1; end if; -- assume no new token - v.gotfct := '0'; - v.tick_out := '0'; - v.rxchar := '0'; + v.gotfct := '0'; + v.tick_out := '0'; + v.rxchar := '0'; if inbvalid = '1' then -- process incoming bits - for i in 0 to rxchunk-1 loop - v_inbit := inbits(i); + for i in 0 to rxchunk - 1 loop + v_inbit := inbits(i); -- got a bit transition - v.bit_seen := '1'; + v.bit_seen := '1'; if v.bitcnt(0) = '1' then -- received new token -- note that this will not happen before null_seen='1' if (v.parity xor v_inbit) = '0' then -- Parity check failed. - v.errpar := '1'; + v.errpar := '1'; else if v.control = '1' then -- received control code case v.bitshift(7 downto 6) is when "00" => -- FCT or NULL - v.gotfct := not r.escaped; - v.escaped := '0'; + v.gotfct := not r.escaped; + v.escaped := '0'; when "10" => -- EOP if r.escaped = '1' then - v.erresc := '1'; + v.erresc := '1'; end if; - v.escaped := '0'; - v.rxchar := not r.escaped; - v.rxflag := '1'; - v.datareg := "00000000"; + v.escaped := '0'; + v.rxchar := not r.escaped; + v.rxflag := '1'; + v.datareg := "00000000"; when "01" => -- EEP if r.escaped = '1' then - v.erresc := '1'; + v.erresc := '1'; end if; - v.escaped := '0'; - v.rxchar := not r.escaped; - v.rxflag := '1'; - v.datareg := "00000001"; + v.escaped := '0'; + v.rxchar := not r.escaped; + v.rxflag := '1'; + v.datareg := "00000001"; when others => -- ESC if r.escaped = '1' then - v.erresc := '1'; + v.erresc := '1'; end if; - v.escaped := '1'; + v.escaped := '1'; end case; else -- received 8-bit character if r.escaped = '1' then -- received Time-Code - v.tick_out := '1'; - v.timereg := v.bitshift(7 downto 0); + v.tick_out := '1'; + v.timereg := v.bitshift(7 downto 0); else -- received data character - v.rxflag := '0'; - v.rxchar := '1'; - v.datareg := v.bitshift(7 downto 0); + v.rxflag := '0'; + v.rxchar := '1'; + v.datareg := v.bitshift(7 downto 0); end if; - v.escaped := '0'; + v.escaped := '0'; end if; end if; -- prepare for next code - v.parity := '0'; - v.control := v_inbit; + v.parity := '0'; + v.control := v_inbit; if v_inbit = '1' then -- next word will be control code. - v.bitcnt := (3 => '1', others => '0'); + v.bitcnt := (3 => '1', others => '0'); else -- next word will be a data byte. - v.bitcnt := (9 => '1', others => '0'); + v.bitcnt := (9 => '1', others => '0'); end if; else -- wait until next code is completely received; -- accumulate parity - v.bitcnt := '0' & v.bitcnt(9 downto 1); - v.parity := v.parity xor v_inbit; + v.bitcnt := '0' & v.bitcnt(9 downto 1); + v.parity := v.parity xor v_inbit; end if; -- detect first NULL @@ -210,11 +206,15 @@ begin end if; -- shift new bit into register. - v.bitshift := v_inbit & v.bitshift(v.bitshift'high downto 1); + v.bitshift := v_inbit & v.bitshift(v.bitshift'high downto 1); end loop; end if; + if invalid_transition = '1' then + v.bitshift := (others => '1'); + end if; + -- synchronous reset if rxen = '0' then v.bit_seen := '0'; @@ -234,30 +234,30 @@ begin end if; -- drive outputs - recvo.gotbit <= r.bit_seen; - recvo.gotnull <= r.null_seen; - recvo.gotfct <= r.gotfct; - recvo.tick_out <= r.tick_out; - recvo.ctrl_out <= r.timereg(7 downto 6); - recvo.time_out <= r.timereg(5 downto 0); - recvo.rxchar <= r.rxchar; - recvo.rxflag <= r.rxflag; - recvo.rxdata <= r.datareg; + recvo.gotbit <= r.bit_seen; + recvo.gotnull <= r.null_seen; + recvo.gotfct <= r.gotfct; + recvo.tick_out <= r.tick_out; + recvo.ctrl_out <= r.timereg(7 downto 6); + recvo.time_out <= r.timereg(5 downto 0); + recvo.rxchar <= r.rxchar; + recvo.rxflag <= r.rxflag; + recvo.rxdata <= r.datareg; if r.bit_seen = '1' and r.disccnt = 0 then - recvo.errdisc <= '1'; + recvo.errdisc <= '1'; else - recvo.errdisc <= '0'; + recvo.errdisc <= '0'; end if; - recvo.errpar <= r.errpar; - recvo.erresc <= r.erresc; + recvo.errpar <= r.errpar; + recvo.erresc <= r.erresc; -- update registers - rin <= v; + rin <= v; end process; -- update registers on rising edge of system clock - process (clk) is + process(clk) is begin if rising_edge(clk) then r <= rin; diff --git a/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecvfront_fast.vhd b/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecvfront_fast.vhd index 4ce08446b..ae33ce4c8 100644 --- a/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecvfront_fast.vhd +++ b/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecvfront_fast.vhd @@ -69,41 +69,34 @@ use work.spwpkg.all; entity spwrecvfront_fast is - generic ( + generic( -- Number of bits to pass to the application per system clock. - rxchunk: integer range 1 to 4 ); + rxchunk : integer range 1 to 4); - port ( + port( -- System clock. - clk: in std_logic; - + clk : in std_logic; -- Sample clock. - rxclk: in std_logic; - + rxclk : in std_logic; -- High to enable receiver; low to disable and reset receiver. - rxen: in std_logic; - + rxen : in std_logic; -- High if there has been recent activity on the input lines. - inact: out std_logic; - + inact : out std_logic; -- High if inbits contains a valid group of received bits. -- If inbvalid='1', the application must sample inbits on -- the rising edge of clk. - inbvalid: out std_logic; - + inbvalid : out std_logic; -- Received bits (bit 0 is the earliest received bit). - inbits: out std_logic_vector(rxchunk-1 downto 0); - + inbits : out std_logic_vector(rxchunk - 1 downto 0); -- Data In signal from SpaceWire bus. - spw_di: in std_logic; - + spw_di : in std_logic; -- Strobe In signal from SpaceWire bus. - spw_si: in std_logic ); + spw_si : in std_logic); -- Turn off FSM extraction. -- Without this, XST will happily apply one-hot encoding to rrx.headptr. - attribute FSM_EXTRACT: string; - attribute FSM_EXTRACT of spwrecvfront_fast: entity is "NO"; + attribute FSM_EXTRACT : string; + attribute FSM_EXTRACT of spwrecvfront_fast : entity is "NO"; end entity spwrecvfront_fast; @@ -111,162 +104,162 @@ architecture spwrecvfront_arch of spwrecvfront_fast is -- width of bit groups in cyclic buffer; -- typically equal to rxchunk, except when rxchunk = 1 - type memwidth_array_type is array(1 to 4) of integer; - constant chunk_to_memwidth: memwidth_array_type := ( 2, 2, 3, 4 ); - constant memwidth: integer := chunk_to_memwidth(rxchunk); + type memwidth_array_type is array (1 to 4) of integer; + constant chunk_to_memwidth : memwidth_array_type := (2, 2, 3, 4); + constant memwidth : integer := chunk_to_memwidth(rxchunk); -- registers in rxclk domain type rxregs_type is record -- stage B: re-register input samples - b_di0: std_ulogic; - b_si0: std_ulogic; - b_di1: std_ulogic; - b_si1: std_ulogic; + b_di0 : std_ulogic; + b_si0 : std_ulogic; + b_di1 : std_ulogic; + b_si1 : std_ulogic; -- stage C: data/strobe decoding - c_bit: std_logic_vector(1 downto 0); - c_val: std_logic_vector(1 downto 0); - c_xor1: std_ulogic; + c_bit : std_logic_vector(1 downto 0); + c_val : std_logic_vector(1 downto 0); + c_xor1 : std_ulogic; -- stage D: collect groups of memwidth bits - d_shift: std_logic_vector(memwidth-1 downto 0); - d_count: std_logic_vector(memwidth-1 downto 0); + d_shift : std_logic_vector(memwidth - 1 downto 0); + d_count : std_logic_vector(memwidth - 1 downto 0); -- cyclic buffer access - bufdata: std_logic_vector(memwidth-1 downto 0); - bufwrite: std_ulogic; - headptr: std_logic_vector(2 downto 0); + bufdata : std_logic_vector(memwidth - 1 downto 0); + bufwrite : std_ulogic; + headptr : std_logic_vector(2 downto 0); -- activity detection - bitcnt: std_logic_vector(2 downto 0); + bitcnt : std_logic_vector(2 downto 0); end record; -- registers in system clock domain type regs_type is record -- data path from buffer to output - tailptr: std_logic_vector(2 downto 0); - inbvalid: std_ulogic; + tailptr : std_logic_vector(2 downto 0); + inbvalid : std_ulogic; -- split 2-bit groups if rxchunk=1 - splitbit: std_ulogic; - splitinx: std_ulogic; - splitvalid: std_ulogic; + splitbit : std_ulogic; + splitinx : std_ulogic; + splitvalid : std_ulogic; -- activity detection - bitcntp: std_logic_vector(2 downto 0); - inact: std_ulogic; + bitcntp : std_logic_vector(2 downto 0); + inact : std_ulogic; -- reset signal towards rxclk domain - rxdis: std_ulogic; + rxdis : std_ulogic; end record; - constant regs_reset: regs_type := ( - tailptr => "000", - inbvalid => '0', - splitbit => '0', - splitinx => '0', - splitvalid => '0', - bitcntp => "000", - inact => '0', - rxdis => '1' ); + constant regs_reset : regs_type := ( + tailptr => "000", + inbvalid => '0', + splitbit => '0', + splitinx => '0', + splitvalid => '0', + bitcntp => "000", + inact => '0', + rxdis => '1'); -- Signals that are re-synchronized from rxclk to system clock domain. type syncsys_type is record - headptr: std_logic_vector(2 downto 0); -- pointer in cyclic buffer - bitcnt: std_logic_vector(2 downto 0); -- activity detection + headptr : std_logic_vector(2 downto 0); -- pointer in cyclic buffer + bitcnt : std_logic_vector(2 downto 0); -- activity detection end record; -- Registers. - signal r: regs_type := regs_reset; - signal rin: regs_type; - signal rrx, rrxin: rxregs_type; + signal r : regs_type := regs_reset; + signal rin : regs_type; + signal rrx, rrxin : rxregs_type; -- Synchronized signals after crossing clock domains. - signal syncrx_rstn: std_logic; - signal syncsys: syncsys_type; + signal syncrx_rstn : std_logic; + signal syncsys : syncsys_type; -- Output data from cyclic buffer. - signal s_bufdout: std_logic_vector(memwidth-1 downto 0); + signal s_bufdout : std_logic_vector(memwidth - 1 downto 0); -- stage A: input flip-flops for rising/falling rxclk - signal s_a_di0: std_logic; - signal s_a_si0: std_logic; - signal s_a_di1: std_logic; - signal s_a_si1: std_logic; - signal s_a_di2: std_logic; - signal s_a_si2: std_logic; + signal s_a_di0 : std_logic; + signal s_a_si0 : std_logic; + signal s_a_di1 : std_logic; + signal s_a_si1 : std_logic; + signal s_a_di2 : std_logic; + signal s_a_si2 : std_logic; -- force use of IOB flip-flops - attribute IOB: string; - attribute IOB of s_a_di1: signal is "TRUE"; - attribute IOB of s_a_si1: signal is "TRUE"; - attribute IOB of s_a_di2: signal is "TRUE"; - attribute IOB of s_a_si2: signal is "TRUE"; + attribute IOB : string; + attribute IOB of s_a_di1 : signal is "TRUE"; + attribute IOB of s_a_si1 : signal is "TRUE"; + attribute IOB of s_a_di2 : signal is "TRUE"; + attribute IOB of s_a_si2 : signal is "TRUE"; begin -- Cyclic data buffer. - bufmem: spwram - generic map ( - abits => 3, - dbits => memwidth ) - port map ( - rclk => clk, - wclk => rxclk, - ren => '1', - raddr => r.tailptr, - rdata => s_bufdout, - wen => rrx.bufwrite, - waddr => rrx.headptr, - wdata => rrx.bufdata ); + bufmem : spwram + generic map( + abits => 3, + dbits => memwidth) + port map( + rclk => clk, + wclk => rxclk, + ren => '1', + raddr => r.tailptr, + rdata => s_bufdout, + wen => rrx.bufwrite, + waddr => rrx.headptr, + wdata => rrx.bufdata); -- Synchronize reset signal for rxclk domain. - syncrx_reset: syncdff - port map ( clk => rxclk, rst => r.rxdis, di => '1', do => syncrx_rstn ); + syncrx_reset : syncdff + port map(clk => rxclk, rst => r.rxdis, di => '1', do => syncrx_rstn); -- Synchronize signals from rxclk domain to system clock domain. - syncsys_headptr0: syncdff - port map ( clk => clk, rst => r.rxdis, di => rrx.headptr(0), do => syncsys.headptr(0) ); - syncsys_headptr1: syncdff - port map ( clk => clk, rst => r.rxdis, di => rrx.headptr(1), do => syncsys.headptr(1) ); - syncsys_headptr2: syncdff - port map ( clk => clk, rst => r.rxdis, di => rrx.headptr(2), do => syncsys.headptr(2) ); - syncsys_bitcnt0: syncdff - port map ( clk => clk, rst => r.rxdis, di => rrx.bitcnt(0), do => syncsys.bitcnt(0) ); - syncsys_bitcnt1: syncdff - port map ( clk => clk, rst => r.rxdis, di => rrx.bitcnt(1), do => syncsys.bitcnt(1) ); - syncsys_bitcnt2: syncdff - port map ( clk => clk, rst => r.rxdis, di => rrx.bitcnt(2), do => syncsys.bitcnt(2) ); + syncsys_headptr0 : syncdff + port map(clk => clk, rst => r.rxdis, di => rrx.headptr(0), do => syncsys.headptr(0)); + syncsys_headptr1 : syncdff + port map(clk => clk, rst => r.rxdis, di => rrx.headptr(1), do => syncsys.headptr(1)); + syncsys_headptr2 : syncdff + port map(clk => clk, rst => r.rxdis, di => rrx.headptr(2), do => syncsys.headptr(2)); + syncsys_bitcnt0 : syncdff + port map(clk => clk, rst => r.rxdis, di => rrx.bitcnt(0), do => syncsys.bitcnt(0)); + syncsys_bitcnt1 : syncdff + port map(clk => clk, rst => r.rxdis, di => rrx.bitcnt(1), do => syncsys.bitcnt(1)); + syncsys_bitcnt2 : syncdff + port map(clk => clk, rst => r.rxdis, di => rrx.bitcnt(2), do => syncsys.bitcnt(2)); -- sample inputs on rising edge of rxclk - process (rxclk) is + process(rxclk) is begin if rising_edge(rxclk) then - s_a_di1 <= spw_di; - s_a_si1 <= spw_si; + s_a_di1 <= spw_di; + s_a_si1 <= spw_si; end if; end process; -- sample inputs on falling edge of rxclk - process (rxclk) is + process(rxclk) is begin if falling_edge(rxclk) then - s_a_di2 <= spw_di; - s_a_si2 <= spw_si; + s_a_di2 <= spw_di; + s_a_si2 <= spw_si; -- reregister inputs in fabric flip-flops - s_a_di0 <= s_a_di2; - s_a_si0 <= s_a_si2; + s_a_di0 <= s_a_di2; + s_a_si0 <= s_a_si2; end if; end process; -- combinatorial process - process (r, rrx, rxen, syncrx_rstn, syncsys, s_bufdout, s_a_di0, s_a_si0, s_a_di1, s_a_si1) - variable v: regs_type; - variable vrx: rxregs_type; + process(r, rrx, rxen, syncrx_rstn, syncsys, s_bufdout, s_a_di0, s_a_si0, s_a_di1, s_a_si1) + variable v : regs_type; + variable vrx : rxregs_type; begin - v := r; - vrx := rrx; + v := r; + vrx := rrx; -- ---- SAMPLE CLOCK DOMAIN ---- -- stage B: re-register input samples - vrx.b_di0 := s_a_di0; - vrx.b_si0 := s_a_si0; - vrx.b_di1 := s_a_di1; - vrx.b_si1 := s_a_si1; + vrx.b_di0 := s_a_di0; + vrx.b_si0 := s_a_si0; + vrx.b_di1 := s_a_di1; + vrx.b_si1 := s_a_si1; -- stage C: decode data/strobe and detect valid bits if (rrx.b_di0 xor rrx.b_si0 xor rrx.c_xor1) = '1' then @@ -275,10 +268,8 @@ begin vrx.c_bit(0) := rrx.b_di1; end if; vrx.c_bit(1) := rrx.b_di1; - vrx.c_val(0) := (rrx.b_di0 xor rrx.b_si0 xor rrx.c_xor1) or - (rrx.b_di0 xor rrx.b_si0 xor rrx.b_di1 xor rrx.b_si1); - vrx.c_val(1) := (rrx.b_di0 xor rrx.b_si0 xor rrx.c_xor1) and - (rrx.b_di0 xor rrx.b_si0 xor rrx.b_di1 xor rrx.b_si1); + vrx.c_val(0) := (rrx.b_di0 xor rrx.b_si0 xor rrx.c_xor1) or (rrx.b_di0 xor rrx.b_si0 xor rrx.b_di1 xor rrx.b_si1); + vrx.c_val(1) := (rrx.b_di0 xor rrx.b_si0 xor rrx.c_xor1) and (rrx.b_di0 xor rrx.b_si0 xor rrx.b_di1 xor rrx.b_si1); vrx.c_xor1 := rrx.b_di1 xor rrx.b_si1; -- Note: @@ -291,24 +282,24 @@ begin -- shift incoming bits into register if rrx.c_val(1) = '1' then - vrx.d_shift := rrx.c_bit & rrx.d_shift(memwidth-1 downto 2); + vrx.d_shift := rrx.c_bit & rrx.d_shift(memwidth - 1 downto 2); else - vrx.d_shift := rrx.c_bit(0) & rrx.d_shift(memwidth-1 downto 1); + vrx.d_shift := rrx.c_bit(0) & rrx.d_shift(memwidth - 1 downto 1); end if; -- prepare to store a group of memwidth bits if rrx.d_count(0) = '1' then -- only one more bit needed - vrx.bufdata := rrx.c_bit(0) & rrx.d_shift(memwidth-1 downto 1); + vrx.bufdata := rrx.c_bit(0) & rrx.d_shift(memwidth - 1 downto 1); else - vrx.bufdata := rrx.c_bit & rrx.d_shift(memwidth-1 downto 2); + vrx.bufdata := rrx.c_bit & rrx.d_shift(memwidth - 1 downto 2); end if; -- countdown nr of needed bits (one-hot counter) if rrx.c_val(1) = '1' then - vrx.d_count := rrx.d_count(1 downto 0) & rrx.d_count(memwidth-1 downto 2); + vrx.d_count := rrx.d_count(1 downto 0) & rrx.d_count(memwidth - 1 downto 2); else - vrx.d_count := rrx.d_count(0 downto 0) & rrx.d_count(memwidth-1 downto 1); + vrx.d_count := rrx.d_count(0 downto 0) & rrx.d_count(memwidth - 1 downto 1); end if; end if; @@ -323,18 +314,18 @@ begin -- Activity detection. if rrx.c_val(0) = '1' then - vrx.bitcnt := std_logic_vector(unsigned(rrx.bitcnt) + 1); + vrx.bitcnt := std_logic_vector(unsigned(rrx.bitcnt) + 1); end if; -- Synchronous reset of rxclk domain. if syncrx_rstn = '0' then - vrx.c_val := "00"; - vrx.c_xor1 := '0'; - vrx.d_count := (others => '0'); - vrx.d_count(memwidth-1) := '1'; - vrx.bufwrite := '0'; - vrx.headptr := "000"; - vrx.bitcnt := "000"; + vrx.c_val := "00"; + vrx.c_xor1 := '0'; + vrx.d_count := (others => '0'); + vrx.d_count(memwidth - 1) := '1'; + vrx.bufwrite := '0'; + vrx.headptr := "000"; + vrx.bitcnt := "000"; end if; -- ---- SYSTEM CLOCK DOMAIN ---- @@ -344,13 +335,13 @@ begin -- not yet been written by the rxclk domain. if r.tailptr = syncsys.headptr then -- No more data in cyclic buffer. - v.inbvalid := '0'; + v.inbvalid := '0'; else -- Reading valid data from cyclic buffer. - v.inbvalid := '1'; + v.inbvalid := '1'; -- Increment tail pointer. if rxchunk /= 1 then - v.tailptr := std_logic_vector(unsigned(r.tailptr) + 1); + v.tailptr := std_logic_vector(unsigned(r.tailptr) + 1); end if; end if; @@ -358,55 +349,55 @@ begin if rxchunk = 1 then -- Select one of the two bits. if r.splitinx = '0' then - v.splitbit := s_bufdout(0); + v.splitbit := s_bufdout(0); else - v.splitbit := s_bufdout(1); + v.splitbit := s_bufdout(1); end if; -- Indicate valid bit. v.splitvalid := r.inbvalid; -- Increment tail pointer. if r.inbvalid = '1' then - v.splitinx := not r.splitinx; + v.splitinx := not r.splitinx; if r.splitinx = '0' then - v.tailptr := std_logic_vector(unsigned(r.tailptr) + 1); + v.tailptr := std_logic_vector(unsigned(r.tailptr) + 1); end if; end if; end if; -- Activity detection. - v.bitcntp := syncsys.bitcnt; + v.bitcntp := syncsys.bitcnt; if r.bitcntp = syncsys.bitcnt then - v.inact := '0'; + v.inact := '0'; else - v.inact := '1'; + v.inact := '1'; end if; -- Synchronous reset of system clock domain. if rxen = '0' then - v := regs_reset; + v := regs_reset; end if; -- Register rxen to ensure glitch-free signal to rxclk domain - v.rxdis := not rxen; + v.rxdis := not rxen; -- drive outputs - inact <= r.inact; + inact <= r.inact; if rxchunk = 1 then - inbvalid <= r.splitvalid; - inbits(0) <= r.splitbit; + inbvalid <= r.splitvalid; + inbits(0) <= r.splitbit; else - inbvalid <= r.inbvalid; - inbits <= s_bufdout; + inbvalid <= r.inbvalid; + inbits <= s_bufdout; end if; -- update registers - rrxin <= vrx; - rin <= v; + rrxin <= vrx; + rin <= v; end process; -- update registers on rising edge of rxclk - process (rxclk) is + process(rxclk) is begin if rising_edge(rxclk) then rrx <= rrxin; @@ -414,7 +405,7 @@ begin end process; -- update registers on rising edge of system clock - process (clk) is + process(clk) is begin if rising_edge(clk) then r <= rin; diff --git a/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecvfront_generic.vhd b/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecvfront_generic.vhd index 2104f2346..b318c4cb9 100644 --- a/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecvfront_generic.vhd +++ b/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecvfront_generic.vhd @@ -15,79 +15,81 @@ use ieee.numeric_std.all; entity spwrecvfront_generic is - port ( + port( -- System clock. - clk: in std_logic; - + clk : in std_logic; -- High to enable receiver; low to disable and reset receiver. - rxen: in std_logic; - + rxen : in std_logic; -- High if there has been recent activity on the input lines. - inact: out std_logic; - + inact : out std_logic; -- High if inbits contains a valid received bit. -- If inbvalid='1', the application must sample inbits on -- the rising edge of clk. - inbvalid: out std_logic; - + inbvalid : out std_logic; -- Received bit - inbits: out std_logic_vector(0 downto 0); - + inbits : out std_logic_vector(0 downto 0); + -- High if invalid transition detected + invalid_transition : out std_logic; -- Data In signal from SpaceWire bus. - spw_di: in std_logic; - + spw_di : in std_logic; -- Strobe In signal from SpaceWire bus. - spw_si: in std_logic ); + spw_si : in std_logic); end entity spwrecvfront_generic; architecture spwrecvfront_arch of spwrecvfront_generic is -- input flip-flops - signal s_spwdi1: std_ulogic; - signal s_spwsi1: std_ulogic; - signal s_spwdi2: std_ulogic; - signal s_spwsi2: std_ulogic; + signal s_spwdi1 : std_ulogic; + signal s_spwsi1 : std_ulogic; + signal s_spwdi2 : std_ulogic; + signal s_spwsi2 : std_ulogic; -- data/strobe decoding - signal s_spwsi3: std_ulogic; + signal s_spwsi3 : std_ulogic; -- output registers - signal s_inbvalid: std_ulogic; - signal s_inbit: std_ulogic; + signal s_inbvalid : std_ulogic; + signal s_inbit : std_ulogic; + + -- invalid transition detection + signal s_invalid_transition : std_ulogic; begin -- drive outputs - inact <= s_inbvalid; - inbvalid <= s_inbvalid; - inbits(0) <= s_inbit; + inact <= s_inbvalid; + inbvalid <= s_inbvalid; + inbits(0) <= s_inbit; + invalid_transition <= s_invalid_transition; -- synchronous process - process (clk) is + process(clk) is begin if rising_edge(clk) then -- sample input signal - s_spwdi1 <= spw_di; - s_spwsi1 <= spw_si; + s_spwdi1 <= spw_di; + s_spwsi1 <= spw_si; -- more flip-flops for safe synchronization - s_spwdi2 <= s_spwdi1; - s_spwsi2 <= s_spwsi1; + s_spwdi2 <= s_spwdi1; + s_spwsi2 <= s_spwsi1; -- keep strobe signal for data/strobe decoding - s_spwsi3 <= s_spwsi2; + s_spwsi3 <= s_spwsi2; -- keep data bit for data/strobe decoding - s_inbit <= s_spwdi2; + s_inbit <= s_spwdi2; if rxen = '1' then -- data/strobe decoding - s_inbvalid <= s_spwdi2 xor s_spwsi2 xor s_inbit xor s_spwsi3; + s_inbvalid <= s_spwdi2 xor s_spwsi2 xor s_inbit xor s_spwsi3; + s_invalid_transition <= (s_spwdi2 xor s_inbit) and (s_spwsi2 xor s_spwsi3); else -- reset receiver - s_inbvalid <= '0'; + s_inbvalid <= '0'; + s_invalid_transition <= '0'; end if; end if; diff --git a/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwstream.vhd b/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwstream.vhd index fd8ccade2..28fd18393 100644 --- a/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwstream.vhd +++ b/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwstream.vhd @@ -22,175 +22,132 @@ use work.spwpkg.all; entity spwstream is - generic ( + generic( -- System clock frequency in Hz. -- This must be set to the frequency of "clk". It is used to setup -- counters for reset timing, disconnect timeout and to transmit -- at 10 Mbit/s during the link handshake. - sysfreq: real; - + sysfreq : real; -- Transmit clock frequency in Hz (only if tximpl = impl_fast). -- This must be set to the frequency of "txclk". It is used to -- transmit at 10 Mbit/s during the link handshake. - txclkfreq: real := 0.0; - + txclkfreq : real := 0.0; -- Selection of a receiver front-end implementation. - rximpl: spw_implementation_type := impl_generic; - + rximpl : spw_implementation_type := impl_generic; -- Maximum number of bits received per system clock -- (must be 1 in case of impl_generic). - rxchunk: integer range 1 to 4 := 1; - + rxchunk : integer range 1 to 4 := 1; -- Selection of a transmitter implementation. - tximpl: spw_implementation_type := impl_generic; - + tximpl : spw_implementation_type := impl_generic; -- Size of the receive FIFO as the 2-logarithm of the number of bytes. -- Must be at least 6 (64 bytes). - rxfifosize_bits: integer range 6 to 14 := 11; - + rxfifosize_bits : integer range 6 to 14 := 11; -- Size of the transmit FIFO as the 2-logarithm of the number of bytes. - txfifosize_bits: integer range 2 to 14 := 11 + txfifosize_bits : integer range 2 to 14 := 11 ); - port ( + port( -- System clock. - clk: in std_logic; - + clk : in std_logic; -- Receiver sample clock (only for impl_fast) - rxclk: in std_logic; - + rxclk : in std_logic; -- Transmit clock (only for impl_fast) - txclk: in std_logic; - + txclk : in std_logic; -- Synchronous reset (active-high). - rst: in std_logic; - + rst : in std_logic; -- Enables automatic link start on receipt of a NULL character. - autostart: in std_logic; - + autostart : in std_logic; -- Enables link start once the Ready state is reached. -- Without autostart or linkstart, the link remains in state Ready. - linkstart: in std_logic; - + linkstart : in std_logic; -- Do not start link (overrides linkstart and autostart) and/or -- disconnect a running link. - linkdis: in std_logic; - + linkdis : in std_logic; -- Scaling factor minus 1, used to scale the transmit base clock into -- the transmission bit rate. The system clock (for impl_generic) or -- the txclk (for impl_fast) is divided by (unsigned(txdivcnt) + 1). -- Changing this signal will immediately change the transmission rate. -- During link setup, the transmission rate is always 10 Mbit/s. - txdivcnt: in std_logic_vector(7 downto 0); - + txdivcnt : in std_logic_vector(7 downto 0); -- High for one clock cycle to request transmission of a TimeCode. -- The request is registered inside the entity until it can be processed. - tick_in: in std_logic; - + tick_in : in std_logic; -- Control bits of the TimeCode to be sent. Must be valid while tick_in is high. - ctrl_in: in std_logic_vector(1 downto 0); - + ctrl_in : in std_logic_vector(1 downto 0); -- Counter value of the TimeCode to be sent. Must be valid while tick_in is high. - time_in: in std_logic_vector(5 downto 0); - + time_in : in std_logic_vector(5 downto 0); -- Pulled high by the application to write an N-Char to the transmit -- queue. If "txwrite" and "txrdy" are both high on the rising edge -- of "clk", a character is added to the transmit queue. -- This signal has no effect if "txrdy" is low. - txwrite: in std_logic; - + txwrite : in std_logic; -- Control flag to be sent with the next N_Char. -- Must be valid while txwrite is high. - txflag: in std_logic; - + txflag : in std_logic; -- Byte to be sent, or "00000000" for EOP or "00000001" for EEP. -- Must be valid while txwrite is high. - txdata: in std_logic_vector(7 downto 0); - + txdata : in std_logic_vector(7 downto 0); -- High if the entity is ready to accept an N-Char for transmission. - txrdy: out std_logic; - + txrdy : out std_logic; -- High if the transmission queue is at least half full. - txhalff: out std_logic; - + txhalff : out std_logic; -- High for one clock cycle if a TimeCode was just received. - tick_out: out std_logic; - + tick_out : out std_logic; -- Control bits of the last received TimeCode. - ctrl_out: out std_logic_vector(1 downto 0); - + ctrl_out : out std_logic_vector(1 downto 0); -- Counter value of the last received TimeCode. - time_out: out std_logic_vector(5 downto 0); - + time_out : out std_logic_vector(5 downto 0); -- High if "rxflag" and "rxdata" contain valid data. -- This signal is high unless the receive FIFO is empty. - rxvalid: out std_logic; - + rxvalid : out std_logic; -- High if the receive FIFO is at least half full. - rxhalff: out std_logic; - + rxhalff : out std_logic; -- High if the received character is EOP or EEP; low if the received -- character is a data byte. Valid if "rxvalid" is high. - rxflag: out std_logic; - + rxflag : out std_logic; -- Received byte, or "00000000" for EOP or "00000001" for EEP. -- Valid if "rxvalid" is high. - rxdata: out std_logic_vector(7 downto 0); - + rxdata : out std_logic_vector(7 downto 0); -- Pulled high by the application to accept a received character. -- If "rxvalid" and "rxread" are both high on the rising edge of "clk", -- a character is removed from the receive FIFO and "rxvalid", "rxflag" -- and "rxdata" are updated. -- This signal has no effect if "rxvalid" is low. - rxread: in std_logic; - + rxread : in std_logic; -- High if the link state machine is currently in the Started state. - started: out std_logic; - + started : out std_logic; -- High if the link state machine is currently in the Connecting state. - connecting: out std_logic; - + connecting : out std_logic; -- High if the link state machine is currently in the Run state, indicating -- that the link is fully operational. If none of started, connecting or running -- is high, the link is in an initial state and the transmitter is not yet enabled. - running: out std_logic; - + running : out std_logic; -- Disconnect detected in state Run. Triggers a reset and reconnect of the link. -- This indication is auto-clearing. - errdisc: out std_logic; - + errdisc : out std_logic; -- Parity error detected in state Run. Triggers a reset and reconnect of the link. -- This indication is auto-clearing. - errpar: out std_logic; - + errpar : out std_logic; -- Invalid escape sequence detected in state Run. Triggers a reset and reconnect of -- the link. This indication is auto-clearing. - erresc: out std_logic; - + erresc : out std_logic; -- Credit error detected. Triggers a reset and reconnect of the link. -- This indication is auto-clearing. - errcred: out std_logic; - + errcred : out std_logic; -- Data In signal from SpaceWire bus. - spw_di: in std_logic; - + spw_di : in std_logic; -- Strobe In signal from SpaceWire bus. - spw_si: in std_logic; - + spw_si : in std_logic; -- Data Out signal to SpaceWire bus. - spw_do: out std_logic; - + spw_do : out std_logic; -- Strobe Out signal to SpaceWire bus. - spw_so: out std_logic; - + spw_so : out std_logic; -- Error injection main input request (active high) - err_inj_i: in std_logic; - + err_inj_i : in std_logic; -- Error injection - error type selection - err_sel_i: in t_spw_err_sel; - + err_sel_i : in t_spw_err_sel; -- Error injection - status - err_stat_o: out t_spw_err_stat + err_stat_o : out t_spw_err_stat ); end entity spwstream; @@ -198,206 +155,206 @@ end entity spwstream; architecture spwstream_arch of spwstream is -- Convert boolean to std_logic. - type bool_to_logic_type is array(boolean) of std_ulogic; - constant bool_to_logic: bool_to_logic_type := (false => '0', true => '1'); + type bool_to_logic_type is array (boolean) of std_ulogic; + constant bool_to_logic : bool_to_logic_type := (false => '0', true => '1'); -- Reset time (6.4 us) in system clocks - constant reset_time: integer := integer(sysfreq * 6.4e-6); + constant reset_time : integer := integer(sysfreq * 6.4e-6); -- Disconnect time (850 ns) in system clocks - constant disconnect_time: integer := integer(sysfreq * 850.0e-9); + constant disconnect_time : integer := integer(sysfreq * 850.0e-9); -- Initial tx clock scaler (10 Mbit). - type impl_to_real_type is array(spw_implementation_type) of real; - constant tximpl_to_txclk_freq: impl_to_real_type := - (impl_generic => sysfreq, impl_fast => txclkfreq); - constant effective_txclk_freq: real := tximpl_to_txclk_freq(tximpl); - constant default_divcnt: std_logic_vector(7 downto 0) := - std_logic_vector(to_unsigned(integer(effective_txclk_freq / 10.0e6 - 1.0), 8)); + type impl_to_real_type is array (spw_implementation_type) of real; + constant tximpl_to_txclk_freq : impl_to_real_type := (impl_generic => sysfreq, impl_fast => txclkfreq); + constant effective_txclk_freq : real := tximpl_to_txclk_freq(tximpl); + constant default_divcnt : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(integer(effective_txclk_freq / 10.0e6 - 1.0), 8)); -- Registers. type regs_type is record -- packet state - rxpacket: std_logic; -- '1' when receiving a packet - rxeep: std_logic; -- '1' when rx EEP character pending - txpacket: std_logic; -- '1' when transmitting a packet - txdiscard: std_logic; -- '1' when discarding a tx packet + rxpacket : std_logic; -- '1' when receiving a packet + rxeep : std_logic; -- '1' when rx EEP character pending + txpacket : std_logic; -- '1' when transmitting a packet + txdiscard : std_logic; -- '1' when discarding a tx packet -- FIFO pointers - rxfifo_raddr: std_logic_vector(rxfifosize_bits-1 downto 0); - rxfifo_waddr: std_logic_vector(rxfifosize_bits-1 downto 0); - txfifo_raddr: std_logic_vector(txfifosize_bits-1 downto 0); - txfifo_waddr: std_logic_vector(txfifosize_bits-1 downto 0); + rxfifo_raddr : std_logic_vector(rxfifosize_bits - 1 downto 0); + rxfifo_waddr : std_logic_vector(rxfifosize_bits - 1 downto 0); + txfifo_raddr : std_logic_vector(txfifosize_bits - 1 downto 0); + txfifo_waddr : std_logic_vector(txfifosize_bits - 1 downto 0); -- FIFO state - rxfifo_rvalid: std_logic; -- '1' if s_rxfifo_rdata is valid - txfifo_rvalid: std_logic; -- '1' if s_txfifo_rdata is valid - rxfull: std_logic; -- '1' if RX fifo is full - rxhalff: std_logic; -- '1' if RX fifo is at least half full - txfull: std_logic; -- '1' if TX fifo is full - txhalff: std_logic; -- '1' if TX fifo is at least half full - rxroom: std_logic_vector(5 downto 0); + rxfifo_rvalid : std_logic; -- '1' if s_rxfifo_rdata is valid + txfifo_rvalid : std_logic; -- '1' if s_txfifo_rdata is valid + rxfull : std_logic; -- '1' if RX fifo is full + rxhalff : std_logic; -- '1' if RX fifo is at least half full + txfull : std_logic; -- '1' if TX fifo is full + txhalff : std_logic; -- '1' if TX fifo is at least half full + rxroom : std_logic_vector(5 downto 0); end record; - constant regs_reset: regs_type := ( - rxpacket => '0', - rxeep => '0', - txpacket => '0', - txdiscard => '0', - rxfifo_raddr => (others => '0'), - rxfifo_waddr => (others => '0'), - txfifo_raddr => (others => '0'), - txfifo_waddr => (others => '0'), - rxfifo_rvalid => '0', - txfifo_rvalid => '0', - rxfull => '0', - rxhalff => '0', - txfull => '0', - txhalff => '0', - rxroom => (others => '0') ); - - signal r: regs_type := regs_reset; - signal rin: regs_type; + constant regs_reset : regs_type := ( + rxpacket => '0', + rxeep => '0', + txpacket => '0', + txdiscard => '0', + rxfifo_raddr => (others => '0'), + rxfifo_waddr => (others => '0'), + txfifo_raddr => (others => '0'), + txfifo_waddr => (others => '0'), + rxfifo_rvalid => '0', + txfifo_rvalid => '0', + rxfull => '0', + rxhalff => '0', + txfull => '0', + txhalff => '0', + rxroom => (others => '0')); + + signal r : regs_type := regs_reset; + signal rin : regs_type; -- Interface signals to components. - signal recv_rxen: std_logic; - signal recvo: spw_recv_out_type; - signal recv_inact: std_logic; - signal recv_inbvalid: std_logic; - signal recv_inbits: std_logic_vector(rxchunk-1 downto 0); - signal xmiti: spw_xmit_in_type; - signal xmito: spw_xmit_out_type; - signal xmit_divcnt: std_logic_vector(7 downto 0); - signal linki: spw_link_in_type; - signal linko: spw_link_out_type; + signal recv_rxen : std_logic; + signal recvo : spw_recv_out_type; + signal recv_inact : std_logic; + signal recv_inbvalid : std_logic; + signal recv_inbits : std_logic_vector(rxchunk - 1 downto 0); + signal recv_invalid_transition : std_logic; + signal xmiti : spw_xmit_in_type; + signal xmito : spw_xmit_out_type; + signal xmit_divcnt : std_logic_vector(7 downto 0); + signal linki : spw_link_in_type; + signal linko : spw_link_out_type; -- Memory interface signals. - signal s_rxfifo_raddr: std_logic_vector(rxfifosize_bits-1 downto 0); - signal s_rxfifo_rdata: std_logic_vector(8 downto 0); - signal s_rxfifo_wen: std_logic; - signal s_rxfifo_waddr: std_logic_vector(rxfifosize_bits-1 downto 0); - signal s_rxfifo_wdata: std_logic_vector(8 downto 0); - signal s_txfifo_raddr: std_logic_vector(txfifosize_bits-1 downto 0); - signal s_txfifo_rdata: std_logic_vector(8 downto 0); - signal s_txfifo_wen: std_logic; - signal s_txfifo_waddr: std_logic_vector(txfifosize_bits-1 downto 0); - signal s_txfifo_wdata: std_logic_vector(8 downto 0); + signal s_rxfifo_raddr : std_logic_vector(rxfifosize_bits - 1 downto 0); + signal s_rxfifo_rdata : std_logic_vector(8 downto 0); + signal s_rxfifo_wen : std_logic; + signal s_rxfifo_waddr : std_logic_vector(rxfifosize_bits - 1 downto 0); + signal s_rxfifo_wdata : std_logic_vector(8 downto 0); + signal s_txfifo_raddr : std_logic_vector(txfifosize_bits - 1 downto 0); + signal s_txfifo_rdata : std_logic_vector(8 downto 0); + signal s_txfifo_wen : std_logic; + signal s_txfifo_waddr : std_logic_vector(txfifosize_bits - 1 downto 0); + signal s_txfifo_wdata : std_logic_vector(8 downto 0); begin -- Instantiate link controller. - link_inst: spwlink - generic map ( - reset_time => reset_time ) - port map ( - clk => clk, - rst => rst, - linki => linki, - linko => linko, - rxen => recv_rxen, - recvo => recvo, - xmiti => xmiti, - xmito => xmito ); + link_inst : spwlink + generic map( + reset_time => reset_time) + port map( + clk => clk, + rst => rst, + linki => linki, + linko => linko, + rxen => recv_rxen, + recvo => recvo, + xmiti => xmiti, + xmito => xmito); -- Instantiate receiver. - recv_inst: spwrecv + recv_inst : spwrecv generic map( disconnect_time => disconnect_time, - rxchunk => rxchunk ) - port map ( - clk => clk, - rxen => recv_rxen, - recvo => recvo, - inact => recv_inact, - inbvalid => recv_inbvalid, - inbits => recv_inbits ); + rxchunk => rxchunk) + port map( + clk => clk, + rxen => recv_rxen, + recvo => recvo, + inact => recv_inact, + inbvalid => recv_inbvalid, + inbits => recv_inbits, + invalid_transition => recv_invalid_transition); -- Instantiate transmitter. - xmit_sel0: if tximpl = impl_generic generate - xmit_inst: spwxmit - port map ( - clk => clk, - rst => rst, - divcnt => xmit_divcnt, - xmiti => xmiti, - xmito => xmito, - spw_do => spw_do, - spw_so => spw_so ); + xmit_sel0 : if tximpl = impl_generic generate + xmit_inst : spwxmit + port map( + clk => clk, + rst => rst, + divcnt => xmit_divcnt, + xmiti => xmiti, + xmito => xmito, + spw_do => spw_do, + spw_so => spw_so); end generate; - xmit_sel1: if tximpl = impl_fast generate - xmit_fast_inst: spwxmit_fast - port map ( - clk => clk, - txclk => txclk, - rst => rst, - divcnt => xmit_divcnt, - xmiti => xmiti, - xmito => xmito, - spw_do => spw_do, - spw_so => spw_so ); + xmit_sel1 : if tximpl = impl_fast generate + xmit_fast_inst : spwxmit_fast + port map( + clk => clk, + txclk => txclk, + rst => rst, + divcnt => xmit_divcnt, + xmiti => xmiti, + xmito => xmito, + spw_do => spw_do, + spw_so => spw_so); end generate; -- Instantiate receiver front-end. - recvfront_sel0: if rximpl = impl_generic generate - recvfront_generic_inst: spwrecvfront_generic - port map ( - clk => clk, - rxen => recv_rxen, - inact => recv_inact, - inbvalid => recv_inbvalid, - inbits => recv_inbits, - spw_di => spw_di, - spw_si => spw_si ); + recvfront_sel0 : if rximpl = impl_generic generate + recvfront_generic_inst : spwrecvfront_generic + port map( + clk => clk, + rxen => recv_rxen, + inact => recv_inact, + inbvalid => recv_inbvalid, + inbits => recv_inbits, + invalid_transition => recv_invalid_transition, + spw_di => spw_di, + spw_si => spw_si); end generate; - recvfront_sel1: if rximpl = impl_fast generate - recvfront_fast_inst: spwrecvfront_fast - generic map ( - rxchunk => rxchunk ) - port map ( - clk => clk, - rxclk => rxclk, - rxen => recv_rxen, - inact => recv_inact, - inbvalid => recv_inbvalid, - inbits => recv_inbits, - spw_di => spw_di, - spw_si => spw_si ); + recvfront_sel1 : if rximpl = impl_fast generate + recvfront_fast_inst : spwrecvfront_fast + generic map( + rxchunk => rxchunk) + port map( + clk => clk, + rxclk => rxclk, + rxen => recv_rxen, + inact => recv_inact, + inbvalid => recv_inbvalid, + inbits => recv_inbits, + spw_di => spw_di, + spw_si => spw_si); end generate; -- Instantiate RX memory. - rxmem: spwram - generic map ( - abits => rxfifosize_bits, - dbits => 9 ) - port map ( - rclk => clk, - wclk => clk, - ren => '1', - raddr => s_rxfifo_raddr, - rdata => s_rxfifo_rdata, - wen => s_rxfifo_wen, - waddr => s_rxfifo_waddr, - wdata => s_rxfifo_wdata ); + rxmem : spwram + generic map( + abits => rxfifosize_bits, + dbits => 9) + port map( + rclk => clk, + wclk => clk, + ren => '1', + raddr => s_rxfifo_raddr, + rdata => s_rxfifo_rdata, + wen => s_rxfifo_wen, + waddr => s_rxfifo_waddr, + wdata => s_rxfifo_wdata); -- Instantiate TX memory. - txmem: spwram - generic map ( - abits => txfifosize_bits, - dbits => 9 ) - port map ( - rclk => clk, - wclk => clk, - ren => '1', - raddr => s_txfifo_raddr, - rdata => s_txfifo_rdata, - wen => s_txfifo_wen, - waddr => s_txfifo_waddr, - wdata => s_txfifo_wdata ); + txmem : spwram + generic map( + abits => txfifosize_bits, + dbits => 9) + port map( + rclk => clk, + wclk => clk, + ren => '1', + raddr => s_txfifo_raddr, + rdata => s_txfifo_rdata, + wen => s_txfifo_wen, + waddr => s_txfifo_waddr, + wdata => s_txfifo_wdata); -- Combinatorial process - process (r, linko, s_rxfifo_rdata, s_txfifo_rdata, rst, autostart, linkstart, linkdis, - txdivcnt, tick_in, ctrl_in, time_in, txwrite, txflag, txdata, rxread, err_inj_i, err_sel_i) is - variable v: regs_type; - variable v_tmprxroom: unsigned(rxfifosize_bits-1 downto 0); - variable v_tmptxroom: unsigned(txfifosize_bits-1 downto 0); + process(r, linko, s_rxfifo_rdata, s_txfifo_rdata, rst, autostart, linkstart, linkdis, txdivcnt, tick_in, ctrl_in, time_in, txwrite, txflag, txdata, rxread, err_inj_i, err_sel_i) is + variable v : regs_type; + variable v_tmprxroom : unsigned(rxfifosize_bits - 1 downto 0); + variable v_tmptxroom : unsigned(txfifosize_bits - 1 downto 0); begin v := r; v_tmprxroom := to_unsigned(0, v_tmprxroom'length); @@ -406,24 +363,24 @@ begin -- Keep track of whether we are sending and/or receiving a packet. if linko.rxchar = '1' then -- got character - v.rxpacket := not linko.rxflag; + v.rxpacket := not linko.rxflag; end if; if linko.txack = '1' then -- send character - v.txpacket := not s_txfifo_rdata(8); + v.txpacket := not s_txfifo_rdata(8); end if; -- Update RX fifo pointers. if (rxread = '1') and (r.rxfifo_rvalid = '1') then -- read from fifo - v.rxfifo_raddr := std_logic_vector(unsigned(r.rxfifo_raddr) + 1); + v.rxfifo_raddr := std_logic_vector(unsigned(r.rxfifo_raddr) + 1); end if; if r.rxfull = '0' then if (linko.rxchar = '1') or (r.rxeep = '1') then -- write to fifo (received char or pending EEP) - v.rxfifo_waddr := std_logic_vector(unsigned(r.rxfifo_waddr) + 1); + v.rxfifo_waddr := std_logic_vector(unsigned(r.rxfifo_waddr) + 1); end if; - v.rxeep := '0'; + v.rxeep := '0'; end if; -- Keep track of whether the RX fifo contains valid data. @@ -435,22 +392,22 @@ begin v.rxfull := bool_to_logic(v_tmprxroom = 0); v.rxhalff := not v_tmprxroom(v_tmprxroom'high); if v_tmprxroom > 63 then - v.rxroom := (others => '1'); + v.rxroom := (others => '1'); else - v.rxroom := std_logic_vector(v_tmprxroom(5 downto 0)); + v.rxroom := std_logic_vector(v_tmprxroom(5 downto 0)); end if; -- Update TX fifo pointers. if (r.txfifo_rvalid = '1') and ((linko.txack = '1') or (r.txdiscard = '1')) then -- read from fifo - v.txfifo_raddr := std_logic_vector(unsigned(r.txfifo_raddr) + 1); + v.txfifo_raddr := std_logic_vector(unsigned(r.txfifo_raddr) + 1); if s_txfifo_rdata(8) = '1' then v.txdiscard := '0'; -- got EOP/EEP, stop discarding data end if; end if; if (r.txfull = '0') and (txwrite = '1') then -- write to fifo - v.txfifo_waddr := std_logic_vector(unsigned(r.txfifo_waddr) + 1); + v.txfifo_waddr := std_logic_vector(unsigned(r.txfifo_waddr) + 1); end if; -- Keep track of whether the TX fifo contains valid data. @@ -461,11 +418,11 @@ begin v_tmptxroom := unsigned(r.txfifo_raddr) - unsigned(v.txfifo_waddr) - 1; v.txfull := bool_to_logic(v_tmptxroom = 0); v.txhalff := not v_tmptxroom(v_tmptxroom'high); - + -- If the link is lost, set a flag to discard the current packet. if linko.running = '0' then - v.rxeep := v.rxeep or v.rxpacket; -- use new value of rxpacket - v.txdiscard := v.txdiscard or v.txpacket; -- use new value of txpacket + v.rxeep := v.rxeep or v.rxpacket; -- use new value of rxpacket + v.txdiscard := v.txdiscard or v.txpacket; -- use new value of txpacket v.rxpacket := '0'; v.txpacket := '0'; end if; @@ -476,32 +433,32 @@ begin end if; -- Drive control signals to RX fifo. - s_rxfifo_raddr <= v.rxfifo_raddr; -- using new value of rxfifo_raddr - s_rxfifo_wen <= (not r.rxfull) and (linko.rxchar or r.rxeep); - s_rxfifo_waddr <= r.rxfifo_waddr; + s_rxfifo_raddr <= v.rxfifo_raddr; -- using new value of rxfifo_raddr + s_rxfifo_wen <= (not r.rxfull) and (linko.rxchar or r.rxeep); + s_rxfifo_waddr <= r.rxfifo_waddr; if r.rxeep = '1' then - s_rxfifo_wdata <= "100000001"; + s_rxfifo_wdata <= "100000001"; else - s_rxfifo_wdata <= linko.rxflag & linko.rxdata; + s_rxfifo_wdata <= linko.rxflag & linko.rxdata; end if; -- Drive control signals to TX fifo. - s_txfifo_raddr <= v.txfifo_raddr; -- using new value of txfifo_raddr - s_txfifo_wen <= (not r.txfull) and txwrite; - s_txfifo_waddr <= r.txfifo_waddr; - s_txfifo_wdata <= txflag & txdata; + s_txfifo_raddr <= v.txfifo_raddr; -- using new value of txfifo_raddr + s_txfifo_wen <= (not r.txfull) and txwrite; + s_txfifo_waddr <= r.txfifo_waddr; + s_txfifo_wdata <= txflag & txdata; -- Drive inputs to spwlink. - linki.autostart <= autostart; - linki.linkstart <= linkstart; - linki.linkdis <= linkdis; - linki.rxroom <= r.rxroom; - linki.tick_in <= tick_in; - linki.ctrl_in <= ctrl_in; - linki.time_in <= time_in; - linki.txwrite <= r.txfifo_rvalid and not r.txdiscard; - linki.txflag <= s_txfifo_rdata(8); - linki.txdata <= s_txfifo_rdata(7 downto 0); + linki.autostart <= autostart; + linki.linkstart <= linkstart; + linki.linkdis <= linkdis; + linki.rxroom <= r.rxroom; + linki.tick_in <= tick_in; + linki.ctrl_in <= ctrl_in; + linki.time_in <= time_in; + linki.txwrite <= r.txfifo_rvalid and not r.txdiscard; + linki.txflag <= s_txfifo_rdata(8); + linki.txdata <= s_txfifo_rdata(7 downto 0); linki.err_usr_i.err_inj_i <= err_inj_i; linki.err_usr_i.err_sel_i <= err_sel_i; @@ -513,23 +470,23 @@ begin end if; -- Drive outputs. - txrdy <= not r.txfull; - txhalff <= r.txhalff; - tick_out <= linko.tick_out; - ctrl_out <= linko.ctrl_out; - time_out <= linko.time_out; - rxvalid <= r.rxfifo_rvalid; - rxhalff <= r.rxhalff; - rxflag <= s_rxfifo_rdata(8); - rxdata <= s_rxfifo_rdata(7 downto 0); - started <= linko.started; - connecting <= linko.connecting; - running <= linko.running; - errdisc <= linko.errdisc; - errpar <= linko.errpar; - erresc <= linko.erresc; - errcred <= linko.errcred; - err_stat_o <= linko.err_usr_o.err_stat_o; + txrdy <= not r.txfull; + txhalff <= r.txhalff; + tick_out <= linko.tick_out; + ctrl_out <= linko.ctrl_out; + time_out <= linko.time_out; + rxvalid <= r.rxfifo_rvalid; + rxhalff <= r.rxhalff; + rxflag <= s_rxfifo_rdata(8); + rxdata <= s_rxfifo_rdata(7 downto 0); + started <= linko.started; + connecting <= linko.connecting; + running <= linko.running; + errdisc <= linko.errdisc; + errpar <= linko.errpar; + erresc <= linko.erresc; + errcred <= linko.errcred; + err_stat_o <= linko.err_usr_o.err_stat_o; -- Reset. if rst = '1' then @@ -550,7 +507,7 @@ begin end process; -- Update registers. - process (clk) is + process(clk) is begin if rising_edge(clk) then r <= rin; diff --git a/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwxmit.vhd b/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwxmit.vhd index c8a78b2d3..be05a3841 100644 --- a/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwxmit.vhd +++ b/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwxmit.vhd @@ -12,30 +12,24 @@ use work.spwpkg.all; entity spwxmit is - port ( + port( -- System clock. - clk: in std_logic; - + clk : in std_logic; -- Synchronous reset (active-high). - rst: in std_logic; - + rst : in std_logic; -- Scaling factor minus 1, used to scale the system clock into the -- transmission bit rate. The system clock is divided by -- (unsigned(divcnt) + 1). Changing this signal will immediately -- change the transmission rate. - divcnt: in std_logic_vector(7 downto 0); - + divcnt : in std_logic_vector(7 downto 0); -- Input signals from spwlink. - xmiti: in spw_xmit_in_type; - + xmiti : in spw_xmit_in_type; -- Output signals to spwlink. - xmito: out spw_xmit_out_type; - + xmito : out spw_xmit_out_type; -- Data Out signal to SpaceWire bus. - spw_do: out std_logic; - + spw_do : out std_logic; -- Strobe Out signal to SpaceWire bus. - spw_so: out std_logic + spw_so : out std_logic ); end entity spwxmit; @@ -45,61 +39,61 @@ architecture spwxmit_arch of spwxmit is -- Registers type regs_type is record -- tx clock - txclken: std_ulogic; -- high if a bit must be transmitted - txclkcnt: unsigned(7 downto 0); + txclken : std_ulogic; -- high if a bit must be transmitted + txclkcnt : unsigned(7 downto 0); -- output shift register - bitshift: std_logic_vector(12 downto 0); - bitcnt: unsigned(3 downto 0); + bitshift : std_logic_vector(12 downto 0); + bitcnt : unsigned(3 downto 0); -- output signals - out_data: std_ulogic; - out_strobe: std_ulogic; + out_data : std_ulogic; + out_strobe : std_ulogic; -- parity flag - parity: std_ulogic; + parity : std_ulogic; -- pending time tick - pend_tick: std_ulogic; - pend_time: std_logic_vector(7 downto 0); + pend_tick : std_ulogic; + pend_time : std_logic_vector(7 downto 0); -- transmitter mode - allow_fct: std_ulogic; -- allowed to send FCTs - allow_char: std_ulogic; -- allowed to send data and time - sent_null: std_ulogic; -- sent at least one NULL token - sent_fct: std_ulogic; -- sent at least one FCT token + allow_fct : std_ulogic; -- allowed to send FCTs + allow_char : std_ulogic; -- allowed to send data and time + sent_null : std_ulogic; -- sent at least one NULL token + sent_fct : std_ulogic; -- sent at least one FCT token end record; -- Initial state - constant regs_reset: regs_type := ( - txclken => '0', - txclkcnt => "00000000", - bitshift => (others => '0'), - bitcnt => "0000", - out_data => '0', - out_strobe => '0', - parity => '0', - pend_tick => '0', - pend_time => (others => '0'), - allow_fct => '0', - allow_char => '0', - sent_null => '0', - sent_fct => '0' ); + constant regs_reset : regs_type := ( + txclken => '0', + txclkcnt => "00000000", + bitshift => (others => '0'), + bitcnt => "0000", + out_data => '0', + out_strobe => '0', + parity => '0', + pend_tick => '0', + pend_time => (others => '0'), + allow_fct => '0', + allow_char => '0', + sent_null => '0', + sent_fct => '0'); -- Registers - signal r: regs_type := regs_reset; - signal rin: regs_type; + signal r : regs_type := regs_reset; + signal rin : regs_type; begin -- Combinatorial process - process (r, rst, divcnt, xmiti) is - variable v: regs_type; + process(r, rst, divcnt, xmiti) is + variable v : regs_type; begin v := r; -- Generate TX clock. if r.txclkcnt = 0 then - v.txclkcnt := unsigned(divcnt); - v.txclken := '1'; + v.txclkcnt := unsigned(divcnt); + v.txclken := '1'; else - v.txclkcnt := r.txclkcnt - 1; - v.txclken := '0'; + v.txclkcnt := r.txclkcnt - 1; + v.txclken := '0'; end if; if xmiti.txen = '0' then @@ -122,14 +116,13 @@ begin else -- Transmitter enabled. - v.allow_fct := (not xmiti.stnull) and r.sent_null; - + v.allow_fct := (not xmiti.stnull) and r.sent_null; + -- If a char sequence error requested, force allow_char = '1' if (xmiti.err_inj_ch_seq = '1') then - v.allow_char := '1'; - else - v.allow_char := (not xmiti.stnull) and r.sent_null and - (not xmiti.stfct) and r.sent_fct; + v.allow_char := '1'; + else + v.allow_char := (not xmiti.stnull) and r.sent_null and (not xmiti.stfct) and r.sent_fct; end if; -- On tick of transmission clock, put next bit on the output. @@ -140,50 +133,50 @@ begin -- Need to start a new character. if (r.allow_char = '1') and (r.pend_tick = '1') then -- Send Time-Code. - v.out_data := r.parity; + v.out_data := r.parity; v.bitshift(12 downto 5) := r.pend_time; v.bitshift(4 downto 0) := "01111"; - v.bitcnt := to_unsigned(13, v.bitcnt'length); - v.parity := '0'; - v.pend_tick := '0'; + v.bitcnt := to_unsigned(13, v.bitcnt'length); + v.parity := '0'; + v.pend_tick := '0'; elsif (r.allow_fct = '1') and (xmiti.fct_in = '1') then -- Send FCT. - v.out_data := r.parity; - v.bitshift(2 downto 0) := "001"; - v.bitcnt := to_unsigned(3, v.bitcnt'length); - v.parity := '1'; - v.sent_fct := '1'; + v.out_data := r.parity; + v.bitshift(2 downto 0) := "001"; + v.bitcnt := to_unsigned(3, v.bitcnt'length); + v.parity := '1'; + v.sent_fct := '1'; elsif (r.allow_char = '1') and (xmiti.txwrite = '1') then -- Send N-Char. v.bitshift(0) := xmiti.txflag; - v.parity := xmiti.txflag; + v.parity := xmiti.txflag; if xmiti.txflag = '0' then -- Data byte - v.out_data := not r.parity; + v.out_data := not r.parity; v.bitshift(8 downto 1) := xmiti.txdata; - v.bitcnt := to_unsigned(9, v.bitcnt'length); + v.bitcnt := to_unsigned(9, v.bitcnt'length); else -- EOP or EEP - v.out_data := r.parity; + v.out_data := r.parity; v.bitshift(1) := xmiti.txdata(0); v.bitshift(2) := not xmiti.txdata(0); - v.bitcnt := to_unsigned(3, v.bitcnt'length); + v.bitcnt := to_unsigned(3, v.bitcnt'length); end if; else -- Send NULL. - v.out_data := r.parity; + v.out_data := r.parity; -- Parity error injection check if (xmiti.err_inj_par = '1') then - -- Force wrong parity bit in fct portion code - -- It can´t be confused with eop, eep, or another esc. - v.bitshift(6 downto 0) := "0011111"; - -- Escape error injection check + -- Force wrong parity bit in fct portion code + -- It can´t be confused with eop, eep, or another esc. + v.bitshift(6 downto 0) := "0011111"; + -- Escape error injection check elsif (xmiti.err_inj_esc = '1') then - -- Force another esc in fct portion code: esc + esc. - v.bitshift(6 downto 0) := "1110111"; + -- Force another esc in fct portion code: esc + esc. + v.bitshift(6 downto 0) := "1110111"; -- Normal null code else - v.bitshift(6 downto 0) := "0010111"; + v.bitshift(6 downto 0) := "0010111"; end if; v.bitcnt := to_unsigned(7, v.bitcnt'length); v.parity := '0'; @@ -193,10 +186,10 @@ begin else -- Shift next bit to the output. - v.out_data := r.bitshift(0); - v.parity := r.parity xor r.bitshift(0); - v.bitshift(r.bitshift'high-1 downto 0) := r.bitshift(r.bitshift'high downto 1); - v.bitcnt := r.bitcnt - 1; + v.out_data := r.bitshift(0); + v.parity := r.parity xor r.bitshift(0); + v.bitshift(r.bitshift'high - 1 downto 0) := r.bitshift(r.bitshift'high downto 1); + v.bitcnt := r.bitcnt - 1; end if; @@ -225,24 +218,20 @@ begin -- (ready for token) AND (FCTs allowed) AND -- ((characters not allowed) OR (no timecode pending)) AND -- (FCT requested) - if (xmiti.txen = '1') and - (r.txclken = '1') and (r.bitcnt = 0) and (r.allow_fct = '1') and - ((r.allow_char = '0') or (r.pend_tick = '0')) then - xmito.fctack <= xmiti.fct_in; + if (xmiti.txen = '1') and (r.txclken = '1') and (r.bitcnt = 0) and (r.allow_fct = '1') and ((r.allow_char = '0') or (r.pend_tick = '0')) then + xmito.fctack <= xmiti.fct_in; else - xmito.fctack <= '0'; + xmito.fctack <= '0'; end if; -- Set txack high if (transmitter enabled) AND -- (ready for token) AND (characters enabled) AND -- (no timecode pending) AND (no FCT requested) AND -- (character requested) - if (xmiti.txen = '1') and - (r.txclken = '1') and (r.bitcnt = 0) and (r.allow_char = '1') and - (r.pend_tick = '0') and (xmiti.fct_in = '0') then - xmito.txack <= xmiti.txwrite; + if (xmiti.txen = '1') and (r.txclken = '1') and (r.bitcnt = 0) and (r.allow_char = '1') and (r.pend_tick = '0') and (xmiti.fct_in = '0') then + xmito.txack <= xmiti.txwrite; else - xmito.txack <= '0'; + xmito.txack <= '0'; end if; -- Update registers @@ -250,7 +239,7 @@ begin end process; -- Synchronous process - process (clk) is + process(clk) is begin if rising_edge(clk) then @@ -258,8 +247,8 @@ begin r <= rin; -- Drive spacewire output signals - spw_do <= r.out_data; - spw_so <= r.out_strobe; + spw_do <= r.out_data; + spw_so <= r.out_strobe; end if; end process; diff --git a/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwxmit_fast.vhd b/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwxmit_fast.vhd index fe1f9e150..034970e3d 100644 --- a/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwxmit_fast.vhd +++ b/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwxmit_fast.vhd @@ -149,215 +149,208 @@ use work.spwpkg.all; entity spwxmit_fast is - port ( + port( -- System clock. - clk: in std_logic; - + clk : in std_logic; -- Transmit clock. - txclk: in std_logic; - + txclk : in std_logic; -- Synchronous reset (active-high) -- Used asynchronously by fast clock domain (must be glitch-free). - rst: in std_logic; - + rst : in std_logic; -- Scaling factor minus 1, used to scale the system clock into the -- transmission bit rate. The system clock is divided by -- (unsigned(divcnt) + 1). Changing this signal will immediately -- change the transmission rate. - divcnt: in std_logic_vector(7 downto 0); - + divcnt : in std_logic_vector(7 downto 0); -- Input signals from spwlink. - xmiti: in spw_xmit_in_type; - + xmiti : in spw_xmit_in_type; -- Output signals to spwlink. - xmito: out spw_xmit_out_type; - + xmito : out spw_xmit_out_type; -- Data Out signal to SpaceWire bus. - spw_do: out std_logic; - + spw_do : out std_logic; -- Strobe Out signal to SpaceWire bus. - spw_so: out std_logic + spw_so : out std_logic ); -- Turn off FSM extraction to avoid synchronization problems. - attribute FSM_EXTRACT: string; - attribute FSM_EXTRACT of spwxmit_fast: entity is "NO"; + attribute FSM_EXTRACT : string; + attribute FSM_EXTRACT of spwxmit_fast : entity is "NO"; end entity spwxmit_fast; architecture spwxmit_fast_arch of spwxmit_fast is -- Convert boolean to std_logic. - type bool_to_logic_type is array(boolean) of std_ulogic; - constant bool_to_logic: bool_to_logic_type := (false => '0', true => '1'); + type bool_to_logic_type is array (boolean) of std_ulogic; + constant bool_to_logic : bool_to_logic_type := (false => '0', true => '1'); -- Data records passed between clock domains. type token_type is record - tick: std_ulogic; -- send time code - fct: std_ulogic; -- send FCT - fctpiggy: std_ulogic; -- send FCT and N-char - flag: std_ulogic; -- send EOP or EEP - char: std_logic_vector(7 downto 0); -- character or time code + tick : std_ulogic; -- send time code + fct : std_ulogic; -- send FCT + fctpiggy : std_ulogic; -- send FCT and N-char + flag : std_ulogic; -- send EOP or EEP + char : std_logic_vector(7 downto 0); -- character or time code end record; -- Registers in txclk domain type txregs_type is record -- sync to system clock domain - txflip0: std_ulogic; - txflip1: std_ulogic; + txflip0 : std_ulogic; + txflip1 : std_ulogic; -- stage B - b_update: std_ulogic; - b_mux: std_ulogic; - b_txflip: std_ulogic; - b_valid: std_ulogic; - b_token: token_type; + b_update : std_ulogic; + b_mux : std_ulogic; + b_txflip : std_ulogic; + b_valid : std_ulogic; + b_token : token_type; -- stage C - c_update: std_ulogic; - c_busy: std_ulogic; - c_esc: std_ulogic; - c_fct: std_ulogic; - c_bits: std_logic_vector(8 downto 0); + c_update : std_ulogic; + c_busy : std_ulogic; + c_esc : std_ulogic; + c_fct : std_ulogic; + c_bits : std_logic_vector(8 downto 0); -- stage D - d_bits: std_logic_vector(8 downto 0); - d_cnt4: std_ulogic; - d_cnt10: std_ulogic; + d_bits : std_logic_vector(8 downto 0); + d_cnt4 : std_ulogic; + d_cnt10 : std_ulogic; -- stage E - e_valid: std_ulogic; - e_shift: std_logic_vector(9 downto 0); - e_count: std_logic_vector(9 downto 0); - e_parity: std_ulogic; + e_valid : std_ulogic; + e_shift : std_logic_vector(9 downto 0); + e_count : std_logic_vector(9 downto 0); + e_parity : std_ulogic; -- stage F - f_spwdo: std_ulogic; - f_spwso: std_ulogic; + f_spwdo : std_ulogic; + f_spwso : std_ulogic; -- tx clock enable logic - txclken: std_ulogic; - txclkpre: std_ulogic; - txclkcnt: std_logic_vector(7 downto 0); - txclkcy: std_logic_vector(2 downto 0); - txclkdone: std_logic_vector(1 downto 0); - txclkdiv: std_logic_vector(7 downto 0); - txdivnorm: std_ulogic; + txclken : std_ulogic; + txclkpre : std_ulogic; + txclkcnt : std_logic_vector(7 downto 0); + txclkcy : std_logic_vector(2 downto 0); + txclkdone : std_logic_vector(1 downto 0); + txclkdiv : std_logic_vector(7 downto 0); + txdivnorm : std_ulogic; end record; -- Registers in system clock domain type regs_type is record -- sync status to txclk domain - txenreg: std_ulogic; - txdivreg: std_logic_vector(7 downto 0); - txdivnorm: std_ulogic; - txdivtmp: std_logic_vector(1 downto 0); - txdivsafe: std_ulogic; + txenreg : std_ulogic; + txdivreg : std_logic_vector(7 downto 0); + txdivnorm : std_ulogic; + txdivtmp : std_logic_vector(1 downto 0); + txdivsafe : std_ulogic; -- data stream to txclk domain - sysflip0: std_ulogic; - sysflip1: std_ulogic; - token0: token_type; - token1: token_type; - tokmux: std_ulogic; + sysflip0 : std_ulogic; + sysflip1 : std_ulogic; + token0 : token_type; + token1 : token_type; + tokmux : std_ulogic; -- transmitter management - pend_fct: std_ulogic; -- '1' if an outgoing FCT is pending - pend_char: std_ulogic; -- '1' if an outgoing N-Char is pending - pend_data: std_logic_vector(8 downto 0); -- control flag and data bits of pending char - pend_tick: std_ulogic; -- '1' if an outgoing time tick is pending - pend_time: std_logic_vector(7 downto 0); -- data bits of pending time tick - allow_fct: std_ulogic; -- '1' when allowed to send FCTs - allow_char: std_ulogic; -- '1' when allowed to send data and time - sent_fct: std_ulogic; -- '1' when at least one FCT token was sent + pend_fct : std_ulogic; -- '1' if an outgoing FCT is pending + pend_char : std_ulogic; -- '1' if an outgoing N-Char is pending + pend_data : std_logic_vector(8 downto 0); -- control flag and data bits of pending char + pend_tick : std_ulogic; -- '1' if an outgoing time tick is pending + pend_time : std_logic_vector(7 downto 0); -- data bits of pending time tick + allow_fct : std_ulogic; -- '1' when allowed to send FCTs + allow_char : std_ulogic; -- '1' when allowed to send data and time + sent_fct : std_ulogic; -- '1' when at least one FCT token was sent end record; -- Initial state of system clock domain - constant token_reset: token_type := ( - tick => '0', - fct => '0', - fctpiggy => '0', - flag => '0', - char => (others => '0') ); - constant regs_reset: regs_type := ( - txenreg => '0', - txdivreg => (others => '0'), - txdivnorm => '0', - txdivtmp => "00", - txdivsafe => '0', - sysflip0 => '0', - sysflip1 => '0', - token0 => token_reset, - token1 => token_reset, - tokmux => '0', - pend_fct => '0', - pend_char => '0', - pend_data => (others => '0'), - pend_tick => '0', - pend_time => (others => '0'), - allow_fct => '0', - allow_char => '0', - sent_fct => '0' ); + constant token_reset : token_type := ( + tick => '0', + fct => '0', + fctpiggy => '0', + flag => '0', + char => (others => '0')); + constant regs_reset : regs_type := ( + txenreg => '0', + txdivreg => (others => '0'), + txdivnorm => '0', + txdivtmp => "00", + txdivsafe => '0', + sysflip0 => '0', + sysflip1 => '0', + token0 => token_reset, + token1 => token_reset, + tokmux => '0', + pend_fct => '0', + pend_char => '0', + pend_data => (others => '0'), + pend_tick => '0', + pend_time => (others => '0'), + allow_fct => '0', + allow_char => '0', + sent_fct => '0'); -- Signals that are re-synchronized from system clock to txclk domain. type synctx_type is record - rstn: std_ulogic; - sysflip0: std_ulogic; - sysflip1: std_ulogic; - txen: std_ulogic; - txdivsafe: std_ulogic; + rstn : std_ulogic; + sysflip0 : std_ulogic; + sysflip1 : std_ulogic; + txen : std_ulogic; + txdivsafe : std_ulogic; end record; -- Signals that are re-synchronized from txclk to system clock domain. type syncsys_type is record - txflip0: std_ulogic; - txflip1: std_ulogic; + txflip0 : std_ulogic; + txflip1 : std_ulogic; end record; -- Registers - signal rtx: txregs_type; - signal rtxin: txregs_type; - signal r: regs_type := regs_reset; - signal rin: regs_type; + signal rtx : txregs_type; + signal rtxin : txregs_type; + signal r : regs_type := regs_reset; + signal rin : regs_type; -- Synchronized signals after crossing clock domains. - signal synctx: synctx_type; - signal syncsys: syncsys_type; + signal synctx : synctx_type; + signal syncsys : syncsys_type; -- Output flip-flops - signal s_spwdo: std_logic; - signal s_spwso: std_logic; + signal s_spwdo : std_logic; + signal s_spwso : std_logic; -- Force use of IOB flip-flops - attribute IOB: string; - attribute IOB of s_spwdo: signal is "TRUE"; - attribute IOB of s_spwso: signal is "TRUE"; + attribute IOB : string; + attribute IOB of s_spwdo : signal is "TRUE"; + attribute IOB of s_spwso : signal is "TRUE"; begin -- Reset synchronizer for txclk domain. - synctx_rst: syncdff - port map ( clk => txclk, rst => rst, di => '1', do => synctx.rstn ); + synctx_rst : syncdff + port map(clk => txclk, rst => rst, di => '1', do => synctx.rstn); -- Synchronize signals from system clock domain to txclk domain. - synctx_sysflip0: syncdff - port map ( clk => txclk, rst => rst, di => r.sysflip0, do => synctx.sysflip0 ); - synctx_sysflip1: syncdff - port map ( clk => txclk, rst => rst, di => r.sysflip1, do => synctx.sysflip1 ); - synctx_txen: syncdff - port map ( clk => txclk, rst => rst, di => r.txenreg, do => synctx.txen ); - synctx_txdivsafe: syncdff - port map ( clk => txclk, rst => rst, di => r.txdivsafe, do => synctx.txdivsafe ); + synctx_sysflip0 : syncdff + port map(clk => txclk, rst => rst, di => r.sysflip0, do => synctx.sysflip0); + synctx_sysflip1 : syncdff + port map(clk => txclk, rst => rst, di => r.sysflip1, do => synctx.sysflip1); + synctx_txen : syncdff + port map(clk => txclk, rst => rst, di => r.txenreg, do => synctx.txen); + synctx_txdivsafe : syncdff + port map(clk => txclk, rst => rst, di => r.txdivsafe, do => synctx.txdivsafe); -- Synchronize signals from txclk domain to system clock domain. - syncsys_txflip0: syncdff - port map ( clk => clk, rst => rst, di => rtx.txflip0, do => syncsys.txflip0 ); - syncsys_txflip1: syncdff - port map ( clk => clk, rst => rst, di => rtx.txflip1, do => syncsys.txflip1 ); + syncsys_txflip0 : syncdff + port map(clk => clk, rst => rst, di => rtx.txflip0, do => syncsys.txflip0); + syncsys_txflip1 : syncdff + port map(clk => clk, rst => rst, di => rtx.txflip1, do => syncsys.txflip1); -- Drive SpaceWire output signals - spw_do <= s_spwdo; - spw_so <= s_spwso; + spw_do <= s_spwdo; + spw_so <= s_spwso; -- Combinatorial process - process (r, rtx, rst, divcnt, xmiti, synctx, syncsys) is - variable v: regs_type; - variable vtx: txregs_type; - variable v_needtoken: std_ulogic; - variable v_havetoken: std_ulogic; - variable v_token: token_type; + process(r, rtx, rst, divcnt, xmiti, synctx, syncsys) is + variable v : regs_type; + variable vtx : txregs_type; + variable v_needtoken : std_ulogic; + variable v_havetoken : std_ulogic; + variable v_token : token_type; begin v := r; vtx := rtx; @@ -406,45 +399,42 @@ begin -- Time-codes are broken into two tokens: ESC + char. -- Enable c_esc on the first pass of a NULL or a time-code. - vtx.c_esc := (rtx.b_token.tick or (not rtx.b_valid)) and - (not rtx.c_esc); + vtx.c_esc := (rtx.b_token.tick or (not rtx.b_valid)) and (not rtx.c_esc); -- Enable c_fct on the first pass of an FCT and on -- the second pass of a NULL (also the first pass, but c_esc -- is stronger than c_fct). - vtx.c_fct := (rtx.b_token.fct and (not rtx.c_busy)) or - (not rtx.b_valid); + vtx.c_fct := (rtx.b_token.fct and (not rtx.c_busy)) or (not rtx.b_valid); -- Enable c_busy on the first pass of a NULL or a time-code -- or a piggy-backed FCT. This will tell stage B that we are -- not done yet. - vtx.c_busy := (rtx.b_token.tick or (not rtx.b_valid) or - rtx.b_token.fctpiggy) and (not rtx.c_busy); + vtx.c_busy := (rtx.b_token.tick or (not rtx.b_valid) or rtx.b_token.fctpiggy) and (not rtx.c_busy); if rtx.b_token.flag = '1' then if rtx.b_token.char(0) = '0' then -- prepare to send EOP - vtx.c_bits := "000000101"; -- EOP = P101 + vtx.c_bits := "000000101"; -- EOP = P101 else -- prepare to send EEP - vtx.c_bits := "000000011"; -- EEP = P110 + vtx.c_bits := "000000011"; -- EEP = P110 end if; else -- prepare to send data char - vtx.c_bits := rtx.b_token.char & '0'; + vtx.c_bits := rtx.b_token.char & '0'; end if; end if; -- Stage D: Prepare to transmit FCT, ESC, or the stuff from stage C. if rtx.c_esc = '1' then -- prepare to send ESC - vtx.d_bits := "000000111"; -- ESC = P111 - vtx.d_cnt4 := '1'; -- 3 bits + implicit parity bit + vtx.d_bits := "000000111"; -- ESC = P111 + vtx.d_cnt4 := '1'; -- 3 bits + implicit parity bit vtx.d_cnt10 := '0'; elsif rtx.c_fct = '1' then -- prepare to send FCT - vtx.d_bits := "000000001"; -- FCT = P100 - vtx.d_cnt4 := '1'; -- 3 bits + implicit parity bit + vtx.d_bits := "000000001"; -- FCT = P100 + vtx.d_cnt4 := '1'; -- 3 bits + implicit parity bit vtx.d_cnt10 := '0'; else -- send the stuff from stage C. @@ -457,11 +447,11 @@ begin if rtx.txclken = '1' then if rtx.e_count(0) = '1' then -- reload shift register; output parity bit - vtx.e_valid := '1'; + vtx.e_valid := '1'; vtx.e_shift(vtx.e_shift'high downto 1) := rtx.d_bits; - vtx.e_shift(0) := not (rtx.e_parity xor rtx.d_bits(0)); - vtx.e_count := rtx.d_cnt10 & "00000" & rtx.d_cnt4 & "000"; - vtx.e_parity := rtx.d_bits(0); + vtx.e_shift(0) := not (rtx.e_parity xor rtx.d_bits(0)); + vtx.e_count := rtx.d_cnt10 & "00000" & rtx.d_cnt4 & "000"; + vtx.e_parity := rtx.d_bits(0); else -- shift bits to output; update parity bit vtx.e_shift := '0' & rtx.e_shift(rtx.e_shift'high downto 1); @@ -493,15 +483,15 @@ begin vtx.txclkcnt(5 downto 4) := std_logic_vector(unsigned(rtx.txclkcnt(5 downto 4)) - unsigned(rtx.txclkcy(1 downto 1))); vtx.txclkcnt(7 downto 6) := std_logic_vector(unsigned(rtx.txclkcnt(7 downto 6)) - unsigned(rtx.txclkcy(2 downto 2))); -- propagate carry in blocks of two bits - vtx.txclkcy(0) := bool_to_logic(rtx.txclkcnt(1 downto 0) = "00"); - vtx.txclkcy(1) := rtx.txclkcy(0) and bool_to_logic(rtx.txclkcnt(3 downto 2) = "00"); - vtx.txclkcy(2) := rtx.txclkcy(1) and bool_to_logic(rtx.txclkcnt(5 downto 4) = "00"); + vtx.txclkcy(0) := bool_to_logic(rtx.txclkcnt(1 downto 0) = "00"); + vtx.txclkcy(1) := rtx.txclkcy(0) and bool_to_logic(rtx.txclkcnt(3 downto 2) = "00"); + vtx.txclkcy(2) := rtx.txclkcy(1) and bool_to_logic(rtx.txclkcnt(5 downto 4) = "00"); -- detect value 2 in counter - vtx.txclkdone(0) := bool_to_logic(rtx.txclkcnt(3 downto 0) = "0010"); - vtx.txclkdone(1) := bool_to_logic(rtx.txclkcnt(7 downto 4) = "0000"); + vtx.txclkdone(0) := bool_to_logic(rtx.txclkcnt(3 downto 0) = "0010"); + vtx.txclkdone(1) := bool_to_logic(rtx.txclkcnt(7 downto 4) = "0000"); -- trigger txclken - vtx.txclken := (rtx.txclkdone(0) and rtx.txclkdone(1)) or rtx.txclkpre; - vtx.txclkpre := (not rtx.txdivnorm) and ((not rtx.txclkpre) or (not rtx.txclkdiv(0))); + vtx.txclken := (rtx.txclkdone(0) and rtx.txclkdone(1)) or rtx.txclkpre; + vtx.txclkpre := (not rtx.txdivnorm) and ((not rtx.txclkpre) or (not rtx.txclkdiv(0))); -- reload counter if rtx.txclken = '1' then vtx.txclkcnt := rtx.txclkdiv; @@ -517,21 +507,21 @@ begin -- Transmitter disabled. if synctx.txen = '0' then - vtx.txflip0 := '0'; - vtx.txflip1 := '0'; - vtx.b_update := '0'; - vtx.b_mux := '0'; - vtx.b_valid := '0'; - vtx.c_update := '0'; - vtx.c_busy := '1'; - vtx.c_esc := '1'; -- need to send 2nd part of NULL - vtx.c_fct := '1'; - vtx.d_bits := "000000111"; -- ESC = P111 - vtx.d_cnt4 := '1'; -- 3 bits + implicit parity bit - vtx.d_cnt10 := '0'; - vtx.e_valid := '0'; - vtx.e_parity := '0'; - vtx.e_count := (0 => '1', others => '0'); + vtx.txflip0 := '0'; + vtx.txflip1 := '0'; + vtx.b_update := '0'; + vtx.b_mux := '0'; + vtx.b_valid := '0'; + vtx.c_update := '0'; + vtx.c_busy := '1'; + vtx.c_esc := '1'; -- need to send 2nd part of NULL + vtx.c_fct := '1'; + vtx.d_bits := "000000111"; -- ESC = P111 + vtx.d_cnt4 := '1'; -- 3 bits + implicit parity bit + vtx.d_cnt10 := '0'; + vtx.e_valid := '0'; + vtx.e_parity := '0'; + vtx.e_count := (0 => '1', others => '0'); end if; -- Reset. @@ -548,7 +538,7 @@ begin -- ---- SYSTEM CLOCK DOMAIN ---- -- Hold divcnt and txen for use by txclk domain. - v.txdivtmp := std_logic_vector(unsigned(r.txdivtmp) - 1); + v.txdivtmp := std_logic_vector(unsigned(r.txdivtmp) - 1); if r.txdivtmp = "00" then if r.txdivsafe = '0' then -- Latch the current value of divcnt and txen. @@ -569,26 +559,26 @@ begin -- Pass falling edge of txen signal as soon as possible. if xmiti.txen = '0' then - v.txenreg := '0'; + v.txenreg := '0'; end if; -- Store requests for FCT transmission. if xmiti.fct_in = '1' and r.allow_fct = '1' then - v.pend_fct := '1'; + v.pend_fct := '1'; end if; if xmiti.txen = '0' then -- Transmitter disabled; reset state. - v.sysflip0 := '0'; - v.sysflip1 := '0'; - v.tokmux := '0'; - v.pend_fct := '0'; - v.pend_char := '0'; - v.pend_tick := '0'; - v.allow_fct := '0'; - v.allow_char := '0'; - v.sent_fct := '0'; + v.sysflip0 := '0'; + v.sysflip1 := '0'; + v.tokmux := '0'; + v.pend_fct := '0'; + v.pend_char := '0'; + v.pend_tick := '0'; + v.allow_fct := '0'; + v.allow_char := '0'; + v.sent_fct := '0'; else @@ -606,23 +596,23 @@ begin -- Prepare new token. if r.allow_char = '1' and r.pend_tick = '1' then -- prepare to send time code - v_token.tick := '1'; - v_token.fct := '0'; + v_token.tick := '1'; + v_token.fct := '0'; v_token.fctpiggy := '0'; - v_token.flag := '0'; - v_token.char := r.pend_time; - v_havetoken := '1'; + v_token.flag := '0'; + v_token.char := r.pend_time; + v_havetoken := '1'; if v_needtoken = '1' then v.pend_tick := '0'; end if; else if r.allow_fct = '1' and (xmiti.fct_in = '1' or r.pend_fct = '1') then -- prepare to send FCT - v_token.fct := '1'; - v_havetoken := '1'; + v_token.fct := '1'; + v_havetoken := '1'; if v_needtoken = '1' then - v.pend_fct := '0'; - v.sent_fct := '1'; + v.pend_fct := '0'; + v.sent_fct := '1'; end if; end if; if r.allow_char = '1' and r.pend_char = '1' then @@ -630,9 +620,9 @@ begin -- Note: it is possible to send an FCT and an N-Char -- together by enabling the fctpiggy flag. v_token.fctpiggy := v_token.fct; - v_token.flag := r.pend_data(8); - v_token.char := r.pend_data(7 downto 0); - v_havetoken := '1'; + v_token.flag := r.pend_data(8); + v_token.char := r.pend_data(7 downto 0); + v_havetoken := '1'; if v_needtoken = '1' then v.pend_char := '0'; end if; @@ -643,15 +633,15 @@ begin if v_havetoken = '1' then if r.tokmux = '0' then if r.sysflip0 = syncsys.txflip0 then - v.sysflip0 := not r.sysflip0; - v.token0 := v_token; - v.tokmux := '1'; + v.sysflip0 := not r.sysflip0; + v.token0 := v_token; + v.tokmux := '1'; end if; else if r.sysflip1 = syncsys.txflip1 then - v.sysflip1 := not r.sysflip1; - v.token1 := v_token; - v.tokmux := '0'; + v.sysflip1 := not r.sysflip1; + v.token1 := v_token; + v.tokmux := '0'; end if; end if; end if; @@ -662,8 +652,8 @@ begin -- Store request for data transmission. if xmiti.txwrite = '1' and r.allow_char = '1' and r.pend_char = '0' then - v.pend_char := '1'; - v.pend_data := xmiti.txflag & xmiti.txdata; + v.pend_char := '1'; + v.pend_data := xmiti.txflag & xmiti.txdata; end if; -- Store requests for time tick transmission. @@ -684,33 +674,31 @@ begin -- Set fctack high if (FCT requested) and (FCTs allowed) AND -- (no FCT pending) - xmito.fctack <= xmiti.fct_in and xmiti.txen and r.allow_fct and - (not r.pend_fct); + xmito.fctack <= xmiti.fct_in and xmiti.txen and r.allow_fct and (not r.pend_fct); -- Set txack high if (character requested) AND (characters allowed) AND -- (no character pending) - xmito.txack <= xmiti.txwrite and xmiti.txen and r.allow_char and - (not r.pend_char); + xmito.txack <= xmiti.txwrite and xmiti.txen and r.allow_char and (not r.pend_char); -- Update registers. - rin <= v; - rtxin <= vtx; + rin <= v; + rtxin <= vtx; end process; -- Synchronous process in txclk domain - process (txclk) is + process(txclk) is begin if rising_edge(txclk) then -- drive spacewire output signals s_spwdo <= rtx.f_spwdo; s_spwso <= rtx.f_spwso; -- update registers - rtx <= rtxin; + rtx <= rtxin; end if; end process; -- Synchronous process in system clock domain - process (clk) is + process(clk) is begin if rising_edge(clk) then -- update registers diff --git a/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/spwc_spacewire_channel_top.vhd b/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/spwc_spacewire_channel_top.vhd index 9fad1246f..0e16e6581 100644 --- a/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/spwc_spacewire_channel_top.vhd +++ b/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/spwc_spacewire_channel_top.vhd @@ -17,265 +17,266 @@ use work.spwc_errinj_pkg.all; use work.spwc_leds_controller_pkg.all; entity spwc_spacewire_channel_top is - generic( - g_SPWC_TESTBENCH_MODE : std_logic := '0' - ); - port( - reset_i : in std_logic := '0'; -- -- reset_sink.reset - clk_100_i : in std_logic := '0'; -- -- clock_sink_100mhz.clk - clk_200_i : in std_logic := '0'; -- -- clock_sink_200mhz.clk - spw_lvds_p_data_in_i : in std_logic := '0'; -- -- conduit_end_spacewire_lvds.spw_lvds_p_data_in_signal - spw_lvds_n_data_in_i : in std_logic := '0'; -- -- .spw_lvds_n_data_in_signal - spw_lvds_p_strobe_in_i : in std_logic := '0'; -- -- .spw_lvds_p_strobe_in_signal - spw_lvds_n_strobe_in_i : in std_logic := '0'; -- -- .spw_lvds_n_strobe_in_signal - spw_lvds_p_data_out_o : out std_logic; -- -- .spw_lvds_p_data_out_signal - spw_lvds_n_data_out_o : out std_logic; -- -- .spw_lvds_n_data_out_signal - spw_lvds_p_strobe_out_o : out std_logic; -- -- .spw_lvds_p_strobe_out_signal - spw_lvds_n_strobe_out_o : out std_logic; -- -- .spw_lvds_n_strobe_out_signal - spw_rx_enable_i : in std_logic := '0'; -- -- conduit_end_spacewire_enable.spw_rx_enable_signal - spw_tx_enable_i : in std_logic := '0'; -- -- .spw_tx_enable_signal - spw_red_status_led_o : out std_logic; -- -- conduit_end_spacewire_leds.spw_red_status_led_signal - spw_green_status_led_o : out std_logic; -- -- .spw_green_status_led_signal - spw_link_command_autostart_i : in std_logic := '0'; -- -- conduit_end_spacewire_channel.spw_link_command_autostart_signal - spw_link_command_linkstart_i : in std_logic := '0'; -- -- .spw_link_command_linkstart_signal - spw_link_command_linkdis_i : in std_logic := '0'; -- -- .spw_link_command_linkdis_signal - spw_link_command_txdivcnt_i : in std_logic_vector(7 downto 0) := (others => '0'); -- .spw_link_command_txdivcnt_signal - spw_timecode_tx_tick_in_i : in std_logic := '0'; -- -- .spw_timecode_tx_tick_in_signal - spw_timecode_tx_ctrl_in_i : in std_logic_vector(1 downto 0) := (others => '0'); -- .spw_timecode_tx_ctrl_in_signal - spw_timecode_tx_time_in_i : in std_logic_vector(5 downto 0) := (others => '0'); -- .spw_timecode_tx_time_in_signal - spw_data_rx_command_rxread_i : in std_logic := '0'; -- -- .spw_data_rx_command_rxread_signal - spw_data_tx_command_txwrite_i : in std_logic := '0'; -- -- .spw_data_tx_command_txwrite_signal - spw_data_tx_command_txflag_i : in std_logic := '0'; -- -- .spw_data_tx_command_txflag_signal - spw_data_tx_command_txdata_i : in std_logic_vector(7 downto 0) := (others => '0'); -- .spw_data_tx_command_txdata_signal - spw_errinj_ctrl_start_errinj_i : in std_logic := '0'; -- -- .spw_errinj_ctrl_start_errinj_signal - spw_errinj_ctrl_reset_errinj_i : in std_logic := '0'; -- -- .spw_errinj_ctrl_reset_errinj_signal - spw_errinj_ctrl_errinj_code_i : in std_logic_vector(3 downto 0) := (others => '0'); -- .spw_errinj_ctrl_errinj_code_signal - spw_link_status_started_o : out std_logic; -- -- .spw_link_status_started_signal - spw_link_status_connecting_o : out std_logic; -- -- .spw_link_status_connecting_signal - spw_link_status_running_o : out std_logic; -- -- .spw_link_status_running_signal - spw_link_error_errdisc_o : out std_logic; -- -- .spw_link_error_errdisc_signal - spw_link_error_errpar_o : out std_logic; -- -- .spw_link_error_errpar_signal - spw_link_error_erresc_o : out std_logic; -- -- .spw_link_error_erresc_signal - spw_link_error_errcred_o : out std_logic; -- -- .spw_link_error_errcred_signal - spw_timecode_rx_tick_out_o : out std_logic; -- -- .spw_timecode_rx_tick_out_signal - spw_timecode_rx_ctrl_out_o : out std_logic_vector(1 downto 0); -- -- .spw_timecode_rx_ctrl_out_signal - spw_timecode_rx_time_out_o : out std_logic_vector(5 downto 0); -- -- .spw_timecode_rx_time_out_signal - spw_data_rx_status_rxvalid_o : out std_logic; -- -- .spw_data_rx_status_rxvalid_signal - spw_data_rx_status_rxhalff_o : out std_logic; -- -- .spw_data_rx_status_rxhalff_signal - spw_data_rx_status_rxflag_o : out std_logic; -- -- .spw_data_rx_status_rxflag_signal - spw_data_rx_status_rxdata_o : out std_logic_vector(7 downto 0); -- -- .spw_data_rx_status_rxdata_signal - spw_data_tx_status_txrdy_o : out std_logic; -- -- .spw_data_tx_status_txrdy_signal - spw_data_tx_status_txhalff_o : out std_logic; -- -- .spw_data_tx_status_txhalff_signal - spw_errinj_ctrl_errinj_busy_o : out std_logic; -- -- .spw_errinj_ctrl_errinj_busy_signal - spw_errinj_ctrl_errinj_ready_o : out std_logic --- -- .spw_errinj_ctrl_errinj_ready_signal - ); + generic( + g_SPWC_TESTBENCH_MODE : std_logic := '0' + ); + port( + reset_i : in std_logic := '0'; -- -- reset_sink.reset + clk_100_i : in std_logic := '0'; -- -- clock_sink_100mhz.clk + clk_200_i : in std_logic := '0'; -- -- clock_sink_200mhz.clk + spw_lvds_p_data_in_i : in std_logic := '0'; -- -- conduit_end_spacewire_lvds.spw_lvds_p_data_in_signal + spw_lvds_n_data_in_i : in std_logic := '0'; -- -- .spw_lvds_n_data_in_signal + spw_lvds_p_strobe_in_i : in std_logic := '0'; -- -- .spw_lvds_p_strobe_in_signal + spw_lvds_n_strobe_in_i : in std_logic := '0'; -- -- .spw_lvds_n_strobe_in_signal + spw_lvds_p_data_out_o : out std_logic; -- -- .spw_lvds_p_data_out_signal + spw_lvds_n_data_out_o : out std_logic; -- -- .spw_lvds_n_data_out_signal + spw_lvds_p_strobe_out_o : out std_logic; -- -- .spw_lvds_p_strobe_out_signal + spw_lvds_n_strobe_out_o : out std_logic; -- -- .spw_lvds_n_strobe_out_signal + spw_rx_enable_i : in std_logic := '0'; -- -- conduit_end_spacewire_enable.spw_rx_enable_signal + spw_tx_enable_i : in std_logic := '0'; -- -- .spw_tx_enable_signal + spw_red_status_led_o : out std_logic; -- -- conduit_end_spacewire_leds.spw_red_status_led_signal + spw_green_status_led_o : out std_logic; -- -- .spw_green_status_led_signal + spw_link_command_enable_i : in std_logic := '0'; -- -- conduit_end_spacewire_channel.spw_link_command_enable_signal + spw_link_command_autostart_i : in std_logic := '0'; -- -- .spw_link_command_autostart_signal + spw_link_command_linkstart_i : in std_logic := '0'; -- -- .spw_link_command_linkstart_signal + spw_link_command_linkdis_i : in std_logic := '0'; -- -- .spw_link_command_linkdis_signal + spw_link_command_txdivcnt_i : in std_logic_vector(7 downto 0) := (others => '0'); -- .spw_link_command_txdivcnt_signal + spw_timecode_tx_tick_in_i : in std_logic := '0'; -- -- .spw_timecode_tx_tick_in_signal + spw_timecode_tx_ctrl_in_i : in std_logic_vector(1 downto 0) := (others => '0'); -- .spw_timecode_tx_ctrl_in_signal + spw_timecode_tx_time_in_i : in std_logic_vector(5 downto 0) := (others => '0'); -- .spw_timecode_tx_time_in_signal + spw_data_rx_command_rxread_i : in std_logic := '0'; -- -- .spw_data_rx_command_rxread_signal + spw_data_tx_command_txwrite_i : in std_logic := '0'; -- -- .spw_data_tx_command_txwrite_signal + spw_data_tx_command_txflag_i : in std_logic := '0'; -- -- .spw_data_tx_command_txflag_signal + spw_data_tx_command_txdata_i : in std_logic_vector(7 downto 0) := (others => '0'); -- .spw_data_tx_command_txdata_signal + spw_errinj_ctrl_start_errinj_i : in std_logic := '0'; -- -- .spw_errinj_ctrl_start_errinj_signal + spw_errinj_ctrl_reset_errinj_i : in std_logic := '0'; -- -- .spw_errinj_ctrl_reset_errinj_signal + spw_errinj_ctrl_errinj_code_i : in std_logic_vector(3 downto 0) := (others => '0'); -- .spw_errinj_ctrl_errinj_code_signal + spw_link_status_started_o : out std_logic; -- -- .spw_link_status_started_signal + spw_link_status_connecting_o : out std_logic; -- -- .spw_link_status_connecting_signal + spw_link_status_running_o : out std_logic; -- -- .spw_link_status_running_signal + spw_link_error_errdisc_o : out std_logic; -- -- .spw_link_error_errdisc_signal + spw_link_error_errpar_o : out std_logic; -- -- .spw_link_error_errpar_signal + spw_link_error_erresc_o : out std_logic; -- -- .spw_link_error_erresc_signal + spw_link_error_errcred_o : out std_logic; -- -- .spw_link_error_errcred_signal + spw_timecode_rx_tick_out_o : out std_logic; -- -- .spw_timecode_rx_tick_out_signal + spw_timecode_rx_ctrl_out_o : out std_logic_vector(1 downto 0); -- -- .spw_timecode_rx_ctrl_out_signal + spw_timecode_rx_time_out_o : out std_logic_vector(5 downto 0); -- -- .spw_timecode_rx_time_out_signal + spw_data_rx_status_rxvalid_o : out std_logic; -- -- .spw_data_rx_status_rxvalid_signal + spw_data_rx_status_rxhalff_o : out std_logic; -- -- .spw_data_rx_status_rxhalff_signal + spw_data_rx_status_rxflag_o : out std_logic; -- -- .spw_data_rx_status_rxflag_signal + spw_data_rx_status_rxdata_o : out std_logic_vector(7 downto 0); -- -- .spw_data_rx_status_rxdata_signal + spw_data_tx_status_txrdy_o : out std_logic; -- -- .spw_data_tx_status_txrdy_signal + spw_data_tx_status_txhalff_o : out std_logic; -- -- .spw_data_tx_status_txhalff_signal + spw_errinj_ctrl_errinj_busy_o : out std_logic; -- -- .spw_errinj_ctrl_errinj_busy_signal + spw_errinj_ctrl_errinj_ready_o : out std_logic --- -- .spw_errinj_ctrl_errinj_ready_signal + ); end entity spwc_spacewire_channel_top; architecture rtl of spwc_spacewire_channel_top is - -- Alias -- + -- Alias -- - -- Basic Alias - alias a_avs_clock is clk_100_i; - alias a_spw_clock is clk_200_i; - alias a_reset is reset_i; + -- Basic Alias + alias a_avs_clock is clk_100_i; + alias a_spw_clock is clk_200_i; + alias a_reset is reset_i; - -- Constants -- + -- Constants -- - -- Signals -- + -- Signals -- - -- SpaceWire Codec Clock Synchronization Signals (200 MHz) - signal s_spw_codec_link_command_spw : t_spwc_codec_link_command; - signal s_spw_codec_link_status_spw : t_spwc_codec_link_status; - signal s_spw_codec_link_error_spw : t_spwc_codec_link_error; - signal s_spw_codec_timecode_rx_spw : t_spwc_codec_timecode_rx; - signal s_spw_codec_data_rx_status_spw : t_spwc_codec_data_rx_status; - signal s_spw_codec_data_tx_status_spw : t_spwc_codec_data_tx_status; - signal s_spw_codec_err_inj_status_spw : t_spwc_codec_err_inj_status; - signal s_spw_codec_timecode_tx_spw : t_spwc_codec_timecode_tx; - signal s_spw_codec_data_rx_command_spw : t_spwc_codec_data_rx_command; - signal s_spw_codec_data_tx_command_spw : t_spwc_codec_data_tx_command; - signal s_spw_codec_err_inj_command_spw : t_spwc_codec_err_inj_command; + -- SpaceWire Codec Clock Synchronization Signals (200 MHz) + signal s_spw_codec_link_command_spw : t_spwc_codec_link_command; + signal s_spw_codec_link_status_spw : t_spwc_codec_link_status; + signal s_spw_codec_link_error_spw : t_spwc_codec_link_error; + signal s_spw_codec_timecode_rx_spw : t_spwc_codec_timecode_rx; + signal s_spw_codec_data_rx_status_spw : t_spwc_codec_data_rx_status; + signal s_spw_codec_data_tx_status_spw : t_spwc_codec_data_tx_status; + signal s_spw_codec_err_inj_status_spw : t_spwc_codec_err_inj_status; + signal s_spw_codec_timecode_tx_spw : t_spwc_codec_timecode_tx; + signal s_spw_codec_data_rx_command_spw : t_spwc_codec_data_rx_command; + signal s_spw_codec_data_tx_command_spw : t_spwc_codec_data_tx_command; + signal s_spw_codec_err_inj_command_spw : t_spwc_codec_err_inj_command; - -- Spacewire Error Injection Controller Signals - signal s_spw_errinj_controller_control : t_spwc_errinj_controller_control; - signal s_spw_errinj_controller_status : t_spwc_errinj_controller_status; + -- Spacewire Error Injection Controller Signals + signal s_spw_errinj_controller_control : t_spwc_errinj_controller_control; + signal s_spw_errinj_controller_status : t_spwc_errinj_controller_status; - -- SpaceWire Codec Data-Strobe Signals - signal s_spw_codec_ds_encoding_rx : t_spwc_codec_ds_encoding_rx; - signal s_spw_codec_ds_encoding_tx : t_spwc_codec_ds_encoding_tx; + -- SpaceWire Codec Data-Strobe Signals + signal s_spw_codec_ds_encoding_rx : t_spwc_codec_ds_encoding_rx; + signal s_spw_codec_ds_encoding_tx : t_spwc_codec_ds_encoding_tx; - -- SpaceWire LVDS Data-Strobe Signals - signal s_spw_logical_data_in : std_logic; - signal s_spw_logical_strobe_in : std_logic; - signal s_spw_logical_data_out : std_logic; - signal s_spw_logical_strobe_out : std_logic; + -- SpaceWire LVDS Data-Strobe Signals + signal s_spw_logical_data_in : std_logic; + signal s_spw_logical_strobe_in : std_logic; + signal s_spw_logical_data_out : std_logic; + signal s_spw_logical_strobe_out : std_logic; - -- SpaceWire Leds Controller Signals - signal s_spw_leds_control : t_spwc_spw_leds_control; + -- SpaceWire Leds Controller Signals + signal s_spw_leds_control : t_spwc_spw_leds_control; begin - -- Entities Instantiation -- - - -- SpaceWire Codec Clock Domain Synchronization Instantiation - spwc_clk_synchronization_top_inst : entity work.spwc_clk_synchronization_top - port map( - clk_avs_i => a_avs_clock, - clk_spw_i => a_spw_clock, - rst_i => a_reset, - spw_codec_link_command_avs_i.autostart => spw_link_command_autostart_i, - spw_codec_link_command_avs_i.linkstart => spw_link_command_linkstart_i, - spw_codec_link_command_avs_i.linkdis => spw_link_command_linkdis_i, - spw_codec_link_command_avs_i.txdivcnt => spw_link_command_txdivcnt_i, - spw_codec_timecode_tx_avs_i.tick_in => spw_timecode_tx_tick_in_i, - spw_codec_timecode_tx_avs_i.ctrl_in => spw_timecode_tx_ctrl_in_i, - spw_codec_timecode_tx_avs_i.time_in => spw_timecode_tx_time_in_i, - spw_codec_data_rx_command_avs_i.rxread => spw_data_rx_command_rxread_i, - spw_codec_data_tx_command_avs_i.txwrite => spw_data_tx_command_txwrite_i, - spw_codec_data_tx_command_avs_i.txflag => spw_data_tx_command_txflag_i, - spw_codec_data_tx_command_avs_i.txdata => spw_data_tx_command_txdata_i, - spw_errinj_ctrl_control_avs_i.start_errinj => spw_errinj_ctrl_start_errinj_i, - spw_errinj_ctrl_control_avs_i.reset_errinj => spw_errinj_ctrl_reset_errinj_i, - spw_errinj_ctrl_control_avs_i.errinj_code => spw_errinj_ctrl_errinj_code_i, - spw_codec_link_status_spw_i => s_spw_codec_link_status_spw, - spw_codec_link_error_spw_i => s_spw_codec_link_error_spw, - spw_codec_timecode_rx_spw_i => s_spw_codec_timecode_rx_spw, - spw_codec_data_rx_status_spw_i => s_spw_codec_data_rx_status_spw, - spw_codec_data_tx_status_spw_i => s_spw_codec_data_tx_status_spw, - spw_errinj_ctrl_status_spw_i => s_spw_errinj_controller_status, - spw_codec_link_status_avs_o.started => spw_link_status_started_o, - spw_codec_link_status_avs_o.connecting => spw_link_status_connecting_o, - spw_codec_link_status_avs_o.running => spw_link_status_running_o, - spw_codec_link_error_avs_o.errdisc => spw_link_error_errdisc_o, - spw_codec_link_error_avs_o.errpar => spw_link_error_errpar_o, - spw_codec_link_error_avs_o.erresc => spw_link_error_erresc_o, - spw_codec_link_error_avs_o.errcred => spw_link_error_errcred_o, - spw_codec_timecode_rx_avs_o.tick_out => spw_timecode_rx_tick_out_o, - spw_codec_timecode_rx_avs_o.ctrl_out => spw_timecode_rx_ctrl_out_o, - spw_codec_timecode_rx_avs_o.time_out => spw_timecode_rx_time_out_o, - spw_codec_data_rx_status_avs_o.rxvalid => spw_data_rx_status_rxvalid_o, - spw_codec_data_rx_status_avs_o.rxhalff => spw_data_rx_status_rxhalff_o, - spw_codec_data_rx_status_avs_o.rxflag => spw_data_rx_status_rxflag_o, - spw_codec_data_rx_status_avs_o.rxdata => spw_data_rx_status_rxdata_o, - spw_codec_data_tx_status_avs_o.txrdy => spw_data_tx_status_txrdy_o, - spw_codec_data_tx_status_avs_o.txhalff => spw_data_tx_status_txhalff_o, - spw_errinj_ctrl_status_avs_o.errinj_busy => spw_errinj_ctrl_errinj_busy_o, - spw_errinj_ctrl_status_avs_o.errinj_ready => spw_errinj_ctrl_errinj_ready_o, - spw_codec_link_command_spw_o => s_spw_codec_link_command_spw, - spw_codec_timecode_tx_spw_o => s_spw_codec_timecode_tx_spw, - spw_codec_data_rx_command_spw_o => s_spw_codec_data_rx_command_spw, - spw_codec_data_tx_command_spw_o => s_spw_codec_data_tx_command_spw, - spw_errinj_ctrl_control_spw_o => s_spw_errinj_controller_control - ); - - -- SpaceWire Error Injection Controller Instantiation - spwc_errinj_controller_ent_inst : entity work.spwc_errinj_controller_ent - port map( - clk_i => a_spw_clock, - rst_i => a_reset, - errinj_controller_control_i => s_spw_errinj_controller_control, - spw_codec_link_status_i => s_spw_codec_link_status_spw, - spw_codec_err_inj_status_i => s_spw_codec_err_inj_status_spw, - errinj_controller_status_o => s_spw_errinj_controller_status, - spw_codec_err_inj_command_o => s_spw_codec_err_inj_command_spw - ); - - -- SpaceWire Codec Instantiation - spwc_codec_ent_inst : entity work.spwc_codec_ent - port map( - clk_spw_i => a_spw_clock, - rst_i => a_reset, - spw_codec_link_command_i => s_spw_codec_link_command_spw, - spw_codec_ds_encoding_rx_i => s_spw_codec_ds_encoding_rx, - spw_codec_timecode_tx_i => s_spw_codec_timecode_tx_spw, - spw_codec_data_rx_command_i => s_spw_codec_data_rx_command_spw, - spw_codec_data_tx_command_i => s_spw_codec_data_tx_command_spw, - spw_codec_err_inj_command_i => s_spw_codec_err_inj_command_spw, - spw_codec_link_status_o => s_spw_codec_link_status_spw, - spw_codec_ds_encoding_tx_o => s_spw_codec_ds_encoding_tx, - spw_codec_link_error_o => s_spw_codec_link_error_spw, - spw_codec_timecode_rx_o => s_spw_codec_timecode_rx_spw, - spw_codec_data_rx_status_o => s_spw_codec_data_rx_status_spw, - spw_codec_data_tx_status_o => s_spw_codec_data_tx_status_spw, - spw_codec_err_inj_status_o => s_spw_codec_err_inj_status_spw - ); - - -- SpaceWire Data-Strobe Testbench Generate - g_spwc_ds_testbench : if (g_SPWC_TESTBENCH_MODE = '1') generate - - s_spw_logical_data_in <= spw_lvds_p_data_in_i; - s_spw_logical_strobe_in <= spw_lvds_p_strobe_in_i; - spw_lvds_p_data_out_o <= s_spw_logical_data_out; - spw_lvds_p_strobe_out_o <= s_spw_logical_strobe_out; - spw_lvds_n_data_out_o <= '0'; - spw_lvds_n_strobe_out_o <= '0'; - - end generate g_spwc_ds_testbench; - - -- SpaceWire Data-Strobe ALTIOBUF Generate - g_spwc_ds_altiobuff : if (g_SPWC_TESTBENCH_MODE = '0') generate - - -- SpaceWire Data-Strobe Rx Diferential Inputs ALTIOBUF Instantiation - spwc_spw_rx_altiobuf_inst : entity work.spwc_spw_rx_altiobuf - port map( - datain(0) => spw_lvds_p_data_in_i, - datain(1) => spw_lvds_p_strobe_in_i, - datain_b(0) => spw_lvds_n_data_in_i, - datain_b(1) => spw_lvds_n_strobe_in_i, - dataout(0) => s_spw_logical_data_in, - dataout(1) => s_spw_logical_strobe_in - ); - - -- SpaceWire Data-Strobe Tx Diferential Outputs ALTIOBUF Instantiation - spwc_spw_tx_altiobuf_inst : entity work.spwc_spw_tx_altiobuf - port map( - datain(0) => s_spw_logical_data_out, - datain(1) => s_spw_logical_strobe_out, - dataout(0) => spw_lvds_p_data_out_o, - dataout(1) => spw_lvds_p_strobe_out_o, - dataout_b(0) => spw_lvds_n_data_out_o, - dataout_b(1) => spw_lvds_n_strobe_out_o - ); - - end generate g_spwc_ds_altiobuff; - - -- SpaceWire LEDs Controller Instantiation - spwc_leds_controller_ent_inst : entity work.spwc_leds_controller_ent - port map( - clk_i => a_spw_clock, - rst_i => a_reset, - leds_channel_status_i.link_status_running => s_spw_codec_link_status_spw.running, - leds_channel_status_i.data_rx_command_rxread => s_spw_codec_data_rx_command_spw.rxread, - leds_channel_status_i.data_tx_command_txwrite => s_spw_codec_data_tx_command_spw.txwrite, - leds_control_o => s_spw_leds_control - ); - - -- SpaceWire LEDs Outputs ALTIOBUF Instantiation - spwc_leds_out_altiobuf_inst : entity work.spwc_leds_out_altiobuf - port map( - datain(1) => s_spw_leds_control.red_status_led, - datain(0) => s_spw_leds_control.green_status_led, - dataout(1) => spw_red_status_led_o, - dataout(0) => spw_green_status_led_o - ); - - -- Signals Assignments -- - - -- Spacewire Data-Strobe Input Signals Assignments - s_spw_codec_ds_encoding_rx.spw_di <= ('0') when (a_reset = '1') - else (s_spw_logical_data_in) when (spw_rx_enable_i = '1') - else ('0'); - s_spw_codec_ds_encoding_rx.spw_si <= ('0') when (a_reset = '1') - else (s_spw_logical_strobe_in) when (spw_rx_enable_i = '1') - else ('0'); - - -- Spacewire Data-Strobe Output Signals Assignments - s_spw_logical_data_out <= ('0') when (a_reset = '1') - else (s_spw_codec_ds_encoding_tx.spw_do) when (spw_tx_enable_i = '1') - else ('0'); - s_spw_logical_strobe_out <= ('0') when (a_reset = '1') - else (s_spw_codec_ds_encoding_tx.spw_so) when (spw_tx_enable_i = '1') - else ('0'); + -- Entities Instantiation -- + + -- SpaceWire Codec Clock Domain Synchronization Instantiation + spwc_clk_synchronization_top_inst : entity work.spwc_clk_synchronization_top + port map( + clk_avs_i => a_avs_clock, + clk_spw_i => a_spw_clock, + rst_i => a_reset, + spw_codec_link_command_avs_i.autostart => spw_link_command_autostart_i, + spw_codec_link_command_avs_i.linkstart => spw_link_command_linkstart_i, + spw_codec_link_command_avs_i.linkdis => spw_link_command_linkdis_i, + spw_codec_link_command_avs_i.txdivcnt => spw_link_command_txdivcnt_i, + spw_codec_timecode_tx_avs_i.tick_in => spw_timecode_tx_tick_in_i, + spw_codec_timecode_tx_avs_i.ctrl_in => spw_timecode_tx_ctrl_in_i, + spw_codec_timecode_tx_avs_i.time_in => spw_timecode_tx_time_in_i, + spw_codec_data_rx_command_avs_i.rxread => spw_data_rx_command_rxread_i, + spw_codec_data_tx_command_avs_i.txwrite => spw_data_tx_command_txwrite_i, + spw_codec_data_tx_command_avs_i.txflag => spw_data_tx_command_txflag_i, + spw_codec_data_tx_command_avs_i.txdata => spw_data_tx_command_txdata_i, + spw_errinj_ctrl_control_avs_i.start_errinj => spw_errinj_ctrl_start_errinj_i, + spw_errinj_ctrl_control_avs_i.reset_errinj => spw_errinj_ctrl_reset_errinj_i, + spw_errinj_ctrl_control_avs_i.errinj_code => spw_errinj_ctrl_errinj_code_i, + spw_codec_link_status_spw_i => s_spw_codec_link_status_spw, + spw_codec_link_error_spw_i => s_spw_codec_link_error_spw, + spw_codec_timecode_rx_spw_i => s_spw_codec_timecode_rx_spw, + spw_codec_data_rx_status_spw_i => s_spw_codec_data_rx_status_spw, + spw_codec_data_tx_status_spw_i => s_spw_codec_data_tx_status_spw, + spw_errinj_ctrl_status_spw_i => s_spw_errinj_controller_status, + spw_codec_link_status_avs_o.started => spw_link_status_started_o, + spw_codec_link_status_avs_o.connecting => spw_link_status_connecting_o, + spw_codec_link_status_avs_o.running => spw_link_status_running_o, + spw_codec_link_error_avs_o.errdisc => spw_link_error_errdisc_o, + spw_codec_link_error_avs_o.errpar => spw_link_error_errpar_o, + spw_codec_link_error_avs_o.erresc => spw_link_error_erresc_o, + spw_codec_link_error_avs_o.errcred => spw_link_error_errcred_o, + spw_codec_timecode_rx_avs_o.tick_out => spw_timecode_rx_tick_out_o, + spw_codec_timecode_rx_avs_o.ctrl_out => spw_timecode_rx_ctrl_out_o, + spw_codec_timecode_rx_avs_o.time_out => spw_timecode_rx_time_out_o, + spw_codec_data_rx_status_avs_o.rxvalid => spw_data_rx_status_rxvalid_o, + spw_codec_data_rx_status_avs_o.rxhalff => spw_data_rx_status_rxhalff_o, + spw_codec_data_rx_status_avs_o.rxflag => spw_data_rx_status_rxflag_o, + spw_codec_data_rx_status_avs_o.rxdata => spw_data_rx_status_rxdata_o, + spw_codec_data_tx_status_avs_o.txrdy => spw_data_tx_status_txrdy_o, + spw_codec_data_tx_status_avs_o.txhalff => spw_data_tx_status_txhalff_o, + spw_errinj_ctrl_status_avs_o.errinj_busy => spw_errinj_ctrl_errinj_busy_o, + spw_errinj_ctrl_status_avs_o.errinj_ready => spw_errinj_ctrl_errinj_ready_o, + spw_codec_link_command_spw_o => s_spw_codec_link_command_spw, + spw_codec_timecode_tx_spw_o => s_spw_codec_timecode_tx_spw, + spw_codec_data_rx_command_spw_o => s_spw_codec_data_rx_command_spw, + spw_codec_data_tx_command_spw_o => s_spw_codec_data_tx_command_spw, + spw_errinj_ctrl_control_spw_o => s_spw_errinj_controller_control + ); + + -- SpaceWire Error Injection Controller Instantiation + spwc_errinj_controller_ent_inst : entity work.spwc_errinj_controller_ent + port map( + clk_i => a_spw_clock, + rst_i => a_reset, + errinj_controller_control_i => s_spw_errinj_controller_control, + spw_codec_link_status_i => s_spw_codec_link_status_spw, + spw_codec_err_inj_status_i => s_spw_codec_err_inj_status_spw, + errinj_controller_status_o => s_spw_errinj_controller_status, + spw_codec_err_inj_command_o => s_spw_codec_err_inj_command_spw + ); + + -- SpaceWire Codec Instantiation + spwc_codec_ent_inst : entity work.spwc_codec_ent + port map( + clk_spw_i => a_spw_clock, + rst_i => a_reset, + spw_codec_link_command_i => s_spw_codec_link_command_spw, + spw_codec_ds_encoding_rx_i => s_spw_codec_ds_encoding_rx, + spw_codec_timecode_tx_i => s_spw_codec_timecode_tx_spw, + spw_codec_data_rx_command_i => s_spw_codec_data_rx_command_spw, + spw_codec_data_tx_command_i => s_spw_codec_data_tx_command_spw, + spw_codec_err_inj_command_i => s_spw_codec_err_inj_command_spw, + spw_codec_link_status_o => s_spw_codec_link_status_spw, + spw_codec_ds_encoding_tx_o => s_spw_codec_ds_encoding_tx, + spw_codec_link_error_o => s_spw_codec_link_error_spw, + spw_codec_timecode_rx_o => s_spw_codec_timecode_rx_spw, + spw_codec_data_rx_status_o => s_spw_codec_data_rx_status_spw, + spw_codec_data_tx_status_o => s_spw_codec_data_tx_status_spw, + spw_codec_err_inj_status_o => s_spw_codec_err_inj_status_spw + ); + + -- SpaceWire Data-Strobe Testbench Generate + g_spwc_ds_testbench : if (g_SPWC_TESTBENCH_MODE = '1') generate + + s_spw_logical_data_in <= spw_lvds_p_data_in_i; + s_spw_logical_strobe_in <= spw_lvds_p_strobe_in_i; + spw_lvds_p_data_out_o <= s_spw_logical_data_out; + spw_lvds_p_strobe_out_o <= s_spw_logical_strobe_out; + spw_lvds_n_data_out_o <= '0'; + spw_lvds_n_strobe_out_o <= '0'; + + end generate g_spwc_ds_testbench; + + -- SpaceWire Data-Strobe ALTIOBUF Generate + g_spwc_ds_altiobuff : if (g_SPWC_TESTBENCH_MODE = '0') generate + + -- SpaceWire Data-Strobe Rx Diferential Inputs ALTIOBUF Instantiation + spwc_spw_rx_altiobuf_inst : entity work.spwc_spw_rx_altiobuf + port map( + datain(0) => spw_lvds_p_data_in_i, + datain(1) => spw_lvds_p_strobe_in_i, + datain_b(0) => spw_lvds_n_data_in_i, + datain_b(1) => spw_lvds_n_strobe_in_i, + dataout(0) => s_spw_logical_data_in, + dataout(1) => s_spw_logical_strobe_in + ); + + -- SpaceWire Data-Strobe Tx Diferential Outputs ALTIOBUF Instantiation + spwc_spw_tx_altiobuf_inst : entity work.spwc_spw_tx_altiobuf + port map( + datain(0) => s_spw_logical_data_out, + datain(1) => s_spw_logical_strobe_out, + dataout(0) => spw_lvds_p_data_out_o, + dataout(1) => spw_lvds_p_strobe_out_o, + dataout_b(0) => spw_lvds_n_data_out_o, + dataout_b(1) => spw_lvds_n_strobe_out_o + ); + + end generate g_spwc_ds_altiobuff; + + -- SpaceWire LEDs Controller Instantiation + spwc_leds_controller_ent_inst : entity work.spwc_leds_controller_ent + port map( + clk_i => a_spw_clock, + rst_i => a_reset, + leds_channel_status_i.link_status_running => s_spw_codec_link_status_spw.running, + leds_channel_status_i.data_rx_command_rxread => s_spw_codec_data_rx_command_spw.rxread, + leds_channel_status_i.data_tx_command_txwrite => s_spw_codec_data_tx_command_spw.txwrite, + leds_control_o => s_spw_leds_control + ); + + -- SpaceWire LEDs Outputs ALTIOBUF Instantiation + spwc_leds_out_altiobuf_inst : entity work.spwc_leds_out_altiobuf + port map( + datain(1) => s_spw_leds_control.red_status_led, + datain(0) => s_spw_leds_control.green_status_led, + dataout(1) => spw_red_status_led_o, + dataout(0) => spw_green_status_led_o + ); + + -- Signals Assignments -- + + -- Spacewire Data-Strobe Input Signals Assignments + s_spw_codec_ds_encoding_rx.spw_di <= ('0') when (a_reset = '1') + else (s_spw_logical_data_in) when ((spw_rx_enable_i = '1') and (spw_link_command_enable_i = '1')) + else ('0'); + s_spw_codec_ds_encoding_rx.spw_si <= ('0') when (a_reset = '1') + else (s_spw_logical_strobe_in) when ((spw_rx_enable_i = '1') and (spw_link_command_enable_i = '1')) + else ('0'); + + -- Spacewire Data-Strobe Output Signals Assignments + s_spw_logical_data_out <= ('0') when (a_reset = '1') + else (s_spw_codec_ds_encoding_tx.spw_do) when ((spw_tx_enable_i = '1') and (spw_link_command_enable_i = '1')) + else ('0'); + s_spw_logical_strobe_out <= ('0') when (a_reset = '1') + else (s_spw_codec_ds_encoding_tx.spw_so) when ((spw_tx_enable_i = '1') and (spw_link_command_enable_i = '1')) + else ('0'); end architecture rtl; -- of spwc_spacewire_channel_top diff --git a/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel_hw.tcl b/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel_hw.tcl index 783f776c9..302b68edb 100644 --- a/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel_hw.tcl +++ b/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel_hw.tcl @@ -4,7 +4,7 @@ # -# SpaceWire_Channel "SpaceWire_Channel" v1.4 +# SpaceWire_Channel "SpaceWire_Channel" v1.5 # rfranca 2020.06.30.17:45:51 # # @@ -20,7 +20,7 @@ package require -exact qsys 16.1 # set_module_property DESCRIPTION "" set_module_property NAME SpaceWire_Channel -set_module_property VERSION 1.4 +set_module_property VERSION 1.5 set_module_property INTERNAL false set_module_property OPAQUE_ADDRESS_MAP true set_module_property AUTHOR rfranca @@ -287,6 +287,7 @@ set_interface_property conduit_end_spacewire_channel PORT_NAME_MAP "" set_interface_property conduit_end_spacewire_channel CMSIS_SVD_VARIABLES "" set_interface_property conduit_end_spacewire_channel SVD_ADDRESS_GROUP "" +add_interface_port conduit_end_spacewire_channel spw_link_command_enable_i spw_link_command_enable_signal Input 1 add_interface_port conduit_end_spacewire_channel spw_link_command_autostart_i spw_link_command_autostart_signal Input 1 add_interface_port conduit_end_spacewire_channel spw_link_command_linkstart_i spw_link_command_linkstart_signal Input 1 add_interface_port conduit_end_spacewire_channel spw_link_command_linkdis_i spw_link_command_linkdis_signal Input 1 diff --git a/FPGA_Developments/SpaceWire_Channel/Development/Testbench/SpaceWire_Channel.cr.mti b/FPGA_Developments/SpaceWire_Channel/Development/Testbench/SpaceWire_Channel.cr.mti index 1940b4b4e..f58c65264 100644 --- a/FPGA_Developments/SpaceWire_Channel/Development/Testbench/SpaceWire_Channel.cr.mti +++ b/FPGA_Developments/SpaceWire_Channel/Development/Testbench/SpaceWire_Channel.cr.mti @@ -1,4 +1,4 @@ -../SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_tx_timecode_ent.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_tx_timecode_ent.vhd +../SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_tx_timecode_ent.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_tx_timecode_ent.vhd Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 -- Loading package STANDARD -- Loading package TEXTIO @@ -10,7 +10,7 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct -- Compiling architecture RTL of spwc_clk_synchronization_tx_timecode_ent -- Loading entity spwc_timecode_dc_fifo -} {} {}} ../SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecv.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecv.vhd +} {} {}} ../SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecv.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecv.vhd Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 -- Loading package STANDARD -- Loading package TEXTIO @@ -30,7 +30,7 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct -- Compiling entity spwstream -- Compiling architecture spwstream_arch of spwstream -} {} {}} ../SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_status_ent.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_status_ent.vhd +} {} {}} ../SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_status_ent.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_status_ent.vhd Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 -- Loading package STANDARD -- Loading package TEXTIO @@ -53,7 +53,7 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct -- Compiling entity spwrecvfront_fast -- Compiling architecture spwrecvfront_arch of spwrecvfront_fast -} {} {}} ../SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwlink.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwlink.vhd +} {} {}} ../SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwlink.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwlink.vhd Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 -- Loading package STANDARD -- Loading package TEXTIO @@ -63,7 +63,7 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct -- Compiling entity spwlink -- Compiling architecture spwlink_arch of spwlink -} {} {}} ../SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwram.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwram.vhd +} {} {}} ../SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwram.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwram.vhd Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 -- Loading package STANDARD -- Loading package TEXTIO @@ -72,7 +72,7 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct -- Compiling entity spwram -- Compiling architecture spwram_arch of spwram -} {} {}} ../Testbench/testbench_top.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/Testbench/testbench_top.vhd +} {} {}} ../Testbench/testbench_top.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/Testbench/testbench_top.vhd Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 -- Loading package STANDARD -- Loading package TEXTIO @@ -87,7 +87,7 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct -- Loading entity spwc_spacewire_channel_top -- Loading entity spwstream -} {} {}} ../Testbench/testbench_synchronization_top.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/Testbench/testbench_synchronization_top.vhd +} {} {}} ../Testbench/testbench_synchronization_top.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/Testbench/testbench_synchronization_top.vhd Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 -- Loading package STANDARD -- Loading package TEXTIO @@ -109,7 +109,7 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct -- Loading package std_logic_1164 -- Compiling package spwpkg -} {} {}} ../SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_rx_data_ent.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_rx_data_ent.vhd +} {} {}} ../SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_rx_data_ent.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_rx_data_ent.vhd Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 -- Loading package STANDARD -- Loading package TEXTIO @@ -143,7 +143,7 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct -- Compiling entity config_avs_stimuli -- Compiling architecture RTL of config_avs_stimuli -} {} {}} ../SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecvfront_generic.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecvfront_generic.vhd +} {} {}} ../SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecvfront_generic.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecvfront_generic.vhd Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 -- Loading package STANDARD -- Loading package TEXTIO @@ -174,7 +174,7 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct -- Compiling entity spwrecv -- Compiling architecture spwrecv_arch of spwrecv -} {} {}} ../SpaceWire_Channel/SPW_CODEC/altera_ip/altiobuf/spwc_spw_tx_altiobuf/spwc_spw_tx_altiobuf.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/altera_ip/altiobuf/spwc_spw_tx_altiobuf/spwc_spw_tx_altiobuf.vhd +} {} {}} ../SpaceWire_Channel/SPW_CODEC/altera_ip/altiobuf/spwc_spw_tx_altiobuf/spwc_spw_tx_altiobuf.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/altera_ip/altiobuf/spwc_spw_tx_altiobuf/spwc_spw_tx_altiobuf.vhd Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 -- Loading package STANDARD -- Loading package TEXTIO @@ -184,7 +184,7 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct -- Compiling entity spwc_spw_tx_altiobuf -- Compiling architecture RTL of spwc_spw_tx_altiobuf -} {} {}} ../SpaceWire_Channel/SPW_CODEC/spwc_codec.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spwc_codec.vhd +} {} {}} ../SpaceWire_Channel/SPW_CODEC/spwc_codec.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spwc_codec.vhd Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 -- Loading package STANDARD -- Loading package TEXTIO @@ -196,7 +196,7 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct -- Compiling architecture rtl of spwc_codec_ent -- Loading entity spwstream -} {} {}} ../SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwxmit.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwxmit.vhd +} {} {}} ../SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwxmit.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwxmit.vhd Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 -- Loading package STANDARD -- Loading package TEXTIO @@ -206,7 +206,7 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct -- Compiling entity spwxmit -- Compiling architecture spwxmit_arch of spwxmit -} {} {}} ../SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_commands_ent.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_commands_ent.vhd +} {} {}} ../SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_commands_ent.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_commands_ent.vhd Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 -- Loading package STANDARD -- Loading package TEXTIO @@ -219,7 +219,7 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct -- Compiling architecture RTL of spwc_clk_synchronization_commands_ent -- Loading entity spwc_command_dc_fifo -} {} {}} ../SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spwc_data_dc_fifo/spwc_data_dc_fifo.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spwc_data_dc_fifo/spwc_data_dc_fifo.vhd +} {} {}} ../SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spwc_data_dc_fifo/spwc_data_dc_fifo.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spwc_data_dc_fifo/spwc_data_dc_fifo.vhd Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 -- Loading package STANDARD -- Loading package TEXTIO @@ -263,7 +263,7 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct -- Compiling entity spwram -- Compiling architecture spwram_arch of spwram -} {} {}} ../SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/streamtest.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/streamtest.vhd +} {} {}} ../SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/streamtest.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/streamtest.vhd Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 -- Loading package STANDARD -- Loading package TEXTIO @@ -273,7 +273,7 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct -- Compiling entity streamtest -- Compiling architecture streamtest_arch of streamtest -} {} {}} ../SpaceWire_Channel/SPW_ERRINJ/spwc_errinj_controller_ent.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_ERRINJ/spwc_errinj_controller_ent.vhd +} {} {}} ../SpaceWire_Channel/SPW_ERRINJ/spwc_errinj_controller_ent.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_ERRINJ/spwc_errinj_controller_ent.vhd Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 -- Loading package STANDARD -- Loading package TEXTIO @@ -285,7 +285,7 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct -- Compiling entity spwc_errinj_controller_ent -- Compiling architecture RTL of spwc_errinj_controller_ent -} {} {}} ../SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_rx_timecode_ent.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_rx_timecode_ent.vhd +} {} {}} ../SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_rx_timecode_ent.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_rx_timecode_ent.vhd Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 -- Loading package STANDARD -- Loading package TEXTIO @@ -306,7 +306,7 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct -- Compiling entity spwrecvfront_generic -- Compiling architecture spwrecvfront_arch of spwrecvfront_generic -} {} {}} ../SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwxmit_fast.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwxmit_fast.vhd +} {} {}} ../SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwxmit_fast.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwxmit_fast.vhd Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 -- Loading package STANDARD -- Loading package TEXTIO @@ -326,7 +326,7 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct -- Compiling entity spwxmit -- Compiling architecture spwxmit_arch of spwxmit -} {} {}} ../SpaceWire_Channel/SPW_ERRINJ/spwc_errinj_pkg.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_ERRINJ/spwc_errinj_pkg.vhd +} {} {}} ../SpaceWire_Channel/SPW_ERRINJ/spwc_errinj_pkg.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_ERRINJ/spwc_errinj_pkg.vhd Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 -- Loading package STANDARD -- Loading package TEXTIO @@ -358,7 +358,7 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct -- Compiling architecture RTL of spwc_clk_synchronization_status_ent -- Loading entity spwc_status_dc_fifo -} {} {}} ../SpaceWire_Channel/SPW_LEDS_CONTROLLER/spwc_leds_controller_pkg.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_LEDS_CONTROLLER/spwc_leds_controller_pkg.vhd +} {} {}} ../SpaceWire_Channel/SPW_LEDS_CONTROLLER/spwc_leds_controller_pkg.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_LEDS_CONTROLLER/spwc_leds_controller_pkg.vhd Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 -- Loading package STANDARD -- Loading package TEXTIO @@ -368,7 +368,7 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct -- Compiling package body spwc_leds_controller_pkg -- Loading package spwc_leds_controller_pkg -} {} {}} ../SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spwc_command_dc_fifo/spwc_command_dc_fifo.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spwc_command_dc_fifo/spwc_command_dc_fifo.vhd +} {} {}} ../SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spwc_command_dc_fifo/spwc_command_dc_fifo.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spwc_command_dc_fifo/spwc_command_dc_fifo.vhd Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 -- Loading package STANDARD -- Loading package TEXTIO @@ -376,17 +376,18 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct -- Compiling entity spwc_command_dc_fifo -- Compiling architecture SYN of spwc_command_dc_fifo -} {} {}} ../SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwerr.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwerr.vhd +} {} {}} ../SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwerr.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwerr.vhd Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 -- Loading package STANDARD -- Loading package TEXTIO -- Loading package std_logic_1164 -- Loading package NUMERIC_STD +-- Loading package MATH_REAL -- Loading package spwpkg -- Compiling entity spwerr -- Compiling architecture spwerr_arch of spwerr -} {} {}} ../SpaceWire_Channel/SPW_LEDS_CONTROLLER/altera_ip/altiobuf/spwc_leds_out_altiobuf/spwc_leds_out_altiobuf.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_LEDS_CONTROLLER/altera_ip/altiobuf/spwc_leds_out_altiobuf/spwc_leds_out_altiobuf.vhd +} {} {}} ../SpaceWire_Channel/SPW_LEDS_CONTROLLER/altera_ip/altiobuf/spwc_leds_out_altiobuf/spwc_leds_out_altiobuf.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_LEDS_CONTROLLER/altera_ip/altiobuf/spwc_leds_out_altiobuf/spwc_leds_out_altiobuf.vhd Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 -- Loading package STANDARD -- Loading package TEXTIO @@ -420,7 +421,7 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct -- Compiling entity streamtest -- Compiling architecture streamtest_arch of streamtest -} {} {}} ../SpaceWire_Channel/spwc_spacewire_channel_top.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/spwc_spacewire_channel_top.vhd +} {} {}} ../SpaceWire_Channel/spwc_spacewire_channel_top.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/spwc_spacewire_channel_top.vhd Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 -- Loading package STANDARD -- Loading package TEXTIO @@ -440,7 +441,7 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct -- Loading entity spwc_leds_controller_ent -- Loading entity spwc_leds_out_altiobuf -} {} {}} ../SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/syncdff.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/syncdff.vhd +} {} {}} ../SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/syncdff.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/syncdff.vhd Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 -- Loading package STANDARD -- Loading package TEXTIO @@ -448,7 +449,7 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct -- Compiling entity syncdff -- Compiling architecture syncdff_arch of syncdff -} {} {}} ../Testbench/config_spw_stimuli.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/Testbench/config_spw_stimuli.vhd +} {} {}} ../Testbench/config_spw_stimuli.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/Testbench/config_spw_stimuli.vhd Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 -- Loading package STANDARD -- Loading package TEXTIO @@ -459,7 +460,7 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct -- Compiling entity config_spw_stimuli -- Compiling architecture RTL of config_spw_stimuli -} {} {}} ../Testbench/config_avs_stimuli.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/Testbench/config_avs_stimuli.vhd +} {} {}} ../Testbench/config_avs_stimuli.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/Testbench/config_avs_stimuli.vhd Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 -- Loading package STANDARD -- Loading package TEXTIO @@ -482,7 +483,7 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct -- Compiling architecture RTL of spwc_clk_synchronization_rx_data_ent -- Loading entity spwc_data_dc_fifo -} {} {}} ../SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_tx_data_ent.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_tx_data_ent.vhd +} {} {}} ../SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_tx_data_ent.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_tx_data_ent.vhd Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 -- Loading package STANDARD -- Loading package TEXTIO @@ -504,7 +505,7 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct -- Compiling entity spwxmit_fast -- Compiling architecture spwxmit_fast_arch of spwxmit_fast -} {} {}} ../SpaceWire_Channel/SPW_LEDS_CONTROLLER/spwc_leds_controller_ent.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_LEDS_CONTROLLER/spwc_leds_controller_ent.vhd +} {} {}} ../SpaceWire_Channel/SPW_LEDS_CONTROLLER/spwc_leds_controller_ent.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_LEDS_CONTROLLER/spwc_leds_controller_ent.vhd Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 -- Loading package STANDARD -- Loading package TEXTIO @@ -526,7 +527,7 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct -- Compiling architecture RTL of spwc_clk_synchronization_commands_ent -- Loading entity spwc_command_dc_fifo -} {} {}} ../SpaceWire_Channel/SPW_CODEC/spwc_codec_pkg.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spwc_codec_pkg.vhd +} {} {}} ../SpaceWire_Channel/SPW_CODEC/spwc_codec_pkg.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spwc_codec_pkg.vhd Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 -- Loading package STANDARD -- Loading package TEXTIO @@ -535,7 +536,7 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct -- Loading package spwpkg -- Compiling package spwc_codec_pkg -} {} {}} ../SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwstream.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwstream.vhd +} {} {}} ../SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwstream.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwstream.vhd Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 -- Loading package STANDARD -- Loading package TEXTIO @@ -545,7 +546,7 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct -- Compiling entity spwstream -- Compiling architecture spwstream_arch of spwstream -} {} {}} ../SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spwc_timecode_dc_fifo/spwc_timecode_dc_fifo.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spwc_timecode_dc_fifo/spwc_timecode_dc_fifo.vhd +} {} {}} ../SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spwc_timecode_dc_fifo/spwc_timecode_dc_fifo.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spwc_timecode_dc_fifo/spwc_timecode_dc_fifo.vhd Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 -- Loading package STANDARD -- Loading package TEXTIO @@ -553,7 +554,7 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct -- Compiling entity spwc_timecode_dc_fifo -- Compiling architecture SYN of spwc_timecode_dc_fifo -} {} {}} ../SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_top.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_top.vhd +} {} {}} ../SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_top.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_top.vhd Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 -- Loading package STANDARD -- Loading package TEXTIO @@ -571,7 +572,7 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct -- Loading entity spwc_clk_synchronization_tx_timecode_ent -- Loading entity spwc_clk_synchronization_rx_timecode_ent -} {} {}} ../SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecvfront_fast.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecvfront_fast.vhd +} {} {}} ../SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecvfront_fast.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecvfront_fast.vhd Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 -- Loading package STANDARD -- Loading package TEXTIO @@ -581,7 +582,7 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct -- Compiling entity spwrecvfront_fast -- Compiling architecture spwrecvfront_arch of spwrecvfront_fast -} {} {}} ../SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spwc_status_dc_fifo/spwc_status_dc_fifo.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spwc_status_dc_fifo/spwc_status_dc_fifo.vhd +} {} {}} ../SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spwc_status_dc_fifo/spwc_status_dc_fifo.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spwc_status_dc_fifo/spwc_status_dc_fifo.vhd Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 -- Loading package STANDARD -- Loading package TEXTIO @@ -589,7 +590,7 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct -- Compiling entity spwc_status_dc_fifo -- Compiling architecture SYN of spwc_status_dc_fifo -} {} {}} ../SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwpkg.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwpkg.vhd +} {} {}} ../SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwpkg.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwpkg.vhd Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 -- Loading package STANDARD -- Loading package TEXTIO @@ -604,7 +605,7 @@ Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct -- Compiling entity syncdff -- Compiling architecture syncdff_arch of syncdff -} {} {}} ../SpaceWire_Channel/SPW_CODEC/altera_ip/altiobuf/spwc_spw_rx_altiobuf/spwc_spw_rx_altiobuf.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/altera_ip/altiobuf/spwc_spw_rx_altiobuf/spwc_spw_rx_altiobuf.vhd +} {} {}} ../SpaceWire_Channel/SPW_CODEC/altera_ip/altiobuf/spwc_spw_rx_altiobuf/spwc_spw_rx_altiobuf.vhd {1 {vcom -work work -2002 -explicit -stats=none D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/altera_ip/altiobuf/spwc_spw_rx_altiobuf/spwc_spw_rx_altiobuf.vhd Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 -- Loading package STANDARD -- Loading package TEXTIO diff --git a/FPGA_Developments/SpaceWire_Channel/Development/Testbench/SpaceWire_Channel.mpf b/FPGA_Developments/SpaceWire_Channel/Development/Testbench/SpaceWire_Channel.mpf index 470339b85..5e1d76121 100644 --- a/FPGA_Developments/SpaceWire_Channel/Development/Testbench/SpaceWire_Channel.mpf +++ b/FPGA_Developments/SpaceWire_Channel/Development/Testbench/SpaceWire_Channel.mpf @@ -412,79 +412,79 @@ Project_DefaultLib = work Project_SortMethod = unused Project_Files_Count = 37 Project_File_0 = ../SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecvfront_generic.vhd -Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CODEC last_compile 1607035842 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 6 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CODEC last_compile 1620845105 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 6 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_1 = ../SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_tx_data_ent.vhd -Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CLK_SYNCHRONIZATION last_compile 1599275932 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 24 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CLK_SYNCHRONIZATION last_compile 1607084436 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 24 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_2 = ../SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_tx_timecode_ent.vhd -Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CLK_SYNCHRONIZATION last_compile 1595826185 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 22 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CLK_SYNCHRONIZATION last_compile 1607084436 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 22 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_3 = ../SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwxmit_fast.vhd -Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CODEC last_compile 1607035842 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 9 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CODEC last_compile 1620696974 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 9 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_4 = ../SpaceWire_Channel/SPW_CODEC/altera_ip/altiobuf/spwc_spw_tx_altiobuf/spwc_spw_tx_altiobuf.vhd -Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CODEC last_compile 1599275932 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 15 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CODEC last_compile 1607084436 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 15 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_5 = ../SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecv.vhd -Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CODEC last_compile 1607035842 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 4 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CODEC last_compile 1620845154 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 4 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_6 = ../SpaceWire_Channel/SPW_CODEC/spwc_codec.vhd -Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CODEC last_compile 1607035842 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 17 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CODEC last_compile 1607084436 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 17 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_7 = ../SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwxmit.vhd -Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CODEC last_compile 1607035842 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 8 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CODEC last_compile 1620696971 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 8 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_8 = ../SpaceWire_Channel/SPW_LEDS_CONTROLLER/spwc_leds_controller_ent.vhd -Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_LEDS_CONTROLLER last_compile 1599275932 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 31 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_LEDS_CONTROLLER last_compile 1607084436 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 31 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_9 = ../SpaceWire_Channel/SPW_ERRINJ/spwc_errinj_pkg.vhd -Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_ERRINJ last_compile 1607035842 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 12 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_ERRINJ last_compile 1607084436 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 12 dont_compile 0 cover_nosub 0 vhdl_use93 2002 Project_File_10 = ../SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_commands_ent.vhd -Project_File_P_10 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CLK_SYNCHRONIZATION last_compile 1607035842 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 26 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_10 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CLK_SYNCHRONIZATION last_compile 1607084436 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 26 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_11 = ../SpaceWire_Channel/SPW_CODEC/spwc_codec_pkg.vhd -Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CODEC last_compile 1607035842 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 16 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CODEC last_compile 1607084436 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 16 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_12 = ../SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwstream.vhd -Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CODEC last_compile 1607035842 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 7 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CODEC last_compile 1620845081 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 7 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_13 = ../SpaceWire_Channel/SPW_LEDS_CONTROLLER/spwc_leds_controller_pkg.vhd -Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_LEDS_CONTROLLER last_compile 1599275932 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 30 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_LEDS_CONTROLLER last_compile 1607084436 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 30 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_14 = ../SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spwc_data_dc_fifo/spwc_data_dc_fifo.vhd -Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CLK_SYNCHRONIZATION last_compile 1599275932 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 20 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CLK_SYNCHRONIZATION last_compile 1607084436 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 20 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_15 = ../SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spwc_timecode_dc_fifo/spwc_timecode_dc_fifo.vhd -Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CLK_SYNCHRONIZATION last_compile 1599275932 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 21 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CLK_SYNCHRONIZATION last_compile 1607084436 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 21 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_16 = ../SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_status_ent.vhd -Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CLK_SYNCHRONIZATION last_compile 1607035842 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 27 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CLK_SYNCHRONIZATION last_compile 1607084436 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 27 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_17 = ../SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwlink.vhd -Project_File_P_17 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CODEC last_compile 1607035842 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 2 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_17 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CODEC last_compile 1620696820 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 2 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_18 = ../SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecvfront_fast.vhd -Project_File_P_18 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CODEC last_compile 1607035842 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 5 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_18 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CODEC last_compile 1620696981 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 5 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_19 = ../SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_top.vhd -Project_File_P_19 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CLK_SYNCHRONIZATION last_compile 1607035842 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 28 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_19 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CLK_SYNCHRONIZATION last_compile 1607084436 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 28 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_20 = ../SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spwc_command_dc_fifo/spwc_command_dc_fifo.vhd -Project_File_P_20 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CLK_SYNCHRONIZATION last_compile 1607035842 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 18 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_20 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CLK_SYNCHRONIZATION last_compile 1607084436 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 18 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_21 = ../SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwram.vhd -Project_File_P_21 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CODEC last_compile 1607035842 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 3 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_21 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CODEC last_compile 1620696986 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 3 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_22 = ../SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwerr.vhd -Project_File_P_22 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CODEC last_compile 1611201882 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 1 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_22 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CODEC last_compile 1620698079 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 1 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_23 = ../SpaceWire_Channel/SPW_LEDS_CONTROLLER/altera_ip/altiobuf/spwc_leds_out_altiobuf/spwc_leds_out_altiobuf.vhd -Project_File_P_23 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_LEDS_CONTROLLER last_compile 1599275932 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 29 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_23 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_LEDS_CONTROLLER last_compile 1607084436 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 29 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_24 = ../SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spwc_status_dc_fifo/spwc_status_dc_fifo.vhd -Project_File_P_24 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CLK_SYNCHRONIZATION last_compile 1607035842 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 19 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_24 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CLK_SYNCHRONIZATION last_compile 1607084436 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 19 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_25 = ../Testbench/testbench_top.vhd -Project_File_P_25 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1607035842 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 36 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_25 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1620845173 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 36 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_26 = ../SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/streamtest.vhd -Project_File_P_26 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CODEC last_compile 1607035842 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 10 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_26 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CODEC last_compile 1620696968 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 10 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_27 = ../SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwpkg.vhd -Project_File_P_27 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CODEC last_compile 1607035842 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_27 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CODEC last_compile 1620844917 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_28 = ../Testbench/testbench_synchronization_top.vhd -Project_File_P_28 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1607035842 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 35 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_28 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1607084436 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 35 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_29 = ../SpaceWire_Channel/SPW_ERRINJ/spwc_errinj_controller_ent.vhd -Project_File_P_29 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_ERRINJ last_compile 1607035842 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 13 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_P_29 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_ERRINJ last_compile 1607084436 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 13 dont_compile 0 cover_nosub 0 vhdl_use93 2002 Project_File_30 = ../SpaceWire_Channel/spwc_spacewire_channel_top.vhd -Project_File_P_30 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1607035842 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 32 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_P_30 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1620848557 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 32 dont_compile 0 cover_nosub 0 vhdl_use93 2002 Project_File_31 = ../SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/syncdff.vhd -Project_File_P_31 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CODEC last_compile 1607035842 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 11 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_31 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CODEC last_compile 1620696965 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 11 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_32 = ../SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_rx_timecode_ent.vhd -Project_File_P_32 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CLK_SYNCHRONIZATION last_compile 1595826185 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 23 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_32 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CLK_SYNCHRONIZATION last_compile 1607084436 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 23 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_33 = ../Testbench/config_avs_stimuli.vhd -Project_File_P_33 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1595826185 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 33 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_33 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1607084436 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 33 dont_compile 0 cover_nosub 0 vhdl_use93 2002 Project_File_34 = ../Testbench/config_spw_stimuli.vhd -Project_File_P_34 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1595826185 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 34 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_34 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1607084436 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 34 dont_compile 0 cover_nosub 0 vhdl_use93 2002 Project_File_35 = ../SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_rx_data_ent.vhd -Project_File_P_35 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CLK_SYNCHRONIZATION last_compile 1595826185 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 25 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_35 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CLK_SYNCHRONIZATION last_compile 1607084436 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 25 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_36 = ../SpaceWire_Channel/SPW_CODEC/altera_ip/altiobuf/spwc_spw_rx_altiobuf/spwc_spw_rx_altiobuf.vhd -Project_File_P_36 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CODEC last_compile 1599275932 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 14 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_36 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder SPW_CODEC last_compile 1607084436 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 14 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_Sim_Count = 0 Project_Folder_Count = 4 Project_Folder_0 = SPW_CLK_SYNCHRONIZATION diff --git a/FPGA_Developments/SpaceWire_Channel/Development/Testbench/testbench_top.vhd b/FPGA_Developments/SpaceWire_Channel/Development/Testbench/testbench_top.vhd index 982b721ce..9e6af6a2c 100644 --- a/FPGA_Developments/SpaceWire_Channel/Development/Testbench/testbench_top.vhd +++ b/FPGA_Developments/SpaceWire_Channel/Development/Testbench/testbench_top.vhd @@ -10,207 +10,230 @@ end entity testbench_top; architecture RTL of testbench_top is - -- clk and rst signals - signal clk200 : std_logic := '0'; - signal clk100 : std_logic := '0'; - signal rst : std_logic := '1'; - - -- dut signals - - -- lvds signals (comm) - signal s_spw_codec_comm_di : std_logic; - signal s_spw_codec_comm_do : std_logic; - signal s_spw_codec_comm_si : std_logic; - signal s_spw_codec_comm_so : std_logic; - - -- lvds signals (dummy) - signal s_spw_codec_dummy_di : std_logic; - signal s_spw_codec_dummy_do : std_logic; - signal s_spw_codec_dummy_si : std_logic; - signal s_spw_codec_dummy_so : std_logic; - - -- spacewire clock signal - signal s_spw_clock : std_logic; - - --dummy - signal s_dummy_spw_rxvalid : std_logic; - signal s_dummy_spw_rxhalff : std_logic; - signal s_dummy_spw_rxflag : std_logic; - signal s_dummy_spw_rxdata : std_logic_vector(7 downto 0); - signal s_dummy_spw_rxread : std_logic; - - signal s_spwcfg_autostart : std_logic; - signal s_spwcfg_linkstart : std_logic; - signal s_spwcfg_linkdis : std_logic; - signal s_spwcfg_txdivcnt : std_logic_vector(7 downto 0); - - signal s_spwerr_start_errinj : std_logic; - signal s_spwerr_reset_errinj : std_logic; - signal s_spwerr_errinj_code : std_logic_vector(3 downto 0); - - signal s_stats_spw_started : std_logic; - signal s_stats_spw_connecting : std_logic; - signal s_stats_spw_running : std_logic; - signal s_error_spw_errdisc : std_logic; - signal s_error_spw_errpar : std_logic; - signal s_error_spw_erresc : std_logic; - signal s_error_spw_errcred : std_logic; + -- clk and rst signals + signal clk200 : std_logic := '0'; + signal clk100 : std_logic := '0'; + signal rst : std_logic := '1'; + + -- dut signals + + -- lvds signals (comm) + signal s_spw_codec_comm_di : std_logic; + signal s_spw_codec_comm_do : std_logic; + signal s_spw_codec_comm_si : std_logic; + signal s_spw_codec_comm_so : std_logic; + + -- lvds signals (dummy) + signal s_spw_codec_dummy_di : std_logic; + signal s_spw_codec_dummy_do : std_logic; + signal s_spw_codec_dummy_si : std_logic; + signal s_spw_codec_dummy_so : std_logic; + + -- spacewire clock signal + signal s_spw_clock : std_logic; + + -- spacewire enable signal + signal s_spw_enable : std_logic; + + --dummy + signal s_dummy_spw_rxvalid : std_logic; + signal s_dummy_spw_rxhalff : std_logic; + signal s_dummy_spw_rxflag : std_logic; + signal s_dummy_spw_rxdata : std_logic_vector(7 downto 0); + signal s_dummy_spw_rxread : std_logic; + + signal s_spwcfg_autostart : std_logic; + signal s_spwcfg_linkstart : std_logic; + signal s_spwcfg_linkdis : std_logic; + signal s_spwcfg_txdivcnt : std_logic_vector(7 downto 0); + + signal s_spwerr_start_errinj : std_logic; + signal s_spwerr_reset_errinj : std_logic; + signal s_spwerr_errinj_code : std_logic_vector(3 downto 0); + + signal s_stats_spw_started : std_logic; + signal s_stats_spw_connecting : std_logic; + signal s_stats_spw_running : std_logic; + signal s_error_spw_errdisc : std_logic; + signal s_error_spw_errpar : std_logic; + signal s_error_spw_erresc : std_logic; + signal s_error_spw_errcred : std_logic; + + constant c_SPW_DI_RANDOM_NOISE : std_logic_vector(1023 downto 0) := "1110001000110011001111001001110101100101011010000101100110000000110110100100011110000111110001111101011111101110110101111010100010100001011111111010111110001111010101000101011010110000000111010011010110101100000110101000010110101100110111111001100001100101101100010100100101100110111010011000000111100001010000110000111111110101001011110011010011110000101101111110110000101001010110110011100011000101110000000001101111000000110110010110100011100000011100101110000111001110001000101000001101100110111001011001011000011000010111110010100110010100011010110110111011111010111011001001000000011100101101111000100000001101011011000001111111000101010101001110110010110001111000000000100011000001111110100001001100010110110010001010101000001001000000100111011111100110000000101100001101110100110110001101111000011011011100110110001100011111101111011101010111101100110111001111111000000011010111111000110100100100010100000110101001000010001110001000001011110000111011110000101100000110100111101001000001111111101100010000010100110110"; + constant c_SPW_SI_RANDOM_NOISE : std_logic_vector(1023 downto 0) := "0011101011111111011110101100111000101011100001101001011001111011100111111011110111010111100010110010101100111111100110101100110100000011110100110101101111000010001011000101111101111011101111111000111111001100111001011101100001110110000001010101111010010101100111001100000111111101010011100100001011000101001110010011010100001011001001000000101000000110110101111101001001010011000111110110010111011110010111000011101100011001100110000100110001100001011110010011101101001011100010000001000000010100110110101000110001010111111011000011000000001000100010000100011001000101001100110100110001000100001111010000001010010001100000010101010001111111100100111100000101000011101011111110100100100101111010010110111101010010110001110110101101101110001111101101011101001010011000100111001110110100011100000011110011010011100001000000010110111110110110011001000000111111001110001000111100100111110110000010000111110101100011000101001101101101100101010001010011000000011111001000111010100110010001111101111001010100000100001001000001100011"; + + signal s_random_noise_cnt : natural range 0 to 1023; begin - clk200 <= not clk200 after 2.5 ns; -- 200 MHz - clk100 <= not clk100 after 5 ns; -- 100 MHz - rst <= '0' after 100 ns; - - spwc_spacewire_channel_top_inst : entity work.spwc_spacewire_channel_top - generic map( - g_SPWC_TESTBENCH_MODE => '1' - ) - port map( - reset_i => rst, - clk_100_i => clk100, - clk_200_i => clk200, - spw_lvds_p_data_in_i => s_spw_codec_comm_di, - spw_lvds_n_data_in_i => '0', - spw_lvds_p_strobe_in_i => s_spw_codec_comm_si, - spw_lvds_n_strobe_in_i => '0', - spw_lvds_p_data_out_o => s_spw_codec_comm_do, - spw_lvds_n_data_out_o => open, - spw_lvds_p_strobe_out_o => s_spw_codec_comm_so, - spw_lvds_n_strobe_out_o => open, - spw_rx_enable_i => '1', - spw_tx_enable_i => '1', - spw_red_status_led_o => open, - spw_green_status_led_o => open, - spw_link_command_autostart_i => s_spwcfg_autostart, - spw_link_command_linkstart_i => s_spwcfg_linkstart, - spw_link_command_linkdis_i => s_spwcfg_linkdis, - spw_link_command_txdivcnt_i => s_spwcfg_txdivcnt, - spw_timecode_tx_tick_in_i => '0', - spw_timecode_tx_ctrl_in_i => (others => '0'), - spw_timecode_tx_time_in_i => (others => '0'), - spw_data_rx_command_rxread_i => '0', - spw_data_tx_command_txwrite_i => '0', - spw_data_tx_command_txflag_i => '0', - spw_data_tx_command_txdata_i => (others => '0'), - spw_errinj_ctrl_start_errinj_i => s_spwerr_start_errinj, - spw_errinj_ctrl_reset_errinj_i => s_spwerr_reset_errinj, - spw_errinj_ctrl_errinj_code_i => s_spwerr_errinj_code, - spw_link_status_started_o => open, - spw_link_status_connecting_o => open, - spw_link_status_running_o => open, - spw_link_error_errdisc_o => open, - spw_link_error_errpar_o => open, - spw_link_error_erresc_o => open, - spw_link_error_errcred_o => open, - spw_timecode_rx_tick_out_o => open, - spw_timecode_rx_ctrl_out_o => open, - spw_timecode_rx_time_out_o => open, - spw_data_rx_status_rxvalid_o => open, - spw_data_rx_status_rxhalff_o => open, - spw_data_rx_status_rxflag_o => open, - spw_data_rx_status_rxdata_o => open, - spw_data_tx_status_txrdy_o => open, - spw_data_tx_status_txhalff_o => open, - spw_errinj_ctrl_errinj_busy_o => open, - spw_errinj_ctrl_errinj_ready_o => open - ); - - -- s_spw_codec_comm_di <= s_spw_codec_comm_do; - -- s_spw_codec_comm_si <= s_spw_codec_comm_so; - - p_spw_cfg : process(clk100, rst) is - variable v_cnt : natural := 0; - begin - if rst = '1' then - s_spwcfg_autostart <= '0'; - s_spwcfg_linkstart <= '0'; - s_spwcfg_linkdis <= '0'; - s_spwcfg_txdivcnt <= x"01"; - s_spwerr_start_errinj <= '0'; - s_spwerr_reset_errinj <= '0'; - s_spwerr_errinj_code <= c_SPWC_ERRINJ_CODE_NONE; - v_cnt := 0; - elsif rising_edge(clk100) then - s_spwcfg_autostart <= '1'; - s_spwcfg_linkstart <= '0'; - s_spwcfg_linkdis <= '0'; - s_spwcfg_txdivcnt <= x"01"; - - s_spwerr_start_errinj <= '0'; - s_spwerr_reset_errinj <= '0'; - s_spwerr_errinj_code <= c_SPWC_ERRINJ_CODE_NONE; - case (v_cnt) is - when 5000 => - s_spwerr_start_errinj <= '1'; - when 6000 => - s_spwerr_reset_errinj <= '1'; - when others => - null; - end case; - v_cnt := v_cnt + 1; - - end if; - end process p_spw_cfg; - - s_spw_clock <= (s_spw_codec_comm_so) xor (s_spw_codec_comm_do); - - -- spw connection - -- SpaceWire Light Codec Component - spw_stimuli_spwstream_inst : entity work.spwstream - generic map( - sysfreq => 200000000.0, - txclkfreq => 0.0, - rximpl => impl_generic, - rxchunk => 1, - tximpl => impl_generic, - rxfifosize_bits => 11, - txfifosize_bits => 11 - ) - port map( - clk => clk200, - rxclk => clk200, - txclk => clk200, - rst => rst, - autostart => '1', - linkstart => '1', - linkdis => '0', - txdivcnt => x"01", - tick_in => '0', - ctrl_in => "00", - time_in => "000000", - txwrite => '0', - txflag => '0', - txdata => x"00", - txrdy => open, - txhalff => open, - tick_out => open, - ctrl_out => open, - time_out => open, - rxvalid => s_dummy_spw_rxvalid, - rxhalff => s_dummy_spw_rxhalff, - rxflag => s_dummy_spw_rxflag, - rxdata => s_dummy_spw_rxdata, - rxread => s_dummy_spw_rxread, - started => s_stats_spw_started, - connecting => s_stats_spw_connecting, - running => s_stats_spw_running, - errdisc => s_error_spw_errdisc, - errpar => s_error_spw_errpar, - erresc => s_error_spw_erresc, - errcred => s_error_spw_errcred, - spw_di => s_spw_codec_dummy_di, - spw_si => s_spw_codec_dummy_si, - spw_do => s_spw_codec_dummy_do, - spw_so => s_spw_codec_dummy_so, - err_inj_i => '0', - err_sel_i => reserved, - err_stat_o => open - ); - - s_spw_codec_comm_di <= s_spw_codec_dummy_do; - s_spw_codec_comm_si <= s_spw_codec_dummy_so; - s_spw_codec_dummy_di <= s_spw_codec_comm_do; - s_spw_codec_dummy_si <= s_spw_codec_comm_so; + clk200 <= not clk200 after 2.5 ns; -- 200 MHz + clk100 <= not clk100 after 5 ns; -- 100 MHz + rst <= '0' after 100 ns; + + spwc_spacewire_channel_top_inst : entity work.spwc_spacewire_channel_top + generic map( + g_SPWC_TESTBENCH_MODE => '1' + ) + port map( + reset_i => rst, + clk_100_i => clk100, + clk_200_i => clk200, + spw_lvds_p_data_in_i => s_spw_codec_comm_di, + spw_lvds_n_data_in_i => '0', + spw_lvds_p_strobe_in_i => s_spw_codec_comm_si, + spw_lvds_n_strobe_in_i => '0', + spw_lvds_p_data_out_o => s_spw_codec_comm_do, + spw_lvds_n_data_out_o => open, + spw_lvds_p_strobe_out_o => s_spw_codec_comm_so, + spw_lvds_n_strobe_out_o => open, + spw_rx_enable_i => s_spw_enable, + spw_tx_enable_i => s_spw_enable, + spw_red_status_led_o => open, + spw_green_status_led_o => open, + spw_link_command_autostart_i => s_spwcfg_autostart, + spw_link_command_linkstart_i => s_spwcfg_linkstart, + spw_link_command_linkdis_i => s_spwcfg_linkdis, + spw_link_command_txdivcnt_i => s_spwcfg_txdivcnt, + spw_timecode_tx_tick_in_i => '0', + spw_timecode_tx_ctrl_in_i => (others => '0'), + spw_timecode_tx_time_in_i => (others => '0'), + spw_data_rx_command_rxread_i => '0', + spw_data_tx_command_txwrite_i => '0', + spw_data_tx_command_txflag_i => '0', + spw_data_tx_command_txdata_i => (others => '0'), + spw_errinj_ctrl_start_errinj_i => s_spwerr_start_errinj, + spw_errinj_ctrl_reset_errinj_i => s_spwerr_reset_errinj, + spw_errinj_ctrl_errinj_code_i => s_spwerr_errinj_code, + spw_link_status_started_o => open, + spw_link_status_connecting_o => open, + spw_link_status_running_o => open, + spw_link_error_errdisc_o => open, + spw_link_error_errpar_o => open, + spw_link_error_erresc_o => open, + spw_link_error_errcred_o => open, + spw_timecode_rx_tick_out_o => open, + spw_timecode_rx_ctrl_out_o => open, + spw_timecode_rx_time_out_o => open, + spw_data_rx_status_rxvalid_o => open, + spw_data_rx_status_rxhalff_o => open, + spw_data_rx_status_rxflag_o => open, + spw_data_rx_status_rxdata_o => open, + spw_data_tx_status_txrdy_o => open, + spw_data_tx_status_txhalff_o => open, + spw_errinj_ctrl_errinj_busy_o => open, + spw_errinj_ctrl_errinj_ready_o => open + ); + + s_spw_enable <= '0', '1' after 5 us; + + -- s_spw_codec_comm_di <= s_spw_codec_comm_do; + -- s_spw_codec_comm_si <= s_spw_codec_comm_so; + + p_spw_cfg : process(clk100, rst) is + variable v_cnt : natural := 0; + begin + if rst = '1' then + s_spwcfg_autostart <= '0'; + s_spwcfg_linkstart <= '0'; + s_spwcfg_linkdis <= '0'; + s_spwcfg_txdivcnt <= x"01"; + s_spwerr_start_errinj <= '0'; + s_spwerr_reset_errinj <= '0'; + s_spwerr_errinj_code <= c_SPWC_ERRINJ_CODE_NONE; + s_random_noise_cnt <= 1023; + v_cnt := 0; + elsif rising_edge(clk100) then + s_spwcfg_autostart <= '1'; + s_spwcfg_linkstart <= '1'; + s_spwcfg_linkdis <= '0'; + s_spwcfg_txdivcnt <= x"01"; + + s_spwerr_start_errinj <= '0'; + s_spwerr_reset_errinj <= '0'; + s_spwerr_errinj_code <= c_SPWC_ERRINJ_CODE_NONE; + -- s_spwerr_errinj_code <= c_SPWC_ERRINJ_CODE_PARITY; + case (v_cnt) is + when 5000 => + -- s_spwerr_start_errinj <= '1'; + -- s_spwcfg_autostart <= '1'; + -- s_spwcfg_linkstart <= '1'; + -- s_spwcfg_linkdis <= '0'; + when 6000 => + -- s_spwerr_reset_errinj <= '1'; + when others => + null; + end case; + v_cnt := v_cnt + 1; + + if (s_random_noise_cnt = 0) then + s_random_noise_cnt <= 1023; + else + s_random_noise_cnt <= s_random_noise_cnt - 1; + end if; + + end if; + end process p_spw_cfg; + + s_spw_clock <= (s_spw_codec_comm_so) xor (s_spw_codec_comm_do); + + -- spw connection + -- SpaceWire Light Codec Component + spw_stimuli_spwstream_inst : entity work.spwstream + generic map( + sysfreq => 200000000.0, + txclkfreq => 0.0, + rximpl => impl_generic, + rxchunk => 1, + tximpl => impl_generic, + rxfifosize_bits => 11, + txfifosize_bits => 11 + ) + port map( + clk => clk200, + rxclk => clk200, + txclk => clk200, + rst => rst, + autostart => '1', + linkstart => '1', + linkdis => '0', + txdivcnt => x"01", + tick_in => '0', + ctrl_in => "00", + time_in => "000000", + txwrite => '0', + txflag => '0', + txdata => x"00", + txrdy => open, + txhalff => open, + tick_out => open, + ctrl_out => open, + time_out => open, + rxvalid => s_dummy_spw_rxvalid, + rxhalff => s_dummy_spw_rxhalff, + rxflag => s_dummy_spw_rxflag, + rxdata => s_dummy_spw_rxdata, + rxread => s_dummy_spw_rxread, + started => s_stats_spw_started, + connecting => s_stats_spw_connecting, + running => s_stats_spw_running, + errdisc => s_error_spw_errdisc, + errpar => s_error_spw_errpar, + erresc => s_error_spw_erresc, + errcred => s_error_spw_errcred, + spw_di => s_spw_codec_dummy_di, + spw_si => s_spw_codec_dummy_si, + spw_do => s_spw_codec_dummy_do, + spw_so => s_spw_codec_dummy_so, + err_inj_i => '0', + err_sel_i => reserved, + err_stat_o => open + ); + +-- s_spw_codec_comm_di <= c_SPW_DI_RANDOM_NOISE(s_random_noise_cnt); +-- s_spw_codec_comm_si <= c_SPW_SI_RANDOM_NOISE(s_random_noise_cnt); + s_spw_codec_comm_di <= s_spw_codec_dummy_do; + s_spw_codec_comm_si <= s_spw_codec_dummy_so; + s_spw_codec_dummy_di <= s_spw_codec_comm_do; + s_spw_codec_dummy_si <= s_spw_codec_comm_so; end architecture RTL; diff --git a/FPGA_Developments/SpaceWire_Channel/Development/Testbench/transcript b/FPGA_Developments/SpaceWire_Channel/Development/Testbench/transcript index a3ff610c4..af322957c 100644 --- a/FPGA_Developments/SpaceWire_Channel/Development/Testbench/transcript +++ b/FPGA_Developments/SpaceWire_Channel/Development/Testbench/transcript @@ -1,50 +1,7 @@ # Reading C:/intelFPGA/18.1/modelsim_ase/tcl/vsim/pref.tcl -# OpenFile D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/Testbench/SpaceWire_Channel.mpf +# OpenFile D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/Testbench/SpaceWire_Channel.mpf # Loading project SpaceWire_Channel -# Compile of spwpkg.vhd was successful. -# Compile of spwerr.vhd was successful with warnings. -# Compile of spwlink.vhd was successful. -# Compile of spwram.vhd was successful. -# Compile of spwrecv.vhd was successful. -# Compile of spwrecvfront_fast.vhd was successful. -# Compile of spwrecvfront_generic.vhd was successful. -# Compile of spwstream.vhd was successful. -# Compile of spwxmit.vhd was successful. -# Compile of spwxmit_fast.vhd was successful. -# Compile of streamtest.vhd was successful. -# Compile of syncdff.vhd was successful. -# Compile of spwc_errinj_pkg.vhd was successful. -# Compile of spwc_errinj_controller_ent.vhd failed with 4 errors. -# Compile of spwc_spw_rx_altiobuf.vhd was successful. -# Compile of spwc_spw_tx_altiobuf.vhd was successful. -# Compile of spwc_codec_pkg.vhd was successful. -# Compile of spwc_codec.vhd was successful. -# Compile of spwc_command_dc_fifo.vhd was successful. -# Compile of spwc_status_dc_fifo.vhd was successful. -# Compile of spwc_data_dc_fifo.vhd was successful. -# Compile of spwc_timecode_dc_fifo.vhd was successful. -# Compile of spwc_clk_synchronization_tx_timecode_ent.vhd was successful. -# Compile of spwc_clk_synchronization_rx_timecode_ent.vhd was successful. -# Compile of spwc_clk_synchronization_tx_data_ent.vhd was successful. -# Compile of spwc_clk_synchronization_rx_data_ent.vhd was successful. -# Compile of spwc_clk_synchronization_commands_ent.vhd was successful. -# Compile of spwc_clk_synchronization_status_ent.vhd was successful. -# Compile of spwc_clk_synchronization_top.vhd was successful. -# Compile of spwc_leds_out_altiobuf.vhd was successful. -# Compile of spwc_leds_controller_pkg.vhd was successful. -# Compile of spwc_leds_controller_ent.vhd was successful. -# Compile of spwc_spacewire_channel_top.vhd failed with 4 errors. -# Compile of config_avs_stimuli.vhd was successful. -# Compile of config_spw_stimuli.vhd was successful. -# Compile of testbench_synchronization_top.vhd was successful. -# Compile of testbench_top.vhd was successful. -# 37 compiles, 2 failed with 8 errors. -# Compile of spwerr.vhd was successful with warnings. -# Compile of spwc_errinj_controller_ent.vhd was successful. # Compile of spwc_spacewire_channel_top.vhd was successful. -# 3 compiles, 0 failed with no errors. -# Compile of spwerr.vhd was successful with warnings. -# Compile of spwerr.vhd was successful. # Compile of spwpkg.vhd was successful. # Compile of spwerr.vhd was successful. # Compile of spwlink.vhd was successful. diff --git a/FPGA_Developments/SpaceWire_Channel/Development/Testbench/vsim.wlf b/FPGA_Developments/SpaceWire_Channel/Development/Testbench/vsim.wlf index 4cbf909e3..5fe162d23 100644 Binary files a/FPGA_Developments/SpaceWire_Channel/Development/Testbench/vsim.wlf and b/FPGA_Developments/SpaceWire_Channel/Development/Testbench/vsim.wlf differ diff --git a/FPGA_Developments/SpaceWire_Channel/Development/Testbench/work/_info b/FPGA_Developments/SpaceWire_Channel/Development/Testbench/work/_info index b3d855c07..6e61b23e0 100644 --- a/FPGA_Developments/SpaceWire_Channel/Development/Testbench/work/_info +++ b/FPGA_Developments/SpaceWire_Channel/Development/Testbench/work/_info @@ -9,26 +9,26 @@ z2 cModel Technology dD:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/UART_Module/Development/Testbench Econfig_avs_stimuli -Z0 w1595826185 -Z1 DPx4 work 6 spwpkg 0 22 `Z443Q00J38VTS96N;::b1 +Z0 w1607084436 +Z1 DPx4 work 6 spwpkg 0 22 a5Agjb>z@D5bUGlcjJGE70 Z2 DPx4 work 14 spwc_codec_pkg 0 22 KM8d9fViX`c_Rz8>?zAn<0 Z3 DPx4 ieee 11 numeric_std 0 22 :ASDNFgHXf_ih3J@9F3Ze1 Z4 DPx3 std 6 textio 0 22 zE1`LPoLg^DX3Oz^4Fj1K3 Z5 DPx4 ieee 14 std_logic_1164 0 22 eNV`TJ_GofJTzYa?f<@Oe1 -Z6 dD:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/Testbench -Z7 8D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/Testbench/config_avs_stimuli.vhd -Z8 FD:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/Testbench/config_avs_stimuli.vhd +Z6 dD:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/Testbench +Z7 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-reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/Testbench/config_avs_stimuli.vhd| +Z13 !s107 D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/Testbench/config_avs_stimuli.vhd| !i113 1 Z14 o-work work -2002 -explicit Z15 tExplicit 1 CvgOpt 0 @@ -61,19 +61,19 @@ R3 R4 R5 R6 -Z17 8D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/Testbench/config_spw_stimuli.vhd -Z18 FD:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/Testbench/config_spw_stimuli.vhd +Z17 8D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/Testbench/config_spw_stimuli.vhd +Z18 FD:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/Testbench/config_spw_stimuli.vhd l0 L7 VO:hL0Fi7AX1LLo4g9hHM51 !s100 W6PEP5BDAlGeLXj>SoeR80 R9 32 -Z19 !s110 1611201893 +R10 !i10b 1 -Z20 !s108 1611201893.000000 -Z21 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/Testbench/config_spw_stimuli.vhd| -Z22 !s107 D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/Testbench/config_spw_stimuli.vhd| +Z19 !s108 1620848596.000000 +Z20 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/Testbench/config_spw_stimuli.vhd| +Z21 !s107 D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/Testbench/config_spw_stimuli.vhd| !i113 1 R14 R15 @@ -83,50 +83,50 @@ R2 R3 R4 R5 -Z23 DEx4 work 18 config_spw_stimuli 0 22 O:hL0Fi7AX1LLo4g9hHM51 +Z22 DEx4 work 18 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8D:/rfranca/Development/GitHub/SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spw_codec.vhd -Z45 FD:/rfranca/Development/GitHub/SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spw_codec.vhd +R26 +Z43 8D:/rfranca/Development/GitHub/SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spw_codec.vhd +Z44 FD:/rfranca/Development/GitHub/SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spw_codec.vhd l0 L8 V][UJSbCdd9EY>ZO2 !s100 Bh?1i:AmId3dj0dK9fz=k2 R9 32 -R46 +R45 !i10b 1 +R46 R47 R48 -R49 !i113 1 R14 R15 Pspw_codec_pkg -R25 +R24 R3 R4 R5 -R43 -R27 +R42 +R26 8D:/rfranca/Development/GitHub/SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spw_codec_pkg.vhd FD:/rfranca/Development/GitHub/SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spw_codec_pkg.vhd l0 @@ -253,171 +253,171 @@ V8cXa^iN6WLUHQT46aNPhO1 !s100 ]:kiVoGH?3nJ`9IaciU_Q1 R9 32 -R46 +R45 !i10b 1 -R47 +R46 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/rfranca/Development/GitHub/SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spw_codec_pkg.vhd| !s107 D:/rfranca/Development/GitHub/SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spw_codec_pkg.vhd| !i113 1 R14 R15 Espw_data_dc_fifo -Z50 w1574393811 +Z49 w1574393811 R4 R5 -R27 -Z51 8D:/rfranca/Development/GitHub/SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spw_data_dc_fifo/spw_data_dc_fifo.vhd -Z52 FD:/rfranca/Development/GitHub/SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spw_data_dc_fifo/spw_data_dc_fifo.vhd +R26 +Z50 8D:/rfranca/Development/GitHub/SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spw_data_dc_fifo/spw_data_dc_fifo.vhd +Z51 FD:/rfranca/Development/GitHub/SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spw_data_dc_fifo/spw_data_dc_fifo.vhd l0 L42 VI<6zf3<^8n7:`Kbadk85z3 !s100 RP3OUQ^5Rgb[2g6[olbW`3 R9 32 -R46 +R45 !i10b 1 -R47 -Z53 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/rfranca/Development/GitHub/SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spw_data_dc_fifo/spw_data_dc_fifo.vhd| -Z54 !s107 D:/rfranca/Development/GitHub/SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spw_data_dc_fifo/spw_data_dc_fifo.vhd| +R46 +Z52 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/rfranca/Development/GitHub/SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spw_data_dc_fifo/spw_data_dc_fifo.vhd| +Z53 !s107 D:/rfranca/Development/GitHub/SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spw_data_dc_fifo/spw_data_dc_fifo.vhd| !i113 1 R14 R15 Asyn R4 R5 -R42 +R41 l101 L60 VAjGhRN_WQG>jDEa0YBUcK2 !s100 ^[GUkD9caOW]H`dCjbjLV2 R9 32 -R46 +R45 !i10b 1 -R47 +R46 +R52 R53 -R54 !i113 1 R14 R15 Espw_timecode_dc_fifo -R50 +R49 R4 R5 -R27 -Z55 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R15 Asyn R4 R5 -R41 +R40 l101 L60 V_R8TJm::g06W6A2BhUlzJ0 !s100 L@l7SL8>jTVPRUlYXHK1U0 R9 32 -R30 +R29 !i10b 1 -R47 +R46 +R56 R57 -R58 !i113 1 R14 R15 Espwc_clk_synchronization_commands_ent -Z59 w1607035842 +R0 R1 R2 -Z60 DPx4 work 15 spwc_errinj_pkg 0 22 1LThXcof0?3N85O2SGL4`3 +Z58 DPx4 work 15 spwc_errinj_pkg 0 22 1LThXcof0?3N85O2SGL4`3 R3 R4 R5 R6 -Z61 8D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_commands_ent.vhd -Z62 FD:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_commands_ent.vhd +Z59 8D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_commands_ent.vhd +Z60 FD:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_commands_ent.vhd l0 L8 VzB>kba=1>]MZ@[HA^m^aG3 !s100 V9cmIS3hz2nZHCdW:G>Y>0 R9 32 -Z63 !s110 1611201891 +Z61 !s110 1620848594 !i10b 1 -Z64 !s108 1611201891.000000 -Z65 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_commands_ent.vhd| -Z66 !s107 D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_commands_ent.vhd| +Z62 !s108 1620848594.000000 +Z63 !s90 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spwc_codec_pkg 0 22 ?ef1B>21aYHNN`n8<3?:a2 +Z67 w1592287558 +R24 +Z68 DPx4 work 14 spwc_codec_pkg 0 22 ?ef1B>21aYHNN`n8<3?:a2 R3 R4 R5 -R27 -Z71 8D:/rfranca/Development/GitHub/SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_ent.vhd -Z72 FD:/rfranca/Development/GitHub/SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_ent.vhd +R26 +Z69 8D:/rfranca/Development/GitHub/SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_ent.vhd +Z70 FD:/rfranca/Development/GitHub/SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_ent.vhd l0 L7 VZOKa`PWc<e91 !s100 cFjQBLS0LK]_l09;j`ag`3 R9 32 -R73 +R71 !i10b 1 +R72 +R73 R74 -R75 -R76 !i113 1 R14 R15 @@ -444,41 +444,41 @@ R3 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FD:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_tx_data_ent.vhd +Z102 8D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_tx_data_ent.vhd +Z103 FD:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_tx_data_ent.vhd l0 L7 VDkYU832QjJ@e:cGf8S6`P1 !s100 8<96>gzoIdU;ThzZ8^nH:3 R9 32 -R86 +R61 !i10b 1 -R87 -Z107 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_tx_data_ent.vhd| -Z108 !s107 D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_tx_data_ent.vhd| +R62 +Z104 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_tx_data_ent.vhd| +Z105 !s107 D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_tx_data_ent.vhd| !i113 1 R14 R15 Artl -R78 +R76 R1 R2 R3 R4 R5 -R102 +R100 l31 L19 VX6a0>V><:YMQXNVgco^h?1 !s100 gGYej6[iQ65DbKiMFoFQO1 R9 32 -R86 +R61 !i10b 1 -R87 -R107 -R108 +R62 +R104 +R105 !i113 1 R14 R15 @@ -683,87 +683,87 @@ R3 R4 R5 R6 -Z109 8D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_tx_timecode_ent.vhd -Z110 FD:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_tx_timecode_ent.vhd +Z106 8D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_tx_timecode_ent.vhd +Z107 FD:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_tx_timecode_ent.vhd l0 L7 VcYEIf`gG<]0nRhaPMaEB03 !s100 NVRgE[leVoa_ek8UN`[W>1 R9 32 -R86 +Z108 !s110 1620848593 !i10b 1 -R87 -Z111 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_tx_timecode_ent.vhd| -Z112 !s107 D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_tx_timecode_ent.vhd| +R84 +Z109 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_tx_timecode_ent.vhd| +Z110 !s107 D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/spwc_clk_synchronization_tx_timecode_ent.vhd| !i113 1 R14 R15 Artl -R77 +R75 R1 R2 R3 R4 R5 -R101 +R99 l26 L17 Vg>2H3j8__cPLfD??OQ?UT3 !s100 P@2ab5KQE4boB5?RS7f[e0 R9 32 -R86 +R108 !i10b 1 -R87 -R111 -R112 +R84 +R109 +R110 !i113 1 R14 R15 Espwc_codec_ent -R59 +R0 R2 R1 R3 R4 R5 R6 -Z113 8D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spwc_codec.vhd -Z114 FD:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spwc_codec.vhd +Z111 8D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spwc_codec.vhd +Z112 FD:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spwc_codec.vhd l0 L8 VZ8c9Bb>:8jfPzUAPmKXzO_m0 +Z117 DEx4 work 9 spwstream 0 22 4QMMVh2BkQEZn`Vd9lYo51 R2 R1 R3 R4 R5 -Z120 DEx4 work 14 spwc_codec_ent 0 22 Z8c9Bb>:8jfPzUAPmKX:8jfPzUAPmKXn@Rdh1 R9 32 -R115 +R113 !i10b 1 +R114 +R115 R116 -R117 -R118 !i113 1 R14 R15 @@ -772,146 +772,146 @@ R1 R3 R4 R5 -R59 +R0 R6 -8D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spwc_codec_pkg.vhd -FD:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spwc_codec_pkg.vhd +8D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spwc_codec_pkg.vhd +FD:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spwc_codec_pkg.vhd l0 L7 VKM8d9fViX`c_Rz8>?zAn<0 !s100 Z?bzX42IUkhghmKEDl4nP1 R9 32 -R115 +R113 !i10b 1 -R116 -!s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spwc_codec_pkg.vhd| -!s107 D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spwc_codec_pkg.vhd| +R114 +!s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spwc_codec_pkg.vhd| +!s107 D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spwc_codec_pkg.vhd| !i113 1 R14 R15 Espwc_command_dc_fifo -R59 +R0 R4 R5 R6 -Z121 8D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spwc_command_dc_fifo/spwc_command_dc_fifo.vhd -Z122 FD:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spwc_command_dc_fifo/spwc_command_dc_fifo.vhd +Z119 8D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spwc_command_dc_fifo/spwc_command_dc_fifo.vhd +Z120 FD:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spwc_command_dc_fifo/spwc_command_dc_fifo.vhd l0 L42 VIzK9kh0?m26[[BoNmRiaN1 !s100 ?:LTGHoVS:S0fQNaA_@TP0 R9 32 -R115 +R113 !i10b 1 -R116 -Z123 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spwc_command_dc_fifo/spwc_command_dc_fifo.vhd| -Z124 !s107 D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spwc_command_dc_fifo/spwc_command_dc_fifo.vhd| +R114 +Z121 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spwc_command_dc_fifo/spwc_command_dc_fifo.vhd| +Z122 !s107 D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spwc_command_dc_fifo/spwc_command_dc_fifo.vhd| !i113 1 R14 R15 Asyn R4 R5 -R67 +R65 l102 L60 VggBb0Q7e^KJQJ`PAZ>ko91 !s100 N^onJI2A21=El]_JS5?cE1 R9 32 -R115 +R113 !i10b 1 -R116 -R123 -R124 +R114 +R121 +R122 !i113 1 R14 R15 Espwc_data_dc_fifo -R104 +R0 R4 R5 R6 -Z125 8D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spwc_data_dc_fifo/spwc_data_dc_fifo.vhd -Z126 FD:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spwc_data_dc_fifo/spwc_data_dc_fifo.vhd +Z123 8D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spwc_data_dc_fifo/spwc_data_dc_fifo.vhd +Z124 FD:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spwc_data_dc_fifo/spwc_data_dc_fifo.vhd l0 L42 VMRNhgaTjkQ0Dj]oTS=5Dh2 !s100 SbIfMBAaG4gihOQD1jzl70 R9 32 -R86 +R108 !i10b 1 -R87 -Z127 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spwc_data_dc_fifo/spwc_data_dc_fifo.vhd| -Z128 !s107 D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spwc_data_dc_fifo/spwc_data_dc_fifo.vhd| +R84 +Z125 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spwc_data_dc_fifo/spwc_data_dc_fifo.vhd| +Z126 !s107 D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spwc_data_dc_fifo/spwc_data_dc_fifo.vhd| !i113 1 R14 R15 Asyn R4 R5 -R78 +R76 l102 L60 VKV=M`d0GX@OXZ[XN8fU5T1 !s100 `=BaZ3K7Io[OXVN@9iza41 R9 32 -R86 +R108 !i10b 1 -R87 -R127 -R128 +R84 +R125 +R126 !i113 1 R14 R15 Espwc_errinj_controller_ent -R59 +R0 R1 R2 -R60 +R58 R3 R4 R5 R6 -Z129 8D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_ERRINJ/spwc_errinj_controller_ent.vhd -Z130 FD:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_ERRINJ/spwc_errinj_controller_ent.vhd +Z127 8D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_ERRINJ/spwc_errinj_controller_ent.vhd +Z128 FD:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_ERRINJ/spwc_errinj_controller_ent.vhd l0 L9 VDCkmidiH]Z]R5ID?hieY63 !s100 ^=dVK]NSnAkGb_ad3oHU13 R9 32 -Z131 !s110 1611201888 +Z129 !s110 1620848591 !i10b 1 -Z132 !s108 1611201888.000000 -Z133 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_ERRINJ/spwc_errinj_controller_ent.vhd| -Z134 !s107 D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_ERRINJ/spwc_errinj_controller_ent.vhd| +Z130 !s108 1620848591.000000 +Z131 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_ERRINJ/spwc_errinj_controller_ent.vhd| +Z132 !s107 D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_ERRINJ/spwc_errinj_controller_ent.vhd| !i113 1 R14 R15 Artl R1 R2 -R60 +R58 R3 R4 R5 -Z135 DEx4 work 26 spwc_errinj_controller_ent 0 22 DCkmidiH]Z]R5ID?hieY63 +Z133 DEx4 work 26 spwc_errinj_controller_ent 0 22 DCkmidiH]Z]R5ID?hieY63 l36 L21 V>`3NeG3 !s100 5`ThNfn1zB;ICFJAeiFDZ2 R9 32 -R131 +R129 !i10b 1 +R130 +R131 R132 -R133 -R134 !i113 1 R14 R15 @@ -919,26 +919,26 @@ Pspwc_errinj_pkg R3 R4 R5 -R59 +R0 R6 -Z136 8D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_ERRINJ/spwc_errinj_pkg.vhd -Z137 FD:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_ERRINJ/spwc_errinj_pkg.vhd +Z134 8D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_ERRINJ/spwc_errinj_pkg.vhd +Z135 FD:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_ERRINJ/spwc_errinj_pkg.vhd l0 L5 V1LThXcof0?3N85O2SGL4`3 !s100 Z4Uo1oU8V2NoggnBDb2nC1 R9 32 -R131 +R129 !i10b 1 -R132 -Z138 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_ERRINJ/spwc_errinj_pkg.vhd| -Z139 !s107 D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_ERRINJ/spwc_errinj_pkg.vhd| +R130 +Z136 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_ERRINJ/spwc_errinj_pkg.vhd| +Z137 !s107 D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_ERRINJ/spwc_errinj_pkg.vhd| !i113 1 R14 R15 Bbody -R60 +R58 R3 R4 R5 @@ -948,54 +948,54 @@ V:EXe`Lj;gln8kn=Vi7^752 !s100 z;=O8Piz0eVT@mLi@>KKS1 R9 32 -R131 +R129 !i10b 1 -R132 -R138 -R139 +R130 +R136 +R137 !i113 1 R14 R15 Espwc_leds_controller_ent -R104 -Z140 DPx4 work 24 spwc_leds_controller_pkg 0 22 hnh<9?gCbR4YCfmnE5KJ@0 +R0 +Z138 DPx4 work 24 spwc_leds_controller_pkg 0 22 hnh<9?gCbR4YCfmnE5KJ@0 R3 R4 R5 R6 -Z141 8D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_LEDS_CONTROLLER/spwc_leds_controller_ent.vhd -Z142 FD:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_LEDS_CONTROLLER/spwc_leds_controller_ent.vhd +Z139 8D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_LEDS_CONTROLLER/spwc_leds_controller_ent.vhd +Z140 FD:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_LEDS_CONTROLLER/spwc_leds_controller_ent.vhd l0 L7 V[PG3_z0B5m8aQlFNA6aOS3 !s100 jWR43I[;kEMkgmOXX9R3B3 R9 32 -R10 +R96 !i10b 1 R11 -Z143 !s90 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D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CLK_SYNCHRONIZATION/altera_ipcore/dcfifo/spwc_timecode_dc_fifo/spwc_timecode_dc_fifo.vhd| !i113 1 R14 R15 Asyn R4 R5 -R77 +R75 l102 L60 VO822Qo41QR1FjKh?5_=nB3 !s100 IXL:30BR4VD91T@N`zSzE0 R9 32 -R86 +R108 !i10b 1 -R87 +R84 +R202 R203 -R204 !i113 1 R14 R15 Espwerr -Z205 w1611201882 +Z204 w1620698079 R1 +Z205 DPx4 ieee 9 math_real 0 22 Sk6CSihbPL3?`2 -!s100 eHaYjXCDGoe_1D3KYczR;1 +DEx4 work 6 spwerr 0 22 O7PI=de<<0EG?V0=CGd=I3 +l89 +L36 +V0RhP;@:=E[FmfjSgFlfOD1 +!s100 nhfd3>@dJ`@HY1JCLn8S30 R9 32 R208 @@ -1611,26 +1613,69 @@ R211 !i113 1 R14 R15 +Espwerr_old +Z212 w1619639168 +Z213 DPx4 work 6 spwpkg 0 22 `Z443Q00J38VTS96N;::b1 +R3 +R4 +R5 +R6 +Z214 8D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/Testbench/spwerr_old.vhd +Z215 FD:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/Testbench/spwerr_old.vhd +l0 +L16 +V>EeH0L4:9Q[HoP>;9>5Ge0 +!s100 z6zNS4]W4ECMCZ8kK91KT2 +R9 +32 +Z216 !s110 1619639253 +!i10b 1 +Z217 !s108 1619639253.000000 +Z218 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/Testbench/spwerr_old.vhd| +Z219 !s107 D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/Testbench/spwerr_old.vhd| +!i113 1 +R14 +R15 +Aspwerr_arch +R213 +R3 +R4 +R5 +DEx4 work 10 spwerr_old 0 22 >EeH0L4:9Q[HoP>;9>5Ge0 +l82 +L35 +VK^1BMQ275TA6B8dU3b3 -!s100 LLZ=V>PDa[[1j97dOm@`@1 +VW_?GD0mjL<:4]8E^hEElQ1 +!s100 n:JhnN4jV^Sb@z4fS?gcg2 R9 32 -Z214 !s110 1611201886 +R208 !i10b 1 -Z215 !s108 1611201886.000000 -Z216 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwlink.vhd| -Z217 !s107 D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwlink.vhd| +R209 +Z223 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwlink.vhd| +Z224 !s107 D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwlink.vhd| !i113 1 R14 R15 @@ -1639,61 +1684,61 @@ R1 R3 R4 R5 -DEx4 work 7 spwlink 0 22 2N1zTA>MQ275TA6B8dU3b3 +DEx4 work 7 spwlink 0 22 W_?GD0mjL<:4]8E^hEElQ1 l86 L44 -V`W?mZ8ez>cg^Wa_Tg4^E:0 -!s100 OAmLa`A8PnZ>[^0cG@WZd3 +Vd814ME2POcaYXd3Od6mAW2 +!s100 P<9XALM4NId;LEN0DiV@g1 R9 32 -R214 +R208 !i10b 1 -R215 -R216 -R217 +R209 +R223 +R224 !i113 1 R14 R15 Pspwpkg R4 R5 -R59 +w1620844917 R6 -8D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwpkg.vhd -FD:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwpkg.vhd +8D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwpkg.vhd +FD:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwpkg.vhd l0 L8 -V`Z443Q00J38VTS96N;::b1 -!s100 >zgL?HaeAgWm2jbbNJJ[E1 +Va5Agjb>z@D5bUGlcjJGE70 +!s100 ?@6mjB>ZUkUMzhN;JJeL50 R9 32 R208 !i10b 1 R209 -!s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwpkg.vhd| -!s107 D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwpkg.vhd| +!s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwpkg.vhd| +!s107 D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwpkg.vhd| !i113 1 R14 R15 Espwram -R59 +Z225 w1620696986 R3 R4 R5 R6 -Z218 8D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwram.vhd -Z219 FD:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwram.vhd +Z226 8D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwram.vhd +Z227 FD:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwram.vhd l0 L10 -Vio9em64ZTWROlDce^iN>C2 -!s100 EUQJ1>]QNWjIj6Zn>4WQh1 +VVaWgfTL]S[_^lRAKm;F1o1 +!s100 GGF9naSBASYh4BMcACh[I1 R9 32 -R214 +R208 !i10b 1 -R215 -Z220 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwram.vhd| -Z221 !s107 D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwram.vhd| +R209 +Z228 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwram.vhd| +Z229 !s107 D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwram.vhd| !i113 1 R14 R15 @@ -1701,41 +1746,41 @@ Aspwram_arch R3 R4 R5 -DEx4 work 6 spwram 0 22 io9em64ZTWROlDce^iN>C2 -l35 +DEx4 work 6 spwram 0 22 VaWgfTL]S[_^lRAKm;F1o1 +l34 L28 -V]Ea3=B_9;5YVZ>JM20JKS2 -!s100 okl6iPF>3QaCh2Ldczd@T2 +VX=aJ53Fg]kioz][H56`iA0 +!s100 SC^=[a;9^LoK@7[Bez4b<3 R9 32 -R214 +R208 !i10b 1 -R215 -R220 -R221 +R209 +R228 +R229 !i113 1 R14 R15 Espwrecv -R59 +Z230 w1620845154 R1 R3 R4 R5 R6 -Z222 8D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecv.vhd -Z223 FD:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecv.vhd +Z231 8D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecv.vhd +Z232 FD:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecv.vhd l0 L16 -VnElH@Q?YVh1CAIm5BaGHT1 -!s100 MI=YX3oiWafcI@TofD^@]1 +V0N=^61_TNdo@c5QEZAOLV3 +!s100 z7b;ma8?[V@[6[1NGhjT31 R9 32 -R214 +Z233 !s110 1620848590 !i10b 1 -R215 -Z224 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecv.vhd| -Z225 !s107 D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecv.vhd| +R209 +Z234 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecv.vhd| +Z235 !s107 D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecv.vhd| !i113 1 R14 R15 @@ -1744,41 +1789,41 @@ R1 R3 R4 R5 -DEx4 work 7 spwrecv 0 22 nElH@Q?YVh1CAIm5BaGHT1 -l101 -L49 -Vnl_6EJj_Mfe`jb1=8h]bU3 -!s100 ^c3WTJ4Ao3z@Jg7kh6P:=2 +DEx4 work 7 spwrecv 0 22 0N=^61_TNdo@c5QEZAOLV3 +l97 +L45 +VP1:Jg<<6_2h1`VVT6[d>X3 +!s100 ;abmGgNM1jo>Q1 +DEx4 work 17 spwrecvfront_fast 0 22 3@LOQ_f^NBASG?oJI6[]k2 +l192 +L103 +VYZlJ@]O:kT0 R9 32 -R214 +R233 !i10b 1 -R215 -R228 -R229 +R239 +R240 +R241 !i113 1 R14 R15 Espwrecvfront_generic -R59 +Z242 w1620845105 R3 R4 R5 R6 -Z230 8D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecvfront_generic.vhd -Z231 FD:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecvfront_generic.vhd +Z243 8D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecvfront_generic.vhd +Z244 FD:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecvfront_generic.vhd l0 L16 -VEl06nCMSZ=?6GcFiGIA;D3 -!s100 cQd9MjILFQD4L=2ST@9`j1 +VaJl;8`RJcz=AK^]fK2 R9 32 -Z232 !s110 1611201887 +R233 !i10b 1 -R215 -Z233 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecvfront_generic.vhd| -Z234 !s107 D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecvfront_generic.vhd| +R239 +Z245 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecvfront_generic.vhd| +Z246 !s107 D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecvfront_generic.vhd| !i113 1 R14 R15 @@ -1828,41 +1873,41 @@ Aspwrecvfront_arch R3 R4 R5 -DEx4 work 20 spwrecvfront_generic 0 22 El06nCMSZ=?6GcFiGIA;D3 -l59 -L44 -VY?X;jNeQ`i00595];L?CD1 -!s100 @Qjz2IQjaJ]eejN]K`WIM3 +DEx4 work 20 spwrecvfront_generic 0 22 aJl;8`RJcz=AzO_m0 -!s100 UEcOc@Gh]7]d?njM3 +!s100 7VYlfT2l^T47<]G>zY?FA1 R9 32 -R232 +R233 !i10b 1 -R237 -R238 R239 +R250 +R251 !i113 1 R14 R15 Espwxmit -R59 +Z252 w1620696971 R1 R3 R4 R5 R6 -Z240 8D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwxmit.vhd -Z241 FD:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwxmit.vhd +Z253 8D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwxmit.vhd +Z254 FD:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwxmit.vhd l0 L13 -V0[CGLQJbUNZ37OLkdh=Ea3 -!s100 kd;DUhQR]86fMJ0WDD`c?2 +V63YFE3Lz@S@Y1@i_YH3Nk1 +!s100 2F:VP];z`G]DWH5j>HSD71 R9 32 -R232 +R233 !i10b 1 -R237 -Z242 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwxmit.vhd| -Z243 !s107 D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwxmit.vhd| +R239 +Z255 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwxmit.vhd| +Z256 !s107 D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwxmit.vhd| !i113 1 R14 R15 @@ -1914,41 +1959,41 @@ R1 R3 R4 R5 -DEx4 work 7 spwxmit 0 22 0[CGLQJbUNZ37OLkdh=Ea3 -l88 -L43 -VFUcVIIWTP7<7^D`21 +DEx4 work 7 spwxmit 0 22 63YFE3Lz@S@Y1@i_YH3Nk1 +l82 +L37 +VS@^Dfl7ZFmf1:jYQWdSl23 +!s100 VcRk<]dEFLdlXHHNjagRI3 R9 32 -R232 +R233 !i10b 1 -R237 -R242 -R243 +R239 +R255 +R256 !i113 1 R14 R15 Espwxmit_fast -R59 +Z257 w1620696974 R1 R3 R4 R5 R6 -Z244 8D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwxmit_fast.vhd -Z245 FD:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwxmit_fast.vhd +Z258 8D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwxmit_fast.vhd +Z259 FD:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwxmit_fast.vhd l0 L150 -Vb02QZKFLXHS9beURSKh1MkMPIPNFLfC1 +VNSOP9H:mn:z6eh7C0Q6B^1 +!s100 =>Zz9^okI>8b<0?;XTKKl2 R9 32 -R232 +R129 !i10b 1 -R237 -Z246 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwxmit_fast.vhd| -Z247 !s107 D:/rfranca/Development/GitHub/SimuCam_Development2/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwxmit_fast.vhd| +R239 +Z260 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwxmit_fast.vhd| +Z261 !s107 D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwxmit_fast.vhd| !i113 1 R14 R15 @@ -1957,41 +2002,41 @@ R1 R3 R4 R5 -DEx4 work 12 spwxmit_fast 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!s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/Testbench/testbench_top.vhd| +Z280 !s107 D:/rfranca/Development/GitHub/IWF_SimuCam_Development/FPGA_Developments/SpaceWire_Channel/Development/Testbench/testbench_top.vhd| !i113 1 R14 R15 Artl -R119 -R140 +R117 +R138 R2 -R161 -R60 +R160 +R58 R1 R3 R4 R5 -Z264 DEx4 work 13 testbench_top 0 22 Q79b=g>OPnQ>U_0@zceW;1 -l59 +Z281 DEx4 work 13 testbench_top 0 22 Q79b=g>OPnQ>U_0@zceW;1 +l67 L11 -Z265 Vj>Z[_`EZLBMCdnUzlJhcj1 -Z266 !s100 F50<2c>a139OXJcfZ>JLD1 +Z282 VI[VIK_CQK:[TG05ABW`X;1 +Z283 !s100 BiJbYO5A@>R0 CLK, - RST => RST, - DATA_IN_AVALON => AVALON_SLAVE_WRITEDATA, - ADDRESS_IN_AVALON => AVALON_SLAVE_ADDRESS, - ENABLE_DATA_IN_AVALON => AVALON_SLAVE_WRITE, - SEG_DATA => SEG_DATA, - SEG1_ON_OFF => SEG1_ON_OFF, - SEG1_UPDATE => SEG1_UPDATE, - SEG1_TEST => SEG1_TEST, - SEG0_ON_OFF => SEG0_ON_OFF, - SEG0_UPDATE => SEG0_UPDATE, - SEG0_TEST => SEG0_TEST - ); - - DOUBLE_DABBLE : ENTITY DOUBLE_DABBLE_8BIT - PORT MAP( - CLK => CLK, - RST => RST, - DD_ENABLE => DD_ENABLE, - DD_IDLE => DD_IDLE, - DD_CLEAR => DD_CLEAR, - DD_INTEGER_IN => DD_INTEGER, - DD_BCD2_OUT => OPEN, - DD_BCD1_OUT => DD_BCD1, - DD_BCD0_OUT => DD_BCD0 - ); - - SSDP1 : ENTITY SEVEN_SEG_DPS - PORT MAP( - CLK => CLK, - RST => RST, - SEG_ENABLE => SEG1_ENABLE, - SEG_BCD_IN => SEG1_BCD_IN, - SEG_DBITS_OUT => SEG1_DBITS_OUT - ); - - SSDP0 : ENTITY SEVEN_SEG_DPS - PORT MAP( - CLK => CLK, - RST => RST, - SEG_ENABLE => SEG0_ENABLE, - SEG_BCD_IN => SEG0_BCD_IN, - SEG_DBITS_OUT => SEG0_DBITS_OUT - ); - - GLOBAL : PROCESS (CLK, RST) - VARIABLE PAST_INTEGER : UNSIGNED(7 DOWNTO 0) := (OTHERS => '0'); - VARIABLE DELAY : STD_LOGIC := '0'; - BEGIN - IF (RST = '1') THEN - PAST_INTEGER := (OTHERS => '0'); - DD_ENABLE <= '0'; - DD_CLEAR <= '1'; - SEG1_ENABLE <= '0'; - SEG0_ENABLE <= '0'; - STATE_MACHINE <= S_STANDBY; - ELSIF (RISING_EDGE(CLK)) THEN - CASE STATE_MACHINE IS - - WHEN S_STANDBY => - DD_ENABLE <= '0'; - DD_CLEAR <= '0'; - SEG1_ENABLE <= '0'; - SEG0_ENABLE <= '0'; - IF ((SEG_DATA /= PAST_INTEGER) AND (DD_IDLE = '1')) THEN - PAST_INTEGER := SEG_DATA; - DD_INTEGER <= SEG_DATA; - DD_ENABLE <= '1'; - DELAY := '1'; - STATE_MACHINE <= S_WORKING; - ELSE - STATE_MACHINE <= S_STANDBY; - END IF; - - WHEN S_WORKING => - DD_ENABLE <= '0'; - IF (DELAY = '1') THEN - DELAY := '0'; - STATE_MACHINE <= S_WORKING; - ELSE - IF (DD_IDLE = '1') THEN - STATE_MACHINE <= S_UPDATE; - ELSE - STATE_MACHINE <= S_WORKING; - END IF; - END IF; - - WHEN S_UPDATE => - - SEG1_BCD_IN <= DD_BCD1; - IF (SEG1_UPDATE = '1') THEN - SEG1_ENABLE <= '1'; - END IF; - SEG0_BCD_IN <= DD_BCD0; - IF (SEG0_UPDATE = '1') THEN - SEG0_ENABLE <= '1'; - END IF; - DD_CLEAR <= '1'; - STATE_MACHINE <= S_STANDBY; - - END CASE; - END IF; - END PROCESS GLOBAL; - - SEVEN_SEG_DSP1_OUT <= - X"FF" WHEN (SEG1_ON_OFF = '0') ELSE - X"00" WHEN ((SEG1_ON_OFF = '1') AND (SEG1_TEST = '1')) ELSE - SEG1_DBITS_OUT WHEN ((SEG1_ON_OFF = '1') AND (SEG1_TEST = '0')); - - SEVEN_SEG_DSP0_OUT <= - X"FF" WHEN (SEG0_ON_OFF = '0') ELSE - X"00" WHEN ((SEG0_ON_OFF = '1') AND (SEG0_TEST = '1')) ELSE - SEG0_DBITS_OUT WHEN ((SEG0_ON_OFF = '1') AND (SEG0_TEST = '0')); - -END ARCHITECTURE TOP; +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; +USE WORK.ALL; + +ENTITY SEVEN_SEG_TOP IS + PORT ( + +------------------------------------------------------------------------------- +-- GLOBAL +------------------------------------------------------------------------------- + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + +------------------------------------------------------------------------------- +-- AVALON +------------------------------------------------------------------------------- + AVALON_SLAVE_ADDRESS : IN STD_LOGIC; + AVALON_SLAVE_WRITE : IN STD_LOGIC; + AVALON_SLAVE_WRITEDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + +------------------------------------------------------------------------------- +-- OUTPUTS +------------------------------------------------------------------------------- + SEVEN_SEG_DSP1_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + SEVEN_SEG_DSP0_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + + ); + +END ENTITY SEVEN_SEG_TOP; + + +ARCHITECTURE TOP OF SEVEN_SEG_TOP IS + + ------------------------------------------------------------------------------- + -- SEVEN SEGMENT REGISTER + ------------------------------------------------------------------------------- + SIGNAL SEG_DATA : UNSIGNED(7 DOWNTO 0); + SIGNAL SEG1_ON_OFF : STD_LOGIC; + SIGNAL SEG1_UPDATE : STD_LOGIC; + SIGNAL SEG1_TEST : STD_LOGIC; + SIGNAL SEG0_ON_OFF : STD_LOGIC; + SIGNAL SEG0_UPDATE : STD_LOGIC; + SIGNAL SEG0_TEST : STD_LOGIC; + + ------------------------------------------------------------------------------- + -- DOUBLE DABBLE + ------------------------------------------------------------------------------- + SIGNAL DD_ENABLE : STD_LOGIC; + SIGNAL DD_IDLE : STD_LOGIC; + SIGNAL DD_CLEAR : STD_LOGIC; + SIGNAL DD_INTEGER : UNSIGNED(7 DOWNTO 0); + SIGNAL DD_BCD1 : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL DD_BCD0 : STD_LOGIC_VECTOR(3 DOWNTO 0); + + ------------------------------------------------------------------------------- + -- SEVEN SEGMENT DISPLAY 1 + ------------------------------------------------------------------------------- + SIGNAL SEG1_ENABLE : STD_LOGIC; + SIGNAL SEG1_BCD_IN : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL SEG1_DBITS_OUT : STD_LOGIC_VECTOR(7 DOWNTO 0); + + ------------------------------------------------------------------------------- + -- SEVEN SEGMENT DISPLAY 0 + ------------------------------------------------------------------------------- + SIGNAL SEG0_ENABLE : STD_LOGIC; + SIGNAL SEG0_BCD_IN : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL SEG0_DBITS_OUT : STD_LOGIC_VECTOR(7 DOWNTO 0); + + ------------------------------------------------------------------------------- + -- STATE_MACHINE + ------------------------------------------------------------------------------- + + TYPE SST_STATE_MACHINE IS ( + S_STANDBY, + S_WORKING, + S_UPDATE + ); + SIGNAL STATE_MACHINE : SST_STATE_MACHINE := S_STANDBY; + +BEGIN + + SSDP_REGISTER : ENTITY SEVEN_SEG_REGISTER + PORT MAP( + CLK => CLK, + RST => RST, + DATA_IN_AVALON => AVALON_SLAVE_WRITEDATA, + ADDRESS_IN_AVALON => AVALON_SLAVE_ADDRESS, + ENABLE_DATA_IN_AVALON => AVALON_SLAVE_WRITE, + SEG_DATA => SEG_DATA, + SEG1_ON_OFF => SEG1_ON_OFF, + SEG1_UPDATE => SEG1_UPDATE, + SEG1_TEST => SEG1_TEST, + SEG0_ON_OFF => SEG0_ON_OFF, + SEG0_UPDATE => SEG0_UPDATE, + SEG0_TEST => SEG0_TEST + ); + + DOUBLE_DABBLE : ENTITY DOUBLE_DABBLE_8BIT + PORT MAP( + CLK => CLK, + RST => RST, + DD_ENABLE => DD_ENABLE, + DD_IDLE => DD_IDLE, + DD_CLEAR => DD_CLEAR, + DD_INTEGER_IN => DD_INTEGER, + DD_BCD2_OUT => OPEN, + DD_BCD1_OUT => DD_BCD1, + DD_BCD0_OUT => DD_BCD0 + ); + + SSDP1 : ENTITY SEVEN_SEG_DPS + PORT MAP( + CLK => CLK, + RST => RST, + SEG_ENABLE => SEG1_ENABLE, + SEG_BCD_IN => SEG1_BCD_IN, + SEG_DBITS_OUT => SEG1_DBITS_OUT + ); + + SSDP0 : ENTITY SEVEN_SEG_DPS + PORT MAP( + CLK => CLK, + RST => RST, + SEG_ENABLE => SEG0_ENABLE, + SEG_BCD_IN => SEG0_BCD_IN, + SEG_DBITS_OUT => SEG0_DBITS_OUT + ); + + GLOBAL : PROCESS (CLK, RST) + VARIABLE PAST_INTEGER : UNSIGNED(7 DOWNTO 0) := (OTHERS => '0'); + VARIABLE DELAY : STD_LOGIC := '0'; + BEGIN + IF (RST = '1') THEN + PAST_INTEGER := (OTHERS => '0'); + DD_ENABLE <= '0'; + DD_CLEAR <= '1'; + SEG1_ENABLE <= '0'; + SEG0_ENABLE <= '0'; + STATE_MACHINE <= S_STANDBY; + ELSIF (RISING_EDGE(CLK)) THEN + CASE STATE_MACHINE IS + + WHEN S_STANDBY => + DD_ENABLE <= '0'; + DD_CLEAR <= '0'; + SEG1_ENABLE <= '0'; + SEG0_ENABLE <= '0'; + IF ((SEG_DATA /= PAST_INTEGER) AND (DD_IDLE = '1')) THEN + PAST_INTEGER := SEG_DATA; + DD_INTEGER <= SEG_DATA; + DD_ENABLE <= '1'; + DELAY := '1'; + STATE_MACHINE <= S_WORKING; + ELSE + STATE_MACHINE <= S_STANDBY; + END IF; + + WHEN S_WORKING => + DD_ENABLE <= '0'; + IF (DELAY = '1') THEN + DELAY := '0'; + STATE_MACHINE <= S_WORKING; + ELSE + IF (DD_IDLE = '1') THEN + STATE_MACHINE <= S_UPDATE; + ELSE + STATE_MACHINE <= S_WORKING; + END IF; + END IF; + + WHEN S_UPDATE => + + SEG1_BCD_IN <= DD_BCD1; + IF (SEG1_UPDATE = '1') THEN + SEG1_ENABLE <= '1'; + END IF; + SEG0_BCD_IN <= DD_BCD0; + IF (SEG0_UPDATE = '1') THEN + SEG0_ENABLE <= '1'; + END IF; + DD_CLEAR <= '1'; + STATE_MACHINE <= S_STANDBY; + + END CASE; + END IF; + END PROCESS GLOBAL; + + SEVEN_SEG_DSP1_OUT <= + X"FF" WHEN (RST = '1') ELSE + X"FF" WHEN (SEG1_ON_OFF = '0') ELSE + X"00" WHEN ((SEG1_ON_OFF = '1') AND (SEG1_TEST = '1')) ELSE + SEG1_DBITS_OUT WHEN ((SEG1_ON_OFF = '1') AND (SEG1_TEST = '0')) ELSE + X"FF"; + + SEVEN_SEG_DSP0_OUT <= + X"FF" WHEN (RST = '1') ELSE + X"FF" WHEN (SEG0_ON_OFF = '0') ELSE + X"00" WHEN ((SEG0_ON_OFF = '1') AND (SEG0_TEST = '1')) ELSE + SEG0_DBITS_OUT WHEN ((SEG0_ON_OFF = '1') AND (SEG0_TEST = '0')) ELSE + X"FF"; + +END ARCHITECTURE TOP; diff --git a/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwerr.vhd b/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwerr.vhd index 3ad602e4d..03ffa099f 100644 --- a/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwerr.vhd +++ b/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwerr.vhd @@ -89,7 +89,7 @@ architecture spwerr_arch of spwerr is begin -- Combinatorial process - process(r, err_usr_i, err_link_i) is + process(r, rst, err_usr_i, err_link_i) is variable v : regs_type; begin v := r; @@ -319,16 +319,25 @@ begin end if; end if; + -- Reset + if rst = '1' then + v := regs_reset; + err_usr_o.err_stat_o <= stby; + err_link_o.err_disc_o <= '0'; + err_link_o.err_par_o <= '0'; + err_link_o.err_esc_o <= '0'; + err_link_o.err_credit_o <= '0'; + err_link_o.err_ch_seq_o <= '0'; + end if; + -- Update future state regs. rin <= v; end process; - -- Sequential process - rst, update regs. - process(clk, rst) is + -- Sequential process - update regs. + process(clk) is begin - if (rst = '1') then - r <= regs_reset; - elsif rising_edge(clk) then + if rising_edge(clk) then r <= rin; end if; end process; diff --git a/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwlink.vhd b/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwlink.vhd index 8670ffd27..307ed77ed 100644 --- a/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwlink.vhd +++ b/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwlink.vhd @@ -12,324 +12,320 @@ use work.spwpkg.all; entity spwlink is - generic( - -- Reset time expressed in system clock cycles. - -- Should be 6.4 us (5.82 us .. 7.2 us) according to the standard. - reset_time : integer - ); - - port( - -- System clock. - clk : in std_logic; - -- Synchronous reset (active-high). - -- Disconnects, resets error conditions, puts the link state machine - -- in state ErrorReset. - rst : in std_logic; - -- Link level inputs. - linki : in spw_link_in_type; - -- Link level outputs. - linko : out spw_link_out_type; - -- Receiver enable signal to spwrecv. - rxen : out std_logic; - -- Output signals from spwrecv. - recvo : in spw_recv_out_type; - -- Input signals for spwxmit. - xmiti : out spw_xmit_in_type; - -- Output signals from spwxmit. - xmito : in spw_xmit_out_type - ); + generic( + -- Reset time expressed in system clock cycles. + -- Should be 6.4 us (5.82 us .. 7.2 us) according to the standard. + reset_time : integer + ); + + port( + -- System clock. + clk : in std_logic; + -- Synchronous reset (active-high). + -- Disconnects, resets error conditions, puts the link state machine + -- in state ErrorReset. + rst : in std_logic; + -- Link level inputs. + linki : in spw_link_in_type; + -- Link level outputs. + linko : out spw_link_out_type; + -- Receiver enable signal to spwrecv. + rxen : out std_logic; + -- Output signals from spwrecv. + recvo : in spw_recv_out_type; + -- Input signals for spwxmit. + xmiti : out spw_xmit_in_type; + -- Output signals from spwxmit. + xmito : in spw_xmit_out_type + ); end entity spwlink; architecture spwlink_arch of spwlink is - -- Convert boolean to std_logic. - type bool_to_logic_type is array (boolean) of std_ulogic; - constant bool_to_logic : bool_to_logic_type := (false => '0', true => '1'); - - -- State machine. - type state_type is ( - S_ErrorReset, S_ErrorWait, S_Ready, S_Started, S_Connecting, S_Run); - - -- Registers - type regs_type is record - -- state machine - state : state_type; - -- credit accounting - tx_credit : unsigned(5 downto 0); - rx_credit : unsigned(5 downto 0); - errcred : std_ulogic; - -- reset timer - timercnt : unsigned(10 downto 0); - timerdone : std_ulogic; - -- signal to transmitter - xmit_fct_in : std_ulogic; - end record; - - -- Initial state - constant regs_reset : regs_type := ( - state => S_ErrorReset, - tx_credit => "000000", - rx_credit => "000000", - errcred => '0', - timercnt => to_unsigned(reset_time, 11), - timerdone => '0', - xmit_fct_in => '0'); - - signal r : regs_type := regs_reset; - signal rin : regs_type; - - -- Internal interface - spwerr <-> spwlink - signal link_to_err : spwerr_from_link_type; - signal err_to_link : spwerr_to_link_type; + -- Convert boolean to std_logic. + type bool_to_logic_type is array (boolean) of std_ulogic; + constant bool_to_logic : bool_to_logic_type := (false => '0', true => '1'); + + -- State machine. + type state_type is ( + S_ErrorReset, S_ErrorWait, S_Ready, S_Started, S_Connecting, S_Run); + + -- Registers + type regs_type is record + -- state machine + state : state_type; + -- credit accounting + tx_credit : unsigned(5 downto 0); + rx_credit : unsigned(5 downto 0); + errcred : std_ulogic; + -- reset timer + timercnt : unsigned(10 downto 0); + timerdone : std_ulogic; + -- signal to transmitter + xmit_fct_in : std_ulogic; + end record; + + -- Initial state + constant regs_reset : regs_type := ( + state => S_ErrorReset, + tx_credit => "000000", + rx_credit => "000000", + errcred => '0', + timercnt => to_unsigned(reset_time, 11), + timerdone => '0', + xmit_fct_in => '0'); + + signal r : regs_type := regs_reset; + signal rin : regs_type; + + -- Internal interface - spwerr <-> spwlink + signal link_to_err : spwerr_from_link_type; + signal err_to_link : spwerr_to_link_type; begin - -- Instantiate error controller. - err_inst : spwerr - port map( - clk => clk, - rst => rst, - err_link_i => link_to_err, - err_link_o => err_to_link, - err_usr_i => linki.err_usr_i, - err_usr_o => linko.err_usr_o - ); - - -- Combinatorial process - process(r, rst, linki, recvo, xmito, err_to_link) is - variable v : regs_type; - variable v_timerrst : std_logic; - variable v_xmiti : spw_xmit_in_type; - begin - v := r; - v_timerrst := '0'; - - -- State machine. - case r.state is - - when S_ErrorReset => - -- Wait for timer. - if r.timercnt = 0 then - v.state := S_ErrorWait; - v_timerrst := '1'; - end if; - v.errcred := '0'; - v.xmit_fct_in := '0'; - - when S_ErrorWait => - -- Wait for 2 timer periods. - if ((recvo.errdisc or recvo.errpar or recvo.erresc) = '1') or - ((recvo.gotfct or recvo.tick_out or recvo.rxchar) = '1') then - -- Note: spwrecv will never issue errpar, erresc, gotfct, - -- tick_out or rxchar before the first NULL has been seen. - -- Therefore it's ok here to bail on those conditions - -- without explicitly testing got_null. - v.state := S_ErrorReset; -- error, go back to reset - v_timerrst := '1'; - elsif r.timercnt = 0 then - if r.timerdone = '1' then - v.state := S_Ready; - v_timerrst := '1'; - end if; - end if; - - when S_Ready => - -- Wait for link start. - if ((recvo.errdisc or recvo.errpar or recvo.erresc) = '1') or - ((recvo.gotfct or recvo.tick_out or recvo.rxchar) = '1') then - v.state := S_ErrorReset; -- error, go back to reset - v_timerrst := '1'; - elsif (linki.linkdis = '0') and (r.xmit_fct_in = '1') and - ((linki.linkstart or (linki.autostart and recvo.gotnull)) = '1') then - v.state := S_Started; -- link enabled; start sending NULL - v_timerrst := '1'; - end if; - - when S_Started => - -- Wait for NULL. - if ((recvo.errdisc or recvo.errpar or recvo.erresc) = '1') or - ((recvo.gotfct or recvo.tick_out or recvo.rxchar) = '1') or - ((r.timercnt = 0) and r.timerdone = '1') then - v.state := S_ErrorReset; -- error, go back to reset - v_timerrst := '1'; - elsif recvo.gotnull = '1' then - v.state := S_Connecting; -- received null, continue - v_timerrst := '1'; - end if; - - when S_Connecting => - -- Wait for FCT. - if ((recvo.errdisc or recvo.errpar or recvo.erresc) = '1') or - ((recvo.tick_out or recvo.rxchar) = '1') or - ((r.timercnt = 0) and r.timerdone = '1') then - v.state := S_ErrorReset; -- error, go back to reset - v_timerrst := '1'; - elsif recvo.gotfct = '1' then - v.state := S_Run; -- got FCT, init completed - end if; - - when S_Run => - -- All is well. - if ((recvo.errdisc or recvo.errpar or recvo.erresc) = '1') or (r.errcred = '1') or - -- Spwerr can cause a disconnetion by forcing link disable - ((linki.linkdis or err_to_link.err_disc_o) = '1') then - v.state := S_ErrorReset; -- error, go back to reset - v_timerrst := '1'; - end if; - - end case; - - -- Update credit counters. - if r.state = S_ErrorReset then - - -- reset credit - v.tx_credit := to_unsigned(0, v.tx_credit'length); - v.rx_credit := to_unsigned(0, v.rx_credit'length); - - else - - -- update TX credit - if recvo.gotfct = '1' then - -- just received a FCT token - v.tx_credit := v.tx_credit + to_unsigned(8, v.tx_credit'length); - if r.tx_credit > 48 then - -- received too many FCT tokens - v.errcred := '1'; - end if; - end if; - -- Only decrements tx_credit without char sequence error injection - if (err_to_link.err_ch_seq_o = '0') then - if xmito.txack = '1' then - -- just sent one byte - v.tx_credit := v.tx_credit - to_unsigned(1, v.tx_credit'length); - end if; - end if; - - -- Only increments rx_credit without credit error injection - if (err_to_link.err_credit_o = '0') then - -- update RX credit after sending FCT - if xmito.fctack = '1' then - -- just sent a FCT token - v.rx_credit := v.rx_credit + to_unsigned(8, v.rx_credit'length); - end if; - end if; - - -- decide about sending FCT tokens - v.xmit_fct_in := bool_to_logic((v.rx_credit <= 48) and (v.rx_credit + to_unsigned(8, v.rx_credit'length) <= unsigned(linki.rxroom))); - - -- update RX credit after receiving character - if recvo.rxchar = '1' then - -- just received a character - v.rx_credit := v.rx_credit - to_unsigned(1, v.rx_credit'length); - if r.rx_credit = 0 then - -- remote transmitter violated its credit - v.errcred := '1'; - end if; - end if; - - end if; - - -- Update the initializaton reset timer. - if v_timerrst = '1' then - v.timercnt := to_unsigned(reset_time, v.timercnt'length); - v.timerdone := '0'; - else - if r.timercnt = 0 then - v.timercnt := to_unsigned(reset_time, v.timercnt'length); - v.timerdone := '1'; - else - v.timercnt := r.timercnt - 1; - end if; - end if; - - -- Reset - if rst = '1' then - v := regs_reset; - end if; - - -- Drive link level outputs. - linko.started <= bool_to_logic(r.state = S_Started); - linko.connecting <= bool_to_logic(r.state = S_Connecting); - linko.running <= bool_to_logic(r.state = S_Run); - linko.errdisc <= recvo.errdisc and bool_to_logic(r.state = S_Run); - linko.errpar <= recvo.errpar and bool_to_logic(r.state = S_Run); - linko.erresc <= recvo.erresc and bool_to_logic(r.state = S_Run); - linko.errcred <= r.errcred; - linko.txack <= xmito.txack; - linko.tick_out <= recvo.tick_out and bool_to_logic(r.state = S_Run); - linko.ctrl_out <= recvo.ctrl_out; - linko.time_out <= recvo.time_out; - linko.rxchar <= recvo.rxchar and bool_to_logic(r.state = S_Run); - linko.rxflag <= recvo.rxflag; - linko.rxdata <= recvo.rxdata; - - -- Drive receiver inputs. - rxen <= bool_to_logic(r.state /= S_ErrorReset); - - -- Drive transmitter input signals. - -- v_xmiti intercepts signals - v_xmiti.txen := bool_to_logic(r.state = S_Started or r.state = S_Connecting or r.state = S_Run); - v_xmiti.stnull := bool_to_logic(r.state = S_Started); - v_xmiti.stfct := bool_to_logic(r.state = S_Connecting); - v_xmiti.fct_in := r.xmit_fct_in; - v_xmiti.tick_in := linki.tick_in and bool_to_logic(r.state = S_Run); - v_xmiti.ctrl_in := linki.ctrl_in; - v_xmiti.time_in := linki.time_in; - v_xmiti.txwrite := linki.txwrite and bool_to_logic(r.tx_credit /= 0); - v_xmiti.txflag := linki.txflag; - v_xmiti.txdata := linki.txdata; - - -- Logic for parity, escape, charactere sequence and credit errors: update v_xmiti. - if ((err_to_link.err_par_o or err_to_link.err_esc_o) = '1') then - -- For parity and escape errors (treated directly by xmiti unity), send only null condition is a must. - v_xmiti.stnull := '1'; - elsif (err_to_link.err_credit_o = '1') then - -- Prepare conditions to send 8 x fct - -- No need to use counter or fsm, because err_credit_o pulse is long enough. - v_xmiti.tick_in := '0'; - v_xmiti.fct_in := '1'; - elsif (err_to_link.err_ch_seq_o = '1') then - -- Prepare conditions to send a N-char outside run state - v_xmiti.fct_in := '0'; - -- Send EOP outside run state - v_xmiti.txflag := '1'; - v_xmiti.txdata := "00000000"; - v_xmiti.txwrite := '1'; - end if; - - -- Write back to xmiti inputs. - -- If there is no error injection request, it is a simple bypass. - xmiti.txen <= v_xmiti.txen; - xmiti.stnull <= v_xmiti.stnull; - xmiti.stfct <= v_xmiti.stfct; - xmiti.fct_in <= v_xmiti.fct_in; - xmiti.tick_in <= v_xmiti.tick_in; - xmiti.ctrl_in <= v_xmiti.ctrl_in; - xmiti.time_in <= v_xmiti.time_in; - xmiti.txwrite <= v_xmiti.txwrite; - xmiti.txflag <= v_xmiti.txflag; - xmiti.txdata <= v_xmiti.txdata; - -- Parity, escape, char sequence, and credit error injection must also be treated directly by xmit unity - xmiti.err_inj_par <= err_to_link.err_par_o; - xmiti.err_inj_esc <= err_to_link.err_esc_o; - xmiti.err_inj_ch_seq <= err_to_link.err_ch_seq_o; - xmiti.err_inj_credit <= err_to_link.err_credit_o; - - -- Drive spwerr inputs. - link_to_err.run_state <= bool_to_logic(r.state = S_Run); - link_to_err.start_or_conn_state <= bool_to_logic(r.state = S_Started or r.state = S_Connecting); - - -- Update registers. - rin <= v; - end process; - - -- Update registers. - process(clk) is - begin - if rising_edge(clk) then - r <= rin; - end if; - end process; + -- Instantiate error controller. + err_inst : spwerr + port map( + clk => clk, + rst => rst, + err_link_i => link_to_err, + err_link_o => err_to_link, + err_usr_i => linki.err_usr_i, + err_usr_o => linko.err_usr_o + ); + + -- Combinatorial process + process(r, rst, linki, recvo, xmito, err_to_link) is + variable v : regs_type; + variable v_timerrst : std_logic; + variable v_xmiti : spw_xmit_in_type; + begin + v := r; + v_timerrst := '0'; + + -- State machine. + case r.state is + + when S_ErrorReset => + -- Wait for timer. + if r.timercnt = 0 then + v.state := S_ErrorWait; + v_timerrst := '1'; + end if; + v.errcred := '0'; + v.xmit_fct_in := '0'; + + when S_ErrorWait => + -- Wait for 2 timer periods. + if ((recvo.errdisc or recvo.errpar or recvo.erresc) = '1') or ((recvo.gotfct or recvo.tick_out or recvo.rxchar) = '1') then + -- Note: spwrecv will never issue errpar, erresc, gotfct, + -- tick_out or rxchar before the first NULL has been seen. + -- Therefore it's ok here to bail on those conditions + -- without explicitly testing got_null. + v.state := S_ErrorReset; -- error, go back to reset + v_timerrst := '1'; + elsif r.timercnt = 0 then + if r.timerdone = '1' then + v.state := S_Ready; + v_timerrst := '1'; + end if; + end if; + + when S_Ready => + -- Wait for link start. + if ((recvo.errdisc or recvo.errpar or recvo.erresc) = '1') or ((recvo.gotfct or recvo.tick_out or recvo.rxchar) = '1') then + v.state := S_ErrorReset; -- error, go back to reset + v_timerrst := '1'; + elsif (linki.linkdis = '0') and (r.xmit_fct_in = '1') and ((linki.linkstart or (linki.autostart and recvo.gotnull)) = '1') then + v.state := S_Started; -- link enabled; start sending NULL + v_timerrst := '1'; + end if; + + when S_Started => + -- Wait for NULL. + if ((recvo.errdisc or recvo.errpar or recvo.erresc) = '1') or ((recvo.gotfct or recvo.tick_out or recvo.rxchar) = '1') or ((r.timercnt = 0) and r.timerdone = '1') then + v.state := S_ErrorReset; -- error, go back to reset + v_timerrst := '1'; + elsif recvo.gotnull = '1' then + v.state := S_Connecting; -- received null, continue + v_timerrst := '1'; + end if; + + when S_Connecting => + -- Wait for FCT. + if ((recvo.errdisc or recvo.errpar or recvo.erresc) = '1') or ((recvo.tick_out or recvo.rxchar) = '1') or ((r.timercnt = 0) and r.timerdone = '1') then + v.state := S_ErrorReset; -- error, go back to reset + v_timerrst := '1'; + elsif recvo.gotfct = '1' then + v.state := S_Run; -- got FCT, init completed + end if; + + when S_Run => + -- All is well. + if ((recvo.errdisc or recvo.errpar or recvo.erresc) = '1') or (r.errcred = '1') or -- Spwerr can cause a disconnetion by forcing link disable + ((linki.linkdis or err_to_link.err_disc_o) = '1') then + v.state := S_ErrorReset; -- error, go back to reset + v_timerrst := '1'; + end if; + + when others => + v.state := S_ErrorReset; -- recover from invalid state + v_timerrst := '1'; + + end case; + + -- Update credit counters. + if r.state = S_ErrorReset then + + -- reset credit + v.tx_credit := to_unsigned(0, v.tx_credit'length); + v.rx_credit := to_unsigned(0, v.rx_credit'length); + + else + + -- update TX credit + if recvo.gotfct = '1' then + -- just received a FCT token + v.tx_credit := v.tx_credit + to_unsigned(8, v.tx_credit'length); + if r.tx_credit > 48 then + -- received too many FCT tokens + v.errcred := '1'; + end if; + end if; + -- Only decrements tx_credit without char sequence error injection + if (err_to_link.err_ch_seq_o = '0') then + if xmito.txack = '1' then + -- just sent one byte + v.tx_credit := v.tx_credit - to_unsigned(1, v.tx_credit'length); + end if; + end if; + + -- Only increments rx_credit without credit error injection + if (err_to_link.err_credit_o = '0') then + -- update RX credit after sending FCT + if xmito.fctack = '1' then + -- just sent a FCT token + v.rx_credit := v.rx_credit + to_unsigned(8, v.rx_credit'length); + end if; + end if; + + -- decide about sending FCT tokens + v.xmit_fct_in := bool_to_logic((v.rx_credit <= 48) and (v.rx_credit + to_unsigned(8, v.rx_credit'length) <= unsigned(linki.rxroom))); + + -- update RX credit after receiving character + if recvo.rxchar = '1' then + -- just received a character + v.rx_credit := v.rx_credit - to_unsigned(1, v.rx_credit'length); + if r.rx_credit = 0 then + -- remote transmitter violated its credit + v.errcred := '1'; + end if; + end if; + + end if; + + -- Update the initializaton reset timer. + if v_timerrst = '1' then + v.timercnt := to_unsigned(reset_time, v.timercnt'length); + v.timerdone := '0'; + else + if r.timercnt = 0 then + v.timercnt := to_unsigned(reset_time, v.timercnt'length); + v.timerdone := '1'; + else + v.timercnt := r.timercnt - 1; + end if; + end if; + + -- Reset + if rst = '1' then + v := regs_reset; + end if; + + -- Drive link level outputs. + linko.started <= bool_to_logic(r.state = S_Started); + linko.connecting <= bool_to_logic(r.state = S_Connecting); + linko.running <= bool_to_logic(r.state = S_Run); + linko.errdisc <= recvo.errdisc and bool_to_logic(r.state = S_Run); + linko.errpar <= recvo.errpar and bool_to_logic(r.state = S_Run); + linko.erresc <= recvo.erresc and bool_to_logic(r.state = S_Run); + linko.errcred <= r.errcred; + linko.txack <= xmito.txack; + linko.tick_out <= recvo.tick_out and bool_to_logic(r.state = S_Run); + linko.ctrl_out <= recvo.ctrl_out; + linko.time_out <= recvo.time_out; + linko.rxchar <= recvo.rxchar and bool_to_logic(r.state = S_Run); + linko.rxflag <= recvo.rxflag; + linko.rxdata <= recvo.rxdata; + + -- Drive receiver inputs. + rxen <= bool_to_logic(r.state /= S_ErrorReset); + + -- Drive transmitter input signals. + -- v_xmiti intercepts signals + v_xmiti.txen := bool_to_logic(r.state = S_Started or r.state = S_Connecting or r.state = S_Run); + v_xmiti.stnull := bool_to_logic(r.state = S_Started); + v_xmiti.stfct := bool_to_logic(r.state = S_Connecting); + v_xmiti.fct_in := r.xmit_fct_in; + v_xmiti.tick_in := linki.tick_in and bool_to_logic(r.state = S_Run); + v_xmiti.ctrl_in := linki.ctrl_in; + v_xmiti.time_in := linki.time_in; + v_xmiti.txwrite := linki.txwrite and bool_to_logic(r.tx_credit /= 0); + v_xmiti.txflag := linki.txflag; + v_xmiti.txdata := linki.txdata; + + -- Logic for parity, escape, charactere sequence and credit errors: update v_xmiti. + if ((err_to_link.err_par_o or err_to_link.err_esc_o) = '1') then + -- For parity and escape errors (treated directly by xmiti unity), send only null condition is a must. + v_xmiti.stnull := '1'; + elsif (err_to_link.err_credit_o = '1') then + -- Prepare conditions to send 8 x fct + -- No need to use counter or fsm, because err_credit_o pulse is long enough. + v_xmiti.tick_in := '0'; + v_xmiti.fct_in := '1'; + elsif (err_to_link.err_ch_seq_o = '1') then + -- Prepare conditions to send a N-char outside run state + v_xmiti.fct_in := '0'; + -- Send EOP outside run state + v_xmiti.txflag := '1'; + v_xmiti.txdata := "00000000"; + v_xmiti.txwrite := '1'; + end if; + + -- Write back to xmiti inputs. + -- If there is no error injection request, it is a simple bypass. + xmiti.txen <= v_xmiti.txen; + xmiti.stnull <= v_xmiti.stnull; + xmiti.stfct <= v_xmiti.stfct; + xmiti.fct_in <= v_xmiti.fct_in; + xmiti.tick_in <= v_xmiti.tick_in; + xmiti.ctrl_in <= v_xmiti.ctrl_in; + xmiti.time_in <= v_xmiti.time_in; + xmiti.txwrite <= v_xmiti.txwrite; + xmiti.txflag <= v_xmiti.txflag; + xmiti.txdata <= v_xmiti.txdata; + -- Parity, escape, char sequence, and credit error injection must also be treated directly by xmit unity + xmiti.err_inj_par <= err_to_link.err_par_o; + xmiti.err_inj_esc <= err_to_link.err_esc_o; + xmiti.err_inj_ch_seq <= err_to_link.err_ch_seq_o; + xmiti.err_inj_credit <= err_to_link.err_credit_o; + + -- Drive spwerr inputs. + link_to_err.run_state <= bool_to_logic(r.state = S_Run); + link_to_err.start_or_conn_state <= bool_to_logic(r.state = S_Started or r.state = S_Connecting); + + -- Update registers. + rin <= v; + end process; + + -- Update registers. + process(clk) is + begin + if rising_edge(clk) then + r <= rin; + end if; + end process; end architecture spwlink_arch; diff --git a/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwpkg.vhd b/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwpkg.vhd index b4fe8ffdc..6c2ad076f 100644 --- a/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwpkg.vhd +++ b/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwpkg.vhd @@ -7,454 +7,456 @@ use ieee.std_logic_1164.all; package spwpkg is - -- Indicates a platform-specific implementation. - type spw_implementation_type is (impl_generic, impl_fast); + -- Indicates a platform-specific implementation. + type spw_implementation_type is (impl_generic, impl_fast); - -- Enumerated type for spwerr error selection values - -- Obs.: esc_eop, esc_eep: future implementation - type t_spw_err_sel is (disconnection, parity, esc_eop, esc_eep, esc_esc, credit, ch_seq, reserved); + -- Enumerated type for spwerr error selection values + -- Obs.: esc_eop, esc_eep: future implementation + type t_spw_err_sel is (disconnection, parity, esc_eop, esc_eep, esc_esc, credit, ch_seq, reserved); - -- Enumerated type for spwerr error status values - type t_spw_err_stat is (stby, accepted, invalid, inconsistent, ended_ok, reserved); + -- Enumerated type for spwerr error status values + type t_spw_err_stat is (stby, accepted, invalid, inconsistent, ended_ok, reserved); - -- Input signals from toplevel to spwerr. - type spwerr_from_usr_type is record + -- Input signals from toplevel to spwerr. + type spwerr_from_usr_type is record - err_inj_i : std_logic; - err_sel_i : t_spw_err_sel; - end record; + err_inj_i : std_logic; + err_sel_i : t_spw_err_sel; + end record; - -- Output signals from spwerr to toplevel - type spwerr_to_usr_type is record + -- Output signals from spwerr to toplevel + type spwerr_to_usr_type is record - err_stat_o : t_spw_err_stat; - end record; + err_stat_o : t_spw_err_stat; + end record; - -- Input signals from spwlink to spwerr. - type spwerr_from_link_type is record + -- Input signals from spwlink to spwerr. + type spwerr_from_link_type is record - run_state : std_logic; - start_or_conn_state: std_logic; - end record; + run_state : std_logic; + start_or_conn_state : std_logic; + end record; - -- Output signals from spwerr to spwlink - type spwerr_to_link_type is record + -- Output signals from spwerr to spwlink + type spwerr_to_link_type is record - err_disc_o : std_logic; - err_par_o : std_logic; - err_esc_o : std_logic; - err_credit_o : std_logic; - err_ch_seq_o : std_logic; - end record; + err_disc_o : std_logic; + err_par_o : std_logic; + err_esc_o : std_logic; + err_credit_o : std_logic; + err_ch_seq_o : std_logic; + end record; - -- Input signals to spwlink. - type spw_link_in_type is record + -- Input signals to spwlink. + type spw_link_in_type is record - -- Enables automatic link start on receipt of a NULL character. - autostart : std_logic; + -- Enables automatic link start on receipt of a NULL character. + autostart : std_logic; - -- Enables link start once the Ready state is reached. - -- Without either "autostart" or "linkstart", the link remains in - -- state Ready. - linkstart : std_logic; + -- Enables link start once the Ready state is reached. + -- Without either "autostart" or "linkstart", the link remains in + -- state Ready. + linkstart : std_logic; - -- Do not start link (overrides "linkstart" and "autostart") and/or - -- disconnect the currently running link. - linkdis : std_logic; + -- Do not start link (overrides "linkstart" and "autostart") and/or + -- disconnect the currently running link. + linkdis : std_logic; - -- Number of bytes available in the receive buffer. Used to for - -- flow-control operation. At least 8 bytes must be available - -- initially, otherwise the link can not start. Values larger than 63 - -- are irrelevant and may be presented as 63. The available room may - -- decrease by one byte due to the reception of an N-Char; in that case - -- the "rxroom" signal must be updated on the clock following the clock - -- on which "rxchar" is high. Under no other circumstances may "rxroom" - -- be decreased. - rxroom : std_logic_vector(5 downto 0); + -- Number of bytes available in the receive buffer. Used to for + -- flow-control operation. At least 8 bytes must be available + -- initially, otherwise the link can not start. Values larger than 63 + -- are irrelevant and may be presented as 63. The available room may + -- decrease by one byte due to the reception of an N-Char; in that case + -- the "rxroom" signal must be updated on the clock following the clock + -- on which "rxchar" is high. Under no other circumstances may "rxroom" + -- be decreased. + rxroom : std_logic_vector(5 downto 0); - -- High for one clock cycle to request transmission of a TimeCode. - -- The request is registered inside spwxmit until it can be processed. - tick_in : std_logic; + -- High for one clock cycle to request transmission of a TimeCode. + -- The request is registered inside spwxmit until it can be processed. + tick_in : std_logic; - -- Control bits of the TimeCode to be sent. - -- Must be valid while tick_in is high. - ctrl_in : std_logic_vector(1 downto 0); + -- Control bits of the TimeCode to be sent. + -- Must be valid while tick_in is high. + ctrl_in : std_logic_vector(1 downto 0); - -- Counter value of the TimeCode to be sent. - -- Must be valid while tick_in is high. - time_in : std_logic_vector(5 downto 0); + -- Counter value of the TimeCode to be sent. + -- Must be valid while tick_in is high. + time_in : std_logic_vector(5 downto 0); - -- Requests transmission of an N-Char. - -- Keep this signal high until confirmed by "txack". - txwrite : std_logic; + -- Requests transmission of an N-Char. + -- Keep this signal high until confirmed by "txack". + txwrite : std_logic; - -- Control flag to be sent with the next N-Char. - -- Must be valid while "txwrite" is high. - txflag : std_logic; + -- Control flag to be sent with the next N-Char. + -- Must be valid while "txwrite" is high. + txflag : std_logic; - -- Byte to be sent, or "00000000" for EOP or "00000001" for EEP. - -- Must be valid while "txwrite" is high. - txdata : std_logic_vector(7 downto 0); + -- Byte to be sent, or "00000000" for EOP or "00000001" for EEP. + -- Must be valid while "txwrite" is high. + txdata : std_logic_vector(7 downto 0); - -- Spwerr interface in - toplevel - err_usr_i : spwerr_from_usr_type; - end record; + -- Spwerr interface in - toplevel + err_usr_i : spwerr_from_usr_type; + end record; - -- Output signals from spwlink. - type spw_link_out_type is record + -- Output signals from spwlink. + type spw_link_out_type is record - -- High if the link state machine is currently in state Started. - started : std_logic; + -- High if the link state machine is currently in state Started. + started : std_logic; - -- High if the link state machine is currently in state Connecting. - connecting : std_logic; + -- High if the link state machine is currently in state Connecting. + connecting : std_logic; - -- High if the link state machine is currently in state Run. - running : std_logic; + -- High if the link state machine is currently in state Run. + running : std_logic; - -- Disconnect detected in state Run. Triggers a reset and reconnect. - -- This indication is auto-clearing. - errdisc : std_logic; + -- Disconnect detected in state Run. Triggers a reset and reconnect. + -- This indication is auto-clearing. + errdisc : std_logic; - -- Parity error detected in state Run. Triggers a reset and reconnect. - -- This indication is auto-clearing. - errpar : std_logic; + -- Parity error detected in state Run. Triggers a reset and reconnect. + -- This indication is auto-clearing. + errpar : std_logic; - -- Invalid escape sequence detected in state Run. - -- Triggers a reset and reconnect; auto-clearing. - erresc : std_logic; + -- Invalid escape sequence detected in state Run. + -- Triggers a reset and reconnect; auto-clearing. + erresc : std_logic; - -- Credit error detected. Triggers a reset and reconnect. - -- This indication is auto-clearing. - errcred : std_logic; + -- Credit error detected. Triggers a reset and reconnect. + -- This indication is auto-clearing. + errcred : std_logic; - -- High to confirm the transmission of an N-Char. - -- This is a Wishbone-style handshake signal. It has a combinatorial - -- dependency on "txwrite". - txack : std_logic; + -- High to confirm the transmission of an N-Char. + -- This is a Wishbone-style handshake signal. It has a combinatorial + -- dependency on "txwrite". + txack : std_logic; - -- High for one clock cycle if a TimeCode was just received. - -- Verification of the TimeCode as described in 8.12.2 of ECSS-E-50 - -- is not implemented; all received timecodes are reported. - tick_out : std_logic; + -- High for one clock cycle if a TimeCode was just received. + -- Verification of the TimeCode as described in 8.12.2 of ECSS-E-50 + -- is not implemented; all received timecodes are reported. + tick_out : std_logic; - -- Control bits of last received TimeCode. - ctrl_out : std_logic_vector(1 downto 0); + -- Control bits of last received TimeCode. + ctrl_out : std_logic_vector(1 downto 0); - -- Counter value of last received TimeCode. - time_out : std_logic_vector(5 downto 0); + -- Counter value of last received TimeCode. + time_out : std_logic_vector(5 downto 0); - -- High for one clock cycle if an N-Char (data byte or EOP or EEP) was - -- just received. The data bits must be accepted immediately from - -- "rxflag" and "rxdata". - rxchar : std_logic; + -- High for one clock cycle if an N-Char (data byte or EOP or EEP) was + -- just received. The data bits must be accepted immediately from + -- "rxflag" and "rxdata". + rxchar : std_logic; - -- High if the received character is EOP or EEP, low if it is a data - -- byte. Valid when "rxchar" is high. - rxflag : std_logic; + -- High if the received character is EOP or EEP, low if it is a data + -- byte. Valid when "rxchar" is high. + rxflag : std_logic; - -- Received byte, or "00000000" for EOP or "00000001" for EEP. - -- Valid when "rxchar" is high. - rxdata : std_logic_vector(7 downto 0); + -- Received byte, or "00000000" for EOP or "00000001" for EEP. + -- Valid when "rxchar" is high. + rxdata : std_logic_vector(7 downto 0); - -- Spwerr interface out - toplevel - err_usr_o : spwerr_to_usr_type; - end record; + -- Spwerr interface out - toplevel + err_usr_o : spwerr_to_usr_type; + end record; - -- Output signals from spwrecv to spwlink. - type spw_recv_out_type is record + -- Output signals from spwrecv to spwlink. + type spw_recv_out_type is record - -- High if at least one signal change was seen since enable. - -- Resets to low when rxen is low. - gotbit : std_logic; + -- High if at least one signal change was seen since enable. + -- Resets to low when rxen is low. + gotbit : std_logic; - -- High if at least one valid NULL pattern was detected since enable. - -- Resets to low when rxen is low. - gotnull : std_logic; + -- High if at least one valid NULL pattern was detected since enable. + -- Resets to low when rxen is low. + gotnull : std_logic; - -- High for one clock cycle if an FCT token was just received. - gotfct : std_logic; + -- High for one clock cycle if an FCT token was just received. + gotfct : std_logic; - -- High for one clock cycle if a TimeCode was just received. - tick_out : std_logic; + -- High for one clock cycle if a TimeCode was just received. + tick_out : std_logic; - -- Control bits of last received TimeCode. - ctrl_out : std_logic_vector(1 downto 0); + -- Control bits of last received TimeCode. + ctrl_out : std_logic_vector(1 downto 0); - -- Counter value of last received TimeCode. - time_out : std_logic_vector(5 downto 0); + -- Counter value of last received TimeCode. + time_out : std_logic_vector(5 downto 0); - -- High for one clock cycle if an N-Char (data byte or EOP/EEP) was just received. - rxchar : std_logic; + -- High for one clock cycle if an N-Char (data byte or EOP/EEP) was just received. + rxchar : std_logic; - -- High if rxchar is high and the received character is EOP or EEP. - -- Low if rxchar is high and the received character is a data byte. - rxflag : std_logic; - - -- Received byte, or "00000000" for EOP or "00000001" for EEP. - -- Valid when "rxchar" is high. - rxdata : std_logic_vector(7 downto 0); - - -- Disconnect detected (after a signal change was seen). - -- Resets to low when rxen is low or when a signal change is seen. - errdisc : std_logic; - - -- Parity error detected (after a valid NULL pattern was seen). - -- Sticky; resets to low when rxen is low. - errpar : std_logic; - - -- Escape sequence error detected (after a valid NULL pattern was seen). - -- Sticky; resets to low when rxen is low. - erresc : std_logic; - end record; - - -- Input signals to spwxmit from spwlink. - type spw_xmit_in_type is record - - -- High to enable transmitter; low to disable and reset transmitter. - txen : std_logic; - - -- Indicates that only NULL characters may be transmitted. - stnull : std_logic; - - -- Indicates that only NULL and/or FCT characters may be transmitted. - stfct : std_logic; - - -- Requests transmission of an FCT character. - -- Keep this signal high until confirmed by "fctack". - fct_in : std_logic; - - -- High for one clock cycle to request transmission of a TimeCode. - -- The request is registered inside spwxmit until it can be processed. - tick_in : std_logic; - - -- Control bits of the TimeCode to be sent. - -- Must be valid while "tick_in" is high. - ctrl_in : std_logic_vector(1 downto 0); - - -- Counter value of the TimeCode to be sent. - -- Must be valid while "tick_in" is high. - time_in : std_logic_vector(5 downto 0); - - -- Request transmission of an N-Char. - -- Keep this signal high until confirmed by "txack". - txwrite : std_logic; - - -- Control flag to be sent with the next N-Char. - -- Must be valid while "txwrite" is high. - txflag : std_logic; - - -- Byte to send, or "00000000" for EOP or "00000001" for EEP. - -- Must be valid while "txwrite" is high. - txdata : std_logic_vector(7 downto 0); - - -- Parity error injection control bit (from spwerr: internal to link) - err_inj_par: std_logic; - - -- Escape error injection control bit (from spwerr: internal to link) - err_inj_esc: std_logic; - - -- Char sequence error injection control bit (from spwerr: internal to link) - err_inj_ch_seq: std_logic; - - -- Credit error injection control bit (from spwerr: internal to link) - err_inj_credit: std_logic; - - end record; - - -- Output signals from spwxmit to spwlink. - type spw_xmit_out_type is record - - -- High to confirm transmission on an FCT character. - -- This is a Wishbone-style handshaking signal; it is combinatorially - -- dependent on "fct_in". - fctack : std_logic; - - -- High to confirm transmission of an N-Char. - -- This is a Wishbone-style handshaking signal; it is combinatorially - -- dependent on both "fct_in" and "txwrite". - txack : std_logic; - end record; - - -- Character-stream interface - component spwstream is - generic( - sysfreq : real; -- clk freq in Hz - txclkfreq : real := 0.0; -- txclk freq in Hz - rximpl : spw_implementation_type := impl_generic; - rxchunk : integer range 1 to 4 := 1; -- max bits per clk - tximpl : spw_implementation_type := impl_generic; - rxfifosize_bits : integer range 6 to 14 := 11; -- rx fifo size - txfifosize_bits : integer range 2 to 14 := 11 -- tx fifo size - ); - port( - clk : in std_logic; -- system clock - rxclk : in std_logic; -- receiver sample clock - txclk : in std_logic; -- transmit clock - rst : in std_logic; -- synchronous reset - autostart : in std_logic; -- automatic link start - linkstart : in std_logic; -- forced link start - linkdis : in std_logic; -- stop link - txdivcnt : in std_logic_vector(7 downto 0); -- tx scale factor - tick_in : in std_logic; -- request timecode xmit - ctrl_in : in std_logic_vector(1 downto 0); - time_in : in std_logic_vector(5 downto 0); - txwrite : in std_logic; -- request character xmit - txflag : in std_logic; -- control flag of tx char - txdata : in std_logic_vector(7 downto 0); - txrdy : out std_logic; -- room in tx fifo - txhalff : out std_logic; -- tx fifo half full - tick_out : out std_logic; -- timecode received - ctrl_out : out std_logic_vector(1 downto 0); - time_out : out std_logic_vector(5 downto 0); - rxvalid : out std_logic; -- rx fifo not empty - rxhalff : out std_logic; -- rx fifo half full - rxflag : out std_logic; -- control flag of rx char - rxdata : out std_logic_vector(7 downto 0); - rxread : in std_logic; -- accept rx character - started : out std_logic; -- link in Started state - connecting : out std_logic; -- link in Connecting state - running : out std_logic; -- link in Run state - errdisc : out std_logic; -- disconnect error - errpar : out std_logic; -- parity error - erresc : out std_logic; -- escape error - errcred : out std_logic; -- credit error - spw_di : in std_logic; - spw_si : in std_logic; - spw_do : out std_logic; - spw_so : out std_logic; - -- spwerr user interface - err_inj_i : in std_logic; - err_sel_i : in t_spw_err_sel; - err_stat_o : out t_spw_err_stat - ); - end component spwstream; - - -- Link Level Interface - component spwlink is - generic( - reset_time : integer -- reset time in clocks (6.4 us) - ); - port( - clk : in std_logic; -- system clock - rst : in std_logic; -- synchronous reset (active-high) - linki : in spw_link_in_type; - linko : out spw_link_out_type; - rxen : out std_logic; - recvo : in spw_recv_out_type; - xmiti : out spw_xmit_in_type; - xmito : in spw_xmit_out_type - ); - end component spwlink; - - -- Receiver - component spwrecv is - generic( - disconnect_time : integer range 1 to 255; -- disconnect period in system clock cycles - rxchunk : integer range 1 to 4 -- nr of bits per system clock - ); - port( - clk : in std_logic; -- system clock - rxen : in std_logic; -- receiver enabled - recvo : out spw_recv_out_type; - inact : in std_logic; - inbvalid : in std_logic; - inbits : in std_logic_vector(rxchunk - 1 downto 0) - ); - end component spwrecv; - - -- Transmitter (generic implementation) - component spwxmit is - port( - clk : in std_logic; -- system clock - rst : in std_logic; -- synchronous reset (active-high) - divcnt : in std_logic_vector(7 downto 0); - xmiti : in spw_xmit_in_type; - xmito : out spw_xmit_out_type; - spw_do : out std_logic; -- tx data to SPW bus - spw_so : out std_logic -- tx strobe to SPW bus - ); - end component spwxmit; - - -- Transmitter (separate tx clock domain) - component spwxmit_fast is - port( - clk : in std_logic; -- system clock - txclk : in std_logic; -- transmit clock - rst : in std_logic; -- synchronous reset (active-high) - divcnt : in std_logic_vector(7 downto 0); - xmiti : in spw_xmit_in_type; - xmito : out spw_xmit_out_type; - spw_do : out std_logic; -- tx data to SPW bus - spw_so : out std_logic -- tx strobe to SPW bus - ); - end component spwxmit_fast; - - -- Front-end for SpaceWire Receiver (generic implementation) - component spwrecvfront_generic is - port( - clk : in std_logic; -- system clock - rxen : in std_logic; -- high to enable receiver - inact : out std_logic; -- high if activity on input - inbvalid : out std_logic; -- high if inbits contains a valid received bit - inbits : out std_logic_vector(0 downto 0); -- received bit - spw_di : in std_logic; -- Data In signal from SpaceWire bus - spw_si : in std_logic -- Strobe In signal from SpaceWire bus - ); - end component spwrecvfront_generic; - - -- Front-end for SpaceWire Receiver (separate rx clock domain) - component spwrecvfront_fast is - generic( - rxchunk : integer range 1 to 4 -- max number of bits per system clock - ); - port( - clk : in std_logic; -- system clock - rxclk : in std_logic; -- sample clock (DDR) - rxen : in std_logic; -- high to enable receiver - inact : out std_logic; -- high if activity on input - inbvalid : out std_logic; -- high if inbits contains a valid group of received bits - inbits : out std_logic_vector(rxchunk - 1 downto 0); -- received bits - spw_di : in std_logic; -- Data In signal from SpaceWire bus - spw_si : in std_logic -- Strobe In signal from SpaceWire bus - ); - end component spwrecvfront_fast; - - -- Synchronous two-port memory. - component spwram is - generic( - abits : integer; - dbits : integer); - port( - rclk : in std_logic; - wclk : in std_logic; - ren : in std_logic; - raddr : in std_logic_vector(abits - 1 downto 0); - rdata : out std_logic_vector(dbits - 1 downto 0); - wen : in std_logic; - waddr : in std_logic_vector(abits - 1 downto 0); - wdata : in std_logic_vector(dbits - 1 downto 0)); - end component spwram; - - -- Double flip-flop synchronizer. - component syncdff is - port( - clk : in std_logic; -- clock (destination domain) - rst : in std_logic; -- asynchronous reset, active-high - di : in std_logic; -- input data - do : out std_logic); -- output data - end component syncdff; - - -- Spwerr Interface - component spwerr is - port( - clk : in std_logic; -- system clock - rst : in std_logic; -- asynchronous reset (active-high) - err_link_i : in spwerr_from_link_type; - err_link_o : out spwerr_to_link_type; - err_usr_i : in spwerr_from_usr_type; - err_usr_o : out spwerr_to_usr_type - ); - end component spwerr; + -- High if rxchar is high and the received character is EOP or EEP. + -- Low if rxchar is high and the received character is a data byte. + rxflag : std_logic; + + -- Received byte, or "00000000" for EOP or "00000001" for EEP. + -- Valid when "rxchar" is high. + rxdata : std_logic_vector(7 downto 0); + + -- Disconnect detected (after a signal change was seen). + -- Resets to low when rxen is low or when a signal change is seen. + errdisc : std_logic; + + -- Parity error detected (after a valid NULL pattern was seen). + -- Sticky; resets to low when rxen is low. + errpar : std_logic; + + -- Escape sequence error detected (after a valid NULL pattern was seen). + -- Sticky; resets to low when rxen is low. + erresc : std_logic; + end record; + + -- Input signals to spwxmit from spwlink. + type spw_xmit_in_type is record + + -- High to enable transmitter; low to disable and reset transmitter. + txen : std_logic; + + -- Indicates that only NULL characters may be transmitted. + stnull : std_logic; + + -- Indicates that only NULL and/or FCT characters may be transmitted. + stfct : std_logic; + + -- Requests transmission of an FCT character. + -- Keep this signal high until confirmed by "fctack". + fct_in : std_logic; + + -- High for one clock cycle to request transmission of a TimeCode. + -- The request is registered inside spwxmit until it can be processed. + tick_in : std_logic; + + -- Control bits of the TimeCode to be sent. + -- Must be valid while "tick_in" is high. + ctrl_in : std_logic_vector(1 downto 0); + + -- Counter value of the TimeCode to be sent. + -- Must be valid while "tick_in" is high. + time_in : std_logic_vector(5 downto 0); + + -- Request transmission of an N-Char. + -- Keep this signal high until confirmed by "txack". + txwrite : std_logic; + + -- Control flag to be sent with the next N-Char. + -- Must be valid while "txwrite" is high. + txflag : std_logic; + + -- Byte to send, or "00000000" for EOP or "00000001" for EEP. + -- Must be valid while "txwrite" is high. + txdata : std_logic_vector(7 downto 0); + + -- Parity error injection control bit (from spwerr: internal to link) + err_inj_par : std_logic; + + -- Escape error injection control bit (from spwerr: internal to link) + err_inj_esc : std_logic; + + -- Char sequence error injection control bit (from spwerr: internal to link) + err_inj_ch_seq : std_logic; + + -- Credit error injection control bit (from spwerr: internal to link) + err_inj_credit : std_logic; + + end record; + + -- Output signals from spwxmit to spwlink. + type spw_xmit_out_type is record + + -- High to confirm transmission on an FCT character. + -- This is a Wishbone-style handshaking signal; it is combinatorially + -- dependent on "fct_in". + fctack : std_logic; + + -- High to confirm transmission of an N-Char. + -- This is a Wishbone-style handshaking signal; it is combinatorially + -- dependent on both "fct_in" and "txwrite". + txack : std_logic; + end record; + + -- Character-stream interface + component spwstream is + generic( + sysfreq : real; -- clk freq in Hz + txclkfreq : real := 0.0; -- txclk freq in Hz + rximpl : spw_implementation_type := impl_generic; + rxchunk : integer range 1 to 4 := 1; -- max bits per clk + tximpl : spw_implementation_type := impl_generic; + rxfifosize_bits : integer range 6 to 14 := 11; -- rx fifo size + txfifosize_bits : integer range 2 to 14 := 11 -- tx fifo size + ); + port( + clk : in std_logic; -- system clock + rxclk : in std_logic; -- receiver sample clock + txclk : in std_logic; -- transmit clock + rst : in std_logic; -- synchronous reset + autostart : in std_logic; -- automatic link start + linkstart : in std_logic; -- forced link start + linkdis : in std_logic; -- stop link + txdivcnt : in std_logic_vector(7 downto 0); -- tx scale factor + tick_in : in std_logic; -- request timecode xmit + ctrl_in : in std_logic_vector(1 downto 0); + time_in : in std_logic_vector(5 downto 0); + txwrite : in std_logic; -- request character xmit + txflag : in std_logic; -- control flag of tx char + txdata : in std_logic_vector(7 downto 0); + txrdy : out std_logic; -- room in tx fifo + txhalff : out std_logic; -- tx fifo half full + tick_out : out std_logic; -- timecode received + ctrl_out : out std_logic_vector(1 downto 0); + time_out : out std_logic_vector(5 downto 0); + rxvalid : out std_logic; -- rx fifo not empty + rxhalff : out std_logic; -- rx fifo half full + rxflag : out std_logic; -- control flag of rx char + rxdata : out std_logic_vector(7 downto 0); + rxread : in std_logic; -- accept rx character + started : out std_logic; -- link in Started state + connecting : out std_logic; -- link in Connecting state + running : out std_logic; -- link in Run state + errdisc : out std_logic; -- disconnect error + errpar : out std_logic; -- parity error + erresc : out std_logic; -- escape error + errcred : out std_logic; -- credit error + spw_di : in std_logic; + spw_si : in std_logic; + spw_do : out std_logic; + spw_so : out std_logic; + -- spwerr user interface + err_inj_i : in std_logic; + err_sel_i : in t_spw_err_sel; + err_stat_o : out t_spw_err_stat + ); + end component spwstream; + + -- Link Level Interface + component spwlink is + generic( + reset_time : integer -- reset time in clocks (6.4 us) + ); + port( + clk : in std_logic; -- system clock + rst : in std_logic; -- synchronous reset (active-high) + linki : in spw_link_in_type; + linko : out spw_link_out_type; + rxen : out std_logic; + recvo : in spw_recv_out_type; + xmiti : out spw_xmit_in_type; + xmito : in spw_xmit_out_type + ); + end component spwlink; + + -- Receiver + component spwrecv is + generic( + disconnect_time : integer range 1 to 255; -- disconnect period in system clock cycles + rxchunk : integer range 1 to 4 -- nr of bits per system clock + ); + port( + clk : in std_logic; -- system clock + rxen : in std_logic; -- receiver enabled + recvo : out spw_recv_out_type; + inact : in std_logic; + inbvalid : in std_logic; + inbits : in std_logic_vector(rxchunk - 1 downto 0); + invalid_transition : in std_logic -- high if invalid transition detected + ); + end component spwrecv; + + -- Transmitter (generic implementation) + component spwxmit is + port( + clk : in std_logic; -- system clock + rst : in std_logic; -- synchronous reset (active-high) + divcnt : in std_logic_vector(7 downto 0); + xmiti : in spw_xmit_in_type; + xmito : out spw_xmit_out_type; + spw_do : out std_logic; -- tx data to SPW bus + spw_so : out std_logic -- tx strobe to SPW bus + ); + end component spwxmit; + + -- Transmitter (separate tx clock domain) + component spwxmit_fast is + port( + clk : in std_logic; -- system clock + txclk : in std_logic; -- transmit clock + rst : in std_logic; -- synchronous reset (active-high) + divcnt : in std_logic_vector(7 downto 0); + xmiti : in spw_xmit_in_type; + xmito : out spw_xmit_out_type; + spw_do : out std_logic; -- tx data to SPW bus + spw_so : out std_logic -- tx strobe to SPW bus + ); + end component spwxmit_fast; + + -- Front-end for SpaceWire Receiver (generic implementation) + component spwrecvfront_generic is + port( + clk : in std_logic; -- system clock + rxen : in std_logic; -- high to enable receiver + inact : out std_logic; -- high if activity on input + inbvalid : out std_logic; -- high if inbits contains a valid received bit + inbits : out std_logic_vector(0 downto 0); -- received bit + invalid_transition : out std_logic; -- high if invalid transition detected + spw_di : in std_logic; -- Data In signal from SpaceWire bus + spw_si : in std_logic -- Strobe In signal from SpaceWire bus + ); + end component spwrecvfront_generic; + + -- Front-end for SpaceWire Receiver (separate rx clock domain) + component spwrecvfront_fast is + generic( + rxchunk : integer range 1 to 4 -- max number of bits per system clock + ); + port( + clk : in std_logic; -- system clock + rxclk : in std_logic; -- sample clock (DDR) + rxen : in std_logic; -- high to enable receiver + inact : out std_logic; -- high if activity on input + inbvalid : out std_logic; -- high if inbits contains a valid group of received bits + inbits : out std_logic_vector(rxchunk - 1 downto 0); -- received bits + spw_di : in std_logic; -- Data In signal from SpaceWire bus + spw_si : in std_logic -- Strobe In signal from SpaceWire bus + ); + end component spwrecvfront_fast; + + -- Synchronous two-port memory. + component spwram is + generic( + abits : integer; + dbits : integer); + port( + rclk : in std_logic; + wclk : in std_logic; + ren : in std_logic; + raddr : in std_logic_vector(abits - 1 downto 0); + rdata : out std_logic_vector(dbits - 1 downto 0); + wen : in std_logic; + waddr : in std_logic_vector(abits - 1 downto 0); + wdata : in std_logic_vector(dbits - 1 downto 0)); + end component spwram; + + -- Double flip-flop synchronizer. + component syncdff is + port( + clk : in std_logic; -- clock (destination domain) + rst : in std_logic; -- asynchronous reset, active-high + di : in std_logic; -- input data + do : out std_logic); -- output data + end component syncdff; + + -- Spwerr Interface + component spwerr is + port( + clk : in std_logic; -- system clock + rst : in std_logic; -- asynchronous reset (active-high) + err_link_i : in spwerr_from_link_type; + err_link_o : out spwerr_to_link_type; + err_usr_i : in spwerr_from_usr_type; + err_usr_o : out spwerr_to_usr_type + ); + end component spwerr; end package; diff --git a/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwram.vhd b/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwram.vhd index cee9e8df7..06e1578d1 100644 --- a/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwram.vhd +++ b/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwram.vhd @@ -9,33 +9,32 @@ use ieee.numeric_std.all; entity spwram is - generic ( - abits: integer; - dbits: integer ); - - port ( - rclk: in std_logic; - wclk: in std_logic; - ren: in std_logic; - raddr: in std_logic_vector(abits-1 downto 0); - rdata: out std_logic_vector(dbits-1 downto 0); - wen: in std_logic; - waddr: in std_logic_vector(abits-1 downto 0); - wdata: in std_logic_vector(dbits-1 downto 0) ); + generic( + abits : integer; + dbits : integer); + + port( + rclk : in std_logic; + wclk : in std_logic; + ren : in std_logic; + raddr : in std_logic_vector(abits - 1 downto 0); + rdata : out std_logic_vector(dbits - 1 downto 0); + wen : in std_logic; + waddr : in std_logic_vector(abits - 1 downto 0); + wdata : in std_logic_vector(dbits - 1 downto 0)); end entity spwram; architecture spwram_arch of spwram is - type mem_type is array(0 to (2**abits - 1)) of - std_logic_vector(dbits-1 downto 0); + type mem_type is array (0 to (2**abits - 1)) of std_logic_vector(dbits - 1 downto 0); - signal s_mem: mem_type; + signal s_mem : mem_type; begin -- read process - process (rclk) is + process(rclk) is begin if rising_edge(rclk) then if ren = '1' then @@ -45,7 +44,7 @@ begin end process; -- write process - process (wclk) is + process(wclk) is begin if rising_edge(wclk) then if wen = '1' then diff --git a/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecv.vhd b/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecv.vhd index 98c7a2919..c5d58c457 100644 --- a/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecv.vhd +++ b/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecv.vhd @@ -15,33 +15,29 @@ use work.spwpkg.all; entity spwrecv is - generic ( + generic( -- Disconnect timeout, expressed in system clock cycles. -- Should be 850 ns (727 ns .. 1000 ns) according to the standard. - disconnect_time: integer range 1 to 255; - + disconnect_time : integer range 1 to 255; -- Nr of bits sampled per system clock. - rxchunk: integer range 1 to 4 + rxchunk : integer range 1 to 4 ); - port ( + port( -- System clock. - clk: in std_logic; - + clk : in std_logic; -- High to enable receiver; low to disable and reset receiver. - rxen: in std_logic; - + rxen : in std_logic; -- Output signals to spwlink. - recvo: out spw_recv_out_type; - + recvo : out spw_recv_out_type; -- High if there has been recent activity on the input lines. - inact: in std_logic; - + inact : in std_logic; -- High if inbits contains a valid group of received bits. - inbvalid: in std_logic; - + inbvalid : in std_logic; -- Received bits from receiver front-end. - inbits: in std_logic_vector(rxchunk-1 downto 0) + inbits : in std_logic_vector(rxchunk - 1 downto 0); + -- High if invalid transition detected + invalid_transition : in std_logic ); end entity spwrecv; @@ -51,151 +47,151 @@ architecture spwrecv_arch of spwrecv is -- registers type regs_type is record -- receiver state - bit_seen: std_ulogic; -- got a bit transition - null_seen: std_ulogic; -- got a NULL token + bit_seen : std_ulogic; -- got a bit transition + null_seen : std_ulogic; -- got a NULL token -- input shift register - bitshift: std_logic_vector(8 downto 0); - bitcnt: std_logic_vector(9 downto 0); -- one-hot counter + bitshift : std_logic_vector(8 downto 0); + bitcnt : std_logic_vector(9 downto 0); -- one-hot counter -- parity flag - parity: std_ulogic; + parity : std_ulogic; -- decoding - control: std_ulogic; -- next code is control code - escaped: std_ulogic; -- last code was ESC + control : std_ulogic; -- next code is control code + escaped : std_ulogic; -- last code was ESC -- output registers - gotfct: std_ulogic; - tick_out: std_ulogic; - rxchar: std_ulogic; - rxflag: std_ulogic; - timereg: std_logic_vector(7 downto 0); - datareg: std_logic_vector(7 downto 0); + gotfct : std_ulogic; + tick_out : std_ulogic; + rxchar : std_ulogic; + rxflag : std_ulogic; + timereg : std_logic_vector(7 downto 0); + datareg : std_logic_vector(7 downto 0); -- disconnect timer - disccnt: unsigned(7 downto 0); + disccnt : unsigned(7 downto 0); -- error flags - errpar: std_ulogic; - erresc: std_ulogic; + errpar : std_ulogic; + erresc : std_ulogic; end record; -- Initial state - constant regs_reset: regs_type := ( - bit_seen => '0', - null_seen => '0', - bitshift => (others => '1'), - bitcnt => (others => '0'), - parity => '0', - control => '0', - escaped => '0', - gotfct => '0', - tick_out => '0', - rxchar => '0', - rxflag => '0', - timereg => (others => '0'), - datareg => (others => '0'), - disccnt => "00000000", - errpar => '0', - erresc => '0' ); + constant regs_reset : regs_type := ( + bit_seen => '0', + null_seen => '0', + bitshift => (others => '1'), + bitcnt => (others => '0'), + parity => '0', + control => '0', + escaped => '0', + gotfct => '0', + tick_out => '0', + rxchar => '0', + rxflag => '0', + timereg => (others => '0'), + datareg => (others => '0'), + disccnt => "00000000", + errpar => '0', + erresc => '0'); -- registers - signal r: regs_type := regs_reset; - signal rin: regs_type; + signal r : regs_type := regs_reset; + signal rin : regs_type; begin -- combinatorial process - process (r, rxen, inact, inbvalid, inbits) - variable v: regs_type; - variable v_inbit: std_ulogic; + process(r, rxen, inact, inbvalid, inbits, invalid_transition) + variable v : regs_type; + variable v_inbit : std_ulogic; begin - v := r; - v_inbit := '0'; + v := r; + v_inbit := '0'; -- disconnect timer if inact = '1' then -- activity on input; reset timer - v.disccnt := to_unsigned(disconnect_time, v.disccnt'length); + v.disccnt := to_unsigned(disconnect_time, v.disccnt'length); elsif r.disccnt /= 0 then -- count down - v.disccnt := r.disccnt - 1; + v.disccnt := r.disccnt - 1; end if; -- assume no new token - v.gotfct := '0'; - v.tick_out := '0'; - v.rxchar := '0'; + v.gotfct := '0'; + v.tick_out := '0'; + v.rxchar := '0'; if inbvalid = '1' then -- process incoming bits - for i in 0 to rxchunk-1 loop - v_inbit := inbits(i); + for i in 0 to rxchunk - 1 loop + v_inbit := inbits(i); -- got a bit transition - v.bit_seen := '1'; + v.bit_seen := '1'; if v.bitcnt(0) = '1' then -- received new token -- note that this will not happen before null_seen='1' if (v.parity xor v_inbit) = '0' then -- Parity check failed. - v.errpar := '1'; + v.errpar := '1'; else if v.control = '1' then -- received control code case v.bitshift(7 downto 6) is when "00" => -- FCT or NULL - v.gotfct := not r.escaped; - v.escaped := '0'; + v.gotfct := not r.escaped; + v.escaped := '0'; when "10" => -- EOP if r.escaped = '1' then - v.erresc := '1'; + v.erresc := '1'; end if; - v.escaped := '0'; - v.rxchar := not r.escaped; - v.rxflag := '1'; - v.datareg := "00000000"; + v.escaped := '0'; + v.rxchar := not r.escaped; + v.rxflag := '1'; + v.datareg := "00000000"; when "01" => -- EEP if r.escaped = '1' then - v.erresc := '1'; + v.erresc := '1'; end if; - v.escaped := '0'; - v.rxchar := not r.escaped; - v.rxflag := '1'; - v.datareg := "00000001"; + v.escaped := '0'; + v.rxchar := not r.escaped; + v.rxflag := '1'; + v.datareg := "00000001"; when others => -- ESC if r.escaped = '1' then - v.erresc := '1'; + v.erresc := '1'; end if; - v.escaped := '1'; + v.escaped := '1'; end case; else -- received 8-bit character if r.escaped = '1' then -- received Time-Code - v.tick_out := '1'; - v.timereg := v.bitshift(7 downto 0); + v.tick_out := '1'; + v.timereg := v.bitshift(7 downto 0); else -- received data character - v.rxflag := '0'; - v.rxchar := '1'; - v.datareg := v.bitshift(7 downto 0); + v.rxflag := '0'; + v.rxchar := '1'; + v.datareg := v.bitshift(7 downto 0); end if; - v.escaped := '0'; + v.escaped := '0'; end if; end if; -- prepare for next code - v.parity := '0'; - v.control := v_inbit; + v.parity := '0'; + v.control := v_inbit; if v_inbit = '1' then -- next word will be control code. - v.bitcnt := (3 => '1', others => '0'); + v.bitcnt := (3 => '1', others => '0'); else -- next word will be a data byte. - v.bitcnt := (9 => '1', others => '0'); + v.bitcnt := (9 => '1', others => '0'); end if; else -- wait until next code is completely received; -- accumulate parity - v.bitcnt := '0' & v.bitcnt(9 downto 1); - v.parity := v.parity xor v_inbit; + v.bitcnt := '0' & v.bitcnt(9 downto 1); + v.parity := v.parity xor v_inbit; end if; -- detect first NULL @@ -210,11 +206,15 @@ begin end if; -- shift new bit into register. - v.bitshift := v_inbit & v.bitshift(v.bitshift'high downto 1); + v.bitshift := v_inbit & v.bitshift(v.bitshift'high downto 1); end loop; end if; + if invalid_transition = '1' then + v.bitshift := (others => '1'); + end if; + -- synchronous reset if rxen = '0' then v.bit_seen := '0'; @@ -234,30 +234,30 @@ begin end if; -- drive outputs - recvo.gotbit <= r.bit_seen; - recvo.gotnull <= r.null_seen; - recvo.gotfct <= r.gotfct; - recvo.tick_out <= r.tick_out; - recvo.ctrl_out <= r.timereg(7 downto 6); - recvo.time_out <= r.timereg(5 downto 0); - recvo.rxchar <= r.rxchar; - recvo.rxflag <= r.rxflag; - recvo.rxdata <= r.datareg; + recvo.gotbit <= r.bit_seen; + recvo.gotnull <= r.null_seen; + recvo.gotfct <= r.gotfct; + recvo.tick_out <= r.tick_out; + recvo.ctrl_out <= r.timereg(7 downto 6); + recvo.time_out <= r.timereg(5 downto 0); + recvo.rxchar <= r.rxchar; + recvo.rxflag <= r.rxflag; + recvo.rxdata <= r.datareg; if r.bit_seen = '1' and r.disccnt = 0 then - recvo.errdisc <= '1'; + recvo.errdisc <= '1'; else - recvo.errdisc <= '0'; + recvo.errdisc <= '0'; end if; - recvo.errpar <= r.errpar; - recvo.erresc <= r.erresc; + recvo.errpar <= r.errpar; + recvo.erresc <= r.erresc; -- update registers - rin <= v; + rin <= v; end process; -- update registers on rising edge of system clock - process (clk) is + process(clk) is begin if rising_edge(clk) then r <= rin; diff --git a/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecvfront_fast.vhd b/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecvfront_fast.vhd index 4ce08446b..ae33ce4c8 100644 --- a/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecvfront_fast.vhd +++ b/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecvfront_fast.vhd @@ -69,41 +69,34 @@ use work.spwpkg.all; entity spwrecvfront_fast is - generic ( + generic( -- Number of bits to pass to the application per system clock. - rxchunk: integer range 1 to 4 ); + rxchunk : integer range 1 to 4); - port ( + port( -- System clock. - clk: in std_logic; - + clk : in std_logic; -- Sample clock. - rxclk: in std_logic; - + rxclk : in std_logic; -- High to enable receiver; low to disable and reset receiver. - rxen: in std_logic; - + rxen : in std_logic; -- High if there has been recent activity on the input lines. - inact: out std_logic; - + inact : out std_logic; -- High if inbits contains a valid group of received bits. -- If inbvalid='1', the application must sample inbits on -- the rising edge of clk. - inbvalid: out std_logic; - + inbvalid : out std_logic; -- Received bits (bit 0 is the earliest received bit). - inbits: out std_logic_vector(rxchunk-1 downto 0); - + inbits : out std_logic_vector(rxchunk - 1 downto 0); -- Data In signal from SpaceWire bus. - spw_di: in std_logic; - + spw_di : in std_logic; -- Strobe In signal from SpaceWire bus. - spw_si: in std_logic ); + spw_si : in std_logic); -- Turn off FSM extraction. -- Without this, XST will happily apply one-hot encoding to rrx.headptr. - attribute FSM_EXTRACT: string; - attribute FSM_EXTRACT of spwrecvfront_fast: entity is "NO"; + attribute FSM_EXTRACT : string; + attribute FSM_EXTRACT of spwrecvfront_fast : entity is "NO"; end entity spwrecvfront_fast; @@ -111,162 +104,162 @@ architecture spwrecvfront_arch of spwrecvfront_fast is -- width of bit groups in cyclic buffer; -- typically equal to rxchunk, except when rxchunk = 1 - type memwidth_array_type is array(1 to 4) of integer; - constant chunk_to_memwidth: memwidth_array_type := ( 2, 2, 3, 4 ); - constant memwidth: integer := chunk_to_memwidth(rxchunk); + type memwidth_array_type is array (1 to 4) of integer; + constant chunk_to_memwidth : memwidth_array_type := (2, 2, 3, 4); + constant memwidth : integer := chunk_to_memwidth(rxchunk); -- registers in rxclk domain type rxregs_type is record -- stage B: re-register input samples - b_di0: std_ulogic; - b_si0: std_ulogic; - b_di1: std_ulogic; - b_si1: std_ulogic; + b_di0 : std_ulogic; + b_si0 : std_ulogic; + b_di1 : std_ulogic; + b_si1 : std_ulogic; -- stage C: data/strobe decoding - c_bit: std_logic_vector(1 downto 0); - c_val: std_logic_vector(1 downto 0); - c_xor1: std_ulogic; + c_bit : std_logic_vector(1 downto 0); + c_val : std_logic_vector(1 downto 0); + c_xor1 : std_ulogic; -- stage D: collect groups of memwidth bits - d_shift: std_logic_vector(memwidth-1 downto 0); - d_count: std_logic_vector(memwidth-1 downto 0); + d_shift : std_logic_vector(memwidth - 1 downto 0); + d_count : std_logic_vector(memwidth - 1 downto 0); -- cyclic buffer access - bufdata: std_logic_vector(memwidth-1 downto 0); - bufwrite: std_ulogic; - headptr: std_logic_vector(2 downto 0); + bufdata : std_logic_vector(memwidth - 1 downto 0); + bufwrite : std_ulogic; + headptr : std_logic_vector(2 downto 0); -- activity detection - bitcnt: std_logic_vector(2 downto 0); + bitcnt : std_logic_vector(2 downto 0); end record; -- registers in system clock domain type regs_type is record -- data path from buffer to output - tailptr: std_logic_vector(2 downto 0); - inbvalid: std_ulogic; + tailptr : std_logic_vector(2 downto 0); + inbvalid : std_ulogic; -- split 2-bit groups if rxchunk=1 - splitbit: std_ulogic; - splitinx: std_ulogic; - splitvalid: std_ulogic; + splitbit : std_ulogic; + splitinx : std_ulogic; + splitvalid : std_ulogic; -- activity detection - bitcntp: std_logic_vector(2 downto 0); - inact: std_ulogic; + bitcntp : std_logic_vector(2 downto 0); + inact : std_ulogic; -- reset signal towards rxclk domain - rxdis: std_ulogic; + rxdis : std_ulogic; end record; - constant regs_reset: regs_type := ( - tailptr => "000", - inbvalid => '0', - splitbit => '0', - splitinx => '0', - splitvalid => '0', - bitcntp => "000", - inact => '0', - rxdis => '1' ); + constant regs_reset : regs_type := ( + tailptr => "000", + inbvalid => '0', + splitbit => '0', + splitinx => '0', + splitvalid => '0', + bitcntp => "000", + inact => '0', + rxdis => '1'); -- Signals that are re-synchronized from rxclk to system clock domain. type syncsys_type is record - headptr: std_logic_vector(2 downto 0); -- pointer in cyclic buffer - bitcnt: std_logic_vector(2 downto 0); -- activity detection + headptr : std_logic_vector(2 downto 0); -- pointer in cyclic buffer + bitcnt : std_logic_vector(2 downto 0); -- activity detection end record; -- Registers. - signal r: regs_type := regs_reset; - signal rin: regs_type; - signal rrx, rrxin: rxregs_type; + signal r : regs_type := regs_reset; + signal rin : regs_type; + signal rrx, rrxin : rxregs_type; -- Synchronized signals after crossing clock domains. - signal syncrx_rstn: std_logic; - signal syncsys: syncsys_type; + signal syncrx_rstn : std_logic; + signal syncsys : syncsys_type; -- Output data from cyclic buffer. - signal s_bufdout: std_logic_vector(memwidth-1 downto 0); + signal s_bufdout : std_logic_vector(memwidth - 1 downto 0); -- stage A: input flip-flops for rising/falling rxclk - signal s_a_di0: std_logic; - signal s_a_si0: std_logic; - signal s_a_di1: std_logic; - signal s_a_si1: std_logic; - signal s_a_di2: std_logic; - signal s_a_si2: std_logic; + signal s_a_di0 : std_logic; + signal s_a_si0 : std_logic; + signal s_a_di1 : std_logic; + signal s_a_si1 : std_logic; + signal s_a_di2 : std_logic; + signal s_a_si2 : std_logic; -- force use of IOB flip-flops - attribute IOB: string; - attribute IOB of s_a_di1: signal is "TRUE"; - attribute IOB of s_a_si1: signal is "TRUE"; - attribute IOB of s_a_di2: signal is "TRUE"; - attribute IOB of s_a_si2: signal is "TRUE"; + attribute IOB : string; + attribute IOB of s_a_di1 : signal is "TRUE"; + attribute IOB of s_a_si1 : signal is "TRUE"; + attribute IOB of s_a_di2 : signal is "TRUE"; + attribute IOB of s_a_si2 : signal is "TRUE"; begin -- Cyclic data buffer. - bufmem: spwram - generic map ( - abits => 3, - dbits => memwidth ) - port map ( - rclk => clk, - wclk => rxclk, - ren => '1', - raddr => r.tailptr, - rdata => s_bufdout, - wen => rrx.bufwrite, - waddr => rrx.headptr, - wdata => rrx.bufdata ); + bufmem : spwram + generic map( + abits => 3, + dbits => memwidth) + port map( + rclk => clk, + wclk => rxclk, + ren => '1', + raddr => r.tailptr, + rdata => s_bufdout, + wen => rrx.bufwrite, + waddr => rrx.headptr, + wdata => rrx.bufdata); -- Synchronize reset signal for rxclk domain. - syncrx_reset: syncdff - port map ( clk => rxclk, rst => r.rxdis, di => '1', do => syncrx_rstn ); + syncrx_reset : syncdff + port map(clk => rxclk, rst => r.rxdis, di => '1', do => syncrx_rstn); -- Synchronize signals from rxclk domain to system clock domain. - syncsys_headptr0: syncdff - port map ( clk => clk, rst => r.rxdis, di => rrx.headptr(0), do => syncsys.headptr(0) ); - syncsys_headptr1: syncdff - port map ( clk => clk, rst => r.rxdis, di => rrx.headptr(1), do => syncsys.headptr(1) ); - syncsys_headptr2: syncdff - port map ( clk => clk, rst => r.rxdis, di => rrx.headptr(2), do => syncsys.headptr(2) ); - syncsys_bitcnt0: syncdff - port map ( clk => clk, rst => r.rxdis, di => rrx.bitcnt(0), do => syncsys.bitcnt(0) ); - syncsys_bitcnt1: syncdff - port map ( clk => clk, rst => r.rxdis, di => rrx.bitcnt(1), do => syncsys.bitcnt(1) ); - syncsys_bitcnt2: syncdff - port map ( clk => clk, rst => r.rxdis, di => rrx.bitcnt(2), do => syncsys.bitcnt(2) ); + syncsys_headptr0 : syncdff + port map(clk => clk, rst => r.rxdis, di => rrx.headptr(0), do => syncsys.headptr(0)); + syncsys_headptr1 : syncdff + port map(clk => clk, rst => r.rxdis, di => rrx.headptr(1), do => syncsys.headptr(1)); + syncsys_headptr2 : syncdff + port map(clk => clk, rst => r.rxdis, di => rrx.headptr(2), do => syncsys.headptr(2)); + syncsys_bitcnt0 : syncdff + port map(clk => clk, rst => r.rxdis, di => rrx.bitcnt(0), do => syncsys.bitcnt(0)); + syncsys_bitcnt1 : syncdff + port map(clk => clk, rst => r.rxdis, di => rrx.bitcnt(1), do => syncsys.bitcnt(1)); + syncsys_bitcnt2 : syncdff + port map(clk => clk, rst => r.rxdis, di => rrx.bitcnt(2), do => syncsys.bitcnt(2)); -- sample inputs on rising edge of rxclk - process (rxclk) is + process(rxclk) is begin if rising_edge(rxclk) then - s_a_di1 <= spw_di; - s_a_si1 <= spw_si; + s_a_di1 <= spw_di; + s_a_si1 <= spw_si; end if; end process; -- sample inputs on falling edge of rxclk - process (rxclk) is + process(rxclk) is begin if falling_edge(rxclk) then - s_a_di2 <= spw_di; - s_a_si2 <= spw_si; + s_a_di2 <= spw_di; + s_a_si2 <= spw_si; -- reregister inputs in fabric flip-flops - s_a_di0 <= s_a_di2; - s_a_si0 <= s_a_si2; + s_a_di0 <= s_a_di2; + s_a_si0 <= s_a_si2; end if; end process; -- combinatorial process - process (r, rrx, rxen, syncrx_rstn, syncsys, s_bufdout, s_a_di0, s_a_si0, s_a_di1, s_a_si1) - variable v: regs_type; - variable vrx: rxregs_type; + process(r, rrx, rxen, syncrx_rstn, syncsys, s_bufdout, s_a_di0, s_a_si0, s_a_di1, s_a_si1) + variable v : regs_type; + variable vrx : rxregs_type; begin - v := r; - vrx := rrx; + v := r; + vrx := rrx; -- ---- SAMPLE CLOCK DOMAIN ---- -- stage B: re-register input samples - vrx.b_di0 := s_a_di0; - vrx.b_si0 := s_a_si0; - vrx.b_di1 := s_a_di1; - vrx.b_si1 := s_a_si1; + vrx.b_di0 := s_a_di0; + vrx.b_si0 := s_a_si0; + vrx.b_di1 := s_a_di1; + vrx.b_si1 := s_a_si1; -- stage C: decode data/strobe and detect valid bits if (rrx.b_di0 xor rrx.b_si0 xor rrx.c_xor1) = '1' then @@ -275,10 +268,8 @@ begin vrx.c_bit(0) := rrx.b_di1; end if; vrx.c_bit(1) := rrx.b_di1; - vrx.c_val(0) := (rrx.b_di0 xor rrx.b_si0 xor rrx.c_xor1) or - (rrx.b_di0 xor rrx.b_si0 xor rrx.b_di1 xor rrx.b_si1); - vrx.c_val(1) := (rrx.b_di0 xor rrx.b_si0 xor rrx.c_xor1) and - (rrx.b_di0 xor rrx.b_si0 xor rrx.b_di1 xor rrx.b_si1); + vrx.c_val(0) := (rrx.b_di0 xor rrx.b_si0 xor rrx.c_xor1) or (rrx.b_di0 xor rrx.b_si0 xor rrx.b_di1 xor rrx.b_si1); + vrx.c_val(1) := (rrx.b_di0 xor rrx.b_si0 xor rrx.c_xor1) and (rrx.b_di0 xor rrx.b_si0 xor rrx.b_di1 xor rrx.b_si1); vrx.c_xor1 := rrx.b_di1 xor rrx.b_si1; -- Note: @@ -291,24 +282,24 @@ begin -- shift incoming bits into register if rrx.c_val(1) = '1' then - vrx.d_shift := rrx.c_bit & rrx.d_shift(memwidth-1 downto 2); + vrx.d_shift := rrx.c_bit & rrx.d_shift(memwidth - 1 downto 2); else - vrx.d_shift := rrx.c_bit(0) & rrx.d_shift(memwidth-1 downto 1); + vrx.d_shift := rrx.c_bit(0) & rrx.d_shift(memwidth - 1 downto 1); end if; -- prepare to store a group of memwidth bits if rrx.d_count(0) = '1' then -- only one more bit needed - vrx.bufdata := rrx.c_bit(0) & rrx.d_shift(memwidth-1 downto 1); + vrx.bufdata := rrx.c_bit(0) & rrx.d_shift(memwidth - 1 downto 1); else - vrx.bufdata := rrx.c_bit & rrx.d_shift(memwidth-1 downto 2); + vrx.bufdata := rrx.c_bit & rrx.d_shift(memwidth - 1 downto 2); end if; -- countdown nr of needed bits (one-hot counter) if rrx.c_val(1) = '1' then - vrx.d_count := rrx.d_count(1 downto 0) & rrx.d_count(memwidth-1 downto 2); + vrx.d_count := rrx.d_count(1 downto 0) & rrx.d_count(memwidth - 1 downto 2); else - vrx.d_count := rrx.d_count(0 downto 0) & rrx.d_count(memwidth-1 downto 1); + vrx.d_count := rrx.d_count(0 downto 0) & rrx.d_count(memwidth - 1 downto 1); end if; end if; @@ -323,18 +314,18 @@ begin -- Activity detection. if rrx.c_val(0) = '1' then - vrx.bitcnt := std_logic_vector(unsigned(rrx.bitcnt) + 1); + vrx.bitcnt := std_logic_vector(unsigned(rrx.bitcnt) + 1); end if; -- Synchronous reset of rxclk domain. if syncrx_rstn = '0' then - vrx.c_val := "00"; - vrx.c_xor1 := '0'; - vrx.d_count := (others => '0'); - vrx.d_count(memwidth-1) := '1'; - vrx.bufwrite := '0'; - vrx.headptr := "000"; - vrx.bitcnt := "000"; + vrx.c_val := "00"; + vrx.c_xor1 := '0'; + vrx.d_count := (others => '0'); + vrx.d_count(memwidth - 1) := '1'; + vrx.bufwrite := '0'; + vrx.headptr := "000"; + vrx.bitcnt := "000"; end if; -- ---- SYSTEM CLOCK DOMAIN ---- @@ -344,13 +335,13 @@ begin -- not yet been written by the rxclk domain. if r.tailptr = syncsys.headptr then -- No more data in cyclic buffer. - v.inbvalid := '0'; + v.inbvalid := '0'; else -- Reading valid data from cyclic buffer. - v.inbvalid := '1'; + v.inbvalid := '1'; -- Increment tail pointer. if rxchunk /= 1 then - v.tailptr := std_logic_vector(unsigned(r.tailptr) + 1); + v.tailptr := std_logic_vector(unsigned(r.tailptr) + 1); end if; end if; @@ -358,55 +349,55 @@ begin if rxchunk = 1 then -- Select one of the two bits. if r.splitinx = '0' then - v.splitbit := s_bufdout(0); + v.splitbit := s_bufdout(0); else - v.splitbit := s_bufdout(1); + v.splitbit := s_bufdout(1); end if; -- Indicate valid bit. v.splitvalid := r.inbvalid; -- Increment tail pointer. if r.inbvalid = '1' then - v.splitinx := not r.splitinx; + v.splitinx := not r.splitinx; if r.splitinx = '0' then - v.tailptr := std_logic_vector(unsigned(r.tailptr) + 1); + v.tailptr := std_logic_vector(unsigned(r.tailptr) + 1); end if; end if; end if; -- Activity detection. - v.bitcntp := syncsys.bitcnt; + v.bitcntp := syncsys.bitcnt; if r.bitcntp = syncsys.bitcnt then - v.inact := '0'; + v.inact := '0'; else - v.inact := '1'; + v.inact := '1'; end if; -- Synchronous reset of system clock domain. if rxen = '0' then - v := regs_reset; + v := regs_reset; end if; -- Register rxen to ensure glitch-free signal to rxclk domain - v.rxdis := not rxen; + v.rxdis := not rxen; -- drive outputs - inact <= r.inact; + inact <= r.inact; if rxchunk = 1 then - inbvalid <= r.splitvalid; - inbits(0) <= r.splitbit; + inbvalid <= r.splitvalid; + inbits(0) <= r.splitbit; else - inbvalid <= r.inbvalid; - inbits <= s_bufdout; + inbvalid <= r.inbvalid; + inbits <= s_bufdout; end if; -- update registers - rrxin <= vrx; - rin <= v; + rrxin <= vrx; + rin <= v; end process; -- update registers on rising edge of rxclk - process (rxclk) is + process(rxclk) is begin if rising_edge(rxclk) then rrx <= rrxin; @@ -414,7 +405,7 @@ begin end process; -- update registers on rising edge of system clock - process (clk) is + process(clk) is begin if rising_edge(clk) then r <= rin; diff --git a/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecvfront_generic.vhd b/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecvfront_generic.vhd index 2104f2346..b318c4cb9 100644 --- a/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecvfront_generic.vhd +++ b/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwrecvfront_generic.vhd @@ -15,79 +15,81 @@ use ieee.numeric_std.all; entity spwrecvfront_generic is - port ( + port( -- System clock. - clk: in std_logic; - + clk : in std_logic; -- High to enable receiver; low to disable and reset receiver. - rxen: in std_logic; - + rxen : in std_logic; -- High if there has been recent activity on the input lines. - inact: out std_logic; - + inact : out std_logic; -- High if inbits contains a valid received bit. -- If inbvalid='1', the application must sample inbits on -- the rising edge of clk. - inbvalid: out std_logic; - + inbvalid : out std_logic; -- Received bit - inbits: out std_logic_vector(0 downto 0); - + inbits : out std_logic_vector(0 downto 0); + -- High if invalid transition detected + invalid_transition : out std_logic; -- Data In signal from SpaceWire bus. - spw_di: in std_logic; - + spw_di : in std_logic; -- Strobe In signal from SpaceWire bus. - spw_si: in std_logic ); + spw_si : in std_logic); end entity spwrecvfront_generic; architecture spwrecvfront_arch of spwrecvfront_generic is -- input flip-flops - signal s_spwdi1: std_ulogic; - signal s_spwsi1: std_ulogic; - signal s_spwdi2: std_ulogic; - signal s_spwsi2: std_ulogic; + signal s_spwdi1 : std_ulogic; + signal s_spwsi1 : std_ulogic; + signal s_spwdi2 : std_ulogic; + signal s_spwsi2 : std_ulogic; -- data/strobe decoding - signal s_spwsi3: std_ulogic; + signal s_spwsi3 : std_ulogic; -- output registers - signal s_inbvalid: std_ulogic; - signal s_inbit: std_ulogic; + signal s_inbvalid : std_ulogic; + signal s_inbit : std_ulogic; + + -- invalid transition detection + signal s_invalid_transition : std_ulogic; begin -- drive outputs - inact <= s_inbvalid; - inbvalid <= s_inbvalid; - inbits(0) <= s_inbit; + inact <= s_inbvalid; + inbvalid <= s_inbvalid; + inbits(0) <= s_inbit; + invalid_transition <= s_invalid_transition; -- synchronous process - process (clk) is + process(clk) is begin if rising_edge(clk) then -- sample input signal - s_spwdi1 <= spw_di; - s_spwsi1 <= spw_si; + s_spwdi1 <= spw_di; + s_spwsi1 <= spw_si; -- more flip-flops for safe synchronization - s_spwdi2 <= s_spwdi1; - s_spwsi2 <= s_spwsi1; + s_spwdi2 <= s_spwdi1; + s_spwsi2 <= s_spwsi1; -- keep strobe signal for data/strobe decoding - s_spwsi3 <= s_spwsi2; + s_spwsi3 <= s_spwsi2; -- keep data bit for data/strobe decoding - s_inbit <= s_spwdi2; + s_inbit <= s_spwdi2; if rxen = '1' then -- data/strobe decoding - s_inbvalid <= s_spwdi2 xor s_spwsi2 xor s_inbit xor s_spwsi3; + s_inbvalid <= s_spwdi2 xor s_spwsi2 xor s_inbit xor s_spwsi3; + s_invalid_transition <= (s_spwdi2 xor s_inbit) and (s_spwsi2 xor s_spwsi3); else -- reset receiver - s_inbvalid <= '0'; + s_inbvalid <= '0'; + s_invalid_transition <= '0'; end if; end if; diff --git a/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwstream.vhd b/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwstream.vhd index fd8ccade2..28fd18393 100644 --- a/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwstream.vhd +++ b/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwstream.vhd @@ -22,175 +22,132 @@ use work.spwpkg.all; entity spwstream is - generic ( + generic( -- System clock frequency in Hz. -- This must be set to the frequency of "clk". It is used to setup -- counters for reset timing, disconnect timeout and to transmit -- at 10 Mbit/s during the link handshake. - sysfreq: real; - + sysfreq : real; -- Transmit clock frequency in Hz (only if tximpl = impl_fast). -- This must be set to the frequency of "txclk". It is used to -- transmit at 10 Mbit/s during the link handshake. - txclkfreq: real := 0.0; - + txclkfreq : real := 0.0; -- Selection of a receiver front-end implementation. - rximpl: spw_implementation_type := impl_generic; - + rximpl : spw_implementation_type := impl_generic; -- Maximum number of bits received per system clock -- (must be 1 in case of impl_generic). - rxchunk: integer range 1 to 4 := 1; - + rxchunk : integer range 1 to 4 := 1; -- Selection of a transmitter implementation. - tximpl: spw_implementation_type := impl_generic; - + tximpl : spw_implementation_type := impl_generic; -- Size of the receive FIFO as the 2-logarithm of the number of bytes. -- Must be at least 6 (64 bytes). - rxfifosize_bits: integer range 6 to 14 := 11; - + rxfifosize_bits : integer range 6 to 14 := 11; -- Size of the transmit FIFO as the 2-logarithm of the number of bytes. - txfifosize_bits: integer range 2 to 14 := 11 + txfifosize_bits : integer range 2 to 14 := 11 ); - port ( + port( -- System clock. - clk: in std_logic; - + clk : in std_logic; -- Receiver sample clock (only for impl_fast) - rxclk: in std_logic; - + rxclk : in std_logic; -- Transmit clock (only for impl_fast) - txclk: in std_logic; - + txclk : in std_logic; -- Synchronous reset (active-high). - rst: in std_logic; - + rst : in std_logic; -- Enables automatic link start on receipt of a NULL character. - autostart: in std_logic; - + autostart : in std_logic; -- Enables link start once the Ready state is reached. -- Without autostart or linkstart, the link remains in state Ready. - linkstart: in std_logic; - + linkstart : in std_logic; -- Do not start link (overrides linkstart and autostart) and/or -- disconnect a running link. - linkdis: in std_logic; - + linkdis : in std_logic; -- Scaling factor minus 1, used to scale the transmit base clock into -- the transmission bit rate. The system clock (for impl_generic) or -- the txclk (for impl_fast) is divided by (unsigned(txdivcnt) + 1). -- Changing this signal will immediately change the transmission rate. -- During link setup, the transmission rate is always 10 Mbit/s. - txdivcnt: in std_logic_vector(7 downto 0); - + txdivcnt : in std_logic_vector(7 downto 0); -- High for one clock cycle to request transmission of a TimeCode. -- The request is registered inside the entity until it can be processed. - tick_in: in std_logic; - + tick_in : in std_logic; -- Control bits of the TimeCode to be sent. Must be valid while tick_in is high. - ctrl_in: in std_logic_vector(1 downto 0); - + ctrl_in : in std_logic_vector(1 downto 0); -- Counter value of the TimeCode to be sent. Must be valid while tick_in is high. - time_in: in std_logic_vector(5 downto 0); - + time_in : in std_logic_vector(5 downto 0); -- Pulled high by the application to write an N-Char to the transmit -- queue. If "txwrite" and "txrdy" are both high on the rising edge -- of "clk", a character is added to the transmit queue. -- This signal has no effect if "txrdy" is low. - txwrite: in std_logic; - + txwrite : in std_logic; -- Control flag to be sent with the next N_Char. -- Must be valid while txwrite is high. - txflag: in std_logic; - + txflag : in std_logic; -- Byte to be sent, or "00000000" for EOP or "00000001" for EEP. -- Must be valid while txwrite is high. - txdata: in std_logic_vector(7 downto 0); - + txdata : in std_logic_vector(7 downto 0); -- High if the entity is ready to accept an N-Char for transmission. - txrdy: out std_logic; - + txrdy : out std_logic; -- High if the transmission queue is at least half full. - txhalff: out std_logic; - + txhalff : out std_logic; -- High for one clock cycle if a TimeCode was just received. - tick_out: out std_logic; - + tick_out : out std_logic; -- Control bits of the last received TimeCode. - ctrl_out: out std_logic_vector(1 downto 0); - + ctrl_out : out std_logic_vector(1 downto 0); -- Counter value of the last received TimeCode. - time_out: out std_logic_vector(5 downto 0); - + time_out : out std_logic_vector(5 downto 0); -- High if "rxflag" and "rxdata" contain valid data. -- This signal is high unless the receive FIFO is empty. - rxvalid: out std_logic; - + rxvalid : out std_logic; -- High if the receive FIFO is at least half full. - rxhalff: out std_logic; - + rxhalff : out std_logic; -- High if the received character is EOP or EEP; low if the received -- character is a data byte. Valid if "rxvalid" is high. - rxflag: out std_logic; - + rxflag : out std_logic; -- Received byte, or "00000000" for EOP or "00000001" for EEP. -- Valid if "rxvalid" is high. - rxdata: out std_logic_vector(7 downto 0); - + rxdata : out std_logic_vector(7 downto 0); -- Pulled high by the application to accept a received character. -- If "rxvalid" and "rxread" are both high on the rising edge of "clk", -- a character is removed from the receive FIFO and "rxvalid", "rxflag" -- and "rxdata" are updated. -- This signal has no effect if "rxvalid" is low. - rxread: in std_logic; - + rxread : in std_logic; -- High if the link state machine is currently in the Started state. - started: out std_logic; - + started : out std_logic; -- High if the link state machine is currently in the Connecting state. - connecting: out std_logic; - + connecting : out std_logic; -- High if the link state machine is currently in the Run state, indicating -- that the link is fully operational. If none of started, connecting or running -- is high, the link is in an initial state and the transmitter is not yet enabled. - running: out std_logic; - + running : out std_logic; -- Disconnect detected in state Run. Triggers a reset and reconnect of the link. -- This indication is auto-clearing. - errdisc: out std_logic; - + errdisc : out std_logic; -- Parity error detected in state Run. Triggers a reset and reconnect of the link. -- This indication is auto-clearing. - errpar: out std_logic; - + errpar : out std_logic; -- Invalid escape sequence detected in state Run. Triggers a reset and reconnect of -- the link. This indication is auto-clearing. - erresc: out std_logic; - + erresc : out std_logic; -- Credit error detected. Triggers a reset and reconnect of the link. -- This indication is auto-clearing. - errcred: out std_logic; - + errcred : out std_logic; -- Data In signal from SpaceWire bus. - spw_di: in std_logic; - + spw_di : in std_logic; -- Strobe In signal from SpaceWire bus. - spw_si: in std_logic; - + spw_si : in std_logic; -- Data Out signal to SpaceWire bus. - spw_do: out std_logic; - + spw_do : out std_logic; -- Strobe Out signal to SpaceWire bus. - spw_so: out std_logic; - + spw_so : out std_logic; -- Error injection main input request (active high) - err_inj_i: in std_logic; - + err_inj_i : in std_logic; -- Error injection - error type selection - err_sel_i: in t_spw_err_sel; - + err_sel_i : in t_spw_err_sel; -- Error injection - status - err_stat_o: out t_spw_err_stat + err_stat_o : out t_spw_err_stat ); end entity spwstream; @@ -198,206 +155,206 @@ end entity spwstream; architecture spwstream_arch of spwstream is -- Convert boolean to std_logic. - type bool_to_logic_type is array(boolean) of std_ulogic; - constant bool_to_logic: bool_to_logic_type := (false => '0', true => '1'); + type bool_to_logic_type is array (boolean) of std_ulogic; + constant bool_to_logic : bool_to_logic_type := (false => '0', true => '1'); -- Reset time (6.4 us) in system clocks - constant reset_time: integer := integer(sysfreq * 6.4e-6); + constant reset_time : integer := integer(sysfreq * 6.4e-6); -- Disconnect time (850 ns) in system clocks - constant disconnect_time: integer := integer(sysfreq * 850.0e-9); + constant disconnect_time : integer := integer(sysfreq * 850.0e-9); -- Initial tx clock scaler (10 Mbit). - type impl_to_real_type is array(spw_implementation_type) of real; - constant tximpl_to_txclk_freq: impl_to_real_type := - (impl_generic => sysfreq, impl_fast => txclkfreq); - constant effective_txclk_freq: real := tximpl_to_txclk_freq(tximpl); - constant default_divcnt: std_logic_vector(7 downto 0) := - std_logic_vector(to_unsigned(integer(effective_txclk_freq / 10.0e6 - 1.0), 8)); + type impl_to_real_type is array (spw_implementation_type) of real; + constant tximpl_to_txclk_freq : impl_to_real_type := (impl_generic => sysfreq, impl_fast => txclkfreq); + constant effective_txclk_freq : real := tximpl_to_txclk_freq(tximpl); + constant default_divcnt : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(integer(effective_txclk_freq / 10.0e6 - 1.0), 8)); -- Registers. type regs_type is record -- packet state - rxpacket: std_logic; -- '1' when receiving a packet - rxeep: std_logic; -- '1' when rx EEP character pending - txpacket: std_logic; -- '1' when transmitting a packet - txdiscard: std_logic; -- '1' when discarding a tx packet + rxpacket : std_logic; -- '1' when receiving a packet + rxeep : std_logic; -- '1' when rx EEP character pending + txpacket : std_logic; -- '1' when transmitting a packet + txdiscard : std_logic; -- '1' when discarding a tx packet -- FIFO pointers - rxfifo_raddr: std_logic_vector(rxfifosize_bits-1 downto 0); - rxfifo_waddr: std_logic_vector(rxfifosize_bits-1 downto 0); - txfifo_raddr: std_logic_vector(txfifosize_bits-1 downto 0); - txfifo_waddr: std_logic_vector(txfifosize_bits-1 downto 0); + rxfifo_raddr : std_logic_vector(rxfifosize_bits - 1 downto 0); + rxfifo_waddr : std_logic_vector(rxfifosize_bits - 1 downto 0); + txfifo_raddr : std_logic_vector(txfifosize_bits - 1 downto 0); + txfifo_waddr : std_logic_vector(txfifosize_bits - 1 downto 0); -- FIFO state - rxfifo_rvalid: std_logic; -- '1' if s_rxfifo_rdata is valid - txfifo_rvalid: std_logic; -- '1' if s_txfifo_rdata is valid - rxfull: std_logic; -- '1' if RX fifo is full - rxhalff: std_logic; -- '1' if RX fifo is at least half full - txfull: std_logic; -- '1' if TX fifo is full - txhalff: std_logic; -- '1' if TX fifo is at least half full - rxroom: std_logic_vector(5 downto 0); + rxfifo_rvalid : std_logic; -- '1' if s_rxfifo_rdata is valid + txfifo_rvalid : std_logic; -- '1' if s_txfifo_rdata is valid + rxfull : std_logic; -- '1' if RX fifo is full + rxhalff : std_logic; -- '1' if RX fifo is at least half full + txfull : std_logic; -- '1' if TX fifo is full + txhalff : std_logic; -- '1' if TX fifo is at least half full + rxroom : std_logic_vector(5 downto 0); end record; - constant regs_reset: regs_type := ( - rxpacket => '0', - rxeep => '0', - txpacket => '0', - txdiscard => '0', - rxfifo_raddr => (others => '0'), - rxfifo_waddr => (others => '0'), - txfifo_raddr => (others => '0'), - txfifo_waddr => (others => '0'), - rxfifo_rvalid => '0', - txfifo_rvalid => '0', - rxfull => '0', - rxhalff => '0', - txfull => '0', - txhalff => '0', - rxroom => (others => '0') ); - - signal r: regs_type := regs_reset; - signal rin: regs_type; + constant regs_reset : regs_type := ( + rxpacket => '0', + rxeep => '0', + txpacket => '0', + txdiscard => '0', + rxfifo_raddr => (others => '0'), + rxfifo_waddr => (others => '0'), + txfifo_raddr => (others => '0'), + txfifo_waddr => (others => '0'), + rxfifo_rvalid => '0', + txfifo_rvalid => '0', + rxfull => '0', + rxhalff => '0', + txfull => '0', + txhalff => '0', + rxroom => (others => '0')); + + signal r : regs_type := regs_reset; + signal rin : regs_type; -- Interface signals to components. - signal recv_rxen: std_logic; - signal recvo: spw_recv_out_type; - signal recv_inact: std_logic; - signal recv_inbvalid: std_logic; - signal recv_inbits: std_logic_vector(rxchunk-1 downto 0); - signal xmiti: spw_xmit_in_type; - signal xmito: spw_xmit_out_type; - signal xmit_divcnt: std_logic_vector(7 downto 0); - signal linki: spw_link_in_type; - signal linko: spw_link_out_type; + signal recv_rxen : std_logic; + signal recvo : spw_recv_out_type; + signal recv_inact : std_logic; + signal recv_inbvalid : std_logic; + signal recv_inbits : std_logic_vector(rxchunk - 1 downto 0); + signal recv_invalid_transition : std_logic; + signal xmiti : spw_xmit_in_type; + signal xmito : spw_xmit_out_type; + signal xmit_divcnt : std_logic_vector(7 downto 0); + signal linki : spw_link_in_type; + signal linko : spw_link_out_type; -- Memory interface signals. - signal s_rxfifo_raddr: std_logic_vector(rxfifosize_bits-1 downto 0); - signal s_rxfifo_rdata: std_logic_vector(8 downto 0); - signal s_rxfifo_wen: std_logic; - signal s_rxfifo_waddr: std_logic_vector(rxfifosize_bits-1 downto 0); - signal s_rxfifo_wdata: std_logic_vector(8 downto 0); - signal s_txfifo_raddr: std_logic_vector(txfifosize_bits-1 downto 0); - signal s_txfifo_rdata: std_logic_vector(8 downto 0); - signal s_txfifo_wen: std_logic; - signal s_txfifo_waddr: std_logic_vector(txfifosize_bits-1 downto 0); - signal s_txfifo_wdata: std_logic_vector(8 downto 0); + signal s_rxfifo_raddr : std_logic_vector(rxfifosize_bits - 1 downto 0); + signal s_rxfifo_rdata : std_logic_vector(8 downto 0); + signal s_rxfifo_wen : std_logic; + signal s_rxfifo_waddr : std_logic_vector(rxfifosize_bits - 1 downto 0); + signal s_rxfifo_wdata : std_logic_vector(8 downto 0); + signal s_txfifo_raddr : std_logic_vector(txfifosize_bits - 1 downto 0); + signal s_txfifo_rdata : std_logic_vector(8 downto 0); + signal s_txfifo_wen : std_logic; + signal s_txfifo_waddr : std_logic_vector(txfifosize_bits - 1 downto 0); + signal s_txfifo_wdata : std_logic_vector(8 downto 0); begin -- Instantiate link controller. - link_inst: spwlink - generic map ( - reset_time => reset_time ) - port map ( - clk => clk, - rst => rst, - linki => linki, - linko => linko, - rxen => recv_rxen, - recvo => recvo, - xmiti => xmiti, - xmito => xmito ); + link_inst : spwlink + generic map( + reset_time => reset_time) + port map( + clk => clk, + rst => rst, + linki => linki, + linko => linko, + rxen => recv_rxen, + recvo => recvo, + xmiti => xmiti, + xmito => xmito); -- Instantiate receiver. - recv_inst: spwrecv + recv_inst : spwrecv generic map( disconnect_time => disconnect_time, - rxchunk => rxchunk ) - port map ( - clk => clk, - rxen => recv_rxen, - recvo => recvo, - inact => recv_inact, - inbvalid => recv_inbvalid, - inbits => recv_inbits ); + rxchunk => rxchunk) + port map( + clk => clk, + rxen => recv_rxen, + recvo => recvo, + inact => recv_inact, + inbvalid => recv_inbvalid, + inbits => recv_inbits, + invalid_transition => recv_invalid_transition); -- Instantiate transmitter. - xmit_sel0: if tximpl = impl_generic generate - xmit_inst: spwxmit - port map ( - clk => clk, - rst => rst, - divcnt => xmit_divcnt, - xmiti => xmiti, - xmito => xmito, - spw_do => spw_do, - spw_so => spw_so ); + xmit_sel0 : if tximpl = impl_generic generate + xmit_inst : spwxmit + port map( + clk => clk, + rst => rst, + divcnt => xmit_divcnt, + xmiti => xmiti, + xmito => xmito, + spw_do => spw_do, + spw_so => spw_so); end generate; - xmit_sel1: if tximpl = impl_fast generate - xmit_fast_inst: spwxmit_fast - port map ( - clk => clk, - txclk => txclk, - rst => rst, - divcnt => xmit_divcnt, - xmiti => xmiti, - xmito => xmito, - spw_do => spw_do, - spw_so => spw_so ); + xmit_sel1 : if tximpl = impl_fast generate + xmit_fast_inst : spwxmit_fast + port map( + clk => clk, + txclk => txclk, + rst => rst, + divcnt => xmit_divcnt, + xmiti => xmiti, + xmito => xmito, + spw_do => spw_do, + spw_so => spw_so); end generate; -- Instantiate receiver front-end. - recvfront_sel0: if rximpl = impl_generic generate - recvfront_generic_inst: spwrecvfront_generic - port map ( - clk => clk, - rxen => recv_rxen, - inact => recv_inact, - inbvalid => recv_inbvalid, - inbits => recv_inbits, - spw_di => spw_di, - spw_si => spw_si ); + recvfront_sel0 : if rximpl = impl_generic generate + recvfront_generic_inst : spwrecvfront_generic + port map( + clk => clk, + rxen => recv_rxen, + inact => recv_inact, + inbvalid => recv_inbvalid, + inbits => recv_inbits, + invalid_transition => recv_invalid_transition, + spw_di => spw_di, + spw_si => spw_si); end generate; - recvfront_sel1: if rximpl = impl_fast generate - recvfront_fast_inst: spwrecvfront_fast - generic map ( - rxchunk => rxchunk ) - port map ( - clk => clk, - rxclk => rxclk, - rxen => recv_rxen, - inact => recv_inact, - inbvalid => recv_inbvalid, - inbits => recv_inbits, - spw_di => spw_di, - spw_si => spw_si ); + recvfront_sel1 : if rximpl = impl_fast generate + recvfront_fast_inst : spwrecvfront_fast + generic map( + rxchunk => rxchunk) + port map( + clk => clk, + rxclk => rxclk, + rxen => recv_rxen, + inact => recv_inact, + inbvalid => recv_inbvalid, + inbits => recv_inbits, + spw_di => spw_di, + spw_si => spw_si); end generate; -- Instantiate RX memory. - rxmem: spwram - generic map ( - abits => rxfifosize_bits, - dbits => 9 ) - port map ( - rclk => clk, - wclk => clk, - ren => '1', - raddr => s_rxfifo_raddr, - rdata => s_rxfifo_rdata, - wen => s_rxfifo_wen, - waddr => s_rxfifo_waddr, - wdata => s_rxfifo_wdata ); + rxmem : spwram + generic map( + abits => rxfifosize_bits, + dbits => 9) + port map( + rclk => clk, + wclk => clk, + ren => '1', + raddr => s_rxfifo_raddr, + rdata => s_rxfifo_rdata, + wen => s_rxfifo_wen, + waddr => s_rxfifo_waddr, + wdata => s_rxfifo_wdata); -- Instantiate TX memory. - txmem: spwram - generic map ( - abits => txfifosize_bits, - dbits => 9 ) - port map ( - rclk => clk, - wclk => clk, - ren => '1', - raddr => s_txfifo_raddr, - rdata => s_txfifo_rdata, - wen => s_txfifo_wen, - waddr => s_txfifo_waddr, - wdata => s_txfifo_wdata ); + txmem : spwram + generic map( + abits => txfifosize_bits, + dbits => 9) + port map( + rclk => clk, + wclk => clk, + ren => '1', + raddr => s_txfifo_raddr, + rdata => s_txfifo_rdata, + wen => s_txfifo_wen, + waddr => s_txfifo_waddr, + wdata => s_txfifo_wdata); -- Combinatorial process - process (r, linko, s_rxfifo_rdata, s_txfifo_rdata, rst, autostart, linkstart, linkdis, - txdivcnt, tick_in, ctrl_in, time_in, txwrite, txflag, txdata, rxread, err_inj_i, err_sel_i) is - variable v: regs_type; - variable v_tmprxroom: unsigned(rxfifosize_bits-1 downto 0); - variable v_tmptxroom: unsigned(txfifosize_bits-1 downto 0); + process(r, linko, s_rxfifo_rdata, s_txfifo_rdata, rst, autostart, linkstart, linkdis, txdivcnt, tick_in, ctrl_in, time_in, txwrite, txflag, txdata, rxread, err_inj_i, err_sel_i) is + variable v : regs_type; + variable v_tmprxroom : unsigned(rxfifosize_bits - 1 downto 0); + variable v_tmptxroom : unsigned(txfifosize_bits - 1 downto 0); begin v := r; v_tmprxroom := to_unsigned(0, v_tmprxroom'length); @@ -406,24 +363,24 @@ begin -- Keep track of whether we are sending and/or receiving a packet. if linko.rxchar = '1' then -- got character - v.rxpacket := not linko.rxflag; + v.rxpacket := not linko.rxflag; end if; if linko.txack = '1' then -- send character - v.txpacket := not s_txfifo_rdata(8); + v.txpacket := not s_txfifo_rdata(8); end if; -- Update RX fifo pointers. if (rxread = '1') and (r.rxfifo_rvalid = '1') then -- read from fifo - v.rxfifo_raddr := std_logic_vector(unsigned(r.rxfifo_raddr) + 1); + v.rxfifo_raddr := std_logic_vector(unsigned(r.rxfifo_raddr) + 1); end if; if r.rxfull = '0' then if (linko.rxchar = '1') or (r.rxeep = '1') then -- write to fifo (received char or pending EEP) - v.rxfifo_waddr := std_logic_vector(unsigned(r.rxfifo_waddr) + 1); + v.rxfifo_waddr := std_logic_vector(unsigned(r.rxfifo_waddr) + 1); end if; - v.rxeep := '0'; + v.rxeep := '0'; end if; -- Keep track of whether the RX fifo contains valid data. @@ -435,22 +392,22 @@ begin v.rxfull := bool_to_logic(v_tmprxroom = 0); v.rxhalff := not v_tmprxroom(v_tmprxroom'high); if v_tmprxroom > 63 then - v.rxroom := (others => '1'); + v.rxroom := (others => '1'); else - v.rxroom := std_logic_vector(v_tmprxroom(5 downto 0)); + v.rxroom := std_logic_vector(v_tmprxroom(5 downto 0)); end if; -- Update TX fifo pointers. if (r.txfifo_rvalid = '1') and ((linko.txack = '1') or (r.txdiscard = '1')) then -- read from fifo - v.txfifo_raddr := std_logic_vector(unsigned(r.txfifo_raddr) + 1); + v.txfifo_raddr := std_logic_vector(unsigned(r.txfifo_raddr) + 1); if s_txfifo_rdata(8) = '1' then v.txdiscard := '0'; -- got EOP/EEP, stop discarding data end if; end if; if (r.txfull = '0') and (txwrite = '1') then -- write to fifo - v.txfifo_waddr := std_logic_vector(unsigned(r.txfifo_waddr) + 1); + v.txfifo_waddr := std_logic_vector(unsigned(r.txfifo_waddr) + 1); end if; -- Keep track of whether the TX fifo contains valid data. @@ -461,11 +418,11 @@ begin v_tmptxroom := unsigned(r.txfifo_raddr) - unsigned(v.txfifo_waddr) - 1; v.txfull := bool_to_logic(v_tmptxroom = 0); v.txhalff := not v_tmptxroom(v_tmptxroom'high); - + -- If the link is lost, set a flag to discard the current packet. if linko.running = '0' then - v.rxeep := v.rxeep or v.rxpacket; -- use new value of rxpacket - v.txdiscard := v.txdiscard or v.txpacket; -- use new value of txpacket + v.rxeep := v.rxeep or v.rxpacket; -- use new value of rxpacket + v.txdiscard := v.txdiscard or v.txpacket; -- use new value of txpacket v.rxpacket := '0'; v.txpacket := '0'; end if; @@ -476,32 +433,32 @@ begin end if; -- Drive control signals to RX fifo. - s_rxfifo_raddr <= v.rxfifo_raddr; -- using new value of rxfifo_raddr - s_rxfifo_wen <= (not r.rxfull) and (linko.rxchar or r.rxeep); - s_rxfifo_waddr <= r.rxfifo_waddr; + s_rxfifo_raddr <= v.rxfifo_raddr; -- using new value of rxfifo_raddr + s_rxfifo_wen <= (not r.rxfull) and (linko.rxchar or r.rxeep); + s_rxfifo_waddr <= r.rxfifo_waddr; if r.rxeep = '1' then - s_rxfifo_wdata <= "100000001"; + s_rxfifo_wdata <= "100000001"; else - s_rxfifo_wdata <= linko.rxflag & linko.rxdata; + s_rxfifo_wdata <= linko.rxflag & linko.rxdata; end if; -- Drive control signals to TX fifo. - s_txfifo_raddr <= v.txfifo_raddr; -- using new value of txfifo_raddr - s_txfifo_wen <= (not r.txfull) and txwrite; - s_txfifo_waddr <= r.txfifo_waddr; - s_txfifo_wdata <= txflag & txdata; + s_txfifo_raddr <= v.txfifo_raddr; -- using new value of txfifo_raddr + s_txfifo_wen <= (not r.txfull) and txwrite; + s_txfifo_waddr <= r.txfifo_waddr; + s_txfifo_wdata <= txflag & txdata; -- Drive inputs to spwlink. - linki.autostart <= autostart; - linki.linkstart <= linkstart; - linki.linkdis <= linkdis; - linki.rxroom <= r.rxroom; - linki.tick_in <= tick_in; - linki.ctrl_in <= ctrl_in; - linki.time_in <= time_in; - linki.txwrite <= r.txfifo_rvalid and not r.txdiscard; - linki.txflag <= s_txfifo_rdata(8); - linki.txdata <= s_txfifo_rdata(7 downto 0); + linki.autostart <= autostart; + linki.linkstart <= linkstart; + linki.linkdis <= linkdis; + linki.rxroom <= r.rxroom; + linki.tick_in <= tick_in; + linki.ctrl_in <= ctrl_in; + linki.time_in <= time_in; + linki.txwrite <= r.txfifo_rvalid and not r.txdiscard; + linki.txflag <= s_txfifo_rdata(8); + linki.txdata <= s_txfifo_rdata(7 downto 0); linki.err_usr_i.err_inj_i <= err_inj_i; linki.err_usr_i.err_sel_i <= err_sel_i; @@ -513,23 +470,23 @@ begin end if; -- Drive outputs. - txrdy <= not r.txfull; - txhalff <= r.txhalff; - tick_out <= linko.tick_out; - ctrl_out <= linko.ctrl_out; - time_out <= linko.time_out; - rxvalid <= r.rxfifo_rvalid; - rxhalff <= r.rxhalff; - rxflag <= s_rxfifo_rdata(8); - rxdata <= s_rxfifo_rdata(7 downto 0); - started <= linko.started; - connecting <= linko.connecting; - running <= linko.running; - errdisc <= linko.errdisc; - errpar <= linko.errpar; - erresc <= linko.erresc; - errcred <= linko.errcred; - err_stat_o <= linko.err_usr_o.err_stat_o; + txrdy <= not r.txfull; + txhalff <= r.txhalff; + tick_out <= linko.tick_out; + ctrl_out <= linko.ctrl_out; + time_out <= linko.time_out; + rxvalid <= r.rxfifo_rvalid; + rxhalff <= r.rxhalff; + rxflag <= s_rxfifo_rdata(8); + rxdata <= s_rxfifo_rdata(7 downto 0); + started <= linko.started; + connecting <= linko.connecting; + running <= linko.running; + errdisc <= linko.errdisc; + errpar <= linko.errpar; + erresc <= linko.erresc; + errcred <= linko.errcred; + err_stat_o <= linko.err_usr_o.err_stat_o; -- Reset. if rst = '1' then @@ -550,7 +507,7 @@ begin end process; -- Update registers. - process (clk) is + process(clk) is begin if rising_edge(clk) then r <= rin; diff --git a/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwxmit.vhd b/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwxmit.vhd index c8a78b2d3..be05a3841 100644 --- a/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwxmit.vhd +++ b/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwxmit.vhd @@ -12,30 +12,24 @@ use work.spwpkg.all; entity spwxmit is - port ( + port( -- System clock. - clk: in std_logic; - + clk : in std_logic; -- Synchronous reset (active-high). - rst: in std_logic; - + rst : in std_logic; -- Scaling factor minus 1, used to scale the system clock into the -- transmission bit rate. The system clock is divided by -- (unsigned(divcnt) + 1). Changing this signal will immediately -- change the transmission rate. - divcnt: in std_logic_vector(7 downto 0); - + divcnt : in std_logic_vector(7 downto 0); -- Input signals from spwlink. - xmiti: in spw_xmit_in_type; - + xmiti : in spw_xmit_in_type; -- Output signals to spwlink. - xmito: out spw_xmit_out_type; - + xmito : out spw_xmit_out_type; -- Data Out signal to SpaceWire bus. - spw_do: out std_logic; - + spw_do : out std_logic; -- Strobe Out signal to SpaceWire bus. - spw_so: out std_logic + spw_so : out std_logic ); end entity spwxmit; @@ -45,61 +39,61 @@ architecture spwxmit_arch of spwxmit is -- Registers type regs_type is record -- tx clock - txclken: std_ulogic; -- high if a bit must be transmitted - txclkcnt: unsigned(7 downto 0); + txclken : std_ulogic; -- high if a bit must be transmitted + txclkcnt : unsigned(7 downto 0); -- output shift register - bitshift: std_logic_vector(12 downto 0); - bitcnt: unsigned(3 downto 0); + bitshift : std_logic_vector(12 downto 0); + bitcnt : unsigned(3 downto 0); -- output signals - out_data: std_ulogic; - out_strobe: std_ulogic; + out_data : std_ulogic; + out_strobe : std_ulogic; -- parity flag - parity: std_ulogic; + parity : std_ulogic; -- pending time tick - pend_tick: std_ulogic; - pend_time: std_logic_vector(7 downto 0); + pend_tick : std_ulogic; + pend_time : std_logic_vector(7 downto 0); -- transmitter mode - allow_fct: std_ulogic; -- allowed to send FCTs - allow_char: std_ulogic; -- allowed to send data and time - sent_null: std_ulogic; -- sent at least one NULL token - sent_fct: std_ulogic; -- sent at least one FCT token + allow_fct : std_ulogic; -- allowed to send FCTs + allow_char : std_ulogic; -- allowed to send data and time + sent_null : std_ulogic; -- sent at least one NULL token + sent_fct : std_ulogic; -- sent at least one FCT token end record; -- Initial state - constant regs_reset: regs_type := ( - txclken => '0', - txclkcnt => "00000000", - bitshift => (others => '0'), - bitcnt => "0000", - out_data => '0', - out_strobe => '0', - parity => '0', - pend_tick => '0', - pend_time => (others => '0'), - allow_fct => '0', - allow_char => '0', - sent_null => '0', - sent_fct => '0' ); + constant regs_reset : regs_type := ( + txclken => '0', + txclkcnt => "00000000", + bitshift => (others => '0'), + bitcnt => "0000", + out_data => '0', + out_strobe => '0', + parity => '0', + pend_tick => '0', + pend_time => (others => '0'), + allow_fct => '0', + allow_char => '0', + sent_null => '0', + sent_fct => '0'); -- Registers - signal r: regs_type := regs_reset; - signal rin: regs_type; + signal r : regs_type := regs_reset; + signal rin : regs_type; begin -- Combinatorial process - process (r, rst, divcnt, xmiti) is - variable v: regs_type; + process(r, rst, divcnt, xmiti) is + variable v : regs_type; begin v := r; -- Generate TX clock. if r.txclkcnt = 0 then - v.txclkcnt := unsigned(divcnt); - v.txclken := '1'; + v.txclkcnt := unsigned(divcnt); + v.txclken := '1'; else - v.txclkcnt := r.txclkcnt - 1; - v.txclken := '0'; + v.txclkcnt := r.txclkcnt - 1; + v.txclken := '0'; end if; if xmiti.txen = '0' then @@ -122,14 +116,13 @@ begin else -- Transmitter enabled. - v.allow_fct := (not xmiti.stnull) and r.sent_null; - + v.allow_fct := (not xmiti.stnull) and r.sent_null; + -- If a char sequence error requested, force allow_char = '1' if (xmiti.err_inj_ch_seq = '1') then - v.allow_char := '1'; - else - v.allow_char := (not xmiti.stnull) and r.sent_null and - (not xmiti.stfct) and r.sent_fct; + v.allow_char := '1'; + else + v.allow_char := (not xmiti.stnull) and r.sent_null and (not xmiti.stfct) and r.sent_fct; end if; -- On tick of transmission clock, put next bit on the output. @@ -140,50 +133,50 @@ begin -- Need to start a new character. if (r.allow_char = '1') and (r.pend_tick = '1') then -- Send Time-Code. - v.out_data := r.parity; + v.out_data := r.parity; v.bitshift(12 downto 5) := r.pend_time; v.bitshift(4 downto 0) := "01111"; - v.bitcnt := to_unsigned(13, v.bitcnt'length); - v.parity := '0'; - v.pend_tick := '0'; + v.bitcnt := to_unsigned(13, v.bitcnt'length); + v.parity := '0'; + v.pend_tick := '0'; elsif (r.allow_fct = '1') and (xmiti.fct_in = '1') then -- Send FCT. - v.out_data := r.parity; - v.bitshift(2 downto 0) := "001"; - v.bitcnt := to_unsigned(3, v.bitcnt'length); - v.parity := '1'; - v.sent_fct := '1'; + v.out_data := r.parity; + v.bitshift(2 downto 0) := "001"; + v.bitcnt := to_unsigned(3, v.bitcnt'length); + v.parity := '1'; + v.sent_fct := '1'; elsif (r.allow_char = '1') and (xmiti.txwrite = '1') then -- Send N-Char. v.bitshift(0) := xmiti.txflag; - v.parity := xmiti.txflag; + v.parity := xmiti.txflag; if xmiti.txflag = '0' then -- Data byte - v.out_data := not r.parity; + v.out_data := not r.parity; v.bitshift(8 downto 1) := xmiti.txdata; - v.bitcnt := to_unsigned(9, v.bitcnt'length); + v.bitcnt := to_unsigned(9, v.bitcnt'length); else -- EOP or EEP - v.out_data := r.parity; + v.out_data := r.parity; v.bitshift(1) := xmiti.txdata(0); v.bitshift(2) := not xmiti.txdata(0); - v.bitcnt := to_unsigned(3, v.bitcnt'length); + v.bitcnt := to_unsigned(3, v.bitcnt'length); end if; else -- Send NULL. - v.out_data := r.parity; + v.out_data := r.parity; -- Parity error injection check if (xmiti.err_inj_par = '1') then - -- Force wrong parity bit in fct portion code - -- It can´t be confused with eop, eep, or another esc. - v.bitshift(6 downto 0) := "0011111"; - -- Escape error injection check + -- Force wrong parity bit in fct portion code + -- It can´t be confused with eop, eep, or another esc. + v.bitshift(6 downto 0) := "0011111"; + -- Escape error injection check elsif (xmiti.err_inj_esc = '1') then - -- Force another esc in fct portion code: esc + esc. - v.bitshift(6 downto 0) := "1110111"; + -- Force another esc in fct portion code: esc + esc. + v.bitshift(6 downto 0) := "1110111"; -- Normal null code else - v.bitshift(6 downto 0) := "0010111"; + v.bitshift(6 downto 0) := "0010111"; end if; v.bitcnt := to_unsigned(7, v.bitcnt'length); v.parity := '0'; @@ -193,10 +186,10 @@ begin else -- Shift next bit to the output. - v.out_data := r.bitshift(0); - v.parity := r.parity xor r.bitshift(0); - v.bitshift(r.bitshift'high-1 downto 0) := r.bitshift(r.bitshift'high downto 1); - v.bitcnt := r.bitcnt - 1; + v.out_data := r.bitshift(0); + v.parity := r.parity xor r.bitshift(0); + v.bitshift(r.bitshift'high - 1 downto 0) := r.bitshift(r.bitshift'high downto 1); + v.bitcnt := r.bitcnt - 1; end if; @@ -225,24 +218,20 @@ begin -- (ready for token) AND (FCTs allowed) AND -- ((characters not allowed) OR (no timecode pending)) AND -- (FCT requested) - if (xmiti.txen = '1') and - (r.txclken = '1') and (r.bitcnt = 0) and (r.allow_fct = '1') and - ((r.allow_char = '0') or (r.pend_tick = '0')) then - xmito.fctack <= xmiti.fct_in; + if (xmiti.txen = '1') and (r.txclken = '1') and (r.bitcnt = 0) and (r.allow_fct = '1') and ((r.allow_char = '0') or (r.pend_tick = '0')) then + xmito.fctack <= xmiti.fct_in; else - xmito.fctack <= '0'; + xmito.fctack <= '0'; end if; -- Set txack high if (transmitter enabled) AND -- (ready for token) AND (characters enabled) AND -- (no timecode pending) AND (no FCT requested) AND -- (character requested) - if (xmiti.txen = '1') and - (r.txclken = '1') and (r.bitcnt = 0) and (r.allow_char = '1') and - (r.pend_tick = '0') and (xmiti.fct_in = '0') then - xmito.txack <= xmiti.txwrite; + if (xmiti.txen = '1') and (r.txclken = '1') and (r.bitcnt = 0) and (r.allow_char = '1') and (r.pend_tick = '0') and (xmiti.fct_in = '0') then + xmito.txack <= xmiti.txwrite; else - xmito.txack <= '0'; + xmito.txack <= '0'; end if; -- Update registers @@ -250,7 +239,7 @@ begin end process; -- Synchronous process - process (clk) is + process(clk) is begin if rising_edge(clk) then @@ -258,8 +247,8 @@ begin r <= rin; -- Drive spacewire output signals - spw_do <= r.out_data; - spw_so <= r.out_strobe; + spw_do <= r.out_data; + spw_so <= r.out_strobe; end if; end process; diff --git a/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwxmit_fast.vhd b/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwxmit_fast.vhd index fe1f9e150..034970e3d 100644 --- a/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwxmit_fast.vhd +++ b/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/SPW_CODEC/spacewire_light_codec_err/spwxmit_fast.vhd @@ -149,215 +149,208 @@ use work.spwpkg.all; entity spwxmit_fast is - port ( + port( -- System clock. - clk: in std_logic; - + clk : in std_logic; -- Transmit clock. - txclk: in std_logic; - + txclk : in std_logic; -- Synchronous reset (active-high) -- Used asynchronously by fast clock domain (must be glitch-free). - rst: in std_logic; - + rst : in std_logic; -- Scaling factor minus 1, used to scale the system clock into the -- transmission bit rate. The system clock is divided by -- (unsigned(divcnt) + 1). Changing this signal will immediately -- change the transmission rate. - divcnt: in std_logic_vector(7 downto 0); - + divcnt : in std_logic_vector(7 downto 0); -- Input signals from spwlink. - xmiti: in spw_xmit_in_type; - + xmiti : in spw_xmit_in_type; -- Output signals to spwlink. - xmito: out spw_xmit_out_type; - + xmito : out spw_xmit_out_type; -- Data Out signal to SpaceWire bus. - spw_do: out std_logic; - + spw_do : out std_logic; -- Strobe Out signal to SpaceWire bus. - spw_so: out std_logic + spw_so : out std_logic ); -- Turn off FSM extraction to avoid synchronization problems. - attribute FSM_EXTRACT: string; - attribute FSM_EXTRACT of spwxmit_fast: entity is "NO"; + attribute FSM_EXTRACT : string; + attribute FSM_EXTRACT of spwxmit_fast : entity is "NO"; end entity spwxmit_fast; architecture spwxmit_fast_arch of spwxmit_fast is -- Convert boolean to std_logic. - type bool_to_logic_type is array(boolean) of std_ulogic; - constant bool_to_logic: bool_to_logic_type := (false => '0', true => '1'); + type bool_to_logic_type is array (boolean) of std_ulogic; + constant bool_to_logic : bool_to_logic_type := (false => '0', true => '1'); -- Data records passed between clock domains. type token_type is record - tick: std_ulogic; -- send time code - fct: std_ulogic; -- send FCT - fctpiggy: std_ulogic; -- send FCT and N-char - flag: std_ulogic; -- send EOP or EEP - char: std_logic_vector(7 downto 0); -- character or time code + tick : std_ulogic; -- send time code + fct : std_ulogic; -- send FCT + fctpiggy : std_ulogic; -- send FCT and N-char + flag : std_ulogic; -- send EOP or EEP + char : std_logic_vector(7 downto 0); -- character or time code end record; -- Registers in txclk domain type txregs_type is record -- sync to system clock domain - txflip0: std_ulogic; - txflip1: std_ulogic; + txflip0 : std_ulogic; + txflip1 : std_ulogic; -- stage B - b_update: std_ulogic; - b_mux: std_ulogic; - b_txflip: std_ulogic; - b_valid: std_ulogic; - b_token: token_type; + b_update : std_ulogic; + b_mux : std_ulogic; + b_txflip : std_ulogic; + b_valid : std_ulogic; + b_token : token_type; -- stage C - c_update: std_ulogic; - c_busy: std_ulogic; - c_esc: std_ulogic; - c_fct: std_ulogic; - c_bits: std_logic_vector(8 downto 0); + c_update : std_ulogic; + c_busy : std_ulogic; + c_esc : std_ulogic; + c_fct : std_ulogic; + c_bits : std_logic_vector(8 downto 0); -- stage D - d_bits: std_logic_vector(8 downto 0); - d_cnt4: std_ulogic; - d_cnt10: std_ulogic; + d_bits : std_logic_vector(8 downto 0); + d_cnt4 : std_ulogic; + d_cnt10 : std_ulogic; -- stage E - e_valid: std_ulogic; - e_shift: std_logic_vector(9 downto 0); - e_count: std_logic_vector(9 downto 0); - e_parity: std_ulogic; + e_valid : std_ulogic; + e_shift : std_logic_vector(9 downto 0); + e_count : std_logic_vector(9 downto 0); + e_parity : std_ulogic; -- stage F - f_spwdo: std_ulogic; - f_spwso: std_ulogic; + f_spwdo : std_ulogic; + f_spwso : std_ulogic; -- tx clock enable logic - txclken: std_ulogic; - txclkpre: std_ulogic; - txclkcnt: std_logic_vector(7 downto 0); - txclkcy: std_logic_vector(2 downto 0); - txclkdone: std_logic_vector(1 downto 0); - txclkdiv: std_logic_vector(7 downto 0); - txdivnorm: std_ulogic; + txclken : std_ulogic; + txclkpre : std_ulogic; + txclkcnt : std_logic_vector(7 downto 0); + txclkcy : std_logic_vector(2 downto 0); + txclkdone : std_logic_vector(1 downto 0); + txclkdiv : std_logic_vector(7 downto 0); + txdivnorm : std_ulogic; end record; -- Registers in system clock domain type regs_type is record -- sync status to txclk domain - txenreg: std_ulogic; - txdivreg: std_logic_vector(7 downto 0); - txdivnorm: std_ulogic; - txdivtmp: std_logic_vector(1 downto 0); - txdivsafe: std_ulogic; + txenreg : std_ulogic; + txdivreg : std_logic_vector(7 downto 0); + txdivnorm : std_ulogic; + txdivtmp : std_logic_vector(1 downto 0); + txdivsafe : std_ulogic; -- data stream to txclk domain - sysflip0: std_ulogic; - sysflip1: std_ulogic; - token0: token_type; - token1: token_type; - tokmux: std_ulogic; + sysflip0 : std_ulogic; + sysflip1 : std_ulogic; + token0 : token_type; + token1 : token_type; + tokmux : std_ulogic; -- transmitter management - pend_fct: std_ulogic; -- '1' if an outgoing FCT is pending - pend_char: std_ulogic; -- '1' if an outgoing N-Char is pending - pend_data: std_logic_vector(8 downto 0); -- control flag and data bits of pending char - pend_tick: std_ulogic; -- '1' if an outgoing time tick is pending - pend_time: std_logic_vector(7 downto 0); -- data bits of pending time tick - allow_fct: std_ulogic; -- '1' when allowed to send FCTs - allow_char: std_ulogic; -- '1' when allowed to send data and time - sent_fct: std_ulogic; -- '1' when at least one FCT token was sent + pend_fct : std_ulogic; -- '1' if an outgoing FCT is pending + pend_char : std_ulogic; -- '1' if an outgoing N-Char is pending + pend_data : std_logic_vector(8 downto 0); -- control flag and data bits of pending char + pend_tick : std_ulogic; -- '1' if an outgoing time tick is pending + pend_time : std_logic_vector(7 downto 0); -- data bits of pending time tick + allow_fct : std_ulogic; -- '1' when allowed to send FCTs + allow_char : std_ulogic; -- '1' when allowed to send data and time + sent_fct : std_ulogic; -- '1' when at least one FCT token was sent end record; -- Initial state of system clock domain - constant token_reset: token_type := ( - tick => '0', - fct => '0', - fctpiggy => '0', - flag => '0', - char => (others => '0') ); - constant regs_reset: regs_type := ( - txenreg => '0', - txdivreg => (others => '0'), - txdivnorm => '0', - txdivtmp => "00", - txdivsafe => '0', - sysflip0 => '0', - sysflip1 => '0', - token0 => token_reset, - token1 => token_reset, - tokmux => '0', - pend_fct => '0', - pend_char => '0', - pend_data => (others => '0'), - pend_tick => '0', - pend_time => (others => '0'), - allow_fct => '0', - allow_char => '0', - sent_fct => '0' ); + constant token_reset : token_type := ( + tick => '0', + fct => '0', + fctpiggy => '0', + flag => '0', + char => (others => '0')); + constant regs_reset : regs_type := ( + txenreg => '0', + txdivreg => (others => '0'), + txdivnorm => '0', + txdivtmp => "00", + txdivsafe => '0', + sysflip0 => '0', + sysflip1 => '0', + token0 => token_reset, + token1 => token_reset, + tokmux => '0', + pend_fct => '0', + pend_char => '0', + pend_data => (others => '0'), + pend_tick => '0', + pend_time => (others => '0'), + allow_fct => '0', + allow_char => '0', + sent_fct => '0'); -- Signals that are re-synchronized from system clock to txclk domain. type synctx_type is record - rstn: std_ulogic; - sysflip0: std_ulogic; - sysflip1: std_ulogic; - txen: std_ulogic; - txdivsafe: std_ulogic; + rstn : std_ulogic; + sysflip0 : std_ulogic; + sysflip1 : std_ulogic; + txen : std_ulogic; + txdivsafe : std_ulogic; end record; -- Signals that are re-synchronized from txclk to system clock domain. type syncsys_type is record - txflip0: std_ulogic; - txflip1: std_ulogic; + txflip0 : std_ulogic; + txflip1 : std_ulogic; end record; -- Registers - signal rtx: txregs_type; - signal rtxin: txregs_type; - signal r: regs_type := regs_reset; - signal rin: regs_type; + signal rtx : txregs_type; + signal rtxin : txregs_type; + signal r : regs_type := regs_reset; + signal rin : regs_type; -- Synchronized signals after crossing clock domains. - signal synctx: synctx_type; - signal syncsys: syncsys_type; + signal synctx : synctx_type; + signal syncsys : syncsys_type; -- Output flip-flops - signal s_spwdo: std_logic; - signal s_spwso: std_logic; + signal s_spwdo : std_logic; + signal s_spwso : std_logic; -- Force use of IOB flip-flops - attribute IOB: string; - attribute IOB of s_spwdo: signal is "TRUE"; - attribute IOB of s_spwso: signal is "TRUE"; + attribute IOB : string; + attribute IOB of s_spwdo : signal is "TRUE"; + attribute IOB of s_spwso : signal is "TRUE"; begin -- Reset synchronizer for txclk domain. - synctx_rst: syncdff - port map ( clk => txclk, rst => rst, di => '1', do => synctx.rstn ); + synctx_rst : syncdff + port map(clk => txclk, rst => rst, di => '1', do => synctx.rstn); -- Synchronize signals from system clock domain to txclk domain. - synctx_sysflip0: syncdff - port map ( clk => txclk, rst => rst, di => r.sysflip0, do => synctx.sysflip0 ); - synctx_sysflip1: syncdff - port map ( clk => txclk, rst => rst, di => r.sysflip1, do => synctx.sysflip1 ); - synctx_txen: syncdff - port map ( clk => txclk, rst => rst, di => r.txenreg, do => synctx.txen ); - synctx_txdivsafe: syncdff - port map ( clk => txclk, rst => rst, di => r.txdivsafe, do => synctx.txdivsafe ); + synctx_sysflip0 : syncdff + port map(clk => txclk, rst => rst, di => r.sysflip0, do => synctx.sysflip0); + synctx_sysflip1 : syncdff + port map(clk => txclk, rst => rst, di => r.sysflip1, do => synctx.sysflip1); + synctx_txen : syncdff + port map(clk => txclk, rst => rst, di => r.txenreg, do => synctx.txen); + synctx_txdivsafe : syncdff + port map(clk => txclk, rst => rst, di => r.txdivsafe, do => synctx.txdivsafe); -- Synchronize signals from txclk domain to system clock domain. - syncsys_txflip0: syncdff - port map ( clk => clk, rst => rst, di => rtx.txflip0, do => syncsys.txflip0 ); - syncsys_txflip1: syncdff - port map ( clk => clk, rst => rst, di => rtx.txflip1, do => syncsys.txflip1 ); + syncsys_txflip0 : syncdff + port map(clk => clk, rst => rst, di => rtx.txflip0, do => syncsys.txflip0); + syncsys_txflip1 : syncdff + port map(clk => clk, rst => rst, di => rtx.txflip1, do => syncsys.txflip1); -- Drive SpaceWire output signals - spw_do <= s_spwdo; - spw_so <= s_spwso; + spw_do <= s_spwdo; + spw_so <= s_spwso; -- Combinatorial process - process (r, rtx, rst, divcnt, xmiti, synctx, syncsys) is - variable v: regs_type; - variable vtx: txregs_type; - variable v_needtoken: std_ulogic; - variable v_havetoken: std_ulogic; - variable v_token: token_type; + process(r, rtx, rst, divcnt, xmiti, synctx, syncsys) is + variable v : regs_type; + variable vtx : txregs_type; + variable v_needtoken : std_ulogic; + variable v_havetoken : std_ulogic; + variable v_token : token_type; begin v := r; vtx := rtx; @@ -406,45 +399,42 @@ begin -- Time-codes are broken into two tokens: ESC + char. -- Enable c_esc on the first pass of a NULL or a time-code. - vtx.c_esc := (rtx.b_token.tick or (not rtx.b_valid)) and - (not rtx.c_esc); + vtx.c_esc := (rtx.b_token.tick or (not rtx.b_valid)) and (not rtx.c_esc); -- Enable c_fct on the first pass of an FCT and on -- the second pass of a NULL (also the first pass, but c_esc -- is stronger than c_fct). - vtx.c_fct := (rtx.b_token.fct and (not rtx.c_busy)) or - (not rtx.b_valid); + vtx.c_fct := (rtx.b_token.fct and (not rtx.c_busy)) or (not rtx.b_valid); -- Enable c_busy on the first pass of a NULL or a time-code -- or a piggy-backed FCT. This will tell stage B that we are -- not done yet. - vtx.c_busy := (rtx.b_token.tick or (not rtx.b_valid) or - rtx.b_token.fctpiggy) and (not rtx.c_busy); + vtx.c_busy := (rtx.b_token.tick or (not rtx.b_valid) or rtx.b_token.fctpiggy) and (not rtx.c_busy); if rtx.b_token.flag = '1' then if rtx.b_token.char(0) = '0' then -- prepare to send EOP - vtx.c_bits := "000000101"; -- EOP = P101 + vtx.c_bits := "000000101"; -- EOP = P101 else -- prepare to send EEP - vtx.c_bits := "000000011"; -- EEP = P110 + vtx.c_bits := "000000011"; -- EEP = P110 end if; else -- prepare to send data char - vtx.c_bits := rtx.b_token.char & '0'; + vtx.c_bits := rtx.b_token.char & '0'; end if; end if; -- Stage D: Prepare to transmit FCT, ESC, or the stuff from stage C. if rtx.c_esc = '1' then -- prepare to send ESC - vtx.d_bits := "000000111"; -- ESC = P111 - vtx.d_cnt4 := '1'; -- 3 bits + implicit parity bit + vtx.d_bits := "000000111"; -- ESC = P111 + vtx.d_cnt4 := '1'; -- 3 bits + implicit parity bit vtx.d_cnt10 := '0'; elsif rtx.c_fct = '1' then -- prepare to send FCT - vtx.d_bits := "000000001"; -- FCT = P100 - vtx.d_cnt4 := '1'; -- 3 bits + implicit parity bit + vtx.d_bits := "000000001"; -- FCT = P100 + vtx.d_cnt4 := '1'; -- 3 bits + implicit parity bit vtx.d_cnt10 := '0'; else -- send the stuff from stage C. @@ -457,11 +447,11 @@ begin if rtx.txclken = '1' then if rtx.e_count(0) = '1' then -- reload shift register; output parity bit - vtx.e_valid := '1'; + vtx.e_valid := '1'; vtx.e_shift(vtx.e_shift'high downto 1) := rtx.d_bits; - vtx.e_shift(0) := not (rtx.e_parity xor rtx.d_bits(0)); - vtx.e_count := rtx.d_cnt10 & "00000" & rtx.d_cnt4 & "000"; - vtx.e_parity := rtx.d_bits(0); + vtx.e_shift(0) := not (rtx.e_parity xor rtx.d_bits(0)); + vtx.e_count := rtx.d_cnt10 & "00000" & rtx.d_cnt4 & "000"; + vtx.e_parity := rtx.d_bits(0); else -- shift bits to output; update parity bit vtx.e_shift := '0' & rtx.e_shift(rtx.e_shift'high downto 1); @@ -493,15 +483,15 @@ begin vtx.txclkcnt(5 downto 4) := std_logic_vector(unsigned(rtx.txclkcnt(5 downto 4)) - unsigned(rtx.txclkcy(1 downto 1))); vtx.txclkcnt(7 downto 6) := std_logic_vector(unsigned(rtx.txclkcnt(7 downto 6)) - unsigned(rtx.txclkcy(2 downto 2))); -- propagate carry in blocks of two bits - vtx.txclkcy(0) := bool_to_logic(rtx.txclkcnt(1 downto 0) = "00"); - vtx.txclkcy(1) := rtx.txclkcy(0) and bool_to_logic(rtx.txclkcnt(3 downto 2) = "00"); - vtx.txclkcy(2) := rtx.txclkcy(1) and bool_to_logic(rtx.txclkcnt(5 downto 4) = "00"); + vtx.txclkcy(0) := bool_to_logic(rtx.txclkcnt(1 downto 0) = "00"); + vtx.txclkcy(1) := rtx.txclkcy(0) and bool_to_logic(rtx.txclkcnt(3 downto 2) = "00"); + vtx.txclkcy(2) := rtx.txclkcy(1) and bool_to_logic(rtx.txclkcnt(5 downto 4) = "00"); -- detect value 2 in counter - vtx.txclkdone(0) := bool_to_logic(rtx.txclkcnt(3 downto 0) = "0010"); - vtx.txclkdone(1) := bool_to_logic(rtx.txclkcnt(7 downto 4) = "0000"); + vtx.txclkdone(0) := bool_to_logic(rtx.txclkcnt(3 downto 0) = "0010"); + vtx.txclkdone(1) := bool_to_logic(rtx.txclkcnt(7 downto 4) = "0000"); -- trigger txclken - vtx.txclken := (rtx.txclkdone(0) and rtx.txclkdone(1)) or rtx.txclkpre; - vtx.txclkpre := (not rtx.txdivnorm) and ((not rtx.txclkpre) or (not rtx.txclkdiv(0))); + vtx.txclken := (rtx.txclkdone(0) and rtx.txclkdone(1)) or rtx.txclkpre; + vtx.txclkpre := (not rtx.txdivnorm) and ((not rtx.txclkpre) or (not rtx.txclkdiv(0))); -- reload counter if rtx.txclken = '1' then vtx.txclkcnt := rtx.txclkdiv; @@ -517,21 +507,21 @@ begin -- Transmitter disabled. if synctx.txen = '0' then - vtx.txflip0 := '0'; - vtx.txflip1 := '0'; - vtx.b_update := '0'; - vtx.b_mux := '0'; - vtx.b_valid := '0'; - vtx.c_update := '0'; - vtx.c_busy := '1'; - vtx.c_esc := '1'; -- need to send 2nd part of NULL - vtx.c_fct := '1'; - vtx.d_bits := "000000111"; -- ESC = P111 - vtx.d_cnt4 := '1'; -- 3 bits + implicit parity bit - vtx.d_cnt10 := '0'; - vtx.e_valid := '0'; - vtx.e_parity := '0'; - vtx.e_count := (0 => '1', others => '0'); + vtx.txflip0 := '0'; + vtx.txflip1 := '0'; + vtx.b_update := '0'; + vtx.b_mux := '0'; + vtx.b_valid := '0'; + vtx.c_update := '0'; + vtx.c_busy := '1'; + vtx.c_esc := '1'; -- need to send 2nd part of NULL + vtx.c_fct := '1'; + vtx.d_bits := "000000111"; -- ESC = P111 + vtx.d_cnt4 := '1'; -- 3 bits + implicit parity bit + vtx.d_cnt10 := '0'; + vtx.e_valid := '0'; + vtx.e_parity := '0'; + vtx.e_count := (0 => '1', others => '0'); end if; -- Reset. @@ -548,7 +538,7 @@ begin -- ---- SYSTEM CLOCK DOMAIN ---- -- Hold divcnt and txen for use by txclk domain. - v.txdivtmp := std_logic_vector(unsigned(r.txdivtmp) - 1); + v.txdivtmp := std_logic_vector(unsigned(r.txdivtmp) - 1); if r.txdivtmp = "00" then if r.txdivsafe = '0' then -- Latch the current value of divcnt and txen. @@ -569,26 +559,26 @@ begin -- Pass falling edge of txen signal as soon as possible. if xmiti.txen = '0' then - v.txenreg := '0'; + v.txenreg := '0'; end if; -- Store requests for FCT transmission. if xmiti.fct_in = '1' and r.allow_fct = '1' then - v.pend_fct := '1'; + v.pend_fct := '1'; end if; if xmiti.txen = '0' then -- Transmitter disabled; reset state. - v.sysflip0 := '0'; - v.sysflip1 := '0'; - v.tokmux := '0'; - v.pend_fct := '0'; - v.pend_char := '0'; - v.pend_tick := '0'; - v.allow_fct := '0'; - v.allow_char := '0'; - v.sent_fct := '0'; + v.sysflip0 := '0'; + v.sysflip1 := '0'; + v.tokmux := '0'; + v.pend_fct := '0'; + v.pend_char := '0'; + v.pend_tick := '0'; + v.allow_fct := '0'; + v.allow_char := '0'; + v.sent_fct := '0'; else @@ -606,23 +596,23 @@ begin -- Prepare new token. if r.allow_char = '1' and r.pend_tick = '1' then -- prepare to send time code - v_token.tick := '1'; - v_token.fct := '0'; + v_token.tick := '1'; + v_token.fct := '0'; v_token.fctpiggy := '0'; - v_token.flag := '0'; - v_token.char := r.pend_time; - v_havetoken := '1'; + v_token.flag := '0'; + v_token.char := r.pend_time; + v_havetoken := '1'; if v_needtoken = '1' then v.pend_tick := '0'; end if; else if r.allow_fct = '1' and (xmiti.fct_in = '1' or r.pend_fct = '1') then -- prepare to send FCT - v_token.fct := '1'; - v_havetoken := '1'; + v_token.fct := '1'; + v_havetoken := '1'; if v_needtoken = '1' then - v.pend_fct := '0'; - v.sent_fct := '1'; + v.pend_fct := '0'; + v.sent_fct := '1'; end if; end if; if r.allow_char = '1' and r.pend_char = '1' then @@ -630,9 +620,9 @@ begin -- Note: it is possible to send an FCT and an N-Char -- together by enabling the fctpiggy flag. v_token.fctpiggy := v_token.fct; - v_token.flag := r.pend_data(8); - v_token.char := r.pend_data(7 downto 0); - v_havetoken := '1'; + v_token.flag := r.pend_data(8); + v_token.char := r.pend_data(7 downto 0); + v_havetoken := '1'; if v_needtoken = '1' then v.pend_char := '0'; end if; @@ -643,15 +633,15 @@ begin if v_havetoken = '1' then if r.tokmux = '0' then if r.sysflip0 = syncsys.txflip0 then - v.sysflip0 := not r.sysflip0; - v.token0 := v_token; - v.tokmux := '1'; + v.sysflip0 := not r.sysflip0; + v.token0 := v_token; + v.tokmux := '1'; end if; else if r.sysflip1 = syncsys.txflip1 then - v.sysflip1 := not r.sysflip1; - v.token1 := v_token; - v.tokmux := '0'; + v.sysflip1 := not r.sysflip1; + v.token1 := v_token; + v.tokmux := '0'; end if; end if; end if; @@ -662,8 +652,8 @@ begin -- Store request for data transmission. if xmiti.txwrite = '1' and r.allow_char = '1' and r.pend_char = '0' then - v.pend_char := '1'; - v.pend_data := xmiti.txflag & xmiti.txdata; + v.pend_char := '1'; + v.pend_data := xmiti.txflag & xmiti.txdata; end if; -- Store requests for time tick transmission. @@ -684,33 +674,31 @@ begin -- Set fctack high if (FCT requested) and (FCTs allowed) AND -- (no FCT pending) - xmito.fctack <= xmiti.fct_in and xmiti.txen and r.allow_fct and - (not r.pend_fct); + xmito.fctack <= xmiti.fct_in and xmiti.txen and r.allow_fct and (not r.pend_fct); -- Set txack high if (character requested) AND (characters allowed) AND -- (no character pending) - xmito.txack <= xmiti.txwrite and xmiti.txen and r.allow_char and - (not r.pend_char); + xmito.txack <= xmiti.txwrite and xmiti.txen and r.allow_char and (not r.pend_char); -- Update registers. - rin <= v; - rtxin <= vtx; + rin <= v; + rtxin <= vtx; end process; -- Synchronous process in txclk domain - process (txclk) is + process(txclk) is begin if rising_edge(txclk) then -- drive spacewire output signals s_spwdo <= rtx.f_spwdo; s_spwso <= rtx.f_spwso; -- update registers - rtx <= rtxin; + rtx <= rtxin; end if; end process; -- Synchronous process in system clock domain - process (clk) is + process(clk) is begin if rising_edge(clk) then -- update registers diff --git a/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/spwc_spacewire_channel_top.vhd b/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/spwc_spacewire_channel_top.vhd index 9fad1246f..0e16e6581 100644 --- a/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/spwc_spacewire_channel_top.vhd +++ b/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel/spwc_spacewire_channel_top.vhd @@ -17,265 +17,266 @@ use work.spwc_errinj_pkg.all; use work.spwc_leds_controller_pkg.all; entity spwc_spacewire_channel_top is - generic( - g_SPWC_TESTBENCH_MODE : std_logic := '0' - ); - port( - reset_i : in std_logic := '0'; -- -- reset_sink.reset - clk_100_i : in std_logic := '0'; -- -- clock_sink_100mhz.clk - clk_200_i : in std_logic := '0'; -- -- clock_sink_200mhz.clk - spw_lvds_p_data_in_i : in std_logic := '0'; -- -- conduit_end_spacewire_lvds.spw_lvds_p_data_in_signal - spw_lvds_n_data_in_i : in std_logic := '0'; -- -- .spw_lvds_n_data_in_signal - spw_lvds_p_strobe_in_i : in std_logic := '0'; -- -- .spw_lvds_p_strobe_in_signal - spw_lvds_n_strobe_in_i : in std_logic := '0'; -- -- .spw_lvds_n_strobe_in_signal - spw_lvds_p_data_out_o : out std_logic; -- -- .spw_lvds_p_data_out_signal - spw_lvds_n_data_out_o : out std_logic; -- -- .spw_lvds_n_data_out_signal - spw_lvds_p_strobe_out_o : out std_logic; -- -- .spw_lvds_p_strobe_out_signal - spw_lvds_n_strobe_out_o : out std_logic; -- -- .spw_lvds_n_strobe_out_signal - spw_rx_enable_i : in std_logic := '0'; -- -- conduit_end_spacewire_enable.spw_rx_enable_signal - spw_tx_enable_i : in std_logic := '0'; -- -- .spw_tx_enable_signal - spw_red_status_led_o : out std_logic; -- -- conduit_end_spacewire_leds.spw_red_status_led_signal - spw_green_status_led_o : out std_logic; -- -- .spw_green_status_led_signal - spw_link_command_autostart_i : in std_logic := '0'; -- -- conduit_end_spacewire_channel.spw_link_command_autostart_signal - spw_link_command_linkstart_i : in std_logic := '0'; -- -- .spw_link_command_linkstart_signal - spw_link_command_linkdis_i : in std_logic := '0'; -- -- .spw_link_command_linkdis_signal - spw_link_command_txdivcnt_i : in std_logic_vector(7 downto 0) := (others => '0'); -- .spw_link_command_txdivcnt_signal - spw_timecode_tx_tick_in_i : in std_logic := '0'; -- -- .spw_timecode_tx_tick_in_signal - spw_timecode_tx_ctrl_in_i : in std_logic_vector(1 downto 0) := (others => '0'); -- .spw_timecode_tx_ctrl_in_signal - spw_timecode_tx_time_in_i : in std_logic_vector(5 downto 0) := (others => '0'); -- .spw_timecode_tx_time_in_signal - spw_data_rx_command_rxread_i : in std_logic := '0'; -- -- .spw_data_rx_command_rxread_signal - spw_data_tx_command_txwrite_i : in std_logic := '0'; -- -- .spw_data_tx_command_txwrite_signal - spw_data_tx_command_txflag_i : in std_logic := '0'; -- -- .spw_data_tx_command_txflag_signal - spw_data_tx_command_txdata_i : in std_logic_vector(7 downto 0) := (others => '0'); -- .spw_data_tx_command_txdata_signal - spw_errinj_ctrl_start_errinj_i : in std_logic := '0'; -- -- .spw_errinj_ctrl_start_errinj_signal - spw_errinj_ctrl_reset_errinj_i : in std_logic := '0'; -- -- .spw_errinj_ctrl_reset_errinj_signal - spw_errinj_ctrl_errinj_code_i : in std_logic_vector(3 downto 0) := (others => '0'); -- .spw_errinj_ctrl_errinj_code_signal - spw_link_status_started_o : out std_logic; -- -- .spw_link_status_started_signal - spw_link_status_connecting_o : out std_logic; -- -- .spw_link_status_connecting_signal - spw_link_status_running_o : out std_logic; -- -- .spw_link_status_running_signal - spw_link_error_errdisc_o : out std_logic; -- -- .spw_link_error_errdisc_signal - spw_link_error_errpar_o : out std_logic; -- -- .spw_link_error_errpar_signal - spw_link_error_erresc_o : out std_logic; -- -- .spw_link_error_erresc_signal - spw_link_error_errcred_o : out std_logic; -- -- .spw_link_error_errcred_signal - spw_timecode_rx_tick_out_o : out std_logic; -- -- .spw_timecode_rx_tick_out_signal - spw_timecode_rx_ctrl_out_o : out std_logic_vector(1 downto 0); -- -- .spw_timecode_rx_ctrl_out_signal - spw_timecode_rx_time_out_o : out std_logic_vector(5 downto 0); -- -- .spw_timecode_rx_time_out_signal - spw_data_rx_status_rxvalid_o : out std_logic; -- -- .spw_data_rx_status_rxvalid_signal - spw_data_rx_status_rxhalff_o : out std_logic; -- -- .spw_data_rx_status_rxhalff_signal - spw_data_rx_status_rxflag_o : out std_logic; -- -- .spw_data_rx_status_rxflag_signal - spw_data_rx_status_rxdata_o : out std_logic_vector(7 downto 0); -- -- .spw_data_rx_status_rxdata_signal - spw_data_tx_status_txrdy_o : out std_logic; -- -- .spw_data_tx_status_txrdy_signal - spw_data_tx_status_txhalff_o : out std_logic; -- -- .spw_data_tx_status_txhalff_signal - spw_errinj_ctrl_errinj_busy_o : out std_logic; -- -- .spw_errinj_ctrl_errinj_busy_signal - spw_errinj_ctrl_errinj_ready_o : out std_logic --- -- .spw_errinj_ctrl_errinj_ready_signal - ); + generic( + g_SPWC_TESTBENCH_MODE : std_logic := '0' + ); + port( + reset_i : in std_logic := '0'; -- -- reset_sink.reset + clk_100_i : in std_logic := '0'; -- -- clock_sink_100mhz.clk + clk_200_i : in std_logic := '0'; -- -- clock_sink_200mhz.clk + spw_lvds_p_data_in_i : in std_logic := '0'; -- -- conduit_end_spacewire_lvds.spw_lvds_p_data_in_signal + spw_lvds_n_data_in_i : in std_logic := '0'; -- -- .spw_lvds_n_data_in_signal + spw_lvds_p_strobe_in_i : in std_logic := '0'; -- -- .spw_lvds_p_strobe_in_signal + spw_lvds_n_strobe_in_i : in std_logic := '0'; -- -- .spw_lvds_n_strobe_in_signal + spw_lvds_p_data_out_o : out std_logic; -- -- .spw_lvds_p_data_out_signal + spw_lvds_n_data_out_o : out std_logic; -- -- .spw_lvds_n_data_out_signal + spw_lvds_p_strobe_out_o : out std_logic; -- -- .spw_lvds_p_strobe_out_signal + spw_lvds_n_strobe_out_o : out std_logic; -- -- .spw_lvds_n_strobe_out_signal + spw_rx_enable_i : in std_logic := '0'; -- -- conduit_end_spacewire_enable.spw_rx_enable_signal + spw_tx_enable_i : in std_logic := '0'; -- -- .spw_tx_enable_signal + spw_red_status_led_o : out std_logic; -- -- conduit_end_spacewire_leds.spw_red_status_led_signal + spw_green_status_led_o : out std_logic; -- -- .spw_green_status_led_signal + spw_link_command_enable_i : in std_logic := '0'; -- -- conduit_end_spacewire_channel.spw_link_command_enable_signal + spw_link_command_autostart_i : in std_logic := '0'; -- -- .spw_link_command_autostart_signal + spw_link_command_linkstart_i : in std_logic := '0'; -- -- .spw_link_command_linkstart_signal + spw_link_command_linkdis_i : in std_logic := '0'; -- -- .spw_link_command_linkdis_signal + spw_link_command_txdivcnt_i : in std_logic_vector(7 downto 0) := (others => '0'); -- .spw_link_command_txdivcnt_signal + spw_timecode_tx_tick_in_i : in std_logic := '0'; -- -- .spw_timecode_tx_tick_in_signal + spw_timecode_tx_ctrl_in_i : in std_logic_vector(1 downto 0) := (others => '0'); -- .spw_timecode_tx_ctrl_in_signal + spw_timecode_tx_time_in_i : in std_logic_vector(5 downto 0) := (others => '0'); -- .spw_timecode_tx_time_in_signal + spw_data_rx_command_rxread_i : in std_logic := '0'; -- -- .spw_data_rx_command_rxread_signal + spw_data_tx_command_txwrite_i : in std_logic := '0'; -- -- .spw_data_tx_command_txwrite_signal + spw_data_tx_command_txflag_i : in std_logic := '0'; -- -- .spw_data_tx_command_txflag_signal + spw_data_tx_command_txdata_i : in std_logic_vector(7 downto 0) := (others => '0'); -- .spw_data_tx_command_txdata_signal + spw_errinj_ctrl_start_errinj_i : in std_logic := '0'; -- -- .spw_errinj_ctrl_start_errinj_signal + spw_errinj_ctrl_reset_errinj_i : in std_logic := '0'; -- -- .spw_errinj_ctrl_reset_errinj_signal + spw_errinj_ctrl_errinj_code_i : in std_logic_vector(3 downto 0) := (others => '0'); -- .spw_errinj_ctrl_errinj_code_signal + spw_link_status_started_o : out std_logic; -- -- .spw_link_status_started_signal + spw_link_status_connecting_o : out std_logic; -- -- .spw_link_status_connecting_signal + spw_link_status_running_o : out std_logic; -- -- .spw_link_status_running_signal + spw_link_error_errdisc_o : out std_logic; -- -- .spw_link_error_errdisc_signal + spw_link_error_errpar_o : out std_logic; -- -- .spw_link_error_errpar_signal + spw_link_error_erresc_o : out std_logic; -- -- .spw_link_error_erresc_signal + spw_link_error_errcred_o : out std_logic; -- -- .spw_link_error_errcred_signal + spw_timecode_rx_tick_out_o : out std_logic; -- -- .spw_timecode_rx_tick_out_signal + spw_timecode_rx_ctrl_out_o : out std_logic_vector(1 downto 0); -- -- .spw_timecode_rx_ctrl_out_signal + spw_timecode_rx_time_out_o : out std_logic_vector(5 downto 0); -- -- .spw_timecode_rx_time_out_signal + spw_data_rx_status_rxvalid_o : out std_logic; -- -- .spw_data_rx_status_rxvalid_signal + spw_data_rx_status_rxhalff_o : out std_logic; -- -- .spw_data_rx_status_rxhalff_signal + spw_data_rx_status_rxflag_o : out std_logic; -- -- .spw_data_rx_status_rxflag_signal + spw_data_rx_status_rxdata_o : out std_logic_vector(7 downto 0); -- -- .spw_data_rx_status_rxdata_signal + spw_data_tx_status_txrdy_o : out std_logic; -- -- .spw_data_tx_status_txrdy_signal + spw_data_tx_status_txhalff_o : out std_logic; -- -- .spw_data_tx_status_txhalff_signal + spw_errinj_ctrl_errinj_busy_o : out std_logic; -- -- .spw_errinj_ctrl_errinj_busy_signal + spw_errinj_ctrl_errinj_ready_o : out std_logic --- -- .spw_errinj_ctrl_errinj_ready_signal + ); end entity spwc_spacewire_channel_top; architecture rtl of spwc_spacewire_channel_top is - -- Alias -- + -- Alias -- - -- Basic Alias - alias a_avs_clock is clk_100_i; - alias a_spw_clock is clk_200_i; - alias a_reset is reset_i; + -- Basic Alias + alias a_avs_clock is clk_100_i; + alias a_spw_clock is clk_200_i; + alias a_reset is reset_i; - -- Constants -- + -- Constants -- - -- Signals -- + -- Signals -- - -- SpaceWire Codec Clock Synchronization Signals (200 MHz) - signal s_spw_codec_link_command_spw : t_spwc_codec_link_command; - signal s_spw_codec_link_status_spw : t_spwc_codec_link_status; - signal s_spw_codec_link_error_spw : t_spwc_codec_link_error; - signal s_spw_codec_timecode_rx_spw : t_spwc_codec_timecode_rx; - signal s_spw_codec_data_rx_status_spw : t_spwc_codec_data_rx_status; - signal s_spw_codec_data_tx_status_spw : t_spwc_codec_data_tx_status; - signal s_spw_codec_err_inj_status_spw : t_spwc_codec_err_inj_status; - signal s_spw_codec_timecode_tx_spw : t_spwc_codec_timecode_tx; - signal s_spw_codec_data_rx_command_spw : t_spwc_codec_data_rx_command; - signal s_spw_codec_data_tx_command_spw : t_spwc_codec_data_tx_command; - signal s_spw_codec_err_inj_command_spw : t_spwc_codec_err_inj_command; + -- SpaceWire Codec Clock Synchronization Signals (200 MHz) + signal s_spw_codec_link_command_spw : t_spwc_codec_link_command; + signal s_spw_codec_link_status_spw : t_spwc_codec_link_status; + signal s_spw_codec_link_error_spw : t_spwc_codec_link_error; + signal s_spw_codec_timecode_rx_spw : t_spwc_codec_timecode_rx; + signal s_spw_codec_data_rx_status_spw : t_spwc_codec_data_rx_status; + signal s_spw_codec_data_tx_status_spw : t_spwc_codec_data_tx_status; + signal s_spw_codec_err_inj_status_spw : t_spwc_codec_err_inj_status; + signal s_spw_codec_timecode_tx_spw : t_spwc_codec_timecode_tx; + signal s_spw_codec_data_rx_command_spw : t_spwc_codec_data_rx_command; + signal s_spw_codec_data_tx_command_spw : t_spwc_codec_data_tx_command; + signal s_spw_codec_err_inj_command_spw : t_spwc_codec_err_inj_command; - -- Spacewire Error Injection Controller Signals - signal s_spw_errinj_controller_control : t_spwc_errinj_controller_control; - signal s_spw_errinj_controller_status : t_spwc_errinj_controller_status; + -- Spacewire Error Injection Controller Signals + signal s_spw_errinj_controller_control : t_spwc_errinj_controller_control; + signal s_spw_errinj_controller_status : t_spwc_errinj_controller_status; - -- SpaceWire Codec Data-Strobe Signals - signal s_spw_codec_ds_encoding_rx : t_spwc_codec_ds_encoding_rx; - signal s_spw_codec_ds_encoding_tx : t_spwc_codec_ds_encoding_tx; + -- SpaceWire Codec Data-Strobe Signals + signal s_spw_codec_ds_encoding_rx : t_spwc_codec_ds_encoding_rx; + signal s_spw_codec_ds_encoding_tx : t_spwc_codec_ds_encoding_tx; - -- SpaceWire LVDS Data-Strobe Signals - signal s_spw_logical_data_in : std_logic; - signal s_spw_logical_strobe_in : std_logic; - signal s_spw_logical_data_out : std_logic; - signal s_spw_logical_strobe_out : std_logic; + -- SpaceWire LVDS Data-Strobe Signals + signal s_spw_logical_data_in : std_logic; + signal s_spw_logical_strobe_in : std_logic; + signal s_spw_logical_data_out : std_logic; + signal s_spw_logical_strobe_out : std_logic; - -- SpaceWire Leds Controller Signals - signal s_spw_leds_control : t_spwc_spw_leds_control; + -- SpaceWire Leds Controller Signals + signal s_spw_leds_control : t_spwc_spw_leds_control; begin - -- Entities Instantiation -- - - -- SpaceWire Codec Clock Domain Synchronization Instantiation - spwc_clk_synchronization_top_inst : entity work.spwc_clk_synchronization_top - port map( - clk_avs_i => a_avs_clock, - clk_spw_i => a_spw_clock, - rst_i => a_reset, - spw_codec_link_command_avs_i.autostart => spw_link_command_autostart_i, - spw_codec_link_command_avs_i.linkstart => spw_link_command_linkstart_i, - spw_codec_link_command_avs_i.linkdis => spw_link_command_linkdis_i, - spw_codec_link_command_avs_i.txdivcnt => spw_link_command_txdivcnt_i, - spw_codec_timecode_tx_avs_i.tick_in => spw_timecode_tx_tick_in_i, - spw_codec_timecode_tx_avs_i.ctrl_in => spw_timecode_tx_ctrl_in_i, - spw_codec_timecode_tx_avs_i.time_in => spw_timecode_tx_time_in_i, - spw_codec_data_rx_command_avs_i.rxread => spw_data_rx_command_rxread_i, - spw_codec_data_tx_command_avs_i.txwrite => spw_data_tx_command_txwrite_i, - spw_codec_data_tx_command_avs_i.txflag => spw_data_tx_command_txflag_i, - spw_codec_data_tx_command_avs_i.txdata => spw_data_tx_command_txdata_i, - spw_errinj_ctrl_control_avs_i.start_errinj => spw_errinj_ctrl_start_errinj_i, - spw_errinj_ctrl_control_avs_i.reset_errinj => spw_errinj_ctrl_reset_errinj_i, - spw_errinj_ctrl_control_avs_i.errinj_code => spw_errinj_ctrl_errinj_code_i, - spw_codec_link_status_spw_i => s_spw_codec_link_status_spw, - spw_codec_link_error_spw_i => s_spw_codec_link_error_spw, - spw_codec_timecode_rx_spw_i => s_spw_codec_timecode_rx_spw, - spw_codec_data_rx_status_spw_i => s_spw_codec_data_rx_status_spw, - spw_codec_data_tx_status_spw_i => s_spw_codec_data_tx_status_spw, - spw_errinj_ctrl_status_spw_i => s_spw_errinj_controller_status, - spw_codec_link_status_avs_o.started => spw_link_status_started_o, - spw_codec_link_status_avs_o.connecting => spw_link_status_connecting_o, - spw_codec_link_status_avs_o.running => spw_link_status_running_o, - spw_codec_link_error_avs_o.errdisc => spw_link_error_errdisc_o, - spw_codec_link_error_avs_o.errpar => spw_link_error_errpar_o, - spw_codec_link_error_avs_o.erresc => spw_link_error_erresc_o, - spw_codec_link_error_avs_o.errcred => spw_link_error_errcred_o, - spw_codec_timecode_rx_avs_o.tick_out => spw_timecode_rx_tick_out_o, - spw_codec_timecode_rx_avs_o.ctrl_out => spw_timecode_rx_ctrl_out_o, - spw_codec_timecode_rx_avs_o.time_out => spw_timecode_rx_time_out_o, - spw_codec_data_rx_status_avs_o.rxvalid => spw_data_rx_status_rxvalid_o, - spw_codec_data_rx_status_avs_o.rxhalff => spw_data_rx_status_rxhalff_o, - spw_codec_data_rx_status_avs_o.rxflag => spw_data_rx_status_rxflag_o, - spw_codec_data_rx_status_avs_o.rxdata => spw_data_rx_status_rxdata_o, - spw_codec_data_tx_status_avs_o.txrdy => spw_data_tx_status_txrdy_o, - spw_codec_data_tx_status_avs_o.txhalff => spw_data_tx_status_txhalff_o, - spw_errinj_ctrl_status_avs_o.errinj_busy => spw_errinj_ctrl_errinj_busy_o, - spw_errinj_ctrl_status_avs_o.errinj_ready => spw_errinj_ctrl_errinj_ready_o, - spw_codec_link_command_spw_o => s_spw_codec_link_command_spw, - spw_codec_timecode_tx_spw_o => s_spw_codec_timecode_tx_spw, - spw_codec_data_rx_command_spw_o => s_spw_codec_data_rx_command_spw, - spw_codec_data_tx_command_spw_o => s_spw_codec_data_tx_command_spw, - spw_errinj_ctrl_control_spw_o => s_spw_errinj_controller_control - ); - - -- SpaceWire Error Injection Controller Instantiation - spwc_errinj_controller_ent_inst : entity work.spwc_errinj_controller_ent - port map( - clk_i => a_spw_clock, - rst_i => a_reset, - errinj_controller_control_i => s_spw_errinj_controller_control, - spw_codec_link_status_i => s_spw_codec_link_status_spw, - spw_codec_err_inj_status_i => s_spw_codec_err_inj_status_spw, - errinj_controller_status_o => s_spw_errinj_controller_status, - spw_codec_err_inj_command_o => s_spw_codec_err_inj_command_spw - ); - - -- SpaceWire Codec Instantiation - spwc_codec_ent_inst : entity work.spwc_codec_ent - port map( - clk_spw_i => a_spw_clock, - rst_i => a_reset, - spw_codec_link_command_i => s_spw_codec_link_command_spw, - spw_codec_ds_encoding_rx_i => s_spw_codec_ds_encoding_rx, - spw_codec_timecode_tx_i => s_spw_codec_timecode_tx_spw, - spw_codec_data_rx_command_i => s_spw_codec_data_rx_command_spw, - spw_codec_data_tx_command_i => s_spw_codec_data_tx_command_spw, - spw_codec_err_inj_command_i => s_spw_codec_err_inj_command_spw, - spw_codec_link_status_o => s_spw_codec_link_status_spw, - spw_codec_ds_encoding_tx_o => s_spw_codec_ds_encoding_tx, - spw_codec_link_error_o => s_spw_codec_link_error_spw, - spw_codec_timecode_rx_o => s_spw_codec_timecode_rx_spw, - spw_codec_data_rx_status_o => s_spw_codec_data_rx_status_spw, - spw_codec_data_tx_status_o => s_spw_codec_data_tx_status_spw, - spw_codec_err_inj_status_o => s_spw_codec_err_inj_status_spw - ); - - -- SpaceWire Data-Strobe Testbench Generate - g_spwc_ds_testbench : if (g_SPWC_TESTBENCH_MODE = '1') generate - - s_spw_logical_data_in <= spw_lvds_p_data_in_i; - s_spw_logical_strobe_in <= spw_lvds_p_strobe_in_i; - spw_lvds_p_data_out_o <= s_spw_logical_data_out; - spw_lvds_p_strobe_out_o <= s_spw_logical_strobe_out; - spw_lvds_n_data_out_o <= '0'; - spw_lvds_n_strobe_out_o <= '0'; - - end generate g_spwc_ds_testbench; - - -- SpaceWire Data-Strobe ALTIOBUF Generate - g_spwc_ds_altiobuff : if (g_SPWC_TESTBENCH_MODE = '0') generate - - -- SpaceWire Data-Strobe Rx Diferential Inputs ALTIOBUF Instantiation - spwc_spw_rx_altiobuf_inst : entity work.spwc_spw_rx_altiobuf - port map( - datain(0) => spw_lvds_p_data_in_i, - datain(1) => spw_lvds_p_strobe_in_i, - datain_b(0) => spw_lvds_n_data_in_i, - datain_b(1) => spw_lvds_n_strobe_in_i, - dataout(0) => s_spw_logical_data_in, - dataout(1) => s_spw_logical_strobe_in - ); - - -- SpaceWire Data-Strobe Tx Diferential Outputs ALTIOBUF Instantiation - spwc_spw_tx_altiobuf_inst : entity work.spwc_spw_tx_altiobuf - port map( - datain(0) => s_spw_logical_data_out, - datain(1) => s_spw_logical_strobe_out, - dataout(0) => spw_lvds_p_data_out_o, - dataout(1) => spw_lvds_p_strobe_out_o, - dataout_b(0) => spw_lvds_n_data_out_o, - dataout_b(1) => spw_lvds_n_strobe_out_o - ); - - end generate g_spwc_ds_altiobuff; - - -- SpaceWire LEDs Controller Instantiation - spwc_leds_controller_ent_inst : entity work.spwc_leds_controller_ent - port map( - clk_i => a_spw_clock, - rst_i => a_reset, - leds_channel_status_i.link_status_running => s_spw_codec_link_status_spw.running, - leds_channel_status_i.data_rx_command_rxread => s_spw_codec_data_rx_command_spw.rxread, - leds_channel_status_i.data_tx_command_txwrite => s_spw_codec_data_tx_command_spw.txwrite, - leds_control_o => s_spw_leds_control - ); - - -- SpaceWire LEDs Outputs ALTIOBUF Instantiation - spwc_leds_out_altiobuf_inst : entity work.spwc_leds_out_altiobuf - port map( - datain(1) => s_spw_leds_control.red_status_led, - datain(0) => s_spw_leds_control.green_status_led, - dataout(1) => spw_red_status_led_o, - dataout(0) => spw_green_status_led_o - ); - - -- Signals Assignments -- - - -- Spacewire Data-Strobe Input Signals Assignments - s_spw_codec_ds_encoding_rx.spw_di <= ('0') when (a_reset = '1') - else (s_spw_logical_data_in) when (spw_rx_enable_i = '1') - else ('0'); - s_spw_codec_ds_encoding_rx.spw_si <= ('0') when (a_reset = '1') - else (s_spw_logical_strobe_in) when (spw_rx_enable_i = '1') - else ('0'); - - -- Spacewire Data-Strobe Output Signals Assignments - s_spw_logical_data_out <= ('0') when (a_reset = '1') - else (s_spw_codec_ds_encoding_tx.spw_do) when (spw_tx_enable_i = '1') - else ('0'); - s_spw_logical_strobe_out <= ('0') when (a_reset = '1') - else (s_spw_codec_ds_encoding_tx.spw_so) when (spw_tx_enable_i = '1') - else ('0'); + -- Entities Instantiation -- + + -- SpaceWire Codec Clock Domain Synchronization Instantiation + spwc_clk_synchronization_top_inst : entity work.spwc_clk_synchronization_top + port map( + clk_avs_i => a_avs_clock, + clk_spw_i => a_spw_clock, + rst_i => a_reset, + spw_codec_link_command_avs_i.autostart => spw_link_command_autostart_i, + spw_codec_link_command_avs_i.linkstart => spw_link_command_linkstart_i, + spw_codec_link_command_avs_i.linkdis => spw_link_command_linkdis_i, + spw_codec_link_command_avs_i.txdivcnt => spw_link_command_txdivcnt_i, + spw_codec_timecode_tx_avs_i.tick_in => spw_timecode_tx_tick_in_i, + spw_codec_timecode_tx_avs_i.ctrl_in => spw_timecode_tx_ctrl_in_i, + spw_codec_timecode_tx_avs_i.time_in => spw_timecode_tx_time_in_i, + spw_codec_data_rx_command_avs_i.rxread => spw_data_rx_command_rxread_i, + spw_codec_data_tx_command_avs_i.txwrite => spw_data_tx_command_txwrite_i, + spw_codec_data_tx_command_avs_i.txflag => spw_data_tx_command_txflag_i, + spw_codec_data_tx_command_avs_i.txdata => spw_data_tx_command_txdata_i, + spw_errinj_ctrl_control_avs_i.start_errinj => spw_errinj_ctrl_start_errinj_i, + spw_errinj_ctrl_control_avs_i.reset_errinj => spw_errinj_ctrl_reset_errinj_i, + spw_errinj_ctrl_control_avs_i.errinj_code => spw_errinj_ctrl_errinj_code_i, + spw_codec_link_status_spw_i => s_spw_codec_link_status_spw, + spw_codec_link_error_spw_i => s_spw_codec_link_error_spw, + spw_codec_timecode_rx_spw_i => s_spw_codec_timecode_rx_spw, + spw_codec_data_rx_status_spw_i => s_spw_codec_data_rx_status_spw, + spw_codec_data_tx_status_spw_i => s_spw_codec_data_tx_status_spw, + spw_errinj_ctrl_status_spw_i => s_spw_errinj_controller_status, + spw_codec_link_status_avs_o.started => spw_link_status_started_o, + spw_codec_link_status_avs_o.connecting => spw_link_status_connecting_o, + spw_codec_link_status_avs_o.running => spw_link_status_running_o, + spw_codec_link_error_avs_o.errdisc => spw_link_error_errdisc_o, + spw_codec_link_error_avs_o.errpar => spw_link_error_errpar_o, + spw_codec_link_error_avs_o.erresc => spw_link_error_erresc_o, + spw_codec_link_error_avs_o.errcred => spw_link_error_errcred_o, + spw_codec_timecode_rx_avs_o.tick_out => spw_timecode_rx_tick_out_o, + spw_codec_timecode_rx_avs_o.ctrl_out => spw_timecode_rx_ctrl_out_o, + spw_codec_timecode_rx_avs_o.time_out => spw_timecode_rx_time_out_o, + spw_codec_data_rx_status_avs_o.rxvalid => spw_data_rx_status_rxvalid_o, + spw_codec_data_rx_status_avs_o.rxhalff => spw_data_rx_status_rxhalff_o, + spw_codec_data_rx_status_avs_o.rxflag => spw_data_rx_status_rxflag_o, + spw_codec_data_rx_status_avs_o.rxdata => spw_data_rx_status_rxdata_o, + spw_codec_data_tx_status_avs_o.txrdy => spw_data_tx_status_txrdy_o, + spw_codec_data_tx_status_avs_o.txhalff => spw_data_tx_status_txhalff_o, + spw_errinj_ctrl_status_avs_o.errinj_busy => spw_errinj_ctrl_errinj_busy_o, + spw_errinj_ctrl_status_avs_o.errinj_ready => spw_errinj_ctrl_errinj_ready_o, + spw_codec_link_command_spw_o => s_spw_codec_link_command_spw, + spw_codec_timecode_tx_spw_o => s_spw_codec_timecode_tx_spw, + spw_codec_data_rx_command_spw_o => s_spw_codec_data_rx_command_spw, + spw_codec_data_tx_command_spw_o => s_spw_codec_data_tx_command_spw, + spw_errinj_ctrl_control_spw_o => s_spw_errinj_controller_control + ); + + -- SpaceWire Error Injection Controller Instantiation + spwc_errinj_controller_ent_inst : entity work.spwc_errinj_controller_ent + port map( + clk_i => a_spw_clock, + rst_i => a_reset, + errinj_controller_control_i => s_spw_errinj_controller_control, + spw_codec_link_status_i => s_spw_codec_link_status_spw, + spw_codec_err_inj_status_i => s_spw_codec_err_inj_status_spw, + errinj_controller_status_o => s_spw_errinj_controller_status, + spw_codec_err_inj_command_o => s_spw_codec_err_inj_command_spw + ); + + -- SpaceWire Codec Instantiation + spwc_codec_ent_inst : entity work.spwc_codec_ent + port map( + clk_spw_i => a_spw_clock, + rst_i => a_reset, + spw_codec_link_command_i => s_spw_codec_link_command_spw, + spw_codec_ds_encoding_rx_i => s_spw_codec_ds_encoding_rx, + spw_codec_timecode_tx_i => s_spw_codec_timecode_tx_spw, + spw_codec_data_rx_command_i => s_spw_codec_data_rx_command_spw, + spw_codec_data_tx_command_i => s_spw_codec_data_tx_command_spw, + spw_codec_err_inj_command_i => s_spw_codec_err_inj_command_spw, + spw_codec_link_status_o => s_spw_codec_link_status_spw, + spw_codec_ds_encoding_tx_o => s_spw_codec_ds_encoding_tx, + spw_codec_link_error_o => s_spw_codec_link_error_spw, + spw_codec_timecode_rx_o => s_spw_codec_timecode_rx_spw, + spw_codec_data_rx_status_o => s_spw_codec_data_rx_status_spw, + spw_codec_data_tx_status_o => s_spw_codec_data_tx_status_spw, + spw_codec_err_inj_status_o => s_spw_codec_err_inj_status_spw + ); + + -- SpaceWire Data-Strobe Testbench Generate + g_spwc_ds_testbench : if (g_SPWC_TESTBENCH_MODE = '1') generate + + s_spw_logical_data_in <= spw_lvds_p_data_in_i; + s_spw_logical_strobe_in <= spw_lvds_p_strobe_in_i; + spw_lvds_p_data_out_o <= s_spw_logical_data_out; + spw_lvds_p_strobe_out_o <= s_spw_logical_strobe_out; + spw_lvds_n_data_out_o <= '0'; + spw_lvds_n_strobe_out_o <= '0'; + + end generate g_spwc_ds_testbench; + + -- SpaceWire Data-Strobe ALTIOBUF Generate + g_spwc_ds_altiobuff : if (g_SPWC_TESTBENCH_MODE = '0') generate + + -- SpaceWire Data-Strobe Rx Diferential Inputs ALTIOBUF Instantiation + spwc_spw_rx_altiobuf_inst : entity work.spwc_spw_rx_altiobuf + port map( + datain(0) => spw_lvds_p_data_in_i, + datain(1) => spw_lvds_p_strobe_in_i, + datain_b(0) => spw_lvds_n_data_in_i, + datain_b(1) => spw_lvds_n_strobe_in_i, + dataout(0) => s_spw_logical_data_in, + dataout(1) => s_spw_logical_strobe_in + ); + + -- SpaceWire Data-Strobe Tx Diferential Outputs ALTIOBUF Instantiation + spwc_spw_tx_altiobuf_inst : entity work.spwc_spw_tx_altiobuf + port map( + datain(0) => s_spw_logical_data_out, + datain(1) => s_spw_logical_strobe_out, + dataout(0) => spw_lvds_p_data_out_o, + dataout(1) => spw_lvds_p_strobe_out_o, + dataout_b(0) => spw_lvds_n_data_out_o, + dataout_b(1) => spw_lvds_n_strobe_out_o + ); + + end generate g_spwc_ds_altiobuff; + + -- SpaceWire LEDs Controller Instantiation + spwc_leds_controller_ent_inst : entity work.spwc_leds_controller_ent + port map( + clk_i => a_spw_clock, + rst_i => a_reset, + leds_channel_status_i.link_status_running => s_spw_codec_link_status_spw.running, + leds_channel_status_i.data_rx_command_rxread => s_spw_codec_data_rx_command_spw.rxread, + leds_channel_status_i.data_tx_command_txwrite => s_spw_codec_data_tx_command_spw.txwrite, + leds_control_o => s_spw_leds_control + ); + + -- SpaceWire LEDs Outputs ALTIOBUF Instantiation + spwc_leds_out_altiobuf_inst : entity work.spwc_leds_out_altiobuf + port map( + datain(1) => s_spw_leds_control.red_status_led, + datain(0) => s_spw_leds_control.green_status_led, + dataout(1) => spw_red_status_led_o, + dataout(0) => spw_green_status_led_o + ); + + -- Signals Assignments -- + + -- Spacewire Data-Strobe Input Signals Assignments + s_spw_codec_ds_encoding_rx.spw_di <= ('0') when (a_reset = '1') + else (s_spw_logical_data_in) when ((spw_rx_enable_i = '1') and (spw_link_command_enable_i = '1')) + else ('0'); + s_spw_codec_ds_encoding_rx.spw_si <= ('0') when (a_reset = '1') + else (s_spw_logical_strobe_in) when ((spw_rx_enable_i = '1') and (spw_link_command_enable_i = '1')) + else ('0'); + + -- Spacewire Data-Strobe Output Signals Assignments + s_spw_logical_data_out <= ('0') when (a_reset = '1') + else (s_spw_codec_ds_encoding_tx.spw_do) when ((spw_tx_enable_i = '1') and (spw_link_command_enable_i = '1')) + else ('0'); + s_spw_logical_strobe_out <= ('0') when (a_reset = '1') + else (s_spw_codec_ds_encoding_tx.spw_so) when ((spw_tx_enable_i = '1') and (spw_link_command_enable_i = '1')) + else ('0'); end architecture rtl; -- of spwc_spacewire_channel_top diff --git a/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel_hw.tcl b/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel_hw.tcl index 783f776c9..302b68edb 100644 --- a/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel_hw.tcl +++ b/G3U_HW_V02_2GB/Hardware_Project/Avalon/SpaceWire_Channel_hw.tcl @@ -4,7 +4,7 @@ # -# SpaceWire_Channel "SpaceWire_Channel" v1.4 +# SpaceWire_Channel "SpaceWire_Channel" v1.5 # rfranca 2020.06.30.17:45:51 # # @@ -20,7 +20,7 @@ package require -exact qsys 16.1 # set_module_property DESCRIPTION "" set_module_property NAME SpaceWire_Channel -set_module_property VERSION 1.4 +set_module_property VERSION 1.5 set_module_property INTERNAL false set_module_property OPAQUE_ADDRESS_MAP true set_module_property AUTHOR rfranca @@ -287,6 +287,7 @@ set_interface_property conduit_end_spacewire_channel PORT_NAME_MAP "" set_interface_property conduit_end_spacewire_channel CMSIS_SVD_VARIABLES "" set_interface_property conduit_end_spacewire_channel SVD_ADDRESS_GROUP "" +add_interface_port conduit_end_spacewire_channel spw_link_command_enable_i spw_link_command_enable_signal Input 1 add_interface_port conduit_end_spacewire_channel spw_link_command_autostart_i spw_link_command_autostart_signal Input 1 add_interface_port conduit_end_spacewire_channel spw_link_command_linkstart_i spw_link_command_linkstart_signal Input 1 add_interface_port conduit_end_spacewire_channel spw_link_command_linkdis_i spw_link_command_linkdis_signal Input 1 diff --git a/G3U_HW_V02_2GB/Qsys_Project/software/Simucam_R0_UART/simucam_main.c b/G3U_HW_V02_2GB/Qsys_Project/software/Simucam_R0_UART/simucam_main.c index b763e0c5f..6867c77ce 100644 --- a/G3U_HW_V02_2GB/Qsys_Project/software/Simucam_R0_UART/simucam_main.c +++ b/G3U_HW_V02_2GB/Qsys_Project/software/Simucam_R0_UART/simucam_main.c @@ -555,7 +555,7 @@ int main(void) fprintf(fp, "Failure to initialize SimuCam Critical HW!\n"); fprintf(fp, "Initialization attempt %lu, ", uliRstcGetResetCounter()); #endif - /* Need to reset 2 times (3 tries) before locking the SimuCam */ + /* Need to reset 2 times (3 tries) before halting the SimuCam */ if (3 > uliRstcGetResetCounter()) { /* There are more initialization tries to make */ #if DEBUG_ON @@ -566,7 +566,7 @@ int main(void) /* No more tries, lock the SimuCam */ #if DEBUG_ON - fprintf(fp, "SimuCam will be locked now!\n"); + fprintf(fp, "SimuCam will be halted now!\n"); #endif vFailTestCriticasParts(); }