r_last and r_valid for 2 cycles

[mslijepc]

We get the r_last and r_valid for 2 cycles

I guess that it can be fixed, instead of

SystemC-Components/src/bus_interfaces/axi/pin/ace_target.h

Line 420 in ed4a529

wait(this->r_ready.posedge_event() | clk_delayed);

putting it in else

if(this->r_ready.read()) { ... 
} else {
            wait(this->r_ready.posedge_event() | clk_delayed); 
}

Because in any case we wait for one cycle afterwards

SystemC-Components/src/bus_interfaces/axi/pin/ace_target.h

Line 428 in ed4a529

wait(clk_i.posedge_event());

[eyck]

Your proposed fix will not work. ready will be set and cleared by the rising edge of the initiator. The line you prose is being executed in the delta-cycle right after rising edge of the clock- becaus of this wait. But this is the deltacycle where the ready is cleared by the initiator (or maybe not).
To me the the waveform looks like a back-to-back response of the target. Can you try to set the ready to 0 after the first response?

[mslijepc]

No, it's not back to back. This is the full waveform

For every response, we wait for have 2 cycles ready and last

You are right.. Would then maybe this be correct?

else {
                wait(clk_i.posedge_event());
            }