-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathgpio.patch
513 lines (512 loc) · 17.4 KB
/
gpio.patch
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
diff -Naur a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi 2020-02-04 13:18:54.659867000 +0530
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi 2020-02-04 13:49:34.019834274 +0530
@@ -154,6 +154,21 @@
clocks = <&hfclk>, <&rtcclk>;
#clock-cells = <1>;
};
+
+ gpio0: gpio@10060000 {
+ compatible = "sifive,fu540-c000-gpio", "sifive,gpio0";
+ reg = <0x0 0x10060000 0x0 0x1000>;
+ reg-names = "control";
+ interrupt-parent = <&plic0>;
+ interrupts = <7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22>;
+ ngpios = <16>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
uart0: serial@10010000 {
compatible = "sifive,fu540-c000-uart", "sifive,uart0";
reg = <0x0 0x10010000 0x0 0x1000>;
diff -Naur a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
--- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts 2020-02-04 13:18:54.659867000 +0530
+++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts 2020-02-04 13:51:04.400198420 +0530
@@ -94,3 +94,7 @@
&pwm1 {
status = "okay";
};
+
+&gpio0 {
+ status = "okay";
+};
diff -Naur a/drivers/gpio/gpio-sifive.c b/drivers/gpio/gpio-sifive.c
--- a/drivers/gpio/gpio-sifive.c 1970-01-01 05:30:00.000000000 +0530
+++ b/drivers/gpio/gpio-sifive.c 2020-02-04 18:00:14.220972994 +0530
@@ -0,0 +1,444 @@
+#include <linux/bitops.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/gpio/driver.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/raid/pq.h>
+
+#define GPIO_INPUT_VAL 0x00
+#define GPIO_INPUT_EN 0x04
+#define GPIO_OUTPUT_EN 0x08
+#define GPIO_OUTPUT_VAL 0x0C
+#define GPIO_PULLUP_EN 0x10
+#define GPIO_PIN_DS 0x14
+#define GPIO_RISE_IE 0x18
+#define GPIO_RISE_IP 0x1C
+#define GPIO_FALL_IE 0x20
+#define GPIO_FALL_IP 0x24
+#define GPIO_HIGH_IE 0x28
+#define GPIO_HIGH_IP 0x2C
+#define GPIO_LOW_IE 0x30
+#define GPIO_LOW_IP 0x34
+#define GPIO_OUTPUT_XOR 0x40
+
+#define GPIO_MAX_CNT 32
+#define GPIO_ENABLE_BITS 0x83FF
+
+//#define GPIO_SIFIVE_DEBUG
+#ifdef GPIO_SIFIVE_DEBUG
+ #define gpio_sifive_debug(...) printk("GPIO: " __VA_ARGS__)
+#else
+ #define gpio_sifive_debug(...)
+#endif
+
+struct sifive_gpio {
+ raw_spinlock_t lock;
+ void __iomem *base;
+ struct gpio_chip gc;
+ unsigned int irq_enable;
+ unsigned int irq_type[GPIO_MAX_CNT];
+ unsigned int irq_parent[GPIO_MAX_CNT];
+ struct sifive_gpio *self_ptr[GPIO_MAX_CNT];
+};
+
+
+static void gpio_sifive_debug_reg(struct sifive_gpio *chip)
+{
+#ifdef GPIO_SIFIVE_DEBUG
+ u32 value;
+ int reg;
+
+ if (!chip->base) return;
+ gpio_sifive_debug("registers values ---------------------------\n");
+ for (reg=GPIO_INPUT_VAL; reg<=GPIO_OUTPUT_XOR; reg+=4) {
+ value = readl(chip->base + reg);
+ gpio_sifive_debug("reg=[%02X], value=[%08X]\n", reg, value);
+ }
+ gpio_sifive_debug("irq_enable=[%08X]\n", chip->irq_enable);
+ gpio_sifive_debug("irq_type=%d\n", chip->irq_type[0]);
+ gpio_sifive_debug("irq_parent=%d\n", chip->irq_parent[0]);
+ gpio_sifive_debug("\n");
+#endif
+}
+
+static void gpio_sifive_assign_bit(void __iomem *ptr, int offset, int value)
+{
+ // It's frustrating that we are not allowed to use the device atomics
+ // which are GUARANTEED to be supported by this device on RISC-V
+ u32 bit = BIT(offset);
+ u32 old = readl(ptr);
+
+ bit = (value) ? old | bit : old & ~bit;
+ writel(bit, ptr);
+}
+
+static int gpio_sifive_direction_input(struct gpio_chip *gc, unsigned offset)
+{
+ struct sifive_gpio *chip = gpiochip_get_data(gc);
+ unsigned long flags;
+
+ if (offset >= gc->ngpio)
+ return -EINVAL;
+
+ raw_spin_lock_irqsave(&chip->lock, flags);
+ gpio_sifive_assign_bit(chip->base + GPIO_OUTPUT_EN, offset, 0);
+ gpio_sifive_assign_bit(chip->base + GPIO_INPUT_EN, offset, 1);
+ raw_spin_unlock_irqrestore(&chip->lock, flags);
+
+ return 0;
+}
+
+static int gpio_sifive_direction_output(struct gpio_chip *gc, unsigned offset
+ , int value)
+{
+ struct sifive_gpio *chip = gpiochip_get_data(gc);
+ unsigned long flags;
+
+ if (offset >= gc->ngpio)
+ return -EINVAL;
+
+ raw_spin_lock_irqsave(&chip->lock, flags);
+ gpio_sifive_assign_bit(chip->base + GPIO_INPUT_EN, offset, 0);
+ gpio_sifive_assign_bit(chip->base + GPIO_OUTPUT_EN, offset, 1);
+ gpio_sifive_assign_bit(chip->base + GPIO_OUTPUT_VAL, offset, value);
+ raw_spin_unlock_irqrestore(&chip->lock, flags);
+
+ return 0;
+}
+
+static int gpio_sifive_get_direction(struct gpio_chip *gc, unsigned offset)
+{
+ struct sifive_gpio *chip = gpiochip_get_data(gc);
+ int value;
+
+ if (offset >= gc->ngpio)
+ return -EINVAL;
+
+ value = readl(chip->base + GPIO_OUTPUT_EN) & BIT(offset);
+ return !value;
+}
+
+static int gpio_sifive_get_value(struct gpio_chip *gc, unsigned offset)
+{
+ struct sifive_gpio *chip = gpiochip_get_data(gc);
+ int index, value;
+
+ if (offset >= gc->ngpio)
+ return -EINVAL;
+
+ index = gpio_sifive_get_direction(gc, offset) ?
+ GPIO_INPUT_VAL : GPIO_OUTPUT_VAL;
+ value = readl(chip->base + index) & BIT(offset);
+ return value;
+}
+
+static void gpio_sifive_set_value(struct gpio_chip *gc, unsigned
+offset, int value)
+{
+ struct sifive_gpio *chip = gpiochip_get_data(gc);
+ unsigned long flags;
+ int index;
+
+ if (offset >= gc->ngpio)
+ return;
+
+ index = gpio_sifive_get_direction(gc, offset) ?
+ GPIO_INPUT_VAL : GPIO_OUTPUT_VAL;
+ raw_spin_lock_irqsave(&chip->lock, flags);
+ gpio_sifive_assign_bit(chip->base + index, offset, value);
+ raw_spin_unlock_irqrestore(&chip->lock, flags);
+}
+
+static void gpio_sifive_set_default(struct sifive_gpio *chip, u32 bits)
+{
+ if (bits == GPIO_ENABLE_BITS) {
+ //Input Enable/Disable
+ writel(bits, chip->base + GPIO_INPUT_EN);
+ return;
+ }
+ //Interrupts Enable/Disable
+ writel(bits, chip->base + GPIO_RISE_IE);
+ writel(bits, chip->base + GPIO_FALL_IE);
+ writel(bits, chip->base + GPIO_HIGH_IE);
+ writel(bits, chip->base + GPIO_LOW_IE);
+
+ writel(bits, chip->base + GPIO_RISE_IP);
+ writel(bits, chip->base + GPIO_FALL_IP);
+ writel(bits, chip->base + GPIO_HIGH_IP);
+ writel(bits, chip->base + GPIO_LOW_IP);
+
+ chip->irq_enable = bits;
+}
+
+static void gpio_sifive_set_ie(struct sifive_gpio *chip, int offset)
+{
+ unsigned long flags;
+ unsigned irq_type;
+
+ raw_spin_lock_irqsave(&chip->lock, flags);
+ irq_type = (chip->irq_enable & BIT(offset)) ?
+chip->irq_type[offset] : 0;
+ gpio_sifive_assign_bit(chip->base + GPIO_RISE_IE, offset,
+irq_type & IRQ_TYPE_EDGE_RISING);
+ gpio_sifive_assign_bit(chip->base + GPIO_FALL_IE, offset,
+irq_type & IRQ_TYPE_EDGE_FALLING);
+ gpio_sifive_assign_bit(chip->base + GPIO_HIGH_IE, offset,
+irq_type & IRQ_TYPE_LEVEL_HIGH);
+ gpio_sifive_assign_bit(chip->base + GPIO_LOW_IE, offset,
+irq_type & IRQ_TYPE_LEVEL_LOW);
+ raw_spin_unlock_irqrestore(&chip->lock, flags);
+}
+
+static int gpio_sifive_irq_set_type(struct irq_data *d, unsigned irq_type)
+{
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct sifive_gpio *chip = gpiochip_get_data(gc);
+ int offset = irqd_to_hwirq(d);
+
+ if (offset < 0 || offset >= gc->ngpio)
+ return -EINVAL;
+
+ chip->irq_type[offset] = irq_type;
+ gpio_sifive_set_ie(chip, offset);
+
+ return 0;
+}
+
+/* chained_irq_{enter,exit} already mask the parent */
+static void gpio_sifive_irq_mask(struct irq_data *d) { }
+static void gpio_sifive_irq_unmask(struct irq_data *d) { }
+
+static void gpio_sifive_irq_enable(struct irq_data *d)
+{
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct sifive_gpio *chip = gpiochip_get_data(gc);
+ int offset = irqd_to_hwirq(d) % GPIO_MAX_CNT; // must not fail
+ u32 bit = BIT(offset);
+
+ /* Switch to input */
+ gpio_sifive_direction_input(gc, offset);
+
+ /* Clear any sticky pending interrupts */
+ writel(bit, chip->base + GPIO_RISE_IP);
+ writel(bit, chip->base + GPIO_FALL_IP);
+ writel(bit, chip->base + GPIO_HIGH_IP);
+ writel(bit, chip->base + GPIO_LOW_IP);
+
+ /* Enable interrupts */
+ chip->irq_enable |= bit;
+ gpio_sifive_set_ie(chip, offset);
+}
+
+static void gpio_sifive_irq_disable(struct irq_data *d)
+{
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct sifive_gpio *chip = gpiochip_get_data(gc);
+ int offset = irqd_to_hwirq(d) % GPIO_MAX_CNT; // must not fail
+ u32 bit = BIT(offset);
+
+ /* Disable interrupts */
+ chip->irq_enable &= ~bit;
+ gpio_sifive_set_ie(chip, offset);
+}
+
+static struct irq_chip gpio_sifive_irqchip = {
+ .name = "sifive-gpio",
+ .irq_set_type = gpio_sifive_irq_set_type,
+ .irq_mask = gpio_sifive_irq_mask,
+ .irq_unmask = gpio_sifive_irq_unmask,
+ .irq_enable = gpio_sifive_irq_enable,
+ .irq_disable = gpio_sifive_irq_disable,
+};
+
+static void gpio_sifive_irq_handler(struct irq_desc *desc)
+{
+ struct irq_chip *irqchip = irq_desc_get_chip(desc);
+ struct sifive_gpio **self_ptr = irq_desc_get_handler_data(desc);
+ struct sifive_gpio *chip = *self_ptr;
+ int offset = self_ptr - &chip->self_ptr[0];
+ //int offset = desc->irq_data.irq - chip->irq_parent[0];
+ u32 bit = BIT(offset);
+
+ chained_irq_enter(irqchip, desc);
+
+ /* Re-arm the edge irq_types so don't miss the next one */
+ writel(bit, chip->base + GPIO_RISE_IP);
+ writel(bit, chip->base + GPIO_FALL_IP);
+
+ generic_handle_irq(irq_find_mapping(chip->gc.irq.domain, offset));
+
+ /* Re-arm the level irq_types after handling to prevent
+spurious refire */
+ writel(bit, chip->base + GPIO_HIGH_IP);
+ writel(bit, chip->base + GPIO_LOW_IP);
+
+ chained_irq_exit(irqchip, desc);
+
+ gpio_sifive_debug("irq handler: offset=%d\n", offset);
+}
+
+#ifdef GPIO_SIFIVE_DEBUG
+static void gpio_sifive_set_irq_enable(struct sifive_gpio *chip,
+unsigned offset)
+{
+ u32 bit = BIT(offset);
+
+ /* Switch to input */
+ gpio_sifive_direction_input(&chip->gc, offset);
+
+ /* Clear any sticky pending interrupts */
+ writel(bit, chip->base + GPIO_RISE_IP);
+ writel(bit, chip->base + GPIO_FALL_IP);
+ writel(bit, chip->base + GPIO_HIGH_IP);
+ writel(bit, chip->base + GPIO_LOW_IP);
+
+ /* Enable interrupts */
+ chip->irq_enable |= bit;
+ gpio_sifive_set_ie(chip, offset);
+}
+
+static void gpio_sifive_set_irq_disable(struct sifive_gpio *chip,
+unsigned offset)
+{
+ u32 bit = BIT(offset);
+ chip->irq_enable &= ~bit;
+ gpio_sifive_set_ie(chip, offset);
+}
+#endif
+
+static int gpio_sifive_chip_setup(struct platform_device *pdev
+ , struct sifive_gpio *chip, int ngpio)
+{
+ struct device *dev = &pdev->dev;
+ int gpio, irq, ret;
+
+ raw_spin_lock_init(&chip->lock);
+ chip->gc.direction_input = gpio_sifive_direction_input;
+ chip->gc.direction_output = gpio_sifive_direction_output;
+ chip->gc.get_direction = gpio_sifive_get_direction;
+ chip->gc.get = gpio_sifive_get_value;
+ chip->gc.set = gpio_sifive_set_value;
+ chip->gc.base = -1;
+ chip->gc.ngpio = ngpio;
+ chip->gc.label = dev_name(dev);
+ chip->gc.parent = dev;
+ chip->gc.owner = THIS_MODULE;
+
+ ret = gpiochip_add_data(&chip->gc, chip);
+ if (ret)
+ return ret;
+
+ /* Disable all GPIO interrupts before enabling parent interrupts */
+ gpio_sifive_set_default(chip, 0);
+
+ ret = gpiochip_irqchip_add(&chip->gc, &gpio_sifive_irqchip, 0
+ , handle_simple_irq, IRQ_TYPE_NONE);
+ if (ret) {
+ dev_err(dev, "GPIO: could not add irqchip\n");
+ gpiochip_remove(&chip->gc);
+ return ret;
+ }
+
+ chip->gc.irq.num_parents = ngpio;
+ chip->gc.irq.parents = &chip->irq_parent[0];
+ chip->gc.irq.map = &chip->irq_parent[0];
+
+ for (gpio = 0; gpio < ngpio; ++gpio) {
+ irq = platform_get_irq(pdev, gpio);
+ if (irq < 0) {
+ dev_err(dev, "GPIO: invalid IRQ\n");
+ gpiochip_remove(&chip->gc);
+ return -ENODEV;
+ }
+ chip->self_ptr[gpio] = chip;
+ chip->irq_parent[gpio] = irq;
+ chip->irq_type[gpio] = IRQ_TYPE_LEVEL_HIGH;
+ }
+ for (gpio = 0; gpio < ngpio; ++gpio) {
+ irq = chip->irq_parent[gpio];
+ irq_set_chained_handler_and_data(irq, gpio_sifive_irq_handler
+ , &chip->self_ptr[gpio]);
+ irq_set_parent(irq_find_mapping(chip->gc.irq.domain,
+gpio), irq);
+ }
+
+ //Enable GPIO Input for default
+ gpio_sifive_set_default(chip, GPIO_ENABLE_BITS);
+ return 0;
+}
+
+static int gpio_sifive_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *node = pdev->dev.of_node;
+ struct sifive_gpio *chip;
+ struct resource *res;
+ int ngpio;
+
+ chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
+ if (!chip) {
+ dev_err(dev, "out of memory\n");
+ return -ENOMEM;
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ chip->base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(chip->base)) {
+ dev_err(dev, "failed to allocate device memory\n");
+ return PTR_ERR(chip->base);
+ }
+ gpio_sifive_debug_reg(chip);
+
+ if(of_property_read_u32(node, "ngpios", &ngpio))
+ ngpio = of_irq_count(node);
+
+ if (ngpio >= GPIO_MAX_CNT) {
+ dev_err(dev, "too many ngpios.\n");
+ return -EINVAL;
+ }
+
+ if (gpio_sifive_chip_setup(pdev, chip, ngpio) < 0) {
+ dev_err(dev, "failed to gpio sifive setup.\n");
+ return -EINVAL;
+ }
+
+ platform_set_drvdata(pdev, chip);
+ dev_info(dev, "GPIO SiFive driver registered %d GPIOs\n", ngpio);
+
+#ifdef GPIO_SIFIVE_DEBUG
+ gpio_sifive_set_irq_enable(chip, 7); ///GPIO7 interrupt
+enabled for test
+ gpio_sifive_set_irq_disable(chip, 9); ///GPIO9 interrupt
+disabled for test
+#endif
+ gpio_sifive_debug_reg(chip);
+ return 0;
+}
+
+static const struct of_device_id gpio_sifive_match[] = {
+ {
+ .compatible = "sifive,gpio0",
+ },
+ { },
+};
+MODULE_DEVICE_TABLE(of, gpio_sifive_match);
+
+static struct platform_driver gpio_sifive_driver = {
+ .probe = gpio_sifive_probe,
+ .driver = {
+ .name = "gpio-sifive",
+ .of_match_table = of_match_ptr(gpio_sifive_match),
+ },
+};
+module_platform_driver(gpio_sifive_driver);
+
+MODULE_DESCRIPTION("SiFive GPIO driver");
+MODULE_LICENSE("GPL v2");
diff -Naur a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
--- a/drivers/gpio/Kconfig 2020-02-04 13:18:55.479871000 +0530
+++ b/drivers/gpio/Kconfig 2020-02-04 13:52:36.456574262 +0530
@@ -666,6 +666,14 @@
Note: This driver doesn't registers itself automatically, as it
needs to be provided with platform specific configuration.
(See eg. CONFIG_PCENGINES_APU2.)
+
+config GPIO_SIFIVE
+ tristate "SiFive GPIO support"
+ depends on OF_GPIO
+ select GPIOLIB_IRQCHIP
+ help
+ Say yes here to support the GPIO device on SiFive SoCs.
+
endmenu
menu "Port-mapped I/O GPIO drivers"
diff -Naur a/drivers/gpio/Makefile b/drivers/gpio/Makefile
--- a/drivers/gpio/Makefile 2020-02-04 13:18:55.479871000 +0530
+++ b/drivers/gpio/Makefile 2020-02-04 13:53:20.696756413 +0530
@@ -121,6 +121,7 @@
obj-$(CONFIG_GPIO_SAMA5D2_PIOBU) += gpio-sama5d2-piobu.o
obj-$(CONFIG_GPIO_SCH311X) += gpio-sch311x.o
obj-$(CONFIG_GPIO_SCH) += gpio-sch.o
+obj-$(CONFIG_GPIO_SIFIVE) += gpio-sifive.o
obj-$(CONFIG_GPIO_SIOX) += gpio-siox.o
obj-$(CONFIG_GPIO_SODAVILLE) += gpio-sodaville.o
obj-$(CONFIG_GPIO_SPEAR_SPICS) += gpio-spear-spics.o