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Bender.yml
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# Copyright 2025 ETH Zurich and University of Bologna.
# Solderpad Hardware License, Version 0.51, see LICENSE for details.
# SPDX-License-Identifier: SHL-0.51
package:
name: picobello
authors:
- "Tim Fischer <fischeti@iis.ee.ethz.ch>"
dependencies:
register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: "0.4.5" }
axi: { git: "https://github.com/pulp-platform/axi.git", version: "0.39.6" }
common_cells: { git: "https://github.com/pulp-platform/common_cells.git", rev: "picobello" }
cheshire: { git: "https://github.com/pulp-platform/cheshire.git", rev: "picobello" }
snitch_cluster: { git: "https://github.com/pulp-platform/snitch_cluster.git", rev: "d20adf56986cbd7aaaf406602642cd6bdf73701c" }
floo_noc: { git: "https://github.com/pulp-platform/FlooNoC.git", rev: "develop" }
obi: { git: "https://github.com/pulp-platform/obi.git", rev: "8ceb36dd8b1a2179d56cc7ddb0c31d6b11257a28" }
redmule: { git: "https://github.com/pulp-platform/redmule.git", rev: "picobello" }
hci: { git: "https://github.com/pulp-platform/hci.git", rev: "06fcba671e060f2e1b03b7ebe2d3e719f1557099" }
datamover: { git: "https://github.com/FrancescoConti/datamover.git", rev: "fb7d09c201ab52de23b11adf12b36d8e75c4c0e6" } # branch: transpose
apb: { git: "https://github.com/pulp-platform/apb.git", version: "0.2.4" }
apb_fll_if: { git: "https://github.com/pulp-platform/apb_fll_if.git", rev: "structs" }
axi_obi: { path: "hw/axi_obi" }
picobello-pd: { path: "./pd" }
fhg_spu_cluster: { path: "./.deps/fhg_spu_cluster" }
workspace:
package_links:
.deps/snitch_cluster: snitch_cluster
sources:
# Source files grouped in levels. Files in level 0 have no dependencies on files in this
# package. Files in level 1 only depend on files in level 0, files in level 2 on files in
# levels 1 and 0, etc. Files within a level are ordered alphabetically.
# Level 0
- target: pb_gen_rtl
files:
# Level 0.0
- .generated/floo_picobello_noc_pkg.sv
- .generated/snitch_cluster_pkg.sv
- .generated/pb_soc_regs_pkg.sv
# Level 0.1
- .generated/pb_soc_regs.sv
- .generated/snitch_cluster_wrapper.sv
# Level 1
- hw/picobello_pkg.sv
- hw/snitch_hwpe_subsystem.sv
- hw/snitch_tcdm_aligner.sv
# Level 2
- hw/cluster_tile.sv
- hw/cheshire_tile.sv
- hw/mem_tile.sv
- hw/spm_tile.sv
- hw/dummy_tile.sv
- target: not(asic)
files:
- hw/fhg_spu_tile.sv
- target: asic
files:
- .deps/fhg_spu_cluster/hw/fhg_spu_tile.sv
# Level 3
- hw/picobello_top.sv
- target: any(simulation, test)
include_dirs:
- .generated
- target/sim/include
files:
- target/sim/src/fixture_picobello_top.sv
- target/sim/src/tb_picobello_top.sv
- target: asic
files:
- pd/hw/picobello_chip.sv
- target: all(any(simulation, test), asic)
include_dirs:
- .generated
- pd/target/sim/include
- target/sim/include
files:
- pd/target/sim/src/fixture_picobello_chip.sv
- pd/target/sim/src/tb_picobello_chip.sv
- pd/target/sim/src/tb_picobello_chip_config.sv