diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
index 98c33766..2758f3b7 100644
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@@ -58,8 +58,10 @@ jobs:
python-version: "3.11"
- name: Install deps
run: python -m pip install --upgrade pip "mkdocs<2" mkdocs-material
- - name: Build docs (MkDocs)
+ - name: Build docs (English MkDocs)
run: mkdocs build --strict
+ - name: Build docs (Chinese MkDocs)
+ run: mkdocs build --strict -f mkdocs.zh.yml -d site/zh
lint:
runs-on: ubuntu-latest
diff --git a/.github/workflows/pages.yml b/.github/workflows/pages.yml
index ede67bbd..5553382f 100644
--- a/.github/workflows/pages.yml
+++ b/.github/workflows/pages.yml
@@ -33,9 +33,12 @@ jobs:
run: |
python -m pip install --upgrade pip "mkdocs<2" mkdocs-material
- - name: Build MkDocs site
+ - name: Build English docs
run: mkdocs build --strict
+ - name: Build Chinese docs
+ run: mkdocs build --strict -f mkdocs.zh.yml -d site/zh
+
- name: Upload artifact
uses: actions/upload-pages-artifact@v5
with:
diff --git a/README.md b/README.md
index b12d17f4..2bac1c66 100644
--- a/README.md
+++ b/README.md
@@ -94,7 +94,6 @@ linx-isa/
| Submodule | Repository | Purpose |
|-----------|------------|---------|
| `compiler/llvm` | [LinxISA/llvm-project](https://github.com/LinxISA/llvm-project) | LLVM-based compiler for Linx |
-| `compiler/ptoas` | [LinxISA/ptoas](https://github.com/LinxISA/ptoas) | PTO assembler and PTO-to-Linx lowering toolchain |
| `emulator/qemu` | [LinxISA/qemu](https://github.com/LinxISA/qemu) | QEMU-based emulator |
| `kernel/linux` | [LinxISA/linux](https://github.com/LinxISA/linux) | Linux kernel port |
| `rtl/LinxCore` | [LinxISA/LinxCore](https://github.com/LinxISA/LinxCore) | RTL implementation |
@@ -102,7 +101,6 @@ linx-isa/
| `lib/glibc` | [LinxISA/glibc](https://github.com/LinxISA/glibc) | GNU C Library port |
| `lib/musl` | [LinxISA/musl](https://github.com/LinxISA/musl) | musl libc port |
| `workloads/pto_kernels` | [LinxISA/PTO-Kernel](https://github.com/LinxISA/PTO-Kernel) | PTO accelerator kernels |
-| `skills/linx-skills` | [LinxISA/linx-skills](https://github.com/LinxISA/linx-skills) | Canonical LinxISA Codex skills |
### Updating Submodules
@@ -112,7 +110,7 @@ git submodule sync --recursive
git submodule update --init --recursive
# Pull latest from upstream
-git submodule update --remote compiler/llvm compiler/ptoas emulator/qemu kernel/linux rtl/LinxCore tools/pyCircuit lib/glibc lib/musl workloads/pto_kernels skills/linx-skills
+git submodule update --remote compiler/llvm emulator/qemu kernel/linux rtl/LinxCore tools/pyCircuit lib/glibc lib/musl workloads/pto_kernels
# Verify layout
bash tools/ci/check_repo_layout.sh
diff --git a/docs/architecture/README.md b/docs/architecture/README.md
index 6aadd15a..565d9f7f 100644
--- a/docs/architecture/README.md
+++ b/docs/architecture/README.md
@@ -12,32 +12,42 @@ Architecture-facing documentation lives under `docs/architecture/`.
- `docs/architecture/v0.56-rendering-kernel-authoring.md`
- `docs/architecture/v0.56-rendering-pto-contract.md`
- `docs/architecture/v0.56-rendering-command-contract.md`
-- published LinxCore mirrors:
+- published LinxCore pages:
- `docs/architecture/linxcore/overview.md`
- `docs/architecture/linxcore/microarchitecture.md`
- `docs/architecture/linxcore/interfaces.md`
- `docs/architecture/linxcore/verification-matrix.md`
- `docs/architecture/linxcore/module-catalog.md`
- `docs/architecture/linxcore/pipeline-stage-catalog.md`
-- canonical LinxCore authoring source:
- - `rtl/LinxCore/docs/architecture/overview.md`
- - `rtl/LinxCore/docs/architecture/microarchitecture.md`
- - `rtl/LinxCore/docs/architecture/interfaces.md`
- - `rtl/LinxCore/docs/architecture/verification-matrix.md`
- - `rtl/LinxCore/docs/architecture/module-catalog.md`
- - `rtl/LinxCore/docs/architecture/pipeline-stage-catalog.md`
+- LinxCore source material:
+ - `rtl/LinxCore/docs/architecture/`
## ISA manual
- `docs/architecture/isa-manual/`
- AsciiDoc ISA manual source and generated PDF.
+## Published bilingual manual surface
+
+The published docs site now has a broader manual hierarchy than the AsciiDoc
+manual alone:
+
+- ISA/publication pages under `docs/background/`, `docs/compiler/`,
+ and the expanded `docs/isa/` tree,
+- a Chinese edition under `docs/zh/` with path parity,
+- the existing generated `docs/isa/groups/` and `docs/isa/instructions/`
+ retained as appendix/reference rather than the primary manual home.
+
+The normative rule does not change: architecture-affecting behavior is still
+owned by the English v0.56 contract pages and the English AsciiDoc manual.
+The broader manual pages are the primary published narrative surface,
+but they must stay synchronized with those normative sources.
+
## Governance notes
- LinxArch pages are the canonical architecture contract for bring-up and gates.
- LinxCore contract authoring lives in `rtl/LinxCore/docs/architecture/`; the
- superproject `docs/architecture/linxcore/` pages are generated publication
- mirrors.
+ superproject `docs/architecture/linxcore/` pages are published copies.
- Implementation-specific deep dives in submodules must link back to these
contract pages.
- Any architecture-affecting change must update LinxArch first, then implementation.
diff --git a/docs/architecture/isa-manual/README.md b/docs/architecture/isa-manual/README.md
index ce5f165a..7f252831 100644
--- a/docs/architecture/isa-manual/README.md
+++ b/docs/architecture/isa-manual/README.md
@@ -7,6 +7,17 @@ This directory contains the live v0.56.2 ISA manual for the **Linx Instruction S
The content is specific to Linx’s design (block-structured control flow, `BSTART/BSTOP`, ClockHands temporaries,
template instructions like `FENTRY`, etc).
+The docs site also publishes a broader Markdown manual hierarchy for the standalone site. That broader hierarchy is the primary public
+navigation surface, but this English AsciiDoc manual remains the normative
+English manual source for architecture-visible behavior.
+
+Related published pages:
+
+- `docs/background/`
+- `docs/compiler/`
+- `docs/isa/`
+- `docs/zh/` (Chinese edition)
+
## Build
From this directory:
diff --git a/docs/architecture/linxcore/interfaces.md b/docs/architecture/linxcore/interfaces.md
index 8132a92c..7fa967b9 100644
--- a/docs/architecture/linxcore/interfaces.md
+++ b/docs/architecture/linxcore/interfaces.md
@@ -1,5 +1,4 @@
# LinxCore External Interface Contracts
-
## pyCircuit-LinxCore interface contract (LC-IF-PYC-001)
The pyCircuit/LinxCore integration contract is versioned and gate-enforced.
diff --git a/docs/architecture/linxcore/microarchitecture.md b/docs/architecture/linxcore/microarchitecture.md
index f62a7d7b..f50f83b0 100644
--- a/docs/architecture/linxcore/microarchitecture.md
+++ b/docs/architecture/linxcore/microarchitecture.md
@@ -1,12 +1,4 @@
-
-
-
# LinxCore v0.56 Microarchitecture Contract
-
-> This published page mirrors the canonical LinxCore source in
-> `rtl/LinxCore/docs/architecture/microarchitecture.md`.
-
-
## Baseline superscalar contract
LinxCore is the canonical superscalar out-of-order core for LinxISA `v0.56`.
diff --git a/docs/architecture/linxcore/module-catalog.md b/docs/architecture/linxcore/module-catalog.md
index 3f414a62..af790bef 100644
--- a/docs/architecture/linxcore/module-catalog.md
+++ b/docs/architecture/linxcore/module-catalog.md
@@ -1,12 +1,4 @@
-
-
-
# LinxCore Module Catalog
-
-> This published page mirrors the canonical LinxCore source in
-> `rtl/LinxCore/docs/architecture/module-catalog.md`.
-
-
This chapter defines the canonical module structure for LinxCore under the live
`v0.56` superscalar contract.
diff --git a/docs/architecture/linxcore/overview.md b/docs/architecture/linxcore/overview.md
index 11a09795..6c3d2cbc 100644
--- a/docs/architecture/linxcore/overview.md
+++ b/docs/architecture/linxcore/overview.md
@@ -1,12 +1,4 @@
-
-
-
# LinxCore v0.56 Superscalar Bring-up Overview
-
-> This published page mirrors the canonical LinxCore source in
-> `rtl/LinxCore/docs/architecture/overview.md`.
-
-
## Scope
This document is the top-level specification overview for LinxCore under the
diff --git a/docs/architecture/linxcore/pipeline-stage-catalog.md b/docs/architecture/linxcore/pipeline-stage-catalog.md
index 6747f1e1..e87d7c7f 100644
--- a/docs/architecture/linxcore/pipeline-stage-catalog.md
+++ b/docs/architecture/linxcore/pipeline-stage-catalog.md
@@ -1,12 +1,4 @@
-
-
-
# LinxCore Pipeline Stage Catalog
-
-> This published page mirrors the canonical LinxCore source in
-> `rtl/LinxCore/docs/architecture/pipeline-stage-catalog.md`.
-
-
This chapter defines the architecturally visible LinxCore stage set and the
module that owns each stage.
diff --git a/docs/architecture/linxcore/verification-matrix.md b/docs/architecture/linxcore/verification-matrix.md
index a528eaec..8c6d702c 100644
--- a/docs/architecture/linxcore/verification-matrix.md
+++ b/docs/architecture/linxcore/verification-matrix.md
@@ -1,12 +1,4 @@
-
-
-
# LinxCore v0.56 Verification Matrix
-
-> This published page mirrors the canonical LinxCore source in
-> `rtl/LinxCore/docs/architecture/verification-matrix.md`.
-
-
This matrix ties LinxCore architecture intent to strict required gates.
It is the normative mapping between:
diff --git a/docs/architecture/v0.56-architecture-contract.md b/docs/architecture/v0.56-architecture-contract.md
index 02061ae4..fb3e4f32 100644
--- a/docs/architecture/v0.56-architecture-contract.md
+++ b/docs/architecture/v0.56-architecture-contract.md
@@ -128,16 +128,27 @@ these kernel changes:
- `docs/architecture/linxcore/module-catalog.md`
- `docs/architecture/linxcore/pipeline-stage-catalog.md`
-LinxCore-specific authoring lives in:
+## Published Manual Mirrors
-- `rtl/LinxCore/docs/architecture/overview.md`
-- `rtl/LinxCore/docs/architecture/microarchitecture.md`
-- `rtl/LinxCore/docs/architecture/interfaces.md`
-- `rtl/LinxCore/docs/architecture/verification-matrix.md`
-- `rtl/LinxCore/docs/architecture/module-catalog.md`
-- `rtl/LinxCore/docs/architecture/pipeline-stage-catalog.md`
+The public documentation site now exposes a broader manual
+hierarchy alongside the normative pages above:
-The `docs/architecture/linxcore/` pages remain the published mirrors used by
+- `docs/background/`
+- `docs/compiler/`
+- architecture/state/type/instruction-family pages under `docs/isa/`
+- a Chinese edition of the published surface under `docs/zh/`
+- generated appendix/reference pages under `docs/isa/groups/` and
+ `docs/isa/instructions/`
+
+Those published pages must not drift semantically from the normative contract.
+If a public page and a canonical contract page disagree, the contract page must
+be updated or the public page must be corrected immediately.
+
+LinxCore source material lives in:
+
+- `rtl/LinxCore/docs/architecture/`
+
+The `docs/architecture/linxcore/` pages remain the published pages used by
mkdocs and architecture navigation.
## Conformance Gates
diff --git a/docs/architecture/v0.56-hardening-policy.md b/docs/architecture/v0.56-hardening-policy.md
index c9f50437..24a3152e 100644
--- a/docs/architecture/v0.56-hardening-policy.md
+++ b/docs/architecture/v0.56-hardening-policy.md
@@ -37,11 +37,11 @@ These rules come from:
- `docs/architecture/v0.56-architecture-contract.md`
- `docs/architecture/v0.56-workload-engine-model.md`
- `docs/architecture/v0.56-rendering-command-contract.md`
-- `docs/architecture/linxcore/microarchitecture.md` (published mirror of
+- `docs/architecture/linxcore/microarchitecture.md` (published copy of
`rtl/LinxCore/docs/architecture/microarchitecture.md`)
-- `docs/architecture/linxcore/module-catalog.md` (published mirror of
+- `docs/architecture/linxcore/module-catalog.md` (published copy of
`rtl/LinxCore/docs/architecture/module-catalog.md`)
-- `docs/architecture/linxcore/pipeline-stage-catalog.md` (published mirror of
+- `docs/architecture/linxcore/pipeline-stage-catalog.md` (published copy of
`rtl/LinxCore/docs/architecture/pipeline-stage-catalog.md`)
- `isa/v0.56/state/rendering_profile.json`
- `docs/architecture/isa-manual/src/chapters/08_tile_blocks.adoc`
diff --git a/docs/assets/lang-map.json b/docs/assets/lang-map.json
new file mode 100644
index 00000000..f288c87c
--- /dev/null
+++ b/docs/assets/lang-map.json
@@ -0,0 +1,4222 @@
+{
+ "/": "/zh/",
+ "/README/": "/zh/README/",
+ "/architecture/README/": "/zh/architecture/README/",
+ "/architecture/isa-manual/README/": "/zh/architecture/isa-manual/README/",
+ "/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/concurrent-ruby-1.3.6/README/": "/zh/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/concurrent-ruby-1.3.6/README/",
+ "/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/hashery-2.1.2/HISTORY/": "/zh/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/hashery-2.1.2/HISTORY/",
+ "/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/hashery-2.1.2/README/": "/zh/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/hashery-2.1.2/README/",
+ "/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/pdf-reader-2.15.1/README/": "/zh/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/pdf-reader-2.15.1/README/",
+ "/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/prawn-icon-3.0.0/CHANGELOG/": "/zh/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/prawn-icon-3.0.0/CHANGELOG/",
+ "/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/prawn-icon-3.0.0/README/": "/zh/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/prawn-icon-3.0.0/README/",
+ "/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/prawn-svg-0.32.0/README/": "/zh/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/prawn-svg-0.32.0/README/",
+ "/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/public_suffix-5.1.1/2.0-Upgrade/": "/zh/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/public_suffix-5.1.1/2.0-Upgrade/",
+ "/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/public_suffix-5.1.1/CHANGELOG/": "/zh/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/public_suffix-5.1.1/CHANGELOG/",
+ "/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/public_suffix-5.1.1/README/": "/zh/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/public_suffix-5.1.1/README/",
+ "/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/public_suffix-5.1.1/SECURITY/": "/zh/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/public_suffix-5.1.1/SECURITY/",
+ "/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/rexml-3.4.4/NEWS/": "/zh/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/rexml-3.4.4/NEWS/",
+ "/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/rexml-3.4.4/README/": "/zh/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/rexml-3.4.4/README/",
+ "/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/ruby-rc4-0.1.5/README/": "/zh/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/ruby-rc4-0.1.5/README/",
+ "/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/safe_yaml-1.0.5/CHANGES/": "/zh/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/safe_yaml-1.0.5/CHANGES/",
+ "/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/safe_yaml-1.0.5/README/": "/zh/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/safe_yaml-1.0.5/README/",
+ "/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/treetop-1.6.18/README/": "/zh/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/treetop-1.6.18/README/",
+ "/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/ttfunk-1.7.0/CHANGELOG/": "/zh/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/ttfunk-1.7.0/CHANGELOG/",
+ "/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/ttfunk-1.7.0/README/": "/zh/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/ttfunk-1.7.0/README/",
+ "/architecture/linxcore-unified-ai-render-gpgpu/": "/zh/architecture/linxcore-unified-ai-render-gpgpu/",
+ "/architecture/linxcore/interfaces/": "/zh/architecture/linxcore/interfaces/",
+ "/architecture/linxcore/microarchitecture/": "/zh/architecture/linxcore/microarchitecture/",
+ "/architecture/linxcore/module-catalog/": "/zh/architecture/linxcore/module-catalog/",
+ "/architecture/linxcore/overview/": "/zh/architecture/linxcore/overview/",
+ "/architecture/linxcore/pipeline-stage-catalog/": "/zh/architecture/linxcore/pipeline-stage-catalog/",
+ "/architecture/linxcore/verification-matrix/": "/zh/architecture/linxcore/verification-matrix/",
+ "/architecture/research/linx-simt-alt-compiler-gap-analysis/": "/zh/architecture/research/linx-simt-alt-compiler-gap-analysis/",
+ "/architecture/v0.56-architecture-contract/": "/zh/architecture/v0.56-architecture-contract/",
+ "/architecture/v0.56-hardening-policy/": "/zh/architecture/v0.56-hardening-policy/",
+ "/architecture/v0.56-rendering-command-contract/": "/zh/architecture/v0.56-rendering-command-contract/",
+ "/architecture/v0.56-rendering-kernel-authoring/": "/zh/architecture/v0.56-rendering-kernel-authoring/",
+ "/architecture/v0.56-rendering-pto-contract/": "/zh/architecture/v0.56-rendering-pto-contract/",
+ "/architecture/v0.56-simt-compiler-contract-plan/": "/zh/architecture/v0.56-simt-compiler-contract-plan/",
+ "/architecture/v0.56-simt-compiler-contract/": "/zh/architecture/v0.56-simt-compiler-contract/",
+ "/architecture/v0.56-workload-engine-model/": "/zh/architecture/v0.56-workload-engine-model/",
+ "/backend/exu/": "/zh/backend/exu/",
+ "/backend/issue/": "/zh/backend/issue/",
+ "/backend/pe_rf/": "/zh/backend/pe_rf/",
+ "/backend/rob/": "/zh/backend/rob/",
+ "/backend/scheduler/": "/zh/backend/scheduler/",
+ "/background/": "/zh/background/",
+ "/bcc/bdecode/": "/zh/bcc/bdecode/",
+ "/bcc/bdispatch/": "/zh/bcc/bdispatch/",
+ "/bcc/bhcache/": "/zh/bcc/bhcache/",
+ "/bcc/bifu/": "/zh/bcc/bifu/",
+ "/bcc/bp/": "/zh/bcc/bp/",
+ "/bcc/bren/": "/zh/bcc/bren/",
+ "/bcc/brf/": "/zh/bcc/brf/",
+ "/bcc/brob/": "/zh/bcc/brob/",
+ "/bcc/overview/": "/zh/bcc/overview/",
+ "/bringup/ALIGNMENT_MATRIX/": "/zh/bringup/ALIGNMENT_MATRIX/",
+ "/bringup/AVS_CONTRACT/": "/zh/bringup/AVS_CONTRACT/",
+ "/bringup/CPP_BRINGUP_CONTRACT/": "/zh/bringup/CPP_BRINGUP_CONTRACT/",
+ "/bringup/CROSSSTACK_SKILLS_SUMMARY/": "/zh/bringup/CROSSSTACK_SKILLS_SUMMARY/",
+ "/bringup/GATE_STATUS/": "/zh/bringup/GATE_STATUS/",
+ "/bringup/GETTING_STARTED/": "/zh/bringup/GETTING_STARTED/",
+ "/bringup/ISA_GAP_ANALYSIS/": "/zh/bringup/ISA_GAP_ANALYSIS/",
+ "/bringup/LINX_ASM_ABI_UNWIND_CONTEXT_CHECKLIST/": "/zh/bringup/LINX_ASM_ABI_UNWIND_CONTEXT_CHECKLIST/",
+ "/bringup/MATURITY_PLAN/": "/zh/bringup/MATURITY_PLAN/",
+ "/bringup/PROGRESS/": "/zh/bringup/PROGRESS/",
+ "/bringup/README/": "/zh/bringup/README/",
+ "/bringup/SIMT_COMPILER_MATURITY_PLAN/": "/zh/bringup/SIMT_COMPILER_MATURITY_PLAN/",
+ "/bringup/SIMT_COMPILER_SUPPORTED_SUBSET/": "/zh/bringup/SIMT_COMPILER_SUPPORTED_SUBSET/",
+ "/bringup/SUPERPROJECT_BRINGUP_CHECKLIST/": "/zh/bringup/SUPERPROJECT_BRINGUP_CHECKLIST/",
+ "/bringup/agent_runs/checklists/architecture_docs/": "/zh/bringup/agent_runs/checklists/architecture_docs/",
+ "/bringup/agent_runs/checklists/compiler_llvm/": "/zh/bringup/agent_runs/checklists/compiler_llvm/",
+ "/bringup/agent_runs/checklists/emulator_qemu/": "/zh/bringup/agent_runs/checklists/emulator_qemu/",
+ "/bringup/agent_runs/checklists/integration_release/": "/zh/bringup/agent_runs/checklists/integration_release/",
+ "/bringup/agent_runs/checklists/kernel_linux/": "/zh/bringup/agent_runs/checklists/kernel_linux/",
+ "/bringup/agent_runs/checklists/libc_runtime/": "/zh/bringup/agent_runs/checklists/libc_runtime/",
+ "/bringup/agent_runs/checklists/linxcore_rtl/": "/zh/bringup/agent_runs/checklists/linxcore_rtl/",
+ "/bringup/agent_runs/checklists/pycircuit_model/": "/zh/bringup/agent_runs/checklists/pycircuit_model/",
+ "/bringup/agent_runs/checklists/specint_qemu/": "/zh/bringup/agent_runs/checklists/specint_qemu/",
+ "/bringup/agent_runs/checklists/testbench_verif/": "/zh/bringup/agent_runs/checklists/testbench_verif/",
+ "/bringup/agent_runs/checklists/trace_linxtrace/": "/zh/bringup/agent_runs/checklists/trace_linxtrace/",
+ "/bringup/agent_runs/skills_evolution/summary-2026-02-28-r1-phase-next-skills/": "/zh/bringup/agent_runs/skills_evolution/summary-2026-02-28-r1-phase-next-skills/",
+ "/bringup/agent_runs/skills_evolution/summary-2026-05-15-qemu-callret-closure/": "/zh/bringup/agent_runs/skills_evolution/summary-2026-05-15-qemu-callret-closure/",
+ "/bringup/code_density_and_dynamic_reduction/": "/zh/bringup/code_density_and_dynamic_reduction/",
+ "/bringup/contracts/fpga_platform_contract/": "/zh/bringup/contracts/fpga_platform_contract/",
+ "/bringup/contracts/pyc_artifact_contract/": "/zh/bringup/contracts/pyc_artifact_contract/",
+ "/bringup/contracts/pyc_linxcore_interface_contract/": "/zh/bringup/contracts/pyc_linxcore_interface_contract/",
+ "/bringup/contracts/trace_schema/": "/zh/bringup/contracts/trace_schema/",
+ "/bringup/gates/qemu_isa_coverage_latest/": "/zh/bringup/gates/qemu_isa_coverage_latest/",
+ "/bringup/gates/qemu_opcode_sync_latest/": "/zh/bringup/gates/qemu_opcode_sync_latest/",
+ "/bringup/libc_status/": "/zh/bringup/libc_status/",
+ "/bringup/phases/01_compiler/": "/zh/bringup/phases/01_compiler/",
+ "/bringup/phases/02_isa_spec/": "/zh/bringup/phases/02_isa_spec/",
+ "/bringup/phases/03_emulator_qemu/": "/zh/bringup/phases/03_emulator_qemu/",
+ "/bringup/phases/04_rtl/": "/zh/bringup/phases/04_rtl/",
+ "/bringup/phases/05_fpga_zybo_z7/": "/zh/bringup/phases/05_fpga_zybo_z7/",
+ "/bringup/phases/06_linux_on_janus/": "/zh/bringup/phases/06_linux_on_janus/",
+ "/bringup/phases/07_toolchain_glibc/": "/zh/bringup/phases/07_toolchain_glibc/",
+ "/bringup/phases/08_toolchain_musl/": "/zh/bringup/phases/08_toolchain_musl/",
+ "/bringup/phases/README/": "/zh/bringup/phases/README/",
+ "/bringup/plan/arch/": "/zh/bringup/plan/arch/",
+ "/bringup/plan/isa_clarifications/": "/zh/bringup/plan/isa_clarifications/",
+ "/bringup/plan/sail_formalization_v0.3/": "/zh/bringup/plan/sail_formalization_v0.3/",
+ "/bringup/plan/sail_review_log_v0.3/": "/zh/bringup/plan/sail_review_log_v0.3/",
+ "/bringup/plan/submodule_isa_alignment_v0.56/": "/zh/bringup/plan/submodule_isa_alignment_v0.56/",
+ "/bringup/rendering_vulkan_bringup/": "/zh/bringup/rendering_vulkan_bringup/",
+ "/bringup/spec_linxcore_xcheck/": "/zh/bringup/spec_linxcore_xcheck/",
+ "/bringup/virtio_9p_debug/": "/zh/bringup/virtio_9p_debug/",
+ "/change_log/update_v0.12/": "/zh/change_log/update_v0.12/",
+ "/change_log/update_v0.13/": "/zh/change_log/update_v0.13/",
+ "/change_log/update_v0.16/": "/zh/change_log/update_v0.16/",
+ "/change_log/update_v0.20/": "/zh/change_log/update_v0.20/",
+ "/change_log/update_v0.30/": "/zh/change_log/update_v0.30/",
+ "/change_log/update_v0.31/": "/zh/change_log/update_v0.31/",
+ "/change_log/update_v0.32/": "/zh/change_log/update_v0.32/",
+ "/change_log/update_v0.33/": "/zh/change_log/update_v0.33/",
+ "/change_log/update_v0.34/": "/zh/change_log/update_v0.34/",
+ "/change_log/update_v0.35/": "/zh/change_log/update_v0.35/",
+ "/change_log/update_v0.36/": "/zh/change_log/update_v0.36/",
+ "/change_log/update_v0.40/": "/zh/change_log/update_v0.40/",
+ "/change_log/update_v0.41/": "/zh/change_log/update_v0.41/",
+ "/change_log/update_v0.42/": "/zh/change_log/update_v0.42/",
+ "/change_log/update_v0.43/": "/zh/change_log/update_v0.43/",
+ "/change_log/update_v0.50/": "/zh/change_log/update_v0.50/",
+ "/change_log/update_v0.51/": "/zh/change_log/update_v0.51/",
+ "/change_log/update_v0.52/": "/zh/change_log/update_v0.52/",
+ "/change_log/update_v0.53/": "/zh/change_log/update_v0.53/",
+ "/change_log/update_v0.54/": "/zh/change_log/update_v0.54/",
+ "/change_log/update_v0.55/": "/zh/change_log/update_v0.55/",
+ "/change_log/update_v0.56/": "/zh/change_log/update_v0.56/",
+ "/compiler/Calling-Convention/": "/zh/compiler/Calling-Convention/",
+ "/compiler/assembly_manual/Architecture_Register/": "/zh/compiler/assembly_manual/Architecture_Register/",
+ "/compiler/assembly_manual/Assemble_syntax/": "/zh/compiler/assembly_manual/Assemble_syntax/",
+ "/compiler/assembly_manual/BlockISA_assemble_difference/": "/zh/compiler/assembly_manual/BlockISA_assemble_difference/",
+ "/compiler/assembly_manual/Compressed_Instruction/": "/zh/compiler/assembly_manual/Compressed_Instruction/",
+ "/compiler/assembly_manual/Conditional_execution/": "/zh/compiler/assembly_manual/Conditional_execution/",
+ "/compiler/assembly_manual/Constant_Immediate_Value/": "/zh/compiler/assembly_manual/Constant_Immediate_Value/",
+ "/compiler/assembly_manual/Function_alignment/": "/zh/compiler/assembly_manual/Function_alignment/",
+ "/compiler/assembly_manual/Inline_Assembly/": "/zh/compiler/assembly_manual/Inline_Assembly/",
+ "/compiler/assembly_manual/Introduct_BlockISA_assemble_tool/": "/zh/compiler/assembly_manual/Introduct_BlockISA_assemble_tool/",
+ "/compiler/assembly_manual/Introduction/": "/zh/compiler/assembly_manual/Introduction/",
+ "/compiler/assembly_manual/Introduction_assemble_language/": "/zh/compiler/assembly_manual/Introduction_assemble_language/",
+ "/compiler/assembly_manual/Micro-Instruction/": "/zh/compiler/assembly_manual/Micro-Instruction/",
+ "/compiler/assembly_manual/Micro-assemble-instruction/": "/zh/compiler/assembly_manual/Micro-assemble-instruction/",
+ "/compiler/assembly_manual/PC_value/": "/zh/compiler/assembly_manual/PC_value/",
+ "/compiler/assembly_manual/Pseudo_instruction/": "/zh/compiler/assembly_manual/Pseudo_instruction/",
+ "/compiler/assembly_manual/SIMT_instruction/": "/zh/compiler/assembly_manual/SIMT_instruction/",
+ "/compiler/assembly_manual/Standard_binary_interge_instruction/": "/zh/compiler/assembly_manual/Standard_binary_interge_instruction/",
+ "/compiler/assembly_manual/Std_Extern/": "/zh/compiler/assembly_manual/Std_Extern/",
+ "/compiler/assembly_manual/assemble_instruction/": "/zh/compiler/assembly_manual/assemble_instruction/",
+ "/compiler/assembly_manual/atomic_instruction/": "/zh/compiler/assembly_manual/atomic_instruction/",
+ "/compiler/assembly_manual/battr/": "/zh/compiler/assembly_manual/battr/",
+ "/compiler/assembly_manual/bend/": "/zh/compiler/assembly_manual/bend/",
+ "/compiler/assembly_manual/bget/": "/zh/compiler/assembly_manual/bget/",
+ "/compiler/assembly_manual/bhint/": "/zh/compiler/assembly_manual/bhint/",
+ "/compiler/assembly_manual/bitmanipulate_instruction/": "/zh/compiler/assembly_manual/bitmanipulate_instruction/",
+ "/compiler/assembly_manual/block_header/": "/zh/compiler/assembly_manual/block_header/",
+ "/compiler/assembly_manual/block_type/": "/zh/compiler/assembly_manual/block_type/",
+ "/compiler/assembly_manual/bsbar/": "/zh/compiler/assembly_manual/bsbar/",
+ "/compiler/assembly_manual/bset/": "/zh/compiler/assembly_manual/bset/",
+ "/compiler/assembly_manual/bstart/": "/zh/compiler/assembly_manual/bstart/",
+ "/compiler/assembly_manual/bstop/": "/zh/compiler/assembly_manual/bstop/",
+ "/compiler/assembly_manual/btext/": "/zh/compiler/assembly_manual/btext/",
+ "/compiler/assembly_manual/cmp_branch_jmp/": "/zh/compiler/assembly_manual/cmp_branch_jmp/",
+ "/compiler/assembly_manual/const_value/": "/zh/compiler/assembly_manual/const_value/",
+ "/compiler/assembly_manual/example/": "/zh/compiler/assembly_manual/example/",
+ "/compiler/assembly_manual/float_instruction/": "/zh/compiler/assembly_manual/float_instruction/",
+ "/compiler/assembly_manual/label/": "/zh/compiler/assembly_manual/label/",
+ "/compiler/assembly_manual/load_store_instruction/": "/zh/compiler/assembly_manual/load_store_instruction/",
+ "/compiler/assembly_manual/multiple_divide_instruction/": "/zh/compiler/assembly_manual/multiple_divide_instruction/",
+ "/compiler/assembly_manual/section/": "/zh/compiler/assembly_manual/section/",
+ "/compiler/assembly_manual/ssr_instruction/": "/zh/compiler/assembly_manual/ssr_instruction/",
+ "/compiler/assembly_manual/template_block/": "/zh/compiler/assembly_manual/template_block/",
+ "/compiler/hyper_block/": "/zh/compiler/hyper_block/",
+ "/compiler/linker/": "/zh/compiler/linker/",
+ "/compiler/manuals/": "/zh/compiler/manuals/",
+ "/compiler/qemu_slices/": "/zh/compiler/qemu_slices/",
+ "/compiler/run_c_program/": "/zh/compiler/run_c_program/",
+ "/cpu_core_intro/arch/": "/zh/cpu_core_intro/arch/",
+ "/cpu_core_intro/block_bigLittle_core/": "/zh/cpu_core_intro/block_bigLittle_core/",
+ "/figs/bitfield/README_BitField/": "/zh/figs/bitfield/README_BitField/",
+ "/isa/": "/zh/isa/",
+ "/isa/arch/acr/": "/zh/isa/arch/acr/",
+ "/isa/arch/bisa/": "/zh/isa/arch/bisa/",
+ "/isa/arch/branch/": "/zh/isa/arch/branch/",
+ "/isa/arch/constraints/": "/zh/isa/arch/constraints/",
+ "/isa/arch/corestate/": "/zh/isa/arch/corestate/",
+ "/isa/arch/exception/": "/zh/isa/arch/exception/",
+ "/isa/arch/execute/": "/zh/isa/arch/execute/",
+ "/isa/arch/executemachine/": "/zh/isa/arch/executemachine/",
+ "/isa/arch/executemode/": "/zh/isa/arch/executemode/",
+ "/isa/arch/fixup/": "/zh/isa/arch/fixup/",
+ "/isa/arch/prgorder/": "/zh/isa/arch/prgorder/",
+ "/isa/blockIntro/cube_block/header/": "/zh/isa/blockIntro/cube_block/header/",
+ "/isa/blockIntro/cube_block/intro/": "/zh/isa/blockIntro/cube_block/intro/",
+ "/isa/blockIntro/fp_block/fp_arithmetic/": "/zh/isa/blockIntro/fp_block/fp_arithmetic/",
+ "/isa/blockIntro/fp_block/fp_compare/": "/zh/isa/blockIntro/fp_block/fp_compare/",
+ "/isa/blockIntro/fp_block/fp_convert/": "/zh/isa/blockIntro/fp_block/fp_convert/",
+ "/isa/blockIntro/fp_block/instlist/": "/zh/isa/blockIntro/fp_block/instlist/",
+ "/isa/blockIntro/fp_block/intro/": "/zh/isa/blockIntro/fp_block/intro/",
+ "/isa/blockIntro/fp_block/max_min/": "/zh/isa/blockIntro/fp_block/max_min/",
+ "/isa/blockIntro/mem_block/dimmode/": "/zh/isa/blockIntro/mem_block/dimmode/",
+ "/isa/blockIntro/mem_block/header/": "/zh/isa/blockIntro/mem_block/header/",
+ "/isa/blockIntro/mem_block/instlist/": "/zh/isa/blockIntro/mem_block/instlist/",
+ "/isa/blockIntro/mem_block/intro/": "/zh/isa/blockIntro/mem_block/intro/",
+ "/isa/blockIntro/scainstrs/arithmetic/": "/zh/isa/blockIntro/scainstrs/arithmetic/",
+ "/isa/blockIntro/scainstrs/bitmanip/": "/zh/isa/blockIntro/scainstrs/bitmanip/",
+ "/isa/blockIntro/scainstrs/branch/": "/zh/isa/blockIntro/scainstrs/branch/",
+ "/isa/blockIntro/scainstrs/compare/": "/zh/isa/blockIntro/scainstrs/compare/",
+ "/isa/blockIntro/scainstrs/divide/": "/zh/isa/blockIntro/scainstrs/divide/",
+ "/isa/blockIntro/scainstrs/multi/": "/zh/isa/blockIntro/scainstrs/multi/",
+ "/isa/blockIntro/scainstrs/pc_arithmetic/": "/zh/isa/blockIntro/scainstrs/pc_arithmetic/",
+ "/isa/blockIntro/scainstrs/setc/": "/zh/isa/blockIntro/scainstrs/setc/",
+ "/isa/blockIntro/scainstrs/ssr_opration/": "/zh/isa/blockIntro/scainstrs/ssr_opration/",
+ "/isa/blockIntro/std_block/instlist/": "/zh/isa/blockIntro/std_block/instlist/",
+ "/isa/blockIntro/std_block/intro/": "/zh/isa/blockIntro/std_block/intro/",
+ "/isa/blockIntro/std_block/prefetch/": "/zh/isa/blockIntro/std_block/prefetch/",
+ "/isa/blockIntro/sys_block/atomic/": "/zh/isa/blockIntro/sys_block/atomic/",
+ "/isa/blockIntro/sys_block/cachemaintain/": "/zh/isa/blockIntro/sys_block/cachemaintain/",
+ "/isa/blockIntro/sys_block/excutecontrol/": "/zh/isa/blockIntro/sys_block/excutecontrol/",
+ "/isa/blockIntro/sys_block/gqm/": "/zh/isa/blockIntro/sys_block/gqm/",
+ "/isa/blockIntro/sys_block/instlist/": "/zh/isa/blockIntro/sys_block/instlist/",
+ "/isa/blockIntro/sys_block/intro/": "/zh/isa/blockIntro/sys_block/intro/",
+ "/isa/blockIntro/sys_block/lr_sc/": "/zh/isa/blockIntro/sys_block/lr_sc/",
+ "/isa/blockIntro/sys_block/tlb/": "/zh/isa/blockIntro/sys_block/tlb/",
+ "/isa/blockIntro/tepl_block/header/": "/zh/isa/blockIntro/tepl_block/header/",
+ "/isa/blockIntro/tepl_block/intro/": "/zh/isa/blockIntro/tepl_block/intro/",
+ "/isa/blockIntro/tma_block/header/": "/zh/isa/blockIntro/tma_block/header/",
+ "/isa/blockIntro/tma_block/intro/": "/zh/isa/blockIntro/tma_block/intro/",
+ "/isa/blockIntro/vec_block/header/": "/zh/isa/blockIntro/vec_block/header/",
+ "/isa/blockIntro/vec_block/instlist/": "/zh/isa/blockIntro/vec_block/instlist/",
+ "/isa/blockIntro/vec_block/intro/": "/zh/isa/blockIntro/vec_block/intro/",
+ "/isa/blockIntro/vec_block/stack/": "/zh/isa/blockIntro/vec_block/stack/",
+ "/isa/blockIntro/vecinstrs/arithmetic/": "/zh/isa/blockIntro/vecinstrs/arithmetic/",
+ "/isa/blockIntro/vecinstrs/atomic/": "/zh/isa/blockIntro/vecinstrs/atomic/",
+ "/isa/blockIntro/vecinstrs/bitmanip/": "/zh/isa/blockIntro/vecinstrs/bitmanip/",
+ "/isa/blockIntro/vecinstrs/branch/": "/zh/isa/blockIntro/vecinstrs/branch/",
+ "/isa/blockIntro/vecinstrs/compare/": "/zh/isa/blockIntro/vecinstrs/compare/",
+ "/isa/blockIntro/vecinstrs/convert/": "/zh/isa/blockIntro/vecinstrs/convert/",
+ "/isa/blockIntro/vecinstrs/fp_arithmetic/": "/zh/isa/blockIntro/vecinstrs/fp_arithmetic/",
+ "/isa/blockIntro/vecinstrs/fp_compare/": "/zh/isa/blockIntro/vecinstrs/fp_compare/",
+ "/isa/blockIntro/vecinstrs/gqm/": "/zh/isa/blockIntro/vecinstrs/gqm/",
+ "/isa/blockIntro/vecinstrs/instIntro/": "/zh/isa/blockIntro/vecinstrs/instIntro/",
+ "/isa/blockIntro/vecinstrs/loadStore/": "/zh/isa/blockIntro/vecinstrs/loadStore/",
+ "/isa/blockIntro/vecinstrs/loadStoreBridge/": "/zh/isa/blockIntro/vecinstrs/loadStoreBridge/",
+ "/isa/blockIntro/vecinstrs/max_min/": "/zh/isa/blockIntro/vecinstrs/max_min/",
+ "/isa/blockIntro/vecinstrs/mul_div/": "/zh/isa/blockIntro/vecinstrs/mul_div/",
+ "/isa/blockIntro/vecinstrs/reduce/": "/zh/isa/blockIntro/vecinstrs/reduce/",
+ "/isa/blockIntro/vecinstrs/shuffle/": "/zh/isa/blockIntro/vecinstrs/shuffle/",
+ "/isa/blockIntro/xb_block/intro/": "/zh/isa/blockIntro/xb_block/intro/",
+ "/isa/custom/custom_isa/": "/zh/isa/custom/custom_isa/",
+ "/isa/custom/hac_intf/": "/zh/isa/custom/hac_intf/",
+ "/isa/datatype/BF16/": "/zh/isa/datatype/BF16/",
+ "/isa/datatype/FP16/": "/zh/isa/datatype/FP16/",
+ "/isa/datatype/FP32/": "/zh/isa/datatype/FP32/",
+ "/isa/datatype/FP4/": "/zh/isa/datatype/FP4/",
+ "/isa/datatype/FP6/": "/zh/isa/datatype/FP6/",
+ "/isa/datatype/FP64/": "/zh/isa/datatype/FP64/",
+ "/isa/datatype/FP8/": "/zh/isa/datatype/FP8/",
+ "/isa/datatype/HF32/": "/zh/isa/datatype/HF32/",
+ "/isa/datatype/HiF4/": "/zh/isa/datatype/HiF4/",
+ "/isa/datatype/HiF8/": "/zh/isa/datatype/HiF8/",
+ "/isa/datatype/HiF_SCALE/": "/zh/isa/datatype/HiF_SCALE/",
+ "/isa/datatype/INT16/": "/zh/isa/datatype/INT16/",
+ "/isa/datatype/INT32/": "/zh/isa/datatype/INT32/",
+ "/isa/datatype/INT4/": "/zh/isa/datatype/INT4/",
+ "/isa/datatype/INT64/": "/zh/isa/datatype/INT64/",
+ "/isa/datatype/INT8/": "/zh/isa/datatype/INT8/",
+ "/isa/datatype/MXFP4/": "/zh/isa/datatype/MXFP4/",
+ "/isa/datatype/MXFP6/": "/zh/isa/datatype/MXFP6/",
+ "/isa/datatype/MXFP8/": "/zh/isa/datatype/MXFP8/",
+ "/isa/datatype/MX_SCALE/": "/zh/isa/datatype/MX_SCALE/",
+ "/isa/datatype/TF32/": "/zh/isa/datatype/TF32/",
+ "/isa/datatype/UINT16/": "/zh/isa/datatype/UINT16/",
+ "/isa/datatype/UINT32/": "/zh/isa/datatype/UINT32/",
+ "/isa/datatype/UINT4/": "/zh/isa/datatype/UINT4/",
+ "/isa/datatype/UINT64/": "/zh/isa/datatype/UINT64/",
+ "/isa/datatype/UINT8/": "/zh/isa/datatype/UINT8/",
+ "/isa/datatype/intro/": "/zh/isa/datatype/intro/",
+ "/isa/encoding/": "/zh/isa/encoding/",
+ "/isa/encoding/overview/": "/zh/isa/encoding/overview/",
+ "/isa/encoding/space/": "/zh/isa/encoding/space/",
+ "/isa/exception/acr/": "/zh/isa/exception/acr/",
+ "/isa/exception/acr_switch/": "/zh/isa/exception/acr_switch/",
+ "/isa/exception/exception/": "/zh/isa/exception/exception/",
+ "/isa/exception/interrupt/": "/zh/isa/exception/interrupt/",
+ "/isa/groups/": "/zh/isa/groups/",
+ "/isa/groups/arithmetic/": "/zh/isa/groups/arithmetic/",
+ "/isa/groups/arithmetic_operation/": "/zh/isa/groups/arithmetic_operation/",
+ "/isa/groups/arithmetic_operation_32bit/": "/zh/isa/groups/arithmetic_operation_32bit/",
+ "/isa/groups/arithmetic_operation_64bit/": "/zh/isa/groups/arithmetic_operation_64bit/",
+ "/isa/groups/atomic/": "/zh/isa/groups/atomic/",
+ "/isa/groups/atomic_operation/": "/zh/isa/groups/atomic_operation/",
+ "/isa/groups/bit_manipulation/": "/zh/isa/groups/bit_manipulation/",
+ "/isa/groups/bit_operation/": "/zh/isa/groups/bit_operation/",
+ "/isa/groups/block_argument/": "/zh/isa/groups/block_argument/",
+ "/isa/groups/block_control_attribute/": "/zh/isa/groups/block_control_attribute/",
+ "/isa/groups/block_data_attribute/": "/zh/isa/groups/block_data_attribute/",
+ "/isa/groups/block_dimension/": "/zh/isa/groups/block_dimension/",
+ "/isa/groups/block_hint/": "/zh/isa/groups/block_hint/",
+ "/isa/groups/block_input_output/": "/zh/isa/groups/block_input_output/",
+ "/isa/groups/block_offset/": "/zh/isa/groups/block_offset/",
+ "/isa/groups/block_split/": "/zh/isa/groups/block_split/",
+ "/isa/groups/branch/": "/zh/isa/groups/branch/",
+ "/isa/groups/bstart/": "/zh/isa/groups/bstart/",
+ "/isa/groups/c_bstart/": "/zh/isa/groups/c_bstart/",
+ "/isa/groups/c_tinst/": "/zh/isa/groups/c_tinst/",
+ "/isa/groups/c_unary/": "/zh/isa/groups/c_unary/",
+ "/isa/groups/cache_maintain/": "/zh/isa/groups/cache_maintain/",
+ "/isa/groups/compare_instruction/": "/zh/isa/groups/compare_instruction/",
+ "/isa/groups/compound_operation/": "/zh/isa/groups/compound_operation/",
+ "/isa/groups/concat/": "/zh/isa/groups/concat/",
+ "/isa/groups/division/": "/zh/isa/groups/division/",
+ "/isa/groups/execution_control/": "/zh/isa/groups/execution_control/",
+ "/isa/groups/floating_point_arithmetic/": "/zh/isa/groups/floating_point_arithmetic/",
+ "/isa/groups/floating_point_compare/": "/zh/isa/groups/floating_point_compare/",
+ "/isa/groups/format_convert/": "/zh/isa/groups/format_convert/",
+ "/isa/groups/general/": "/zh/isa/groups/general/",
+ "/isa/groups/general_manager/": "/zh/isa/groups/general_manager/",
+ "/isa/groups/immediate/": "/zh/isa/groups/immediate/",
+ "/isa/groups/load_immediate_offset/": "/zh/isa/groups/load_immediate_offset/",
+ "/isa/groups/load_long_offset/": "/zh/isa/groups/load_long_offset/",
+ "/isa/groups/load_pair/": "/zh/isa/groups/load_pair/",
+ "/isa/groups/load_pc_relative/": "/zh/isa/groups/load_pc_relative/",
+ "/isa/groups/load_post_index/": "/zh/isa/groups/load_post_index/",
+ "/isa/groups/load_pre_index/": "/zh/isa/groups/load_pre_index/",
+ "/isa/groups/load_register_offset/": "/zh/isa/groups/load_register_offset/",
+ "/isa/groups/load_symbol/": "/zh/isa/groups/load_symbol/",
+ "/isa/groups/load_unscaled/": "/zh/isa/groups/load_unscaled/",
+ "/isa/groups/long_immediate/": "/zh/isa/groups/long_immediate/",
+ "/isa/groups/max_min/": "/zh/isa/groups/max_min/",
+ "/isa/groups/move/": "/zh/isa/groups/move/",
+ "/isa/groups/multi_cycle_alu/": "/zh/isa/groups/multi_cycle_alu/",
+ "/isa/groups/pc_relative/": "/zh/isa/groups/pc_relative/",
+ "/isa/groups/prefetch/": "/zh/isa/groups/prefetch/",
+ "/isa/groups/reduce_operation_with_register/": "/zh/isa/groups/reduce_operation_with_register/",
+ "/isa/groups/reserve/": "/zh/isa/groups/reserve/",
+ "/isa/groups/set_commit_argument/": "/zh/isa/groups/set_commit_argument/",
+ "/isa/groups/shuffle/": "/zh/isa/groups/shuffle/",
+ "/isa/groups/ssr_access/": "/zh/isa/groups/ssr_access/",
+ "/isa/groups/store_immediate_offset/": "/zh/isa/groups/store_immediate_offset/",
+ "/isa/groups/store_long_offset/": "/zh/isa/groups/store_long_offset/",
+ "/isa/groups/store_offset/": "/zh/isa/groups/store_offset/",
+ "/isa/groups/store_pair/": "/zh/isa/groups/store_pair/",
+ "/isa/groups/store_pc_relative/": "/zh/isa/groups/store_pc_relative/",
+ "/isa/groups/store_post_index/": "/zh/isa/groups/store_post_index/",
+ "/isa/groups/store_pre_index/": "/zh/isa/groups/store_pre_index/",
+ "/isa/groups/store_register_offset/": "/zh/isa/groups/store_register_offset/",
+ "/isa/groups/store_symbol/": "/zh/isa/groups/store_symbol/",
+ "/isa/groups/three_source_floating_point/": "/zh/isa/groups/three_source_floating_point/",
+ "/isa/groups/three_source_integer/": "/zh/isa/groups/three_source_integer/",
+ "/isa/groups/two_source_floating_point/": "/zh/isa/groups/two_source_floating_point/",
+ "/isa/header/B.CATR/": "/zh/isa/header/B.CATR/",
+ "/isa/header/B.DATR/": "/zh/isa/header/B.DATR/",
+ "/isa/header/B.DIM/": "/zh/isa/header/B.DIM/",
+ "/isa/header/B.HINT/": "/zh/isa/header/B.HINT/",
+ "/isa/header/B.IOD/": "/zh/isa/header/B.IOD/",
+ "/isa/header/B.IOR/": "/zh/isa/header/B.IOR/",
+ "/isa/header/B.IOT/": "/zh/isa/header/B.IOT/",
+ "/isa/header/B.TEXT/": "/zh/isa/header/B.TEXT/",
+ "/isa/header/BSTART.FP/": "/zh/isa/header/BSTART.FP/",
+ "/isa/header/BSTART.STD/": "/zh/isa/header/BSTART.STD/",
+ "/isa/header/BSTART.SYS/": "/zh/isa/header/BSTART.SYS/",
+ "/isa/header/BSTART/": "/zh/isa/header/BSTART/",
+ "/isa/header/BSTOP/": "/zh/isa/header/BSTOP/",
+ "/isa/header/C.B.DIM/": "/zh/isa/header/C.B.DIM/",
+ "/isa/header/C.BSTART/": "/zh/isa/header/C.BSTART/",
+ "/isa/header/ComBlockIntro/": "/zh/isa/header/ComBlockIntro/",
+ "/isa/header/HL.BSTART/": "/zh/isa/header/HL.BSTART/",
+ "/isa/header/Intro/": "/zh/isa/header/Intro/",
+ "/isa/header/L.BSTART/": "/zh/isa/header/L.BSTART/",
+ "/isa/header/XB/": "/zh/isa/header/XB/",
+ "/isa/header/templateblock/ERCOV/": "/zh/isa/header/templateblock/ERCOV/",
+ "/isa/header/templateblock/ESAVE/": "/zh/isa/header/templateblock/ESAVE/",
+ "/isa/header/templateblock/FENTRY/": "/zh/isa/header/templateblock/FENTRY/",
+ "/isa/header/templateblock/FEXIT/": "/zh/isa/header/templateblock/FEXIT/",
+ "/isa/header/templateblock/FRET.RA/": "/zh/isa/header/templateblock/FRET.RA/",
+ "/isa/header/templateblock/FRET.STK/": "/zh/isa/header/templateblock/FRET.STK/",
+ "/isa/header/templateblock/GETMSG/": "/zh/isa/header/templateblock/GETMSG/",
+ "/isa/header/templateblock/MCOPY.D/": "/zh/isa/header/templateblock/MCOPY.D/",
+ "/isa/header/templateblock/MCOPY/": "/zh/isa/header/templateblock/MCOPY/",
+ "/isa/header/templateblock/MSET/": "/zh/isa/header/templateblock/MSET/",
+ "/isa/header/templateblock/intro/": "/zh/isa/header/templateblock/intro/",
+ "/isa/header/tileblock/ACCCVT/": "/zh/isa/header/tileblock/ACCCVT/",
+ "/isa/header/tileblock/MGATHER/": "/zh/isa/header/tileblock/MGATHER/",
+ "/isa/header/tileblock/MSCATTER/": "/zh/isa/header/tileblock/MSCATTER/",
+ "/isa/header/tileblock/TABS/": "/zh/isa/header/tileblock/TABS/",
+ "/isa/header/tileblock/TADD/": "/zh/isa/header/tileblock/TADD/",
+ "/isa/header/tileblock/TADDC/": "/zh/isa/header/tileblock/TADDC/",
+ "/isa/header/tileblock/TADDS/": "/zh/isa/header/tileblock/TADDS/",
+ "/isa/header/tileblock/TADDSC/": "/zh/isa/header/tileblock/TADDSC/",
+ "/isa/header/tileblock/TAND/": "/zh/isa/header/tileblock/TAND/",
+ "/isa/header/tileblock/TANDS/": "/zh/isa/header/tileblock/TANDS/",
+ "/isa/header/tileblock/TCMP/": "/zh/isa/header/tileblock/TCMP/",
+ "/isa/header/tileblock/TCMPS/": "/zh/isa/header/tileblock/TCMPS/",
+ "/isa/header/tileblock/TCOLEXPAND/": "/zh/isa/header/tileblock/TCOLEXPAND/",
+ "/isa/header/tileblock/TCOLEXPANDADD/": "/zh/isa/header/tileblock/TCOLEXPANDADD/",
+ "/isa/header/tileblock/TCOLEXPANDDIV/": "/zh/isa/header/tileblock/TCOLEXPANDDIV/",
+ "/isa/header/tileblock/TCOLEXPANDEXPDIF/": "/zh/isa/header/tileblock/TCOLEXPANDEXPDIF/",
+ "/isa/header/tileblock/TCOLEXPANDMAX/": "/zh/isa/header/tileblock/TCOLEXPANDMAX/",
+ "/isa/header/tileblock/TCOLEXPANDMIN/": "/zh/isa/header/tileblock/TCOLEXPANDMIN/",
+ "/isa/header/tileblock/TCOLEXPANDMUL/": "/zh/isa/header/tileblock/TCOLEXPANDMUL/",
+ "/isa/header/tileblock/TCOLEXPANDSUB/": "/zh/isa/header/tileblock/TCOLEXPANDSUB/",
+ "/isa/header/tileblock/TCOLMAX/": "/zh/isa/header/tileblock/TCOLMAX/",
+ "/isa/header/tileblock/TCOLMIN/": "/zh/isa/header/tileblock/TCOLMIN/",
+ "/isa/header/tileblock/TCOLPROD/": "/zh/isa/header/tileblock/TCOLPROD/",
+ "/isa/header/tileblock/TCOLSUM/": "/zh/isa/header/tileblock/TCOLSUM/",
+ "/isa/header/tileblock/TCVT/": "/zh/isa/header/tileblock/TCVT/",
+ "/isa/header/tileblock/TDIV/": "/zh/isa/header/tileblock/TDIV/",
+ "/isa/header/tileblock/TDIVS/": "/zh/isa/header/tileblock/TDIVS/",
+ "/isa/header/tileblock/TEXP/": "/zh/isa/header/tileblock/TEXP/",
+ "/isa/header/tileblock/TEXPANDS/": "/zh/isa/header/tileblock/TEXPANDS/",
+ "/isa/header/tileblock/TFMOD/": "/zh/isa/header/tileblock/TFMOD/",
+ "/isa/header/tileblock/TFMODS/": "/zh/isa/header/tileblock/TFMODS/",
+ "/isa/header/tileblock/TGATHER/": "/zh/isa/header/tileblock/TGATHER/",
+ "/isa/header/tileblock/TGEMV.ACC/": "/zh/isa/header/tileblock/TGEMV.ACC/",
+ "/isa/header/tileblock/TGEMV.BIAS/": "/zh/isa/header/tileblock/TGEMV.BIAS/",
+ "/isa/header/tileblock/TGEMV/": "/zh/isa/header/tileblock/TGEMV/",
+ "/isa/header/tileblock/TGEMVMX.ACC/": "/zh/isa/header/tileblock/TGEMVMX.ACC/",
+ "/isa/header/tileblock/TGEMVMX.BIAS/": "/zh/isa/header/tileblock/TGEMVMX.BIAS/",
+ "/isa/header/tileblock/TGEMVMX/": "/zh/isa/header/tileblock/TGEMVMX/",
+ "/isa/header/tileblock/THISTOGRAM/": "/zh/isa/header/tileblock/THISTOGRAM/",
+ "/isa/header/tileblock/TLOAD/": "/zh/isa/header/tileblock/TLOAD/",
+ "/isa/header/tileblock/TLOG/": "/zh/isa/header/tileblock/TLOG/",
+ "/isa/header/tileblock/TLRELU/": "/zh/isa/header/tileblock/TLRELU/",
+ "/isa/header/tileblock/TMATMUL.ACC/": "/zh/isa/header/tileblock/TMATMUL.ACC/",
+ "/isa/header/tileblock/TMATMUL.BIAS/": "/zh/isa/header/tileblock/TMATMUL.BIAS/",
+ "/isa/header/tileblock/TMATMUL/": "/zh/isa/header/tileblock/TMATMUL/",
+ "/isa/header/tileblock/TMATMULMX.ACC/": "/zh/isa/header/tileblock/TMATMULMX.ACC/",
+ "/isa/header/tileblock/TMATMULMX.BIAS/": "/zh/isa/header/tileblock/TMATMULMX.BIAS/",
+ "/isa/header/tileblock/TMATMULMX/": "/zh/isa/header/tileblock/TMATMULMX/",
+ "/isa/header/tileblock/TMAX/": "/zh/isa/header/tileblock/TMAX/",
+ "/isa/header/tileblock/TMAXS/": "/zh/isa/header/tileblock/TMAXS/",
+ "/isa/header/tileblock/TMIN/": "/zh/isa/header/tileblock/TMIN/",
+ "/isa/header/tileblock/TMINS/": "/zh/isa/header/tileblock/TMINS/",
+ "/isa/header/tileblock/TMOV/": "/zh/isa/header/tileblock/TMOV/",
+ "/isa/header/tileblock/TMUL/": "/zh/isa/header/tileblock/TMUL/",
+ "/isa/header/tileblock/TMULS/": "/zh/isa/header/tileblock/TMULS/",
+ "/isa/header/tileblock/TNEG/": "/zh/isa/header/tileblock/TNEG/",
+ "/isa/header/tileblock/TNOT/": "/zh/isa/header/tileblock/TNOT/",
+ "/isa/header/tileblock/TOR/": "/zh/isa/header/tileblock/TOR/",
+ "/isa/header/tileblock/TORS/": "/zh/isa/header/tileblock/TORS/",
+ "/isa/header/tileblock/TPRELU/": "/zh/isa/header/tileblock/TPRELU/",
+ "/isa/header/tileblock/TRECIP/": "/zh/isa/header/tileblock/TRECIP/",
+ "/isa/header/tileblock/TRELU/": "/zh/isa/header/tileblock/TRELU/",
+ "/isa/header/tileblock/TREM/": "/zh/isa/header/tileblock/TREM/",
+ "/isa/header/tileblock/TREMS/": "/zh/isa/header/tileblock/TREMS/",
+ "/isa/header/tileblock/TROWEXPAND/": "/zh/isa/header/tileblock/TROWEXPAND/",
+ "/isa/header/tileblock/TROWEXPANDADD/": "/zh/isa/header/tileblock/TROWEXPANDADD/",
+ "/isa/header/tileblock/TROWEXPANDDIV/": "/zh/isa/header/tileblock/TROWEXPANDDIV/",
+ "/isa/header/tileblock/TROWEXPANDEXPDIF/": "/zh/isa/header/tileblock/TROWEXPANDEXPDIF/",
+ "/isa/header/tileblock/TROWEXPANDMAX/": "/zh/isa/header/tileblock/TROWEXPANDMAX/",
+ "/isa/header/tileblock/TROWEXPANDMIN/": "/zh/isa/header/tileblock/TROWEXPANDMIN/",
+ "/isa/header/tileblock/TROWEXPANDMUL/": "/zh/isa/header/tileblock/TROWEXPANDMUL/",
+ "/isa/header/tileblock/TROWEXPANDSUB/": "/zh/isa/header/tileblock/TROWEXPANDSUB/",
+ "/isa/header/tileblock/TROWMAX/": "/zh/isa/header/tileblock/TROWMAX/",
+ "/isa/header/tileblock/TROWMIN/": "/zh/isa/header/tileblock/TROWMIN/",
+ "/isa/header/tileblock/TROWPROD/": "/zh/isa/header/tileblock/TROWPROD/",
+ "/isa/header/tileblock/TROWSUM/": "/zh/isa/header/tileblock/TROWSUM/",
+ "/isa/header/tileblock/TRSQRT/": "/zh/isa/header/tileblock/TRSQRT/",
+ "/isa/header/tileblock/TSCATTER/": "/zh/isa/header/tileblock/TSCATTER/",
+ "/isa/header/tileblock/TSEL/": "/zh/isa/header/tileblock/TSEL/",
+ "/isa/header/tileblock/TSELS/": "/zh/isa/header/tileblock/TSELS/",
+ "/isa/header/tileblock/TSHL/": "/zh/isa/header/tileblock/TSHL/",
+ "/isa/header/tileblock/TSHLS/": "/zh/isa/header/tileblock/TSHLS/",
+ "/isa/header/tileblock/TSHR/": "/zh/isa/header/tileblock/TSHR/",
+ "/isa/header/tileblock/TSHRS/": "/zh/isa/header/tileblock/TSHRS/",
+ "/isa/header/tileblock/TSQRT/": "/zh/isa/header/tileblock/TSQRT/",
+ "/isa/header/tileblock/TSTORE/": "/zh/isa/header/tileblock/TSTORE/",
+ "/isa/header/tileblock/TSUB/": "/zh/isa/header/tileblock/TSUB/",
+ "/isa/header/tileblock/TSUBC/": "/zh/isa/header/tileblock/TSUBC/",
+ "/isa/header/tileblock/TSUBS/": "/zh/isa/header/tileblock/TSUBS/",
+ "/isa/header/tileblock/TSUBSC/": "/zh/isa/header/tileblock/TSUBSC/",
+ "/isa/header/tileblock/TTRANS/": "/zh/isa/header/tileblock/TTRANS/",
+ "/isa/header/tileblock/TXOR/": "/zh/isa/header/tileblock/TXOR/",
+ "/isa/header/tileblock/TXORS/": "/zh/isa/header/tileblock/TXORS/",
+ "/isa/header/tileblock/intro/": "/zh/isa/header/tileblock/intro/",
+ "/isa/inst/LibPseudoCode/": "/zh/isa/inst/LibPseudoCode/",
+ "/isa/inst/instrUsage/": "/zh/isa/inst/instrUsage/",
+ "/isa/inst/misa_c/C.ADD/": "/zh/isa/inst/misa_c/C.ADD/",
+ "/isa/inst/misa_c/C.ADDI/": "/zh/isa/inst/misa_c/C.ADDI/",
+ "/isa/inst/misa_c/C.AND/": "/zh/isa/inst/misa_c/C.AND/",
+ "/isa/inst/misa_c/C.CMP.EQI/": "/zh/isa/inst/misa_c/C.CMP.EQI/",
+ "/isa/inst/misa_c/C.CMP.NEI/": "/zh/isa/inst/misa_c/C.CMP.NEI/",
+ "/isa/inst/misa_c/C.EBREAK/": "/zh/isa/inst/misa_c/C.EBREAK/",
+ "/isa/inst/misa_c/C.LDI/": "/zh/isa/inst/misa_c/C.LDI/",
+ "/isa/inst/misa_c/C.LWI/": "/zh/isa/inst/misa_c/C.LWI/",
+ "/isa/inst/misa_c/C.MOVI/": "/zh/isa/inst/misa_c/C.MOVI/",
+ "/isa/inst/misa_c/C.MOVR/": "/zh/isa/inst/misa_c/C.MOVR/",
+ "/isa/inst/misa_c/C.OR/": "/zh/isa/inst/misa_c/C.OR/",
+ "/isa/inst/misa_c/C.SDI/": "/zh/isa/inst/misa_c/C.SDI/",
+ "/isa/inst/misa_c/C.SETC.EQ/": "/zh/isa/inst/misa_c/C.SETC.EQ/",
+ "/isa/inst/misa_c/C.SETC.NE/": "/zh/isa/inst/misa_c/C.SETC.NE/",
+ "/isa/inst/misa_c/C.SETC.TGT/": "/zh/isa/inst/misa_c/C.SETC.TGT/",
+ "/isa/inst/misa_c/C.SETRET/": "/zh/isa/inst/misa_c/C.SETRET/",
+ "/isa/inst/misa_c/C.SEXT.B/": "/zh/isa/inst/misa_c/C.SEXT.B/",
+ "/isa/inst/misa_c/C.SEXT.H/": "/zh/isa/inst/misa_c/C.SEXT.H/",
+ "/isa/inst/misa_c/C.SEXT.W/": "/zh/isa/inst/misa_c/C.SEXT.W/",
+ "/isa/inst/misa_c/C.SLLI/": "/zh/isa/inst/misa_c/C.SLLI/",
+ "/isa/inst/misa_c/C.SRLI/": "/zh/isa/inst/misa_c/C.SRLI/",
+ "/isa/inst/misa_c/C.SSRGET/": "/zh/isa/inst/misa_c/C.SSRGET/",
+ "/isa/inst/misa_c/C.SUB/": "/zh/isa/inst/misa_c/C.SUB/",
+ "/isa/inst/misa_c/C.SWI/": "/zh/isa/inst/misa_c/C.SWI/",
+ "/isa/inst/misa_c/C.ZEXT.B/": "/zh/isa/inst/misa_c/C.ZEXT.B/",
+ "/isa/inst/misa_c/C.ZEXT.H/": "/zh/isa/inst/misa_c/C.ZEXT.H/",
+ "/isa/inst/misa_c/C.ZEXT.W/": "/zh/isa/inst/misa_c/C.ZEXT.W/",
+ "/isa/inst/misa_f/FABS/": "/zh/isa/inst/misa_f/FABS/",
+ "/isa/inst/misa_f/FADD/": "/zh/isa/inst/misa_f/FADD/",
+ "/isa/inst/misa_f/FCVT/": "/zh/isa/inst/misa_f/FCVT/",
+ "/isa/inst/misa_f/FCVTA/": "/zh/isa/inst/misa_f/FCVTA/",
+ "/isa/inst/misa_f/FCVTM/": "/zh/isa/inst/misa_f/FCVTM/",
+ "/isa/inst/misa_f/FCVTN/": "/zh/isa/inst/misa_f/FCVTN/",
+ "/isa/inst/misa_f/FCVTP/": "/zh/isa/inst/misa_f/FCVTP/",
+ "/isa/inst/misa_f/FCVTZ/": "/zh/isa/inst/misa_f/FCVTZ/",
+ "/isa/inst/misa_f/FDIV/": "/zh/isa/inst/misa_f/FDIV/",
+ "/isa/inst/misa_f/FEQ/": "/zh/isa/inst/misa_f/FEQ/",
+ "/isa/inst/misa_f/FEQS/": "/zh/isa/inst/misa_f/FEQS/",
+ "/isa/inst/misa_f/FEXP/": "/zh/isa/inst/misa_f/FEXP/",
+ "/isa/inst/misa_f/FGE/": "/zh/isa/inst/misa_f/FGE/",
+ "/isa/inst/misa_f/FGES/": "/zh/isa/inst/misa_f/FGES/",
+ "/isa/inst/misa_f/FLT/": "/zh/isa/inst/misa_f/FLT/",
+ "/isa/inst/misa_f/FLTS/": "/zh/isa/inst/misa_f/FLTS/",
+ "/isa/inst/misa_f/FMADD/": "/zh/isa/inst/misa_f/FMADD/",
+ "/isa/inst/misa_f/FMAX/": "/zh/isa/inst/misa_f/FMAX/",
+ "/isa/inst/misa_f/FMIN/": "/zh/isa/inst/misa_f/FMIN/",
+ "/isa/inst/misa_f/FMSUB/": "/zh/isa/inst/misa_f/FMSUB/",
+ "/isa/inst/misa_f/FMUL/": "/zh/isa/inst/misa_f/FMUL/",
+ "/isa/inst/misa_f/FNE/": "/zh/isa/inst/misa_f/FNE/",
+ "/isa/inst/misa_f/FNES/": "/zh/isa/inst/misa_f/FNES/",
+ "/isa/inst/misa_f/FNMADD/": "/zh/isa/inst/misa_f/FNMADD/",
+ "/isa/inst/misa_f/FNMSUB/": "/zh/isa/inst/misa_f/FNMSUB/",
+ "/isa/inst/misa_f/FRECIP/": "/zh/isa/inst/misa_f/FRECIP/",
+ "/isa/inst/misa_f/FSQRT/": "/zh/isa/inst/misa_f/FSQRT/",
+ "/isa/inst/misa_f/FSUB/": "/zh/isa/inst/misa_f/FSUB/",
+ "/isa/inst/misa_f/MAX/": "/zh/isa/inst/misa_f/MAX/",
+ "/isa/inst/misa_f/MAXU/": "/zh/isa/inst/misa_f/MAXU/",
+ "/isa/inst/misa_f/MIN/": "/zh/isa/inst/misa_f/MIN/",
+ "/isa/inst/misa_f/MINU/": "/zh/isa/inst/misa_f/MINU/",
+ "/isa/inst/misa_f/SCVTF/": "/zh/isa/inst/misa_f/SCVTF/",
+ "/isa/inst/misa_f/UCVTF/": "/zh/isa/inst/misa_f/UCVTF/",
+ "/isa/inst/misa_g/ADD/": "/zh/isa/inst/misa_g/ADD/",
+ "/isa/inst/misa_g/ADDI/": "/zh/isa/inst/misa_g/ADDI/",
+ "/isa/inst/misa_g/ADDIW/": "/zh/isa/inst/misa_g/ADDIW/",
+ "/isa/inst/misa_g/ADDTPC/": "/zh/isa/inst/misa_g/ADDTPC/",
+ "/isa/inst/misa_g/ADDW/": "/zh/isa/inst/misa_g/ADDW/",
+ "/isa/inst/misa_g/AND/": "/zh/isa/inst/misa_g/AND/",
+ "/isa/inst/misa_g/ANDI/": "/zh/isa/inst/misa_g/ANDI/",
+ "/isa/inst/misa_g/ANDIW/": "/zh/isa/inst/misa_g/ANDIW/",
+ "/isa/inst/misa_g/ANDW/": "/zh/isa/inst/misa_g/ANDW/",
+ "/isa/inst/misa_g/B.EQ/": "/zh/isa/inst/misa_g/B.EQ/",
+ "/isa/inst/misa_g/B.GE/": "/zh/isa/inst/misa_g/B.GE/",
+ "/isa/inst/misa_g/B.GEU/": "/zh/isa/inst/misa_g/B.GEU/",
+ "/isa/inst/misa_g/B.LT/": "/zh/isa/inst/misa_g/B.LT/",
+ "/isa/inst/misa_g/B.LTU/": "/zh/isa/inst/misa_g/B.LTU/",
+ "/isa/inst/misa_g/B.NE/": "/zh/isa/inst/misa_g/B.NE/",
+ "/isa/inst/misa_g/B.NZ/": "/zh/isa/inst/misa_g/B.NZ/",
+ "/isa/inst/misa_g/B.Z/": "/zh/isa/inst/misa_g/B.Z/",
+ "/isa/inst/misa_g/BCNT/": "/zh/isa/inst/misa_g/BCNT/",
+ "/isa/inst/misa_g/BIC/": "/zh/isa/inst/misa_g/BIC/",
+ "/isa/inst/misa_g/BIS/": "/zh/isa/inst/misa_g/BIS/",
+ "/isa/inst/misa_g/BXS/": "/zh/isa/inst/misa_g/BXS/",
+ "/isa/inst/misa_g/BXU/": "/zh/isa/inst/misa_g/BXU/",
+ "/isa/inst/misa_g/CLZ/": "/zh/isa/inst/misa_g/CLZ/",
+ "/isa/inst/misa_g/CMP.AND/": "/zh/isa/inst/misa_g/CMP.AND/",
+ "/isa/inst/misa_g/CMP.ANDI/": "/zh/isa/inst/misa_g/CMP.ANDI/",
+ "/isa/inst/misa_g/CMP.EQ/": "/zh/isa/inst/misa_g/CMP.EQ/",
+ "/isa/inst/misa_g/CMP.EQI/": "/zh/isa/inst/misa_g/CMP.EQI/",
+ "/isa/inst/misa_g/CMP.GE/": "/zh/isa/inst/misa_g/CMP.GE/",
+ "/isa/inst/misa_g/CMP.GEI/": "/zh/isa/inst/misa_g/CMP.GEI/",
+ "/isa/inst/misa_g/CMP.GEU/": "/zh/isa/inst/misa_g/CMP.GEU/",
+ "/isa/inst/misa_g/CMP.GEUI/": "/zh/isa/inst/misa_g/CMP.GEUI/",
+ "/isa/inst/misa_g/CMP.LT/": "/zh/isa/inst/misa_g/CMP.LT/",
+ "/isa/inst/misa_g/CMP.LTI/": "/zh/isa/inst/misa_g/CMP.LTI/",
+ "/isa/inst/misa_g/CMP.LTU/": "/zh/isa/inst/misa_g/CMP.LTU/",
+ "/isa/inst/misa_g/CMP.LTUI/": "/zh/isa/inst/misa_g/CMP.LTUI/",
+ "/isa/inst/misa_g/CMP.NE/": "/zh/isa/inst/misa_g/CMP.NE/",
+ "/isa/inst/misa_g/CMP.NEI/": "/zh/isa/inst/misa_g/CMP.NEI/",
+ "/isa/inst/misa_g/CMP.OR/": "/zh/isa/inst/misa_g/CMP.OR/",
+ "/isa/inst/misa_g/CMP.ORI/": "/zh/isa/inst/misa_g/CMP.ORI/",
+ "/isa/inst/misa_g/CSEL/": "/zh/isa/inst/misa_g/CSEL/",
+ "/isa/inst/misa_g/CTZ/": "/zh/isa/inst/misa_g/CTZ/",
+ "/isa/inst/misa_g/DIV/": "/zh/isa/inst/misa_g/DIV/",
+ "/isa/inst/misa_g/DIVU/": "/zh/isa/inst/misa_g/DIVU/",
+ "/isa/inst/misa_g/DIVUW/": "/zh/isa/inst/misa_g/DIVUW/",
+ "/isa/inst/misa_g/DIVW/": "/zh/isa/inst/misa_g/DIVW/",
+ "/isa/inst/misa_g/J/": "/zh/isa/inst/misa_g/J/",
+ "/isa/inst/misa_g/JR/": "/zh/isa/inst/misa_g/JR/",
+ "/isa/inst/misa_g/LB.PCR/": "/zh/isa/inst/misa_g/LB.PCR/",
+ "/isa/inst/misa_g/LB/": "/zh/isa/inst/misa_g/LB/",
+ "/isa/inst/misa_g/LBI/": "/zh/isa/inst/misa_g/LBI/",
+ "/isa/inst/misa_g/LBU.PCR/": "/zh/isa/inst/misa_g/LBU.PCR/",
+ "/isa/inst/misa_g/LBU/": "/zh/isa/inst/misa_g/LBU/",
+ "/isa/inst/misa_g/LBUI/": "/zh/isa/inst/misa_g/LBUI/",
+ "/isa/inst/misa_g/LD.PCR/": "/zh/isa/inst/misa_g/LD.PCR/",
+ "/isa/inst/misa_g/LD/": "/zh/isa/inst/misa_g/LD/",
+ "/isa/inst/misa_g/LDI.U/": "/zh/isa/inst/misa_g/LDI.U/",
+ "/isa/inst/misa_g/LDI/": "/zh/isa/inst/misa_g/LDI/",
+ "/isa/inst/misa_g/LH.PCR/": "/zh/isa/inst/misa_g/LH.PCR/",
+ "/isa/inst/misa_g/LH/": "/zh/isa/inst/misa_g/LH/",
+ "/isa/inst/misa_g/LHI.U/": "/zh/isa/inst/misa_g/LHI.U/",
+ "/isa/inst/misa_g/LHI/": "/zh/isa/inst/misa_g/LHI/",
+ "/isa/inst/misa_g/LHU.PCR/": "/zh/isa/inst/misa_g/LHU.PCR/",
+ "/isa/inst/misa_g/LHU/": "/zh/isa/inst/misa_g/LHU/",
+ "/isa/inst/misa_g/LHUI.U/": "/zh/isa/inst/misa_g/LHUI.U/",
+ "/isa/inst/misa_g/LHUI/": "/zh/isa/inst/misa_g/LHUI/",
+ "/isa/inst/misa_g/LSRGET/": "/zh/isa/inst/misa_g/LSRGET/",
+ "/isa/inst/misa_g/LUI/": "/zh/isa/inst/misa_g/LUI/",
+ "/isa/inst/misa_g/LW.PCR/": "/zh/isa/inst/misa_g/LW.PCR/",
+ "/isa/inst/misa_g/LW/": "/zh/isa/inst/misa_g/LW/",
+ "/isa/inst/misa_g/LWI.U/": "/zh/isa/inst/misa_g/LWI.U/",
+ "/isa/inst/misa_g/LWI/": "/zh/isa/inst/misa_g/LWI/",
+ "/isa/inst/misa_g/LWU.PCR/": "/zh/isa/inst/misa_g/LWU.PCR/",
+ "/isa/inst/misa_g/LWU/": "/zh/isa/inst/misa_g/LWU/",
+ "/isa/inst/misa_g/LWUI.U/": "/zh/isa/inst/misa_g/LWUI.U/",
+ "/isa/inst/misa_g/LWUI/": "/zh/isa/inst/misa_g/LWUI/",
+ "/isa/inst/misa_g/MADD/": "/zh/isa/inst/misa_g/MADD/",
+ "/isa/inst/misa_g/MADDW/": "/zh/isa/inst/misa_g/MADDW/",
+ "/isa/inst/misa_g/MUL/": "/zh/isa/inst/misa_g/MUL/",
+ "/isa/inst/misa_g/MULU/": "/zh/isa/inst/misa_g/MULU/",
+ "/isa/inst/misa_g/MULUW/": "/zh/isa/inst/misa_g/MULUW/",
+ "/isa/inst/misa_g/MULW/": "/zh/isa/inst/misa_g/MULW/",
+ "/isa/inst/misa_g/OR/": "/zh/isa/inst/misa_g/OR/",
+ "/isa/inst/misa_g/ORI/": "/zh/isa/inst/misa_g/ORI/",
+ "/isa/inst/misa_g/ORIW/": "/zh/isa/inst/misa_g/ORIW/",
+ "/isa/inst/misa_g/ORW/": "/zh/isa/inst/misa_g/ORW/",
+ "/isa/inst/misa_g/REM/": "/zh/isa/inst/misa_g/REM/",
+ "/isa/inst/misa_g/REMU/": "/zh/isa/inst/misa_g/REMU/",
+ "/isa/inst/misa_g/REMUW/": "/zh/isa/inst/misa_g/REMUW/",
+ "/isa/inst/misa_g/REMW/": "/zh/isa/inst/misa_g/REMW/",
+ "/isa/inst/misa_g/REV/": "/zh/isa/inst/misa_g/REV/",
+ "/isa/inst/misa_g/SB.PCR/": "/zh/isa/inst/misa_g/SB.PCR/",
+ "/isa/inst/misa_g/SB/": "/zh/isa/inst/misa_g/SB/",
+ "/isa/inst/misa_g/SBI/": "/zh/isa/inst/misa_g/SBI/",
+ "/isa/inst/misa_g/SD.PCR/": "/zh/isa/inst/misa_g/SD.PCR/",
+ "/isa/inst/misa_g/SD.U/": "/zh/isa/inst/misa_g/SD.U/",
+ "/isa/inst/misa_g/SD/": "/zh/isa/inst/misa_g/SD/",
+ "/isa/inst/misa_g/SDI.U/": "/zh/isa/inst/misa_g/SDI.U/",
+ "/isa/inst/misa_g/SDI/": "/zh/isa/inst/misa_g/SDI/",
+ "/isa/inst/misa_g/SETC.AND/": "/zh/isa/inst/misa_g/SETC.AND/",
+ "/isa/inst/misa_g/SETC.ANDI/": "/zh/isa/inst/misa_g/SETC.ANDI/",
+ "/isa/inst/misa_g/SETC.EQ/": "/zh/isa/inst/misa_g/SETC.EQ/",
+ "/isa/inst/misa_g/SETC.EQI/": "/zh/isa/inst/misa_g/SETC.EQI/",
+ "/isa/inst/misa_g/SETC.GE/": "/zh/isa/inst/misa_g/SETC.GE/",
+ "/isa/inst/misa_g/SETC.GEI/": "/zh/isa/inst/misa_g/SETC.GEI/",
+ "/isa/inst/misa_g/SETC.GEU/": "/zh/isa/inst/misa_g/SETC.GEU/",
+ "/isa/inst/misa_g/SETC.GEUI/": "/zh/isa/inst/misa_g/SETC.GEUI/",
+ "/isa/inst/misa_g/SETC.LT/": "/zh/isa/inst/misa_g/SETC.LT/",
+ "/isa/inst/misa_g/SETC.LTI/": "/zh/isa/inst/misa_g/SETC.LTI/",
+ "/isa/inst/misa_g/SETC.LTU/": "/zh/isa/inst/misa_g/SETC.LTU/",
+ "/isa/inst/misa_g/SETC.LTUI/": "/zh/isa/inst/misa_g/SETC.LTUI/",
+ "/isa/inst/misa_g/SETC.NE/": "/zh/isa/inst/misa_g/SETC.NE/",
+ "/isa/inst/misa_g/SETC.NEI/": "/zh/isa/inst/misa_g/SETC.NEI/",
+ "/isa/inst/misa_g/SETC.OR/": "/zh/isa/inst/misa_g/SETC.OR/",
+ "/isa/inst/misa_g/SETC.ORI/": "/zh/isa/inst/misa_g/SETC.ORI/",
+ "/isa/inst/misa_g/SETC.TGT/": "/zh/isa/inst/misa_g/SETC.TGT/",
+ "/isa/inst/misa_g/SETRET/": "/zh/isa/inst/misa_g/SETRET/",
+ "/isa/inst/misa_g/SH.PCR/": "/zh/isa/inst/misa_g/SH.PCR/",
+ "/isa/inst/misa_g/SH.U/": "/zh/isa/inst/misa_g/SH.U/",
+ "/isa/inst/misa_g/SH/": "/zh/isa/inst/misa_g/SH/",
+ "/isa/inst/misa_g/SHI.U/": "/zh/isa/inst/misa_g/SHI.U/",
+ "/isa/inst/misa_g/SHI/": "/zh/isa/inst/misa_g/SHI/",
+ "/isa/inst/misa_g/SLL/": "/zh/isa/inst/misa_g/SLL/",
+ "/isa/inst/misa_g/SLLI/": "/zh/isa/inst/misa_g/SLLI/",
+ "/isa/inst/misa_g/SLLIW/": "/zh/isa/inst/misa_g/SLLIW/",
+ "/isa/inst/misa_g/SLLW/": "/zh/isa/inst/misa_g/SLLW/",
+ "/isa/inst/misa_g/SRA/": "/zh/isa/inst/misa_g/SRA/",
+ "/isa/inst/misa_g/SRAI/": "/zh/isa/inst/misa_g/SRAI/",
+ "/isa/inst/misa_g/SRAIW/": "/zh/isa/inst/misa_g/SRAIW/",
+ "/isa/inst/misa_g/SRAW/": "/zh/isa/inst/misa_g/SRAW/",
+ "/isa/inst/misa_g/SRL/": "/zh/isa/inst/misa_g/SRL/",
+ "/isa/inst/misa_g/SRLI/": "/zh/isa/inst/misa_g/SRLI/",
+ "/isa/inst/misa_g/SRLIW/": "/zh/isa/inst/misa_g/SRLIW/",
+ "/isa/inst/misa_g/SRLW/": "/zh/isa/inst/misa_g/SRLW/",
+ "/isa/inst/misa_g/SSRGET/": "/zh/isa/inst/misa_g/SSRGET/",
+ "/isa/inst/misa_g/SSRSET/": "/zh/isa/inst/misa_g/SSRSET/",
+ "/isa/inst/misa_g/SSRSWAP/": "/zh/isa/inst/misa_g/SSRSWAP/",
+ "/isa/inst/misa_g/SUB/": "/zh/isa/inst/misa_g/SUB/",
+ "/isa/inst/misa_g/SUBI/": "/zh/isa/inst/misa_g/SUBI/",
+ "/isa/inst/misa_g/SUBIW/": "/zh/isa/inst/misa_g/SUBIW/",
+ "/isa/inst/misa_g/SUBW/": "/zh/isa/inst/misa_g/SUBW/",
+ "/isa/inst/misa_g/SW.PCR/": "/zh/isa/inst/misa_g/SW.PCR/",
+ "/isa/inst/misa_g/SW.U/": "/zh/isa/inst/misa_g/SW.U/",
+ "/isa/inst/misa_g/SW/": "/zh/isa/inst/misa_g/SW/",
+ "/isa/inst/misa_g/SWI.U/": "/zh/isa/inst/misa_g/SWI.U/",
+ "/isa/inst/misa_g/SWI/": "/zh/isa/inst/misa_g/SWI/",
+ "/isa/inst/misa_g/XOR/": "/zh/isa/inst/misa_g/XOR/",
+ "/isa/inst/misa_g/XORI/": "/zh/isa/inst/misa_g/XORI/",
+ "/isa/inst/misa_g/XORIW/": "/zh/isa/inst/misa_g/XORIW/",
+ "/isa/inst/misa_g/XORW/": "/zh/isa/inst/misa_g/XORW/",
+ "/isa/inst/misa_h/HL.ADDI/": "/zh/isa/inst/misa_h/HL.ADDI/",
+ "/isa/inst/misa_h/HL.ADDIW/": "/zh/isa/inst/misa_h/HL.ADDIW/",
+ "/isa/inst/misa_h/HL.ADDTPC/": "/zh/isa/inst/misa_h/HL.ADDTPC/",
+ "/isa/inst/misa_h/HL.ANDI/": "/zh/isa/inst/misa_h/HL.ANDI/",
+ "/isa/inst/misa_h/HL.ANDIW/": "/zh/isa/inst/misa_h/HL.ANDIW/",
+ "/isa/inst/misa_h/HL.BFI/": "/zh/isa/inst/misa_h/HL.BFI/",
+ "/isa/inst/misa_h/HL.CASB/": "/zh/isa/inst/misa_h/HL.CASB/",
+ "/isa/inst/misa_h/HL.CASD/": "/zh/isa/inst/misa_h/HL.CASD/",
+ "/isa/inst/misa_h/HL.CASH/": "/zh/isa/inst/misa_h/HL.CASH/",
+ "/isa/inst/misa_h/HL.CASW/": "/zh/isa/inst/misa_h/HL.CASW/",
+ "/isa/inst/misa_h/HL.CCAT/": "/zh/isa/inst/misa_h/HL.CCAT/",
+ "/isa/inst/misa_h/HL.CCATW/": "/zh/isa/inst/misa_h/HL.CCATW/",
+ "/isa/inst/misa_h/HL.CMP.ANDI/": "/zh/isa/inst/misa_h/HL.CMP.ANDI/",
+ "/isa/inst/misa_h/HL.CMP.EQI/": "/zh/isa/inst/misa_h/HL.CMP.EQI/",
+ "/isa/inst/misa_h/HL.CMP.GEI/": "/zh/isa/inst/misa_h/HL.CMP.GEI/",
+ "/isa/inst/misa_h/HL.CMP.GEUI/": "/zh/isa/inst/misa_h/HL.CMP.GEUI/",
+ "/isa/inst/misa_h/HL.CMP.LTI/": "/zh/isa/inst/misa_h/HL.CMP.LTI/",
+ "/isa/inst/misa_h/HL.CMP.LTUI/": "/zh/isa/inst/misa_h/HL.CMP.LTUI/",
+ "/isa/inst/misa_h/HL.CMP.NEI/": "/zh/isa/inst/misa_h/HL.CMP.NEI/",
+ "/isa/inst/misa_h/HL.CMP.ORI/": "/zh/isa/inst/misa_h/HL.CMP.ORI/",
+ "/isa/inst/misa_h/HL.DIV/": "/zh/isa/inst/misa_h/HL.DIV/",
+ "/isa/inst/misa_h/HL.DIVU/": "/zh/isa/inst/misa_h/HL.DIVU/",
+ "/isa/inst/misa_h/HL.DIVUW/": "/zh/isa/inst/misa_h/HL.DIVUW/",
+ "/isa/inst/misa_h/HL.DIVW/": "/zh/isa/inst/misa_h/HL.DIVW/",
+ "/isa/inst/misa_h/HL.LB.PCR/": "/zh/isa/inst/misa_h/HL.LB.PCR/",
+ "/isa/inst/misa_h/HL.LB.PO/": "/zh/isa/inst/misa_h/HL.LB.PO/",
+ "/isa/inst/misa_h/HL.LB.PR/": "/zh/isa/inst/misa_h/HL.LB.PR/",
+ "/isa/inst/misa_h/HL.LBI.PO/": "/zh/isa/inst/misa_h/HL.LBI.PO/",
+ "/isa/inst/misa_h/HL.LBI.PR/": "/zh/isa/inst/misa_h/HL.LBI.PR/",
+ "/isa/inst/misa_h/HL.LBI/": "/zh/isa/inst/misa_h/HL.LBI/",
+ "/isa/inst/misa_h/HL.LBIP/": "/zh/isa/inst/misa_h/HL.LBIP/",
+ "/isa/inst/misa_h/HL.LBP/": "/zh/isa/inst/misa_h/HL.LBP/",
+ "/isa/inst/misa_h/HL.LBU.PCR/": "/zh/isa/inst/misa_h/HL.LBU.PCR/",
+ "/isa/inst/misa_h/HL.LBU.PO/": "/zh/isa/inst/misa_h/HL.LBU.PO/",
+ "/isa/inst/misa_h/HL.LBU.PR/": "/zh/isa/inst/misa_h/HL.LBU.PR/",
+ "/isa/inst/misa_h/HL.LBUI.PO/": "/zh/isa/inst/misa_h/HL.LBUI.PO/",
+ "/isa/inst/misa_h/HL.LBUI.PR/": "/zh/isa/inst/misa_h/HL.LBUI.PR/",
+ "/isa/inst/misa_h/HL.LBUI/": "/zh/isa/inst/misa_h/HL.LBUI/",
+ "/isa/inst/misa_h/HL.LBUIP/": "/zh/isa/inst/misa_h/HL.LBUIP/",
+ "/isa/inst/misa_h/HL.LBUP/": "/zh/isa/inst/misa_h/HL.LBUP/",
+ "/isa/inst/misa_h/HL.LD.PCR/": "/zh/isa/inst/misa_h/HL.LD.PCR/",
+ "/isa/inst/misa_h/HL.LD.PO/": "/zh/isa/inst/misa_h/HL.LD.PO/",
+ "/isa/inst/misa_h/HL.LD.PR/": "/zh/isa/inst/misa_h/HL.LD.PR/",
+ "/isa/inst/misa_h/HL.LDI.PO/": "/zh/isa/inst/misa_h/HL.LDI.PO/",
+ "/isa/inst/misa_h/HL.LDI.PR/": "/zh/isa/inst/misa_h/HL.LDI.PR/",
+ "/isa/inst/misa_h/HL.LDI.U/": "/zh/isa/inst/misa_h/HL.LDI.U/",
+ "/isa/inst/misa_h/HL.LDI.UPO/": "/zh/isa/inst/misa_h/HL.LDI.UPO/",
+ "/isa/inst/misa_h/HL.LDI.UPR/": "/zh/isa/inst/misa_h/HL.LDI.UPR/",
+ "/isa/inst/misa_h/HL.LDI/": "/zh/isa/inst/misa_h/HL.LDI/",
+ "/isa/inst/misa_h/HL.LDIP.U/": "/zh/isa/inst/misa_h/HL.LDIP.U/",
+ "/isa/inst/misa_h/HL.LDIP/": "/zh/isa/inst/misa_h/HL.LDIP/",
+ "/isa/inst/misa_h/HL.LDP/": "/zh/isa/inst/misa_h/HL.LDP/",
+ "/isa/inst/misa_h/HL.LH.PCR/": "/zh/isa/inst/misa_h/HL.LH.PCR/",
+ "/isa/inst/misa_h/HL.LH.PO/": "/zh/isa/inst/misa_h/HL.LH.PO/",
+ "/isa/inst/misa_h/HL.LH.PR/": "/zh/isa/inst/misa_h/HL.LH.PR/",
+ "/isa/inst/misa_h/HL.LHI.PO/": "/zh/isa/inst/misa_h/HL.LHI.PO/",
+ "/isa/inst/misa_h/HL.LHI.PR/": "/zh/isa/inst/misa_h/HL.LHI.PR/",
+ "/isa/inst/misa_h/HL.LHI.U/": "/zh/isa/inst/misa_h/HL.LHI.U/",
+ "/isa/inst/misa_h/HL.LHI.UPO/": "/zh/isa/inst/misa_h/HL.LHI.UPO/",
+ "/isa/inst/misa_h/HL.LHI.UPR/": "/zh/isa/inst/misa_h/HL.LHI.UPR/",
+ "/isa/inst/misa_h/HL.LHI/": "/zh/isa/inst/misa_h/HL.LHI/",
+ "/isa/inst/misa_h/HL.LHIP.U/": "/zh/isa/inst/misa_h/HL.LHIP.U/",
+ "/isa/inst/misa_h/HL.LHIP/": "/zh/isa/inst/misa_h/HL.LHIP/",
+ "/isa/inst/misa_h/HL.LHP/": "/zh/isa/inst/misa_h/HL.LHP/",
+ "/isa/inst/misa_h/HL.LHU.PCR/": "/zh/isa/inst/misa_h/HL.LHU.PCR/",
+ "/isa/inst/misa_h/HL.LHU.PO/": "/zh/isa/inst/misa_h/HL.LHU.PO/",
+ "/isa/inst/misa_h/HL.LHU.PR/": "/zh/isa/inst/misa_h/HL.LHU.PR/",
+ "/isa/inst/misa_h/HL.LHUI.PO/": "/zh/isa/inst/misa_h/HL.LHUI.PO/",
+ "/isa/inst/misa_h/HL.LHUI.PR/": "/zh/isa/inst/misa_h/HL.LHUI.PR/",
+ "/isa/inst/misa_h/HL.LHUI.U/": "/zh/isa/inst/misa_h/HL.LHUI.U/",
+ "/isa/inst/misa_h/HL.LHUI.UPO/": "/zh/isa/inst/misa_h/HL.LHUI.UPO/",
+ "/isa/inst/misa_h/HL.LHUI.UPR/": "/zh/isa/inst/misa_h/HL.LHUI.UPR/",
+ "/isa/inst/misa_h/HL.LHUI/": "/zh/isa/inst/misa_h/HL.LHUI/",
+ "/isa/inst/misa_h/HL.LHUIP.U/": "/zh/isa/inst/misa_h/HL.LHUIP.U/",
+ "/isa/inst/misa_h/HL.LHUIP/": "/zh/isa/inst/misa_h/HL.LHUIP/",
+ "/isa/inst/misa_h/HL.LHUP/": "/zh/isa/inst/misa_h/HL.LHUP/",
+ "/isa/inst/misa_h/HL.LIS/": "/zh/isa/inst/misa_h/HL.LIS/",
+ "/isa/inst/misa_h/HL.LIU/": "/zh/isa/inst/misa_h/HL.LIU/",
+ "/isa/inst/misa_h/HL.LUI/": "/zh/isa/inst/misa_h/HL.LUI/",
+ "/isa/inst/misa_h/HL.LW.PCR/": "/zh/isa/inst/misa_h/HL.LW.PCR/",
+ "/isa/inst/misa_h/HL.LW.PO/": "/zh/isa/inst/misa_h/HL.LW.PO/",
+ "/isa/inst/misa_h/HL.LW.PR/": "/zh/isa/inst/misa_h/HL.LW.PR/",
+ "/isa/inst/misa_h/HL.LWI.PO/": "/zh/isa/inst/misa_h/HL.LWI.PO/",
+ "/isa/inst/misa_h/HL.LWI.PR/": "/zh/isa/inst/misa_h/HL.LWI.PR/",
+ "/isa/inst/misa_h/HL.LWI.U/": "/zh/isa/inst/misa_h/HL.LWI.U/",
+ "/isa/inst/misa_h/HL.LWI.UPO/": "/zh/isa/inst/misa_h/HL.LWI.UPO/",
+ "/isa/inst/misa_h/HL.LWI.UPR/": "/zh/isa/inst/misa_h/HL.LWI.UPR/",
+ "/isa/inst/misa_h/HL.LWI/": "/zh/isa/inst/misa_h/HL.LWI/",
+ "/isa/inst/misa_h/HL.LWIP.U/": "/zh/isa/inst/misa_h/HL.LWIP.U/",
+ "/isa/inst/misa_h/HL.LWIP/": "/zh/isa/inst/misa_h/HL.LWIP/",
+ "/isa/inst/misa_h/HL.LWP/": "/zh/isa/inst/misa_h/HL.LWP/",
+ "/isa/inst/misa_h/HL.LWU.PCR/": "/zh/isa/inst/misa_h/HL.LWU.PCR/",
+ "/isa/inst/misa_h/HL.LWU.PO/": "/zh/isa/inst/misa_h/HL.LWU.PO/",
+ "/isa/inst/misa_h/HL.LWU.PR/": "/zh/isa/inst/misa_h/HL.LWU.PR/",
+ "/isa/inst/misa_h/HL.LWUI.PO/": "/zh/isa/inst/misa_h/HL.LWUI.PO/",
+ "/isa/inst/misa_h/HL.LWUI.PR/": "/zh/isa/inst/misa_h/HL.LWUI.PR/",
+ "/isa/inst/misa_h/HL.LWUI.U/": "/zh/isa/inst/misa_h/HL.LWUI.U/",
+ "/isa/inst/misa_h/HL.LWUI.UPO/": "/zh/isa/inst/misa_h/HL.LWUI.UPO/",
+ "/isa/inst/misa_h/HL.LWUI.UPR/": "/zh/isa/inst/misa_h/HL.LWUI.UPR/",
+ "/isa/inst/misa_h/HL.LWUI/": "/zh/isa/inst/misa_h/HL.LWUI/",
+ "/isa/inst/misa_h/HL.LWUIP.U/": "/zh/isa/inst/misa_h/HL.LWUIP.U/",
+ "/isa/inst/misa_h/HL.LWUIP/": "/zh/isa/inst/misa_h/HL.LWUIP/",
+ "/isa/inst/misa_h/HL.LWUP/": "/zh/isa/inst/misa_h/HL.LWUP/",
+ "/isa/inst/misa_h/HL.MADD/": "/zh/isa/inst/misa_h/HL.MADD/",
+ "/isa/inst/misa_h/HL.MADDW/": "/zh/isa/inst/misa_h/HL.MADDW/",
+ "/isa/inst/misa_h/HL.MIADD/": "/zh/isa/inst/misa_h/HL.MIADD/",
+ "/isa/inst/misa_h/HL.MISUB/": "/zh/isa/inst/misa_h/HL.MISUB/",
+ "/isa/inst/misa_h/HL.MUL/": "/zh/isa/inst/misa_h/HL.MUL/",
+ "/isa/inst/misa_h/HL.MULU/": "/zh/isa/inst/misa_h/HL.MULU/",
+ "/isa/inst/misa_h/HL.ORI/": "/zh/isa/inst/misa_h/HL.ORI/",
+ "/isa/inst/misa_h/HL.ORIW/": "/zh/isa/inst/misa_h/HL.ORIW/",
+ "/isa/inst/misa_h/HL.PRF.A/": "/zh/isa/inst/misa_h/HL.PRF.A/",
+ "/isa/inst/misa_h/HL.PRF/": "/zh/isa/inst/misa_h/HL.PRF/",
+ "/isa/inst/misa_h/HL.PRFI.U/": "/zh/isa/inst/misa_h/HL.PRFI.U/",
+ "/isa/inst/misa_h/HL.PRFI.UA/": "/zh/isa/inst/misa_h/HL.PRFI.UA/",
+ "/isa/inst/misa_h/HL.QMT/": "/zh/isa/inst/misa_h/HL.QMT/",
+ "/isa/inst/misa_h/HL.QPOP/": "/zh/isa/inst/misa_h/HL.QPOP/",
+ "/isa/inst/misa_h/HL.QPUSH/": "/zh/isa/inst/misa_h/HL.QPUSH/",
+ "/isa/inst/misa_h/HL.REM/": "/zh/isa/inst/misa_h/HL.REM/",
+ "/isa/inst/misa_h/HL.REMU/": "/zh/isa/inst/misa_h/HL.REMU/",
+ "/isa/inst/misa_h/HL.REMUW/": "/zh/isa/inst/misa_h/HL.REMUW/",
+ "/isa/inst/misa_h/HL.REMW/": "/zh/isa/inst/misa_h/HL.REMW/",
+ "/isa/inst/misa_h/HL.SB.PCR/": "/zh/isa/inst/misa_h/HL.SB.PCR/",
+ "/isa/inst/misa_h/HL.SB.PO/": "/zh/isa/inst/misa_h/HL.SB.PO/",
+ "/isa/inst/misa_h/HL.SB.PR/": "/zh/isa/inst/misa_h/HL.SB.PR/",
+ "/isa/inst/misa_h/HL.SBI.PO/": "/zh/isa/inst/misa_h/HL.SBI.PO/",
+ "/isa/inst/misa_h/HL.SBI.PR/": "/zh/isa/inst/misa_h/HL.SBI.PR/",
+ "/isa/inst/misa_h/HL.SBI/": "/zh/isa/inst/misa_h/HL.SBI/",
+ "/isa/inst/misa_h/HL.SBIP/": "/zh/isa/inst/misa_h/HL.SBIP/",
+ "/isa/inst/misa_h/HL.SBP/": "/zh/isa/inst/misa_h/HL.SBP/",
+ "/isa/inst/misa_h/HL.SD.PCR/": "/zh/isa/inst/misa_h/HL.SD.PCR/",
+ "/isa/inst/misa_h/HL.SD.PO/": "/zh/isa/inst/misa_h/HL.SD.PO/",
+ "/isa/inst/misa_h/HL.SD.PR/": "/zh/isa/inst/misa_h/HL.SD.PR/",
+ "/isa/inst/misa_h/HL.SD.UPO/": "/zh/isa/inst/misa_h/HL.SD.UPO/",
+ "/isa/inst/misa_h/HL.SD.UPR/": "/zh/isa/inst/misa_h/HL.SD.UPR/",
+ "/isa/inst/misa_h/HL.SDI.PO/": "/zh/isa/inst/misa_h/HL.SDI.PO/",
+ "/isa/inst/misa_h/HL.SDI.PR/": "/zh/isa/inst/misa_h/HL.SDI.PR/",
+ "/isa/inst/misa_h/HL.SDI.U/": "/zh/isa/inst/misa_h/HL.SDI.U/",
+ "/isa/inst/misa_h/HL.SDI.UPO/": "/zh/isa/inst/misa_h/HL.SDI.UPO/",
+ "/isa/inst/misa_h/HL.SDI.UPR/": "/zh/isa/inst/misa_h/HL.SDI.UPR/",
+ "/isa/inst/misa_h/HL.SDI/": "/zh/isa/inst/misa_h/HL.SDI/",
+ "/isa/inst/misa_h/HL.SDIP.U/": "/zh/isa/inst/misa_h/HL.SDIP.U/",
+ "/isa/inst/misa_h/HL.SDIP/": "/zh/isa/inst/misa_h/HL.SDIP/",
+ "/isa/inst/misa_h/HL.SDP.U/": "/zh/isa/inst/misa_h/HL.SDP.U/",
+ "/isa/inst/misa_h/HL.SDP/": "/zh/isa/inst/misa_h/HL.SDP/",
+ "/isa/inst/misa_h/HL.SETC.ANDI/": "/zh/isa/inst/misa_h/HL.SETC.ANDI/",
+ "/isa/inst/misa_h/HL.SETC.EQI/": "/zh/isa/inst/misa_h/HL.SETC.EQI/",
+ "/isa/inst/misa_h/HL.SETC.GEI/": "/zh/isa/inst/misa_h/HL.SETC.GEI/",
+ "/isa/inst/misa_h/HL.SETC.GEUI/": "/zh/isa/inst/misa_h/HL.SETC.GEUI/",
+ "/isa/inst/misa_h/HL.SETC.LTI/": "/zh/isa/inst/misa_h/HL.SETC.LTI/",
+ "/isa/inst/misa_h/HL.SETC.LTUI/": "/zh/isa/inst/misa_h/HL.SETC.LTUI/",
+ "/isa/inst/misa_h/HL.SETC.NEI/": "/zh/isa/inst/misa_h/HL.SETC.NEI/",
+ "/isa/inst/misa_h/HL.SETC.ORI/": "/zh/isa/inst/misa_h/HL.SETC.ORI/",
+ "/isa/inst/misa_h/HL.SETRET/": "/zh/isa/inst/misa_h/HL.SETRET/",
+ "/isa/inst/misa_h/HL.SH.PCR/": "/zh/isa/inst/misa_h/HL.SH.PCR/",
+ "/isa/inst/misa_h/HL.SH.PO/": "/zh/isa/inst/misa_h/HL.SH.PO/",
+ "/isa/inst/misa_h/HL.SH.PR/": "/zh/isa/inst/misa_h/HL.SH.PR/",
+ "/isa/inst/misa_h/HL.SH.UPO/": "/zh/isa/inst/misa_h/HL.SH.UPO/",
+ "/isa/inst/misa_h/HL.SH.UPR/": "/zh/isa/inst/misa_h/HL.SH.UPR/",
+ "/isa/inst/misa_h/HL.SHI.PO/": "/zh/isa/inst/misa_h/HL.SHI.PO/",
+ "/isa/inst/misa_h/HL.SHI.PR/": "/zh/isa/inst/misa_h/HL.SHI.PR/",
+ "/isa/inst/misa_h/HL.SHI.U/": "/zh/isa/inst/misa_h/HL.SHI.U/",
+ "/isa/inst/misa_h/HL.SHI.UPO/": "/zh/isa/inst/misa_h/HL.SHI.UPO/",
+ "/isa/inst/misa_h/HL.SHI.UPR/": "/zh/isa/inst/misa_h/HL.SHI.UPR/",
+ "/isa/inst/misa_h/HL.SHI/": "/zh/isa/inst/misa_h/HL.SHI/",
+ "/isa/inst/misa_h/HL.SHIP.U/": "/zh/isa/inst/misa_h/HL.SHIP.U/",
+ "/isa/inst/misa_h/HL.SHIP/": "/zh/isa/inst/misa_h/HL.SHIP/",
+ "/isa/inst/misa_h/HL.SHP.U/": "/zh/isa/inst/misa_h/HL.SHP.U/",
+ "/isa/inst/misa_h/HL.SHP/": "/zh/isa/inst/misa_h/HL.SHP/",
+ "/isa/inst/misa_h/HL.SSRGET/": "/zh/isa/inst/misa_h/HL.SSRGET/",
+ "/isa/inst/misa_h/HL.SSRSET/": "/zh/isa/inst/misa_h/HL.SSRSET/",
+ "/isa/inst/misa_h/HL.SUBI/": "/zh/isa/inst/misa_h/HL.SUBI/",
+ "/isa/inst/misa_h/HL.SUBIW/": "/zh/isa/inst/misa_h/HL.SUBIW/",
+ "/isa/inst/misa_h/HL.SW.PCR/": "/zh/isa/inst/misa_h/HL.SW.PCR/",
+ "/isa/inst/misa_h/HL.SW.PO/": "/zh/isa/inst/misa_h/HL.SW.PO/",
+ "/isa/inst/misa_h/HL.SW.PR/": "/zh/isa/inst/misa_h/HL.SW.PR/",
+ "/isa/inst/misa_h/HL.SW.UPO/": "/zh/isa/inst/misa_h/HL.SW.UPO/",
+ "/isa/inst/misa_h/HL.SW.UPR/": "/zh/isa/inst/misa_h/HL.SW.UPR/",
+ "/isa/inst/misa_h/HL.SWI.PO/": "/zh/isa/inst/misa_h/HL.SWI.PO/",
+ "/isa/inst/misa_h/HL.SWI.PR/": "/zh/isa/inst/misa_h/HL.SWI.PR/",
+ "/isa/inst/misa_h/HL.SWI.U/": "/zh/isa/inst/misa_h/HL.SWI.U/",
+ "/isa/inst/misa_h/HL.SWI.UPO/": "/zh/isa/inst/misa_h/HL.SWI.UPO/",
+ "/isa/inst/misa_h/HL.SWI.UPR/": "/zh/isa/inst/misa_h/HL.SWI.UPR/",
+ "/isa/inst/misa_h/HL.SWI/": "/zh/isa/inst/misa_h/HL.SWI/",
+ "/isa/inst/misa_h/HL.SWIP.U/": "/zh/isa/inst/misa_h/HL.SWIP.U/",
+ "/isa/inst/misa_h/HL.SWIP/": "/zh/isa/inst/misa_h/HL.SWIP/",
+ "/isa/inst/misa_h/HL.SWP.U/": "/zh/isa/inst/misa_h/HL.SWP.U/",
+ "/isa/inst/misa_h/HL.SWP/": "/zh/isa/inst/misa_h/HL.SWP/",
+ "/isa/inst/misa_h/HL.XORI/": "/zh/isa/inst/misa_h/HL.XORI/",
+ "/isa/inst/misa_h/HL.XORIW/": "/zh/isa/inst/misa_h/HL.XORIW/",
+ "/isa/inst/misa_l/L.ADD/": "/zh/isa/inst/misa_l/L.ADD/",
+ "/isa/inst/misa_l/L.ADDI/": "/zh/isa/inst/misa_l/L.ADDI/",
+ "/isa/inst/misa_l/L.ADDLI/": "/zh/isa/inst/misa_l/L.ADDLI/",
+ "/isa/inst/misa_l/L.AND/": "/zh/isa/inst/misa_l/L.AND/",
+ "/isa/inst/misa_l/L.ANDI/": "/zh/isa/inst/misa_l/L.ANDI/",
+ "/isa/inst/misa_l/L.BCNT/": "/zh/isa/inst/misa_l/L.BCNT/",
+ "/isa/inst/misa_l/L.BIC/": "/zh/isa/inst/misa_l/L.BIC/",
+ "/isa/inst/misa_l/L.BIS/": "/zh/isa/inst/misa_l/L.BIS/",
+ "/isa/inst/misa_l/L.BXS/": "/zh/isa/inst/misa_l/L.BXS/",
+ "/isa/inst/misa_l/L.BXU/": "/zh/isa/inst/misa_l/L.BXU/",
+ "/isa/inst/misa_l/L.CASBP/": "/zh/isa/inst/misa_l/L.CASBP/",
+ "/isa/inst/misa_l/L.CASDP/": "/zh/isa/inst/misa_l/L.CASDP/",
+ "/isa/inst/misa_l/L.CASHP/": "/zh/isa/inst/misa_l/L.CASHP/",
+ "/isa/inst/misa_l/L.CASWP/": "/zh/isa/inst/misa_l/L.CASWP/",
+ "/isa/inst/misa_l/L.CLZ/": "/zh/isa/inst/misa_l/L.CLZ/",
+ "/isa/inst/misa_l/L.CMP.AND/": "/zh/isa/inst/misa_l/L.CMP.AND/",
+ "/isa/inst/misa_l/L.CMP.ANDI/": "/zh/isa/inst/misa_l/L.CMP.ANDI/",
+ "/isa/inst/misa_l/L.CMP.EQ/": "/zh/isa/inst/misa_l/L.CMP.EQ/",
+ "/isa/inst/misa_l/L.CMP.EQI/": "/zh/isa/inst/misa_l/L.CMP.EQI/",
+ "/isa/inst/misa_l/L.CMP.GE/": "/zh/isa/inst/misa_l/L.CMP.GE/",
+ "/isa/inst/misa_l/L.CMP.GEI/": "/zh/isa/inst/misa_l/L.CMP.GEI/",
+ "/isa/inst/misa_l/L.CMP.GEU/": "/zh/isa/inst/misa_l/L.CMP.GEU/",
+ "/isa/inst/misa_l/L.CMP.GEUI/": "/zh/isa/inst/misa_l/L.CMP.GEUI/",
+ "/isa/inst/misa_l/L.CMP.LT/": "/zh/isa/inst/misa_l/L.CMP.LT/",
+ "/isa/inst/misa_l/L.CMP.LTI/": "/zh/isa/inst/misa_l/L.CMP.LTI/",
+ "/isa/inst/misa_l/L.CMP.LTU/": "/zh/isa/inst/misa_l/L.CMP.LTU/",
+ "/isa/inst/misa_l/L.CMP.LTUI/": "/zh/isa/inst/misa_l/L.CMP.LTUI/",
+ "/isa/inst/misa_l/L.CMP.NE/": "/zh/isa/inst/misa_l/L.CMP.NE/",
+ "/isa/inst/misa_l/L.CMP.NEI/": "/zh/isa/inst/misa_l/L.CMP.NEI/",
+ "/isa/inst/misa_l/L.CMP.OR/": "/zh/isa/inst/misa_l/L.CMP.OR/",
+ "/isa/inst/misa_l/L.CMP.ORI/": "/zh/isa/inst/misa_l/L.CMP.ORI/",
+ "/isa/inst/misa_l/L.CSEL/": "/zh/isa/inst/misa_l/L.CSEL/",
+ "/isa/inst/misa_l/L.CTZ/": "/zh/isa/inst/misa_l/L.CTZ/",
+ "/isa/inst/misa_l/L.DIV/": "/zh/isa/inst/misa_l/L.DIV/",
+ "/isa/inst/misa_l/L.FABS/": "/zh/isa/inst/misa_l/L.FABS/",
+ "/isa/inst/misa_l/L.FADD/": "/zh/isa/inst/misa_l/L.FADD/",
+ "/isa/inst/misa_l/L.FCLASS/": "/zh/isa/inst/misa_l/L.FCLASS/",
+ "/isa/inst/misa_l/L.FCVT/": "/zh/isa/inst/misa_l/L.FCVT/",
+ "/isa/inst/misa_l/L.FCVTI/": "/zh/isa/inst/misa_l/L.FCVTI/",
+ "/isa/inst/misa_l/L.FDIV/": "/zh/isa/inst/misa_l/L.FDIV/",
+ "/isa/inst/misa_l/L.FEQ/": "/zh/isa/inst/misa_l/L.FEQ/",
+ "/isa/inst/misa_l/L.FEQS/": "/zh/isa/inst/misa_l/L.FEQS/",
+ "/isa/inst/misa_l/L.FEXP/": "/zh/isa/inst/misa_l/L.FEXP/",
+ "/isa/inst/misa_l/L.FGE/": "/zh/isa/inst/misa_l/L.FGE/",
+ "/isa/inst/misa_l/L.FGES/": "/zh/isa/inst/misa_l/L.FGES/",
+ "/isa/inst/misa_l/L.FLT/": "/zh/isa/inst/misa_l/L.FLT/",
+ "/isa/inst/misa_l/L.FLTS/": "/zh/isa/inst/misa_l/L.FLTS/",
+ "/isa/inst/misa_l/L.FMADD/": "/zh/isa/inst/misa_l/L.FMADD/",
+ "/isa/inst/misa_l/L.FMAX/": "/zh/isa/inst/misa_l/L.FMAX/",
+ "/isa/inst/misa_l/L.FMIN/": "/zh/isa/inst/misa_l/L.FMIN/",
+ "/isa/inst/misa_l/L.FMSUB/": "/zh/isa/inst/misa_l/L.FMSUB/",
+ "/isa/inst/misa_l/L.FMUL/": "/zh/isa/inst/misa_l/L.FMUL/",
+ "/isa/inst/misa_l/L.FNE/": "/zh/isa/inst/misa_l/L.FNE/",
+ "/isa/inst/misa_l/L.FNES/": "/zh/isa/inst/misa_l/L.FNES/",
+ "/isa/inst/misa_l/L.FNMADD/": "/zh/isa/inst/misa_l/L.FNMADD/",
+ "/isa/inst/misa_l/L.FNMSUB/": "/zh/isa/inst/misa_l/L.FNMSUB/",
+ "/isa/inst/misa_l/L.FRECIP/": "/zh/isa/inst/misa_l/L.FRECIP/",
+ "/isa/inst/misa_l/L.FSQRT/": "/zh/isa/inst/misa_l/L.FSQRT/",
+ "/isa/inst/misa_l/L.FSUB/": "/zh/isa/inst/misa_l/L.FSUB/",
+ "/isa/inst/misa_l/L.ICVT/": "/zh/isa/inst/misa_l/L.ICVT/",
+ "/isa/inst/misa_l/L.ICVTF/": "/zh/isa/inst/misa_l/L.ICVTF/",
+ "/isa/inst/misa_l/L.LB.PCR/": "/zh/isa/inst/misa_l/L.LB.PCR/",
+ "/isa/inst/misa_l/L.LB/": "/zh/isa/inst/misa_l/L.LB/",
+ "/isa/inst/misa_l/L.LBI/": "/zh/isa/inst/misa_l/L.LBI/",
+ "/isa/inst/misa_l/L.LBU.PCR/": "/zh/isa/inst/misa_l/L.LBU.PCR/",
+ "/isa/inst/misa_l/L.LBU/": "/zh/isa/inst/misa_l/L.LBU/",
+ "/isa/inst/misa_l/L.LBUI/": "/zh/isa/inst/misa_l/L.LBUI/",
+ "/isa/inst/misa_l/L.LD.ADD/": "/zh/isa/inst/misa_l/L.LD.ADD/",
+ "/isa/inst/misa_l/L.LD.AND/": "/zh/isa/inst/misa_l/L.LD.AND/",
+ "/isa/inst/misa_l/L.LD.MAX/": "/zh/isa/inst/misa_l/L.LD.MAX/",
+ "/isa/inst/misa_l/L.LD.MIN/": "/zh/isa/inst/misa_l/L.LD.MIN/",
+ "/isa/inst/misa_l/L.LD.OR/": "/zh/isa/inst/misa_l/L.LD.OR/",
+ "/isa/inst/misa_l/L.LD.PCR/": "/zh/isa/inst/misa_l/L.LD.PCR/",
+ "/isa/inst/misa_l/L.LD.XOR/": "/zh/isa/inst/misa_l/L.LD.XOR/",
+ "/isa/inst/misa_l/L.LD/": "/zh/isa/inst/misa_l/L.LD/",
+ "/isa/inst/misa_l/L.LDI.U/": "/zh/isa/inst/misa_l/L.LDI.U/",
+ "/isa/inst/misa_l/L.LDI/": "/zh/isa/inst/misa_l/L.LDI/",
+ "/isa/inst/misa_l/L.LH.PCR/": "/zh/isa/inst/misa_l/L.LH.PCR/",
+ "/isa/inst/misa_l/L.LH/": "/zh/isa/inst/misa_l/L.LH/",
+ "/isa/inst/misa_l/L.LHI.U/": "/zh/isa/inst/misa_l/L.LHI.U/",
+ "/isa/inst/misa_l/L.LHI/": "/zh/isa/inst/misa_l/L.LHI/",
+ "/isa/inst/misa_l/L.LHU.PCR/": "/zh/isa/inst/misa_l/L.LHU.PCR/",
+ "/isa/inst/misa_l/L.LHU/": "/zh/isa/inst/misa_l/L.LHU/",
+ "/isa/inst/misa_l/L.LHUI.U/": "/zh/isa/inst/misa_l/L.LHUI.U/",
+ "/isa/inst/misa_l/L.LHUI/": "/zh/isa/inst/misa_l/L.LHUI/",
+ "/isa/inst/misa_l/L.LW.ADD/": "/zh/isa/inst/misa_l/L.LW.ADD/",
+ "/isa/inst/misa_l/L.LW.AND/": "/zh/isa/inst/misa_l/L.LW.AND/",
+ "/isa/inst/misa_l/L.LW.MAX/": "/zh/isa/inst/misa_l/L.LW.MAX/",
+ "/isa/inst/misa_l/L.LW.MIN/": "/zh/isa/inst/misa_l/L.LW.MIN/",
+ "/isa/inst/misa_l/L.LW.OR/": "/zh/isa/inst/misa_l/L.LW.OR/",
+ "/isa/inst/misa_l/L.LW.PCR/": "/zh/isa/inst/misa_l/L.LW.PCR/",
+ "/isa/inst/misa_l/L.LW.XOR/": "/zh/isa/inst/misa_l/L.LW.XOR/",
+ "/isa/inst/misa_l/L.LW/": "/zh/isa/inst/misa_l/L.LW/",
+ "/isa/inst/misa_l/L.LWI.U/": "/zh/isa/inst/misa_l/L.LWI.U/",
+ "/isa/inst/misa_l/L.LWI/": "/zh/isa/inst/misa_l/L.LWI/",
+ "/isa/inst/misa_l/L.LWU.PCR/": "/zh/isa/inst/misa_l/L.LWU.PCR/",
+ "/isa/inst/misa_l/L.LWU/": "/zh/isa/inst/misa_l/L.LWU/",
+ "/isa/inst/misa_l/L.LWUI.U/": "/zh/isa/inst/misa_l/L.LWUI.U/",
+ "/isa/inst/misa_l/L.LWUI/": "/zh/isa/inst/misa_l/L.LWUI/",
+ "/isa/inst/misa_l/L.MADD/": "/zh/isa/inst/misa_l/L.MADD/",
+ "/isa/inst/misa_l/L.MAX/": "/zh/isa/inst/misa_l/L.MAX/",
+ "/isa/inst/misa_l/L.MIN/": "/zh/isa/inst/misa_l/L.MIN/",
+ "/isa/inst/misa_l/L.MUL/": "/zh/isa/inst/misa_l/L.MUL/",
+ "/isa/inst/misa_l/L.OR/": "/zh/isa/inst/misa_l/L.OR/",
+ "/isa/inst/misa_l/L.ORI/": "/zh/isa/inst/misa_l/L.ORI/",
+ "/isa/inst/misa_l/L.QPOP/": "/zh/isa/inst/misa_l/L.QPOP/",
+ "/isa/inst/misa_l/L.QPUSH/": "/zh/isa/inst/misa_l/L.QPUSH/",
+ "/isa/inst/misa_l/L.REM/": "/zh/isa/inst/misa_l/L.REM/",
+ "/isa/inst/misa_l/L.REV/": "/zh/isa/inst/misa_l/L.REV/",
+ "/isa/inst/misa_l/L.SB.PCR/": "/zh/isa/inst/misa_l/L.SB.PCR/",
+ "/isa/inst/misa_l/L.SB/": "/zh/isa/inst/misa_l/L.SB/",
+ "/isa/inst/misa_l/L.SBI/": "/zh/isa/inst/misa_l/L.SBI/",
+ "/isa/inst/misa_l/L.SD.ADD/": "/zh/isa/inst/misa_l/L.SD.ADD/",
+ "/isa/inst/misa_l/L.SD.AND/": "/zh/isa/inst/misa_l/L.SD.AND/",
+ "/isa/inst/misa_l/L.SD.MAX/": "/zh/isa/inst/misa_l/L.SD.MAX/",
+ "/isa/inst/misa_l/L.SD.MIN/": "/zh/isa/inst/misa_l/L.SD.MIN/",
+ "/isa/inst/misa_l/L.SD.OR/": "/zh/isa/inst/misa_l/L.SD.OR/",
+ "/isa/inst/misa_l/L.SD.PCR/": "/zh/isa/inst/misa_l/L.SD.PCR/",
+ "/isa/inst/misa_l/L.SD.U/": "/zh/isa/inst/misa_l/L.SD.U/",
+ "/isa/inst/misa_l/L.SD.XOR/": "/zh/isa/inst/misa_l/L.SD.XOR/",
+ "/isa/inst/misa_l/L.SD/": "/zh/isa/inst/misa_l/L.SD/",
+ "/isa/inst/misa_l/L.SDI.U/": "/zh/isa/inst/misa_l/L.SDI.U/",
+ "/isa/inst/misa_l/L.SDI/": "/zh/isa/inst/misa_l/L.SDI/",
+ "/isa/inst/misa_l/L.SH.PCR/": "/zh/isa/inst/misa_l/L.SH.PCR/",
+ "/isa/inst/misa_l/L.SH.U/": "/zh/isa/inst/misa_l/L.SH.U/",
+ "/isa/inst/misa_l/L.SH/": "/zh/isa/inst/misa_l/L.SH/",
+ "/isa/inst/misa_l/L.SHI.U/": "/zh/isa/inst/misa_l/L.SHI.U/",
+ "/isa/inst/misa_l/L.SHI/": "/zh/isa/inst/misa_l/L.SHI/",
+ "/isa/inst/misa_l/L.SLL/": "/zh/isa/inst/misa_l/L.SLL/",
+ "/isa/inst/misa_l/L.SLLI/": "/zh/isa/inst/misa_l/L.SLLI/",
+ "/isa/inst/misa_l/L.SRA/": "/zh/isa/inst/misa_l/L.SRA/",
+ "/isa/inst/misa_l/L.SRAI/": "/zh/isa/inst/misa_l/L.SRAI/",
+ "/isa/inst/misa_l/L.SRL/": "/zh/isa/inst/misa_l/L.SRL/",
+ "/isa/inst/misa_l/L.SRLI/": "/zh/isa/inst/misa_l/L.SRLI/",
+ "/isa/inst/misa_l/L.SUB/": "/zh/isa/inst/misa_l/L.SUB/",
+ "/isa/inst/misa_l/L.SUBI/": "/zh/isa/inst/misa_l/L.SUBI/",
+ "/isa/inst/misa_l/L.SW.ADD/": "/zh/isa/inst/misa_l/L.SW.ADD/",
+ "/isa/inst/misa_l/L.SW.AND/": "/zh/isa/inst/misa_l/L.SW.AND/",
+ "/isa/inst/misa_l/L.SW.MAX/": "/zh/isa/inst/misa_l/L.SW.MAX/",
+ "/isa/inst/misa_l/L.SW.MIN/": "/zh/isa/inst/misa_l/L.SW.MIN/",
+ "/isa/inst/misa_l/L.SW.OR/": "/zh/isa/inst/misa_l/L.SW.OR/",
+ "/isa/inst/misa_l/L.SW.PCR/": "/zh/isa/inst/misa_l/L.SW.PCR/",
+ "/isa/inst/misa_l/L.SW.U/": "/zh/isa/inst/misa_l/L.SW.U/",
+ "/isa/inst/misa_l/L.SW.XOR/": "/zh/isa/inst/misa_l/L.SW.XOR/",
+ "/isa/inst/misa_l/L.SW/": "/zh/isa/inst/misa_l/L.SW/",
+ "/isa/inst/misa_l/L.SWI.U/": "/zh/isa/inst/misa_l/L.SWI.U/",
+ "/isa/inst/misa_l/L.SWI/": "/zh/isa/inst/misa_l/L.SWI/",
+ "/isa/inst/misa_l/L.XOR/": "/zh/isa/inst/misa_l/L.XOR/",
+ "/isa/inst/misa_l/L.XORI/": "/zh/isa/inst/misa_l/L.XORI/",
+ "/isa/inst/misa_s/ACRC/": "/zh/isa/inst/misa_s/ACRC/",
+ "/isa/inst/misa_s/ACRE/": "/zh/isa/inst/misa_s/ACRE/",
+ "/isa/inst/misa_s/ASSERT/": "/zh/isa/inst/misa_s/ASSERT/",
+ "/isa/inst/misa_s/BC.IALL/": "/zh/isa/inst/misa_s/BC.IALL/",
+ "/isa/inst/misa_s/BC.IVA/": "/zh/isa/inst/misa_s/BC.IVA/",
+ "/isa/inst/misa_s/BSE/": "/zh/isa/inst/misa_s/BSE/",
+ "/isa/inst/misa_s/BWE/": "/zh/isa/inst/misa_s/BWE/",
+ "/isa/inst/misa_s/BWI/": "/zh/isa/inst/misa_s/BWI/",
+ "/isa/inst/misa_s/BWT/": "/zh/isa/inst/misa_s/BWT/",
+ "/isa/inst/misa_s/DC.CISW/": "/zh/isa/inst/misa_s/DC.CISW/",
+ "/isa/inst/misa_s/DC.CIVA/": "/zh/isa/inst/misa_s/DC.CIVA/",
+ "/isa/inst/misa_s/DC.CSW/": "/zh/isa/inst/misa_s/DC.CSW/",
+ "/isa/inst/misa_s/DC.CVA/": "/zh/isa/inst/misa_s/DC.CVA/",
+ "/isa/inst/misa_s/DC.IALL/": "/zh/isa/inst/misa_s/DC.IALL/",
+ "/isa/inst/misa_s/DC.ISW/": "/zh/isa/inst/misa_s/DC.ISW/",
+ "/isa/inst/misa_s/DC.IVA/": "/zh/isa/inst/misa_s/DC.IVA/",
+ "/isa/inst/misa_s/DC.ZVA/": "/zh/isa/inst/misa_s/DC.ZVA/",
+ "/isa/inst/misa_s/DMA/": "/zh/isa/inst/misa_s/DMA/",
+ "/isa/inst/misa_s/DSB/": "/zh/isa/inst/misa_s/DSB/",
+ "/isa/inst/misa_s/EBREAK/": "/zh/isa/inst/misa_s/EBREAK/",
+ "/isa/inst/misa_s/IC.IALL/": "/zh/isa/inst/misa_s/IC.IALL/",
+ "/isa/inst/misa_s/IC.IVA/": "/zh/isa/inst/misa_s/IC.IVA/",
+ "/isa/inst/misa_s/ISB/": "/zh/isa/inst/misa_s/ISB/",
+ "/isa/inst/misa_s/LD.ADD/": "/zh/isa/inst/misa_s/LD.ADD/",
+ "/isa/inst/misa_s/LD.AND/": "/zh/isa/inst/misa_s/LD.AND/",
+ "/isa/inst/misa_s/LD.OR/": "/zh/isa/inst/misa_s/LD.OR/",
+ "/isa/inst/misa_s/LD.SMAX/": "/zh/isa/inst/misa_s/LD.SMAX/",
+ "/isa/inst/misa_s/LD.SMIN/": "/zh/isa/inst/misa_s/LD.SMIN/",
+ "/isa/inst/misa_s/LD.UMAX/": "/zh/isa/inst/misa_s/LD.UMAX/",
+ "/isa/inst/misa_s/LD.UMIN/": "/zh/isa/inst/misa_s/LD.UMIN/",
+ "/isa/inst/misa_s/LD.XOR/": "/zh/isa/inst/misa_s/LD.XOR/",
+ "/isa/inst/misa_s/LR.B/": "/zh/isa/inst/misa_s/LR.B/",
+ "/isa/inst/misa_s/LR.D/": "/zh/isa/inst/misa_s/LR.D/",
+ "/isa/inst/misa_s/LR.H/": "/zh/isa/inst/misa_s/LR.H/",
+ "/isa/inst/misa_s/LR.W/": "/zh/isa/inst/misa_s/LR.W/",
+ "/isa/inst/misa_s/LW.ADD/": "/zh/isa/inst/misa_s/LW.ADD/",
+ "/isa/inst/misa_s/LW.AND/": "/zh/isa/inst/misa_s/LW.AND/",
+ "/isa/inst/misa_s/LW.OR/": "/zh/isa/inst/misa_s/LW.OR/",
+ "/isa/inst/misa_s/LW.SMAX/": "/zh/isa/inst/misa_s/LW.SMAX/",
+ "/isa/inst/misa_s/LW.SMIN/": "/zh/isa/inst/misa_s/LW.SMIN/",
+ "/isa/inst/misa_s/LW.UMAX/": "/zh/isa/inst/misa_s/LW.UMAX/",
+ "/isa/inst/misa_s/LW.UMIN/": "/zh/isa/inst/misa_s/LW.UMIN/",
+ "/isa/inst/misa_s/LW.XOR/": "/zh/isa/inst/misa_s/LW.XOR/",
+ "/isa/inst/misa_s/SC.B/": "/zh/isa/inst/misa_s/SC.B/",
+ "/isa/inst/misa_s/SC.D/": "/zh/isa/inst/misa_s/SC.D/",
+ "/isa/inst/misa_s/SC.H/": "/zh/isa/inst/misa_s/SC.H/",
+ "/isa/inst/misa_s/SC.W/": "/zh/isa/inst/misa_s/SC.W/",
+ "/isa/inst/misa_s/SD.ADD/": "/zh/isa/inst/misa_s/SD.ADD/",
+ "/isa/inst/misa_s/SD.AND/": "/zh/isa/inst/misa_s/SD.AND/",
+ "/isa/inst/misa_s/SD.OR/": "/zh/isa/inst/misa_s/SD.OR/",
+ "/isa/inst/misa_s/SD.SMAX/": "/zh/isa/inst/misa_s/SD.SMAX/",
+ "/isa/inst/misa_s/SD.SMIN/": "/zh/isa/inst/misa_s/SD.SMIN/",
+ "/isa/inst/misa_s/SD.UMAX/": "/zh/isa/inst/misa_s/SD.UMAX/",
+ "/isa/inst/misa_s/SD.UMIN/": "/zh/isa/inst/misa_s/SD.UMIN/",
+ "/isa/inst/misa_s/SD.XOR/": "/zh/isa/inst/misa_s/SD.XOR/",
+ "/isa/inst/misa_s/SW.ADD/": "/zh/isa/inst/misa_s/SW.ADD/",
+ "/isa/inst/misa_s/SW.AND/": "/zh/isa/inst/misa_s/SW.AND/",
+ "/isa/inst/misa_s/SW.OR/": "/zh/isa/inst/misa_s/SW.OR/",
+ "/isa/inst/misa_s/SW.SMAX/": "/zh/isa/inst/misa_s/SW.SMAX/",
+ "/isa/inst/misa_s/SW.SMIN/": "/zh/isa/inst/misa_s/SW.SMIN/",
+ "/isa/inst/misa_s/SW.UMAX/": "/zh/isa/inst/misa_s/SW.UMAX/",
+ "/isa/inst/misa_s/SW.UMIN/": "/zh/isa/inst/misa_s/SW.UMIN/",
+ "/isa/inst/misa_s/SW.XOR/": "/zh/isa/inst/misa_s/SW.XOR/",
+ "/isa/inst/misa_s/SWAPB/": "/zh/isa/inst/misa_s/SWAPB/",
+ "/isa/inst/misa_s/SWAPD/": "/zh/isa/inst/misa_s/SWAPD/",
+ "/isa/inst/misa_s/SWAPH/": "/zh/isa/inst/misa_s/SWAPH/",
+ "/isa/inst/misa_s/SWAPW/": "/zh/isa/inst/misa_s/SWAPW/",
+ "/isa/inst/misa_s/TC.IA/": "/zh/isa/inst/misa_s/TC.IA/",
+ "/isa/inst/misa_s/TC.IALL/": "/zh/isa/inst/misa_s/TC.IALL/",
+ "/isa/inst/misa_s/TC.IAV/": "/zh/isa/inst/misa_s/TC.IAV/",
+ "/isa/inst/misa_s/TC.IV/": "/zh/isa/inst/misa_s/TC.IV/",
+ "/isa/inst/misa_v/V.ADD/": "/zh/isa/inst/misa_v/V.ADD/",
+ "/isa/inst/misa_v/V.ADDI/": "/zh/isa/inst/misa_v/V.ADDI/",
+ "/isa/inst/misa_v/V.AND/": "/zh/isa/inst/misa_v/V.AND/",
+ "/isa/inst/misa_v/V.ANDI/": "/zh/isa/inst/misa_v/V.ANDI/",
+ "/isa/inst/misa_v/V.BCNT/": "/zh/isa/inst/misa_v/V.BCNT/",
+ "/isa/inst/misa_v/V.BIC/": "/zh/isa/inst/misa_v/V.BIC/",
+ "/isa/inst/misa_v/V.BIS/": "/zh/isa/inst/misa_v/V.BIS/",
+ "/isa/inst/misa_v/V.BXS/": "/zh/isa/inst/misa_v/V.BXS/",
+ "/isa/inst/misa_v/V.BXU/": "/zh/isa/inst/misa_v/V.BXU/",
+ "/isa/inst/misa_v/V.CLZ/": "/zh/isa/inst/misa_v/V.CLZ/",
+ "/isa/inst/misa_v/V.CMP.AND/": "/zh/isa/inst/misa_v/V.CMP.AND/",
+ "/isa/inst/misa_v/V.CMP.ANDI/": "/zh/isa/inst/misa_v/V.CMP.ANDI/",
+ "/isa/inst/misa_v/V.CMP.EQ/": "/zh/isa/inst/misa_v/V.CMP.EQ/",
+ "/isa/inst/misa_v/V.CMP.EQI/": "/zh/isa/inst/misa_v/V.CMP.EQI/",
+ "/isa/inst/misa_v/V.CMP.GE/": "/zh/isa/inst/misa_v/V.CMP.GE/",
+ "/isa/inst/misa_v/V.CMP.GEI/": "/zh/isa/inst/misa_v/V.CMP.GEI/",
+ "/isa/inst/misa_v/V.CMP.GEU/": "/zh/isa/inst/misa_v/V.CMP.GEU/",
+ "/isa/inst/misa_v/V.CMP.GEUI/": "/zh/isa/inst/misa_v/V.CMP.GEUI/",
+ "/isa/inst/misa_v/V.CMP.LT/": "/zh/isa/inst/misa_v/V.CMP.LT/",
+ "/isa/inst/misa_v/V.CMP.LTI/": "/zh/isa/inst/misa_v/V.CMP.LTI/",
+ "/isa/inst/misa_v/V.CMP.LTU/": "/zh/isa/inst/misa_v/V.CMP.LTU/",
+ "/isa/inst/misa_v/V.CMP.LTUI/": "/zh/isa/inst/misa_v/V.CMP.LTUI/",
+ "/isa/inst/misa_v/V.CMP.NE/": "/zh/isa/inst/misa_v/V.CMP.NE/",
+ "/isa/inst/misa_v/V.CMP.NEI/": "/zh/isa/inst/misa_v/V.CMP.NEI/",
+ "/isa/inst/misa_v/V.CMP.OR/": "/zh/isa/inst/misa_v/V.CMP.OR/",
+ "/isa/inst/misa_v/V.CMP.ORI/": "/zh/isa/inst/misa_v/V.CMP.ORI/",
+ "/isa/inst/misa_v/V.CSEL/": "/zh/isa/inst/misa_v/V.CSEL/",
+ "/isa/inst/misa_v/V.CTZ/": "/zh/isa/inst/misa_v/V.CTZ/",
+ "/isa/inst/misa_v/V.DIV/": "/zh/isa/inst/misa_v/V.DIV/",
+ "/isa/inst/misa_v/V.FABS/": "/zh/isa/inst/misa_v/V.FABS/",
+ "/isa/inst/misa_v/V.FADD/": "/zh/isa/inst/misa_v/V.FADD/",
+ "/isa/inst/misa_v/V.FCLASS/": "/zh/isa/inst/misa_v/V.FCLASS/",
+ "/isa/inst/misa_v/V.FCVT/": "/zh/isa/inst/misa_v/V.FCVT/",
+ "/isa/inst/misa_v/V.FCVTI/": "/zh/isa/inst/misa_v/V.FCVTI/",
+ "/isa/inst/misa_v/V.FDIV/": "/zh/isa/inst/misa_v/V.FDIV/",
+ "/isa/inst/misa_v/V.FEQ/": "/zh/isa/inst/misa_v/V.FEQ/",
+ "/isa/inst/misa_v/V.FEQS/": "/zh/isa/inst/misa_v/V.FEQS/",
+ "/isa/inst/misa_v/V.FEXP/": "/zh/isa/inst/misa_v/V.FEXP/",
+ "/isa/inst/misa_v/V.FGE/": "/zh/isa/inst/misa_v/V.FGE/",
+ "/isa/inst/misa_v/V.FGES/": "/zh/isa/inst/misa_v/V.FGES/",
+ "/isa/inst/misa_v/V.FLT/": "/zh/isa/inst/misa_v/V.FLT/",
+ "/isa/inst/misa_v/V.FLTS/": "/zh/isa/inst/misa_v/V.FLTS/",
+ "/isa/inst/misa_v/V.FMADD/": "/zh/isa/inst/misa_v/V.FMADD/",
+ "/isa/inst/misa_v/V.FMAX/": "/zh/isa/inst/misa_v/V.FMAX/",
+ "/isa/inst/misa_v/V.FMIN/": "/zh/isa/inst/misa_v/V.FMIN/",
+ "/isa/inst/misa_v/V.FMSUB/": "/zh/isa/inst/misa_v/V.FMSUB/",
+ "/isa/inst/misa_v/V.FMUL/": "/zh/isa/inst/misa_v/V.FMUL/",
+ "/isa/inst/misa_v/V.FNE/": "/zh/isa/inst/misa_v/V.FNE/",
+ "/isa/inst/misa_v/V.FNES/": "/zh/isa/inst/misa_v/V.FNES/",
+ "/isa/inst/misa_v/V.FNMADD/": "/zh/isa/inst/misa_v/V.FNMADD/",
+ "/isa/inst/misa_v/V.FNMSUB/": "/zh/isa/inst/misa_v/V.FNMSUB/",
+ "/isa/inst/misa_v/V.FRECIP/": "/zh/isa/inst/misa_v/V.FRECIP/",
+ "/isa/inst/misa_v/V.FSQRT/": "/zh/isa/inst/misa_v/V.FSQRT/",
+ "/isa/inst/misa_v/V.FSUB/": "/zh/isa/inst/misa_v/V.FSUB/",
+ "/isa/inst/misa_v/V.ICVT/": "/zh/isa/inst/misa_v/V.ICVT/",
+ "/isa/inst/misa_v/V.ICVTF/": "/zh/isa/inst/misa_v/V.ICVTF/",
+ "/isa/inst/misa_v/V.LB.BRG/": "/zh/isa/inst/misa_v/V.LB.BRG/",
+ "/isa/inst/misa_v/V.LB/": "/zh/isa/inst/misa_v/V.LB/",
+ "/isa/inst/misa_v/V.LBI.BRG/": "/zh/isa/inst/misa_v/V.LBI.BRG/",
+ "/isa/inst/misa_v/V.LBI/": "/zh/isa/inst/misa_v/V.LBI/",
+ "/isa/inst/misa_v/V.LBU.BRG/": "/zh/isa/inst/misa_v/V.LBU.BRG/",
+ "/isa/inst/misa_v/V.LBU/": "/zh/isa/inst/misa_v/V.LBU/",
+ "/isa/inst/misa_v/V.LBUI.BRG/": "/zh/isa/inst/misa_v/V.LBUI.BRG/",
+ "/isa/inst/misa_v/V.LBUI/": "/zh/isa/inst/misa_v/V.LBUI/",
+ "/isa/inst/misa_v/V.LD.ADD/": "/zh/isa/inst/misa_v/V.LD.ADD/",
+ "/isa/inst/misa_v/V.LD.AND/": "/zh/isa/inst/misa_v/V.LD.AND/",
+ "/isa/inst/misa_v/V.LD.BRG/": "/zh/isa/inst/misa_v/V.LD.BRG/",
+ "/isa/inst/misa_v/V.LD.MAX/": "/zh/isa/inst/misa_v/V.LD.MAX/",
+ "/isa/inst/misa_v/V.LD.MIN/": "/zh/isa/inst/misa_v/V.LD.MIN/",
+ "/isa/inst/misa_v/V.LD.OR/": "/zh/isa/inst/misa_v/V.LD.OR/",
+ "/isa/inst/misa_v/V.LD.XOR/": "/zh/isa/inst/misa_v/V.LD.XOR/",
+ "/isa/inst/misa_v/V.LD/": "/zh/isa/inst/misa_v/V.LD/",
+ "/isa/inst/misa_v/V.LDI.BRG/": "/zh/isa/inst/misa_v/V.LDI.BRG/",
+ "/isa/inst/misa_v/V.LDI.U/": "/zh/isa/inst/misa_v/V.LDI.U/",
+ "/isa/inst/misa_v/V.LDI.UBRG/": "/zh/isa/inst/misa_v/V.LDI.UBRG/",
+ "/isa/inst/misa_v/V.LDI/": "/zh/isa/inst/misa_v/V.LDI/",
+ "/isa/inst/misa_v/V.LH.BRG/": "/zh/isa/inst/misa_v/V.LH.BRG/",
+ "/isa/inst/misa_v/V.LH/": "/zh/isa/inst/misa_v/V.LH/",
+ "/isa/inst/misa_v/V.LHI.BRG/": "/zh/isa/inst/misa_v/V.LHI.BRG/",
+ "/isa/inst/misa_v/V.LHI.U/": "/zh/isa/inst/misa_v/V.LHI.U/",
+ "/isa/inst/misa_v/V.LHI.UBRG/": "/zh/isa/inst/misa_v/V.LHI.UBRG/",
+ "/isa/inst/misa_v/V.LHI/": "/zh/isa/inst/misa_v/V.LHI/",
+ "/isa/inst/misa_v/V.LHU.BRG/": "/zh/isa/inst/misa_v/V.LHU.BRG/",
+ "/isa/inst/misa_v/V.LHU/": "/zh/isa/inst/misa_v/V.LHU/",
+ "/isa/inst/misa_v/V.LHUI.BRG/": "/zh/isa/inst/misa_v/V.LHUI.BRG/",
+ "/isa/inst/misa_v/V.LHUI.U/": "/zh/isa/inst/misa_v/V.LHUI.U/",
+ "/isa/inst/misa_v/V.LHUI.UBRG/": "/zh/isa/inst/misa_v/V.LHUI.UBRG/",
+ "/isa/inst/misa_v/V.LHUI/": "/zh/isa/inst/misa_v/V.LHUI/",
+ "/isa/inst/misa_v/V.LW.ADD/": "/zh/isa/inst/misa_v/V.LW.ADD/",
+ "/isa/inst/misa_v/V.LW.AND/": "/zh/isa/inst/misa_v/V.LW.AND/",
+ "/isa/inst/misa_v/V.LW.BRG/": "/zh/isa/inst/misa_v/V.LW.BRG/",
+ "/isa/inst/misa_v/V.LW.MAX/": "/zh/isa/inst/misa_v/V.LW.MAX/",
+ "/isa/inst/misa_v/V.LW.MIN/": "/zh/isa/inst/misa_v/V.LW.MIN/",
+ "/isa/inst/misa_v/V.LW.OR/": "/zh/isa/inst/misa_v/V.LW.OR/",
+ "/isa/inst/misa_v/V.LW.XOR/": "/zh/isa/inst/misa_v/V.LW.XOR/",
+ "/isa/inst/misa_v/V.LW/": "/zh/isa/inst/misa_v/V.LW/",
+ "/isa/inst/misa_v/V.LWI.BRG/": "/zh/isa/inst/misa_v/V.LWI.BRG/",
+ "/isa/inst/misa_v/V.LWI.U/": "/zh/isa/inst/misa_v/V.LWI.U/",
+ "/isa/inst/misa_v/V.LWI.UBRG/": "/zh/isa/inst/misa_v/V.LWI.UBRG/",
+ "/isa/inst/misa_v/V.LWI/": "/zh/isa/inst/misa_v/V.LWI/",
+ "/isa/inst/misa_v/V.LWU.BRG/": "/zh/isa/inst/misa_v/V.LWU.BRG/",
+ "/isa/inst/misa_v/V.LWU/": "/zh/isa/inst/misa_v/V.LWU/",
+ "/isa/inst/misa_v/V.LWUI.BRG/": "/zh/isa/inst/misa_v/V.LWUI.BRG/",
+ "/isa/inst/misa_v/V.LWUI.U/": "/zh/isa/inst/misa_v/V.LWUI.U/",
+ "/isa/inst/misa_v/V.LWUI.UBRG/": "/zh/isa/inst/misa_v/V.LWUI.UBRG/",
+ "/isa/inst/misa_v/V.LWUI/": "/zh/isa/inst/misa_v/V.LWUI/",
+ "/isa/inst/misa_v/V.MADD/": "/zh/isa/inst/misa_v/V.MADD/",
+ "/isa/inst/misa_v/V.MAX/": "/zh/isa/inst/misa_v/V.MAX/",
+ "/isa/inst/misa_v/V.MIN/": "/zh/isa/inst/misa_v/V.MIN/",
+ "/isa/inst/misa_v/V.MOV/": "/zh/isa/inst/misa_v/V.MOV/",
+ "/isa/inst/misa_v/V.MUL/": "/zh/isa/inst/misa_v/V.MUL/",
+ "/isa/inst/misa_v/V.OR/": "/zh/isa/inst/misa_v/V.OR/",
+ "/isa/inst/misa_v/V.ORI/": "/zh/isa/inst/misa_v/V.ORI/",
+ "/isa/inst/misa_v/V.PSEL/": "/zh/isa/inst/misa_v/V.PSEL/",
+ "/isa/inst/misa_v/V.QPOP/": "/zh/isa/inst/misa_v/V.QPOP/",
+ "/isa/inst/misa_v/V.QPUSH/": "/zh/isa/inst/misa_v/V.QPUSH/",
+ "/isa/inst/misa_v/V.RDADD/": "/zh/isa/inst/misa_v/V.RDADD/",
+ "/isa/inst/misa_v/V.RDAND/": "/zh/isa/inst/misa_v/V.RDAND/",
+ "/isa/inst/misa_v/V.RDFADD/": "/zh/isa/inst/misa_v/V.RDFADD/",
+ "/isa/inst/misa_v/V.RDFMAX/": "/zh/isa/inst/misa_v/V.RDFMAX/",
+ "/isa/inst/misa_v/V.RDFMIN/": "/zh/isa/inst/misa_v/V.RDFMIN/",
+ "/isa/inst/misa_v/V.RDMAX/": "/zh/isa/inst/misa_v/V.RDMAX/",
+ "/isa/inst/misa_v/V.RDMIN/": "/zh/isa/inst/misa_v/V.RDMIN/",
+ "/isa/inst/misa_v/V.RDOR/": "/zh/isa/inst/misa_v/V.RDOR/",
+ "/isa/inst/misa_v/V.RDXOR/": "/zh/isa/inst/misa_v/V.RDXOR/",
+ "/isa/inst/misa_v/V.REM/": "/zh/isa/inst/misa_v/V.REM/",
+ "/isa/inst/misa_v/V.REV/": "/zh/isa/inst/misa_v/V.REV/",
+ "/isa/inst/misa_v/V.SB.BRG/": "/zh/isa/inst/misa_v/V.SB.BRG/",
+ "/isa/inst/misa_v/V.SB/": "/zh/isa/inst/misa_v/V.SB/",
+ "/isa/inst/misa_v/V.SBI.BRG/": "/zh/isa/inst/misa_v/V.SBI.BRG/",
+ "/isa/inst/misa_v/V.SBI/": "/zh/isa/inst/misa_v/V.SBI/",
+ "/isa/inst/misa_v/V.SD.ADD/": "/zh/isa/inst/misa_v/V.SD.ADD/",
+ "/isa/inst/misa_v/V.SD.AND/": "/zh/isa/inst/misa_v/V.SD.AND/",
+ "/isa/inst/misa_v/V.SD.BRG/": "/zh/isa/inst/misa_v/V.SD.BRG/",
+ "/isa/inst/misa_v/V.SD.MAX/": "/zh/isa/inst/misa_v/V.SD.MAX/",
+ "/isa/inst/misa_v/V.SD.MIN/": "/zh/isa/inst/misa_v/V.SD.MIN/",
+ "/isa/inst/misa_v/V.SD.OR/": "/zh/isa/inst/misa_v/V.SD.OR/",
+ "/isa/inst/misa_v/V.SD.U/": "/zh/isa/inst/misa_v/V.SD.U/",
+ "/isa/inst/misa_v/V.SD.UBRG/": "/zh/isa/inst/misa_v/V.SD.UBRG/",
+ "/isa/inst/misa_v/V.SD.XOR/": "/zh/isa/inst/misa_v/V.SD.XOR/",
+ "/isa/inst/misa_v/V.SD/": "/zh/isa/inst/misa_v/V.SD/",
+ "/isa/inst/misa_v/V.SDI.BRG/": "/zh/isa/inst/misa_v/V.SDI.BRG/",
+ "/isa/inst/misa_v/V.SDI.U/": "/zh/isa/inst/misa_v/V.SDI.U/",
+ "/isa/inst/misa_v/V.SDI.UBRG/": "/zh/isa/inst/misa_v/V.SDI.UBRG/",
+ "/isa/inst/misa_v/V.SDI/": "/zh/isa/inst/misa_v/V.SDI/",
+ "/isa/inst/misa_v/V.SH.BRG/": "/zh/isa/inst/misa_v/V.SH.BRG/",
+ "/isa/inst/misa_v/V.SH.U/": "/zh/isa/inst/misa_v/V.SH.U/",
+ "/isa/inst/misa_v/V.SH.UBRG/": "/zh/isa/inst/misa_v/V.SH.UBRG/",
+ "/isa/inst/misa_v/V.SH/": "/zh/isa/inst/misa_v/V.SH/",
+ "/isa/inst/misa_v/V.SHFL.BFLY/": "/zh/isa/inst/misa_v/V.SHFL.BFLY/",
+ "/isa/inst/misa_v/V.SHFL.DOWN/": "/zh/isa/inst/misa_v/V.SHFL.DOWN/",
+ "/isa/inst/misa_v/V.SHFL.IDX/": "/zh/isa/inst/misa_v/V.SHFL.IDX/",
+ "/isa/inst/misa_v/V.SHFL.UP/": "/zh/isa/inst/misa_v/V.SHFL.UP/",
+ "/isa/inst/misa_v/V.SHFLI.BFLY/": "/zh/isa/inst/misa_v/V.SHFLI.BFLY/",
+ "/isa/inst/misa_v/V.SHFLI.DOWN/": "/zh/isa/inst/misa_v/V.SHFLI.DOWN/",
+ "/isa/inst/misa_v/V.SHFLI.IDX/": "/zh/isa/inst/misa_v/V.SHFLI.IDX/",
+ "/isa/inst/misa_v/V.SHFLI.UP/": "/zh/isa/inst/misa_v/V.SHFLI.UP/",
+ "/isa/inst/misa_v/V.SHI.BRG/": "/zh/isa/inst/misa_v/V.SHI.BRG/",
+ "/isa/inst/misa_v/V.SHI.U/": "/zh/isa/inst/misa_v/V.SHI.U/",
+ "/isa/inst/misa_v/V.SHI.UBRG/": "/zh/isa/inst/misa_v/V.SHI.UBRG/",
+ "/isa/inst/misa_v/V.SHI/": "/zh/isa/inst/misa_v/V.SHI/",
+ "/isa/inst/misa_v/V.SLL/": "/zh/isa/inst/misa_v/V.SLL/",
+ "/isa/inst/misa_v/V.SLLI/": "/zh/isa/inst/misa_v/V.SLLI/",
+ "/isa/inst/misa_v/V.SRA/": "/zh/isa/inst/misa_v/V.SRA/",
+ "/isa/inst/misa_v/V.SRAI/": "/zh/isa/inst/misa_v/V.SRAI/",
+ "/isa/inst/misa_v/V.SRL/": "/zh/isa/inst/misa_v/V.SRL/",
+ "/isa/inst/misa_v/V.SRLI/": "/zh/isa/inst/misa_v/V.SRLI/",
+ "/isa/inst/misa_v/V.SUB/": "/zh/isa/inst/misa_v/V.SUB/",
+ "/isa/inst/misa_v/V.SUBI/": "/zh/isa/inst/misa_v/V.SUBI/",
+ "/isa/inst/misa_v/V.SW.ADD/": "/zh/isa/inst/misa_v/V.SW.ADD/",
+ "/isa/inst/misa_v/V.SW.AND/": "/zh/isa/inst/misa_v/V.SW.AND/",
+ "/isa/inst/misa_v/V.SW.BRG/": "/zh/isa/inst/misa_v/V.SW.BRG/",
+ "/isa/inst/misa_v/V.SW.MAX/": "/zh/isa/inst/misa_v/V.SW.MAX/",
+ "/isa/inst/misa_v/V.SW.MIN/": "/zh/isa/inst/misa_v/V.SW.MIN/",
+ "/isa/inst/misa_v/V.SW.OR/": "/zh/isa/inst/misa_v/V.SW.OR/",
+ "/isa/inst/misa_v/V.SW.U/": "/zh/isa/inst/misa_v/V.SW.U/",
+ "/isa/inst/misa_v/V.SW.UBRG/": "/zh/isa/inst/misa_v/V.SW.UBRG/",
+ "/isa/inst/misa_v/V.SW.XOR/": "/zh/isa/inst/misa_v/V.SW.XOR/",
+ "/isa/inst/misa_v/V.SW/": "/zh/isa/inst/misa_v/V.SW/",
+ "/isa/inst/misa_v/V.SWI.BRG/": "/zh/isa/inst/misa_v/V.SWI.BRG/",
+ "/isa/inst/misa_v/V.SWI.U/": "/zh/isa/inst/misa_v/V.SWI.U/",
+ "/isa/inst/misa_v/V.SWI.UBRG/": "/zh/isa/inst/misa_v/V.SWI.UBRG/",
+ "/isa/inst/misa_v/V.SWI/": "/zh/isa/inst/misa_v/V.SWI/",
+ "/isa/inst/misa_v/V.XOR/": "/zh/isa/inst/misa_v/V.XOR/",
+ "/isa/inst/misa_v/V.XORI/": "/zh/isa/inst/misa_v/V.XORI/",
+ "/isa/instructions/": "/zh/isa/instructions/",
+ "/isa/instructions/acrc/": "/zh/isa/instructions/acrc/",
+ "/isa/instructions/acre/": "/zh/isa/instructions/acre/",
+ "/isa/instructions/add/": "/zh/isa/instructions/add/",
+ "/isa/instructions/addi/": "/zh/isa/instructions/addi/",
+ "/isa/instructions/addiw/": "/zh/isa/instructions/addiw/",
+ "/isa/instructions/addtpc/": "/zh/isa/instructions/addtpc/",
+ "/isa/instructions/addw/": "/zh/isa/instructions/addw/",
+ "/isa/instructions/and/": "/zh/isa/instructions/and/",
+ "/isa/instructions/andi/": "/zh/isa/instructions/andi/",
+ "/isa/instructions/andiw/": "/zh/isa/instructions/andiw/",
+ "/isa/instructions/andw/": "/zh/isa/instructions/andw/",
+ "/isa/instructions/assert/": "/zh/isa/instructions/assert/",
+ "/isa/instructions/b_arg/": "/zh/isa/instructions/b_arg/",
+ "/isa/instructions/b_catr/": "/zh/isa/instructions/b_catr/",
+ "/isa/instructions/b_datr/": "/zh/isa/instructions/b_datr/",
+ "/isa/instructions/b_dim/": "/zh/isa/instructions/b_dim/",
+ "/isa/instructions/b_eq/": "/zh/isa/instructions/b_eq/",
+ "/isa/instructions/b_ge/": "/zh/isa/instructions/b_ge/",
+ "/isa/instructions/b_geu/": "/zh/isa/instructions/b_geu/",
+ "/isa/instructions/b_hint/": "/zh/isa/instructions/b_hint/",
+ "/isa/instructions/b_iod/": "/zh/isa/instructions/b_iod/",
+ "/isa/instructions/b_ior/": "/zh/isa/instructions/b_ior/",
+ "/isa/instructions/b_iot/": "/zh/isa/instructions/b_iot/",
+ "/isa/instructions/b_lt/": "/zh/isa/instructions/b_lt/",
+ "/isa/instructions/b_ltu/": "/zh/isa/instructions/b_ltu/",
+ "/isa/instructions/b_ne/": "/zh/isa/instructions/b_ne/",
+ "/isa/instructions/b_nz/": "/zh/isa/instructions/b_nz/",
+ "/isa/instructions/b_text/": "/zh/isa/instructions/b_text/",
+ "/isa/instructions/b_z/": "/zh/isa/instructions/b_z/",
+ "/isa/instructions/bc_iall/": "/zh/isa/instructions/bc_iall/",
+ "/isa/instructions/bc_iva/": "/zh/isa/instructions/bc_iva/",
+ "/isa/instructions/bcnt/": "/zh/isa/instructions/bcnt/",
+ "/isa/instructions/bic/": "/zh/isa/instructions/bic/",
+ "/isa/instructions/bis/": "/zh/isa/instructions/bis/",
+ "/isa/instructions/bse/": "/zh/isa/instructions/bse/",
+ "/isa/instructions/bstart/": "/zh/isa/instructions/bstart/",
+ "/isa/instructions/bstart_acccvt/": "/zh/isa/instructions/bstart_acccvt/",
+ "/isa/instructions/bstart_call/": "/zh/isa/instructions/bstart_call/",
+ "/isa/instructions/bstart_cube/": "/zh/isa/instructions/bstart_cube/",
+ "/isa/instructions/bstart_fixp/": "/zh/isa/instructions/bstart_fixp/",
+ "/isa/instructions/bstart_fp/": "/zh/isa/instructions/bstart_fp/",
+ "/isa/instructions/bstart_mpar/": "/zh/isa/instructions/bstart_mpar/",
+ "/isa/instructions/bstart_mseq/": "/zh/isa/instructions/bstart_mseq/",
+ "/isa/instructions/bstart_par/": "/zh/isa/instructions/bstart_par/",
+ "/isa/instructions/bstart_std/": "/zh/isa/instructions/bstart_std/",
+ "/isa/instructions/bstart_sys/": "/zh/isa/instructions/bstart_sys/",
+ "/isa/instructions/bstart_tepl/": "/zh/isa/instructions/bstart_tepl/",
+ "/isa/instructions/bstart_tload/": "/zh/isa/instructions/bstart_tload/",
+ "/isa/instructions/bstart_tma/": "/zh/isa/instructions/bstart_tma/",
+ "/isa/instructions/bstart_tmatmul/": "/zh/isa/instructions/bstart_tmatmul/",
+ "/isa/instructions/bstart_tmatmul_acc/": "/zh/isa/instructions/bstart_tmatmul_acc/",
+ "/isa/instructions/bstart_tmov/": "/zh/isa/instructions/bstart_tmov/",
+ "/isa/instructions/bstart_tstore/": "/zh/isa/instructions/bstart_tstore/",
+ "/isa/instructions/bstart_vpar/": "/zh/isa/instructions/bstart_vpar/",
+ "/isa/instructions/bstart_vseq/": "/zh/isa/instructions/bstart_vseq/",
+ "/isa/instructions/bstop/": "/zh/isa/instructions/bstop/",
+ "/isa/instructions/bwe/": "/zh/isa/instructions/bwe/",
+ "/isa/instructions/bwi/": "/zh/isa/instructions/bwi/",
+ "/isa/instructions/bwt/": "/zh/isa/instructions/bwt/",
+ "/isa/instructions/bxs/": "/zh/isa/instructions/bxs/",
+ "/isa/instructions/bxu/": "/zh/isa/instructions/bxu/",
+ "/isa/instructions/c_add/": "/zh/isa/instructions/c_add/",
+ "/isa/instructions/c_addi/": "/zh/isa/instructions/c_addi/",
+ "/isa/instructions/c_and/": "/zh/isa/instructions/c_and/",
+ "/isa/instructions/c_b_dim/": "/zh/isa/instructions/c_b_dim/",
+ "/isa/instructions/c_b_dimi/": "/zh/isa/instructions/c_b_dimi/",
+ "/isa/instructions/c_bstart/": "/zh/isa/instructions/c_bstart/",
+ "/isa/instructions/c_bstart_fp/": "/zh/isa/instructions/c_bstart_fp/",
+ "/isa/instructions/c_bstart_mpar/": "/zh/isa/instructions/c_bstart_mpar/",
+ "/isa/instructions/c_bstart_mseq/": "/zh/isa/instructions/c_bstart_mseq/",
+ "/isa/instructions/c_bstart_std/": "/zh/isa/instructions/c_bstart_std/",
+ "/isa/instructions/c_bstart_sys/": "/zh/isa/instructions/c_bstart_sys/",
+ "/isa/instructions/c_bstart_vpar/": "/zh/isa/instructions/c_bstart_vpar/",
+ "/isa/instructions/c_bstart_vseq/": "/zh/isa/instructions/c_bstart_vseq/",
+ "/isa/instructions/c_bstop/": "/zh/isa/instructions/c_bstop/",
+ "/isa/instructions/c_cmp_eqi/": "/zh/isa/instructions/c_cmp_eqi/",
+ "/isa/instructions/c_cmp_nei/": "/zh/isa/instructions/c_cmp_nei/",
+ "/isa/instructions/c_ebreak/": "/zh/isa/instructions/c_ebreak/",
+ "/isa/instructions/c_ldi/": "/zh/isa/instructions/c_ldi/",
+ "/isa/instructions/c_lwi/": "/zh/isa/instructions/c_lwi/",
+ "/isa/instructions/c_movi/": "/zh/isa/instructions/c_movi/",
+ "/isa/instructions/c_movr/": "/zh/isa/instructions/c_movr/",
+ "/isa/instructions/c_or/": "/zh/isa/instructions/c_or/",
+ "/isa/instructions/c_sdi/": "/zh/isa/instructions/c_sdi/",
+ "/isa/instructions/c_setc_eq/": "/zh/isa/instructions/c_setc_eq/",
+ "/isa/instructions/c_setc_ne/": "/zh/isa/instructions/c_setc_ne/",
+ "/isa/instructions/c_setc_tgt/": "/zh/isa/instructions/c_setc_tgt/",
+ "/isa/instructions/c_setret/": "/zh/isa/instructions/c_setret/",
+ "/isa/instructions/c_sext_b/": "/zh/isa/instructions/c_sext_b/",
+ "/isa/instructions/c_sext_h/": "/zh/isa/instructions/c_sext_h/",
+ "/isa/instructions/c_sext_w/": "/zh/isa/instructions/c_sext_w/",
+ "/isa/instructions/c_slli/": "/zh/isa/instructions/c_slli/",
+ "/isa/instructions/c_srli/": "/zh/isa/instructions/c_srli/",
+ "/isa/instructions/c_ssrget/": "/zh/isa/instructions/c_ssrget/",
+ "/isa/instructions/c_sub/": "/zh/isa/instructions/c_sub/",
+ "/isa/instructions/c_swi/": "/zh/isa/instructions/c_swi/",
+ "/isa/instructions/c_zext_b/": "/zh/isa/instructions/c_zext_b/",
+ "/isa/instructions/c_zext_h/": "/zh/isa/instructions/c_zext_h/",
+ "/isa/instructions/c_zext_w/": "/zh/isa/instructions/c_zext_w/",
+ "/isa/instructions/clz/": "/zh/isa/instructions/clz/",
+ "/isa/instructions/cmp_and/": "/zh/isa/instructions/cmp_and/",
+ "/isa/instructions/cmp_andi/": "/zh/isa/instructions/cmp_andi/",
+ "/isa/instructions/cmp_eq/": "/zh/isa/instructions/cmp_eq/",
+ "/isa/instructions/cmp_eqi/": "/zh/isa/instructions/cmp_eqi/",
+ "/isa/instructions/cmp_ge/": "/zh/isa/instructions/cmp_ge/",
+ "/isa/instructions/cmp_gei/": "/zh/isa/instructions/cmp_gei/",
+ "/isa/instructions/cmp_geu/": "/zh/isa/instructions/cmp_geu/",
+ "/isa/instructions/cmp_geui/": "/zh/isa/instructions/cmp_geui/",
+ "/isa/instructions/cmp_lt/": "/zh/isa/instructions/cmp_lt/",
+ "/isa/instructions/cmp_lti/": "/zh/isa/instructions/cmp_lti/",
+ "/isa/instructions/cmp_ltu/": "/zh/isa/instructions/cmp_ltu/",
+ "/isa/instructions/cmp_ltui/": "/zh/isa/instructions/cmp_ltui/",
+ "/isa/instructions/cmp_ne/": "/zh/isa/instructions/cmp_ne/",
+ "/isa/instructions/cmp_nei/": "/zh/isa/instructions/cmp_nei/",
+ "/isa/instructions/cmp_or/": "/zh/isa/instructions/cmp_or/",
+ "/isa/instructions/cmp_ori/": "/zh/isa/instructions/cmp_ori/",
+ "/isa/instructions/csel/": "/zh/isa/instructions/csel/",
+ "/isa/instructions/ctz/": "/zh/isa/instructions/ctz/",
+ "/isa/instructions/dc_cisw/": "/zh/isa/instructions/dc_cisw/",
+ "/isa/instructions/dc_civa/": "/zh/isa/instructions/dc_civa/",
+ "/isa/instructions/dc_csw/": "/zh/isa/instructions/dc_csw/",
+ "/isa/instructions/dc_cva/": "/zh/isa/instructions/dc_cva/",
+ "/isa/instructions/dc_iall/": "/zh/isa/instructions/dc_iall/",
+ "/isa/instructions/dc_isw/": "/zh/isa/instructions/dc_isw/",
+ "/isa/instructions/dc_iva/": "/zh/isa/instructions/dc_iva/",
+ "/isa/instructions/dc_zva/": "/zh/isa/instructions/dc_zva/",
+ "/isa/instructions/div/": "/zh/isa/instructions/div/",
+ "/isa/instructions/divu/": "/zh/isa/instructions/divu/",
+ "/isa/instructions/divuw/": "/zh/isa/instructions/divuw/",
+ "/isa/instructions/divw/": "/zh/isa/instructions/divw/",
+ "/isa/instructions/ebreak/": "/zh/isa/instructions/ebreak/",
+ "/isa/instructions/ercov/": "/zh/isa/instructions/ercov/",
+ "/isa/instructions/esave/": "/zh/isa/instructions/esave/",
+ "/isa/instructions/fabs/": "/zh/isa/instructions/fabs/",
+ "/isa/instructions/fadd/": "/zh/isa/instructions/fadd/",
+ "/isa/instructions/fcvt/": "/zh/isa/instructions/fcvt/",
+ "/isa/instructions/fcvta/": "/zh/isa/instructions/fcvta/",
+ "/isa/instructions/fcvtm/": "/zh/isa/instructions/fcvtm/",
+ "/isa/instructions/fcvtn/": "/zh/isa/instructions/fcvtn/",
+ "/isa/instructions/fcvtp/": "/zh/isa/instructions/fcvtp/",
+ "/isa/instructions/fcvtz/": "/zh/isa/instructions/fcvtz/",
+ "/isa/instructions/fdiv/": "/zh/isa/instructions/fdiv/",
+ "/isa/instructions/fence_d/": "/zh/isa/instructions/fence_d/",
+ "/isa/instructions/fence_i/": "/zh/isa/instructions/fence_i/",
+ "/isa/instructions/fentry/": "/zh/isa/instructions/fentry/",
+ "/isa/instructions/feq/": "/zh/isa/instructions/feq/",
+ "/isa/instructions/feqs/": "/zh/isa/instructions/feqs/",
+ "/isa/instructions/fexit/": "/zh/isa/instructions/fexit/",
+ "/isa/instructions/fexp/": "/zh/isa/instructions/fexp/",
+ "/isa/instructions/fge/": "/zh/isa/instructions/fge/",
+ "/isa/instructions/fges/": "/zh/isa/instructions/fges/",
+ "/isa/instructions/flt/": "/zh/isa/instructions/flt/",
+ "/isa/instructions/flts/": "/zh/isa/instructions/flts/",
+ "/isa/instructions/fmadd/": "/zh/isa/instructions/fmadd/",
+ "/isa/instructions/fmax/": "/zh/isa/instructions/fmax/",
+ "/isa/instructions/fmin/": "/zh/isa/instructions/fmin/",
+ "/isa/instructions/fmsub/": "/zh/isa/instructions/fmsub/",
+ "/isa/instructions/fmul/": "/zh/isa/instructions/fmul/",
+ "/isa/instructions/fne/": "/zh/isa/instructions/fne/",
+ "/isa/instructions/fnes/": "/zh/isa/instructions/fnes/",
+ "/isa/instructions/fnmadd/": "/zh/isa/instructions/fnmadd/",
+ "/isa/instructions/fnmsub/": "/zh/isa/instructions/fnmsub/",
+ "/isa/instructions/frecip/": "/zh/isa/instructions/frecip/",
+ "/isa/instructions/fret_ra/": "/zh/isa/instructions/fret_ra/",
+ "/isa/instructions/fret_stk/": "/zh/isa/instructions/fret_stk/",
+ "/isa/instructions/fsqrt/": "/zh/isa/instructions/fsqrt/",
+ "/isa/instructions/fsub/": "/zh/isa/instructions/fsub/",
+ "/isa/instructions/hl_addi/": "/zh/isa/instructions/hl_addi/",
+ "/isa/instructions/hl_addiw/": "/zh/isa/instructions/hl_addiw/",
+ "/isa/instructions/hl_addtpc/": "/zh/isa/instructions/hl_addtpc/",
+ "/isa/instructions/hl_andi/": "/zh/isa/instructions/hl_andi/",
+ "/isa/instructions/hl_andiw/": "/zh/isa/instructions/hl_andiw/",
+ "/isa/instructions/hl_bfi/": "/zh/isa/instructions/hl_bfi/",
+ "/isa/instructions/hl_bstart_call/": "/zh/isa/instructions/hl_bstart_call/",
+ "/isa/instructions/hl_bstart_fp/": "/zh/isa/instructions/hl_bstart_fp/",
+ "/isa/instructions/hl_bstart_std/": "/zh/isa/instructions/hl_bstart_std/",
+ "/isa/instructions/hl_bstart_sys/": "/zh/isa/instructions/hl_bstart_sys/",
+ "/isa/instructions/hl_casb/": "/zh/isa/instructions/hl_casb/",
+ "/isa/instructions/hl_casd/": "/zh/isa/instructions/hl_casd/",
+ "/isa/instructions/hl_cash/": "/zh/isa/instructions/hl_cash/",
+ "/isa/instructions/hl_casw/": "/zh/isa/instructions/hl_casw/",
+ "/isa/instructions/hl_ccat/": "/zh/isa/instructions/hl_ccat/",
+ "/isa/instructions/hl_ccatw/": "/zh/isa/instructions/hl_ccatw/",
+ "/isa/instructions/hl_cmp_andi/": "/zh/isa/instructions/hl_cmp_andi/",
+ "/isa/instructions/hl_cmp_eqi/": "/zh/isa/instructions/hl_cmp_eqi/",
+ "/isa/instructions/hl_cmp_gei/": "/zh/isa/instructions/hl_cmp_gei/",
+ "/isa/instructions/hl_cmp_geui/": "/zh/isa/instructions/hl_cmp_geui/",
+ "/isa/instructions/hl_cmp_lti/": "/zh/isa/instructions/hl_cmp_lti/",
+ "/isa/instructions/hl_cmp_ltui/": "/zh/isa/instructions/hl_cmp_ltui/",
+ "/isa/instructions/hl_cmp_nei/": "/zh/isa/instructions/hl_cmp_nei/",
+ "/isa/instructions/hl_cmp_ori/": "/zh/isa/instructions/hl_cmp_ori/",
+ "/isa/instructions/hl_div/": "/zh/isa/instructions/hl_div/",
+ "/isa/instructions/hl_divu/": "/zh/isa/instructions/hl_divu/",
+ "/isa/instructions/hl_divuw/": "/zh/isa/instructions/hl_divuw/",
+ "/isa/instructions/hl_divw/": "/zh/isa/instructions/hl_divw/",
+ "/isa/instructions/hl_lb_pcr/": "/zh/isa/instructions/hl_lb_pcr/",
+ "/isa/instructions/hl_lb_po/": "/zh/isa/instructions/hl_lb_po/",
+ "/isa/instructions/hl_lb_pr/": "/zh/isa/instructions/hl_lb_pr/",
+ "/isa/instructions/hl_lbi/": "/zh/isa/instructions/hl_lbi/",
+ "/isa/instructions/hl_lbi_po/": "/zh/isa/instructions/hl_lbi_po/",
+ "/isa/instructions/hl_lbi_pr/": "/zh/isa/instructions/hl_lbi_pr/",
+ "/isa/instructions/hl_lbip/": "/zh/isa/instructions/hl_lbip/",
+ "/isa/instructions/hl_lbp/": "/zh/isa/instructions/hl_lbp/",
+ "/isa/instructions/hl_lbu_pcr/": "/zh/isa/instructions/hl_lbu_pcr/",
+ "/isa/instructions/hl_lbu_po/": "/zh/isa/instructions/hl_lbu_po/",
+ "/isa/instructions/hl_lbu_pr/": "/zh/isa/instructions/hl_lbu_pr/",
+ "/isa/instructions/hl_lbui/": "/zh/isa/instructions/hl_lbui/",
+ "/isa/instructions/hl_lbui_po/": "/zh/isa/instructions/hl_lbui_po/",
+ "/isa/instructions/hl_lbui_pr/": "/zh/isa/instructions/hl_lbui_pr/",
+ "/isa/instructions/hl_lbuip/": "/zh/isa/instructions/hl_lbuip/",
+ "/isa/instructions/hl_lbup/": "/zh/isa/instructions/hl_lbup/",
+ "/isa/instructions/hl_ld_pcr/": "/zh/isa/instructions/hl_ld_pcr/",
+ "/isa/instructions/hl_ld_po/": "/zh/isa/instructions/hl_ld_po/",
+ "/isa/instructions/hl_ld_pr/": "/zh/isa/instructions/hl_ld_pr/",
+ "/isa/instructions/hl_ldi/": "/zh/isa/instructions/hl_ldi/",
+ "/isa/instructions/hl_ldi_po/": "/zh/isa/instructions/hl_ldi_po/",
+ "/isa/instructions/hl_ldi_pr/": "/zh/isa/instructions/hl_ldi_pr/",
+ "/isa/instructions/hl_ldi_u/": "/zh/isa/instructions/hl_ldi_u/",
+ "/isa/instructions/hl_ldi_upo/": "/zh/isa/instructions/hl_ldi_upo/",
+ "/isa/instructions/hl_ldi_upr/": "/zh/isa/instructions/hl_ldi_upr/",
+ "/isa/instructions/hl_ldip/": "/zh/isa/instructions/hl_ldip/",
+ "/isa/instructions/hl_ldip_u/": "/zh/isa/instructions/hl_ldip_u/",
+ "/isa/instructions/hl_ldp/": "/zh/isa/instructions/hl_ldp/",
+ "/isa/instructions/hl_lh_pcr/": "/zh/isa/instructions/hl_lh_pcr/",
+ "/isa/instructions/hl_lh_po/": "/zh/isa/instructions/hl_lh_po/",
+ "/isa/instructions/hl_lh_pr/": "/zh/isa/instructions/hl_lh_pr/",
+ "/isa/instructions/hl_lhi/": "/zh/isa/instructions/hl_lhi/",
+ "/isa/instructions/hl_lhi_po/": "/zh/isa/instructions/hl_lhi_po/",
+ "/isa/instructions/hl_lhi_pr/": "/zh/isa/instructions/hl_lhi_pr/",
+ "/isa/instructions/hl_lhi_u/": "/zh/isa/instructions/hl_lhi_u/",
+ "/isa/instructions/hl_lhi_upo/": "/zh/isa/instructions/hl_lhi_upo/",
+ "/isa/instructions/hl_lhi_upr/": "/zh/isa/instructions/hl_lhi_upr/",
+ "/isa/instructions/hl_lhip/": "/zh/isa/instructions/hl_lhip/",
+ "/isa/instructions/hl_lhip_u/": "/zh/isa/instructions/hl_lhip_u/",
+ "/isa/instructions/hl_lhp/": "/zh/isa/instructions/hl_lhp/",
+ "/isa/instructions/hl_lhu_pcr/": "/zh/isa/instructions/hl_lhu_pcr/",
+ "/isa/instructions/hl_lhu_po/": "/zh/isa/instructions/hl_lhu_po/",
+ "/isa/instructions/hl_lhu_pr/": "/zh/isa/instructions/hl_lhu_pr/",
+ "/isa/instructions/hl_lhui/": "/zh/isa/instructions/hl_lhui/",
+ "/isa/instructions/hl_lhui_po/": "/zh/isa/instructions/hl_lhui_po/",
+ "/isa/instructions/hl_lhui_pr/": "/zh/isa/instructions/hl_lhui_pr/",
+ "/isa/instructions/hl_lhui_u/": "/zh/isa/instructions/hl_lhui_u/",
+ "/isa/instructions/hl_lhui_upo/": "/zh/isa/instructions/hl_lhui_upo/",
+ "/isa/instructions/hl_lhui_upr/": "/zh/isa/instructions/hl_lhui_upr/",
+ "/isa/instructions/hl_lhuip/": "/zh/isa/instructions/hl_lhuip/",
+ "/isa/instructions/hl_lhuip_u/": "/zh/isa/instructions/hl_lhuip_u/",
+ "/isa/instructions/hl_lhup/": "/zh/isa/instructions/hl_lhup/",
+ "/isa/instructions/hl_lis/": "/zh/isa/instructions/hl_lis/",
+ "/isa/instructions/hl_liu/": "/zh/isa/instructions/hl_liu/",
+ "/isa/instructions/hl_lui/": "/zh/isa/instructions/hl_lui/",
+ "/isa/instructions/hl_lw_pcr/": "/zh/isa/instructions/hl_lw_pcr/",
+ "/isa/instructions/hl_lw_po/": "/zh/isa/instructions/hl_lw_po/",
+ "/isa/instructions/hl_lw_pr/": "/zh/isa/instructions/hl_lw_pr/",
+ "/isa/instructions/hl_lwi/": "/zh/isa/instructions/hl_lwi/",
+ "/isa/instructions/hl_lwi_po/": "/zh/isa/instructions/hl_lwi_po/",
+ "/isa/instructions/hl_lwi_pr/": "/zh/isa/instructions/hl_lwi_pr/",
+ "/isa/instructions/hl_lwi_u/": "/zh/isa/instructions/hl_lwi_u/",
+ "/isa/instructions/hl_lwi_upo/": "/zh/isa/instructions/hl_lwi_upo/",
+ "/isa/instructions/hl_lwi_upr/": "/zh/isa/instructions/hl_lwi_upr/",
+ "/isa/instructions/hl_lwip/": "/zh/isa/instructions/hl_lwip/",
+ "/isa/instructions/hl_lwip_u/": "/zh/isa/instructions/hl_lwip_u/",
+ "/isa/instructions/hl_lwp/": "/zh/isa/instructions/hl_lwp/",
+ "/isa/instructions/hl_lwu_pcr/": "/zh/isa/instructions/hl_lwu_pcr/",
+ "/isa/instructions/hl_lwu_po/": "/zh/isa/instructions/hl_lwu_po/",
+ "/isa/instructions/hl_lwu_pr/": "/zh/isa/instructions/hl_lwu_pr/",
+ "/isa/instructions/hl_lwui/": "/zh/isa/instructions/hl_lwui/",
+ "/isa/instructions/hl_lwui_po/": "/zh/isa/instructions/hl_lwui_po/",
+ "/isa/instructions/hl_lwui_pr/": "/zh/isa/instructions/hl_lwui_pr/",
+ "/isa/instructions/hl_lwui_u/": "/zh/isa/instructions/hl_lwui_u/",
+ "/isa/instructions/hl_lwui_upo/": "/zh/isa/instructions/hl_lwui_upo/",
+ "/isa/instructions/hl_lwui_upr/": "/zh/isa/instructions/hl_lwui_upr/",
+ "/isa/instructions/hl_lwuip/": "/zh/isa/instructions/hl_lwuip/",
+ "/isa/instructions/hl_lwuip_u/": "/zh/isa/instructions/hl_lwuip_u/",
+ "/isa/instructions/hl_lwup/": "/zh/isa/instructions/hl_lwup/",
+ "/isa/instructions/hl_madd/": "/zh/isa/instructions/hl_madd/",
+ "/isa/instructions/hl_maddw/": "/zh/isa/instructions/hl_maddw/",
+ "/isa/instructions/hl_miadd/": "/zh/isa/instructions/hl_miadd/",
+ "/isa/instructions/hl_misub/": "/zh/isa/instructions/hl_misub/",
+ "/isa/instructions/hl_mul/": "/zh/isa/instructions/hl_mul/",
+ "/isa/instructions/hl_mulu/": "/zh/isa/instructions/hl_mulu/",
+ "/isa/instructions/hl_ori/": "/zh/isa/instructions/hl_ori/",
+ "/isa/instructions/hl_oriw/": "/zh/isa/instructions/hl_oriw/",
+ "/isa/instructions/hl_prf/": "/zh/isa/instructions/hl_prf/",
+ "/isa/instructions/hl_prf_a/": "/zh/isa/instructions/hl_prf_a/",
+ "/isa/instructions/hl_prfi_u/": "/zh/isa/instructions/hl_prfi_u/",
+ "/isa/instructions/hl_prfi_ua/": "/zh/isa/instructions/hl_prfi_ua/",
+ "/isa/instructions/hl_qmt/": "/zh/isa/instructions/hl_qmt/",
+ "/isa/instructions/hl_qpop/": "/zh/isa/instructions/hl_qpop/",
+ "/isa/instructions/hl_qpush/": "/zh/isa/instructions/hl_qpush/",
+ "/isa/instructions/hl_rem/": "/zh/isa/instructions/hl_rem/",
+ "/isa/instructions/hl_remu/": "/zh/isa/instructions/hl_remu/",
+ "/isa/instructions/hl_remuw/": "/zh/isa/instructions/hl_remuw/",
+ "/isa/instructions/hl_remw/": "/zh/isa/instructions/hl_remw/",
+ "/isa/instructions/hl_sb_pcr/": "/zh/isa/instructions/hl_sb_pcr/",
+ "/isa/instructions/hl_sb_po/": "/zh/isa/instructions/hl_sb_po/",
+ "/isa/instructions/hl_sb_pr/": "/zh/isa/instructions/hl_sb_pr/",
+ "/isa/instructions/hl_sbi/": "/zh/isa/instructions/hl_sbi/",
+ "/isa/instructions/hl_sbi_po/": "/zh/isa/instructions/hl_sbi_po/",
+ "/isa/instructions/hl_sbi_pr/": "/zh/isa/instructions/hl_sbi_pr/",
+ "/isa/instructions/hl_sbip/": "/zh/isa/instructions/hl_sbip/",
+ "/isa/instructions/hl_sbp/": "/zh/isa/instructions/hl_sbp/",
+ "/isa/instructions/hl_sd_pcr/": "/zh/isa/instructions/hl_sd_pcr/",
+ "/isa/instructions/hl_sd_po/": "/zh/isa/instructions/hl_sd_po/",
+ "/isa/instructions/hl_sd_pr/": "/zh/isa/instructions/hl_sd_pr/",
+ "/isa/instructions/hl_sd_upo/": "/zh/isa/instructions/hl_sd_upo/",
+ "/isa/instructions/hl_sd_upr/": "/zh/isa/instructions/hl_sd_upr/",
+ "/isa/instructions/hl_sdi/": "/zh/isa/instructions/hl_sdi/",
+ "/isa/instructions/hl_sdi_po/": "/zh/isa/instructions/hl_sdi_po/",
+ "/isa/instructions/hl_sdi_pr/": "/zh/isa/instructions/hl_sdi_pr/",
+ "/isa/instructions/hl_sdi_u/": "/zh/isa/instructions/hl_sdi_u/",
+ "/isa/instructions/hl_sdi_upo/": "/zh/isa/instructions/hl_sdi_upo/",
+ "/isa/instructions/hl_sdi_upr/": "/zh/isa/instructions/hl_sdi_upr/",
+ "/isa/instructions/hl_sdip/": "/zh/isa/instructions/hl_sdip/",
+ "/isa/instructions/hl_sdip_u/": "/zh/isa/instructions/hl_sdip_u/",
+ "/isa/instructions/hl_sdp/": "/zh/isa/instructions/hl_sdp/",
+ "/isa/instructions/hl_sdp_u/": "/zh/isa/instructions/hl_sdp_u/",
+ "/isa/instructions/hl_setc_andi/": "/zh/isa/instructions/hl_setc_andi/",
+ "/isa/instructions/hl_setc_eqi/": "/zh/isa/instructions/hl_setc_eqi/",
+ "/isa/instructions/hl_setc_gei/": "/zh/isa/instructions/hl_setc_gei/",
+ "/isa/instructions/hl_setc_geui/": "/zh/isa/instructions/hl_setc_geui/",
+ "/isa/instructions/hl_setc_lti/": "/zh/isa/instructions/hl_setc_lti/",
+ "/isa/instructions/hl_setc_ltui/": "/zh/isa/instructions/hl_setc_ltui/",
+ "/isa/instructions/hl_setc_nei/": "/zh/isa/instructions/hl_setc_nei/",
+ "/isa/instructions/hl_setc_ori/": "/zh/isa/instructions/hl_setc_ori/",
+ "/isa/instructions/hl_setret/": "/zh/isa/instructions/hl_setret/",
+ "/isa/instructions/hl_sh_pcr/": "/zh/isa/instructions/hl_sh_pcr/",
+ "/isa/instructions/hl_sh_po/": "/zh/isa/instructions/hl_sh_po/",
+ "/isa/instructions/hl_sh_pr/": "/zh/isa/instructions/hl_sh_pr/",
+ "/isa/instructions/hl_sh_upo/": "/zh/isa/instructions/hl_sh_upo/",
+ "/isa/instructions/hl_sh_upr/": "/zh/isa/instructions/hl_sh_upr/",
+ "/isa/instructions/hl_shi/": "/zh/isa/instructions/hl_shi/",
+ "/isa/instructions/hl_shi_po/": "/zh/isa/instructions/hl_shi_po/",
+ "/isa/instructions/hl_shi_pr/": "/zh/isa/instructions/hl_shi_pr/",
+ "/isa/instructions/hl_shi_u/": "/zh/isa/instructions/hl_shi_u/",
+ "/isa/instructions/hl_shi_upo/": "/zh/isa/instructions/hl_shi_upo/",
+ "/isa/instructions/hl_shi_upr/": "/zh/isa/instructions/hl_shi_upr/",
+ "/isa/instructions/hl_ship/": "/zh/isa/instructions/hl_ship/",
+ "/isa/instructions/hl_ship_u/": "/zh/isa/instructions/hl_ship_u/",
+ "/isa/instructions/hl_shp/": "/zh/isa/instructions/hl_shp/",
+ "/isa/instructions/hl_shp_u/": "/zh/isa/instructions/hl_shp_u/",
+ "/isa/instructions/hl_ssrget/": "/zh/isa/instructions/hl_ssrget/",
+ "/isa/instructions/hl_ssrset/": "/zh/isa/instructions/hl_ssrset/",
+ "/isa/instructions/hl_subi/": "/zh/isa/instructions/hl_subi/",
+ "/isa/instructions/hl_subiw/": "/zh/isa/instructions/hl_subiw/",
+ "/isa/instructions/hl_sw_pcr/": "/zh/isa/instructions/hl_sw_pcr/",
+ "/isa/instructions/hl_sw_po/": "/zh/isa/instructions/hl_sw_po/",
+ "/isa/instructions/hl_sw_pr/": "/zh/isa/instructions/hl_sw_pr/",
+ "/isa/instructions/hl_sw_upo/": "/zh/isa/instructions/hl_sw_upo/",
+ "/isa/instructions/hl_sw_upr/": "/zh/isa/instructions/hl_sw_upr/",
+ "/isa/instructions/hl_swi/": "/zh/isa/instructions/hl_swi/",
+ "/isa/instructions/hl_swi_po/": "/zh/isa/instructions/hl_swi_po/",
+ "/isa/instructions/hl_swi_pr/": "/zh/isa/instructions/hl_swi_pr/",
+ "/isa/instructions/hl_swi_u/": "/zh/isa/instructions/hl_swi_u/",
+ "/isa/instructions/hl_swi_upo/": "/zh/isa/instructions/hl_swi_upo/",
+ "/isa/instructions/hl_swi_upr/": "/zh/isa/instructions/hl_swi_upr/",
+ "/isa/instructions/hl_swip/": "/zh/isa/instructions/hl_swip/",
+ "/isa/instructions/hl_swip_u/": "/zh/isa/instructions/hl_swip_u/",
+ "/isa/instructions/hl_swp/": "/zh/isa/instructions/hl_swp/",
+ "/isa/instructions/hl_swp_u/": "/zh/isa/instructions/hl_swp_u/",
+ "/isa/instructions/hl_xori/": "/zh/isa/instructions/hl_xori/",
+ "/isa/instructions/hl_xoriw/": "/zh/isa/instructions/hl_xoriw/",
+ "/isa/instructions/ic_iall/": "/zh/isa/instructions/ic_iall/",
+ "/isa/instructions/ic_iva/": "/zh/isa/instructions/ic_iva/",
+ "/isa/instructions/j/": "/zh/isa/instructions/j/",
+ "/isa/instructions/jr/": "/zh/isa/instructions/jr/",
+ "/isa/instructions/lb/": "/zh/isa/instructions/lb/",
+ "/isa/instructions/lb_pcr/": "/zh/isa/instructions/lb_pcr/",
+ "/isa/instructions/lbi/": "/zh/isa/instructions/lbi/",
+ "/isa/instructions/lbu/": "/zh/isa/instructions/lbu/",
+ "/isa/instructions/lbu_pcr/": "/zh/isa/instructions/lbu_pcr/",
+ "/isa/instructions/lbui/": "/zh/isa/instructions/lbui/",
+ "/isa/instructions/ld/": "/zh/isa/instructions/ld/",
+ "/isa/instructions/ld_add/": "/zh/isa/instructions/ld_add/",
+ "/isa/instructions/ld_and/": "/zh/isa/instructions/ld_and/",
+ "/isa/instructions/ld_or/": "/zh/isa/instructions/ld_or/",
+ "/isa/instructions/ld_pcr/": "/zh/isa/instructions/ld_pcr/",
+ "/isa/instructions/ld_smax/": "/zh/isa/instructions/ld_smax/",
+ "/isa/instructions/ld_smin/": "/zh/isa/instructions/ld_smin/",
+ "/isa/instructions/ld_umax/": "/zh/isa/instructions/ld_umax/",
+ "/isa/instructions/ld_umin/": "/zh/isa/instructions/ld_umin/",
+ "/isa/instructions/ld_xor/": "/zh/isa/instructions/ld_xor/",
+ "/isa/instructions/ldi/": "/zh/isa/instructions/ldi/",
+ "/isa/instructions/ldi_u/": "/zh/isa/instructions/ldi_u/",
+ "/isa/instructions/lh/": "/zh/isa/instructions/lh/",
+ "/isa/instructions/lh_pcr/": "/zh/isa/instructions/lh_pcr/",
+ "/isa/instructions/lhi/": "/zh/isa/instructions/lhi/",
+ "/isa/instructions/lhi_u/": "/zh/isa/instructions/lhi_u/",
+ "/isa/instructions/lhu/": "/zh/isa/instructions/lhu/",
+ "/isa/instructions/lhu_pcr/": "/zh/isa/instructions/lhu_pcr/",
+ "/isa/instructions/lhui/": "/zh/isa/instructions/lhui/",
+ "/isa/instructions/lhui_u/": "/zh/isa/instructions/lhui_u/",
+ "/isa/instructions/lr_b/": "/zh/isa/instructions/lr_b/",
+ "/isa/instructions/lr_d/": "/zh/isa/instructions/lr_d/",
+ "/isa/instructions/lr_h/": "/zh/isa/instructions/lr_h/",
+ "/isa/instructions/lr_w/": "/zh/isa/instructions/lr_w/",
+ "/isa/instructions/lsrget/": "/zh/isa/instructions/lsrget/",
+ "/isa/instructions/lui/": "/zh/isa/instructions/lui/",
+ "/isa/instructions/lw/": "/zh/isa/instructions/lw/",
+ "/isa/instructions/lw_add/": "/zh/isa/instructions/lw_add/",
+ "/isa/instructions/lw_and/": "/zh/isa/instructions/lw_and/",
+ "/isa/instructions/lw_or/": "/zh/isa/instructions/lw_or/",
+ "/isa/instructions/lw_pcr/": "/zh/isa/instructions/lw_pcr/",
+ "/isa/instructions/lw_smax/": "/zh/isa/instructions/lw_smax/",
+ "/isa/instructions/lw_smin/": "/zh/isa/instructions/lw_smin/",
+ "/isa/instructions/lw_umax/": "/zh/isa/instructions/lw_umax/",
+ "/isa/instructions/lw_umin/": "/zh/isa/instructions/lw_umin/",
+ "/isa/instructions/lw_xor/": "/zh/isa/instructions/lw_xor/",
+ "/isa/instructions/lwi/": "/zh/isa/instructions/lwi/",
+ "/isa/instructions/lwi_u/": "/zh/isa/instructions/lwi_u/",
+ "/isa/instructions/lwu/": "/zh/isa/instructions/lwu/",
+ "/isa/instructions/lwu_pcr/": "/zh/isa/instructions/lwu_pcr/",
+ "/isa/instructions/lwui/": "/zh/isa/instructions/lwui/",
+ "/isa/instructions/lwui_u/": "/zh/isa/instructions/lwui_u/",
+ "/isa/instructions/madd/": "/zh/isa/instructions/madd/",
+ "/isa/instructions/maddw/": "/zh/isa/instructions/maddw/",
+ "/isa/instructions/max/": "/zh/isa/instructions/max/",
+ "/isa/instructions/maxu/": "/zh/isa/instructions/maxu/",
+ "/isa/instructions/mcopy/": "/zh/isa/instructions/mcopy/",
+ "/isa/instructions/min/": "/zh/isa/instructions/min/",
+ "/isa/instructions/minu/": "/zh/isa/instructions/minu/",
+ "/isa/instructions/mset/": "/zh/isa/instructions/mset/",
+ "/isa/instructions/mul/": "/zh/isa/instructions/mul/",
+ "/isa/instructions/mulu/": "/zh/isa/instructions/mulu/",
+ "/isa/instructions/muluw/": "/zh/isa/instructions/muluw/",
+ "/isa/instructions/mulw/": "/zh/isa/instructions/mulw/",
+ "/isa/instructions/or/": "/zh/isa/instructions/or/",
+ "/isa/instructions/ori/": "/zh/isa/instructions/ori/",
+ "/isa/instructions/oriw/": "/zh/isa/instructions/oriw/",
+ "/isa/instructions/orw/": "/zh/isa/instructions/orw/",
+ "/isa/instructions/prf/": "/zh/isa/instructions/prf/",
+ "/isa/instructions/prfi_u/": "/zh/isa/instructions/prfi_u/",
+ "/isa/instructions/rem/": "/zh/isa/instructions/rem/",
+ "/isa/instructions/remu/": "/zh/isa/instructions/remu/",
+ "/isa/instructions/remuw/": "/zh/isa/instructions/remuw/",
+ "/isa/instructions/remw/": "/zh/isa/instructions/remw/",
+ "/isa/instructions/rev/": "/zh/isa/instructions/rev/",
+ "/isa/instructions/sb/": "/zh/isa/instructions/sb/",
+ "/isa/instructions/sb_pcr/": "/zh/isa/instructions/sb_pcr/",
+ "/isa/instructions/sbi/": "/zh/isa/instructions/sbi/",
+ "/isa/instructions/sc_b/": "/zh/isa/instructions/sc_b/",
+ "/isa/instructions/sc_d/": "/zh/isa/instructions/sc_d/",
+ "/isa/instructions/sc_h/": "/zh/isa/instructions/sc_h/",
+ "/isa/instructions/sc_w/": "/zh/isa/instructions/sc_w/",
+ "/isa/instructions/scvtf/": "/zh/isa/instructions/scvtf/",
+ "/isa/instructions/sd/": "/zh/isa/instructions/sd/",
+ "/isa/instructions/sd_add/": "/zh/isa/instructions/sd_add/",
+ "/isa/instructions/sd_and/": "/zh/isa/instructions/sd_and/",
+ "/isa/instructions/sd_or/": "/zh/isa/instructions/sd_or/",
+ "/isa/instructions/sd_pcr/": "/zh/isa/instructions/sd_pcr/",
+ "/isa/instructions/sd_smax/": "/zh/isa/instructions/sd_smax/",
+ "/isa/instructions/sd_smin/": "/zh/isa/instructions/sd_smin/",
+ "/isa/instructions/sd_u/": "/zh/isa/instructions/sd_u/",
+ "/isa/instructions/sd_umax/": "/zh/isa/instructions/sd_umax/",
+ "/isa/instructions/sd_umin/": "/zh/isa/instructions/sd_umin/",
+ "/isa/instructions/sd_xor/": "/zh/isa/instructions/sd_xor/",
+ "/isa/instructions/sdi/": "/zh/isa/instructions/sdi/",
+ "/isa/instructions/sdi_u/": "/zh/isa/instructions/sdi_u/",
+ "/isa/instructions/setc_and/": "/zh/isa/instructions/setc_and/",
+ "/isa/instructions/setc_andi/": "/zh/isa/instructions/setc_andi/",
+ "/isa/instructions/setc_eq/": "/zh/isa/instructions/setc_eq/",
+ "/isa/instructions/setc_eqi/": "/zh/isa/instructions/setc_eqi/",
+ "/isa/instructions/setc_ge/": "/zh/isa/instructions/setc_ge/",
+ "/isa/instructions/setc_gei/": "/zh/isa/instructions/setc_gei/",
+ "/isa/instructions/setc_geu/": "/zh/isa/instructions/setc_geu/",
+ "/isa/instructions/setc_geui/": "/zh/isa/instructions/setc_geui/",
+ "/isa/instructions/setc_lt/": "/zh/isa/instructions/setc_lt/",
+ "/isa/instructions/setc_lti/": "/zh/isa/instructions/setc_lti/",
+ "/isa/instructions/setc_ltu/": "/zh/isa/instructions/setc_ltu/",
+ "/isa/instructions/setc_ltui/": "/zh/isa/instructions/setc_ltui/",
+ "/isa/instructions/setc_ne/": "/zh/isa/instructions/setc_ne/",
+ "/isa/instructions/setc_nei/": "/zh/isa/instructions/setc_nei/",
+ "/isa/instructions/setc_or/": "/zh/isa/instructions/setc_or/",
+ "/isa/instructions/setc_ori/": "/zh/isa/instructions/setc_ori/",
+ "/isa/instructions/setc_tgt/": "/zh/isa/instructions/setc_tgt/",
+ "/isa/instructions/setret/": "/zh/isa/instructions/setret/",
+ "/isa/instructions/sh/": "/zh/isa/instructions/sh/",
+ "/isa/instructions/sh_pcr/": "/zh/isa/instructions/sh_pcr/",
+ "/isa/instructions/sh_u/": "/zh/isa/instructions/sh_u/",
+ "/isa/instructions/shi/": "/zh/isa/instructions/shi/",
+ "/isa/instructions/shi_u/": "/zh/isa/instructions/shi_u/",
+ "/isa/instructions/sll/": "/zh/isa/instructions/sll/",
+ "/isa/instructions/slli/": "/zh/isa/instructions/slli/",
+ "/isa/instructions/slliw/": "/zh/isa/instructions/slliw/",
+ "/isa/instructions/sllw/": "/zh/isa/instructions/sllw/",
+ "/isa/instructions/sra/": "/zh/isa/instructions/sra/",
+ "/isa/instructions/srai/": "/zh/isa/instructions/srai/",
+ "/isa/instructions/sraiw/": "/zh/isa/instructions/sraiw/",
+ "/isa/instructions/sraw/": "/zh/isa/instructions/sraw/",
+ "/isa/instructions/srl/": "/zh/isa/instructions/srl/",
+ "/isa/instructions/srli/": "/zh/isa/instructions/srli/",
+ "/isa/instructions/srliw/": "/zh/isa/instructions/srliw/",
+ "/isa/instructions/srlw/": "/zh/isa/instructions/srlw/",
+ "/isa/instructions/ssrget/": "/zh/isa/instructions/ssrget/",
+ "/isa/instructions/ssrset/": "/zh/isa/instructions/ssrset/",
+ "/isa/instructions/ssrswap/": "/zh/isa/instructions/ssrswap/",
+ "/isa/instructions/sub/": "/zh/isa/instructions/sub/",
+ "/isa/instructions/subi/": "/zh/isa/instructions/subi/",
+ "/isa/instructions/subiw/": "/zh/isa/instructions/subiw/",
+ "/isa/instructions/subw/": "/zh/isa/instructions/subw/",
+ "/isa/instructions/sw/": "/zh/isa/instructions/sw/",
+ "/isa/instructions/sw_add/": "/zh/isa/instructions/sw_add/",
+ "/isa/instructions/sw_and/": "/zh/isa/instructions/sw_and/",
+ "/isa/instructions/sw_or/": "/zh/isa/instructions/sw_or/",
+ "/isa/instructions/sw_pcr/": "/zh/isa/instructions/sw_pcr/",
+ "/isa/instructions/sw_smax/": "/zh/isa/instructions/sw_smax/",
+ "/isa/instructions/sw_smin/": "/zh/isa/instructions/sw_smin/",
+ "/isa/instructions/sw_u/": "/zh/isa/instructions/sw_u/",
+ "/isa/instructions/sw_umax/": "/zh/isa/instructions/sw_umax/",
+ "/isa/instructions/sw_umin/": "/zh/isa/instructions/sw_umin/",
+ "/isa/instructions/sw_xor/": "/zh/isa/instructions/sw_xor/",
+ "/isa/instructions/swapb/": "/zh/isa/instructions/swapb/",
+ "/isa/instructions/swapd/": "/zh/isa/instructions/swapd/",
+ "/isa/instructions/swaph/": "/zh/isa/instructions/swaph/",
+ "/isa/instructions/swapw/": "/zh/isa/instructions/swapw/",
+ "/isa/instructions/swi/": "/zh/isa/instructions/swi/",
+ "/isa/instructions/swi_u/": "/zh/isa/instructions/swi_u/",
+ "/isa/instructions/tlb_ia/": "/zh/isa/instructions/tlb_ia/",
+ "/isa/instructions/tlb_iall/": "/zh/isa/instructions/tlb_iall/",
+ "/isa/instructions/tlb_iav/": "/zh/isa/instructions/tlb_iav/",
+ "/isa/instructions/tlb_iv/": "/zh/isa/instructions/tlb_iv/",
+ "/isa/instructions/ucvtf/": "/zh/isa/instructions/ucvtf/",
+ "/isa/instructions/v_add/": "/zh/isa/instructions/v_add/",
+ "/isa/instructions/v_addi/": "/zh/isa/instructions/v_addi/",
+ "/isa/instructions/v_and/": "/zh/isa/instructions/v_and/",
+ "/isa/instructions/v_andi/": "/zh/isa/instructions/v_andi/",
+ "/isa/instructions/v_bcnt/": "/zh/isa/instructions/v_bcnt/",
+ "/isa/instructions/v_bic/": "/zh/isa/instructions/v_bic/",
+ "/isa/instructions/v_bis/": "/zh/isa/instructions/v_bis/",
+ "/isa/instructions/v_bxs/": "/zh/isa/instructions/v_bxs/",
+ "/isa/instructions/v_bxu/": "/zh/isa/instructions/v_bxu/",
+ "/isa/instructions/v_clz/": "/zh/isa/instructions/v_clz/",
+ "/isa/instructions/v_cmp_and/": "/zh/isa/instructions/v_cmp_and/",
+ "/isa/instructions/v_cmp_andi/": "/zh/isa/instructions/v_cmp_andi/",
+ "/isa/instructions/v_cmp_eq/": "/zh/isa/instructions/v_cmp_eq/",
+ "/isa/instructions/v_cmp_eqi/": "/zh/isa/instructions/v_cmp_eqi/",
+ "/isa/instructions/v_cmp_ge/": "/zh/isa/instructions/v_cmp_ge/",
+ "/isa/instructions/v_cmp_gei/": "/zh/isa/instructions/v_cmp_gei/",
+ "/isa/instructions/v_cmp_geu/": "/zh/isa/instructions/v_cmp_geu/",
+ "/isa/instructions/v_cmp_geui/": "/zh/isa/instructions/v_cmp_geui/",
+ "/isa/instructions/v_cmp_lt/": "/zh/isa/instructions/v_cmp_lt/",
+ "/isa/instructions/v_cmp_lti/": "/zh/isa/instructions/v_cmp_lti/",
+ "/isa/instructions/v_cmp_ltu/": "/zh/isa/instructions/v_cmp_ltu/",
+ "/isa/instructions/v_cmp_ltui/": "/zh/isa/instructions/v_cmp_ltui/",
+ "/isa/instructions/v_cmp_ne/": "/zh/isa/instructions/v_cmp_ne/",
+ "/isa/instructions/v_cmp_nei/": "/zh/isa/instructions/v_cmp_nei/",
+ "/isa/instructions/v_cmp_or/": "/zh/isa/instructions/v_cmp_or/",
+ "/isa/instructions/v_cmp_ori/": "/zh/isa/instructions/v_cmp_ori/",
+ "/isa/instructions/v_csel/": "/zh/isa/instructions/v_csel/",
+ "/isa/instructions/v_ctz/": "/zh/isa/instructions/v_ctz/",
+ "/isa/instructions/v_div/": "/zh/isa/instructions/v_div/",
+ "/isa/instructions/v_fabs/": "/zh/isa/instructions/v_fabs/",
+ "/isa/instructions/v_fadd/": "/zh/isa/instructions/v_fadd/",
+ "/isa/instructions/v_fclass/": "/zh/isa/instructions/v_fclass/",
+ "/isa/instructions/v_fcvt/": "/zh/isa/instructions/v_fcvt/",
+ "/isa/instructions/v_fcvti/": "/zh/isa/instructions/v_fcvti/",
+ "/isa/instructions/v_fdiv/": "/zh/isa/instructions/v_fdiv/",
+ "/isa/instructions/v_feq/": "/zh/isa/instructions/v_feq/",
+ "/isa/instructions/v_feqs/": "/zh/isa/instructions/v_feqs/",
+ "/isa/instructions/v_fexp/": "/zh/isa/instructions/v_fexp/",
+ "/isa/instructions/v_fge/": "/zh/isa/instructions/v_fge/",
+ "/isa/instructions/v_fges/": "/zh/isa/instructions/v_fges/",
+ "/isa/instructions/v_flt/": "/zh/isa/instructions/v_flt/",
+ "/isa/instructions/v_flts/": "/zh/isa/instructions/v_flts/",
+ "/isa/instructions/v_fmadd/": "/zh/isa/instructions/v_fmadd/",
+ "/isa/instructions/v_fmax/": "/zh/isa/instructions/v_fmax/",
+ "/isa/instructions/v_fmin/": "/zh/isa/instructions/v_fmin/",
+ "/isa/instructions/v_fmsub/": "/zh/isa/instructions/v_fmsub/",
+ "/isa/instructions/v_fmul/": "/zh/isa/instructions/v_fmul/",
+ "/isa/instructions/v_fne/": "/zh/isa/instructions/v_fne/",
+ "/isa/instructions/v_fnes/": "/zh/isa/instructions/v_fnes/",
+ "/isa/instructions/v_fnmadd/": "/zh/isa/instructions/v_fnmadd/",
+ "/isa/instructions/v_fnmsub/": "/zh/isa/instructions/v_fnmsub/",
+ "/isa/instructions/v_frecip/": "/zh/isa/instructions/v_frecip/",
+ "/isa/instructions/v_fsqrt/": "/zh/isa/instructions/v_fsqrt/",
+ "/isa/instructions/v_fsub/": "/zh/isa/instructions/v_fsub/",
+ "/isa/instructions/v_icvt/": "/zh/isa/instructions/v_icvt/",
+ "/isa/instructions/v_icvtf/": "/zh/isa/instructions/v_icvtf/",
+ "/isa/instructions/v_lb/": "/zh/isa/instructions/v_lb/",
+ "/isa/instructions/v_lb_brg/": "/zh/isa/instructions/v_lb_brg/",
+ "/isa/instructions/v_lbi/": "/zh/isa/instructions/v_lbi/",
+ "/isa/instructions/v_lbi_brg/": "/zh/isa/instructions/v_lbi_brg/",
+ "/isa/instructions/v_lbu/": "/zh/isa/instructions/v_lbu/",
+ "/isa/instructions/v_lbu_brg/": "/zh/isa/instructions/v_lbu_brg/",
+ "/isa/instructions/v_lbui/": "/zh/isa/instructions/v_lbui/",
+ "/isa/instructions/v_lbui_brg/": "/zh/isa/instructions/v_lbui_brg/",
+ "/isa/instructions/v_ld/": "/zh/isa/instructions/v_ld/",
+ "/isa/instructions/v_ld_add/": "/zh/isa/instructions/v_ld_add/",
+ "/isa/instructions/v_ld_and/": "/zh/isa/instructions/v_ld_and/",
+ "/isa/instructions/v_ld_brg/": "/zh/isa/instructions/v_ld_brg/",
+ "/isa/instructions/v_ld_max/": "/zh/isa/instructions/v_ld_max/",
+ "/isa/instructions/v_ld_min/": "/zh/isa/instructions/v_ld_min/",
+ "/isa/instructions/v_ld_or/": "/zh/isa/instructions/v_ld_or/",
+ "/isa/instructions/v_ld_xor/": "/zh/isa/instructions/v_ld_xor/",
+ "/isa/instructions/v_ldi/": "/zh/isa/instructions/v_ldi/",
+ "/isa/instructions/v_ldi_brg/": "/zh/isa/instructions/v_ldi_brg/",
+ "/isa/instructions/v_ldi_u/": "/zh/isa/instructions/v_ldi_u/",
+ "/isa/instructions/v_ldi_u_brg/": "/zh/isa/instructions/v_ldi_u_brg/",
+ "/isa/instructions/v_lh/": "/zh/isa/instructions/v_lh/",
+ "/isa/instructions/v_lh_brg/": "/zh/isa/instructions/v_lh_brg/",
+ "/isa/instructions/v_lhi/": "/zh/isa/instructions/v_lhi/",
+ "/isa/instructions/v_lhi_brg/": "/zh/isa/instructions/v_lhi_brg/",
+ "/isa/instructions/v_lhi_u/": "/zh/isa/instructions/v_lhi_u/",
+ "/isa/instructions/v_lhi_u_brg/": "/zh/isa/instructions/v_lhi_u_brg/",
+ "/isa/instructions/v_lhu/": "/zh/isa/instructions/v_lhu/",
+ "/isa/instructions/v_lhu_brg/": "/zh/isa/instructions/v_lhu_brg/",
+ "/isa/instructions/v_lhui/": "/zh/isa/instructions/v_lhui/",
+ "/isa/instructions/v_lhui_brg/": "/zh/isa/instructions/v_lhui_brg/",
+ "/isa/instructions/v_lhui_u/": "/zh/isa/instructions/v_lhui_u/",
+ "/isa/instructions/v_lhui_u_brg/": "/zh/isa/instructions/v_lhui_u_brg/",
+ "/isa/instructions/v_lw/": "/zh/isa/instructions/v_lw/",
+ "/isa/instructions/v_lw_add/": "/zh/isa/instructions/v_lw_add/",
+ "/isa/instructions/v_lw_and/": "/zh/isa/instructions/v_lw_and/",
+ "/isa/instructions/v_lw_brg/": "/zh/isa/instructions/v_lw_brg/",
+ "/isa/instructions/v_lw_max/": "/zh/isa/instructions/v_lw_max/",
+ "/isa/instructions/v_lw_min/": "/zh/isa/instructions/v_lw_min/",
+ "/isa/instructions/v_lw_or/": "/zh/isa/instructions/v_lw_or/",
+ "/isa/instructions/v_lw_xor/": "/zh/isa/instructions/v_lw_xor/",
+ "/isa/instructions/v_lwi/": "/zh/isa/instructions/v_lwi/",
+ "/isa/instructions/v_lwi_brg/": "/zh/isa/instructions/v_lwi_brg/",
+ "/isa/instructions/v_lwi_u/": "/zh/isa/instructions/v_lwi_u/",
+ "/isa/instructions/v_lwi_u_brg/": "/zh/isa/instructions/v_lwi_u_brg/",
+ "/isa/instructions/v_lwu/": "/zh/isa/instructions/v_lwu/",
+ "/isa/instructions/v_lwu_brg/": "/zh/isa/instructions/v_lwu_brg/",
+ "/isa/instructions/v_lwui/": "/zh/isa/instructions/v_lwui/",
+ "/isa/instructions/v_lwui_brg/": "/zh/isa/instructions/v_lwui_brg/",
+ "/isa/instructions/v_lwui_u/": "/zh/isa/instructions/v_lwui_u/",
+ "/isa/instructions/v_lwui_u_brg/": "/zh/isa/instructions/v_lwui_u_brg/",
+ "/isa/instructions/v_madd/": "/zh/isa/instructions/v_madd/",
+ "/isa/instructions/v_max/": "/zh/isa/instructions/v_max/",
+ "/isa/instructions/v_min/": "/zh/isa/instructions/v_min/",
+ "/isa/instructions/v_mul/": "/zh/isa/instructions/v_mul/",
+ "/isa/instructions/v_or/": "/zh/isa/instructions/v_or/",
+ "/isa/instructions/v_ori/": "/zh/isa/instructions/v_ori/",
+ "/isa/instructions/v_psel/": "/zh/isa/instructions/v_psel/",
+ "/isa/instructions/v_qpop/": "/zh/isa/instructions/v_qpop/",
+ "/isa/instructions/v_qpush/": "/zh/isa/instructions/v_qpush/",
+ "/isa/instructions/v_rdadd/": "/zh/isa/instructions/v_rdadd/",
+ "/isa/instructions/v_rdand/": "/zh/isa/instructions/v_rdand/",
+ "/isa/instructions/v_rdfadd/": "/zh/isa/instructions/v_rdfadd/",
+ "/isa/instructions/v_rdfmax/": "/zh/isa/instructions/v_rdfmax/",
+ "/isa/instructions/v_rdfmin/": "/zh/isa/instructions/v_rdfmin/",
+ "/isa/instructions/v_rdmax/": "/zh/isa/instructions/v_rdmax/",
+ "/isa/instructions/v_rdmin/": "/zh/isa/instructions/v_rdmin/",
+ "/isa/instructions/v_rdor/": "/zh/isa/instructions/v_rdor/",
+ "/isa/instructions/v_rdxor/": "/zh/isa/instructions/v_rdxor/",
+ "/isa/instructions/v_rem/": "/zh/isa/instructions/v_rem/",
+ "/isa/instructions/v_rev/": "/zh/isa/instructions/v_rev/",
+ "/isa/instructions/v_sb/": "/zh/isa/instructions/v_sb/",
+ "/isa/instructions/v_sb_brg/": "/zh/isa/instructions/v_sb_brg/",
+ "/isa/instructions/v_sbi/": "/zh/isa/instructions/v_sbi/",
+ "/isa/instructions/v_sbi_brg/": "/zh/isa/instructions/v_sbi_brg/",
+ "/isa/instructions/v_sd/": "/zh/isa/instructions/v_sd/",
+ "/isa/instructions/v_sd_add/": "/zh/isa/instructions/v_sd_add/",
+ "/isa/instructions/v_sd_and/": "/zh/isa/instructions/v_sd_and/",
+ "/isa/instructions/v_sd_brg/": "/zh/isa/instructions/v_sd_brg/",
+ "/isa/instructions/v_sd_max/": "/zh/isa/instructions/v_sd_max/",
+ "/isa/instructions/v_sd_min/": "/zh/isa/instructions/v_sd_min/",
+ "/isa/instructions/v_sd_or/": "/zh/isa/instructions/v_sd_or/",
+ "/isa/instructions/v_sd_u/": "/zh/isa/instructions/v_sd_u/",
+ "/isa/instructions/v_sd_u_brg/": "/zh/isa/instructions/v_sd_u_brg/",
+ "/isa/instructions/v_sd_xor/": "/zh/isa/instructions/v_sd_xor/",
+ "/isa/instructions/v_sdi/": "/zh/isa/instructions/v_sdi/",
+ "/isa/instructions/v_sdi_brg/": "/zh/isa/instructions/v_sdi_brg/",
+ "/isa/instructions/v_sdi_u/": "/zh/isa/instructions/v_sdi_u/",
+ "/isa/instructions/v_sdi_u_brg/": "/zh/isa/instructions/v_sdi_u_brg/",
+ "/isa/instructions/v_sh/": "/zh/isa/instructions/v_sh/",
+ "/isa/instructions/v_sh_brg/": "/zh/isa/instructions/v_sh_brg/",
+ "/isa/instructions/v_sh_u/": "/zh/isa/instructions/v_sh_u/",
+ "/isa/instructions/v_sh_u_brg/": "/zh/isa/instructions/v_sh_u_brg/",
+ "/isa/instructions/v_shfl_bfly/": "/zh/isa/instructions/v_shfl_bfly/",
+ "/isa/instructions/v_shfl_down/": "/zh/isa/instructions/v_shfl_down/",
+ "/isa/instructions/v_shfl_idx/": "/zh/isa/instructions/v_shfl_idx/",
+ "/isa/instructions/v_shfl_up/": "/zh/isa/instructions/v_shfl_up/",
+ "/isa/instructions/v_shfli_bfly/": "/zh/isa/instructions/v_shfli_bfly/",
+ "/isa/instructions/v_shfli_down/": "/zh/isa/instructions/v_shfli_down/",
+ "/isa/instructions/v_shfli_idx/": "/zh/isa/instructions/v_shfli_idx/",
+ "/isa/instructions/v_shfli_up/": "/zh/isa/instructions/v_shfli_up/",
+ "/isa/instructions/v_shi/": "/zh/isa/instructions/v_shi/",
+ "/isa/instructions/v_shi_brg/": "/zh/isa/instructions/v_shi_brg/",
+ "/isa/instructions/v_shi_u/": "/zh/isa/instructions/v_shi_u/",
+ "/isa/instructions/v_shi_u_brg/": "/zh/isa/instructions/v_shi_u_brg/",
+ "/isa/instructions/v_sll/": "/zh/isa/instructions/v_sll/",
+ "/isa/instructions/v_slli/": "/zh/isa/instructions/v_slli/",
+ "/isa/instructions/v_sra/": "/zh/isa/instructions/v_sra/",
+ "/isa/instructions/v_srai/": "/zh/isa/instructions/v_srai/",
+ "/isa/instructions/v_srl/": "/zh/isa/instructions/v_srl/",
+ "/isa/instructions/v_srli/": "/zh/isa/instructions/v_srli/",
+ "/isa/instructions/v_sub/": "/zh/isa/instructions/v_sub/",
+ "/isa/instructions/v_subi/": "/zh/isa/instructions/v_subi/",
+ "/isa/instructions/v_sw/": "/zh/isa/instructions/v_sw/",
+ "/isa/instructions/v_sw_add/": "/zh/isa/instructions/v_sw_add/",
+ "/isa/instructions/v_sw_and/": "/zh/isa/instructions/v_sw_and/",
+ "/isa/instructions/v_sw_brg/": "/zh/isa/instructions/v_sw_brg/",
+ "/isa/instructions/v_sw_max/": "/zh/isa/instructions/v_sw_max/",
+ "/isa/instructions/v_sw_min/": "/zh/isa/instructions/v_sw_min/",
+ "/isa/instructions/v_sw_or/": "/zh/isa/instructions/v_sw_or/",
+ "/isa/instructions/v_sw_u/": "/zh/isa/instructions/v_sw_u/",
+ "/isa/instructions/v_sw_u_brg/": "/zh/isa/instructions/v_sw_u_brg/",
+ "/isa/instructions/v_sw_xor/": "/zh/isa/instructions/v_sw_xor/",
+ "/isa/instructions/v_swi/": "/zh/isa/instructions/v_swi/",
+ "/isa/instructions/v_swi_brg/": "/zh/isa/instructions/v_swi_brg/",
+ "/isa/instructions/v_swi_u/": "/zh/isa/instructions/v_swi_u/",
+ "/isa/instructions/v_swi_u_brg/": "/zh/isa/instructions/v_swi_u_brg/",
+ "/isa/instructions/v_xor/": "/zh/isa/instructions/v_xor/",
+ "/isa/instructions/v_xori/": "/zh/isa/instructions/v_xori/",
+ "/isa/instructions/xb/": "/zh/isa/instructions/xb/",
+ "/isa/instructions/xor/": "/zh/isa/instructions/xor/",
+ "/isa/instructions/xori/": "/zh/isa/instructions/xori/",
+ "/isa/instructions/xoriw/": "/zh/isa/instructions/xoriw/",
+ "/isa/instructions/xorw/": "/zh/isa/instructions/xorw/",
+ "/isa/instset/baseExtInstrs/": "/zh/isa/instset/baseExtInstrs/",
+ "/isa/instset/baseInstrs/": "/zh/isa/instset/baseInstrs/",
+ "/isa/instset/compressInstrs/": "/zh/isa/instset/compressInstrs/",
+ "/isa/instset/haflLongInstrs/": "/zh/isa/instset/haflLongInstrs/",
+ "/isa/instset/longInstrs/": "/zh/isa/instset/longInstrs/",
+ "/isa/instset/standardInstrs/": "/zh/isa/instset/standardInstrs/",
+ "/isa/model/BCC/": "/zh/isa/model/BCC/",
+ "/isa/model/BCTRL/": "/zh/isa/model/BCTRL/",
+ "/isa/model/BIFU/": "/zh/isa/model/BIFU/",
+ "/isa/model/BIssue/": "/zh/isa/model/BIssue/",
+ "/isa/model/BROB/": "/zh/isa/model/BROB/",
+ "/isa/model/BRename/": "/zh/isa/model/BRename/",
+ "/isa/model/iex_dispatch/": "/zh/isa/model/iex_dispatch/",
+ "/isa/model/iex_issueq/": "/zh/isa/model/iex_issueq/",
+ "/isa/model/pe/": "/zh/isa/model/pe/",
+ "/isa/model/pe_ibp/": "/zh/isa/model/pe_ibp/",
+ "/isa/model/pe_ifu/": "/zh/isa/model/pe_ifu/",
+ "/isa/model/pe_rob/": "/zh/isa/model/pe_rob/",
+ "/isa/register/common/barg/": "/zh/isa/register/common/barg/",
+ "/isa/register/common/bpc/": "/zh/isa/register/common/bpc/",
+ "/isa/register/common/ggpr/": "/zh/isa/register/common/ggpr/",
+ "/isa/register/common/intro/": "/zh/isa/register/common/intro/",
+ "/isa/register/common/lgpr/": "/zh/isa/register/common/lgpr/",
+ "/isa/register/common/loop/": "/zh/isa/register/common/loop/",
+ "/isa/register/common/ltar/": "/zh/isa/register/common/ltar/",
+ "/isa/register/common/pred/": "/zh/isa/register/common/pred/",
+ "/isa/register/common/sgpr/": "/zh/isa/register/common/sgpr/",
+ "/isa/register/common/tilereg/": "/zh/isa/register/common/tilereg/",
+ "/isa/register/common/tpc/": "/zh/isa/register/common/tpc/",
+ "/isa/register/common/vgpr/": "/zh/isa/register/common/vgpr/",
+ "/isa/register/ssr/ACR_PARAM/": "/zh/isa/register/ssr/ACR_PARAM/",
+ "/isa/register/ssr/BLOCKID/": "/zh/isa/register/ssr/BLOCKID/",
+ "/isa/register/ssr/BLOCKNUM/": "/zh/isa/register/ssr/BLOCKNUM/",
+ "/isa/register/ssr/CSTATE/": "/zh/isa/register/ssr/CSTATE/",
+ "/isa/register/ssr/CW/": "/zh/isa/register/ssr/CW/",
+ "/isa/register/ssr/CYCLE/": "/zh/isa/register/ssr/CYCLE/",
+ "/isa/register/ssr/EBARG/": "/zh/isa/register/ssr/EBARG/",
+ "/isa/register/ssr/EBPC/": "/zh/isa/register/ssr/EBPC/",
+ "/isa/register/ssr/EBPCN/": "/zh/isa/register/ssr/EBPCN/",
+ "/isa/register/ssr/EBSTATEP/": "/zh/isa/register/ssr/EBSTATEP/",
+ "/isa/register/ssr/ECONFIG/": "/zh/isa/register/ssr/ECONFIG/",
+ "/isa/register/ssr/ECSTATE/": "/zh/isa/register/ssr/ECSTATE/",
+ "/isa/register/ssr/EOIEI/": "/zh/isa/register/ssr/EOIEI/",
+ "/isa/register/ssr/ETEMP/": "/zh/isa/register/ssr/ETEMP/",
+ "/isa/register/ssr/ETPC/": "/zh/isa/register/ssr/ETPC/",
+ "/isa/register/ssr/EVBASE/": "/zh/isa/register/ssr/EVBASE/",
+ "/isa/register/ssr/FUTO/": "/zh/isa/register/ssr/FUTO/",
+ "/isa/register/ssr/GP/": "/zh/isa/register/ssr/GP/",
+ "/isa/register/ssr/IPENDING/": "/zh/isa/register/ssr/IPENDING/",
+ "/isa/register/ssr/LCFR/": "/zh/isa/register/ssr/LCFR/",
+ "/isa/register/ssr/LCFR_EN/": "/zh/isa/register/ssr/LCFR_EN/",
+ "/isa/register/ssr/LXLCID/": "/zh/isa/register/ssr/LXLCID/",
+ "/isa/register/ssr/MMCONFIG/": "/zh/isa/register/ssr/MMCONFIG/",
+ "/isa/register/ssr/MMTBASE/": "/zh/isa/register/ssr/MMTBASE/",
+ "/isa/register/ssr/MSGB/": "/zh/isa/register/ssr/MSGB/",
+ "/isa/register/ssr/SYSCNT/": "/zh/isa/register/ssr/SYSCNT/",
+ "/isa/register/ssr/TIME/": "/zh/isa/register/ssr/TIME/",
+ "/isa/register/ssr/TIMER_TIME/": "/zh/isa/register/ssr/TIMER_TIME/",
+ "/isa/register/ssr/TIMER_TIMECMP/": "/zh/isa/register/ssr/TIMER_TIMECMP/",
+ "/isa/register/ssr/TOPEI/": "/zh/isa/register/ssr/TOPEI/",
+ "/isa/register/ssr/TP/": "/zh/isa/register/ssr/TP/",
+ "/isa/register/ssr/TR/": "/zh/isa/register/ssr/TR/",
+ "/isa/register/ssr/TRAPARG0/": "/zh/isa/register/ssr/TRAPARG0/",
+ "/isa/register/ssr/TRAPNO/": "/zh/isa/register/ssr/TRAPNO/",
+ "/isa/register/ssr/VENDOR/": "/zh/isa/register/ssr/VENDOR/",
+ "/isa/register/ssr/VERSION/": "/zh/isa/register/ssr/VERSION/",
+ "/isa/register/ssr/XBINFO/": "/zh/isa/register/ssr/XBINFO/",
+ "/isa/register/ssr/common/": "/zh/isa/register/ssr/common/",
+ "/isa/register/ssr/lightcore/": "/zh/isa/register/ssr/lightcore/",
+ "/isa/register/ssr/per-acr/": "/zh/isa/register/ssr/per-acr/",
+ "/isa/register/ssr/ssrintro/": "/zh/isa/register/ssr/ssrintro/",
+ "/isa/timer/": "/zh/isa/timer/",
+ "/memory/dcache/load_pipeline/": "/zh/memory/dcache/load_pipeline/",
+ "/memory/dcache/writeback_queue/": "/zh/memory/dcache/writeback_queue/",
+ "/memory/fu/load_pipeline/": "/zh/memory/fu/load_pipeline/",
+ "/memory/fu/store_pipeline/": "/zh/memory/fu/store_pipeline/",
+ "/memory/overview/": "/zh/memory/overview/",
+ "/misc/spec17int/": "/zh/misc/spec17int/",
+ "/pe/codetemplate/": "/zh/pe/codetemplate/",
+ "/pe/ope/": "/zh/pe/ope/",
+ "/performance/regUsageFrequency/": "/zh/performance/regUsageFrequency/",
+ "/performance/specint_analysis/": "/zh/performance/specint_analysis/",
+ "/performance/specint_runpoint/": "/zh/performance/specint_runpoint/",
+ "/performance/specint_temlblock_rate/": "/zh/performance/specint_temlblock_rate/",
+ "/performance/top-down/": "/zh/performance/top-down/",
+ "/project/README/": "/zh/project/README/",
+ "/project/maintainer-repin-checklist/": "/zh/project/maintainer-repin-checklist/",
+ "/project/navigation/": "/zh/project/navigation/",
+ "/project/new-agent-sop/": "/zh/project/new-agent-sop/",
+ "/project/omx-linxisa-playbook/": "/zh/project/omx-linxisa-playbook/",
+ "/project/omx-linxisa-prompt-templates/": "/zh/project/omx-linxisa-prompt-templates/",
+ "/project/repository-flow/": "/zh/project/repository-flow/",
+ "/project/superproject-bringup-methodology/": "/zh/project/superproject-bringup-methodology/",
+ "/reference/README/": "/zh/reference/README/",
+ "/reference/encoding_space_report/": "/zh/reference/encoding_space_report/",
+ "/reference/examples/README/": "/zh/reference/examples/README/",
+ "/reference/examples/v0.56/README/": "/zh/reference/examples/v0.56/README/",
+ "/reference/linxisa-assembly-agent-guide/": "/zh/reference/linxisa-assembly-agent-guide/",
+ "/reference/linxisa-call-ret-contract/": "/zh/reference/linxisa-call-ret-contract/",
+ "/releases/v0.3.0/": "/zh/releases/v0.3.0/",
+ "/releases/v0.56.2/": "/zh/releases/v0.56.2/",
+ "/white_paper/Chapter-2/": "/zh/white_paper/Chapter-2/",
+ "/white_paper/Chapter-3/": "/zh/white_paper/Chapter-3/",
+ "/white_paper/Chapter-4/": "/zh/white_paper/Chapter-4/",
+ "/white_paper/Chapter-5/": "/zh/white_paper/Chapter-5/",
+ "/white_paper/Chapter-6/": "/zh/white_paper/Chapter-6/",
+ "/white_paper/Chapter-7/": "/zh/white_paper/Chapter-7/",
+ "/white_paper/Chapter-8/": "/zh/white_paper/Chapter-8/",
+ "/white_paper/Chapter-9/": "/zh/white_paper/Chapter-9/",
+ "/white_paper/Intro/": "/zh/white_paper/Intro/",
+ "/white_paper_en/chapter1/": "/zh/white_paper_en/chapter1/",
+ "/white_paper_en/chapter2/": "/zh/white_paper_en/chapter2/",
+ "/white_paper_en/chapter3/": "/zh/white_paper_en/chapter3/",
+ "/white_paper_en/chapter4/": "/zh/white_paper_en/chapter4/",
+ "/white_paper_en/chapter5/": "/zh/white_paper_en/chapter5/",
+ "/white_paper_en/chapter6/": "/zh/white_paper_en/chapter6/",
+ "/white_paper_en/chapter7/": "/zh/white_paper_en/chapter7/",
+ "/zh/": "/",
+ "/zh/README/": "/README/",
+ "/zh/architecture/README/": "/architecture/README/",
+ "/zh/architecture/isa-manual/README/": "/architecture/isa-manual/README/",
+ "/zh/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/concurrent-ruby-1.3.6/README/": "/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/concurrent-ruby-1.3.6/README/",
+ "/zh/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/hashery-2.1.2/HISTORY/": "/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/hashery-2.1.2/HISTORY/",
+ "/zh/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/hashery-2.1.2/README/": "/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/hashery-2.1.2/README/",
+ "/zh/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/pdf-reader-2.15.1/README/": "/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/pdf-reader-2.15.1/README/",
+ "/zh/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/prawn-icon-3.0.0/CHANGELOG/": "/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/prawn-icon-3.0.0/CHANGELOG/",
+ "/zh/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/prawn-icon-3.0.0/README/": "/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/prawn-icon-3.0.0/README/",
+ "/zh/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/prawn-svg-0.32.0/README/": "/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/prawn-svg-0.32.0/README/",
+ "/zh/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/public_suffix-5.1.1/2.0-Upgrade/": "/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/public_suffix-5.1.1/2.0-Upgrade/",
+ "/zh/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/public_suffix-5.1.1/CHANGELOG/": "/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/public_suffix-5.1.1/CHANGELOG/",
+ "/zh/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/public_suffix-5.1.1/README/": "/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/public_suffix-5.1.1/README/",
+ "/zh/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/public_suffix-5.1.1/SECURITY/": "/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/public_suffix-5.1.1/SECURITY/",
+ "/zh/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/rexml-3.4.4/NEWS/": "/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/rexml-3.4.4/NEWS/",
+ "/zh/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/rexml-3.4.4/README/": "/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/rexml-3.4.4/README/",
+ "/zh/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/ruby-rc4-0.1.5/README/": "/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/ruby-rc4-0.1.5/README/",
+ "/zh/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/safe_yaml-1.0.5/CHANGES/": "/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/safe_yaml-1.0.5/CHANGES/",
+ "/zh/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/safe_yaml-1.0.5/README/": "/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/safe_yaml-1.0.5/README/",
+ "/zh/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/treetop-1.6.18/README/": "/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/treetop-1.6.18/README/",
+ "/zh/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/ttfunk-1.7.0/CHANGELOG/": "/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/ttfunk-1.7.0/CHANGELOG/",
+ "/zh/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/ttfunk-1.7.0/README/": "/architecture/isa-manual/vendor/bundle/ruby/2.6.0/gems/ttfunk-1.7.0/README/",
+ "/zh/architecture/linxcore-unified-ai-render-gpgpu/": "/architecture/linxcore-unified-ai-render-gpgpu/",
+ "/zh/architecture/linxcore/interfaces/": "/architecture/linxcore/interfaces/",
+ "/zh/architecture/linxcore/microarchitecture/": "/architecture/linxcore/microarchitecture/",
+ "/zh/architecture/linxcore/module-catalog/": "/architecture/linxcore/module-catalog/",
+ "/zh/architecture/linxcore/overview/": "/architecture/linxcore/overview/",
+ "/zh/architecture/linxcore/pipeline-stage-catalog/": "/architecture/linxcore/pipeline-stage-catalog/",
+ "/zh/architecture/linxcore/verification-matrix/": "/architecture/linxcore/verification-matrix/",
+ "/zh/architecture/research/linx-simt-alt-compiler-gap-analysis/": "/architecture/research/linx-simt-alt-compiler-gap-analysis/",
+ "/zh/architecture/v0.56-architecture-contract/": "/architecture/v0.56-architecture-contract/",
+ "/zh/architecture/v0.56-hardening-policy/": "/architecture/v0.56-hardening-policy/",
+ "/zh/architecture/v0.56-rendering-command-contract/": "/architecture/v0.56-rendering-command-contract/",
+ "/zh/architecture/v0.56-rendering-kernel-authoring/": "/architecture/v0.56-rendering-kernel-authoring/",
+ "/zh/architecture/v0.56-rendering-pto-contract/": "/architecture/v0.56-rendering-pto-contract/",
+ "/zh/architecture/v0.56-simt-compiler-contract-plan/": "/architecture/v0.56-simt-compiler-contract-plan/",
+ "/zh/architecture/v0.56-simt-compiler-contract/": "/architecture/v0.56-simt-compiler-contract/",
+ "/zh/architecture/v0.56-workload-engine-model/": "/architecture/v0.56-workload-engine-model/",
+ "/zh/backend/exu/": "/backend/exu/",
+ "/zh/backend/issue/": "/backend/issue/",
+ "/zh/backend/pe_rf/": "/backend/pe_rf/",
+ "/zh/backend/rob/": "/backend/rob/",
+ "/zh/backend/scheduler/": "/backend/scheduler/",
+ "/zh/background/": "/background/",
+ "/zh/bcc/bdecode/": "/bcc/bdecode/",
+ "/zh/bcc/bdispatch/": "/bcc/bdispatch/",
+ "/zh/bcc/bhcache/": "/bcc/bhcache/",
+ "/zh/bcc/bifu/": "/bcc/bifu/",
+ "/zh/bcc/bp/": "/bcc/bp/",
+ "/zh/bcc/bren/": "/bcc/bren/",
+ "/zh/bcc/brf/": "/bcc/brf/",
+ "/zh/bcc/brob/": "/bcc/brob/",
+ "/zh/bcc/overview/": "/bcc/overview/",
+ "/zh/bringup/ALIGNMENT_MATRIX/": "/bringup/ALIGNMENT_MATRIX/",
+ "/zh/bringup/AVS_CONTRACT/": "/bringup/AVS_CONTRACT/",
+ "/zh/bringup/CPP_BRINGUP_CONTRACT/": "/bringup/CPP_BRINGUP_CONTRACT/",
+ "/zh/bringup/CROSSSTACK_SKILLS_SUMMARY/": "/bringup/CROSSSTACK_SKILLS_SUMMARY/",
+ "/zh/bringup/GATE_STATUS/": "/bringup/GATE_STATUS/",
+ "/zh/bringup/GETTING_STARTED/": "/bringup/GETTING_STARTED/",
+ "/zh/bringup/ISA_GAP_ANALYSIS/": "/bringup/ISA_GAP_ANALYSIS/",
+ "/zh/bringup/LINX_ASM_ABI_UNWIND_CONTEXT_CHECKLIST/": "/bringup/LINX_ASM_ABI_UNWIND_CONTEXT_CHECKLIST/",
+ "/zh/bringup/MATURITY_PLAN/": "/bringup/MATURITY_PLAN/",
+ "/zh/bringup/PROGRESS/": "/bringup/PROGRESS/",
+ "/zh/bringup/README/": "/bringup/README/",
+ "/zh/bringup/SIMT_COMPILER_MATURITY_PLAN/": "/bringup/SIMT_COMPILER_MATURITY_PLAN/",
+ "/zh/bringup/SIMT_COMPILER_SUPPORTED_SUBSET/": "/bringup/SIMT_COMPILER_SUPPORTED_SUBSET/",
+ "/zh/bringup/SUPERPROJECT_BRINGUP_CHECKLIST/": "/bringup/SUPERPROJECT_BRINGUP_CHECKLIST/",
+ "/zh/bringup/agent_runs/checklists/architecture_docs/": "/bringup/agent_runs/checklists/architecture_docs/",
+ "/zh/bringup/agent_runs/checklists/compiler_llvm/": "/bringup/agent_runs/checklists/compiler_llvm/",
+ "/zh/bringup/agent_runs/checklists/emulator_qemu/": "/bringup/agent_runs/checklists/emulator_qemu/",
+ "/zh/bringup/agent_runs/checklists/integration_release/": "/bringup/agent_runs/checklists/integration_release/",
+ "/zh/bringup/agent_runs/checklists/kernel_linux/": "/bringup/agent_runs/checklists/kernel_linux/",
+ "/zh/bringup/agent_runs/checklists/libc_runtime/": "/bringup/agent_runs/checklists/libc_runtime/",
+ "/zh/bringup/agent_runs/checklists/linxcore_rtl/": "/bringup/agent_runs/checklists/linxcore_rtl/",
+ "/zh/bringup/agent_runs/checklists/pycircuit_model/": "/bringup/agent_runs/checklists/pycircuit_model/",
+ "/zh/bringup/agent_runs/checklists/specint_qemu/": "/bringup/agent_runs/checklists/specint_qemu/",
+ "/zh/bringup/agent_runs/checklists/testbench_verif/": "/bringup/agent_runs/checklists/testbench_verif/",
+ "/zh/bringup/agent_runs/checklists/trace_linxtrace/": "/bringup/agent_runs/checklists/trace_linxtrace/",
+ "/zh/bringup/agent_runs/skills_evolution/summary-2026-02-28-r1-phase-next-skills/": "/bringup/agent_runs/skills_evolution/summary-2026-02-28-r1-phase-next-skills/",
+ "/zh/bringup/agent_runs/skills_evolution/summary-2026-05-15-qemu-callret-closure/": "/bringup/agent_runs/skills_evolution/summary-2026-05-15-qemu-callret-closure/",
+ "/zh/bringup/code_density_and_dynamic_reduction/": "/bringup/code_density_and_dynamic_reduction/",
+ "/zh/bringup/contracts/fpga_platform_contract/": "/bringup/contracts/fpga_platform_contract/",
+ "/zh/bringup/contracts/pyc_artifact_contract/": "/bringup/contracts/pyc_artifact_contract/",
+ "/zh/bringup/contracts/pyc_linxcore_interface_contract/": "/bringup/contracts/pyc_linxcore_interface_contract/",
+ "/zh/bringup/contracts/trace_schema/": "/bringup/contracts/trace_schema/",
+ "/zh/bringup/gates/qemu_isa_coverage_latest/": "/bringup/gates/qemu_isa_coverage_latest/",
+ "/zh/bringup/gates/qemu_opcode_sync_latest/": "/bringup/gates/qemu_opcode_sync_latest/",
+ "/zh/bringup/libc_status/": "/bringup/libc_status/",
+ "/zh/bringup/phases/01_compiler/": "/bringup/phases/01_compiler/",
+ "/zh/bringup/phases/02_isa_spec/": "/bringup/phases/02_isa_spec/",
+ "/zh/bringup/phases/03_emulator_qemu/": "/bringup/phases/03_emulator_qemu/",
+ "/zh/bringup/phases/04_rtl/": "/bringup/phases/04_rtl/",
+ "/zh/bringup/phases/05_fpga_zybo_z7/": "/bringup/phases/05_fpga_zybo_z7/",
+ "/zh/bringup/phases/06_linux_on_janus/": "/bringup/phases/06_linux_on_janus/",
+ "/zh/bringup/phases/07_toolchain_glibc/": "/bringup/phases/07_toolchain_glibc/",
+ "/zh/bringup/phases/08_toolchain_musl/": "/bringup/phases/08_toolchain_musl/",
+ "/zh/bringup/phases/README/": "/bringup/phases/README/",
+ "/zh/bringup/plan/arch/": "/bringup/plan/arch/",
+ "/zh/bringup/plan/isa_clarifications/": "/bringup/plan/isa_clarifications/",
+ "/zh/bringup/plan/sail_formalization_v0.3/": "/bringup/plan/sail_formalization_v0.3/",
+ "/zh/bringup/plan/sail_review_log_v0.3/": "/bringup/plan/sail_review_log_v0.3/",
+ "/zh/bringup/plan/submodule_isa_alignment_v0.56/": "/bringup/plan/submodule_isa_alignment_v0.56/",
+ "/zh/bringup/rendering_vulkan_bringup/": "/bringup/rendering_vulkan_bringup/",
+ "/zh/bringup/spec_linxcore_xcheck/": "/bringup/spec_linxcore_xcheck/",
+ "/zh/bringup/virtio_9p_debug/": "/bringup/virtio_9p_debug/",
+ "/zh/change_log/update_v0.12/": "/change_log/update_v0.12/",
+ "/zh/change_log/update_v0.13/": "/change_log/update_v0.13/",
+ "/zh/change_log/update_v0.16/": "/change_log/update_v0.16/",
+ "/zh/change_log/update_v0.20/": "/change_log/update_v0.20/",
+ "/zh/change_log/update_v0.30/": "/change_log/update_v0.30/",
+ "/zh/change_log/update_v0.31/": "/change_log/update_v0.31/",
+ "/zh/change_log/update_v0.32/": "/change_log/update_v0.32/",
+ "/zh/change_log/update_v0.33/": "/change_log/update_v0.33/",
+ "/zh/change_log/update_v0.34/": "/change_log/update_v0.34/",
+ "/zh/change_log/update_v0.35/": "/change_log/update_v0.35/",
+ "/zh/change_log/update_v0.36/": "/change_log/update_v0.36/",
+ "/zh/change_log/update_v0.40/": "/change_log/update_v0.40/",
+ "/zh/change_log/update_v0.41/": "/change_log/update_v0.41/",
+ "/zh/change_log/update_v0.42/": "/change_log/update_v0.42/",
+ "/zh/change_log/update_v0.43/": "/change_log/update_v0.43/",
+ "/zh/change_log/update_v0.50/": "/change_log/update_v0.50/",
+ "/zh/change_log/update_v0.51/": "/change_log/update_v0.51/",
+ "/zh/change_log/update_v0.52/": "/change_log/update_v0.52/",
+ "/zh/change_log/update_v0.53/": "/change_log/update_v0.53/",
+ "/zh/change_log/update_v0.54/": "/change_log/update_v0.54/",
+ "/zh/change_log/update_v0.55/": "/change_log/update_v0.55/",
+ "/zh/change_log/update_v0.56/": "/change_log/update_v0.56/",
+ "/zh/compiler/Calling-Convention/": "/compiler/Calling-Convention/",
+ "/zh/compiler/assembly_manual/Architecture_Register/": "/compiler/assembly_manual/Architecture_Register/",
+ "/zh/compiler/assembly_manual/Assemble_syntax/": "/compiler/assembly_manual/Assemble_syntax/",
+ "/zh/compiler/assembly_manual/BlockISA_assemble_difference/": "/compiler/assembly_manual/BlockISA_assemble_difference/",
+ "/zh/compiler/assembly_manual/Compressed_Instruction/": "/compiler/assembly_manual/Compressed_Instruction/",
+ "/zh/compiler/assembly_manual/Conditional_execution/": "/compiler/assembly_manual/Conditional_execution/",
+ "/zh/compiler/assembly_manual/Constant_Immediate_Value/": "/compiler/assembly_manual/Constant_Immediate_Value/",
+ "/zh/compiler/assembly_manual/Function_alignment/": "/compiler/assembly_manual/Function_alignment/",
+ "/zh/compiler/assembly_manual/Inline_Assembly/": "/compiler/assembly_manual/Inline_Assembly/",
+ "/zh/compiler/assembly_manual/Introduct_BlockISA_assemble_tool/": "/compiler/assembly_manual/Introduct_BlockISA_assemble_tool/",
+ "/zh/compiler/assembly_manual/Introduction/": "/compiler/assembly_manual/Introduction/",
+ "/zh/compiler/assembly_manual/Introduction_assemble_language/": "/compiler/assembly_manual/Introduction_assemble_language/",
+ "/zh/compiler/assembly_manual/Micro-Instruction/": "/compiler/assembly_manual/Micro-Instruction/",
+ "/zh/compiler/assembly_manual/Micro-assemble-instruction/": "/compiler/assembly_manual/Micro-assemble-instruction/",
+ "/zh/compiler/assembly_manual/PC_value/": "/compiler/assembly_manual/PC_value/",
+ "/zh/compiler/assembly_manual/Pseudo_instruction/": "/compiler/assembly_manual/Pseudo_instruction/",
+ "/zh/compiler/assembly_manual/SIMT_instruction/": "/compiler/assembly_manual/SIMT_instruction/",
+ "/zh/compiler/assembly_manual/Standard_binary_interge_instruction/": "/compiler/assembly_manual/Standard_binary_interge_instruction/",
+ "/zh/compiler/assembly_manual/Std_Extern/": "/compiler/assembly_manual/Std_Extern/",
+ "/zh/compiler/assembly_manual/assemble_instruction/": "/compiler/assembly_manual/assemble_instruction/",
+ "/zh/compiler/assembly_manual/atomic_instruction/": "/compiler/assembly_manual/atomic_instruction/",
+ "/zh/compiler/assembly_manual/battr/": "/compiler/assembly_manual/battr/",
+ "/zh/compiler/assembly_manual/bend/": "/compiler/assembly_manual/bend/",
+ "/zh/compiler/assembly_manual/bget/": "/compiler/assembly_manual/bget/",
+ "/zh/compiler/assembly_manual/bhint/": "/compiler/assembly_manual/bhint/",
+ "/zh/compiler/assembly_manual/bitmanipulate_instruction/": "/compiler/assembly_manual/bitmanipulate_instruction/",
+ "/zh/compiler/assembly_manual/block_header/": "/compiler/assembly_manual/block_header/",
+ "/zh/compiler/assembly_manual/block_type/": "/compiler/assembly_manual/block_type/",
+ "/zh/compiler/assembly_manual/bsbar/": "/compiler/assembly_manual/bsbar/",
+ "/zh/compiler/assembly_manual/bset/": "/compiler/assembly_manual/bset/",
+ "/zh/compiler/assembly_manual/bstart/": "/compiler/assembly_manual/bstart/",
+ "/zh/compiler/assembly_manual/bstop/": "/compiler/assembly_manual/bstop/",
+ "/zh/compiler/assembly_manual/btext/": "/compiler/assembly_manual/btext/",
+ "/zh/compiler/assembly_manual/cmp_branch_jmp/": "/compiler/assembly_manual/cmp_branch_jmp/",
+ "/zh/compiler/assembly_manual/const_value/": "/compiler/assembly_manual/const_value/",
+ "/zh/compiler/assembly_manual/example/": "/compiler/assembly_manual/example/",
+ "/zh/compiler/assembly_manual/float_instruction/": "/compiler/assembly_manual/float_instruction/",
+ "/zh/compiler/assembly_manual/label/": "/compiler/assembly_manual/label/",
+ "/zh/compiler/assembly_manual/load_store_instruction/": "/compiler/assembly_manual/load_store_instruction/",
+ "/zh/compiler/assembly_manual/multiple_divide_instruction/": "/compiler/assembly_manual/multiple_divide_instruction/",
+ "/zh/compiler/assembly_manual/section/": "/compiler/assembly_manual/section/",
+ "/zh/compiler/assembly_manual/ssr_instruction/": "/compiler/assembly_manual/ssr_instruction/",
+ "/zh/compiler/assembly_manual/template_block/": "/compiler/assembly_manual/template_block/",
+ "/zh/compiler/hyper_block/": "/compiler/hyper_block/",
+ "/zh/compiler/linker/": "/compiler/linker/",
+ "/zh/compiler/manuals/": "/compiler/manuals/",
+ "/zh/compiler/qemu_slices/": "/compiler/qemu_slices/",
+ "/zh/compiler/run_c_program/": "/compiler/run_c_program/",
+ "/zh/cpu_core_intro/arch/": "/cpu_core_intro/arch/",
+ "/zh/cpu_core_intro/block_bigLittle_core/": "/cpu_core_intro/block_bigLittle_core/",
+ "/zh/figs/bitfield/README_BitField/": "/figs/bitfield/README_BitField/",
+ "/zh/isa/": "/isa/",
+ "/zh/isa/arch/acr/": "/isa/arch/acr/",
+ "/zh/isa/arch/bisa/": "/isa/arch/bisa/",
+ "/zh/isa/arch/branch/": "/isa/arch/branch/",
+ "/zh/isa/arch/constraints/": "/isa/arch/constraints/",
+ "/zh/isa/arch/corestate/": "/isa/arch/corestate/",
+ "/zh/isa/arch/exception/": "/isa/arch/exception/",
+ "/zh/isa/arch/execute/": "/isa/arch/execute/",
+ "/zh/isa/arch/executemachine/": "/isa/arch/executemachine/",
+ "/zh/isa/arch/executemode/": "/isa/arch/executemode/",
+ "/zh/isa/arch/fixup/": "/isa/arch/fixup/",
+ "/zh/isa/arch/prgorder/": "/isa/arch/prgorder/",
+ "/zh/isa/blockIntro/cube_block/header/": "/isa/blockIntro/cube_block/header/",
+ "/zh/isa/blockIntro/cube_block/intro/": "/isa/blockIntro/cube_block/intro/",
+ "/zh/isa/blockIntro/fp_block/fp_arithmetic/": "/isa/blockIntro/fp_block/fp_arithmetic/",
+ "/zh/isa/blockIntro/fp_block/fp_compare/": "/isa/blockIntro/fp_block/fp_compare/",
+ "/zh/isa/blockIntro/fp_block/fp_convert/": "/isa/blockIntro/fp_block/fp_convert/",
+ "/zh/isa/blockIntro/fp_block/instlist/": "/isa/blockIntro/fp_block/instlist/",
+ "/zh/isa/blockIntro/fp_block/intro/": "/isa/blockIntro/fp_block/intro/",
+ "/zh/isa/blockIntro/fp_block/max_min/": "/isa/blockIntro/fp_block/max_min/",
+ "/zh/isa/blockIntro/mem_block/dimmode/": "/isa/blockIntro/mem_block/dimmode/",
+ "/zh/isa/blockIntro/mem_block/header/": "/isa/blockIntro/mem_block/header/",
+ "/zh/isa/blockIntro/mem_block/instlist/": "/isa/blockIntro/mem_block/instlist/",
+ "/zh/isa/blockIntro/mem_block/intro/": "/isa/blockIntro/mem_block/intro/",
+ "/zh/isa/blockIntro/scainstrs/arithmetic/": "/isa/blockIntro/scainstrs/arithmetic/",
+ "/zh/isa/blockIntro/scainstrs/bitmanip/": "/isa/blockIntro/scainstrs/bitmanip/",
+ "/zh/isa/blockIntro/scainstrs/branch/": "/isa/blockIntro/scainstrs/branch/",
+ "/zh/isa/blockIntro/scainstrs/compare/": "/isa/blockIntro/scainstrs/compare/",
+ "/zh/isa/blockIntro/scainstrs/divide/": "/isa/blockIntro/scainstrs/divide/",
+ "/zh/isa/blockIntro/scainstrs/multi/": "/isa/blockIntro/scainstrs/multi/",
+ "/zh/isa/blockIntro/scainstrs/pc_arithmetic/": "/isa/blockIntro/scainstrs/pc_arithmetic/",
+ "/zh/isa/blockIntro/scainstrs/setc/": "/isa/blockIntro/scainstrs/setc/",
+ "/zh/isa/blockIntro/scainstrs/ssr_opration/": "/isa/blockIntro/scainstrs/ssr_opration/",
+ "/zh/isa/blockIntro/std_block/instlist/": "/isa/blockIntro/std_block/instlist/",
+ "/zh/isa/blockIntro/std_block/intro/": "/isa/blockIntro/std_block/intro/",
+ "/zh/isa/blockIntro/std_block/prefetch/": "/isa/blockIntro/std_block/prefetch/",
+ "/zh/isa/blockIntro/sys_block/atomic/": "/isa/blockIntro/sys_block/atomic/",
+ "/zh/isa/blockIntro/sys_block/cachemaintain/": "/isa/blockIntro/sys_block/cachemaintain/",
+ "/zh/isa/blockIntro/sys_block/excutecontrol/": "/isa/blockIntro/sys_block/excutecontrol/",
+ "/zh/isa/blockIntro/sys_block/gqm/": "/isa/blockIntro/sys_block/gqm/",
+ "/zh/isa/blockIntro/sys_block/instlist/": "/isa/blockIntro/sys_block/instlist/",
+ "/zh/isa/blockIntro/sys_block/intro/": "/isa/blockIntro/sys_block/intro/",
+ "/zh/isa/blockIntro/sys_block/lr_sc/": "/isa/blockIntro/sys_block/lr_sc/",
+ "/zh/isa/blockIntro/sys_block/tlb/": "/isa/blockIntro/sys_block/tlb/",
+ "/zh/isa/blockIntro/tepl_block/header/": "/isa/blockIntro/tepl_block/header/",
+ "/zh/isa/blockIntro/tepl_block/intro/": "/isa/blockIntro/tepl_block/intro/",
+ "/zh/isa/blockIntro/tma_block/header/": "/isa/blockIntro/tma_block/header/",
+ "/zh/isa/blockIntro/tma_block/intro/": "/isa/blockIntro/tma_block/intro/",
+ "/zh/isa/blockIntro/vec_block/header/": "/isa/blockIntro/vec_block/header/",
+ "/zh/isa/blockIntro/vec_block/instlist/": "/isa/blockIntro/vec_block/instlist/",
+ "/zh/isa/blockIntro/vec_block/intro/": "/isa/blockIntro/vec_block/intro/",
+ "/zh/isa/blockIntro/vec_block/stack/": "/isa/blockIntro/vec_block/stack/",
+ "/zh/isa/blockIntro/vecinstrs/arithmetic/": "/isa/blockIntro/vecinstrs/arithmetic/",
+ "/zh/isa/blockIntro/vecinstrs/atomic/": "/isa/blockIntro/vecinstrs/atomic/",
+ "/zh/isa/blockIntro/vecinstrs/bitmanip/": "/isa/blockIntro/vecinstrs/bitmanip/",
+ "/zh/isa/blockIntro/vecinstrs/branch/": "/isa/blockIntro/vecinstrs/branch/",
+ "/zh/isa/blockIntro/vecinstrs/compare/": "/isa/blockIntro/vecinstrs/compare/",
+ "/zh/isa/blockIntro/vecinstrs/convert/": "/isa/blockIntro/vecinstrs/convert/",
+ "/zh/isa/blockIntro/vecinstrs/fp_arithmetic/": "/isa/blockIntro/vecinstrs/fp_arithmetic/",
+ "/zh/isa/blockIntro/vecinstrs/fp_compare/": "/isa/blockIntro/vecinstrs/fp_compare/",
+ "/zh/isa/blockIntro/vecinstrs/gqm/": "/isa/blockIntro/vecinstrs/gqm/",
+ "/zh/isa/blockIntro/vecinstrs/instIntro/": "/isa/blockIntro/vecinstrs/instIntro/",
+ "/zh/isa/blockIntro/vecinstrs/loadStore/": "/isa/blockIntro/vecinstrs/loadStore/",
+ "/zh/isa/blockIntro/vecinstrs/loadStoreBridge/": "/isa/blockIntro/vecinstrs/loadStoreBridge/",
+ "/zh/isa/blockIntro/vecinstrs/max_min/": "/isa/blockIntro/vecinstrs/max_min/",
+ "/zh/isa/blockIntro/vecinstrs/mul_div/": "/isa/blockIntro/vecinstrs/mul_div/",
+ "/zh/isa/blockIntro/vecinstrs/reduce/": "/isa/blockIntro/vecinstrs/reduce/",
+ "/zh/isa/blockIntro/vecinstrs/shuffle/": "/isa/blockIntro/vecinstrs/shuffle/",
+ "/zh/isa/blockIntro/xb_block/intro/": "/isa/blockIntro/xb_block/intro/",
+ "/zh/isa/custom/custom_isa/": "/isa/custom/custom_isa/",
+ "/zh/isa/custom/hac_intf/": "/isa/custom/hac_intf/",
+ "/zh/isa/datatype/BF16/": "/isa/datatype/BF16/",
+ "/zh/isa/datatype/FP16/": "/isa/datatype/FP16/",
+ "/zh/isa/datatype/FP32/": "/isa/datatype/FP32/",
+ "/zh/isa/datatype/FP4/": "/isa/datatype/FP4/",
+ "/zh/isa/datatype/FP6/": "/isa/datatype/FP6/",
+ "/zh/isa/datatype/FP64/": "/isa/datatype/FP64/",
+ "/zh/isa/datatype/FP8/": "/isa/datatype/FP8/",
+ "/zh/isa/datatype/HF32/": "/isa/datatype/HF32/",
+ "/zh/isa/datatype/HiF4/": "/isa/datatype/HiF4/",
+ "/zh/isa/datatype/HiF8/": "/isa/datatype/HiF8/",
+ "/zh/isa/datatype/HiF_SCALE/": "/isa/datatype/HiF_SCALE/",
+ "/zh/isa/datatype/INT16/": "/isa/datatype/INT16/",
+ "/zh/isa/datatype/INT32/": "/isa/datatype/INT32/",
+ "/zh/isa/datatype/INT4/": "/isa/datatype/INT4/",
+ "/zh/isa/datatype/INT64/": "/isa/datatype/INT64/",
+ "/zh/isa/datatype/INT8/": "/isa/datatype/INT8/",
+ "/zh/isa/datatype/MXFP4/": "/isa/datatype/MXFP4/",
+ "/zh/isa/datatype/MXFP6/": "/isa/datatype/MXFP6/",
+ "/zh/isa/datatype/MXFP8/": "/isa/datatype/MXFP8/",
+ "/zh/isa/datatype/MX_SCALE/": "/isa/datatype/MX_SCALE/",
+ "/zh/isa/datatype/TF32/": "/isa/datatype/TF32/",
+ "/zh/isa/datatype/UINT16/": "/isa/datatype/UINT16/",
+ "/zh/isa/datatype/UINT32/": "/isa/datatype/UINT32/",
+ "/zh/isa/datatype/UINT4/": "/isa/datatype/UINT4/",
+ "/zh/isa/datatype/UINT64/": "/isa/datatype/UINT64/",
+ "/zh/isa/datatype/UINT8/": "/isa/datatype/UINT8/",
+ "/zh/isa/datatype/intro/": "/isa/datatype/intro/",
+ "/zh/isa/encoding/": "/isa/encoding/",
+ "/zh/isa/encoding/overview/": "/isa/encoding/overview/",
+ "/zh/isa/encoding/space/": "/isa/encoding/space/",
+ "/zh/isa/exception/acr/": "/isa/exception/acr/",
+ "/zh/isa/exception/acr_switch/": "/isa/exception/acr_switch/",
+ "/zh/isa/exception/exception/": "/isa/exception/exception/",
+ "/zh/isa/exception/interrupt/": "/isa/exception/interrupt/",
+ "/zh/isa/groups/": "/isa/groups/",
+ "/zh/isa/groups/arithmetic/": "/isa/groups/arithmetic/",
+ "/zh/isa/groups/arithmetic_operation/": "/isa/groups/arithmetic_operation/",
+ "/zh/isa/groups/arithmetic_operation_32bit/": "/isa/groups/arithmetic_operation_32bit/",
+ "/zh/isa/groups/arithmetic_operation_64bit/": "/isa/groups/arithmetic_operation_64bit/",
+ "/zh/isa/groups/atomic/": "/isa/groups/atomic/",
+ "/zh/isa/groups/atomic_operation/": "/isa/groups/atomic_operation/",
+ "/zh/isa/groups/bit_manipulation/": "/isa/groups/bit_manipulation/",
+ "/zh/isa/groups/bit_operation/": "/isa/groups/bit_operation/",
+ "/zh/isa/groups/block_argument/": "/isa/groups/block_argument/",
+ "/zh/isa/groups/block_control_attribute/": "/isa/groups/block_control_attribute/",
+ "/zh/isa/groups/block_data_attribute/": "/isa/groups/block_data_attribute/",
+ "/zh/isa/groups/block_dimension/": "/isa/groups/block_dimension/",
+ "/zh/isa/groups/block_hint/": "/isa/groups/block_hint/",
+ "/zh/isa/groups/block_input_output/": "/isa/groups/block_input_output/",
+ "/zh/isa/groups/block_offset/": "/isa/groups/block_offset/",
+ "/zh/isa/groups/block_split/": "/isa/groups/block_split/",
+ "/zh/isa/groups/branch/": "/isa/groups/branch/",
+ "/zh/isa/groups/bstart/": "/isa/groups/bstart/",
+ "/zh/isa/groups/c_bstart/": "/isa/groups/c_bstart/",
+ "/zh/isa/groups/c_tinst/": "/isa/groups/c_tinst/",
+ "/zh/isa/groups/c_unary/": "/isa/groups/c_unary/",
+ "/zh/isa/groups/cache_maintain/": "/isa/groups/cache_maintain/",
+ "/zh/isa/groups/compare_instruction/": "/isa/groups/compare_instruction/",
+ "/zh/isa/groups/compound_operation/": "/isa/groups/compound_operation/",
+ "/zh/isa/groups/concat/": "/isa/groups/concat/",
+ "/zh/isa/groups/division/": "/isa/groups/division/",
+ "/zh/isa/groups/execution_control/": "/isa/groups/execution_control/",
+ "/zh/isa/groups/floating_point_arithmetic/": "/isa/groups/floating_point_arithmetic/",
+ "/zh/isa/groups/floating_point_compare/": "/isa/groups/floating_point_compare/",
+ "/zh/isa/groups/format_convert/": "/isa/groups/format_convert/",
+ "/zh/isa/groups/general/": "/isa/groups/general/",
+ "/zh/isa/groups/general_manager/": "/isa/groups/general_manager/",
+ "/zh/isa/groups/immediate/": "/isa/groups/immediate/",
+ "/zh/isa/groups/load_immediate_offset/": "/isa/groups/load_immediate_offset/",
+ "/zh/isa/groups/load_long_offset/": "/isa/groups/load_long_offset/",
+ "/zh/isa/groups/load_pair/": "/isa/groups/load_pair/",
+ "/zh/isa/groups/load_pc_relative/": "/isa/groups/load_pc_relative/",
+ "/zh/isa/groups/load_post_index/": "/isa/groups/load_post_index/",
+ "/zh/isa/groups/load_pre_index/": "/isa/groups/load_pre_index/",
+ "/zh/isa/groups/load_register_offset/": "/isa/groups/load_register_offset/",
+ "/zh/isa/groups/load_symbol/": "/isa/groups/load_symbol/",
+ "/zh/isa/groups/load_unscaled/": "/isa/groups/load_unscaled/",
+ "/zh/isa/groups/long_immediate/": "/isa/groups/long_immediate/",
+ "/zh/isa/groups/max_min/": "/isa/groups/max_min/",
+ "/zh/isa/groups/move/": "/isa/groups/move/",
+ "/zh/isa/groups/multi_cycle_alu/": "/isa/groups/multi_cycle_alu/",
+ "/zh/isa/groups/pc_relative/": "/isa/groups/pc_relative/",
+ "/zh/isa/groups/prefetch/": "/isa/groups/prefetch/",
+ "/zh/isa/groups/reduce_operation_with_register/": "/isa/groups/reduce_operation_with_register/",
+ "/zh/isa/groups/reserve/": "/isa/groups/reserve/",
+ "/zh/isa/groups/set_commit_argument/": "/isa/groups/set_commit_argument/",
+ "/zh/isa/groups/shuffle/": "/isa/groups/shuffle/",
+ "/zh/isa/groups/ssr_access/": "/isa/groups/ssr_access/",
+ "/zh/isa/groups/store_immediate_offset/": "/isa/groups/store_immediate_offset/",
+ "/zh/isa/groups/store_long_offset/": "/isa/groups/store_long_offset/",
+ "/zh/isa/groups/store_offset/": "/isa/groups/store_offset/",
+ "/zh/isa/groups/store_pair/": "/isa/groups/store_pair/",
+ "/zh/isa/groups/store_pc_relative/": "/isa/groups/store_pc_relative/",
+ "/zh/isa/groups/store_post_index/": "/isa/groups/store_post_index/",
+ "/zh/isa/groups/store_pre_index/": "/isa/groups/store_pre_index/",
+ "/zh/isa/groups/store_register_offset/": "/isa/groups/store_register_offset/",
+ "/zh/isa/groups/store_symbol/": "/isa/groups/store_symbol/",
+ "/zh/isa/groups/three_source_floating_point/": "/isa/groups/three_source_floating_point/",
+ "/zh/isa/groups/three_source_integer/": "/isa/groups/three_source_integer/",
+ "/zh/isa/groups/two_source_floating_point/": "/isa/groups/two_source_floating_point/",
+ "/zh/isa/header/B.CATR/": "/isa/header/B.CATR/",
+ "/zh/isa/header/B.DATR/": "/isa/header/B.DATR/",
+ "/zh/isa/header/B.DIM/": "/isa/header/B.DIM/",
+ "/zh/isa/header/B.HINT/": "/isa/header/B.HINT/",
+ "/zh/isa/header/B.IOD/": "/isa/header/B.IOD/",
+ "/zh/isa/header/B.IOR/": "/isa/header/B.IOR/",
+ "/zh/isa/header/B.IOT/": "/isa/header/B.IOT/",
+ "/zh/isa/header/B.TEXT/": "/isa/header/B.TEXT/",
+ "/zh/isa/header/BSTART.FP/": "/isa/header/BSTART.FP/",
+ "/zh/isa/header/BSTART.STD/": "/isa/header/BSTART.STD/",
+ "/zh/isa/header/BSTART.SYS/": "/isa/header/BSTART.SYS/",
+ "/zh/isa/header/BSTART/": "/isa/header/BSTART/",
+ "/zh/isa/header/BSTOP/": "/isa/header/BSTOP/",
+ "/zh/isa/header/C.B.DIM/": "/isa/header/C.B.DIM/",
+ "/zh/isa/header/C.BSTART/": "/isa/header/C.BSTART/",
+ "/zh/isa/header/ComBlockIntro/": "/isa/header/ComBlockIntro/",
+ "/zh/isa/header/HL.BSTART/": "/isa/header/HL.BSTART/",
+ "/zh/isa/header/Intro/": "/isa/header/Intro/",
+ "/zh/isa/header/L.BSTART/": "/isa/header/L.BSTART/",
+ "/zh/isa/header/XB/": "/isa/header/XB/",
+ "/zh/isa/header/templateblock/ERCOV/": "/isa/header/templateblock/ERCOV/",
+ "/zh/isa/header/templateblock/ESAVE/": "/isa/header/templateblock/ESAVE/",
+ "/zh/isa/header/templateblock/FENTRY/": "/isa/header/templateblock/FENTRY/",
+ "/zh/isa/header/templateblock/FEXIT/": "/isa/header/templateblock/FEXIT/",
+ "/zh/isa/header/templateblock/FRET.RA/": "/isa/header/templateblock/FRET.RA/",
+ "/zh/isa/header/templateblock/FRET.STK/": "/isa/header/templateblock/FRET.STK/",
+ "/zh/isa/header/templateblock/GETMSG/": "/isa/header/templateblock/GETMSG/",
+ "/zh/isa/header/templateblock/MCOPY.D/": "/isa/header/templateblock/MCOPY.D/",
+ "/zh/isa/header/templateblock/MCOPY/": "/isa/header/templateblock/MCOPY/",
+ "/zh/isa/header/templateblock/MSET/": "/isa/header/templateblock/MSET/",
+ "/zh/isa/header/templateblock/intro/": "/isa/header/templateblock/intro/",
+ "/zh/isa/header/tileblock/ACCCVT/": "/isa/header/tileblock/ACCCVT/",
+ "/zh/isa/header/tileblock/MGATHER/": "/isa/header/tileblock/MGATHER/",
+ "/zh/isa/header/tileblock/MSCATTER/": "/isa/header/tileblock/MSCATTER/",
+ "/zh/isa/header/tileblock/TABS/": "/isa/header/tileblock/TABS/",
+ "/zh/isa/header/tileblock/TADD/": "/isa/header/tileblock/TADD/",
+ "/zh/isa/header/tileblock/TADDC/": "/isa/header/tileblock/TADDC/",
+ "/zh/isa/header/tileblock/TADDS/": "/isa/header/tileblock/TADDS/",
+ "/zh/isa/header/tileblock/TADDSC/": "/isa/header/tileblock/TADDSC/",
+ "/zh/isa/header/tileblock/TAND/": "/isa/header/tileblock/TAND/",
+ "/zh/isa/header/tileblock/TANDS/": "/isa/header/tileblock/TANDS/",
+ "/zh/isa/header/tileblock/TCMP/": "/isa/header/tileblock/TCMP/",
+ "/zh/isa/header/tileblock/TCMPS/": "/isa/header/tileblock/TCMPS/",
+ "/zh/isa/header/tileblock/TCOLEXPAND/": "/isa/header/tileblock/TCOLEXPAND/",
+ "/zh/isa/header/tileblock/TCOLEXPANDADD/": "/isa/header/tileblock/TCOLEXPANDADD/",
+ "/zh/isa/header/tileblock/TCOLEXPANDDIV/": "/isa/header/tileblock/TCOLEXPANDDIV/",
+ "/zh/isa/header/tileblock/TCOLEXPANDEXPDIF/": "/isa/header/tileblock/TCOLEXPANDEXPDIF/",
+ "/zh/isa/header/tileblock/TCOLEXPANDMAX/": "/isa/header/tileblock/TCOLEXPANDMAX/",
+ "/zh/isa/header/tileblock/TCOLEXPANDMIN/": "/isa/header/tileblock/TCOLEXPANDMIN/",
+ "/zh/isa/header/tileblock/TCOLEXPANDMUL/": "/isa/header/tileblock/TCOLEXPANDMUL/",
+ "/zh/isa/header/tileblock/TCOLEXPANDSUB/": "/isa/header/tileblock/TCOLEXPANDSUB/",
+ "/zh/isa/header/tileblock/TCOLMAX/": "/isa/header/tileblock/TCOLMAX/",
+ "/zh/isa/header/tileblock/TCOLMIN/": "/isa/header/tileblock/TCOLMIN/",
+ "/zh/isa/header/tileblock/TCOLPROD/": "/isa/header/tileblock/TCOLPROD/",
+ "/zh/isa/header/tileblock/TCOLSUM/": "/isa/header/tileblock/TCOLSUM/",
+ "/zh/isa/header/tileblock/TCVT/": "/isa/header/tileblock/TCVT/",
+ "/zh/isa/header/tileblock/TDIV/": "/isa/header/tileblock/TDIV/",
+ "/zh/isa/header/tileblock/TDIVS/": "/isa/header/tileblock/TDIVS/",
+ "/zh/isa/header/tileblock/TEXP/": "/isa/header/tileblock/TEXP/",
+ "/zh/isa/header/tileblock/TEXPANDS/": "/isa/header/tileblock/TEXPANDS/",
+ "/zh/isa/header/tileblock/TFMOD/": "/isa/header/tileblock/TFMOD/",
+ "/zh/isa/header/tileblock/TFMODS/": "/isa/header/tileblock/TFMODS/",
+ "/zh/isa/header/tileblock/TGATHER/": "/isa/header/tileblock/TGATHER/",
+ "/zh/isa/header/tileblock/TGEMV.ACC/": "/isa/header/tileblock/TGEMV.ACC/",
+ "/zh/isa/header/tileblock/TGEMV.BIAS/": "/isa/header/tileblock/TGEMV.BIAS/",
+ "/zh/isa/header/tileblock/TGEMV/": "/isa/header/tileblock/TGEMV/",
+ "/zh/isa/header/tileblock/TGEMVMX.ACC/": "/isa/header/tileblock/TGEMVMX.ACC/",
+ "/zh/isa/header/tileblock/TGEMVMX.BIAS/": "/isa/header/tileblock/TGEMVMX.BIAS/",
+ "/zh/isa/header/tileblock/TGEMVMX/": "/isa/header/tileblock/TGEMVMX/",
+ "/zh/isa/header/tileblock/THISTOGRAM/": "/isa/header/tileblock/THISTOGRAM/",
+ "/zh/isa/header/tileblock/TLOAD/": "/isa/header/tileblock/TLOAD/",
+ "/zh/isa/header/tileblock/TLOG/": "/isa/header/tileblock/TLOG/",
+ "/zh/isa/header/tileblock/TLRELU/": "/isa/header/tileblock/TLRELU/",
+ "/zh/isa/header/tileblock/TMATMUL.ACC/": "/isa/header/tileblock/TMATMUL.ACC/",
+ "/zh/isa/header/tileblock/TMATMUL.BIAS/": "/isa/header/tileblock/TMATMUL.BIAS/",
+ "/zh/isa/header/tileblock/TMATMUL/": "/isa/header/tileblock/TMATMUL/",
+ "/zh/isa/header/tileblock/TMATMULMX.ACC/": "/isa/header/tileblock/TMATMULMX.ACC/",
+ "/zh/isa/header/tileblock/TMATMULMX.BIAS/": "/isa/header/tileblock/TMATMULMX.BIAS/",
+ "/zh/isa/header/tileblock/TMATMULMX/": "/isa/header/tileblock/TMATMULMX/",
+ "/zh/isa/header/tileblock/TMAX/": "/isa/header/tileblock/TMAX/",
+ "/zh/isa/header/tileblock/TMAXS/": "/isa/header/tileblock/TMAXS/",
+ "/zh/isa/header/tileblock/TMIN/": "/isa/header/tileblock/TMIN/",
+ "/zh/isa/header/tileblock/TMINS/": "/isa/header/tileblock/TMINS/",
+ "/zh/isa/header/tileblock/TMOV/": "/isa/header/tileblock/TMOV/",
+ "/zh/isa/header/tileblock/TMUL/": "/isa/header/tileblock/TMUL/",
+ "/zh/isa/header/tileblock/TMULS/": "/isa/header/tileblock/TMULS/",
+ "/zh/isa/header/tileblock/TNEG/": "/isa/header/tileblock/TNEG/",
+ "/zh/isa/header/tileblock/TNOT/": "/isa/header/tileblock/TNOT/",
+ "/zh/isa/header/tileblock/TOR/": "/isa/header/tileblock/TOR/",
+ "/zh/isa/header/tileblock/TORS/": "/isa/header/tileblock/TORS/",
+ "/zh/isa/header/tileblock/TPRELU/": "/isa/header/tileblock/TPRELU/",
+ "/zh/isa/header/tileblock/TRECIP/": "/isa/header/tileblock/TRECIP/",
+ "/zh/isa/header/tileblock/TRELU/": "/isa/header/tileblock/TRELU/",
+ "/zh/isa/header/tileblock/TREM/": "/isa/header/tileblock/TREM/",
+ "/zh/isa/header/tileblock/TREMS/": "/isa/header/tileblock/TREMS/",
+ "/zh/isa/header/tileblock/TROWEXPAND/": "/isa/header/tileblock/TROWEXPAND/",
+ "/zh/isa/header/tileblock/TROWEXPANDADD/": "/isa/header/tileblock/TROWEXPANDADD/",
+ "/zh/isa/header/tileblock/TROWEXPANDDIV/": "/isa/header/tileblock/TROWEXPANDDIV/",
+ "/zh/isa/header/tileblock/TROWEXPANDEXPDIF/": "/isa/header/tileblock/TROWEXPANDEXPDIF/",
+ "/zh/isa/header/tileblock/TROWEXPANDMAX/": "/isa/header/tileblock/TROWEXPANDMAX/",
+ "/zh/isa/header/tileblock/TROWEXPANDMIN/": "/isa/header/tileblock/TROWEXPANDMIN/",
+ "/zh/isa/header/tileblock/TROWEXPANDMUL/": "/isa/header/tileblock/TROWEXPANDMUL/",
+ "/zh/isa/header/tileblock/TROWEXPANDSUB/": "/isa/header/tileblock/TROWEXPANDSUB/",
+ "/zh/isa/header/tileblock/TROWMAX/": "/isa/header/tileblock/TROWMAX/",
+ "/zh/isa/header/tileblock/TROWMIN/": "/isa/header/tileblock/TROWMIN/",
+ "/zh/isa/header/tileblock/TROWPROD/": "/isa/header/tileblock/TROWPROD/",
+ "/zh/isa/header/tileblock/TROWSUM/": "/isa/header/tileblock/TROWSUM/",
+ "/zh/isa/header/tileblock/TRSQRT/": "/isa/header/tileblock/TRSQRT/",
+ "/zh/isa/header/tileblock/TSCATTER/": "/isa/header/tileblock/TSCATTER/",
+ "/zh/isa/header/tileblock/TSEL/": "/isa/header/tileblock/TSEL/",
+ "/zh/isa/header/tileblock/TSELS/": "/isa/header/tileblock/TSELS/",
+ "/zh/isa/header/tileblock/TSHL/": "/isa/header/tileblock/TSHL/",
+ "/zh/isa/header/tileblock/TSHLS/": "/isa/header/tileblock/TSHLS/",
+ "/zh/isa/header/tileblock/TSHR/": "/isa/header/tileblock/TSHR/",
+ "/zh/isa/header/tileblock/TSHRS/": "/isa/header/tileblock/TSHRS/",
+ "/zh/isa/header/tileblock/TSQRT/": "/isa/header/tileblock/TSQRT/",
+ "/zh/isa/header/tileblock/TSTORE/": "/isa/header/tileblock/TSTORE/",
+ "/zh/isa/header/tileblock/TSUB/": "/isa/header/tileblock/TSUB/",
+ "/zh/isa/header/tileblock/TSUBC/": "/isa/header/tileblock/TSUBC/",
+ "/zh/isa/header/tileblock/TSUBS/": "/isa/header/tileblock/TSUBS/",
+ "/zh/isa/header/tileblock/TSUBSC/": "/isa/header/tileblock/TSUBSC/",
+ "/zh/isa/header/tileblock/TTRANS/": "/isa/header/tileblock/TTRANS/",
+ "/zh/isa/header/tileblock/TXOR/": "/isa/header/tileblock/TXOR/",
+ "/zh/isa/header/tileblock/TXORS/": "/isa/header/tileblock/TXORS/",
+ "/zh/isa/header/tileblock/intro/": "/isa/header/tileblock/intro/",
+ "/zh/isa/inst/LibPseudoCode/": "/isa/inst/LibPseudoCode/",
+ "/zh/isa/inst/instrUsage/": "/isa/inst/instrUsage/",
+ "/zh/isa/inst/misa_c/C.ADD/": "/isa/inst/misa_c/C.ADD/",
+ "/zh/isa/inst/misa_c/C.ADDI/": "/isa/inst/misa_c/C.ADDI/",
+ "/zh/isa/inst/misa_c/C.AND/": "/isa/inst/misa_c/C.AND/",
+ "/zh/isa/inst/misa_c/C.CMP.EQI/": "/isa/inst/misa_c/C.CMP.EQI/",
+ "/zh/isa/inst/misa_c/C.CMP.NEI/": "/isa/inst/misa_c/C.CMP.NEI/",
+ "/zh/isa/inst/misa_c/C.EBREAK/": "/isa/inst/misa_c/C.EBREAK/",
+ "/zh/isa/inst/misa_c/C.LDI/": "/isa/inst/misa_c/C.LDI/",
+ "/zh/isa/inst/misa_c/C.LWI/": "/isa/inst/misa_c/C.LWI/",
+ "/zh/isa/inst/misa_c/C.MOVI/": "/isa/inst/misa_c/C.MOVI/",
+ "/zh/isa/inst/misa_c/C.MOVR/": "/isa/inst/misa_c/C.MOVR/",
+ "/zh/isa/inst/misa_c/C.OR/": "/isa/inst/misa_c/C.OR/",
+ "/zh/isa/inst/misa_c/C.SDI/": "/isa/inst/misa_c/C.SDI/",
+ "/zh/isa/inst/misa_c/C.SETC.EQ/": "/isa/inst/misa_c/C.SETC.EQ/",
+ "/zh/isa/inst/misa_c/C.SETC.NE/": "/isa/inst/misa_c/C.SETC.NE/",
+ "/zh/isa/inst/misa_c/C.SETC.TGT/": "/isa/inst/misa_c/C.SETC.TGT/",
+ "/zh/isa/inst/misa_c/C.SETRET/": "/isa/inst/misa_c/C.SETRET/",
+ "/zh/isa/inst/misa_c/C.SEXT.B/": "/isa/inst/misa_c/C.SEXT.B/",
+ "/zh/isa/inst/misa_c/C.SEXT.H/": "/isa/inst/misa_c/C.SEXT.H/",
+ "/zh/isa/inst/misa_c/C.SEXT.W/": "/isa/inst/misa_c/C.SEXT.W/",
+ "/zh/isa/inst/misa_c/C.SLLI/": "/isa/inst/misa_c/C.SLLI/",
+ "/zh/isa/inst/misa_c/C.SRLI/": "/isa/inst/misa_c/C.SRLI/",
+ "/zh/isa/inst/misa_c/C.SSRGET/": "/isa/inst/misa_c/C.SSRGET/",
+ "/zh/isa/inst/misa_c/C.SUB/": "/isa/inst/misa_c/C.SUB/",
+ "/zh/isa/inst/misa_c/C.SWI/": "/isa/inst/misa_c/C.SWI/",
+ "/zh/isa/inst/misa_c/C.ZEXT.B/": "/isa/inst/misa_c/C.ZEXT.B/",
+ "/zh/isa/inst/misa_c/C.ZEXT.H/": "/isa/inst/misa_c/C.ZEXT.H/",
+ "/zh/isa/inst/misa_c/C.ZEXT.W/": "/isa/inst/misa_c/C.ZEXT.W/",
+ "/zh/isa/inst/misa_f/FABS/": "/isa/inst/misa_f/FABS/",
+ "/zh/isa/inst/misa_f/FADD/": "/isa/inst/misa_f/FADD/",
+ "/zh/isa/inst/misa_f/FCVT/": "/isa/inst/misa_f/FCVT/",
+ "/zh/isa/inst/misa_f/FCVTA/": "/isa/inst/misa_f/FCVTA/",
+ "/zh/isa/inst/misa_f/FCVTM/": "/isa/inst/misa_f/FCVTM/",
+ "/zh/isa/inst/misa_f/FCVTN/": "/isa/inst/misa_f/FCVTN/",
+ "/zh/isa/inst/misa_f/FCVTP/": "/isa/inst/misa_f/FCVTP/",
+ "/zh/isa/inst/misa_f/FCVTZ/": "/isa/inst/misa_f/FCVTZ/",
+ "/zh/isa/inst/misa_f/FDIV/": "/isa/inst/misa_f/FDIV/",
+ "/zh/isa/inst/misa_f/FEQ/": "/isa/inst/misa_f/FEQ/",
+ "/zh/isa/inst/misa_f/FEQS/": "/isa/inst/misa_f/FEQS/",
+ "/zh/isa/inst/misa_f/FEXP/": "/isa/inst/misa_f/FEXP/",
+ "/zh/isa/inst/misa_f/FGE/": "/isa/inst/misa_f/FGE/",
+ "/zh/isa/inst/misa_f/FGES/": "/isa/inst/misa_f/FGES/",
+ "/zh/isa/inst/misa_f/FLT/": "/isa/inst/misa_f/FLT/",
+ "/zh/isa/inst/misa_f/FLTS/": "/isa/inst/misa_f/FLTS/",
+ "/zh/isa/inst/misa_f/FMADD/": "/isa/inst/misa_f/FMADD/",
+ "/zh/isa/inst/misa_f/FMAX/": "/isa/inst/misa_f/FMAX/",
+ "/zh/isa/inst/misa_f/FMIN/": "/isa/inst/misa_f/FMIN/",
+ "/zh/isa/inst/misa_f/FMSUB/": "/isa/inst/misa_f/FMSUB/",
+ "/zh/isa/inst/misa_f/FMUL/": "/isa/inst/misa_f/FMUL/",
+ "/zh/isa/inst/misa_f/FNE/": "/isa/inst/misa_f/FNE/",
+ "/zh/isa/inst/misa_f/FNES/": "/isa/inst/misa_f/FNES/",
+ "/zh/isa/inst/misa_f/FNMADD/": "/isa/inst/misa_f/FNMADD/",
+ "/zh/isa/inst/misa_f/FNMSUB/": "/isa/inst/misa_f/FNMSUB/",
+ "/zh/isa/inst/misa_f/FRECIP/": "/isa/inst/misa_f/FRECIP/",
+ "/zh/isa/inst/misa_f/FSQRT/": "/isa/inst/misa_f/FSQRT/",
+ "/zh/isa/inst/misa_f/FSUB/": "/isa/inst/misa_f/FSUB/",
+ "/zh/isa/inst/misa_f/MAX/": "/isa/inst/misa_f/MAX/",
+ "/zh/isa/inst/misa_f/MAXU/": "/isa/inst/misa_f/MAXU/",
+ "/zh/isa/inst/misa_f/MIN/": "/isa/inst/misa_f/MIN/",
+ "/zh/isa/inst/misa_f/MINU/": "/isa/inst/misa_f/MINU/",
+ "/zh/isa/inst/misa_f/SCVTF/": "/isa/inst/misa_f/SCVTF/",
+ "/zh/isa/inst/misa_f/UCVTF/": "/isa/inst/misa_f/UCVTF/",
+ "/zh/isa/inst/misa_g/ADD/": "/isa/inst/misa_g/ADD/",
+ "/zh/isa/inst/misa_g/ADDI/": "/isa/inst/misa_g/ADDI/",
+ "/zh/isa/inst/misa_g/ADDIW/": "/isa/inst/misa_g/ADDIW/",
+ "/zh/isa/inst/misa_g/ADDTPC/": "/isa/inst/misa_g/ADDTPC/",
+ "/zh/isa/inst/misa_g/ADDW/": "/isa/inst/misa_g/ADDW/",
+ "/zh/isa/inst/misa_g/AND/": "/isa/inst/misa_g/AND/",
+ "/zh/isa/inst/misa_g/ANDI/": "/isa/inst/misa_g/ANDI/",
+ "/zh/isa/inst/misa_g/ANDIW/": "/isa/inst/misa_g/ANDIW/",
+ "/zh/isa/inst/misa_g/ANDW/": "/isa/inst/misa_g/ANDW/",
+ "/zh/isa/inst/misa_g/B.EQ/": "/isa/inst/misa_g/B.EQ/",
+ "/zh/isa/inst/misa_g/B.GE/": "/isa/inst/misa_g/B.GE/",
+ "/zh/isa/inst/misa_g/B.GEU/": "/isa/inst/misa_g/B.GEU/",
+ "/zh/isa/inst/misa_g/B.LT/": "/isa/inst/misa_g/B.LT/",
+ "/zh/isa/inst/misa_g/B.LTU/": "/isa/inst/misa_g/B.LTU/",
+ "/zh/isa/inst/misa_g/B.NE/": "/isa/inst/misa_g/B.NE/",
+ "/zh/isa/inst/misa_g/B.NZ/": "/isa/inst/misa_g/B.NZ/",
+ "/zh/isa/inst/misa_g/B.Z/": "/isa/inst/misa_g/B.Z/",
+ "/zh/isa/inst/misa_g/BCNT/": "/isa/inst/misa_g/BCNT/",
+ "/zh/isa/inst/misa_g/BIC/": "/isa/inst/misa_g/BIC/",
+ "/zh/isa/inst/misa_g/BIS/": "/isa/inst/misa_g/BIS/",
+ "/zh/isa/inst/misa_g/BXS/": "/isa/inst/misa_g/BXS/",
+ "/zh/isa/inst/misa_g/BXU/": "/isa/inst/misa_g/BXU/",
+ "/zh/isa/inst/misa_g/CLZ/": "/isa/inst/misa_g/CLZ/",
+ "/zh/isa/inst/misa_g/CMP.AND/": "/isa/inst/misa_g/CMP.AND/",
+ "/zh/isa/inst/misa_g/CMP.ANDI/": "/isa/inst/misa_g/CMP.ANDI/",
+ "/zh/isa/inst/misa_g/CMP.EQ/": "/isa/inst/misa_g/CMP.EQ/",
+ "/zh/isa/inst/misa_g/CMP.EQI/": "/isa/inst/misa_g/CMP.EQI/",
+ "/zh/isa/inst/misa_g/CMP.GE/": "/isa/inst/misa_g/CMP.GE/",
+ "/zh/isa/inst/misa_g/CMP.GEI/": "/isa/inst/misa_g/CMP.GEI/",
+ "/zh/isa/inst/misa_g/CMP.GEU/": "/isa/inst/misa_g/CMP.GEU/",
+ "/zh/isa/inst/misa_g/CMP.GEUI/": "/isa/inst/misa_g/CMP.GEUI/",
+ "/zh/isa/inst/misa_g/CMP.LT/": "/isa/inst/misa_g/CMP.LT/",
+ "/zh/isa/inst/misa_g/CMP.LTI/": "/isa/inst/misa_g/CMP.LTI/",
+ "/zh/isa/inst/misa_g/CMP.LTU/": "/isa/inst/misa_g/CMP.LTU/",
+ "/zh/isa/inst/misa_g/CMP.LTUI/": "/isa/inst/misa_g/CMP.LTUI/",
+ "/zh/isa/inst/misa_g/CMP.NE/": "/isa/inst/misa_g/CMP.NE/",
+ "/zh/isa/inst/misa_g/CMP.NEI/": "/isa/inst/misa_g/CMP.NEI/",
+ "/zh/isa/inst/misa_g/CMP.OR/": "/isa/inst/misa_g/CMP.OR/",
+ "/zh/isa/inst/misa_g/CMP.ORI/": "/isa/inst/misa_g/CMP.ORI/",
+ "/zh/isa/inst/misa_g/CSEL/": "/isa/inst/misa_g/CSEL/",
+ "/zh/isa/inst/misa_g/CTZ/": "/isa/inst/misa_g/CTZ/",
+ "/zh/isa/inst/misa_g/DIV/": "/isa/inst/misa_g/DIV/",
+ "/zh/isa/inst/misa_g/DIVU/": "/isa/inst/misa_g/DIVU/",
+ "/zh/isa/inst/misa_g/DIVUW/": "/isa/inst/misa_g/DIVUW/",
+ "/zh/isa/inst/misa_g/DIVW/": "/isa/inst/misa_g/DIVW/",
+ "/zh/isa/inst/misa_g/J/": "/isa/inst/misa_g/J/",
+ "/zh/isa/inst/misa_g/JR/": "/isa/inst/misa_g/JR/",
+ "/zh/isa/inst/misa_g/LB.PCR/": "/isa/inst/misa_g/LB.PCR/",
+ "/zh/isa/inst/misa_g/LB/": "/isa/inst/misa_g/LB/",
+ "/zh/isa/inst/misa_g/LBI/": "/isa/inst/misa_g/LBI/",
+ "/zh/isa/inst/misa_g/LBU.PCR/": "/isa/inst/misa_g/LBU.PCR/",
+ "/zh/isa/inst/misa_g/LBU/": "/isa/inst/misa_g/LBU/",
+ "/zh/isa/inst/misa_g/LBUI/": "/isa/inst/misa_g/LBUI/",
+ "/zh/isa/inst/misa_g/LD.PCR/": "/isa/inst/misa_g/LD.PCR/",
+ "/zh/isa/inst/misa_g/LD/": "/isa/inst/misa_g/LD/",
+ "/zh/isa/inst/misa_g/LDI.U/": "/isa/inst/misa_g/LDI.U/",
+ "/zh/isa/inst/misa_g/LDI/": "/isa/inst/misa_g/LDI/",
+ "/zh/isa/inst/misa_g/LH.PCR/": "/isa/inst/misa_g/LH.PCR/",
+ "/zh/isa/inst/misa_g/LH/": "/isa/inst/misa_g/LH/",
+ "/zh/isa/inst/misa_g/LHI.U/": "/isa/inst/misa_g/LHI.U/",
+ "/zh/isa/inst/misa_g/LHI/": "/isa/inst/misa_g/LHI/",
+ "/zh/isa/inst/misa_g/LHU.PCR/": "/isa/inst/misa_g/LHU.PCR/",
+ "/zh/isa/inst/misa_g/LHU/": "/isa/inst/misa_g/LHU/",
+ "/zh/isa/inst/misa_g/LHUI.U/": "/isa/inst/misa_g/LHUI.U/",
+ "/zh/isa/inst/misa_g/LHUI/": "/isa/inst/misa_g/LHUI/",
+ "/zh/isa/inst/misa_g/LSRGET/": "/isa/inst/misa_g/LSRGET/",
+ "/zh/isa/inst/misa_g/LUI/": "/isa/inst/misa_g/LUI/",
+ "/zh/isa/inst/misa_g/LW.PCR/": "/isa/inst/misa_g/LW.PCR/",
+ "/zh/isa/inst/misa_g/LW/": "/isa/inst/misa_g/LW/",
+ "/zh/isa/inst/misa_g/LWI.U/": "/isa/inst/misa_g/LWI.U/",
+ "/zh/isa/inst/misa_g/LWI/": "/isa/inst/misa_g/LWI/",
+ "/zh/isa/inst/misa_g/LWU.PCR/": "/isa/inst/misa_g/LWU.PCR/",
+ "/zh/isa/inst/misa_g/LWU/": "/isa/inst/misa_g/LWU/",
+ "/zh/isa/inst/misa_g/LWUI.U/": "/isa/inst/misa_g/LWUI.U/",
+ "/zh/isa/inst/misa_g/LWUI/": "/isa/inst/misa_g/LWUI/",
+ "/zh/isa/inst/misa_g/MADD/": "/isa/inst/misa_g/MADD/",
+ "/zh/isa/inst/misa_g/MADDW/": "/isa/inst/misa_g/MADDW/",
+ "/zh/isa/inst/misa_g/MUL/": "/isa/inst/misa_g/MUL/",
+ "/zh/isa/inst/misa_g/MULU/": "/isa/inst/misa_g/MULU/",
+ "/zh/isa/inst/misa_g/MULUW/": "/isa/inst/misa_g/MULUW/",
+ "/zh/isa/inst/misa_g/MULW/": "/isa/inst/misa_g/MULW/",
+ "/zh/isa/inst/misa_g/OR/": "/isa/inst/misa_g/OR/",
+ "/zh/isa/inst/misa_g/ORI/": "/isa/inst/misa_g/ORI/",
+ "/zh/isa/inst/misa_g/ORIW/": "/isa/inst/misa_g/ORIW/",
+ "/zh/isa/inst/misa_g/ORW/": "/isa/inst/misa_g/ORW/",
+ "/zh/isa/inst/misa_g/REM/": "/isa/inst/misa_g/REM/",
+ "/zh/isa/inst/misa_g/REMU/": "/isa/inst/misa_g/REMU/",
+ "/zh/isa/inst/misa_g/REMUW/": "/isa/inst/misa_g/REMUW/",
+ "/zh/isa/inst/misa_g/REMW/": "/isa/inst/misa_g/REMW/",
+ "/zh/isa/inst/misa_g/REV/": "/isa/inst/misa_g/REV/",
+ "/zh/isa/inst/misa_g/SB.PCR/": "/isa/inst/misa_g/SB.PCR/",
+ "/zh/isa/inst/misa_g/SB/": "/isa/inst/misa_g/SB/",
+ "/zh/isa/inst/misa_g/SBI/": "/isa/inst/misa_g/SBI/",
+ "/zh/isa/inst/misa_g/SD.PCR/": "/isa/inst/misa_g/SD.PCR/",
+ "/zh/isa/inst/misa_g/SD.U/": "/isa/inst/misa_g/SD.U/",
+ "/zh/isa/inst/misa_g/SD/": "/isa/inst/misa_g/SD/",
+ "/zh/isa/inst/misa_g/SDI.U/": "/isa/inst/misa_g/SDI.U/",
+ "/zh/isa/inst/misa_g/SDI/": "/isa/inst/misa_g/SDI/",
+ "/zh/isa/inst/misa_g/SETC.AND/": "/isa/inst/misa_g/SETC.AND/",
+ "/zh/isa/inst/misa_g/SETC.ANDI/": "/isa/inst/misa_g/SETC.ANDI/",
+ "/zh/isa/inst/misa_g/SETC.EQ/": "/isa/inst/misa_g/SETC.EQ/",
+ "/zh/isa/inst/misa_g/SETC.EQI/": "/isa/inst/misa_g/SETC.EQI/",
+ "/zh/isa/inst/misa_g/SETC.GE/": "/isa/inst/misa_g/SETC.GE/",
+ "/zh/isa/inst/misa_g/SETC.GEI/": "/isa/inst/misa_g/SETC.GEI/",
+ "/zh/isa/inst/misa_g/SETC.GEU/": "/isa/inst/misa_g/SETC.GEU/",
+ "/zh/isa/inst/misa_g/SETC.GEUI/": "/isa/inst/misa_g/SETC.GEUI/",
+ "/zh/isa/inst/misa_g/SETC.LT/": "/isa/inst/misa_g/SETC.LT/",
+ "/zh/isa/inst/misa_g/SETC.LTI/": "/isa/inst/misa_g/SETC.LTI/",
+ "/zh/isa/inst/misa_g/SETC.LTU/": "/isa/inst/misa_g/SETC.LTU/",
+ "/zh/isa/inst/misa_g/SETC.LTUI/": "/isa/inst/misa_g/SETC.LTUI/",
+ "/zh/isa/inst/misa_g/SETC.NE/": "/isa/inst/misa_g/SETC.NE/",
+ "/zh/isa/inst/misa_g/SETC.NEI/": "/isa/inst/misa_g/SETC.NEI/",
+ "/zh/isa/inst/misa_g/SETC.OR/": "/isa/inst/misa_g/SETC.OR/",
+ "/zh/isa/inst/misa_g/SETC.ORI/": "/isa/inst/misa_g/SETC.ORI/",
+ "/zh/isa/inst/misa_g/SETC.TGT/": "/isa/inst/misa_g/SETC.TGT/",
+ "/zh/isa/inst/misa_g/SETRET/": "/isa/inst/misa_g/SETRET/",
+ "/zh/isa/inst/misa_g/SH.PCR/": "/isa/inst/misa_g/SH.PCR/",
+ "/zh/isa/inst/misa_g/SH.U/": "/isa/inst/misa_g/SH.U/",
+ "/zh/isa/inst/misa_g/SH/": "/isa/inst/misa_g/SH/",
+ "/zh/isa/inst/misa_g/SHI.U/": "/isa/inst/misa_g/SHI.U/",
+ "/zh/isa/inst/misa_g/SHI/": "/isa/inst/misa_g/SHI/",
+ "/zh/isa/inst/misa_g/SLL/": "/isa/inst/misa_g/SLL/",
+ "/zh/isa/inst/misa_g/SLLI/": "/isa/inst/misa_g/SLLI/",
+ "/zh/isa/inst/misa_g/SLLIW/": "/isa/inst/misa_g/SLLIW/",
+ "/zh/isa/inst/misa_g/SLLW/": "/isa/inst/misa_g/SLLW/",
+ "/zh/isa/inst/misa_g/SRA/": "/isa/inst/misa_g/SRA/",
+ "/zh/isa/inst/misa_g/SRAI/": "/isa/inst/misa_g/SRAI/",
+ "/zh/isa/inst/misa_g/SRAIW/": "/isa/inst/misa_g/SRAIW/",
+ "/zh/isa/inst/misa_g/SRAW/": "/isa/inst/misa_g/SRAW/",
+ "/zh/isa/inst/misa_g/SRL/": "/isa/inst/misa_g/SRL/",
+ "/zh/isa/inst/misa_g/SRLI/": "/isa/inst/misa_g/SRLI/",
+ "/zh/isa/inst/misa_g/SRLIW/": "/isa/inst/misa_g/SRLIW/",
+ "/zh/isa/inst/misa_g/SRLW/": "/isa/inst/misa_g/SRLW/",
+ "/zh/isa/inst/misa_g/SSRGET/": "/isa/inst/misa_g/SSRGET/",
+ "/zh/isa/inst/misa_g/SSRSET/": "/isa/inst/misa_g/SSRSET/",
+ "/zh/isa/inst/misa_g/SSRSWAP/": "/isa/inst/misa_g/SSRSWAP/",
+ "/zh/isa/inst/misa_g/SUB/": "/isa/inst/misa_g/SUB/",
+ "/zh/isa/inst/misa_g/SUBI/": "/isa/inst/misa_g/SUBI/",
+ "/zh/isa/inst/misa_g/SUBIW/": "/isa/inst/misa_g/SUBIW/",
+ "/zh/isa/inst/misa_g/SUBW/": "/isa/inst/misa_g/SUBW/",
+ "/zh/isa/inst/misa_g/SW.PCR/": "/isa/inst/misa_g/SW.PCR/",
+ "/zh/isa/inst/misa_g/SW.U/": "/isa/inst/misa_g/SW.U/",
+ "/zh/isa/inst/misa_g/SW/": "/isa/inst/misa_g/SW/",
+ "/zh/isa/inst/misa_g/SWI.U/": "/isa/inst/misa_g/SWI.U/",
+ "/zh/isa/inst/misa_g/SWI/": "/isa/inst/misa_g/SWI/",
+ "/zh/isa/inst/misa_g/XOR/": "/isa/inst/misa_g/XOR/",
+ "/zh/isa/inst/misa_g/XORI/": "/isa/inst/misa_g/XORI/",
+ "/zh/isa/inst/misa_g/XORIW/": "/isa/inst/misa_g/XORIW/",
+ "/zh/isa/inst/misa_g/XORW/": "/isa/inst/misa_g/XORW/",
+ "/zh/isa/inst/misa_h/HL.ADDI/": "/isa/inst/misa_h/HL.ADDI/",
+ "/zh/isa/inst/misa_h/HL.ADDIW/": "/isa/inst/misa_h/HL.ADDIW/",
+ "/zh/isa/inst/misa_h/HL.ADDTPC/": "/isa/inst/misa_h/HL.ADDTPC/",
+ "/zh/isa/inst/misa_h/HL.ANDI/": "/isa/inst/misa_h/HL.ANDI/",
+ "/zh/isa/inst/misa_h/HL.ANDIW/": "/isa/inst/misa_h/HL.ANDIW/",
+ "/zh/isa/inst/misa_h/HL.BFI/": "/isa/inst/misa_h/HL.BFI/",
+ "/zh/isa/inst/misa_h/HL.CASB/": "/isa/inst/misa_h/HL.CASB/",
+ "/zh/isa/inst/misa_h/HL.CASD/": "/isa/inst/misa_h/HL.CASD/",
+ "/zh/isa/inst/misa_h/HL.CASH/": "/isa/inst/misa_h/HL.CASH/",
+ "/zh/isa/inst/misa_h/HL.CASW/": "/isa/inst/misa_h/HL.CASW/",
+ "/zh/isa/inst/misa_h/HL.CCAT/": "/isa/inst/misa_h/HL.CCAT/",
+ "/zh/isa/inst/misa_h/HL.CCATW/": "/isa/inst/misa_h/HL.CCATW/",
+ "/zh/isa/inst/misa_h/HL.CMP.ANDI/": "/isa/inst/misa_h/HL.CMP.ANDI/",
+ "/zh/isa/inst/misa_h/HL.CMP.EQI/": "/isa/inst/misa_h/HL.CMP.EQI/",
+ "/zh/isa/inst/misa_h/HL.CMP.GEI/": "/isa/inst/misa_h/HL.CMP.GEI/",
+ "/zh/isa/inst/misa_h/HL.CMP.GEUI/": "/isa/inst/misa_h/HL.CMP.GEUI/",
+ "/zh/isa/inst/misa_h/HL.CMP.LTI/": "/isa/inst/misa_h/HL.CMP.LTI/",
+ "/zh/isa/inst/misa_h/HL.CMP.LTUI/": "/isa/inst/misa_h/HL.CMP.LTUI/",
+ "/zh/isa/inst/misa_h/HL.CMP.NEI/": "/isa/inst/misa_h/HL.CMP.NEI/",
+ "/zh/isa/inst/misa_h/HL.CMP.ORI/": "/isa/inst/misa_h/HL.CMP.ORI/",
+ "/zh/isa/inst/misa_h/HL.DIV/": "/isa/inst/misa_h/HL.DIV/",
+ "/zh/isa/inst/misa_h/HL.DIVU/": "/isa/inst/misa_h/HL.DIVU/",
+ "/zh/isa/inst/misa_h/HL.DIVUW/": "/isa/inst/misa_h/HL.DIVUW/",
+ "/zh/isa/inst/misa_h/HL.DIVW/": "/isa/inst/misa_h/HL.DIVW/",
+ "/zh/isa/inst/misa_h/HL.LB.PCR/": "/isa/inst/misa_h/HL.LB.PCR/",
+ "/zh/isa/inst/misa_h/HL.LB.PO/": "/isa/inst/misa_h/HL.LB.PO/",
+ "/zh/isa/inst/misa_h/HL.LB.PR/": "/isa/inst/misa_h/HL.LB.PR/",
+ "/zh/isa/inst/misa_h/HL.LBI.PO/": "/isa/inst/misa_h/HL.LBI.PO/",
+ "/zh/isa/inst/misa_h/HL.LBI.PR/": "/isa/inst/misa_h/HL.LBI.PR/",
+ "/zh/isa/inst/misa_h/HL.LBI/": "/isa/inst/misa_h/HL.LBI/",
+ "/zh/isa/inst/misa_h/HL.LBIP/": "/isa/inst/misa_h/HL.LBIP/",
+ "/zh/isa/inst/misa_h/HL.LBP/": "/isa/inst/misa_h/HL.LBP/",
+ "/zh/isa/inst/misa_h/HL.LBU.PCR/": "/isa/inst/misa_h/HL.LBU.PCR/",
+ "/zh/isa/inst/misa_h/HL.LBU.PO/": "/isa/inst/misa_h/HL.LBU.PO/",
+ "/zh/isa/inst/misa_h/HL.LBU.PR/": "/isa/inst/misa_h/HL.LBU.PR/",
+ "/zh/isa/inst/misa_h/HL.LBUI.PO/": "/isa/inst/misa_h/HL.LBUI.PO/",
+ "/zh/isa/inst/misa_h/HL.LBUI.PR/": "/isa/inst/misa_h/HL.LBUI.PR/",
+ "/zh/isa/inst/misa_h/HL.LBUI/": "/isa/inst/misa_h/HL.LBUI/",
+ "/zh/isa/inst/misa_h/HL.LBUIP/": "/isa/inst/misa_h/HL.LBUIP/",
+ "/zh/isa/inst/misa_h/HL.LBUP/": "/isa/inst/misa_h/HL.LBUP/",
+ "/zh/isa/inst/misa_h/HL.LD.PCR/": "/isa/inst/misa_h/HL.LD.PCR/",
+ "/zh/isa/inst/misa_h/HL.LD.PO/": "/isa/inst/misa_h/HL.LD.PO/",
+ "/zh/isa/inst/misa_h/HL.LD.PR/": "/isa/inst/misa_h/HL.LD.PR/",
+ "/zh/isa/inst/misa_h/HL.LDI.PO/": "/isa/inst/misa_h/HL.LDI.PO/",
+ "/zh/isa/inst/misa_h/HL.LDI.PR/": "/isa/inst/misa_h/HL.LDI.PR/",
+ "/zh/isa/inst/misa_h/HL.LDI.U/": "/isa/inst/misa_h/HL.LDI.U/",
+ "/zh/isa/inst/misa_h/HL.LDI.UPO/": "/isa/inst/misa_h/HL.LDI.UPO/",
+ "/zh/isa/inst/misa_h/HL.LDI.UPR/": "/isa/inst/misa_h/HL.LDI.UPR/",
+ "/zh/isa/inst/misa_h/HL.LDI/": "/isa/inst/misa_h/HL.LDI/",
+ "/zh/isa/inst/misa_h/HL.LDIP.U/": "/isa/inst/misa_h/HL.LDIP.U/",
+ "/zh/isa/inst/misa_h/HL.LDIP/": "/isa/inst/misa_h/HL.LDIP/",
+ "/zh/isa/inst/misa_h/HL.LDP/": "/isa/inst/misa_h/HL.LDP/",
+ "/zh/isa/inst/misa_h/HL.LH.PCR/": "/isa/inst/misa_h/HL.LH.PCR/",
+ "/zh/isa/inst/misa_h/HL.LH.PO/": "/isa/inst/misa_h/HL.LH.PO/",
+ "/zh/isa/inst/misa_h/HL.LH.PR/": "/isa/inst/misa_h/HL.LH.PR/",
+ "/zh/isa/inst/misa_h/HL.LHI.PO/": "/isa/inst/misa_h/HL.LHI.PO/",
+ "/zh/isa/inst/misa_h/HL.LHI.PR/": "/isa/inst/misa_h/HL.LHI.PR/",
+ "/zh/isa/inst/misa_h/HL.LHI.U/": "/isa/inst/misa_h/HL.LHI.U/",
+ "/zh/isa/inst/misa_h/HL.LHI.UPO/": "/isa/inst/misa_h/HL.LHI.UPO/",
+ "/zh/isa/inst/misa_h/HL.LHI.UPR/": "/isa/inst/misa_h/HL.LHI.UPR/",
+ "/zh/isa/inst/misa_h/HL.LHI/": "/isa/inst/misa_h/HL.LHI/",
+ "/zh/isa/inst/misa_h/HL.LHIP.U/": "/isa/inst/misa_h/HL.LHIP.U/",
+ "/zh/isa/inst/misa_h/HL.LHIP/": "/isa/inst/misa_h/HL.LHIP/",
+ "/zh/isa/inst/misa_h/HL.LHP/": "/isa/inst/misa_h/HL.LHP/",
+ "/zh/isa/inst/misa_h/HL.LHU.PCR/": "/isa/inst/misa_h/HL.LHU.PCR/",
+ "/zh/isa/inst/misa_h/HL.LHU.PO/": "/isa/inst/misa_h/HL.LHU.PO/",
+ "/zh/isa/inst/misa_h/HL.LHU.PR/": "/isa/inst/misa_h/HL.LHU.PR/",
+ "/zh/isa/inst/misa_h/HL.LHUI.PO/": "/isa/inst/misa_h/HL.LHUI.PO/",
+ "/zh/isa/inst/misa_h/HL.LHUI.PR/": "/isa/inst/misa_h/HL.LHUI.PR/",
+ "/zh/isa/inst/misa_h/HL.LHUI.U/": "/isa/inst/misa_h/HL.LHUI.U/",
+ "/zh/isa/inst/misa_h/HL.LHUI.UPO/": "/isa/inst/misa_h/HL.LHUI.UPO/",
+ "/zh/isa/inst/misa_h/HL.LHUI.UPR/": "/isa/inst/misa_h/HL.LHUI.UPR/",
+ "/zh/isa/inst/misa_h/HL.LHUI/": "/isa/inst/misa_h/HL.LHUI/",
+ "/zh/isa/inst/misa_h/HL.LHUIP.U/": "/isa/inst/misa_h/HL.LHUIP.U/",
+ "/zh/isa/inst/misa_h/HL.LHUIP/": "/isa/inst/misa_h/HL.LHUIP/",
+ "/zh/isa/inst/misa_h/HL.LHUP/": "/isa/inst/misa_h/HL.LHUP/",
+ "/zh/isa/inst/misa_h/HL.LIS/": "/isa/inst/misa_h/HL.LIS/",
+ "/zh/isa/inst/misa_h/HL.LIU/": "/isa/inst/misa_h/HL.LIU/",
+ "/zh/isa/inst/misa_h/HL.LUI/": "/isa/inst/misa_h/HL.LUI/",
+ "/zh/isa/inst/misa_h/HL.LW.PCR/": "/isa/inst/misa_h/HL.LW.PCR/",
+ "/zh/isa/inst/misa_h/HL.LW.PO/": "/isa/inst/misa_h/HL.LW.PO/",
+ "/zh/isa/inst/misa_h/HL.LW.PR/": "/isa/inst/misa_h/HL.LW.PR/",
+ "/zh/isa/inst/misa_h/HL.LWI.PO/": "/isa/inst/misa_h/HL.LWI.PO/",
+ "/zh/isa/inst/misa_h/HL.LWI.PR/": "/isa/inst/misa_h/HL.LWI.PR/",
+ "/zh/isa/inst/misa_h/HL.LWI.U/": "/isa/inst/misa_h/HL.LWI.U/",
+ "/zh/isa/inst/misa_h/HL.LWI.UPO/": "/isa/inst/misa_h/HL.LWI.UPO/",
+ "/zh/isa/inst/misa_h/HL.LWI.UPR/": "/isa/inst/misa_h/HL.LWI.UPR/",
+ "/zh/isa/inst/misa_h/HL.LWI/": "/isa/inst/misa_h/HL.LWI/",
+ "/zh/isa/inst/misa_h/HL.LWIP.U/": "/isa/inst/misa_h/HL.LWIP.U/",
+ "/zh/isa/inst/misa_h/HL.LWIP/": "/isa/inst/misa_h/HL.LWIP/",
+ "/zh/isa/inst/misa_h/HL.LWP/": "/isa/inst/misa_h/HL.LWP/",
+ "/zh/isa/inst/misa_h/HL.LWU.PCR/": "/isa/inst/misa_h/HL.LWU.PCR/",
+ "/zh/isa/inst/misa_h/HL.LWU.PO/": "/isa/inst/misa_h/HL.LWU.PO/",
+ "/zh/isa/inst/misa_h/HL.LWU.PR/": "/isa/inst/misa_h/HL.LWU.PR/",
+ "/zh/isa/inst/misa_h/HL.LWUI.PO/": "/isa/inst/misa_h/HL.LWUI.PO/",
+ "/zh/isa/inst/misa_h/HL.LWUI.PR/": "/isa/inst/misa_h/HL.LWUI.PR/",
+ "/zh/isa/inst/misa_h/HL.LWUI.U/": "/isa/inst/misa_h/HL.LWUI.U/",
+ "/zh/isa/inst/misa_h/HL.LWUI.UPO/": "/isa/inst/misa_h/HL.LWUI.UPO/",
+ "/zh/isa/inst/misa_h/HL.LWUI.UPR/": "/isa/inst/misa_h/HL.LWUI.UPR/",
+ "/zh/isa/inst/misa_h/HL.LWUI/": "/isa/inst/misa_h/HL.LWUI/",
+ "/zh/isa/inst/misa_h/HL.LWUIP.U/": "/isa/inst/misa_h/HL.LWUIP.U/",
+ "/zh/isa/inst/misa_h/HL.LWUIP/": "/isa/inst/misa_h/HL.LWUIP/",
+ "/zh/isa/inst/misa_h/HL.LWUP/": "/isa/inst/misa_h/HL.LWUP/",
+ "/zh/isa/inst/misa_h/HL.MADD/": "/isa/inst/misa_h/HL.MADD/",
+ "/zh/isa/inst/misa_h/HL.MADDW/": "/isa/inst/misa_h/HL.MADDW/",
+ "/zh/isa/inst/misa_h/HL.MIADD/": "/isa/inst/misa_h/HL.MIADD/",
+ "/zh/isa/inst/misa_h/HL.MISUB/": "/isa/inst/misa_h/HL.MISUB/",
+ "/zh/isa/inst/misa_h/HL.MUL/": "/isa/inst/misa_h/HL.MUL/",
+ "/zh/isa/inst/misa_h/HL.MULU/": "/isa/inst/misa_h/HL.MULU/",
+ "/zh/isa/inst/misa_h/HL.ORI/": "/isa/inst/misa_h/HL.ORI/",
+ "/zh/isa/inst/misa_h/HL.ORIW/": "/isa/inst/misa_h/HL.ORIW/",
+ "/zh/isa/inst/misa_h/HL.PRF.A/": "/isa/inst/misa_h/HL.PRF.A/",
+ "/zh/isa/inst/misa_h/HL.PRF/": "/isa/inst/misa_h/HL.PRF/",
+ "/zh/isa/inst/misa_h/HL.PRFI.U/": "/isa/inst/misa_h/HL.PRFI.U/",
+ "/zh/isa/inst/misa_h/HL.PRFI.UA/": "/isa/inst/misa_h/HL.PRFI.UA/",
+ "/zh/isa/inst/misa_h/HL.QMT/": "/isa/inst/misa_h/HL.QMT/",
+ "/zh/isa/inst/misa_h/HL.QPOP/": "/isa/inst/misa_h/HL.QPOP/",
+ "/zh/isa/inst/misa_h/HL.QPUSH/": "/isa/inst/misa_h/HL.QPUSH/",
+ "/zh/isa/inst/misa_h/HL.REM/": "/isa/inst/misa_h/HL.REM/",
+ "/zh/isa/inst/misa_h/HL.REMU/": "/isa/inst/misa_h/HL.REMU/",
+ "/zh/isa/inst/misa_h/HL.REMUW/": "/isa/inst/misa_h/HL.REMUW/",
+ "/zh/isa/inst/misa_h/HL.REMW/": "/isa/inst/misa_h/HL.REMW/",
+ "/zh/isa/inst/misa_h/HL.SB.PCR/": "/isa/inst/misa_h/HL.SB.PCR/",
+ "/zh/isa/inst/misa_h/HL.SB.PO/": "/isa/inst/misa_h/HL.SB.PO/",
+ "/zh/isa/inst/misa_h/HL.SB.PR/": "/isa/inst/misa_h/HL.SB.PR/",
+ "/zh/isa/inst/misa_h/HL.SBI.PO/": "/isa/inst/misa_h/HL.SBI.PO/",
+ "/zh/isa/inst/misa_h/HL.SBI.PR/": "/isa/inst/misa_h/HL.SBI.PR/",
+ "/zh/isa/inst/misa_h/HL.SBI/": "/isa/inst/misa_h/HL.SBI/",
+ "/zh/isa/inst/misa_h/HL.SBIP/": "/isa/inst/misa_h/HL.SBIP/",
+ "/zh/isa/inst/misa_h/HL.SBP/": "/isa/inst/misa_h/HL.SBP/",
+ "/zh/isa/inst/misa_h/HL.SD.PCR/": "/isa/inst/misa_h/HL.SD.PCR/",
+ "/zh/isa/inst/misa_h/HL.SD.PO/": "/isa/inst/misa_h/HL.SD.PO/",
+ "/zh/isa/inst/misa_h/HL.SD.PR/": "/isa/inst/misa_h/HL.SD.PR/",
+ "/zh/isa/inst/misa_h/HL.SD.UPO/": "/isa/inst/misa_h/HL.SD.UPO/",
+ "/zh/isa/inst/misa_h/HL.SD.UPR/": "/isa/inst/misa_h/HL.SD.UPR/",
+ "/zh/isa/inst/misa_h/HL.SDI.PO/": "/isa/inst/misa_h/HL.SDI.PO/",
+ "/zh/isa/inst/misa_h/HL.SDI.PR/": "/isa/inst/misa_h/HL.SDI.PR/",
+ "/zh/isa/inst/misa_h/HL.SDI.U/": "/isa/inst/misa_h/HL.SDI.U/",
+ "/zh/isa/inst/misa_h/HL.SDI.UPO/": "/isa/inst/misa_h/HL.SDI.UPO/",
+ "/zh/isa/inst/misa_h/HL.SDI.UPR/": "/isa/inst/misa_h/HL.SDI.UPR/",
+ "/zh/isa/inst/misa_h/HL.SDI/": "/isa/inst/misa_h/HL.SDI/",
+ "/zh/isa/inst/misa_h/HL.SDIP.U/": "/isa/inst/misa_h/HL.SDIP.U/",
+ "/zh/isa/inst/misa_h/HL.SDIP/": "/isa/inst/misa_h/HL.SDIP/",
+ "/zh/isa/inst/misa_h/HL.SDP.U/": "/isa/inst/misa_h/HL.SDP.U/",
+ "/zh/isa/inst/misa_h/HL.SDP/": "/isa/inst/misa_h/HL.SDP/",
+ "/zh/isa/inst/misa_h/HL.SETC.ANDI/": "/isa/inst/misa_h/HL.SETC.ANDI/",
+ "/zh/isa/inst/misa_h/HL.SETC.EQI/": "/isa/inst/misa_h/HL.SETC.EQI/",
+ "/zh/isa/inst/misa_h/HL.SETC.GEI/": "/isa/inst/misa_h/HL.SETC.GEI/",
+ "/zh/isa/inst/misa_h/HL.SETC.GEUI/": "/isa/inst/misa_h/HL.SETC.GEUI/",
+ "/zh/isa/inst/misa_h/HL.SETC.LTI/": "/isa/inst/misa_h/HL.SETC.LTI/",
+ "/zh/isa/inst/misa_h/HL.SETC.LTUI/": "/isa/inst/misa_h/HL.SETC.LTUI/",
+ "/zh/isa/inst/misa_h/HL.SETC.NEI/": "/isa/inst/misa_h/HL.SETC.NEI/",
+ "/zh/isa/inst/misa_h/HL.SETC.ORI/": "/isa/inst/misa_h/HL.SETC.ORI/",
+ "/zh/isa/inst/misa_h/HL.SETRET/": "/isa/inst/misa_h/HL.SETRET/",
+ "/zh/isa/inst/misa_h/HL.SH.PCR/": "/isa/inst/misa_h/HL.SH.PCR/",
+ "/zh/isa/inst/misa_h/HL.SH.PO/": "/isa/inst/misa_h/HL.SH.PO/",
+ "/zh/isa/inst/misa_h/HL.SH.PR/": "/isa/inst/misa_h/HL.SH.PR/",
+ "/zh/isa/inst/misa_h/HL.SH.UPO/": "/isa/inst/misa_h/HL.SH.UPO/",
+ "/zh/isa/inst/misa_h/HL.SH.UPR/": "/isa/inst/misa_h/HL.SH.UPR/",
+ "/zh/isa/inst/misa_h/HL.SHI.PO/": "/isa/inst/misa_h/HL.SHI.PO/",
+ "/zh/isa/inst/misa_h/HL.SHI.PR/": "/isa/inst/misa_h/HL.SHI.PR/",
+ "/zh/isa/inst/misa_h/HL.SHI.U/": "/isa/inst/misa_h/HL.SHI.U/",
+ "/zh/isa/inst/misa_h/HL.SHI.UPO/": "/isa/inst/misa_h/HL.SHI.UPO/",
+ "/zh/isa/inst/misa_h/HL.SHI.UPR/": "/isa/inst/misa_h/HL.SHI.UPR/",
+ "/zh/isa/inst/misa_h/HL.SHI/": "/isa/inst/misa_h/HL.SHI/",
+ "/zh/isa/inst/misa_h/HL.SHIP.U/": "/isa/inst/misa_h/HL.SHIP.U/",
+ "/zh/isa/inst/misa_h/HL.SHIP/": "/isa/inst/misa_h/HL.SHIP/",
+ "/zh/isa/inst/misa_h/HL.SHP.U/": "/isa/inst/misa_h/HL.SHP.U/",
+ "/zh/isa/inst/misa_h/HL.SHP/": "/isa/inst/misa_h/HL.SHP/",
+ "/zh/isa/inst/misa_h/HL.SSRGET/": "/isa/inst/misa_h/HL.SSRGET/",
+ "/zh/isa/inst/misa_h/HL.SSRSET/": "/isa/inst/misa_h/HL.SSRSET/",
+ "/zh/isa/inst/misa_h/HL.SUBI/": "/isa/inst/misa_h/HL.SUBI/",
+ "/zh/isa/inst/misa_h/HL.SUBIW/": "/isa/inst/misa_h/HL.SUBIW/",
+ "/zh/isa/inst/misa_h/HL.SW.PCR/": "/isa/inst/misa_h/HL.SW.PCR/",
+ "/zh/isa/inst/misa_h/HL.SW.PO/": "/isa/inst/misa_h/HL.SW.PO/",
+ "/zh/isa/inst/misa_h/HL.SW.PR/": "/isa/inst/misa_h/HL.SW.PR/",
+ "/zh/isa/inst/misa_h/HL.SW.UPO/": "/isa/inst/misa_h/HL.SW.UPO/",
+ "/zh/isa/inst/misa_h/HL.SW.UPR/": "/isa/inst/misa_h/HL.SW.UPR/",
+ "/zh/isa/inst/misa_h/HL.SWI.PO/": "/isa/inst/misa_h/HL.SWI.PO/",
+ "/zh/isa/inst/misa_h/HL.SWI.PR/": "/isa/inst/misa_h/HL.SWI.PR/",
+ "/zh/isa/inst/misa_h/HL.SWI.U/": "/isa/inst/misa_h/HL.SWI.U/",
+ "/zh/isa/inst/misa_h/HL.SWI.UPO/": "/isa/inst/misa_h/HL.SWI.UPO/",
+ "/zh/isa/inst/misa_h/HL.SWI.UPR/": "/isa/inst/misa_h/HL.SWI.UPR/",
+ "/zh/isa/inst/misa_h/HL.SWI/": "/isa/inst/misa_h/HL.SWI/",
+ "/zh/isa/inst/misa_h/HL.SWIP.U/": "/isa/inst/misa_h/HL.SWIP.U/",
+ "/zh/isa/inst/misa_h/HL.SWIP/": "/isa/inst/misa_h/HL.SWIP/",
+ "/zh/isa/inst/misa_h/HL.SWP.U/": "/isa/inst/misa_h/HL.SWP.U/",
+ "/zh/isa/inst/misa_h/HL.SWP/": "/isa/inst/misa_h/HL.SWP/",
+ "/zh/isa/inst/misa_h/HL.XORI/": "/isa/inst/misa_h/HL.XORI/",
+ "/zh/isa/inst/misa_h/HL.XORIW/": "/isa/inst/misa_h/HL.XORIW/",
+ "/zh/isa/inst/misa_l/L.ADD/": "/isa/inst/misa_l/L.ADD/",
+ "/zh/isa/inst/misa_l/L.ADDI/": "/isa/inst/misa_l/L.ADDI/",
+ "/zh/isa/inst/misa_l/L.ADDLI/": "/isa/inst/misa_l/L.ADDLI/",
+ "/zh/isa/inst/misa_l/L.AND/": "/isa/inst/misa_l/L.AND/",
+ "/zh/isa/inst/misa_l/L.ANDI/": "/isa/inst/misa_l/L.ANDI/",
+ "/zh/isa/inst/misa_l/L.BCNT/": "/isa/inst/misa_l/L.BCNT/",
+ "/zh/isa/inst/misa_l/L.BIC/": "/isa/inst/misa_l/L.BIC/",
+ "/zh/isa/inst/misa_l/L.BIS/": "/isa/inst/misa_l/L.BIS/",
+ "/zh/isa/inst/misa_l/L.BXS/": "/isa/inst/misa_l/L.BXS/",
+ "/zh/isa/inst/misa_l/L.BXU/": "/isa/inst/misa_l/L.BXU/",
+ "/zh/isa/inst/misa_l/L.CASBP/": "/isa/inst/misa_l/L.CASBP/",
+ "/zh/isa/inst/misa_l/L.CASDP/": "/isa/inst/misa_l/L.CASDP/",
+ "/zh/isa/inst/misa_l/L.CASHP/": "/isa/inst/misa_l/L.CASHP/",
+ "/zh/isa/inst/misa_l/L.CASWP/": "/isa/inst/misa_l/L.CASWP/",
+ "/zh/isa/inst/misa_l/L.CLZ/": "/isa/inst/misa_l/L.CLZ/",
+ "/zh/isa/inst/misa_l/L.CMP.AND/": "/isa/inst/misa_l/L.CMP.AND/",
+ "/zh/isa/inst/misa_l/L.CMP.ANDI/": "/isa/inst/misa_l/L.CMP.ANDI/",
+ "/zh/isa/inst/misa_l/L.CMP.EQ/": "/isa/inst/misa_l/L.CMP.EQ/",
+ "/zh/isa/inst/misa_l/L.CMP.EQI/": "/isa/inst/misa_l/L.CMP.EQI/",
+ "/zh/isa/inst/misa_l/L.CMP.GE/": "/isa/inst/misa_l/L.CMP.GE/",
+ "/zh/isa/inst/misa_l/L.CMP.GEI/": "/isa/inst/misa_l/L.CMP.GEI/",
+ "/zh/isa/inst/misa_l/L.CMP.GEU/": "/isa/inst/misa_l/L.CMP.GEU/",
+ "/zh/isa/inst/misa_l/L.CMP.GEUI/": "/isa/inst/misa_l/L.CMP.GEUI/",
+ "/zh/isa/inst/misa_l/L.CMP.LT/": "/isa/inst/misa_l/L.CMP.LT/",
+ "/zh/isa/inst/misa_l/L.CMP.LTI/": "/isa/inst/misa_l/L.CMP.LTI/",
+ "/zh/isa/inst/misa_l/L.CMP.LTU/": "/isa/inst/misa_l/L.CMP.LTU/",
+ "/zh/isa/inst/misa_l/L.CMP.LTUI/": "/isa/inst/misa_l/L.CMP.LTUI/",
+ "/zh/isa/inst/misa_l/L.CMP.NE/": "/isa/inst/misa_l/L.CMP.NE/",
+ "/zh/isa/inst/misa_l/L.CMP.NEI/": "/isa/inst/misa_l/L.CMP.NEI/",
+ "/zh/isa/inst/misa_l/L.CMP.OR/": "/isa/inst/misa_l/L.CMP.OR/",
+ "/zh/isa/inst/misa_l/L.CMP.ORI/": "/isa/inst/misa_l/L.CMP.ORI/",
+ "/zh/isa/inst/misa_l/L.CSEL/": "/isa/inst/misa_l/L.CSEL/",
+ "/zh/isa/inst/misa_l/L.CTZ/": "/isa/inst/misa_l/L.CTZ/",
+ "/zh/isa/inst/misa_l/L.DIV/": "/isa/inst/misa_l/L.DIV/",
+ "/zh/isa/inst/misa_l/L.FABS/": "/isa/inst/misa_l/L.FABS/",
+ "/zh/isa/inst/misa_l/L.FADD/": "/isa/inst/misa_l/L.FADD/",
+ "/zh/isa/inst/misa_l/L.FCLASS/": "/isa/inst/misa_l/L.FCLASS/",
+ "/zh/isa/inst/misa_l/L.FCVT/": "/isa/inst/misa_l/L.FCVT/",
+ "/zh/isa/inst/misa_l/L.FCVTI/": "/isa/inst/misa_l/L.FCVTI/",
+ "/zh/isa/inst/misa_l/L.FDIV/": "/isa/inst/misa_l/L.FDIV/",
+ "/zh/isa/inst/misa_l/L.FEQ/": "/isa/inst/misa_l/L.FEQ/",
+ "/zh/isa/inst/misa_l/L.FEQS/": "/isa/inst/misa_l/L.FEQS/",
+ "/zh/isa/inst/misa_l/L.FEXP/": "/isa/inst/misa_l/L.FEXP/",
+ "/zh/isa/inst/misa_l/L.FGE/": "/isa/inst/misa_l/L.FGE/",
+ "/zh/isa/inst/misa_l/L.FGES/": "/isa/inst/misa_l/L.FGES/",
+ "/zh/isa/inst/misa_l/L.FLT/": "/isa/inst/misa_l/L.FLT/",
+ "/zh/isa/inst/misa_l/L.FLTS/": "/isa/inst/misa_l/L.FLTS/",
+ "/zh/isa/inst/misa_l/L.FMADD/": "/isa/inst/misa_l/L.FMADD/",
+ "/zh/isa/inst/misa_l/L.FMAX/": "/isa/inst/misa_l/L.FMAX/",
+ "/zh/isa/inst/misa_l/L.FMIN/": "/isa/inst/misa_l/L.FMIN/",
+ "/zh/isa/inst/misa_l/L.FMSUB/": "/isa/inst/misa_l/L.FMSUB/",
+ "/zh/isa/inst/misa_l/L.FMUL/": "/isa/inst/misa_l/L.FMUL/",
+ "/zh/isa/inst/misa_l/L.FNE/": "/isa/inst/misa_l/L.FNE/",
+ "/zh/isa/inst/misa_l/L.FNES/": "/isa/inst/misa_l/L.FNES/",
+ "/zh/isa/inst/misa_l/L.FNMADD/": "/isa/inst/misa_l/L.FNMADD/",
+ "/zh/isa/inst/misa_l/L.FNMSUB/": "/isa/inst/misa_l/L.FNMSUB/",
+ "/zh/isa/inst/misa_l/L.FRECIP/": "/isa/inst/misa_l/L.FRECIP/",
+ "/zh/isa/inst/misa_l/L.FSQRT/": "/isa/inst/misa_l/L.FSQRT/",
+ "/zh/isa/inst/misa_l/L.FSUB/": "/isa/inst/misa_l/L.FSUB/",
+ "/zh/isa/inst/misa_l/L.ICVT/": "/isa/inst/misa_l/L.ICVT/",
+ "/zh/isa/inst/misa_l/L.ICVTF/": "/isa/inst/misa_l/L.ICVTF/",
+ "/zh/isa/inst/misa_l/L.LB.PCR/": "/isa/inst/misa_l/L.LB.PCR/",
+ "/zh/isa/inst/misa_l/L.LB/": "/isa/inst/misa_l/L.LB/",
+ "/zh/isa/inst/misa_l/L.LBI/": "/isa/inst/misa_l/L.LBI/",
+ "/zh/isa/inst/misa_l/L.LBU.PCR/": "/isa/inst/misa_l/L.LBU.PCR/",
+ "/zh/isa/inst/misa_l/L.LBU/": "/isa/inst/misa_l/L.LBU/",
+ "/zh/isa/inst/misa_l/L.LBUI/": "/isa/inst/misa_l/L.LBUI/",
+ "/zh/isa/inst/misa_l/L.LD.ADD/": "/isa/inst/misa_l/L.LD.ADD/",
+ "/zh/isa/inst/misa_l/L.LD.AND/": "/isa/inst/misa_l/L.LD.AND/",
+ "/zh/isa/inst/misa_l/L.LD.MAX/": "/isa/inst/misa_l/L.LD.MAX/",
+ "/zh/isa/inst/misa_l/L.LD.MIN/": "/isa/inst/misa_l/L.LD.MIN/",
+ "/zh/isa/inst/misa_l/L.LD.OR/": "/isa/inst/misa_l/L.LD.OR/",
+ "/zh/isa/inst/misa_l/L.LD.PCR/": "/isa/inst/misa_l/L.LD.PCR/",
+ "/zh/isa/inst/misa_l/L.LD.XOR/": "/isa/inst/misa_l/L.LD.XOR/",
+ "/zh/isa/inst/misa_l/L.LD/": "/isa/inst/misa_l/L.LD/",
+ "/zh/isa/inst/misa_l/L.LDI.U/": "/isa/inst/misa_l/L.LDI.U/",
+ "/zh/isa/inst/misa_l/L.LDI/": "/isa/inst/misa_l/L.LDI/",
+ "/zh/isa/inst/misa_l/L.LH.PCR/": "/isa/inst/misa_l/L.LH.PCR/",
+ "/zh/isa/inst/misa_l/L.LH/": "/isa/inst/misa_l/L.LH/",
+ "/zh/isa/inst/misa_l/L.LHI.U/": "/isa/inst/misa_l/L.LHI.U/",
+ "/zh/isa/inst/misa_l/L.LHI/": "/isa/inst/misa_l/L.LHI/",
+ "/zh/isa/inst/misa_l/L.LHU.PCR/": "/isa/inst/misa_l/L.LHU.PCR/",
+ "/zh/isa/inst/misa_l/L.LHU/": "/isa/inst/misa_l/L.LHU/",
+ "/zh/isa/inst/misa_l/L.LHUI.U/": "/isa/inst/misa_l/L.LHUI.U/",
+ "/zh/isa/inst/misa_l/L.LHUI/": "/isa/inst/misa_l/L.LHUI/",
+ "/zh/isa/inst/misa_l/L.LW.ADD/": "/isa/inst/misa_l/L.LW.ADD/",
+ "/zh/isa/inst/misa_l/L.LW.AND/": "/isa/inst/misa_l/L.LW.AND/",
+ "/zh/isa/inst/misa_l/L.LW.MAX/": "/isa/inst/misa_l/L.LW.MAX/",
+ "/zh/isa/inst/misa_l/L.LW.MIN/": "/isa/inst/misa_l/L.LW.MIN/",
+ "/zh/isa/inst/misa_l/L.LW.OR/": "/isa/inst/misa_l/L.LW.OR/",
+ "/zh/isa/inst/misa_l/L.LW.PCR/": "/isa/inst/misa_l/L.LW.PCR/",
+ "/zh/isa/inst/misa_l/L.LW.XOR/": "/isa/inst/misa_l/L.LW.XOR/",
+ "/zh/isa/inst/misa_l/L.LW/": "/isa/inst/misa_l/L.LW/",
+ "/zh/isa/inst/misa_l/L.LWI.U/": "/isa/inst/misa_l/L.LWI.U/",
+ "/zh/isa/inst/misa_l/L.LWI/": "/isa/inst/misa_l/L.LWI/",
+ "/zh/isa/inst/misa_l/L.LWU.PCR/": "/isa/inst/misa_l/L.LWU.PCR/",
+ "/zh/isa/inst/misa_l/L.LWU/": "/isa/inst/misa_l/L.LWU/",
+ "/zh/isa/inst/misa_l/L.LWUI.U/": "/isa/inst/misa_l/L.LWUI.U/",
+ "/zh/isa/inst/misa_l/L.LWUI/": "/isa/inst/misa_l/L.LWUI/",
+ "/zh/isa/inst/misa_l/L.MADD/": "/isa/inst/misa_l/L.MADD/",
+ "/zh/isa/inst/misa_l/L.MAX/": "/isa/inst/misa_l/L.MAX/",
+ "/zh/isa/inst/misa_l/L.MIN/": "/isa/inst/misa_l/L.MIN/",
+ "/zh/isa/inst/misa_l/L.MUL/": "/isa/inst/misa_l/L.MUL/",
+ "/zh/isa/inst/misa_l/L.OR/": "/isa/inst/misa_l/L.OR/",
+ "/zh/isa/inst/misa_l/L.ORI/": "/isa/inst/misa_l/L.ORI/",
+ "/zh/isa/inst/misa_l/L.QPOP/": "/isa/inst/misa_l/L.QPOP/",
+ "/zh/isa/inst/misa_l/L.QPUSH/": "/isa/inst/misa_l/L.QPUSH/",
+ "/zh/isa/inst/misa_l/L.REM/": "/isa/inst/misa_l/L.REM/",
+ "/zh/isa/inst/misa_l/L.REV/": "/isa/inst/misa_l/L.REV/",
+ "/zh/isa/inst/misa_l/L.SB.PCR/": "/isa/inst/misa_l/L.SB.PCR/",
+ "/zh/isa/inst/misa_l/L.SB/": "/isa/inst/misa_l/L.SB/",
+ "/zh/isa/inst/misa_l/L.SBI/": "/isa/inst/misa_l/L.SBI/",
+ "/zh/isa/inst/misa_l/L.SD.ADD/": "/isa/inst/misa_l/L.SD.ADD/",
+ "/zh/isa/inst/misa_l/L.SD.AND/": "/isa/inst/misa_l/L.SD.AND/",
+ "/zh/isa/inst/misa_l/L.SD.MAX/": "/isa/inst/misa_l/L.SD.MAX/",
+ "/zh/isa/inst/misa_l/L.SD.MIN/": "/isa/inst/misa_l/L.SD.MIN/",
+ "/zh/isa/inst/misa_l/L.SD.OR/": "/isa/inst/misa_l/L.SD.OR/",
+ "/zh/isa/inst/misa_l/L.SD.PCR/": "/isa/inst/misa_l/L.SD.PCR/",
+ "/zh/isa/inst/misa_l/L.SD.U/": "/isa/inst/misa_l/L.SD.U/",
+ "/zh/isa/inst/misa_l/L.SD.XOR/": "/isa/inst/misa_l/L.SD.XOR/",
+ "/zh/isa/inst/misa_l/L.SD/": "/isa/inst/misa_l/L.SD/",
+ "/zh/isa/inst/misa_l/L.SDI.U/": "/isa/inst/misa_l/L.SDI.U/",
+ "/zh/isa/inst/misa_l/L.SDI/": "/isa/inst/misa_l/L.SDI/",
+ "/zh/isa/inst/misa_l/L.SH.PCR/": "/isa/inst/misa_l/L.SH.PCR/",
+ "/zh/isa/inst/misa_l/L.SH.U/": "/isa/inst/misa_l/L.SH.U/",
+ "/zh/isa/inst/misa_l/L.SH/": "/isa/inst/misa_l/L.SH/",
+ "/zh/isa/inst/misa_l/L.SHI.U/": "/isa/inst/misa_l/L.SHI.U/",
+ "/zh/isa/inst/misa_l/L.SHI/": "/isa/inst/misa_l/L.SHI/",
+ "/zh/isa/inst/misa_l/L.SLL/": "/isa/inst/misa_l/L.SLL/",
+ "/zh/isa/inst/misa_l/L.SLLI/": "/isa/inst/misa_l/L.SLLI/",
+ "/zh/isa/inst/misa_l/L.SRA/": "/isa/inst/misa_l/L.SRA/",
+ "/zh/isa/inst/misa_l/L.SRAI/": "/isa/inst/misa_l/L.SRAI/",
+ "/zh/isa/inst/misa_l/L.SRL/": "/isa/inst/misa_l/L.SRL/",
+ "/zh/isa/inst/misa_l/L.SRLI/": "/isa/inst/misa_l/L.SRLI/",
+ "/zh/isa/inst/misa_l/L.SUB/": "/isa/inst/misa_l/L.SUB/",
+ "/zh/isa/inst/misa_l/L.SUBI/": "/isa/inst/misa_l/L.SUBI/",
+ "/zh/isa/inst/misa_l/L.SW.ADD/": "/isa/inst/misa_l/L.SW.ADD/",
+ "/zh/isa/inst/misa_l/L.SW.AND/": "/isa/inst/misa_l/L.SW.AND/",
+ "/zh/isa/inst/misa_l/L.SW.MAX/": "/isa/inst/misa_l/L.SW.MAX/",
+ "/zh/isa/inst/misa_l/L.SW.MIN/": "/isa/inst/misa_l/L.SW.MIN/",
+ "/zh/isa/inst/misa_l/L.SW.OR/": "/isa/inst/misa_l/L.SW.OR/",
+ "/zh/isa/inst/misa_l/L.SW.PCR/": "/isa/inst/misa_l/L.SW.PCR/",
+ "/zh/isa/inst/misa_l/L.SW.U/": "/isa/inst/misa_l/L.SW.U/",
+ "/zh/isa/inst/misa_l/L.SW.XOR/": "/isa/inst/misa_l/L.SW.XOR/",
+ "/zh/isa/inst/misa_l/L.SW/": "/isa/inst/misa_l/L.SW/",
+ "/zh/isa/inst/misa_l/L.SWI.U/": "/isa/inst/misa_l/L.SWI.U/",
+ "/zh/isa/inst/misa_l/L.SWI/": "/isa/inst/misa_l/L.SWI/",
+ "/zh/isa/inst/misa_l/L.XOR/": "/isa/inst/misa_l/L.XOR/",
+ "/zh/isa/inst/misa_l/L.XORI/": "/isa/inst/misa_l/L.XORI/",
+ "/zh/isa/inst/misa_s/ACRC/": "/isa/inst/misa_s/ACRC/",
+ "/zh/isa/inst/misa_s/ACRE/": "/isa/inst/misa_s/ACRE/",
+ "/zh/isa/inst/misa_s/ASSERT/": "/isa/inst/misa_s/ASSERT/",
+ "/zh/isa/inst/misa_s/BC.IALL/": "/isa/inst/misa_s/BC.IALL/",
+ "/zh/isa/inst/misa_s/BC.IVA/": "/isa/inst/misa_s/BC.IVA/",
+ "/zh/isa/inst/misa_s/BSE/": "/isa/inst/misa_s/BSE/",
+ "/zh/isa/inst/misa_s/BWE/": "/isa/inst/misa_s/BWE/",
+ "/zh/isa/inst/misa_s/BWI/": "/isa/inst/misa_s/BWI/",
+ "/zh/isa/inst/misa_s/BWT/": "/isa/inst/misa_s/BWT/",
+ "/zh/isa/inst/misa_s/DC.CISW/": "/isa/inst/misa_s/DC.CISW/",
+ "/zh/isa/inst/misa_s/DC.CIVA/": "/isa/inst/misa_s/DC.CIVA/",
+ "/zh/isa/inst/misa_s/DC.CSW/": "/isa/inst/misa_s/DC.CSW/",
+ "/zh/isa/inst/misa_s/DC.CVA/": "/isa/inst/misa_s/DC.CVA/",
+ "/zh/isa/inst/misa_s/DC.IALL/": "/isa/inst/misa_s/DC.IALL/",
+ "/zh/isa/inst/misa_s/DC.ISW/": "/isa/inst/misa_s/DC.ISW/",
+ "/zh/isa/inst/misa_s/DC.IVA/": "/isa/inst/misa_s/DC.IVA/",
+ "/zh/isa/inst/misa_s/DC.ZVA/": "/isa/inst/misa_s/DC.ZVA/",
+ "/zh/isa/inst/misa_s/DMA/": "/isa/inst/misa_s/DMA/",
+ "/zh/isa/inst/misa_s/DSB/": "/isa/inst/misa_s/DSB/",
+ "/zh/isa/inst/misa_s/EBREAK/": "/isa/inst/misa_s/EBREAK/",
+ "/zh/isa/inst/misa_s/IC.IALL/": "/isa/inst/misa_s/IC.IALL/",
+ "/zh/isa/inst/misa_s/IC.IVA/": "/isa/inst/misa_s/IC.IVA/",
+ "/zh/isa/inst/misa_s/ISB/": "/isa/inst/misa_s/ISB/",
+ "/zh/isa/inst/misa_s/LD.ADD/": "/isa/inst/misa_s/LD.ADD/",
+ "/zh/isa/inst/misa_s/LD.AND/": "/isa/inst/misa_s/LD.AND/",
+ "/zh/isa/inst/misa_s/LD.OR/": "/isa/inst/misa_s/LD.OR/",
+ "/zh/isa/inst/misa_s/LD.SMAX/": "/isa/inst/misa_s/LD.SMAX/",
+ "/zh/isa/inst/misa_s/LD.SMIN/": "/isa/inst/misa_s/LD.SMIN/",
+ "/zh/isa/inst/misa_s/LD.UMAX/": "/isa/inst/misa_s/LD.UMAX/",
+ "/zh/isa/inst/misa_s/LD.UMIN/": "/isa/inst/misa_s/LD.UMIN/",
+ "/zh/isa/inst/misa_s/LD.XOR/": "/isa/inst/misa_s/LD.XOR/",
+ "/zh/isa/inst/misa_s/LR.B/": "/isa/inst/misa_s/LR.B/",
+ "/zh/isa/inst/misa_s/LR.D/": "/isa/inst/misa_s/LR.D/",
+ "/zh/isa/inst/misa_s/LR.H/": "/isa/inst/misa_s/LR.H/",
+ "/zh/isa/inst/misa_s/LR.W/": "/isa/inst/misa_s/LR.W/",
+ "/zh/isa/inst/misa_s/LW.ADD/": "/isa/inst/misa_s/LW.ADD/",
+ "/zh/isa/inst/misa_s/LW.AND/": "/isa/inst/misa_s/LW.AND/",
+ "/zh/isa/inst/misa_s/LW.OR/": "/isa/inst/misa_s/LW.OR/",
+ "/zh/isa/inst/misa_s/LW.SMAX/": "/isa/inst/misa_s/LW.SMAX/",
+ "/zh/isa/inst/misa_s/LW.SMIN/": "/isa/inst/misa_s/LW.SMIN/",
+ "/zh/isa/inst/misa_s/LW.UMAX/": "/isa/inst/misa_s/LW.UMAX/",
+ "/zh/isa/inst/misa_s/LW.UMIN/": "/isa/inst/misa_s/LW.UMIN/",
+ "/zh/isa/inst/misa_s/LW.XOR/": "/isa/inst/misa_s/LW.XOR/",
+ "/zh/isa/inst/misa_s/SC.B/": "/isa/inst/misa_s/SC.B/",
+ "/zh/isa/inst/misa_s/SC.D/": "/isa/inst/misa_s/SC.D/",
+ "/zh/isa/inst/misa_s/SC.H/": "/isa/inst/misa_s/SC.H/",
+ "/zh/isa/inst/misa_s/SC.W/": "/isa/inst/misa_s/SC.W/",
+ "/zh/isa/inst/misa_s/SD.ADD/": "/isa/inst/misa_s/SD.ADD/",
+ "/zh/isa/inst/misa_s/SD.AND/": "/isa/inst/misa_s/SD.AND/",
+ "/zh/isa/inst/misa_s/SD.OR/": "/isa/inst/misa_s/SD.OR/",
+ "/zh/isa/inst/misa_s/SD.SMAX/": "/isa/inst/misa_s/SD.SMAX/",
+ "/zh/isa/inst/misa_s/SD.SMIN/": "/isa/inst/misa_s/SD.SMIN/",
+ "/zh/isa/inst/misa_s/SD.UMAX/": "/isa/inst/misa_s/SD.UMAX/",
+ "/zh/isa/inst/misa_s/SD.UMIN/": "/isa/inst/misa_s/SD.UMIN/",
+ "/zh/isa/inst/misa_s/SD.XOR/": "/isa/inst/misa_s/SD.XOR/",
+ "/zh/isa/inst/misa_s/SW.ADD/": "/isa/inst/misa_s/SW.ADD/",
+ "/zh/isa/inst/misa_s/SW.AND/": "/isa/inst/misa_s/SW.AND/",
+ "/zh/isa/inst/misa_s/SW.OR/": "/isa/inst/misa_s/SW.OR/",
+ "/zh/isa/inst/misa_s/SW.SMAX/": "/isa/inst/misa_s/SW.SMAX/",
+ "/zh/isa/inst/misa_s/SW.SMIN/": "/isa/inst/misa_s/SW.SMIN/",
+ "/zh/isa/inst/misa_s/SW.UMAX/": "/isa/inst/misa_s/SW.UMAX/",
+ "/zh/isa/inst/misa_s/SW.UMIN/": "/isa/inst/misa_s/SW.UMIN/",
+ "/zh/isa/inst/misa_s/SW.XOR/": "/isa/inst/misa_s/SW.XOR/",
+ "/zh/isa/inst/misa_s/SWAPB/": "/isa/inst/misa_s/SWAPB/",
+ "/zh/isa/inst/misa_s/SWAPD/": "/isa/inst/misa_s/SWAPD/",
+ "/zh/isa/inst/misa_s/SWAPH/": "/isa/inst/misa_s/SWAPH/",
+ "/zh/isa/inst/misa_s/SWAPW/": "/isa/inst/misa_s/SWAPW/",
+ "/zh/isa/inst/misa_s/TC.IA/": "/isa/inst/misa_s/TC.IA/",
+ "/zh/isa/inst/misa_s/TC.IALL/": "/isa/inst/misa_s/TC.IALL/",
+ "/zh/isa/inst/misa_s/TC.IAV/": "/isa/inst/misa_s/TC.IAV/",
+ "/zh/isa/inst/misa_s/TC.IV/": "/isa/inst/misa_s/TC.IV/",
+ "/zh/isa/inst/misa_v/V.ADD/": "/isa/inst/misa_v/V.ADD/",
+ "/zh/isa/inst/misa_v/V.ADDI/": "/isa/inst/misa_v/V.ADDI/",
+ "/zh/isa/inst/misa_v/V.AND/": "/isa/inst/misa_v/V.AND/",
+ "/zh/isa/inst/misa_v/V.ANDI/": "/isa/inst/misa_v/V.ANDI/",
+ "/zh/isa/inst/misa_v/V.BCNT/": "/isa/inst/misa_v/V.BCNT/",
+ "/zh/isa/inst/misa_v/V.BIC/": "/isa/inst/misa_v/V.BIC/",
+ "/zh/isa/inst/misa_v/V.BIS/": "/isa/inst/misa_v/V.BIS/",
+ "/zh/isa/inst/misa_v/V.BXS/": "/isa/inst/misa_v/V.BXS/",
+ "/zh/isa/inst/misa_v/V.BXU/": "/isa/inst/misa_v/V.BXU/",
+ "/zh/isa/inst/misa_v/V.CLZ/": "/isa/inst/misa_v/V.CLZ/",
+ "/zh/isa/inst/misa_v/V.CMP.AND/": "/isa/inst/misa_v/V.CMP.AND/",
+ "/zh/isa/inst/misa_v/V.CMP.ANDI/": "/isa/inst/misa_v/V.CMP.ANDI/",
+ "/zh/isa/inst/misa_v/V.CMP.EQ/": "/isa/inst/misa_v/V.CMP.EQ/",
+ "/zh/isa/inst/misa_v/V.CMP.EQI/": "/isa/inst/misa_v/V.CMP.EQI/",
+ "/zh/isa/inst/misa_v/V.CMP.GE/": "/isa/inst/misa_v/V.CMP.GE/",
+ "/zh/isa/inst/misa_v/V.CMP.GEI/": "/isa/inst/misa_v/V.CMP.GEI/",
+ "/zh/isa/inst/misa_v/V.CMP.GEU/": "/isa/inst/misa_v/V.CMP.GEU/",
+ "/zh/isa/inst/misa_v/V.CMP.GEUI/": "/isa/inst/misa_v/V.CMP.GEUI/",
+ "/zh/isa/inst/misa_v/V.CMP.LT/": "/isa/inst/misa_v/V.CMP.LT/",
+ "/zh/isa/inst/misa_v/V.CMP.LTI/": "/isa/inst/misa_v/V.CMP.LTI/",
+ "/zh/isa/inst/misa_v/V.CMP.LTU/": "/isa/inst/misa_v/V.CMP.LTU/",
+ "/zh/isa/inst/misa_v/V.CMP.LTUI/": "/isa/inst/misa_v/V.CMP.LTUI/",
+ "/zh/isa/inst/misa_v/V.CMP.NE/": "/isa/inst/misa_v/V.CMP.NE/",
+ "/zh/isa/inst/misa_v/V.CMP.NEI/": "/isa/inst/misa_v/V.CMP.NEI/",
+ "/zh/isa/inst/misa_v/V.CMP.OR/": "/isa/inst/misa_v/V.CMP.OR/",
+ "/zh/isa/inst/misa_v/V.CMP.ORI/": "/isa/inst/misa_v/V.CMP.ORI/",
+ "/zh/isa/inst/misa_v/V.CSEL/": "/isa/inst/misa_v/V.CSEL/",
+ "/zh/isa/inst/misa_v/V.CTZ/": "/isa/inst/misa_v/V.CTZ/",
+ "/zh/isa/inst/misa_v/V.DIV/": "/isa/inst/misa_v/V.DIV/",
+ "/zh/isa/inst/misa_v/V.FABS/": "/isa/inst/misa_v/V.FABS/",
+ "/zh/isa/inst/misa_v/V.FADD/": "/isa/inst/misa_v/V.FADD/",
+ "/zh/isa/inst/misa_v/V.FCLASS/": "/isa/inst/misa_v/V.FCLASS/",
+ "/zh/isa/inst/misa_v/V.FCVT/": "/isa/inst/misa_v/V.FCVT/",
+ "/zh/isa/inst/misa_v/V.FCVTI/": "/isa/inst/misa_v/V.FCVTI/",
+ "/zh/isa/inst/misa_v/V.FDIV/": "/isa/inst/misa_v/V.FDIV/",
+ "/zh/isa/inst/misa_v/V.FEQ/": "/isa/inst/misa_v/V.FEQ/",
+ "/zh/isa/inst/misa_v/V.FEQS/": "/isa/inst/misa_v/V.FEQS/",
+ "/zh/isa/inst/misa_v/V.FEXP/": "/isa/inst/misa_v/V.FEXP/",
+ "/zh/isa/inst/misa_v/V.FGE/": "/isa/inst/misa_v/V.FGE/",
+ "/zh/isa/inst/misa_v/V.FGES/": "/isa/inst/misa_v/V.FGES/",
+ "/zh/isa/inst/misa_v/V.FLT/": "/isa/inst/misa_v/V.FLT/",
+ "/zh/isa/inst/misa_v/V.FLTS/": "/isa/inst/misa_v/V.FLTS/",
+ "/zh/isa/inst/misa_v/V.FMADD/": "/isa/inst/misa_v/V.FMADD/",
+ "/zh/isa/inst/misa_v/V.FMAX/": "/isa/inst/misa_v/V.FMAX/",
+ "/zh/isa/inst/misa_v/V.FMIN/": "/isa/inst/misa_v/V.FMIN/",
+ "/zh/isa/inst/misa_v/V.FMSUB/": "/isa/inst/misa_v/V.FMSUB/",
+ "/zh/isa/inst/misa_v/V.FMUL/": "/isa/inst/misa_v/V.FMUL/",
+ "/zh/isa/inst/misa_v/V.FNE/": "/isa/inst/misa_v/V.FNE/",
+ "/zh/isa/inst/misa_v/V.FNES/": "/isa/inst/misa_v/V.FNES/",
+ "/zh/isa/inst/misa_v/V.FNMADD/": "/isa/inst/misa_v/V.FNMADD/",
+ "/zh/isa/inst/misa_v/V.FNMSUB/": "/isa/inst/misa_v/V.FNMSUB/",
+ "/zh/isa/inst/misa_v/V.FRECIP/": "/isa/inst/misa_v/V.FRECIP/",
+ "/zh/isa/inst/misa_v/V.FSQRT/": "/isa/inst/misa_v/V.FSQRT/",
+ "/zh/isa/inst/misa_v/V.FSUB/": "/isa/inst/misa_v/V.FSUB/",
+ "/zh/isa/inst/misa_v/V.ICVT/": "/isa/inst/misa_v/V.ICVT/",
+ "/zh/isa/inst/misa_v/V.ICVTF/": "/isa/inst/misa_v/V.ICVTF/",
+ "/zh/isa/inst/misa_v/V.LB.BRG/": "/isa/inst/misa_v/V.LB.BRG/",
+ "/zh/isa/inst/misa_v/V.LB/": "/isa/inst/misa_v/V.LB/",
+ "/zh/isa/inst/misa_v/V.LBI.BRG/": "/isa/inst/misa_v/V.LBI.BRG/",
+ "/zh/isa/inst/misa_v/V.LBI/": "/isa/inst/misa_v/V.LBI/",
+ "/zh/isa/inst/misa_v/V.LBU.BRG/": "/isa/inst/misa_v/V.LBU.BRG/",
+ "/zh/isa/inst/misa_v/V.LBU/": "/isa/inst/misa_v/V.LBU/",
+ "/zh/isa/inst/misa_v/V.LBUI.BRG/": "/isa/inst/misa_v/V.LBUI.BRG/",
+ "/zh/isa/inst/misa_v/V.LBUI/": "/isa/inst/misa_v/V.LBUI/",
+ "/zh/isa/inst/misa_v/V.LD.ADD/": "/isa/inst/misa_v/V.LD.ADD/",
+ "/zh/isa/inst/misa_v/V.LD.AND/": "/isa/inst/misa_v/V.LD.AND/",
+ "/zh/isa/inst/misa_v/V.LD.BRG/": "/isa/inst/misa_v/V.LD.BRG/",
+ "/zh/isa/inst/misa_v/V.LD.MAX/": "/isa/inst/misa_v/V.LD.MAX/",
+ "/zh/isa/inst/misa_v/V.LD.MIN/": "/isa/inst/misa_v/V.LD.MIN/",
+ "/zh/isa/inst/misa_v/V.LD.OR/": "/isa/inst/misa_v/V.LD.OR/",
+ "/zh/isa/inst/misa_v/V.LD.XOR/": "/isa/inst/misa_v/V.LD.XOR/",
+ "/zh/isa/inst/misa_v/V.LD/": "/isa/inst/misa_v/V.LD/",
+ "/zh/isa/inst/misa_v/V.LDI.BRG/": "/isa/inst/misa_v/V.LDI.BRG/",
+ "/zh/isa/inst/misa_v/V.LDI.U/": "/isa/inst/misa_v/V.LDI.U/",
+ "/zh/isa/inst/misa_v/V.LDI.UBRG/": "/isa/inst/misa_v/V.LDI.UBRG/",
+ "/zh/isa/inst/misa_v/V.LDI/": "/isa/inst/misa_v/V.LDI/",
+ "/zh/isa/inst/misa_v/V.LH.BRG/": "/isa/inst/misa_v/V.LH.BRG/",
+ "/zh/isa/inst/misa_v/V.LH/": "/isa/inst/misa_v/V.LH/",
+ "/zh/isa/inst/misa_v/V.LHI.BRG/": "/isa/inst/misa_v/V.LHI.BRG/",
+ "/zh/isa/inst/misa_v/V.LHI.U/": "/isa/inst/misa_v/V.LHI.U/",
+ "/zh/isa/inst/misa_v/V.LHI.UBRG/": "/isa/inst/misa_v/V.LHI.UBRG/",
+ "/zh/isa/inst/misa_v/V.LHI/": "/isa/inst/misa_v/V.LHI/",
+ "/zh/isa/inst/misa_v/V.LHU.BRG/": "/isa/inst/misa_v/V.LHU.BRG/",
+ "/zh/isa/inst/misa_v/V.LHU/": "/isa/inst/misa_v/V.LHU/",
+ "/zh/isa/inst/misa_v/V.LHUI.BRG/": "/isa/inst/misa_v/V.LHUI.BRG/",
+ "/zh/isa/inst/misa_v/V.LHUI.U/": "/isa/inst/misa_v/V.LHUI.U/",
+ "/zh/isa/inst/misa_v/V.LHUI.UBRG/": "/isa/inst/misa_v/V.LHUI.UBRG/",
+ "/zh/isa/inst/misa_v/V.LHUI/": "/isa/inst/misa_v/V.LHUI/",
+ "/zh/isa/inst/misa_v/V.LW.ADD/": "/isa/inst/misa_v/V.LW.ADD/",
+ "/zh/isa/inst/misa_v/V.LW.AND/": "/isa/inst/misa_v/V.LW.AND/",
+ "/zh/isa/inst/misa_v/V.LW.BRG/": "/isa/inst/misa_v/V.LW.BRG/",
+ "/zh/isa/inst/misa_v/V.LW.MAX/": "/isa/inst/misa_v/V.LW.MAX/",
+ "/zh/isa/inst/misa_v/V.LW.MIN/": "/isa/inst/misa_v/V.LW.MIN/",
+ "/zh/isa/inst/misa_v/V.LW.OR/": "/isa/inst/misa_v/V.LW.OR/",
+ "/zh/isa/inst/misa_v/V.LW.XOR/": "/isa/inst/misa_v/V.LW.XOR/",
+ "/zh/isa/inst/misa_v/V.LW/": "/isa/inst/misa_v/V.LW/",
+ "/zh/isa/inst/misa_v/V.LWI.BRG/": "/isa/inst/misa_v/V.LWI.BRG/",
+ "/zh/isa/inst/misa_v/V.LWI.U/": "/isa/inst/misa_v/V.LWI.U/",
+ "/zh/isa/inst/misa_v/V.LWI.UBRG/": "/isa/inst/misa_v/V.LWI.UBRG/",
+ "/zh/isa/inst/misa_v/V.LWI/": "/isa/inst/misa_v/V.LWI/",
+ "/zh/isa/inst/misa_v/V.LWU.BRG/": "/isa/inst/misa_v/V.LWU.BRG/",
+ "/zh/isa/inst/misa_v/V.LWU/": "/isa/inst/misa_v/V.LWU/",
+ "/zh/isa/inst/misa_v/V.LWUI.BRG/": "/isa/inst/misa_v/V.LWUI.BRG/",
+ "/zh/isa/inst/misa_v/V.LWUI.U/": "/isa/inst/misa_v/V.LWUI.U/",
+ "/zh/isa/inst/misa_v/V.LWUI.UBRG/": "/isa/inst/misa_v/V.LWUI.UBRG/",
+ "/zh/isa/inst/misa_v/V.LWUI/": "/isa/inst/misa_v/V.LWUI/",
+ "/zh/isa/inst/misa_v/V.MADD/": "/isa/inst/misa_v/V.MADD/",
+ "/zh/isa/inst/misa_v/V.MAX/": "/isa/inst/misa_v/V.MAX/",
+ "/zh/isa/inst/misa_v/V.MIN/": "/isa/inst/misa_v/V.MIN/",
+ "/zh/isa/inst/misa_v/V.MOV/": "/isa/inst/misa_v/V.MOV/",
+ "/zh/isa/inst/misa_v/V.MUL/": "/isa/inst/misa_v/V.MUL/",
+ "/zh/isa/inst/misa_v/V.OR/": "/isa/inst/misa_v/V.OR/",
+ "/zh/isa/inst/misa_v/V.ORI/": "/isa/inst/misa_v/V.ORI/",
+ "/zh/isa/inst/misa_v/V.PSEL/": "/isa/inst/misa_v/V.PSEL/",
+ "/zh/isa/inst/misa_v/V.QPOP/": "/isa/inst/misa_v/V.QPOP/",
+ "/zh/isa/inst/misa_v/V.QPUSH/": "/isa/inst/misa_v/V.QPUSH/",
+ "/zh/isa/inst/misa_v/V.RDADD/": "/isa/inst/misa_v/V.RDADD/",
+ "/zh/isa/inst/misa_v/V.RDAND/": "/isa/inst/misa_v/V.RDAND/",
+ "/zh/isa/inst/misa_v/V.RDFADD/": "/isa/inst/misa_v/V.RDFADD/",
+ "/zh/isa/inst/misa_v/V.RDFMAX/": "/isa/inst/misa_v/V.RDFMAX/",
+ "/zh/isa/inst/misa_v/V.RDFMIN/": "/isa/inst/misa_v/V.RDFMIN/",
+ "/zh/isa/inst/misa_v/V.RDMAX/": "/isa/inst/misa_v/V.RDMAX/",
+ "/zh/isa/inst/misa_v/V.RDMIN/": "/isa/inst/misa_v/V.RDMIN/",
+ "/zh/isa/inst/misa_v/V.RDOR/": "/isa/inst/misa_v/V.RDOR/",
+ "/zh/isa/inst/misa_v/V.RDXOR/": "/isa/inst/misa_v/V.RDXOR/",
+ "/zh/isa/inst/misa_v/V.REM/": "/isa/inst/misa_v/V.REM/",
+ "/zh/isa/inst/misa_v/V.REV/": "/isa/inst/misa_v/V.REV/",
+ "/zh/isa/inst/misa_v/V.SB.BRG/": "/isa/inst/misa_v/V.SB.BRG/",
+ "/zh/isa/inst/misa_v/V.SB/": "/isa/inst/misa_v/V.SB/",
+ "/zh/isa/inst/misa_v/V.SBI.BRG/": "/isa/inst/misa_v/V.SBI.BRG/",
+ "/zh/isa/inst/misa_v/V.SBI/": "/isa/inst/misa_v/V.SBI/",
+ "/zh/isa/inst/misa_v/V.SD.ADD/": "/isa/inst/misa_v/V.SD.ADD/",
+ "/zh/isa/inst/misa_v/V.SD.AND/": "/isa/inst/misa_v/V.SD.AND/",
+ "/zh/isa/inst/misa_v/V.SD.BRG/": "/isa/inst/misa_v/V.SD.BRG/",
+ "/zh/isa/inst/misa_v/V.SD.MAX/": "/isa/inst/misa_v/V.SD.MAX/",
+ "/zh/isa/inst/misa_v/V.SD.MIN/": "/isa/inst/misa_v/V.SD.MIN/",
+ "/zh/isa/inst/misa_v/V.SD.OR/": "/isa/inst/misa_v/V.SD.OR/",
+ "/zh/isa/inst/misa_v/V.SD.U/": "/isa/inst/misa_v/V.SD.U/",
+ "/zh/isa/inst/misa_v/V.SD.UBRG/": "/isa/inst/misa_v/V.SD.UBRG/",
+ "/zh/isa/inst/misa_v/V.SD.XOR/": "/isa/inst/misa_v/V.SD.XOR/",
+ "/zh/isa/inst/misa_v/V.SD/": "/isa/inst/misa_v/V.SD/",
+ "/zh/isa/inst/misa_v/V.SDI.BRG/": "/isa/inst/misa_v/V.SDI.BRG/",
+ "/zh/isa/inst/misa_v/V.SDI.U/": "/isa/inst/misa_v/V.SDI.U/",
+ "/zh/isa/inst/misa_v/V.SDI.UBRG/": "/isa/inst/misa_v/V.SDI.UBRG/",
+ "/zh/isa/inst/misa_v/V.SDI/": "/isa/inst/misa_v/V.SDI/",
+ "/zh/isa/inst/misa_v/V.SH.BRG/": "/isa/inst/misa_v/V.SH.BRG/",
+ "/zh/isa/inst/misa_v/V.SH.U/": "/isa/inst/misa_v/V.SH.U/",
+ "/zh/isa/inst/misa_v/V.SH.UBRG/": "/isa/inst/misa_v/V.SH.UBRG/",
+ "/zh/isa/inst/misa_v/V.SH/": "/isa/inst/misa_v/V.SH/",
+ "/zh/isa/inst/misa_v/V.SHFL.BFLY/": "/isa/inst/misa_v/V.SHFL.BFLY/",
+ "/zh/isa/inst/misa_v/V.SHFL.DOWN/": "/isa/inst/misa_v/V.SHFL.DOWN/",
+ "/zh/isa/inst/misa_v/V.SHFL.IDX/": "/isa/inst/misa_v/V.SHFL.IDX/",
+ "/zh/isa/inst/misa_v/V.SHFL.UP/": "/isa/inst/misa_v/V.SHFL.UP/",
+ "/zh/isa/inst/misa_v/V.SHFLI.BFLY/": "/isa/inst/misa_v/V.SHFLI.BFLY/",
+ "/zh/isa/inst/misa_v/V.SHFLI.DOWN/": "/isa/inst/misa_v/V.SHFLI.DOWN/",
+ "/zh/isa/inst/misa_v/V.SHFLI.IDX/": "/isa/inst/misa_v/V.SHFLI.IDX/",
+ "/zh/isa/inst/misa_v/V.SHFLI.UP/": "/isa/inst/misa_v/V.SHFLI.UP/",
+ "/zh/isa/inst/misa_v/V.SHI.BRG/": "/isa/inst/misa_v/V.SHI.BRG/",
+ "/zh/isa/inst/misa_v/V.SHI.U/": "/isa/inst/misa_v/V.SHI.U/",
+ "/zh/isa/inst/misa_v/V.SHI.UBRG/": "/isa/inst/misa_v/V.SHI.UBRG/",
+ "/zh/isa/inst/misa_v/V.SHI/": "/isa/inst/misa_v/V.SHI/",
+ "/zh/isa/inst/misa_v/V.SLL/": "/isa/inst/misa_v/V.SLL/",
+ "/zh/isa/inst/misa_v/V.SLLI/": "/isa/inst/misa_v/V.SLLI/",
+ "/zh/isa/inst/misa_v/V.SRA/": "/isa/inst/misa_v/V.SRA/",
+ "/zh/isa/inst/misa_v/V.SRAI/": "/isa/inst/misa_v/V.SRAI/",
+ "/zh/isa/inst/misa_v/V.SRL/": "/isa/inst/misa_v/V.SRL/",
+ "/zh/isa/inst/misa_v/V.SRLI/": "/isa/inst/misa_v/V.SRLI/",
+ "/zh/isa/inst/misa_v/V.SUB/": "/isa/inst/misa_v/V.SUB/",
+ "/zh/isa/inst/misa_v/V.SUBI/": "/isa/inst/misa_v/V.SUBI/",
+ "/zh/isa/inst/misa_v/V.SW.ADD/": "/isa/inst/misa_v/V.SW.ADD/",
+ "/zh/isa/inst/misa_v/V.SW.AND/": "/isa/inst/misa_v/V.SW.AND/",
+ "/zh/isa/inst/misa_v/V.SW.BRG/": "/isa/inst/misa_v/V.SW.BRG/",
+ "/zh/isa/inst/misa_v/V.SW.MAX/": "/isa/inst/misa_v/V.SW.MAX/",
+ "/zh/isa/inst/misa_v/V.SW.MIN/": "/isa/inst/misa_v/V.SW.MIN/",
+ "/zh/isa/inst/misa_v/V.SW.OR/": "/isa/inst/misa_v/V.SW.OR/",
+ "/zh/isa/inst/misa_v/V.SW.U/": "/isa/inst/misa_v/V.SW.U/",
+ "/zh/isa/inst/misa_v/V.SW.UBRG/": "/isa/inst/misa_v/V.SW.UBRG/",
+ "/zh/isa/inst/misa_v/V.SW.XOR/": "/isa/inst/misa_v/V.SW.XOR/",
+ "/zh/isa/inst/misa_v/V.SW/": "/isa/inst/misa_v/V.SW/",
+ "/zh/isa/inst/misa_v/V.SWI.BRG/": "/isa/inst/misa_v/V.SWI.BRG/",
+ "/zh/isa/inst/misa_v/V.SWI.U/": "/isa/inst/misa_v/V.SWI.U/",
+ "/zh/isa/inst/misa_v/V.SWI.UBRG/": "/isa/inst/misa_v/V.SWI.UBRG/",
+ "/zh/isa/inst/misa_v/V.SWI/": "/isa/inst/misa_v/V.SWI/",
+ "/zh/isa/inst/misa_v/V.XOR/": "/isa/inst/misa_v/V.XOR/",
+ "/zh/isa/inst/misa_v/V.XORI/": "/isa/inst/misa_v/V.XORI/",
+ "/zh/isa/instructions/": "/isa/instructions/",
+ "/zh/isa/instructions/acrc/": "/isa/instructions/acrc/",
+ "/zh/isa/instructions/acre/": "/isa/instructions/acre/",
+ "/zh/isa/instructions/add/": "/isa/instructions/add/",
+ "/zh/isa/instructions/addi/": "/isa/instructions/addi/",
+ "/zh/isa/instructions/addiw/": "/isa/instructions/addiw/",
+ "/zh/isa/instructions/addtpc/": "/isa/instructions/addtpc/",
+ "/zh/isa/instructions/addw/": "/isa/instructions/addw/",
+ "/zh/isa/instructions/and/": "/isa/instructions/and/",
+ "/zh/isa/instructions/andi/": "/isa/instructions/andi/",
+ "/zh/isa/instructions/andiw/": "/isa/instructions/andiw/",
+ "/zh/isa/instructions/andw/": "/isa/instructions/andw/",
+ "/zh/isa/instructions/assert/": "/isa/instructions/assert/",
+ "/zh/isa/instructions/b_arg/": "/isa/instructions/b_arg/",
+ "/zh/isa/instructions/b_catr/": "/isa/instructions/b_catr/",
+ "/zh/isa/instructions/b_datr/": "/isa/instructions/b_datr/",
+ "/zh/isa/instructions/b_dim/": "/isa/instructions/b_dim/",
+ "/zh/isa/instructions/b_eq/": "/isa/instructions/b_eq/",
+ "/zh/isa/instructions/b_ge/": "/isa/instructions/b_ge/",
+ "/zh/isa/instructions/b_geu/": "/isa/instructions/b_geu/",
+ "/zh/isa/instructions/b_hint/": "/isa/instructions/b_hint/",
+ "/zh/isa/instructions/b_iod/": "/isa/instructions/b_iod/",
+ "/zh/isa/instructions/b_ior/": "/isa/instructions/b_ior/",
+ "/zh/isa/instructions/b_iot/": "/isa/instructions/b_iot/",
+ "/zh/isa/instructions/b_lt/": "/isa/instructions/b_lt/",
+ "/zh/isa/instructions/b_ltu/": "/isa/instructions/b_ltu/",
+ "/zh/isa/instructions/b_ne/": "/isa/instructions/b_ne/",
+ "/zh/isa/instructions/b_nz/": "/isa/instructions/b_nz/",
+ "/zh/isa/instructions/b_text/": "/isa/instructions/b_text/",
+ "/zh/isa/instructions/b_z/": "/isa/instructions/b_z/",
+ "/zh/isa/instructions/bc_iall/": "/isa/instructions/bc_iall/",
+ "/zh/isa/instructions/bc_iva/": "/isa/instructions/bc_iva/",
+ "/zh/isa/instructions/bcnt/": "/isa/instructions/bcnt/",
+ "/zh/isa/instructions/bic/": "/isa/instructions/bic/",
+ "/zh/isa/instructions/bis/": "/isa/instructions/bis/",
+ "/zh/isa/instructions/bse/": "/isa/instructions/bse/",
+ "/zh/isa/instructions/bstart/": "/isa/instructions/bstart/",
+ "/zh/isa/instructions/bstart_acccvt/": "/isa/instructions/bstart_acccvt/",
+ "/zh/isa/instructions/bstart_call/": "/isa/instructions/bstart_call/",
+ "/zh/isa/instructions/bstart_cube/": "/isa/instructions/bstart_cube/",
+ "/zh/isa/instructions/bstart_fixp/": "/isa/instructions/bstart_fixp/",
+ "/zh/isa/instructions/bstart_fp/": "/isa/instructions/bstart_fp/",
+ "/zh/isa/instructions/bstart_mpar/": "/isa/instructions/bstart_mpar/",
+ "/zh/isa/instructions/bstart_mseq/": "/isa/instructions/bstart_mseq/",
+ "/zh/isa/instructions/bstart_par/": "/isa/instructions/bstart_par/",
+ "/zh/isa/instructions/bstart_std/": "/isa/instructions/bstart_std/",
+ "/zh/isa/instructions/bstart_sys/": "/isa/instructions/bstart_sys/",
+ "/zh/isa/instructions/bstart_tepl/": "/isa/instructions/bstart_tepl/",
+ "/zh/isa/instructions/bstart_tload/": "/isa/instructions/bstart_tload/",
+ "/zh/isa/instructions/bstart_tma/": "/isa/instructions/bstart_tma/",
+ "/zh/isa/instructions/bstart_tmatmul/": "/isa/instructions/bstart_tmatmul/",
+ "/zh/isa/instructions/bstart_tmatmul_acc/": "/isa/instructions/bstart_tmatmul_acc/",
+ "/zh/isa/instructions/bstart_tmov/": "/isa/instructions/bstart_tmov/",
+ "/zh/isa/instructions/bstart_tstore/": "/isa/instructions/bstart_tstore/",
+ "/zh/isa/instructions/bstart_vpar/": "/isa/instructions/bstart_vpar/",
+ "/zh/isa/instructions/bstart_vseq/": "/isa/instructions/bstart_vseq/",
+ "/zh/isa/instructions/bstop/": "/isa/instructions/bstop/",
+ "/zh/isa/instructions/bwe/": "/isa/instructions/bwe/",
+ "/zh/isa/instructions/bwi/": "/isa/instructions/bwi/",
+ "/zh/isa/instructions/bwt/": "/isa/instructions/bwt/",
+ "/zh/isa/instructions/bxs/": "/isa/instructions/bxs/",
+ "/zh/isa/instructions/bxu/": "/isa/instructions/bxu/",
+ "/zh/isa/instructions/c_add/": "/isa/instructions/c_add/",
+ "/zh/isa/instructions/c_addi/": "/isa/instructions/c_addi/",
+ "/zh/isa/instructions/c_and/": "/isa/instructions/c_and/",
+ "/zh/isa/instructions/c_b_dim/": "/isa/instructions/c_b_dim/",
+ "/zh/isa/instructions/c_b_dimi/": "/isa/instructions/c_b_dimi/",
+ "/zh/isa/instructions/c_bstart/": "/isa/instructions/c_bstart/",
+ "/zh/isa/instructions/c_bstart_fp/": "/isa/instructions/c_bstart_fp/",
+ "/zh/isa/instructions/c_bstart_mpar/": "/isa/instructions/c_bstart_mpar/",
+ "/zh/isa/instructions/c_bstart_mseq/": "/isa/instructions/c_bstart_mseq/",
+ "/zh/isa/instructions/c_bstart_std/": "/isa/instructions/c_bstart_std/",
+ "/zh/isa/instructions/c_bstart_sys/": "/isa/instructions/c_bstart_sys/",
+ "/zh/isa/instructions/c_bstart_vpar/": "/isa/instructions/c_bstart_vpar/",
+ "/zh/isa/instructions/c_bstart_vseq/": "/isa/instructions/c_bstart_vseq/",
+ "/zh/isa/instructions/c_bstop/": "/isa/instructions/c_bstop/",
+ "/zh/isa/instructions/c_cmp_eqi/": "/isa/instructions/c_cmp_eqi/",
+ "/zh/isa/instructions/c_cmp_nei/": "/isa/instructions/c_cmp_nei/",
+ "/zh/isa/instructions/c_ebreak/": "/isa/instructions/c_ebreak/",
+ "/zh/isa/instructions/c_ldi/": "/isa/instructions/c_ldi/",
+ "/zh/isa/instructions/c_lwi/": "/isa/instructions/c_lwi/",
+ "/zh/isa/instructions/c_movi/": "/isa/instructions/c_movi/",
+ "/zh/isa/instructions/c_movr/": "/isa/instructions/c_movr/",
+ "/zh/isa/instructions/c_or/": "/isa/instructions/c_or/",
+ "/zh/isa/instructions/c_sdi/": "/isa/instructions/c_sdi/",
+ "/zh/isa/instructions/c_setc_eq/": "/isa/instructions/c_setc_eq/",
+ "/zh/isa/instructions/c_setc_ne/": "/isa/instructions/c_setc_ne/",
+ "/zh/isa/instructions/c_setc_tgt/": "/isa/instructions/c_setc_tgt/",
+ "/zh/isa/instructions/c_setret/": "/isa/instructions/c_setret/",
+ "/zh/isa/instructions/c_sext_b/": "/isa/instructions/c_sext_b/",
+ "/zh/isa/instructions/c_sext_h/": "/isa/instructions/c_sext_h/",
+ "/zh/isa/instructions/c_sext_w/": "/isa/instructions/c_sext_w/",
+ "/zh/isa/instructions/c_slli/": "/isa/instructions/c_slli/",
+ "/zh/isa/instructions/c_srli/": "/isa/instructions/c_srli/",
+ "/zh/isa/instructions/c_ssrget/": "/isa/instructions/c_ssrget/",
+ "/zh/isa/instructions/c_sub/": "/isa/instructions/c_sub/",
+ "/zh/isa/instructions/c_swi/": "/isa/instructions/c_swi/",
+ "/zh/isa/instructions/c_zext_b/": "/isa/instructions/c_zext_b/",
+ "/zh/isa/instructions/c_zext_h/": "/isa/instructions/c_zext_h/",
+ "/zh/isa/instructions/c_zext_w/": "/isa/instructions/c_zext_w/",
+ "/zh/isa/instructions/clz/": "/isa/instructions/clz/",
+ "/zh/isa/instructions/cmp_and/": "/isa/instructions/cmp_and/",
+ "/zh/isa/instructions/cmp_andi/": "/isa/instructions/cmp_andi/",
+ "/zh/isa/instructions/cmp_eq/": "/isa/instructions/cmp_eq/",
+ "/zh/isa/instructions/cmp_eqi/": "/isa/instructions/cmp_eqi/",
+ "/zh/isa/instructions/cmp_ge/": "/isa/instructions/cmp_ge/",
+ "/zh/isa/instructions/cmp_gei/": "/isa/instructions/cmp_gei/",
+ "/zh/isa/instructions/cmp_geu/": "/isa/instructions/cmp_geu/",
+ "/zh/isa/instructions/cmp_geui/": "/isa/instructions/cmp_geui/",
+ "/zh/isa/instructions/cmp_lt/": "/isa/instructions/cmp_lt/",
+ "/zh/isa/instructions/cmp_lti/": "/isa/instructions/cmp_lti/",
+ "/zh/isa/instructions/cmp_ltu/": "/isa/instructions/cmp_ltu/",
+ "/zh/isa/instructions/cmp_ltui/": "/isa/instructions/cmp_ltui/",
+ "/zh/isa/instructions/cmp_ne/": "/isa/instructions/cmp_ne/",
+ "/zh/isa/instructions/cmp_nei/": "/isa/instructions/cmp_nei/",
+ "/zh/isa/instructions/cmp_or/": "/isa/instructions/cmp_or/",
+ "/zh/isa/instructions/cmp_ori/": "/isa/instructions/cmp_ori/",
+ "/zh/isa/instructions/csel/": "/isa/instructions/csel/",
+ "/zh/isa/instructions/ctz/": "/isa/instructions/ctz/",
+ "/zh/isa/instructions/dc_cisw/": "/isa/instructions/dc_cisw/",
+ "/zh/isa/instructions/dc_civa/": "/isa/instructions/dc_civa/",
+ "/zh/isa/instructions/dc_csw/": "/isa/instructions/dc_csw/",
+ "/zh/isa/instructions/dc_cva/": "/isa/instructions/dc_cva/",
+ "/zh/isa/instructions/dc_iall/": "/isa/instructions/dc_iall/",
+ "/zh/isa/instructions/dc_isw/": "/isa/instructions/dc_isw/",
+ "/zh/isa/instructions/dc_iva/": "/isa/instructions/dc_iva/",
+ "/zh/isa/instructions/dc_zva/": "/isa/instructions/dc_zva/",
+ "/zh/isa/instructions/div/": "/isa/instructions/div/",
+ "/zh/isa/instructions/divu/": "/isa/instructions/divu/",
+ "/zh/isa/instructions/divuw/": "/isa/instructions/divuw/",
+ "/zh/isa/instructions/divw/": "/isa/instructions/divw/",
+ "/zh/isa/instructions/ebreak/": "/isa/instructions/ebreak/",
+ "/zh/isa/instructions/ercov/": "/isa/instructions/ercov/",
+ "/zh/isa/instructions/esave/": "/isa/instructions/esave/",
+ "/zh/isa/instructions/fabs/": "/isa/instructions/fabs/",
+ "/zh/isa/instructions/fadd/": "/isa/instructions/fadd/",
+ "/zh/isa/instructions/fcvt/": "/isa/instructions/fcvt/",
+ "/zh/isa/instructions/fcvta/": "/isa/instructions/fcvta/",
+ "/zh/isa/instructions/fcvtm/": "/isa/instructions/fcvtm/",
+ "/zh/isa/instructions/fcvtn/": "/isa/instructions/fcvtn/",
+ "/zh/isa/instructions/fcvtp/": "/isa/instructions/fcvtp/",
+ "/zh/isa/instructions/fcvtz/": "/isa/instructions/fcvtz/",
+ "/zh/isa/instructions/fdiv/": "/isa/instructions/fdiv/",
+ "/zh/isa/instructions/fence_d/": "/isa/instructions/fence_d/",
+ "/zh/isa/instructions/fence_i/": "/isa/instructions/fence_i/",
+ "/zh/isa/instructions/fentry/": "/isa/instructions/fentry/",
+ "/zh/isa/instructions/feq/": "/isa/instructions/feq/",
+ "/zh/isa/instructions/feqs/": "/isa/instructions/feqs/",
+ "/zh/isa/instructions/fexit/": "/isa/instructions/fexit/",
+ "/zh/isa/instructions/fexp/": "/isa/instructions/fexp/",
+ "/zh/isa/instructions/fge/": "/isa/instructions/fge/",
+ "/zh/isa/instructions/fges/": "/isa/instructions/fges/",
+ "/zh/isa/instructions/flt/": "/isa/instructions/flt/",
+ "/zh/isa/instructions/flts/": "/isa/instructions/flts/",
+ "/zh/isa/instructions/fmadd/": "/isa/instructions/fmadd/",
+ "/zh/isa/instructions/fmax/": "/isa/instructions/fmax/",
+ "/zh/isa/instructions/fmin/": "/isa/instructions/fmin/",
+ "/zh/isa/instructions/fmsub/": "/isa/instructions/fmsub/",
+ "/zh/isa/instructions/fmul/": "/isa/instructions/fmul/",
+ "/zh/isa/instructions/fne/": "/isa/instructions/fne/",
+ "/zh/isa/instructions/fnes/": "/isa/instructions/fnes/",
+ "/zh/isa/instructions/fnmadd/": "/isa/instructions/fnmadd/",
+ "/zh/isa/instructions/fnmsub/": "/isa/instructions/fnmsub/",
+ "/zh/isa/instructions/frecip/": "/isa/instructions/frecip/",
+ "/zh/isa/instructions/fret_ra/": "/isa/instructions/fret_ra/",
+ "/zh/isa/instructions/fret_stk/": "/isa/instructions/fret_stk/",
+ "/zh/isa/instructions/fsqrt/": "/isa/instructions/fsqrt/",
+ "/zh/isa/instructions/fsub/": "/isa/instructions/fsub/",
+ "/zh/isa/instructions/hl_addi/": "/isa/instructions/hl_addi/",
+ "/zh/isa/instructions/hl_addiw/": "/isa/instructions/hl_addiw/",
+ "/zh/isa/instructions/hl_addtpc/": "/isa/instructions/hl_addtpc/",
+ "/zh/isa/instructions/hl_andi/": "/isa/instructions/hl_andi/",
+ "/zh/isa/instructions/hl_andiw/": "/isa/instructions/hl_andiw/",
+ "/zh/isa/instructions/hl_bfi/": "/isa/instructions/hl_bfi/",
+ "/zh/isa/instructions/hl_bstart_call/": "/isa/instructions/hl_bstart_call/",
+ "/zh/isa/instructions/hl_bstart_fp/": "/isa/instructions/hl_bstart_fp/",
+ "/zh/isa/instructions/hl_bstart_std/": "/isa/instructions/hl_bstart_std/",
+ "/zh/isa/instructions/hl_bstart_sys/": "/isa/instructions/hl_bstart_sys/",
+ "/zh/isa/instructions/hl_casb/": "/isa/instructions/hl_casb/",
+ "/zh/isa/instructions/hl_casd/": "/isa/instructions/hl_casd/",
+ "/zh/isa/instructions/hl_cash/": "/isa/instructions/hl_cash/",
+ "/zh/isa/instructions/hl_casw/": "/isa/instructions/hl_casw/",
+ "/zh/isa/instructions/hl_ccat/": "/isa/instructions/hl_ccat/",
+ "/zh/isa/instructions/hl_ccatw/": "/isa/instructions/hl_ccatw/",
+ "/zh/isa/instructions/hl_cmp_andi/": "/isa/instructions/hl_cmp_andi/",
+ "/zh/isa/instructions/hl_cmp_eqi/": "/isa/instructions/hl_cmp_eqi/",
+ "/zh/isa/instructions/hl_cmp_gei/": "/isa/instructions/hl_cmp_gei/",
+ "/zh/isa/instructions/hl_cmp_geui/": "/isa/instructions/hl_cmp_geui/",
+ "/zh/isa/instructions/hl_cmp_lti/": "/isa/instructions/hl_cmp_lti/",
+ "/zh/isa/instructions/hl_cmp_ltui/": "/isa/instructions/hl_cmp_ltui/",
+ "/zh/isa/instructions/hl_cmp_nei/": "/isa/instructions/hl_cmp_nei/",
+ "/zh/isa/instructions/hl_cmp_ori/": "/isa/instructions/hl_cmp_ori/",
+ "/zh/isa/instructions/hl_div/": "/isa/instructions/hl_div/",
+ "/zh/isa/instructions/hl_divu/": "/isa/instructions/hl_divu/",
+ "/zh/isa/instructions/hl_divuw/": "/isa/instructions/hl_divuw/",
+ "/zh/isa/instructions/hl_divw/": "/isa/instructions/hl_divw/",
+ "/zh/isa/instructions/hl_lb_pcr/": "/isa/instructions/hl_lb_pcr/",
+ "/zh/isa/instructions/hl_lb_po/": "/isa/instructions/hl_lb_po/",
+ "/zh/isa/instructions/hl_lb_pr/": "/isa/instructions/hl_lb_pr/",
+ "/zh/isa/instructions/hl_lbi/": "/isa/instructions/hl_lbi/",
+ "/zh/isa/instructions/hl_lbi_po/": "/isa/instructions/hl_lbi_po/",
+ "/zh/isa/instructions/hl_lbi_pr/": "/isa/instructions/hl_lbi_pr/",
+ "/zh/isa/instructions/hl_lbip/": "/isa/instructions/hl_lbip/",
+ "/zh/isa/instructions/hl_lbp/": "/isa/instructions/hl_lbp/",
+ "/zh/isa/instructions/hl_lbu_pcr/": "/isa/instructions/hl_lbu_pcr/",
+ "/zh/isa/instructions/hl_lbu_po/": "/isa/instructions/hl_lbu_po/",
+ "/zh/isa/instructions/hl_lbu_pr/": "/isa/instructions/hl_lbu_pr/",
+ "/zh/isa/instructions/hl_lbui/": "/isa/instructions/hl_lbui/",
+ "/zh/isa/instructions/hl_lbui_po/": "/isa/instructions/hl_lbui_po/",
+ "/zh/isa/instructions/hl_lbui_pr/": "/isa/instructions/hl_lbui_pr/",
+ "/zh/isa/instructions/hl_lbuip/": "/isa/instructions/hl_lbuip/",
+ "/zh/isa/instructions/hl_lbup/": "/isa/instructions/hl_lbup/",
+ "/zh/isa/instructions/hl_ld_pcr/": "/isa/instructions/hl_ld_pcr/",
+ "/zh/isa/instructions/hl_ld_po/": "/isa/instructions/hl_ld_po/",
+ "/zh/isa/instructions/hl_ld_pr/": "/isa/instructions/hl_ld_pr/",
+ "/zh/isa/instructions/hl_ldi/": "/isa/instructions/hl_ldi/",
+ "/zh/isa/instructions/hl_ldi_po/": "/isa/instructions/hl_ldi_po/",
+ "/zh/isa/instructions/hl_ldi_pr/": "/isa/instructions/hl_ldi_pr/",
+ "/zh/isa/instructions/hl_ldi_u/": "/isa/instructions/hl_ldi_u/",
+ "/zh/isa/instructions/hl_ldi_upo/": "/isa/instructions/hl_ldi_upo/",
+ "/zh/isa/instructions/hl_ldi_upr/": "/isa/instructions/hl_ldi_upr/",
+ "/zh/isa/instructions/hl_ldip/": "/isa/instructions/hl_ldip/",
+ "/zh/isa/instructions/hl_ldip_u/": "/isa/instructions/hl_ldip_u/",
+ "/zh/isa/instructions/hl_ldp/": "/isa/instructions/hl_ldp/",
+ "/zh/isa/instructions/hl_lh_pcr/": "/isa/instructions/hl_lh_pcr/",
+ "/zh/isa/instructions/hl_lh_po/": "/isa/instructions/hl_lh_po/",
+ "/zh/isa/instructions/hl_lh_pr/": "/isa/instructions/hl_lh_pr/",
+ "/zh/isa/instructions/hl_lhi/": "/isa/instructions/hl_lhi/",
+ "/zh/isa/instructions/hl_lhi_po/": "/isa/instructions/hl_lhi_po/",
+ "/zh/isa/instructions/hl_lhi_pr/": "/isa/instructions/hl_lhi_pr/",
+ "/zh/isa/instructions/hl_lhi_u/": "/isa/instructions/hl_lhi_u/",
+ "/zh/isa/instructions/hl_lhi_upo/": "/isa/instructions/hl_lhi_upo/",
+ "/zh/isa/instructions/hl_lhi_upr/": "/isa/instructions/hl_lhi_upr/",
+ "/zh/isa/instructions/hl_lhip/": "/isa/instructions/hl_lhip/",
+ "/zh/isa/instructions/hl_lhip_u/": "/isa/instructions/hl_lhip_u/",
+ "/zh/isa/instructions/hl_lhp/": "/isa/instructions/hl_lhp/",
+ "/zh/isa/instructions/hl_lhu_pcr/": "/isa/instructions/hl_lhu_pcr/",
+ "/zh/isa/instructions/hl_lhu_po/": "/isa/instructions/hl_lhu_po/",
+ "/zh/isa/instructions/hl_lhu_pr/": "/isa/instructions/hl_lhu_pr/",
+ "/zh/isa/instructions/hl_lhui/": "/isa/instructions/hl_lhui/",
+ "/zh/isa/instructions/hl_lhui_po/": "/isa/instructions/hl_lhui_po/",
+ "/zh/isa/instructions/hl_lhui_pr/": "/isa/instructions/hl_lhui_pr/",
+ "/zh/isa/instructions/hl_lhui_u/": "/isa/instructions/hl_lhui_u/",
+ "/zh/isa/instructions/hl_lhui_upo/": "/isa/instructions/hl_lhui_upo/",
+ "/zh/isa/instructions/hl_lhui_upr/": "/isa/instructions/hl_lhui_upr/",
+ "/zh/isa/instructions/hl_lhuip/": "/isa/instructions/hl_lhuip/",
+ "/zh/isa/instructions/hl_lhuip_u/": "/isa/instructions/hl_lhuip_u/",
+ "/zh/isa/instructions/hl_lhup/": "/isa/instructions/hl_lhup/",
+ "/zh/isa/instructions/hl_lis/": "/isa/instructions/hl_lis/",
+ "/zh/isa/instructions/hl_liu/": "/isa/instructions/hl_liu/",
+ "/zh/isa/instructions/hl_lui/": "/isa/instructions/hl_lui/",
+ "/zh/isa/instructions/hl_lw_pcr/": "/isa/instructions/hl_lw_pcr/",
+ "/zh/isa/instructions/hl_lw_po/": "/isa/instructions/hl_lw_po/",
+ "/zh/isa/instructions/hl_lw_pr/": "/isa/instructions/hl_lw_pr/",
+ "/zh/isa/instructions/hl_lwi/": "/isa/instructions/hl_lwi/",
+ "/zh/isa/instructions/hl_lwi_po/": "/isa/instructions/hl_lwi_po/",
+ "/zh/isa/instructions/hl_lwi_pr/": "/isa/instructions/hl_lwi_pr/",
+ "/zh/isa/instructions/hl_lwi_u/": "/isa/instructions/hl_lwi_u/",
+ "/zh/isa/instructions/hl_lwi_upo/": "/isa/instructions/hl_lwi_upo/",
+ "/zh/isa/instructions/hl_lwi_upr/": "/isa/instructions/hl_lwi_upr/",
+ "/zh/isa/instructions/hl_lwip/": "/isa/instructions/hl_lwip/",
+ "/zh/isa/instructions/hl_lwip_u/": "/isa/instructions/hl_lwip_u/",
+ "/zh/isa/instructions/hl_lwp/": "/isa/instructions/hl_lwp/",
+ "/zh/isa/instructions/hl_lwu_pcr/": "/isa/instructions/hl_lwu_pcr/",
+ "/zh/isa/instructions/hl_lwu_po/": "/isa/instructions/hl_lwu_po/",
+ "/zh/isa/instructions/hl_lwu_pr/": "/isa/instructions/hl_lwu_pr/",
+ "/zh/isa/instructions/hl_lwui/": "/isa/instructions/hl_lwui/",
+ "/zh/isa/instructions/hl_lwui_po/": "/isa/instructions/hl_lwui_po/",
+ "/zh/isa/instructions/hl_lwui_pr/": "/isa/instructions/hl_lwui_pr/",
+ "/zh/isa/instructions/hl_lwui_u/": "/isa/instructions/hl_lwui_u/",
+ "/zh/isa/instructions/hl_lwui_upo/": "/isa/instructions/hl_lwui_upo/",
+ "/zh/isa/instructions/hl_lwui_upr/": "/isa/instructions/hl_lwui_upr/",
+ "/zh/isa/instructions/hl_lwuip/": "/isa/instructions/hl_lwuip/",
+ "/zh/isa/instructions/hl_lwuip_u/": "/isa/instructions/hl_lwuip_u/",
+ "/zh/isa/instructions/hl_lwup/": "/isa/instructions/hl_lwup/",
+ "/zh/isa/instructions/hl_madd/": "/isa/instructions/hl_madd/",
+ "/zh/isa/instructions/hl_maddw/": "/isa/instructions/hl_maddw/",
+ "/zh/isa/instructions/hl_miadd/": "/isa/instructions/hl_miadd/",
+ "/zh/isa/instructions/hl_misub/": "/isa/instructions/hl_misub/",
+ "/zh/isa/instructions/hl_mul/": "/isa/instructions/hl_mul/",
+ "/zh/isa/instructions/hl_mulu/": "/isa/instructions/hl_mulu/",
+ "/zh/isa/instructions/hl_ori/": "/isa/instructions/hl_ori/",
+ "/zh/isa/instructions/hl_oriw/": "/isa/instructions/hl_oriw/",
+ "/zh/isa/instructions/hl_prf/": "/isa/instructions/hl_prf/",
+ "/zh/isa/instructions/hl_prf_a/": "/isa/instructions/hl_prf_a/",
+ "/zh/isa/instructions/hl_prfi_u/": "/isa/instructions/hl_prfi_u/",
+ "/zh/isa/instructions/hl_prfi_ua/": "/isa/instructions/hl_prfi_ua/",
+ "/zh/isa/instructions/hl_qmt/": "/isa/instructions/hl_qmt/",
+ "/zh/isa/instructions/hl_qpop/": "/isa/instructions/hl_qpop/",
+ "/zh/isa/instructions/hl_qpush/": "/isa/instructions/hl_qpush/",
+ "/zh/isa/instructions/hl_rem/": "/isa/instructions/hl_rem/",
+ "/zh/isa/instructions/hl_remu/": "/isa/instructions/hl_remu/",
+ "/zh/isa/instructions/hl_remuw/": "/isa/instructions/hl_remuw/",
+ "/zh/isa/instructions/hl_remw/": "/isa/instructions/hl_remw/",
+ "/zh/isa/instructions/hl_sb_pcr/": "/isa/instructions/hl_sb_pcr/",
+ "/zh/isa/instructions/hl_sb_po/": "/isa/instructions/hl_sb_po/",
+ "/zh/isa/instructions/hl_sb_pr/": "/isa/instructions/hl_sb_pr/",
+ "/zh/isa/instructions/hl_sbi/": "/isa/instructions/hl_sbi/",
+ "/zh/isa/instructions/hl_sbi_po/": "/isa/instructions/hl_sbi_po/",
+ "/zh/isa/instructions/hl_sbi_pr/": "/isa/instructions/hl_sbi_pr/",
+ "/zh/isa/instructions/hl_sbip/": "/isa/instructions/hl_sbip/",
+ "/zh/isa/instructions/hl_sbp/": "/isa/instructions/hl_sbp/",
+ "/zh/isa/instructions/hl_sd_pcr/": "/isa/instructions/hl_sd_pcr/",
+ "/zh/isa/instructions/hl_sd_po/": "/isa/instructions/hl_sd_po/",
+ "/zh/isa/instructions/hl_sd_pr/": "/isa/instructions/hl_sd_pr/",
+ "/zh/isa/instructions/hl_sd_upo/": "/isa/instructions/hl_sd_upo/",
+ "/zh/isa/instructions/hl_sd_upr/": "/isa/instructions/hl_sd_upr/",
+ "/zh/isa/instructions/hl_sdi/": "/isa/instructions/hl_sdi/",
+ "/zh/isa/instructions/hl_sdi_po/": "/isa/instructions/hl_sdi_po/",
+ "/zh/isa/instructions/hl_sdi_pr/": "/isa/instructions/hl_sdi_pr/",
+ "/zh/isa/instructions/hl_sdi_u/": "/isa/instructions/hl_sdi_u/",
+ "/zh/isa/instructions/hl_sdi_upo/": "/isa/instructions/hl_sdi_upo/",
+ "/zh/isa/instructions/hl_sdi_upr/": "/isa/instructions/hl_sdi_upr/",
+ "/zh/isa/instructions/hl_sdip/": "/isa/instructions/hl_sdip/",
+ "/zh/isa/instructions/hl_sdip_u/": "/isa/instructions/hl_sdip_u/",
+ "/zh/isa/instructions/hl_sdp/": "/isa/instructions/hl_sdp/",
+ "/zh/isa/instructions/hl_sdp_u/": "/isa/instructions/hl_sdp_u/",
+ "/zh/isa/instructions/hl_setc_andi/": "/isa/instructions/hl_setc_andi/",
+ "/zh/isa/instructions/hl_setc_eqi/": "/isa/instructions/hl_setc_eqi/",
+ "/zh/isa/instructions/hl_setc_gei/": "/isa/instructions/hl_setc_gei/",
+ "/zh/isa/instructions/hl_setc_geui/": "/isa/instructions/hl_setc_geui/",
+ "/zh/isa/instructions/hl_setc_lti/": "/isa/instructions/hl_setc_lti/",
+ "/zh/isa/instructions/hl_setc_ltui/": "/isa/instructions/hl_setc_ltui/",
+ "/zh/isa/instructions/hl_setc_nei/": "/isa/instructions/hl_setc_nei/",
+ "/zh/isa/instructions/hl_setc_ori/": "/isa/instructions/hl_setc_ori/",
+ "/zh/isa/instructions/hl_setret/": "/isa/instructions/hl_setret/",
+ "/zh/isa/instructions/hl_sh_pcr/": "/isa/instructions/hl_sh_pcr/",
+ "/zh/isa/instructions/hl_sh_po/": "/isa/instructions/hl_sh_po/",
+ "/zh/isa/instructions/hl_sh_pr/": "/isa/instructions/hl_sh_pr/",
+ "/zh/isa/instructions/hl_sh_upo/": "/isa/instructions/hl_sh_upo/",
+ "/zh/isa/instructions/hl_sh_upr/": "/isa/instructions/hl_sh_upr/",
+ "/zh/isa/instructions/hl_shi/": "/isa/instructions/hl_shi/",
+ "/zh/isa/instructions/hl_shi_po/": "/isa/instructions/hl_shi_po/",
+ "/zh/isa/instructions/hl_shi_pr/": "/isa/instructions/hl_shi_pr/",
+ "/zh/isa/instructions/hl_shi_u/": "/isa/instructions/hl_shi_u/",
+ "/zh/isa/instructions/hl_shi_upo/": "/isa/instructions/hl_shi_upo/",
+ "/zh/isa/instructions/hl_shi_upr/": "/isa/instructions/hl_shi_upr/",
+ "/zh/isa/instructions/hl_ship/": "/isa/instructions/hl_ship/",
+ "/zh/isa/instructions/hl_ship_u/": "/isa/instructions/hl_ship_u/",
+ "/zh/isa/instructions/hl_shp/": "/isa/instructions/hl_shp/",
+ "/zh/isa/instructions/hl_shp_u/": "/isa/instructions/hl_shp_u/",
+ "/zh/isa/instructions/hl_ssrget/": "/isa/instructions/hl_ssrget/",
+ "/zh/isa/instructions/hl_ssrset/": "/isa/instructions/hl_ssrset/",
+ "/zh/isa/instructions/hl_subi/": "/isa/instructions/hl_subi/",
+ "/zh/isa/instructions/hl_subiw/": "/isa/instructions/hl_subiw/",
+ "/zh/isa/instructions/hl_sw_pcr/": "/isa/instructions/hl_sw_pcr/",
+ "/zh/isa/instructions/hl_sw_po/": "/isa/instructions/hl_sw_po/",
+ "/zh/isa/instructions/hl_sw_pr/": "/isa/instructions/hl_sw_pr/",
+ "/zh/isa/instructions/hl_sw_upo/": "/isa/instructions/hl_sw_upo/",
+ "/zh/isa/instructions/hl_sw_upr/": "/isa/instructions/hl_sw_upr/",
+ "/zh/isa/instructions/hl_swi/": "/isa/instructions/hl_swi/",
+ "/zh/isa/instructions/hl_swi_po/": "/isa/instructions/hl_swi_po/",
+ "/zh/isa/instructions/hl_swi_pr/": "/isa/instructions/hl_swi_pr/",
+ "/zh/isa/instructions/hl_swi_u/": "/isa/instructions/hl_swi_u/",
+ "/zh/isa/instructions/hl_swi_upo/": "/isa/instructions/hl_swi_upo/",
+ "/zh/isa/instructions/hl_swi_upr/": "/isa/instructions/hl_swi_upr/",
+ "/zh/isa/instructions/hl_swip/": "/isa/instructions/hl_swip/",
+ "/zh/isa/instructions/hl_swip_u/": "/isa/instructions/hl_swip_u/",
+ "/zh/isa/instructions/hl_swp/": "/isa/instructions/hl_swp/",
+ "/zh/isa/instructions/hl_swp_u/": "/isa/instructions/hl_swp_u/",
+ "/zh/isa/instructions/hl_xori/": "/isa/instructions/hl_xori/",
+ "/zh/isa/instructions/hl_xoriw/": "/isa/instructions/hl_xoriw/",
+ "/zh/isa/instructions/ic_iall/": "/isa/instructions/ic_iall/",
+ "/zh/isa/instructions/ic_iva/": "/isa/instructions/ic_iva/",
+ "/zh/isa/instructions/j/": "/isa/instructions/j/",
+ "/zh/isa/instructions/jr/": "/isa/instructions/jr/",
+ "/zh/isa/instructions/lb/": "/isa/instructions/lb/",
+ "/zh/isa/instructions/lb_pcr/": "/isa/instructions/lb_pcr/",
+ "/zh/isa/instructions/lbi/": "/isa/instructions/lbi/",
+ "/zh/isa/instructions/lbu/": "/isa/instructions/lbu/",
+ "/zh/isa/instructions/lbu_pcr/": "/isa/instructions/lbu_pcr/",
+ "/zh/isa/instructions/lbui/": "/isa/instructions/lbui/",
+ "/zh/isa/instructions/ld/": "/isa/instructions/ld/",
+ "/zh/isa/instructions/ld_add/": "/isa/instructions/ld_add/",
+ "/zh/isa/instructions/ld_and/": "/isa/instructions/ld_and/",
+ "/zh/isa/instructions/ld_or/": "/isa/instructions/ld_or/",
+ "/zh/isa/instructions/ld_pcr/": "/isa/instructions/ld_pcr/",
+ "/zh/isa/instructions/ld_smax/": "/isa/instructions/ld_smax/",
+ "/zh/isa/instructions/ld_smin/": "/isa/instructions/ld_smin/",
+ "/zh/isa/instructions/ld_umax/": "/isa/instructions/ld_umax/",
+ "/zh/isa/instructions/ld_umin/": "/isa/instructions/ld_umin/",
+ "/zh/isa/instructions/ld_xor/": "/isa/instructions/ld_xor/",
+ "/zh/isa/instructions/ldi/": "/isa/instructions/ldi/",
+ "/zh/isa/instructions/ldi_u/": "/isa/instructions/ldi_u/",
+ "/zh/isa/instructions/lh/": "/isa/instructions/lh/",
+ "/zh/isa/instructions/lh_pcr/": "/isa/instructions/lh_pcr/",
+ "/zh/isa/instructions/lhi/": "/isa/instructions/lhi/",
+ "/zh/isa/instructions/lhi_u/": "/isa/instructions/lhi_u/",
+ "/zh/isa/instructions/lhu/": "/isa/instructions/lhu/",
+ "/zh/isa/instructions/lhu_pcr/": "/isa/instructions/lhu_pcr/",
+ "/zh/isa/instructions/lhui/": "/isa/instructions/lhui/",
+ "/zh/isa/instructions/lhui_u/": "/isa/instructions/lhui_u/",
+ "/zh/isa/instructions/lr_b/": "/isa/instructions/lr_b/",
+ "/zh/isa/instructions/lr_d/": "/isa/instructions/lr_d/",
+ "/zh/isa/instructions/lr_h/": "/isa/instructions/lr_h/",
+ "/zh/isa/instructions/lr_w/": "/isa/instructions/lr_w/",
+ "/zh/isa/instructions/lsrget/": "/isa/instructions/lsrget/",
+ "/zh/isa/instructions/lui/": "/isa/instructions/lui/",
+ "/zh/isa/instructions/lw/": "/isa/instructions/lw/",
+ "/zh/isa/instructions/lw_add/": "/isa/instructions/lw_add/",
+ "/zh/isa/instructions/lw_and/": "/isa/instructions/lw_and/",
+ "/zh/isa/instructions/lw_or/": "/isa/instructions/lw_or/",
+ "/zh/isa/instructions/lw_pcr/": "/isa/instructions/lw_pcr/",
+ "/zh/isa/instructions/lw_smax/": "/isa/instructions/lw_smax/",
+ "/zh/isa/instructions/lw_smin/": "/isa/instructions/lw_smin/",
+ "/zh/isa/instructions/lw_umax/": "/isa/instructions/lw_umax/",
+ "/zh/isa/instructions/lw_umin/": "/isa/instructions/lw_umin/",
+ "/zh/isa/instructions/lw_xor/": "/isa/instructions/lw_xor/",
+ "/zh/isa/instructions/lwi/": "/isa/instructions/lwi/",
+ "/zh/isa/instructions/lwi_u/": "/isa/instructions/lwi_u/",
+ "/zh/isa/instructions/lwu/": "/isa/instructions/lwu/",
+ "/zh/isa/instructions/lwu_pcr/": "/isa/instructions/lwu_pcr/",
+ "/zh/isa/instructions/lwui/": "/isa/instructions/lwui/",
+ "/zh/isa/instructions/lwui_u/": "/isa/instructions/lwui_u/",
+ "/zh/isa/instructions/madd/": "/isa/instructions/madd/",
+ "/zh/isa/instructions/maddw/": "/isa/instructions/maddw/",
+ "/zh/isa/instructions/max/": "/isa/instructions/max/",
+ "/zh/isa/instructions/maxu/": "/isa/instructions/maxu/",
+ "/zh/isa/instructions/mcopy/": "/isa/instructions/mcopy/",
+ "/zh/isa/instructions/min/": "/isa/instructions/min/",
+ "/zh/isa/instructions/minu/": "/isa/instructions/minu/",
+ "/zh/isa/instructions/mset/": "/isa/instructions/mset/",
+ "/zh/isa/instructions/mul/": "/isa/instructions/mul/",
+ "/zh/isa/instructions/mulu/": "/isa/instructions/mulu/",
+ "/zh/isa/instructions/muluw/": "/isa/instructions/muluw/",
+ "/zh/isa/instructions/mulw/": "/isa/instructions/mulw/",
+ "/zh/isa/instructions/or/": "/isa/instructions/or/",
+ "/zh/isa/instructions/ori/": "/isa/instructions/ori/",
+ "/zh/isa/instructions/oriw/": "/isa/instructions/oriw/",
+ "/zh/isa/instructions/orw/": "/isa/instructions/orw/",
+ "/zh/isa/instructions/prf/": "/isa/instructions/prf/",
+ "/zh/isa/instructions/prfi_u/": "/isa/instructions/prfi_u/",
+ "/zh/isa/instructions/rem/": "/isa/instructions/rem/",
+ "/zh/isa/instructions/remu/": "/isa/instructions/remu/",
+ "/zh/isa/instructions/remuw/": "/isa/instructions/remuw/",
+ "/zh/isa/instructions/remw/": "/isa/instructions/remw/",
+ "/zh/isa/instructions/rev/": "/isa/instructions/rev/",
+ "/zh/isa/instructions/sb/": "/isa/instructions/sb/",
+ "/zh/isa/instructions/sb_pcr/": "/isa/instructions/sb_pcr/",
+ "/zh/isa/instructions/sbi/": "/isa/instructions/sbi/",
+ "/zh/isa/instructions/sc_b/": "/isa/instructions/sc_b/",
+ "/zh/isa/instructions/sc_d/": "/isa/instructions/sc_d/",
+ "/zh/isa/instructions/sc_h/": "/isa/instructions/sc_h/",
+ "/zh/isa/instructions/sc_w/": "/isa/instructions/sc_w/",
+ "/zh/isa/instructions/scvtf/": "/isa/instructions/scvtf/",
+ "/zh/isa/instructions/sd/": "/isa/instructions/sd/",
+ "/zh/isa/instructions/sd_add/": "/isa/instructions/sd_add/",
+ "/zh/isa/instructions/sd_and/": "/isa/instructions/sd_and/",
+ "/zh/isa/instructions/sd_or/": "/isa/instructions/sd_or/",
+ "/zh/isa/instructions/sd_pcr/": "/isa/instructions/sd_pcr/",
+ "/zh/isa/instructions/sd_smax/": "/isa/instructions/sd_smax/",
+ "/zh/isa/instructions/sd_smin/": "/isa/instructions/sd_smin/",
+ "/zh/isa/instructions/sd_u/": "/isa/instructions/sd_u/",
+ "/zh/isa/instructions/sd_umax/": "/isa/instructions/sd_umax/",
+ "/zh/isa/instructions/sd_umin/": "/isa/instructions/sd_umin/",
+ "/zh/isa/instructions/sd_xor/": "/isa/instructions/sd_xor/",
+ "/zh/isa/instructions/sdi/": "/isa/instructions/sdi/",
+ "/zh/isa/instructions/sdi_u/": "/isa/instructions/sdi_u/",
+ "/zh/isa/instructions/setc_and/": "/isa/instructions/setc_and/",
+ "/zh/isa/instructions/setc_andi/": "/isa/instructions/setc_andi/",
+ "/zh/isa/instructions/setc_eq/": "/isa/instructions/setc_eq/",
+ "/zh/isa/instructions/setc_eqi/": "/isa/instructions/setc_eqi/",
+ "/zh/isa/instructions/setc_ge/": "/isa/instructions/setc_ge/",
+ "/zh/isa/instructions/setc_gei/": "/isa/instructions/setc_gei/",
+ "/zh/isa/instructions/setc_geu/": "/isa/instructions/setc_geu/",
+ "/zh/isa/instructions/setc_geui/": "/isa/instructions/setc_geui/",
+ "/zh/isa/instructions/setc_lt/": "/isa/instructions/setc_lt/",
+ "/zh/isa/instructions/setc_lti/": "/isa/instructions/setc_lti/",
+ "/zh/isa/instructions/setc_ltu/": "/isa/instructions/setc_ltu/",
+ "/zh/isa/instructions/setc_ltui/": "/isa/instructions/setc_ltui/",
+ "/zh/isa/instructions/setc_ne/": "/isa/instructions/setc_ne/",
+ "/zh/isa/instructions/setc_nei/": "/isa/instructions/setc_nei/",
+ "/zh/isa/instructions/setc_or/": "/isa/instructions/setc_or/",
+ "/zh/isa/instructions/setc_ori/": "/isa/instructions/setc_ori/",
+ "/zh/isa/instructions/setc_tgt/": "/isa/instructions/setc_tgt/",
+ "/zh/isa/instructions/setret/": "/isa/instructions/setret/",
+ "/zh/isa/instructions/sh/": "/isa/instructions/sh/",
+ "/zh/isa/instructions/sh_pcr/": "/isa/instructions/sh_pcr/",
+ "/zh/isa/instructions/sh_u/": "/isa/instructions/sh_u/",
+ "/zh/isa/instructions/shi/": "/isa/instructions/shi/",
+ "/zh/isa/instructions/shi_u/": "/isa/instructions/shi_u/",
+ "/zh/isa/instructions/sll/": "/isa/instructions/sll/",
+ "/zh/isa/instructions/slli/": "/isa/instructions/slli/",
+ "/zh/isa/instructions/slliw/": "/isa/instructions/slliw/",
+ "/zh/isa/instructions/sllw/": "/isa/instructions/sllw/",
+ "/zh/isa/instructions/sra/": "/isa/instructions/sra/",
+ "/zh/isa/instructions/srai/": "/isa/instructions/srai/",
+ "/zh/isa/instructions/sraiw/": "/isa/instructions/sraiw/",
+ "/zh/isa/instructions/sraw/": "/isa/instructions/sraw/",
+ "/zh/isa/instructions/srl/": "/isa/instructions/srl/",
+ "/zh/isa/instructions/srli/": "/isa/instructions/srli/",
+ "/zh/isa/instructions/srliw/": "/isa/instructions/srliw/",
+ "/zh/isa/instructions/srlw/": "/isa/instructions/srlw/",
+ "/zh/isa/instructions/ssrget/": "/isa/instructions/ssrget/",
+ "/zh/isa/instructions/ssrset/": "/isa/instructions/ssrset/",
+ "/zh/isa/instructions/ssrswap/": "/isa/instructions/ssrswap/",
+ "/zh/isa/instructions/sub/": "/isa/instructions/sub/",
+ "/zh/isa/instructions/subi/": "/isa/instructions/subi/",
+ "/zh/isa/instructions/subiw/": "/isa/instructions/subiw/",
+ "/zh/isa/instructions/subw/": "/isa/instructions/subw/",
+ "/zh/isa/instructions/sw/": "/isa/instructions/sw/",
+ "/zh/isa/instructions/sw_add/": "/isa/instructions/sw_add/",
+ "/zh/isa/instructions/sw_and/": "/isa/instructions/sw_and/",
+ "/zh/isa/instructions/sw_or/": "/isa/instructions/sw_or/",
+ "/zh/isa/instructions/sw_pcr/": "/isa/instructions/sw_pcr/",
+ "/zh/isa/instructions/sw_smax/": "/isa/instructions/sw_smax/",
+ "/zh/isa/instructions/sw_smin/": "/isa/instructions/sw_smin/",
+ "/zh/isa/instructions/sw_u/": "/isa/instructions/sw_u/",
+ "/zh/isa/instructions/sw_umax/": "/isa/instructions/sw_umax/",
+ "/zh/isa/instructions/sw_umin/": "/isa/instructions/sw_umin/",
+ "/zh/isa/instructions/sw_xor/": "/isa/instructions/sw_xor/",
+ "/zh/isa/instructions/swapb/": "/isa/instructions/swapb/",
+ "/zh/isa/instructions/swapd/": "/isa/instructions/swapd/",
+ "/zh/isa/instructions/swaph/": "/isa/instructions/swaph/",
+ "/zh/isa/instructions/swapw/": "/isa/instructions/swapw/",
+ "/zh/isa/instructions/swi/": "/isa/instructions/swi/",
+ "/zh/isa/instructions/swi_u/": "/isa/instructions/swi_u/",
+ "/zh/isa/instructions/tlb_ia/": "/isa/instructions/tlb_ia/",
+ "/zh/isa/instructions/tlb_iall/": "/isa/instructions/tlb_iall/",
+ "/zh/isa/instructions/tlb_iav/": "/isa/instructions/tlb_iav/",
+ "/zh/isa/instructions/tlb_iv/": "/isa/instructions/tlb_iv/",
+ "/zh/isa/instructions/ucvtf/": "/isa/instructions/ucvtf/",
+ "/zh/isa/instructions/v_add/": "/isa/instructions/v_add/",
+ "/zh/isa/instructions/v_addi/": "/isa/instructions/v_addi/",
+ "/zh/isa/instructions/v_and/": "/isa/instructions/v_and/",
+ "/zh/isa/instructions/v_andi/": "/isa/instructions/v_andi/",
+ "/zh/isa/instructions/v_bcnt/": "/isa/instructions/v_bcnt/",
+ "/zh/isa/instructions/v_bic/": "/isa/instructions/v_bic/",
+ "/zh/isa/instructions/v_bis/": "/isa/instructions/v_bis/",
+ "/zh/isa/instructions/v_bxs/": "/isa/instructions/v_bxs/",
+ "/zh/isa/instructions/v_bxu/": "/isa/instructions/v_bxu/",
+ "/zh/isa/instructions/v_clz/": "/isa/instructions/v_clz/",
+ "/zh/isa/instructions/v_cmp_and/": "/isa/instructions/v_cmp_and/",
+ "/zh/isa/instructions/v_cmp_andi/": "/isa/instructions/v_cmp_andi/",
+ "/zh/isa/instructions/v_cmp_eq/": "/isa/instructions/v_cmp_eq/",
+ "/zh/isa/instructions/v_cmp_eqi/": "/isa/instructions/v_cmp_eqi/",
+ "/zh/isa/instructions/v_cmp_ge/": "/isa/instructions/v_cmp_ge/",
+ "/zh/isa/instructions/v_cmp_gei/": "/isa/instructions/v_cmp_gei/",
+ "/zh/isa/instructions/v_cmp_geu/": "/isa/instructions/v_cmp_geu/",
+ "/zh/isa/instructions/v_cmp_geui/": "/isa/instructions/v_cmp_geui/",
+ "/zh/isa/instructions/v_cmp_lt/": "/isa/instructions/v_cmp_lt/",
+ "/zh/isa/instructions/v_cmp_lti/": "/isa/instructions/v_cmp_lti/",
+ "/zh/isa/instructions/v_cmp_ltu/": "/isa/instructions/v_cmp_ltu/",
+ "/zh/isa/instructions/v_cmp_ltui/": "/isa/instructions/v_cmp_ltui/",
+ "/zh/isa/instructions/v_cmp_ne/": "/isa/instructions/v_cmp_ne/",
+ "/zh/isa/instructions/v_cmp_nei/": "/isa/instructions/v_cmp_nei/",
+ "/zh/isa/instructions/v_cmp_or/": "/isa/instructions/v_cmp_or/",
+ "/zh/isa/instructions/v_cmp_ori/": "/isa/instructions/v_cmp_ori/",
+ "/zh/isa/instructions/v_csel/": "/isa/instructions/v_csel/",
+ "/zh/isa/instructions/v_ctz/": "/isa/instructions/v_ctz/",
+ "/zh/isa/instructions/v_div/": "/isa/instructions/v_div/",
+ "/zh/isa/instructions/v_fabs/": "/isa/instructions/v_fabs/",
+ "/zh/isa/instructions/v_fadd/": "/isa/instructions/v_fadd/",
+ "/zh/isa/instructions/v_fclass/": "/isa/instructions/v_fclass/",
+ "/zh/isa/instructions/v_fcvt/": "/isa/instructions/v_fcvt/",
+ "/zh/isa/instructions/v_fcvti/": "/isa/instructions/v_fcvti/",
+ "/zh/isa/instructions/v_fdiv/": "/isa/instructions/v_fdiv/",
+ "/zh/isa/instructions/v_feq/": "/isa/instructions/v_feq/",
+ "/zh/isa/instructions/v_feqs/": "/isa/instructions/v_feqs/",
+ "/zh/isa/instructions/v_fexp/": "/isa/instructions/v_fexp/",
+ "/zh/isa/instructions/v_fge/": "/isa/instructions/v_fge/",
+ "/zh/isa/instructions/v_fges/": "/isa/instructions/v_fges/",
+ "/zh/isa/instructions/v_flt/": "/isa/instructions/v_flt/",
+ "/zh/isa/instructions/v_flts/": "/isa/instructions/v_flts/",
+ "/zh/isa/instructions/v_fmadd/": "/isa/instructions/v_fmadd/",
+ "/zh/isa/instructions/v_fmax/": "/isa/instructions/v_fmax/",
+ "/zh/isa/instructions/v_fmin/": "/isa/instructions/v_fmin/",
+ "/zh/isa/instructions/v_fmsub/": "/isa/instructions/v_fmsub/",
+ "/zh/isa/instructions/v_fmul/": "/isa/instructions/v_fmul/",
+ "/zh/isa/instructions/v_fne/": "/isa/instructions/v_fne/",
+ "/zh/isa/instructions/v_fnes/": "/isa/instructions/v_fnes/",
+ "/zh/isa/instructions/v_fnmadd/": "/isa/instructions/v_fnmadd/",
+ "/zh/isa/instructions/v_fnmsub/": "/isa/instructions/v_fnmsub/",
+ "/zh/isa/instructions/v_frecip/": "/isa/instructions/v_frecip/",
+ "/zh/isa/instructions/v_fsqrt/": "/isa/instructions/v_fsqrt/",
+ "/zh/isa/instructions/v_fsub/": "/isa/instructions/v_fsub/",
+ "/zh/isa/instructions/v_icvt/": "/isa/instructions/v_icvt/",
+ "/zh/isa/instructions/v_icvtf/": "/isa/instructions/v_icvtf/",
+ "/zh/isa/instructions/v_lb/": "/isa/instructions/v_lb/",
+ "/zh/isa/instructions/v_lb_brg/": "/isa/instructions/v_lb_brg/",
+ "/zh/isa/instructions/v_lbi/": "/isa/instructions/v_lbi/",
+ "/zh/isa/instructions/v_lbi_brg/": "/isa/instructions/v_lbi_brg/",
+ "/zh/isa/instructions/v_lbu/": "/isa/instructions/v_lbu/",
+ "/zh/isa/instructions/v_lbu_brg/": "/isa/instructions/v_lbu_brg/",
+ "/zh/isa/instructions/v_lbui/": "/isa/instructions/v_lbui/",
+ "/zh/isa/instructions/v_lbui_brg/": "/isa/instructions/v_lbui_brg/",
+ "/zh/isa/instructions/v_ld/": "/isa/instructions/v_ld/",
+ "/zh/isa/instructions/v_ld_add/": "/isa/instructions/v_ld_add/",
+ "/zh/isa/instructions/v_ld_and/": "/isa/instructions/v_ld_and/",
+ "/zh/isa/instructions/v_ld_brg/": "/isa/instructions/v_ld_brg/",
+ "/zh/isa/instructions/v_ld_max/": "/isa/instructions/v_ld_max/",
+ "/zh/isa/instructions/v_ld_min/": "/isa/instructions/v_ld_min/",
+ "/zh/isa/instructions/v_ld_or/": "/isa/instructions/v_ld_or/",
+ "/zh/isa/instructions/v_ld_xor/": "/isa/instructions/v_ld_xor/",
+ "/zh/isa/instructions/v_ldi/": "/isa/instructions/v_ldi/",
+ "/zh/isa/instructions/v_ldi_brg/": "/isa/instructions/v_ldi_brg/",
+ "/zh/isa/instructions/v_ldi_u/": "/isa/instructions/v_ldi_u/",
+ "/zh/isa/instructions/v_ldi_u_brg/": "/isa/instructions/v_ldi_u_brg/",
+ "/zh/isa/instructions/v_lh/": "/isa/instructions/v_lh/",
+ "/zh/isa/instructions/v_lh_brg/": "/isa/instructions/v_lh_brg/",
+ "/zh/isa/instructions/v_lhi/": "/isa/instructions/v_lhi/",
+ "/zh/isa/instructions/v_lhi_brg/": "/isa/instructions/v_lhi_brg/",
+ "/zh/isa/instructions/v_lhi_u/": "/isa/instructions/v_lhi_u/",
+ "/zh/isa/instructions/v_lhi_u_brg/": "/isa/instructions/v_lhi_u_brg/",
+ "/zh/isa/instructions/v_lhu/": "/isa/instructions/v_lhu/",
+ "/zh/isa/instructions/v_lhu_brg/": "/isa/instructions/v_lhu_brg/",
+ "/zh/isa/instructions/v_lhui/": "/isa/instructions/v_lhui/",
+ "/zh/isa/instructions/v_lhui_brg/": "/isa/instructions/v_lhui_brg/",
+ "/zh/isa/instructions/v_lhui_u/": "/isa/instructions/v_lhui_u/",
+ "/zh/isa/instructions/v_lhui_u_brg/": "/isa/instructions/v_lhui_u_brg/",
+ "/zh/isa/instructions/v_lw/": "/isa/instructions/v_lw/",
+ "/zh/isa/instructions/v_lw_add/": "/isa/instructions/v_lw_add/",
+ "/zh/isa/instructions/v_lw_and/": "/isa/instructions/v_lw_and/",
+ "/zh/isa/instructions/v_lw_brg/": "/isa/instructions/v_lw_brg/",
+ "/zh/isa/instructions/v_lw_max/": "/isa/instructions/v_lw_max/",
+ "/zh/isa/instructions/v_lw_min/": "/isa/instructions/v_lw_min/",
+ "/zh/isa/instructions/v_lw_or/": "/isa/instructions/v_lw_or/",
+ "/zh/isa/instructions/v_lw_xor/": "/isa/instructions/v_lw_xor/",
+ "/zh/isa/instructions/v_lwi/": "/isa/instructions/v_lwi/",
+ "/zh/isa/instructions/v_lwi_brg/": "/isa/instructions/v_lwi_brg/",
+ "/zh/isa/instructions/v_lwi_u/": "/isa/instructions/v_lwi_u/",
+ "/zh/isa/instructions/v_lwi_u_brg/": "/isa/instructions/v_lwi_u_brg/",
+ "/zh/isa/instructions/v_lwu/": "/isa/instructions/v_lwu/",
+ "/zh/isa/instructions/v_lwu_brg/": "/isa/instructions/v_lwu_brg/",
+ "/zh/isa/instructions/v_lwui/": "/isa/instructions/v_lwui/",
+ "/zh/isa/instructions/v_lwui_brg/": "/isa/instructions/v_lwui_brg/",
+ "/zh/isa/instructions/v_lwui_u/": "/isa/instructions/v_lwui_u/",
+ "/zh/isa/instructions/v_lwui_u_brg/": "/isa/instructions/v_lwui_u_brg/",
+ "/zh/isa/instructions/v_madd/": "/isa/instructions/v_madd/",
+ "/zh/isa/instructions/v_max/": "/isa/instructions/v_max/",
+ "/zh/isa/instructions/v_min/": "/isa/instructions/v_min/",
+ "/zh/isa/instructions/v_mul/": "/isa/instructions/v_mul/",
+ "/zh/isa/instructions/v_or/": "/isa/instructions/v_or/",
+ "/zh/isa/instructions/v_ori/": "/isa/instructions/v_ori/",
+ "/zh/isa/instructions/v_psel/": "/isa/instructions/v_psel/",
+ "/zh/isa/instructions/v_qpop/": "/isa/instructions/v_qpop/",
+ "/zh/isa/instructions/v_qpush/": "/isa/instructions/v_qpush/",
+ "/zh/isa/instructions/v_rdadd/": "/isa/instructions/v_rdadd/",
+ "/zh/isa/instructions/v_rdand/": "/isa/instructions/v_rdand/",
+ "/zh/isa/instructions/v_rdfadd/": "/isa/instructions/v_rdfadd/",
+ "/zh/isa/instructions/v_rdfmax/": "/isa/instructions/v_rdfmax/",
+ "/zh/isa/instructions/v_rdfmin/": "/isa/instructions/v_rdfmin/",
+ "/zh/isa/instructions/v_rdmax/": "/isa/instructions/v_rdmax/",
+ "/zh/isa/instructions/v_rdmin/": "/isa/instructions/v_rdmin/",
+ "/zh/isa/instructions/v_rdor/": "/isa/instructions/v_rdor/",
+ "/zh/isa/instructions/v_rdxor/": "/isa/instructions/v_rdxor/",
+ "/zh/isa/instructions/v_rem/": "/isa/instructions/v_rem/",
+ "/zh/isa/instructions/v_rev/": "/isa/instructions/v_rev/",
+ "/zh/isa/instructions/v_sb/": "/isa/instructions/v_sb/",
+ "/zh/isa/instructions/v_sb_brg/": "/isa/instructions/v_sb_brg/",
+ "/zh/isa/instructions/v_sbi/": "/isa/instructions/v_sbi/",
+ "/zh/isa/instructions/v_sbi_brg/": "/isa/instructions/v_sbi_brg/",
+ "/zh/isa/instructions/v_sd/": "/isa/instructions/v_sd/",
+ "/zh/isa/instructions/v_sd_add/": "/isa/instructions/v_sd_add/",
+ "/zh/isa/instructions/v_sd_and/": "/isa/instructions/v_sd_and/",
+ "/zh/isa/instructions/v_sd_brg/": "/isa/instructions/v_sd_brg/",
+ "/zh/isa/instructions/v_sd_max/": "/isa/instructions/v_sd_max/",
+ "/zh/isa/instructions/v_sd_min/": "/isa/instructions/v_sd_min/",
+ "/zh/isa/instructions/v_sd_or/": "/isa/instructions/v_sd_or/",
+ "/zh/isa/instructions/v_sd_u/": "/isa/instructions/v_sd_u/",
+ "/zh/isa/instructions/v_sd_u_brg/": "/isa/instructions/v_sd_u_brg/",
+ "/zh/isa/instructions/v_sd_xor/": "/isa/instructions/v_sd_xor/",
+ "/zh/isa/instructions/v_sdi/": "/isa/instructions/v_sdi/",
+ "/zh/isa/instructions/v_sdi_brg/": "/isa/instructions/v_sdi_brg/",
+ "/zh/isa/instructions/v_sdi_u/": "/isa/instructions/v_sdi_u/",
+ "/zh/isa/instructions/v_sdi_u_brg/": "/isa/instructions/v_sdi_u_brg/",
+ "/zh/isa/instructions/v_sh/": "/isa/instructions/v_sh/",
+ "/zh/isa/instructions/v_sh_brg/": "/isa/instructions/v_sh_brg/",
+ "/zh/isa/instructions/v_sh_u/": "/isa/instructions/v_sh_u/",
+ "/zh/isa/instructions/v_sh_u_brg/": "/isa/instructions/v_sh_u_brg/",
+ "/zh/isa/instructions/v_shfl_bfly/": "/isa/instructions/v_shfl_bfly/",
+ "/zh/isa/instructions/v_shfl_down/": "/isa/instructions/v_shfl_down/",
+ "/zh/isa/instructions/v_shfl_idx/": "/isa/instructions/v_shfl_idx/",
+ "/zh/isa/instructions/v_shfl_up/": "/isa/instructions/v_shfl_up/",
+ "/zh/isa/instructions/v_shfli_bfly/": "/isa/instructions/v_shfli_bfly/",
+ "/zh/isa/instructions/v_shfli_down/": "/isa/instructions/v_shfli_down/",
+ "/zh/isa/instructions/v_shfli_idx/": "/isa/instructions/v_shfli_idx/",
+ "/zh/isa/instructions/v_shfli_up/": "/isa/instructions/v_shfli_up/",
+ "/zh/isa/instructions/v_shi/": "/isa/instructions/v_shi/",
+ "/zh/isa/instructions/v_shi_brg/": "/isa/instructions/v_shi_brg/",
+ "/zh/isa/instructions/v_shi_u/": "/isa/instructions/v_shi_u/",
+ "/zh/isa/instructions/v_shi_u_brg/": "/isa/instructions/v_shi_u_brg/",
+ "/zh/isa/instructions/v_sll/": "/isa/instructions/v_sll/",
+ "/zh/isa/instructions/v_slli/": "/isa/instructions/v_slli/",
+ "/zh/isa/instructions/v_sra/": "/isa/instructions/v_sra/",
+ "/zh/isa/instructions/v_srai/": "/isa/instructions/v_srai/",
+ "/zh/isa/instructions/v_srl/": "/isa/instructions/v_srl/",
+ "/zh/isa/instructions/v_srli/": "/isa/instructions/v_srli/",
+ "/zh/isa/instructions/v_sub/": "/isa/instructions/v_sub/",
+ "/zh/isa/instructions/v_subi/": "/isa/instructions/v_subi/",
+ "/zh/isa/instructions/v_sw/": "/isa/instructions/v_sw/",
+ "/zh/isa/instructions/v_sw_add/": "/isa/instructions/v_sw_add/",
+ "/zh/isa/instructions/v_sw_and/": "/isa/instructions/v_sw_and/",
+ "/zh/isa/instructions/v_sw_brg/": "/isa/instructions/v_sw_brg/",
+ "/zh/isa/instructions/v_sw_max/": "/isa/instructions/v_sw_max/",
+ "/zh/isa/instructions/v_sw_min/": "/isa/instructions/v_sw_min/",
+ "/zh/isa/instructions/v_sw_or/": "/isa/instructions/v_sw_or/",
+ "/zh/isa/instructions/v_sw_u/": "/isa/instructions/v_sw_u/",
+ "/zh/isa/instructions/v_sw_u_brg/": "/isa/instructions/v_sw_u_brg/",
+ "/zh/isa/instructions/v_sw_xor/": "/isa/instructions/v_sw_xor/",
+ "/zh/isa/instructions/v_swi/": "/isa/instructions/v_swi/",
+ "/zh/isa/instructions/v_swi_brg/": "/isa/instructions/v_swi_brg/",
+ "/zh/isa/instructions/v_swi_u/": "/isa/instructions/v_swi_u/",
+ "/zh/isa/instructions/v_swi_u_brg/": "/isa/instructions/v_swi_u_brg/",
+ "/zh/isa/instructions/v_xor/": "/isa/instructions/v_xor/",
+ "/zh/isa/instructions/v_xori/": "/isa/instructions/v_xori/",
+ "/zh/isa/instructions/xb/": "/isa/instructions/xb/",
+ "/zh/isa/instructions/xor/": "/isa/instructions/xor/",
+ "/zh/isa/instructions/xori/": "/isa/instructions/xori/",
+ "/zh/isa/instructions/xoriw/": "/isa/instructions/xoriw/",
+ "/zh/isa/instructions/xorw/": "/isa/instructions/xorw/",
+ "/zh/isa/instset/baseExtInstrs/": "/isa/instset/baseExtInstrs/",
+ "/zh/isa/instset/baseInstrs/": "/isa/instset/baseInstrs/",
+ "/zh/isa/instset/compressInstrs/": "/isa/instset/compressInstrs/",
+ "/zh/isa/instset/haflLongInstrs/": "/isa/instset/haflLongInstrs/",
+ "/zh/isa/instset/longInstrs/": "/isa/instset/longInstrs/",
+ "/zh/isa/instset/standardInstrs/": "/isa/instset/standardInstrs/",
+ "/zh/isa/model/BCC/": "/isa/model/BCC/",
+ "/zh/isa/model/BCTRL/": "/isa/model/BCTRL/",
+ "/zh/isa/model/BIFU/": "/isa/model/BIFU/",
+ "/zh/isa/model/BIssue/": "/isa/model/BIssue/",
+ "/zh/isa/model/BROB/": "/isa/model/BROB/",
+ "/zh/isa/model/BRename/": "/isa/model/BRename/",
+ "/zh/isa/model/iex_dispatch/": "/isa/model/iex_dispatch/",
+ "/zh/isa/model/iex_issueq/": "/isa/model/iex_issueq/",
+ "/zh/isa/model/pe/": "/isa/model/pe/",
+ "/zh/isa/model/pe_ibp/": "/isa/model/pe_ibp/",
+ "/zh/isa/model/pe_ifu/": "/isa/model/pe_ifu/",
+ "/zh/isa/model/pe_rob/": "/isa/model/pe_rob/",
+ "/zh/isa/register/common/barg/": "/isa/register/common/barg/",
+ "/zh/isa/register/common/bpc/": "/isa/register/common/bpc/",
+ "/zh/isa/register/common/ggpr/": "/isa/register/common/ggpr/",
+ "/zh/isa/register/common/intro/": "/isa/register/common/intro/",
+ "/zh/isa/register/common/lgpr/": "/isa/register/common/lgpr/",
+ "/zh/isa/register/common/loop/": "/isa/register/common/loop/",
+ "/zh/isa/register/common/ltar/": "/isa/register/common/ltar/",
+ "/zh/isa/register/common/pred/": "/isa/register/common/pred/",
+ "/zh/isa/register/common/sgpr/": "/isa/register/common/sgpr/",
+ "/zh/isa/register/common/tilereg/": "/isa/register/common/tilereg/",
+ "/zh/isa/register/common/tpc/": "/isa/register/common/tpc/",
+ "/zh/isa/register/common/vgpr/": "/isa/register/common/vgpr/",
+ "/zh/isa/register/ssr/ACR_PARAM/": "/isa/register/ssr/ACR_PARAM/",
+ "/zh/isa/register/ssr/BLOCKID/": "/isa/register/ssr/BLOCKID/",
+ "/zh/isa/register/ssr/BLOCKNUM/": "/isa/register/ssr/BLOCKNUM/",
+ "/zh/isa/register/ssr/CSTATE/": "/isa/register/ssr/CSTATE/",
+ "/zh/isa/register/ssr/CW/": "/isa/register/ssr/CW/",
+ "/zh/isa/register/ssr/CYCLE/": "/isa/register/ssr/CYCLE/",
+ "/zh/isa/register/ssr/EBARG/": "/isa/register/ssr/EBARG/",
+ "/zh/isa/register/ssr/EBPC/": "/isa/register/ssr/EBPC/",
+ "/zh/isa/register/ssr/EBPCN/": "/isa/register/ssr/EBPCN/",
+ "/zh/isa/register/ssr/EBSTATEP/": "/isa/register/ssr/EBSTATEP/",
+ "/zh/isa/register/ssr/ECONFIG/": "/isa/register/ssr/ECONFIG/",
+ "/zh/isa/register/ssr/ECSTATE/": "/isa/register/ssr/ECSTATE/",
+ "/zh/isa/register/ssr/EOIEI/": "/isa/register/ssr/EOIEI/",
+ "/zh/isa/register/ssr/ETEMP/": "/isa/register/ssr/ETEMP/",
+ "/zh/isa/register/ssr/ETPC/": "/isa/register/ssr/ETPC/",
+ "/zh/isa/register/ssr/EVBASE/": "/isa/register/ssr/EVBASE/",
+ "/zh/isa/register/ssr/FUTO/": "/isa/register/ssr/FUTO/",
+ "/zh/isa/register/ssr/GP/": "/isa/register/ssr/GP/",
+ "/zh/isa/register/ssr/IPENDING/": "/isa/register/ssr/IPENDING/",
+ "/zh/isa/register/ssr/LCFR/": "/isa/register/ssr/LCFR/",
+ "/zh/isa/register/ssr/LCFR_EN/": "/isa/register/ssr/LCFR_EN/",
+ "/zh/isa/register/ssr/LXLCID/": "/isa/register/ssr/LXLCID/",
+ "/zh/isa/register/ssr/MMCONFIG/": "/isa/register/ssr/MMCONFIG/",
+ "/zh/isa/register/ssr/MMTBASE/": "/isa/register/ssr/MMTBASE/",
+ "/zh/isa/register/ssr/MSGB/": "/isa/register/ssr/MSGB/",
+ "/zh/isa/register/ssr/SYSCNT/": "/isa/register/ssr/SYSCNT/",
+ "/zh/isa/register/ssr/TIME/": "/isa/register/ssr/TIME/",
+ "/zh/isa/register/ssr/TIMER_TIME/": "/isa/register/ssr/TIMER_TIME/",
+ "/zh/isa/register/ssr/TIMER_TIMECMP/": "/isa/register/ssr/TIMER_TIMECMP/",
+ "/zh/isa/register/ssr/TOPEI/": "/isa/register/ssr/TOPEI/",
+ "/zh/isa/register/ssr/TP/": "/isa/register/ssr/TP/",
+ "/zh/isa/register/ssr/TR/": "/isa/register/ssr/TR/",
+ "/zh/isa/register/ssr/TRAPARG0/": "/isa/register/ssr/TRAPARG0/",
+ "/zh/isa/register/ssr/TRAPNO/": "/isa/register/ssr/TRAPNO/",
+ "/zh/isa/register/ssr/VENDOR/": "/isa/register/ssr/VENDOR/",
+ "/zh/isa/register/ssr/VERSION/": "/isa/register/ssr/VERSION/",
+ "/zh/isa/register/ssr/XBINFO/": "/isa/register/ssr/XBINFO/",
+ "/zh/isa/register/ssr/common/": "/isa/register/ssr/common/",
+ "/zh/isa/register/ssr/lightcore/": "/isa/register/ssr/lightcore/",
+ "/zh/isa/register/ssr/per-acr/": "/isa/register/ssr/per-acr/",
+ "/zh/isa/register/ssr/ssrintro/": "/isa/register/ssr/ssrintro/",
+ "/zh/isa/timer/": "/isa/timer/",
+ "/zh/memory/dcache/load_pipeline/": "/memory/dcache/load_pipeline/",
+ "/zh/memory/dcache/writeback_queue/": "/memory/dcache/writeback_queue/",
+ "/zh/memory/fu/load_pipeline/": "/memory/fu/load_pipeline/",
+ "/zh/memory/fu/store_pipeline/": "/memory/fu/store_pipeline/",
+ "/zh/memory/overview/": "/memory/overview/",
+ "/zh/misc/spec17int/": "/misc/spec17int/",
+ "/zh/pe/codetemplate/": "/pe/codetemplate/",
+ "/zh/pe/ope/": "/pe/ope/",
+ "/zh/performance/regUsageFrequency/": "/performance/regUsageFrequency/",
+ "/zh/performance/specint_analysis/": "/performance/specint_analysis/",
+ "/zh/performance/specint_runpoint/": "/performance/specint_runpoint/",
+ "/zh/performance/specint_temlblock_rate/": "/performance/specint_temlblock_rate/",
+ "/zh/performance/top-down/": "/performance/top-down/",
+ "/zh/project/README/": "/project/README/",
+ "/zh/project/maintainer-repin-checklist/": "/project/maintainer-repin-checklist/",
+ "/zh/project/navigation/": "/project/navigation/",
+ "/zh/project/new-agent-sop/": "/project/new-agent-sop/",
+ "/zh/project/omx-linxisa-playbook/": "/project/omx-linxisa-playbook/",
+ "/zh/project/omx-linxisa-prompt-templates/": "/project/omx-linxisa-prompt-templates/",
+ "/zh/project/repository-flow/": "/project/repository-flow/",
+ "/zh/project/superproject-bringup-methodology/": "/project/superproject-bringup-methodology/",
+ "/zh/reference/README/": "/reference/README/",
+ "/zh/reference/encoding_space_report/": "/reference/encoding_space_report/",
+ "/zh/reference/examples/README/": "/reference/examples/README/",
+ "/zh/reference/examples/v0.56/README/": "/reference/examples/v0.56/README/",
+ "/zh/reference/linxisa-assembly-agent-guide/": "/reference/linxisa-assembly-agent-guide/",
+ "/zh/reference/linxisa-call-ret-contract/": "/reference/linxisa-call-ret-contract/",
+ "/zh/releases/v0.3.0/": "/releases/v0.3.0/",
+ "/zh/releases/v0.56.2/": "/releases/v0.56.2/",
+ "/zh/white_paper/Chapter-2/": "/white_paper/Chapter-2/",
+ "/zh/white_paper/Chapter-3/": "/white_paper/Chapter-3/",
+ "/zh/white_paper/Chapter-4/": "/white_paper/Chapter-4/",
+ "/zh/white_paper/Chapter-5/": "/white_paper/Chapter-5/",
+ "/zh/white_paper/Chapter-6/": "/white_paper/Chapter-6/",
+ "/zh/white_paper/Chapter-7/": "/white_paper/Chapter-7/",
+ "/zh/white_paper/Chapter-8/": "/white_paper/Chapter-8/",
+ "/zh/white_paper/Chapter-9/": "/white_paper/Chapter-9/",
+ "/zh/white_paper/Intro/": "/white_paper/Intro/",
+ "/zh/white_paper_en/chapter1/": "/white_paper_en/chapter1/",
+ "/zh/white_paper_en/chapter2/": "/white_paper_en/chapter2/",
+ "/zh/white_paper_en/chapter3/": "/white_paper_en/chapter3/",
+ "/zh/white_paper_en/chapter4/": "/white_paper_en/chapter4/",
+ "/zh/white_paper_en/chapter5/": "/white_paper_en/chapter5/",
+ "/zh/white_paper_en/chapter6/": "/white_paper_en/chapter6/",
+ "/zh/white_paper_en/chapter7/": "/white_paper_en/chapter7/"
+}
diff --git a/docs/backend/exu.md b/docs/backend/exu.md
new file mode 100644
index 00000000..80a5c408
--- /dev/null
+++ b/docs/backend/exu.md
@@ -0,0 +1,25 @@
+# Execution unit
+
+After the instruction is issued, it will enter the execution unit, which contains three (or more) pipeline levels: register read (RF), data forwarding (BY), and calculation (EX). The calculation can be one or more clock cycles depending on the instruction.
+
+## Data
+
+Within PE, the results of all instructions will be stored in the PE register file. The source operands of all instructions come from the BPC Buffer, block register file and PE register file. Its detailed structure is described in the following chapters:
+
+* [Block Register File](https://openx.huawei.com/mkdocs/project/1410/blockisa-doc/docs/site/docs/bcc/brf/)
+
+* [PE register file](https://openx.huawei.com/mkdocs/project/1410/blockisa-doc/docs/site/docs/backend/pe_rf/)
+
+## Operation
+
+In LinxISA, instructions are divided into three categories: memory access (LSU), calculation (ALU), external communication and PC operation (GSU). We have one or more specific computing units for each type. After the calculation is completed, the result will be sent to the register file in the WriteBack pipeline to be written to the destination register and participate in forwarding.
+
+In this chapter we will divide the calculation into two parts, including:
+
+* [Integer operation](https://openx.huawei.com/mkdocs/project/1410/blockisa-doc/docs/site/docs/backend/exu_int/)
+
+* [Floating point operation](https://openx.huawei.com/mkdocs/project/1410/blockisa-doc/docs/site/docs/backend/exu_fp/)
+
+## Structural block diagram
+
+{ width="800" }
\ No newline at end of file
diff --git a/docs/backend/issue.md b/docs/backend/issue.md
new file mode 100644
index 00000000..83b62901
--- /dev/null
+++ b/docs/backend/issue.md
@@ -0,0 +1,81 @@
+# Issue Queue (ISQ)
+
+The launch queue is where instructions are waiting to be issued. Since the operands required for the instructions are not ready yet, the instructions will wait in this module class. Since microinstructions are divided into three categories: **Memory Access Class (LSU)**, **Computing Class (ALU)**, and **External Communication and PC Operation Class (GSU**), the launch queue is also divided into three categories and five sub-queues, **AB ISQ**, **AM ISQ**, **LS0 ISQ**, **LS1 ISQ**, **GSU ISQ**.
+
+When the instruction is executed, the issue queue will receive the corresponding operand wake-up signal from the downstream to inform the issue queue that the operation number has been calculated. When all source operands required for an instruction in the issue queue have been awakened, the instruction can be selected and issued. In each clock cycle, each issue queue selects an instruction that can be issued and sends it to the downstream computing unit. When there are multiple instructions in the queue that can be issued, the priority selected is the older the program sequence is, the higher it is. Most selected instructions will do a speculative execution operation (precommit) to wake up the instructions in the issue queue to improve performance.
+
+## Introduction to launch queue
+
+Each subqueue can receive up to 2 microinstructions of the corresponding type per clock cycle.
+- GS_ISQ can receive GET/SET type instructions or SGET/SSET type instructions
+- AB_ISQ can receive 1 cycle instructions such as BR/SETC.XX/ALU/STA
+- AM_ISQ can receive 1 cycle instructions such as ALU/STA and 2 cycle MUL instructions
+- LS0_ISQ/LS1_ISQ can receive memory access instructions such as STD/LDA
+
+## Transmit queue field segment| Field segment | Bit width | Description |
+| ---------------- | ---- | ----------------------------------------------- |
+| Src0_vld | 1 | Source operand 0 valid |
+| Src1_vld | 1 | Source operand 1 valid |
+| Src0_tag | 6 | Source operand 0 physical register number |
+| Src1_tag | 6 | Source operand 1 physical register number |
+| Src0_rdy | 1 | Source operand 0 wakeup |
+| Src1_rdy | 1 | Source operand 1 wakeup |
+| Dst_vld | 1 | destination valid |
+| Dst_tag | 1 | Destination physical register number |
+| Entry Valid | 1 | This entry is valid |
+| Block ROBID | 7 | The block ROBID used to record this instruction |
+| PE ROBID | 7 | Microinstruction ROBID used to record this instruction |
+| Load Gene Vector | 2x3 | 3-bit per source operand Load Gene Vector |
+| Depend source | 2x3 | Pipeline representing data dependencies, 3-bit per source operand |
+| Tracking Vector | 2x3 | Indicates the pipeline level at which data should be forwarded, 3-bit per source operand |
+
+## Architecture block diagram
+
+
+In the microarchitecture, we have two computing pipelines, so there are two ALU ISQs. Each clock cycle, the hardware can select the awakened instructions from these two ALU ISQs and send them to the downstream. LSU and GSU have only one pipeline, and only one LSU class instruction and one GSU class instruction can be selected per clock cycle. But currently their launch queue is divided into two banks. If only one Bank has an instruction that can be picked, that instruction is output. If both banks have instructions that can be picked, a polling arbiter is used to ensure that one instruction is picked every clock cycle.
+
+## Wakeup
+Wake-up logic is divided into two categories: active wake-up and passive wake-up. Among them:
+
+* Active wake-up means that before the instruction enters the emission queue, the hardware will query the OOO module that stores the operand status for the wake-up status of the operand required for the instruction. If the operand has been awakened before, the Srcx_rdy field segment of the corresponding source operand of the instruction is set to 1 when it enters the emission queue.
+
+* Passive wake-up means that when an operand is calculated or read, or is about to be obtained, the hardware will wake up the instruction corresponding to the operand by comparing the physical register number in the launch queue, that is, setting Srcx_rdy to 1.The timing of passive awakening is also very important:
+* For instruction A completed in **single clock cycle**, it can wake up other instructions B when it is issued. This is because when instruction B needs to use the data to perform operations, the instruction A it depends on has already been calculated, and instruction B can obtain the dependent data through the forwarding network.
+* For instruction A completed in **multiple clock cycles**, it will not wake up other instructions B immediately when it is issued, but will wake up the source operand of instruction B after N beats. The timing is set so that the forwarded dependent data can be received just when instruction B is issued and calculated. (For the Load instruction, the hardware will assume an execution time of 4 clock cycles, that is, Cache Hit. This solution will be explained in the Load speculative launch chapter)
+
+## Age matrix
+Age Matrix is a module used to record the old and new relationships between entries in the launch queue. It has the following rules:
+
+1. Age matrix cache, using a separate cache to record the age of data stored in the launch queue, that is, recording the order in which an instruction is stored in the cache. Age Matrix always outputs the one-hot code in the cache that is first stored in the emission queue.
+2. The Age Matrix itself does not store the content of the data. It is only responsible for recording the age of the data entering the transmission queue in order to find the oldest entry.
+3. The Age matrix is written at the same time as the emission queue. ISQ stores the information about the instructions themselves, and Age Matrix stores the order of instructions.
+4. The wake-up signal of the instruction in ISQ is used as the unmask signal of the Age Matrix, so that the Age Matrix can find the oldest entry from the unmask entry, thereby satisfying the oldest-first principle of arbitration instructions in the launch queue.
+
+
+### Age Matrix principle:
+1. When a new entry x is pushed into the cache, cell[a][j] is cleared to 0 and cell[i][a] is written to 1. (The rows are written with all 0s, and the columns are written with all 1s. That is shown in blue and yellow as shown in the figure, where i represents the row and j represents the column).
+2. When valid cell[i][j] = 1, it means that the valid entry I and entry j in the cache are older than entry j.
+3. Calculation algorithm for the oldest entry x:
+ 3.1 Any cell[a][j] is either invalid or 1.
+ 3.2 Any cell[i][a] is either invalid or 0.
+
+For example:
+Assuming an emission queue with a depth of 8, the corresponding Age Matrix is as shown in the figure:
+1~7 represents table item 1 ~ table item 7, 0~6 represents table item 0 ~ table item 6;
+
+{ width="800" }
+
+For example:
+When the order of writing to the cache is 3, 1, 5, 4, 2, 0, 7, 6, according to the principle, each time data is written to a new table entry, the rows in the corresponding table entries are written with 0 and the columns are written with 1. After eight times, the Age Matrix as shown in the figure is obtained. You can see that the rows of table entry 3 are all 1 and the columns are all 0, so table entry 3 is the oldest.
+
+{ width="800" }
+
+## Data forwarding (Bypass)
+Generally speaking, register forwarding in the processor is done by using the equality of read PTAG and write PTAG as an enable signal before EXE pipeline to select the correct operand. In the BlockISA microarchitecture, the microarchitecture adopts another way to judge data forwarding. In the emission queue, two additional pieces of information are maintained for each source operand:
+
+1. **Depended Source**:
+Depended Source indicates which pipe the source operand comes from. It has been recorded in OOO in the REN module when the instruction is distributed, and the signal records the pipe through which the instruction is distributed. When subsequent dependent instructions enter the issue queue, the microarchitecture will not only query the wake-up status of its source operand in the rename module, but also query the production pipeline of its source operand, and record it in the issue queue. For ease of understanding, we can regard the Depended Source information as the ordinate of the target data source.2. **Tracking Vector**:
+Tracking Vector represents the pipeline level at which data should be forwarded. e.g. 3'b100 = WB1, 3'b010 = WB2, 3'b001 = W3, 3'b000 = RF. The Tracking Vector will be set through two modules. If the instruction queries OOO when it enters the launch queue and finds that the source operand has been awakened, the Tracking Vector recorded in OOO will be used directly. If the instruction is not awakened when entering ISQ, when the source operand is awakened, the Tracking Vector is set to 3'b100, which means that the data will be visible in the register file after 3 clock cycles. For ease of understanding, we can regard the Depended Source information as the abscissa of the target data source.
+The Tracking vector will be activated when the source operand in the issue queue is awakened. After activation, if the instruction has not been issued, the Tracking Vector of its source operand will be shifted to the right until it is shifted to 0, which means that its source operand can be read directly from RF without forwarding. If the instruction is issued from the emission queue, the two Tracking Vectors of the instruction will no longer be shifted.
+
+Through these two parameters (X, Y coordinates), the microarchitecture can directly select the correct source operation data, thus easing the forwarding logic. At the same time, through this approach, the microarchitecture can save unnecessary RF reading power consumption, thereby saving power consumption.
\ No newline at end of file
diff --git a/docs/backend/pe_rf.md b/docs/backend/pe_rf.md
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+# PE register file
+
+
+The PE register file is a register group at the PE level in Linx Instruction Set Architecture. Its function is to write the operation results of the microinstructions and read the source operands of the microinstructions. Each microinstruction defined in Linx Instruction Set Architecture has its own virtual register. This virtual register does not need to be expressed explicitly, but is bound to the instruction ID within the block. Therefore, we also omit the renaming unit in the microarchitecture, and instead use ROBID to replace the renaming work.
+
+At the same time, in order to make the graph coding more compact, the block instruction set defines that each microinstruction can only index the results of microinstructions 1-8 away from itself. The advantage of this is that microinstructions express an instruction flow graph according to relative distances (within 8), so that the encoding space advantage is greatest. Because in the instruction flow graph, there are very few scenarios where the instruction dependency distance exceeds 8. For scenes where the distance exceeds 8, we can achieve long-distance indexing through copying or chunking.
+
+In the microarchitecture, the PE register file is 64 deep and each register is 64-bit wide. The register file supports 4 writes and 8 reads at the same time. The four execution channels occupy two read ports and one write port respectively.
\ No newline at end of file
diff --git a/docs/backend/rob.md b/docs/backend/rob.md
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+# Linx Instruction Set Architecture ROB (Reorder buffer) introduction
+
+In the processor architecture, ROB is a mechanism to achieve sequential submission of instructions and accurate exception, enabling the processor to achieve precise exception processing and effective hardware speculative execution. The principle can be simply summarized as sequential enqueue and sequential submission (dequeue). This function is usually implemented with a FIFO.
+
+ROB will track the instructions that have been issued in the pipeline, record whether the instructions have been executed, whether exception and other information, and submit the executed instructions in sequence, and save the instruction results to the register file or write them into the memory. Uncommitted instructions will wait in the ROB, so the depth of the ROB is the depth of hardware speculative execution. For most programs, greater speculation depth means more opportunities to exploit parallelism, thereby obtaining better performance.
+
+In order to solve a series of problems such as precise exception, mainstream processors have adopted the sequential submission execution paradigm. However, this paradigm requires instructions to occupy hardware resources until the instruction becomes the oldest instruction before the resources can be released sequentially. At the same time, if the execution time of the oldest instruction is too long, such as the read instruction L3 cache is missing, the instruction will always block the hardware, causing subsequent instructions to be unable to be submitted.
+
+Different from common processor architectures, the ROB in Linx Instruction Set Architecture utilizes the unique blocking mechanism of the structured instruction set, thereby enabling the hardware to simultaneously exploit two dimensions of parallelism during program execution, namely inter-block parallelism (Block Parallelism) and intra-block parallelism (Instruction Parallelism). At the same time, it ensures the accurate status and correctness of the program when blocks are issued out of order, and when microinstructions within the blocks are issued out of order.
+
+Corresponding to the microarchitecture level, structured ROB is divided into two levels: block ROB and microinstruction ROB. Through this layered mechanism, the hardware can decouple blocks from the sequential commit of instructions. That is, since the intra-block microinstructions will only affect the architectural state within the block when executed, and will not affect the external architectural state, the microinstruction ROB only needs to ensure the submission order within the block, while the submission order between blocks will be guaranteed by the superior block ROB. As a result, the microinstruction ROB can submit the oldest microinstructions from different blocks at the same time, thereby achieving the effect of out-of-order submission without affecting the accuracy of architectural state. At the same time, since instructions do not need to be submitted in order, the microinstruction ROB hardware resources can be released in advance, which means that the speculative depth of the ROB is greater than the actual depth, thereby releasing greater parallelism.
+
+It should be noted that this design does not break the computing paradigm of sequential submission, but uses the layered mechanism of the structured instruction set to complete the submission marking of multiple blocks, resulting in the effect of out-of-order submission.
+
+# PE ROB
+The microinstruction ROB is a key module that ensures that microinstructions belonging to the same block are submitted sequentially. It only needs to ensure the execution order within the block, and does not need to ensure that the programs between blocks are also submitted in order. The order submission between blocks will be guaranteed by the superior block ROB. If some microinstructions in multiple blocks have been completed, the microinstructions in these blocks can be submitted in order. When all instructions in a block are submitted, the corresponding entry in the superior block ROB is marked as completed.
+
+Based on the above rules, the most reasonable implementation is to implement the microinstruction ROB as a linked list structure, and have an additional BICT (Block Instruction Commit Tracker) module record the execution of each block.
+
+## Microinstruction ROB table entry structure
+
+
+
+As shown in the figure above, the microinstruction ROB is composed of M slices. Each slice is a block of a ROB and contains K instructions. Each slice can be connected at will through the head and tail pointers to form a linked list structure, which can store a total of M*K instructions. Each slice has the following domain segments:| Field segment | Description |
+| ----------- | --------------------------------------------------------------- |
+| Valid bit | Indicates that the piece is valid and occupied |
+| Wrap bit | Indicates whether the block number wraps around, used to compare the old and new numbers |
+| Head and tail pointers | Indicate the connection relationship of the piece. Only the same block will have pointer connections |
+| Block number | Indicates the sequential number of the block to which the slice belongs |
+| slice number | indicates the sequence number of the slice in the block it belongs to |
+| Block start mark | Indicates that the slice is the first slice of the block |
+| Block end mark | Indicates that the slice is the last slice of the block |
+| Instruction status *K | Each slice can store the status of K instructions. The status includes complete, exception, exception type and other information |
+
+
+## BICT (Block Instruction Commit Tracker) structure
+Since the superior block ROB maintains N header, at most N blocks in the microinstruction ROB are executed at the same time. During execution, each block will be submitted in sequence, and the microinstruction ROB will process submissions from multiple blocks at the same time. In order to ensure the correctness when multiple blocks are submitted at the same time, the hardware also needs to maintain a tracking module BICT to track the submission progress of each block.
+BICT is a stack with a depth of N. Each item in it records the execution status of the corresponding block. It has the following field segments:
+
+| Field segment | Description |
+|---------------------|---------------------------------|
+| Valid bit | Indicates that the entry is valid and occupied |
+| Block number | Indicates the block number corresponding to this entry |
+| The oldest slice pointer of the block | Indicates the position of the oldest slice of the block in the microinstruction ROB |
+
+ ## Microinstruction ROB operation
+### Command entry
+When the upstream module provides a new block, the microinstruction ROB will select a block from the currently free slice, record the currently entered multiple or one microinstruction information into the slice, and mark the fragment as the starting point of the block. In addition, each slice also maintains a write pointer. If the instruction does not fill the K instruction slots, the instruction write pointer of the slice is updated to the next instruction slot to facilitate subsequent continuous writes with the same block instruction. At the same time, the microinstruction ROB will maintain a counter. When the counter is full, it will backpressure the upstream module to prevent the microinstruction ROB from not having enough space to write new blocks.
+When the instruction provided by the upstream module belongs to the same block as the instruction entered in the previous clock cycle, the instruction information can be continued to be written to the slice written in the previous clock cycle. If the number of currently entered instructions exceeds the recording capacity of the current slice, you need to apply for a new free slice to write instructions that exceed the capacity, and update the instruction write pointer of the slice at the same time. In addition, the hardware will also update the head pointer of this slice to the number of the previous slice, and update the tail pointer of the previous slice to the number of this slice.
+### Command update
+When the instruction execution is completed, the status of the instruction in the microinstruction ROB will be updated according to the instruction number. If the instruction is executed normally and completed, the instruction will be updated to the completion status. If the instruction encounters exception during execution, the hardware will update the exception and exception type status of the instruction.
+### Command dequeue
+For each instruction in the microinstruction ROB, it can be dequeued as long as it is the last instruction of its block and is marked as a normal completion status. However, since each slice can only be occupied by one block, as long as all the instructions in the slice are not completed, other blocks cannot occupy the block in advance. At the same time, for simplicity of design, the microinstruction ROB can choose to kick out a slice at the same time, that is, bind K instructions together and queue them up. At the same time, the microinstruction ROB does not need to guarantee the sequential submission of blocks, so the hardware allows multiple slices to be kicked out at the same time.
+When all instructions of a block have been dequeued (that is, when a slice with an end mark is dequeued), the microinstruction ROB will notify the superior block ROB of a signal that the block has been completed.
+### Command to flush out
+When encountering an external exception or interrupt, the microinstruction ROB will find instructions younger than the number and flush them out based on the block number and instruction number of the flush instruction provided by the upstream. At the same time, according to the flushing situation, the valid bit of each slice, the instruction write pointer, and the valid bit of each block in BICT are updated in time.
\ No newline at end of file
diff --git a/docs/backend/scheduler.md b/docs/backend/scheduler.md
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+# Dispatch unit (PE Dispatch)
+The dispatch unit will send the decoded instructions to ISQ and ROB at the same time. A maximum of four microinstructions can be issued per beat, and the dispatch unit will allocate them to different ISQs according to different instruction types. At the same time, for instructions of the same type, the microarchitecture will dispatch microinstructions according to the remaining vacancies of each ISQ.
+
+The ISQs that need to be allocated in the micro-architecture are as follows:
+
+| ISQ Type | Number |Depth| Calculation Category|
+| --| --- | ---|--|
+|ALU 0| 1 | 8|General computing class|
+|ALU 1| 1 | 8|General computing class|
+|GSU | 2 | 8|PC Computing and Inter-Block Communication Category|
+|LSU |2| 8|Memory access class|
+
+
+
+
+Take the ALU instruction as an example: (Note: GSU instructions and LSU instructions apply to the same distribution rules)
+
+The ALU transmission queue has two banks, ALU0 and ALU1. In the same clock cycle, up to four instructions can be written to these two banks. Assume that Free0 Free1 is the number of vacancies in the two banks of ALU0/1, and Instr0 Instr1 Instr2 Instr3 is the four instructions of the same shot and type, and the program sequence is from old to new. Where Instr0 has a higher probability of being valid than Instr1, and so on Instr0 >= Instr1 >= Instr2 >= Instr3. Based on the above conditions, instructions with a high probability of validity are given priority to banks with many vacancies. The details are as follows:
+
+|Rules |ALU 0 Enqueue |ALU1 1 Enqueue|
+|--|--|--|
+|Free0 >= Free1 (the vacancy of ALU0 is greater than or equal to ALU1) |Instr0 Instr1 |Instr2 Instr3|
+|Free0 < Free1 (ALU0 has less space than ALU1) |Instr2 Instr3| Instr0 Instr1|
\ No newline at end of file
diff --git a/docs/background/index.md b/docs/background/index.md
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+# What are LinxISA and block instruction?
+
+LinxISA is a general-purpose computing instruction set that combines scalar, floating-point, vector, system, and customizable operation forms under one architectural framework.
+Under the LinxISA framework, implementers can extend instructions and system design choices around a common programming model instead of maintaining completely separate machines.
+
+LinxISA is positioned as the core computing infrastructure in the era of artificial intelligence. It aims to cover the three computing modes of scalar (Scalar), vector (Vector) and tensor (Tile) with a unified instruction set, integrate SIMD and SIMT execution paradigms, and open up the boundary between AI and graphics rendering tasks.
+
+By building a native parallel execution architecture centered on block instruction, LinxISA achieves a more versatile and scalable computing instruction system than NVIDIA PTX.
+
+Our goal is to design a new, autonomous and controllable, completely different, and technically competitive ISA from scratch.
+
+From the perspective of instruction set architecture, LinxISA is a technically differentiated instruction set design that is significantly different from x86/ARM/RISC-V.
+
+The processor built on LinxISA is called "Linx processor". Relying on its unique instruction architecture design, Linx processor not only has outstanding advantages in performance, chip area and energy efficiency, but also can effectively avoid intellectual property and patent risks, thereby achieving complete autonomy in chip design.
+
+## Introduction to Linx block instruction
+
+Linx block instruction is the core structured-execution concept in LinxISA.
+
+block instruction combines a set of semantically related and tightly operated micro-instructions into a complete "instruction block" to uniformly define the overall input and output, representing a small task (micro-task) that can be scheduled independently. In many computing scenarios, the instruction block can be equivalently expressed as a tensor calculation (micro-kernel), such as a matrix multiplication, convolution kernel or normalization operation. This "block-based" packaging method not only helps the hardware execute complex operators more efficiently, but also increases the optimization space of the compiler and executor.
+
+
+ { width="800" }
+
+
+The compiler emits block-structured binary code on the software side; on the hardware side, the processor no longer has to treat the program as only a flat instruction stream, but can execute the block as a structured unit.
+
+block instruction combines a set of associated microinstructions into a complete "instruction block" and uniformly defines the overall input and output of the block. The compiler compiles the program into binary code in the form of block instruction on the software side; on the hardware side, Linx processor no longer executes the program in the traditional instruction-by-instruction manner, but executes it as a whole according to block instruction.
+
+## Why block instruction is easier to obtain performance improvements
+
+The block instruction set is a hierarchical instruction set with first- and second-level register states. The block instruction dependency and compiler allocation algorithm expresses the entire program hierarchy and defines shared variables and private variables from the instruction level. Linx processor parses and executes the program concurrently according to the two asynchronous pipelines of **header-body**.
+
+{ width="800" }
+
+The core of block instruction performance gains are:- Block Level Parallelism: Linx processor can achieve parallel execution at a higher level and achieve significant performance improvements.
+- Instruction blocks can be regarded as independent computing tasks, achieving "small task" level parallelism within a single core of Linx processor.
+- header and body are separated to realize the decoupling of jump control and actual calculation, improving execution efficiency.
+- Hierarchical register management, the hardware can efficiently allocate and reclaim register resources.
+
+## block instruction: Improve instruction set expression granularity
+
+Overall plan: We use block instruction to improve the granularity of instruction information density. block instruction has a **scope** of additional information. Each instruction no longer expresses a single operation, but a series of operations that are expressed as a block of instructions and make modifications to the system atomically.
+
+However, inside block instruction, we have a simple fixed-length RISC instruction set.
+
+{ width="800" }
+
+
+Compared with the traditional instruction set, block instruction expresses more information, including:
+
+- **Dependencies between instructions within a block**: Through efficient coding, the instruction dependency graph within a block is directly transferred to the micro-architecture. The micro-architecture no longer needs to use complex algorithms to resolve dependencies, reducing the complexity of the micro-architecture.
+
+## block instruction: Hierarchical instruction set
+
+We encapsulate the heterogeneous and accelerated parts into block instruction and express them at different abstract levels, so that under a common framework, new acceleration units can be enabled under the same programming framework.
+
+
+ { width="800" }
+
+- **Fully customized second-layer architecture**: The second-layer instruction set has independent coding space, register and instruction definitions. Extremely scalable. At the same time, it does not affect the first layer architectural state of block instruction. The product line has the ability to customize instructions without destroying the architecture of the hierarchical instruction set.
+- **Private and Shared Registers**: Through the representation of the block instruction range, the compiler can express the first and second layers of architectural register and pass this information directly to the hardware. Through the allocation and management of two-layer registers, hardware implementation overhead is greatly reduced.
+- **Semantic Scope**: If multiple instructions are combined as a whole, the internal complexity and external complexity are decoupled through the interface. No matter how complicated the Scope is, it will not affect the logical operations outside the Scope. With this information, we can mark a range of instructions, thereby improving the information entropy of instruction marking and providing a more efficient interface for instruction prompt information.
+
+## History of block instruction
+
+The concept of LinxISA was not imagined from scratch, but derived from the existing block instruction set.
+
+Among them, the design of the instruction set of LinxISA mainly comes from this paper from Stanford University:
+
+- [BLISS: Block-Aware Instruction Set Architecture (2006)](https://dl.acm.org/doi/abs/10.1145/1162690.1162694)
+
+LinxISA CPU hardware implementation also mainly uses some data inspiration from the EDGE instruction set. The design concept of the EDGE instruction set originated from the data stream processor in the 1970s. The core point is to execute a series of instructions in the form of a block. The inside of the block is expressed by the dependency graph between instructions, while the outside of the block is still expressed in the traditional controlflow (jump) way.
+
+Regarding the design of the EDGE instruction set, you can refer to the following papers:
+
+- [Scaling to the End of Silicon with EDGE Architectures](https://www.cs.utexas.edu/users/cart/trips/publications/computer04.pdf)
+
+- [Exploiting ILP, TLP and DLP with the Polymorphous TRIPS Architecture](https://www.cs.utexas.edu/users/cart/trips/publications/isca03.pdf)- [TRIPS Reference Manual](https://www.cs.utexas.edu/users/cart/trips/publications/TR-05-19.pdf)
+
+## Why is block instruction designed like this?
+
+For a detailed comparison between block instruction and traditional ARM/RISC-V instructions, please see [block instruction Design Philosophy](./phil.md)
\ No newline at end of file
diff --git a/docs/background/phil.md b/docs/background/phil.md
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+# Imported Placeholder
+
+This compatibility page is retained so older internal references continue to resolve while the standalone manual structure stays stable.
diff --git a/docs/bcc/bdecode.md b/docs/bcc/bdecode.md
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+# Block parsing unit (Block Decode)
+
+The block parsing unit is mainly responsible for parsing a 128-bit block instruction retrieved by the BFU, and obtaining the input, output, microinstruction code offset, block type, block characteristics and other information. This information will be used in its downstream modules.
+
+## BlockID generation
+
+Since the Block ROB is divided into each PE, the micro-architecture needs to set up a centralized module in the parsing unit to generate a globally continuous Block ROBID and pass it to the downstream and each PE.
\ No newline at end of file
diff --git a/docs/bcc/bdispatch.md b/docs/bcc/bdispatch.md
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+# BlockDISPATCH
+The Block Dispatch module is responsible for distributing BFU-predicted blocks to different PEs. The distribution rules are affected by the following factors:
+
+* Type-related: Based on the type of the block, send the block to the appropriate PE
+* Dependency related: If the instruction block has multiple PEs to choose from, it will be sent first to the PE where the block with the highest dependency correlation is located.
+* Load related: If the instruction block has multiple PEs to choose from, priority will be given to the PE with the smallest load, that is, the one with the smallest number of blocks being executed in BISQ
\ No newline at end of file
diff --git a/docs/bcc/bhcache.md b/docs/bcc/bhcache.md
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+# header Cache (Block Header Cache, BHC)
+
+The header cache is a first-level cache used to temporarily store Block Header. It is consistent with the L1 Cache in the processor. They are hardware that improves memory access efficiency by utilizing spatial locality and time locality. Since the overall architecture of BFU adopts a different approach from the traditional coupling prediction and instruction fetching, BHC is also used as BTB. BHC does not currently support Hit Under Miss, that is, when a Cache Miss is encountered, subsequent requests will be blocked.
+
+## header cache configuration
+
+* header cache capacity is 64KB, Cacheline granularity is 64B
+* Data Array supports 4 Way group associative structure. Each way has 8 single-port SRAMs, divided into 4 qwords and 8 dwords. The SRAM depth is 256 and the width is 78bit.
+* Tag Array is a single-port SRAM with a depth of 256 and a bit width of 49 bits.
+* Write operations are not supported yet. The only write operations come from Cacheline Fill.
+* VIPT, Virtual Index Physical Tag
+* ECC detection, 1-bit error self-correction, 2-bit error reporting exception
+
+
+## DATA Array reading process
+
+Data Array is divided into two paths: reading and writing. Among them, the data of the write port comes from L2 cache data backfill; the data of the read port comes from the read request of BFU; after reading the data from the Data Array, ECC judgment will be performed, and if an error occurs, the exception signal will be reported. The main processing flow is as follows:
+* In the I2 pipeline, prepare data for reading and writing, and generate enable, address and other signals. For write operations, the data source is L2 data backfill. The hardware will generate write enable, address, write mask and other signals based on the backfill signal. For read operations, the signal source is BFU. The hardware will calculate the data selection and address signals for the read operation based on the input address.
+* In the e1 stage, data read and write operations are implemented. When writing data, the ecc data and data data from fill are written into memory in order; when reading data, since there are 4 ways in total, each way has 4 qwords, and each qword includes two dwords, a total of 32 data will be read. The read data is read out at the e2 stage.
+* In the e2 stage, first each way will select d0 and d1 data from the 8 result data read out by this way based on the qword_en signal. A total of 8 data will be selected for the four ways, and then the d0 and d1 data of a certain way will be selected based on the way_hit signal obtained from the tag.
+* In the e3 stage, perform ecc_err detection on the selected pipe data, and output the err signal and correct_data.
+
+
+## PLRU algorithm
+
+Plru (Partial Least Recently Used) is an algorithm based on lru (Least Recently Used). This module uses the Tree-plru algorithm. The specific implementation is as follows:
+Taking a 4-way cache as an example, 3 status bits need to be set: lvl1_node, lvl2_left, lvl2_right. The initial state is all 0, corresponding to 4 Ways respectively. The corresponding situation is shown in the figure below:
+
+{ width="400" }
+
+When a Fill operation occurs to determine the replacement of Way, the value of lvl1_node is first read, and based on the result, it is decided to continue to determine lvl2_left or lvl2_right. If the value of lvl1_node is 0, read the value of lvl2_left and ignore lvl2_right; if the value of lvl1_node is 1, read the value of lvl2_right and ignore lvl2_left, thereby selecting the replacement Way number. After replacing Way, the status of the three nodes will be updated. In addition to the replacement operation, when a Way hits, the status of the three nodes also needs to be updated.According to the above analysis, it can be seen that when the Fill operation initially occurs, since lvl1_node is 0, the value of lvl2_left will be read, and lvl2_left is also 0, so Way0 is selected for the data writing operation. In the next beat, as data is written to Way0, the status of the three nodes will be updated. The update rules are as follows:
+
+ For lvl1_node, when Way0/1 is selected, set it to 1, and when Way2/3 is selected, set it to 0;
+ For lvl2_left, when Way0 is selected, set it to 1, when Way1 is selected, set it to 0, and keep the other conditions;
+ For lvl2_right, when Way2 is selected, set it to 1, when Way3 is selected, set it to 0, and keep the other conditions;
+
+After the update, the node status is as follows:
+
+{ width="400" }
+
+When a fill operation occurs on this basis, way2 will be selected to write data and update the node status.
\ No newline at end of file
diff --git a/docs/bcc/bifu.md b/docs/bcc/bifu.md
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+# BFU
+
+Block Fetch Unit (BFU) is a module used to fetch Block Header. It is divided into two parts: ISIDE and BSIDE are used for instruction reading and next address prediction respectively. This chapter mainly introduces the ISIDE part, and the BSIDE part will be introduced separately in the [BP](./bp.md/) chapter.
+
+Different from the traditional RISC instruction set, each instruction in LinxISA has a jump attribute, which means that BFU can default to each block instruction as a jump instruction. This feature enables corresponding simplification of the microarchitecture. At the same time, because the block instruction encoding length is relatively long at 128-bit, the microarchitecture currently only fetches one instruction per clock cycle, so part of the prediction logic can be simplified.
+
+## Block jump type
+
+In order to improve the accuracy of prediction, BFU uses five-level pipeline prediction to handle different jump types. These types include:
+
+| Type | Explanation | Assembly flag |
+|---------------|----------|------------|
+| Fall Through | Postponement | bnext.fall |
+| Direct Jump | Direct jump | bnext.direct |
+| CALL | Call jump | bnext.call |
+| Conditional Jump | Conditional Jump | bnext.cond |
+| Indirect | Indirect jump | bnext.ind |
+| Indirect Call | Indirect call | bnext.indcall |
+| Return | Return | bnext.ret |
+| ECall | exception call | bnext.ecall |
+| EReturn | exception return | bnext.eret |
+
+## BFU overall architecture diagram
+
+The picture below shows the work pipeline diagram of BFU.
+
+ { width="800"){ width="800" }
+
+## ISIDE (Instruction Side)
+As shown in the figure, BFU is divided into two streams: iside and bside. The Iside part includes L1 ICache, Pre_decode and Static Predictor modules. The functions of each module are as follows:
+
+*ICache
+Read the stored data in L1 according to the input physical address. The tag determines whether it is a hit. If it is not a hit, a refill request is sent to L2 to rewrite the data. If it is a hit, the data is read out from the data. After the data is read, the pre_decode module parses to obtain the jump attribute of the block, and the static predictor module parses to obtain the offset from the next block (BNEXT offset) carried by the current header and the size of the current block (BSize), thereby calculating and predicting the BPC of the next block.
+
+* block instruction pre-decode (Pre-decode)
+Pre-decoding decodes the 128-bit block instruction obtained from the header cache to obtain jump type, jump offset and other information, and calculates the target address of the direct jump instruction for subsequent branch prediction checkers to determine the correctness of the prediction.
+
+* Static branch predictor (Static Predictor) and branch prediction checker
+ After fetching the instruction, the static branch checker will get some accurate information, including the jump type and the address of the direct jump. After getting this information, the prediction check module mainly checks the following errors:
+
+ **Direct/indirect jump instruction prediction does not jump error:** Check for instructions that must jump such as Direct/Indirect/Call/Indirect/Ret. If the prediction unit encounters such a block and predicts that it will not jump, it is regarded as a prediction error.**Target address error:** For jump instructions (such as Direct, Call, Fall Through, Concat) whose target address can be known through the instruction code, if the predicted address does not match the correct address, it is considered a prediction error.
+ After an error is found, the branch prediction checker will generate the SP Flush signal, clear the pipeline related signals, and restart fetching and prediction from the correct address.
+
+## BSIDE (Branch Prediction Side)
+* uBTB
+Provides fast prediction of 0-cycle jump direction, jump target address, and jump attributes.
+
+*RAS
+The return address stack RAS is essentially similar to a circular buffer, used to predict and track call (also called push, push on the stack) and return (also called pop, pop out of the stack) instruction pairs, and store return addresses. Each RAS entry has two field segments: backlink and target. The backlink field stores the top of stack pointer TOS corresponding to each execution of the call instruction, and the target field stores the target address (VA) given each time the return instruction is executed. If RAS predicts a call (push) instruction every time, a return address will be stored in RAS; if RAS predicts a return (pop) instruction every time, a return address will be popped out of RAS;
+
+{ width="800" }
+
+Figure: Schematic diagram of RAS microarchitecture
+
+*GHR
+It is used to store the final prediction result of each beat jump instruction (jump/no jump), and predict a new GHR value and IHR value based on the past results, and send them to the TAGE and ITBB modules for hash operation respectively to calculate the folded query sequence number and corresponding to the correct jump.
+
+*TAGE
+Used to predict jump directions. There are four prediction tables (numbered 0~3) and one base table. Each entry in each table stores direction predictions for different jumps. Each table is indexed by a different sequence number, where the sequence number is calculated by hashing the global jump history and the PC of the current block. Tables with larger numbers will add longer jump history for hashing, so they are more accurate.
+
+*iBTB
+In the F2 stage of the pipeline, if the pre_decode module on the iside side parses and obtains that the jump attribute of the block is an indirect jump type (including indirect jump INDIR and indirect call INDCALL), a more accurate predicted target address will be provided in iBTB.
+
+* PRED predicts internal competition logic
+In the F3 stage of the pipeline, the main predictor PRED will produce the final and most accurate prediction information of the entire BFU module. There are three types of prediction information: block jump type, block jump direction, and block jump target address.
+For block jump types, the block jump type obtained by the static predictor by parsing header is the most accurate, so the block attributes are directly passed to the main predictor (PRED) module for final prediction.
+For the block jump target address, the block jump target address obtained by the static predictor by parsing header can only be trusted under certain circumstances, that is, when the block jump type is FALL, DIRECT, CONCAT, CALL, COND, the correct jump target address can be obtained by parsing header. In other cases, the target address obtained by the static predictor is not trustworthy. If it is the RET type, the result obtained by RAS two beats after the F1 stage prediction is the most credible; if it is the INDIRECT or INDCALL type, the result obtained by iBTB is the most credible; otherwise, the result obtained by uBTB is used.
+For the block jump direction, if it is CONDblock type, the prediction result of TAGE is used; if block type is FALL or CONCAT type, it is regarded as not jumping, and the other cases are regarded as jumps.
+
+*BRQ
+The branch queue BRQ is essentially similar to a FIFO, which is used to store the real-time running information of the branch predictor and serve as a basis for the update and recovery of the branch predictor when necessary (such as mis-predict, etc.).
+
+{ width="800" }Figure BRQ_TOP module architecture block diagram
+The data in each entry of BRQ is wide. We need to get different parts of an entry under some different conditions (Rob refreshed/Bru refreshed/BRQ parsed correctly) and roll it over to the next cycle. As shown below, "√" means that the field will be read in this case:| BRQ ENT GRP | BRQ ENT Field | rob_flush | bru_flush | Bru correct resolve | width | start bit | end bit |
+| ----------- | ------------- | --------- | --------- | ----------- | ----- | --------- | ------- |
+| GHR | GHRQ_RIDX | √ | √ | √ | 8 | 0 | 7 |
+| IHR | BASE | √ | √ | √ | 12 | 20 | 27 |
+| TAGE | StartPos | | √ | √ | 3 | 8 | |
+| TAGE | STR | | √ | √ | 1 | 11 | |
+| TAGE | TNT | | √ | √ | 1 | 19 | |
+| TAGE | U_b3w0 | | √ | √ | 2 | 21 | |
+| TAGE | CTR_b3w0 | | √ | √ | 2 | 23 | |
+| TAGE | POS_b3w0 | | √ | √ | 2 | 25 | |
+| TAGE | HIT_b3w0 | | √ | √ | 1 | 26 | |
+| TAGE | U_b2w0 | | √ | √ | 2 | 28 | |
+| TAGE | CTR_b2w0 | | √ | √ | 2 | 30 | |
+| TAGE | POS_b2w0 | | √ | √ | 2 | 32 | |
+| TAGE | HIT_b2w0 | | √ | √ | 1 | 33 | || TAGE | U_b1w0 | | √ | √ | 2 | 35 | |
+| TAGE | CTR_b1w0 | | √ | √ | 2 | 37 | |
+| TAGE | POS_b1w0 | | √ | √ | 2 | 39 | |
+| TAGE | HIT_b1w0 | | √ | √ | 1 | 40 | |
+| TAGE | U_b0w0 | | √ | √ | 2 | 42 | |
+| TAGE | CTR_b0w0 | | √ | √ | 2 | 44 | |
+| TAGE | POS_b0w0 | | √ | √ | 2 | 46 | |
+| TAGE | HIT_b0w0 | | √ | √ | 1 | 47 | |
+| RS | TOS | √ | √ | | 6 | 53 | |
+| RS | WPTR | √ | √ | | 6 | 59 | |
+| IBTB | HIT_BNK | | √ | √ | 2 | 61 | 62 |
\ No newline at end of file
diff --git a/docs/bcc/bp.md b/docs/bcc/bp.md
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+++ b/docs/bcc/bp.md
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+## BSIDE (Branch Prediction Side)
+
+* uBTB
+Provides fast prediction of 0-cycle jump direction, jump target address, and jump attributes.
+
+*RAS
+The return address stack RAS is essentially similar to a circular buffer, used to predict and track call (also called push, push on the stack) and return (also called pop, pop out of the stack) instruction pairs, and store return addresses. Each RAS entry has two field segments: backlink and target. The backlink field stores the top of stack pointer TOS corresponding to each execution of the call instruction, and the target field stores the target address (VA) given each time the return instruction is executed. If RAS predicts a call (push) instruction every time, a return address will be stored in RAS; if RAS predicts a return (pop) instruction every time, a return address will be popped out of RAS;
+
+{ width="800" }
+
+Figure: Schematic diagram of RAS microarchitecture
+
+*GHR
+It is used to store the final prediction result of each beat jump instruction (jump/no jump), and predict a new GHR value and IHR value based on the past results, and send them to the TAGE and ITBB modules for hash operation respectively to calculate the folded query sequence number and corresponding to the correct jump.
+
+*TAGE
+Used to predict jump directions. There are four prediction tables (numbered 0~3) and one base table. Each entry in each table stores direction predictions for different jumps. Each table is indexed by a different sequence number, where the sequence number is calculated by hashing the global jump history and the PC of the current block. Tables with larger numbers will add longer jump history for hashing, so they are more accurate.
+
+*iBTB
+In the F2 stage of the pipeline, if the pre_decode module on the iside side parses and obtains that the jump attribute of the block is an indirect jump type (including indirect jump INDIR and indirect call INDCALL), a more accurate predicted target address will be provided in iBTB.
+
+* PRED predicts internal competition logic
+In the F3 stage of the pipeline, the main predictor PRED will produce the final and most accurate prediction information of the entire BFU module. There are three types of prediction information: block jump type, block jump direction, and block jump target address.
+For block jump types, the block jump type obtained by the static predictor by parsing header is the most accurate, so the block attributes are directly passed to the main predictor (PRED) module for final prediction.
+For the block jump target address, the block jump target address obtained by the static predictor by parsing header can only be trusted under certain circumstances, that is, when the block jump type is FALL, DIRECT, CONCAT, CALL, COND, the correct jump target address can be obtained by parsing header. In other cases, the target address obtained by the static predictor is not trustworthy. If it is the RET type, the result obtained by RAS two beats after the F1 stage prediction is the most credible; if it is the INDIRECT or INDCALL type, the result obtained by iBTB is the most credible; otherwise, the result obtained by uBTB is used.
+For the block jump direction, if it is CONDblock type, the prediction result of TAGE is used; if block type is of FALL, CALL, CONCAT type, it is regarded as not jumping, and the other cases are regarded as jumps.
+
+*BRQ
+The branch queue BRQ is essentially similar to a FIFO, which is used to store the real-time running information of the branch predictor and serve as a basis for the update and recovery of the branch predictor when necessary (such as mis-predict, etc.).
+
+{ width="800" }
+
+ Figure BRQ_TOP module architecture block diagram
+The data in each entry of BRQ is wide. We need to get different parts of an entry under some different conditions (Rob refreshed/Bru refreshed/BRQ parsed correctly) and roll it over to the next cycle. As shown below, "√" means that the field will be read in this case:| BRQ ENT GRP | BRQ ENT Field | rob_flush | bru_flush | Bru correct resolve | width | start bit | end bit |
+| ----------- | ------------- | --------- | --------- | ----------- | ----- | --------- | ------- |
+| GHR | GHRQ_RIDX | √ | √ | √ | 8 | 0 | 7 |
+| IHR | BASE | √ | √ | √ | 12 | 20 | 27 |
+| TAGE | StartPos | | √ | √ | 3 | 8 | |
+| TAGE | STR | | √ | √ | 1 | 11 | |
+| TAGE | TNT | | √ | √ | 1 | 19 | |
+| TAGE | U_b3w0 | | √ | √ | 2 | 21 | |
+| TAGE | CTR_b3w0 | | √ | √ | 2 | 23 | |
+| TAGE | POS_b3w0 | | √ | √ | 2 | 25 | |
+| TAGE | HIT_b3w0 | | √ | √ | 1 | 26 | |
+| TAGE | U_b2w0 | | √ | √ | 2 | 28 | |
+| TAGE | CTR_b2w0 | | √ | √ | 2 | 30 | |
+| TAGE | POS_b2w0 | | √ | √ | 2 | 32 | |
+| TAGE | HIT_b2w0 | | √ | √ | 1 | 33 | || TAGE | U_b1w0 | | √ | √ | 2 | 35 | |
+| TAGE | CTR_b1w0 | | √ | √ | 2 | 37 | |
+| TAGE | POS_b1w0 | | √ | √ | 2 | 39 | |
+| TAGE | HIT_b1w0 | | √ | √ | 1 | 40 | |
+| TAGE | U_b0w0 | | √ | √ | 2 | 42 | |
+| TAGE | CTR_b0w0 | | √ | √ | 2 | 44 | |
+| TAGE | POS_b0w0 | | √ | √ | 2 | 46 | |
+| TAGE | HIT_b0w0 | | √ | √ | 1 | 47 | |
+| RS | TOS | √ | √ | | 6 | 53 | |
+| RS | WPTR | √ | √ | | 6 | 59 | |
+| IBTB | HIT_BNK | | √ | √ | 2 | 61 | 62 |
\ No newline at end of file
diff --git a/docs/bcc/bren.md b/docs/bcc/bren.md
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+# Block Rename Unit (Block Rename, BREN)
+
+The block renaming unit is a key component within OOO. It is split into multiple copies and placed in each PE Tile. It is responsible for mapping block architectural register to block physical registers. It can be used to eliminate WAW and WAR competition risk scenarios and improve out-of-order execution efficiency. The block renaming unit will process the input/output domain segment of block instruction. For the output of the block, the block renaming unit will allocate a free physical register for each output register. For the input of a block, the block renaming unit will query its internal speculative map (SMAP) to obtain its corresponding mapping. Different from other processors, the block renaming unit in Linx Instruction Set Architecture adopts a distributed structure to decouple the mapping synchronization problem between different PEs. This chapter mainly introduces the Mask Select, Rename, Physical Register File Mapping Table, Freelist and other modules.
+
+## Architecture block diagram
+{ width="800" }
+
+
+## Mask Select module (Mask Select)
+
+Different from other instruction sets, block instruction of LinxISA has multiple input/output, expressed in two 32-bit Bit Maps. The mask selection module unit is responsible for selecting the corresponding registers from these two 32-bit vector and providing them to subsequent hardware execution. The mask selection module processes input and output independently and in parallel, and each is controlled by the back pressure of the subsequent module. Currently, it supports 4 outputs per beat to allocate free physical registers, and 4 inputs per beat to query mapped physical registers. At the same time, only inputs and outputs from the same block are selected each clock cycle.
+
+
+## Speculative Map Table (SMAP)
+
+The speculative mapping table records the physical mapping of all architectural register and the latest architectural state currently seen in this PE**, refreshes the mapping relationship between architecture and physical registers in real time, and allows new input to query its latest physical register mapping. Its format is as follows:
+
+|architectural register number|corresponds to the latest physical register number|
+|-----|-----|
+|G0|P2|
+|G1|P4|
+|...|...|
+|G31|P42|
+
+For the output of the block, it will update the physical register allocated from the Free List into SMAP every clock cycle, and the allocated mapping relationship will also be recorded in SET PRFT. For the input of the block, the hardware will obtain the mapping relationship of the physical register by querying SMAP, and the queried mapping relationship will also be recorded in GET PRFT.
+
+
+
+## Committed Map Table (CMAP)
+
+The latest non-speculative architectural state is recorded in the submission mapping table to provide backup for possible rollback operations in the future. It is consistent with the data format of SMAP. When an instruction is Commit, PRFT will synchronize the mapping relationship output by the instruction to CMAP. At the same time, the physical registers replaced by updates in CMAP will be recycled to Freelist for subsequent output allocation. In the initial state, CMAP will be assigned a fixed mapping, that is, P0 corresponds to G0, P1 corresponds to G1, and so on.
+
+## Register map table (Phyiscal Register File Table, PRFT)The register map table is divided into two tables, namely GET PRFT and SET PRFT. SET PRFT contains all architectural register-physical register mapping relationships that have been allocated but have not yet been submitted. GET PRFT contains all architectural register-physical register mapping relationships that have currently been queried but have not yet been submitted. When a block is committed, its mapping is read from SET PRFT and CMAP is updated. If a Flush occurs, the mapping relationship newer than the Flush bid will be flushed in both tables, the physical registers flushed in SET PRFT will be released to Freelist, and the saved CMAP mapping relationship will be read out and help restore SMAP.
+
+### Register map control state machine
+
+The commit and flush pointer maintenance of the register map table is extremely error-prone. Due to the bandwidth limitations of the release map, register map table commit and flush operations require more time than BROB. To prevent mistakes, rules need to be followed: one action ends before another can begin. For the recovery operation of PRFT, the flushing and submitting behaviors cannot coexist, that is, the flushing behavior and the recovery operation coexist in the same clock cycle. For BROB, it is in a waiting state until the register map table completes the submission and flushing operations, and then performs the flushing action.
+
+The register map controls the working status through the state machine. When the BROB commits, the state machine enters the "Commit" state and commits the mapping relationship starting from the commit pointer until the BlockID of its mapping instruction reaches the commit BlockID of the BROB. If a Flush scenario occurs, the state machine will enter the "Rebulid" state and restore the mapping relationship to SMAP starting from the commit pointer, and at the same time release the mapping that was flushed from the allocated pointer to Freelist.
+
+## Physical register free list (Freelist)
+
+All physical register codes are maintained in a Freelist. Each clock cycle, the hardware will allocate up to 6 free physical registers from the free list to the Free FIFO. At the same time, the output will also select 6 free physical registers from the Free FIFO for allocation. There are two sources of free registers. One is the physical register that is flushed out of PRFT in the Flush scenario, and the other is the physical register that is replaced after being submitted from CMAP.
+
+
+{ width="800" }
+
+
+## Distributed renaming module
+
+In order to avoid possible layout and routing problems, the entire BCC Backend is distributed among multiple execution engines. There are several benefits to doing this:
+
+1. The output of each PE will only be allocated to the block physical register also located in this PE. Avoiding the routing of physical registers from global allocations.
+2. Since the speculative mapping table only records the latest physical mapping of the local PE block register, rather than the global latest, it avoids the output of each PE to update a global SMAP.
+3. Each clock cycle query from the PE will only access the PRFT of the local PE, thus reducing the number of interfaces on which the PRFT is accessed.
+
+At the same time, the distributed approach also has several disadvantages:
+
+1. The utilization of 64 registers used by a single PE is lower than the utilization of 256 registers used by all PEs.
+2. When a architectural register is allocated by two PEs successively, subsequent PEs need to query the mapping from other PEs, and synchronization cannot be avoided.
+
+For input queries, synchronization issues cannot be avoided. The micro-architecture adopts a compromise solution, that is, for the output, the global SMAP is first synchronized, and then the input will query a global latest mapping, and then store it in the GET PRFT of the corresponding PE. In this way, for each PE, its internal GET PRFT maintains the latest mapping. There are two implementation options for this method:1. Maintain a SMAP for each PE. Each time after the block output is selected, it will be transmitted to all SMAPs at the same time, and the architectural register entry corresponding to the SMAP of the PE to which the block is destined is marked as the latest, and the corresponding entries of the SMAP of other PEs are old. When subsequent block input queries SMAP, multiple mappings of the same architectural register will also be obtained from the SMAPs of multiple PEs at the same time. Then it is aggregated through a GET MERGE module to generate a latest mapping and sent to the GET PRFT of its destination PE. In this way, the micro-architecture finds a latest mapping globally and puts it into the correct PE through aggregation and synchronization. Its architecture diagram is as follows:
+
+{ width="800" }
+
+2. Maintain a global SMAP, so the latest mappings are in one SMAP, thus saving the cost of synchronization.
+
+{ width="800" }
\ No newline at end of file
diff --git a/docs/bcc/brf.md b/docs/bcc/brf.md
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+# Block register file
+
+There are 32 general-purpose register (Block General Purpose Register, GPR) defined in Block ISA, from R0 - R31. Each register width is 64-bit. These registers are mainly responsible for transferring data between blocks. The architectural state register is defined at the block instruction level and must be accessed through the GET/SET instruction to access the architectural state.
+
+PRF is a 4-distributed architecture, and the block register file is divided into four block register files with a depth of 64, which are allocated to each PE. The block register file within each PE supports 1 write and 4 reads. Because the architecture determines that the SET instruction of this PE will only be written to the block register file of this PE, the writing of the SET instruction will only interact with the local block register file. For each PE's GET, the instruction will access four block register files at the same time, so the reading of the GET instruction will cause complex routing on the microarchitecture.
+
+{ width="800" }
\ No newline at end of file
diff --git a/docs/bcc/brob.md b/docs/bcc/brob.md
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+++ b/docs/bcc/brob.md
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+# Reorder Buffer
+
+In Linx Instruction Set Architecture, the reorder buffer is divided into two parts: Block ROB and PE ROB. The purpose and advantages of its structure will be explained in this chapter. The details of the Block ROB and PE ROB microarchitecture will be explained in this chapter and the [PE ROB] (https://openx.huawei.com/mkdocs/project/1410/blockisa-doc/docs/site/docs/backend/rob/) chapter respectively.
+
+
+## Overview of out-of-order execution
+
+Modern processor architectures usually use out-of-order execution and sequential commit computing paradigms. This paradigm refers to rearranging the execution order of the original ordered instruction list according to instruction dependencies and instruction execution cycles while ensuring consistent results, thereby achieving the purpose of improving performance. However, due to the precise interrupt (Precise Interrupt) that may arrive at any time, the hardware also needs to ensure that the hardware executes all the instructions before interrupt, and the instructions after interrupt are not executed in a precise state. Therefore, after the instructions are executed out of order, another step is added: In-order commit. The method is to cache the impact of the instructions executed out of order on the architecture in the on-chip cache. Then the hardware will sequentially change architectural state according to the order in the reordering buffer.
+
+## Overview of reorder buffer
+
+In the processor architecture, the reordering cache mechanism is a mechanism to achieve sequential submission of instructions and accurate exception, enabling the processor to achieve accurate exception processing and effective hardware speculative execution. The principle can be simply summarized as sequential enqueue and sequential submission (dequeue). This function is usually implemented with a FIFO.
+
+The reordering cache will track the instructions that have been issued in the pipeline, record information such as whether the instruction has been executed, whether it is exception, etc., and sequentially submit the executed instructions, and save the instruction results to the register file or write them into the memory. Uncommitted instructions will wait in the ROB, so the depth of the ROB is the depth of hardware speculative execution. For most programs, greater speculation depth means more opportunities to exploit parallelism, thereby obtaining better performance.
+
+## Disadvantages of existing reorder buffers
+
+As mentioned above, in order to solve a series of problems such as accurate exception, mainstream processors have adopted the sequential submission execution paradigm. However, this paradigm requires instructions to occupy hardware resources until the instruction becomes the oldest instruction before the resources can be released sequentially. At the same time, if the execution time of the oldest instruction is too long, such as the read instruction L3 cache is missing, the instruction will always block the hardware, causing subsequent instructions to be unable to be submitted.
+
+## Linx Instruction Set Architecture Reorder buffer overview
+
+Different from common processor architectures, the structured reorder buffer (ROB) of the present invention utilizes the unique blocking mechanism of the structured instruction set, thereby enabling the hardware to simultaneously mine two dimensions of parallelism during program execution, namely inter-block parallelism (Block Parallelism) and intra-block parallelism (Instruction Parallelism). At the same time, it ensures the accurate status and correctness of the program when blocks are issued out of order, and when microinstructions within the blocks are issued out of order.
+
+Corresponding to the microarchitecture level, structured ROB is divided into two levels: block ROB and microinstruction ROB. Through this layered mechanism, the hardware can decouple blocks from the sequential commit of instructions. That is, since the intra-block microinstructions will only affect the architectural state within the block when executed, and will not affect the external architectural state, the microinstruction ROB only needs to ensure the submission order within the block, while the submission order between blocks will be guaranteed by the superior block ROB. As a result, the microinstruction ROB can submit the oldest microinstructions from different blocks at the same time, thereby achieving the effect of out-of-order submission without affecting the accuracy of architectural state. At the same time, since instructions do not need to be submitted in order, the microinstruction ROB hardware resources can be released in advance, which means that the speculative depth of the ROB is greater than the actual depth, thereby releasing greater parallelism.
+
+It should be noted that the present invention does not break the computing paradigm of sequential submission, but uses the layered mechanism of structured instruction sets to complete the submission marking of multiple blocks, resulting in the effect of out-of-order submission.
+
+In order to ensure the correctness of the program, the hardware needs to ensure in two dimensions:
+
+- header submitted in order
+- Microinstructions within a block are committed in orderIn the microarchitecture, regular ROB is split into two levels: block ROB and microinstruction ROB. The two levels respectively ensure the sequential submission of the above-mentioned different granularities. In addition, block ROB and microinstruction ROB will provide block numbers and instruction numbers respectively. Each instruction in the program has a unique set of block numbers and instruction numbers corresponding to it, so that the hardware can track any instruction.
+
+## Block ROB microarchitecture
+
+Block ROB is an important module that maintains the submission order between blocks. Each item records the execution status of a block. Unlike microinstruction ROB, block ROB does not support simultaneous submission of multiple blocks. Since the submission order of microinstructions within the block is already maintained by the microinstruction ROB, the block ROB only needs to maintain the submission order of the block. Usually, the hardware implements this function through the stack, using a first-in-first-out mechanism to ensure the sequential submission of header.
+
+### Block ROB entry structure
+The implementation of the block ROB is a first-in-first-out stack with a depth of 8, and the entry and exit of the block is maintained through read and write pointers. The specific information recorded is as follows:
+
+| Field segment | Description |
+| -------- | ---------------------------------------- |
+| Valid bit | Indicates that the piece is valid and occupied |
+| Wrap bit | Indicates whether the block number wraps around, used to compare the old and new numbers |
+| Block number | Indicates the sequence number of the block |
+| Completion flag | Indicates whether all instructions in this block have completed execution |
+| exception flag | Indicates whether the block encounters exception during execution |
+| exception type | Indicates the exception type encountered during execution of the block |
+
+
+
+### Block ROB operation
+#### 1. Block entry
+Whenever the upstream module delivers one or more header, the hardware will put header into the stack in order according to the write pointer instructions of the block ROB, record its block number information, and update the write pointer. At the same time, the block ROB will maintain a counter. When the counter is full, it will backpressure the upstream module to prevent the ROB from not having enough space to write new blocks.
+#### 2. Block status update
+If all microinstructions in the block are executed, the microinstruction ROB will report the block ROB and mark the corresponding block as completed. If exception occurs during the execution of a certain microinstruction in the block or a jump prediction error occurs, the hardware will report it to the block ROB and mark the corresponding entry as exception status. If the current oldest instruction is marked as exception, the hardware will report the exception and perform corresponding processing according to the system design.
+#### 3. Block dequeue
+The dequeue of block ROB must comply with the rules of block sequential submission (dequeue). The hardware will indicate the next block to be committed through a commit pointer. Every clock cycle, the hardware will query the execution status of X blocks starting from the commit pointer. The number of X is usually determined by hardware timing, implementation methods and performance indicators. If multiple consecutive blocks have been marked completed, commit them all and move the pointer to the next block to be committed.
\ No newline at end of file
diff --git a/docs/bcc/overview.md b/docs/bcc/overview.md
new file mode 100644
index 00000000..7528afb0
--- /dev/null
+++ b/docs/bcc/overview.md
@@ -0,0 +1,19 @@
+# Block Control Core (BCC)
+
+The block control core is the processing and distribution unit of header. It delivers instruction blocks to each PE out of order, allowing each PE to process different instruction blocks in parallel, thus utilizing inter-block parallelism (Block Parallelism) to the maximum extent. In the block control core, the overall hardware processing is block instruction (Block Header). Like ordinary processors, the block control core is also divided into front and rear ends:
+
+## Block Control Core Frontend Pipeline (BCC Frontend)
+
+It includes block instruction [branch prediction unit] (./bp.md), [fetch unit] (./bifu.md), [decoding] (./bdecode.md), [scheduling unit] (./bdispatch.md), etc. Mainly responsible for fetching instructions header instruction and distributing blocks to appropriate execution engines through algorithms.
+
+## Block Control Core Backend Pipeline (BCC Backend)
+
+It includes [general-purpose register rename] (./bren.md), [reorder cache] (./brob.md), emission pipeline, [general-purpose register heap] (ZXM DLINK6QXZ), [Block Address Cache] (./bhcache.md), [PE Execution Engine] (../pe/ope.md), etc., are responsible for the processing and efficient execution of block instruction.
+
+In order to effectively expand the number of back-end execution engines and effectively reduce hardware wiring costs, the microarchitecture decouples the back-end logic of BCC to each execution engine as much as possible in the block dimension and binds it to the execution engine. The bound structure is called **PE Tile**. Therefore, the architecture presents the structure of an overall block control core front-end pipeline and N block control core back-end pipelines. The details are as follows:
+
+{ width="800" }
+
+## BCC overall pipeline
+
+
\ No newline at end of file
diff --git a/docs/bringup/phases/01_compiler.md b/docs/bringup/phases/01_compiler.md
index f5126e5c..3e1530c3 100644
--- a/docs/bringup/phases/01_compiler.md
+++ b/docs/bringup/phases/01_compiler.md
@@ -13,7 +13,7 @@ In-repo compile validation assets are centralized under AVS:
- Host compiler binary commonly used:
- pinned submodule build: `compiler/llvm/build-linxisa-clang/bin/clang`
- or an external toolchain (set `CLANG=/path/to/clang`)
-- Supported bring-up target on the current in-repo lane: `linx64-linx-none-elf`
+- Supported bring-up target on the current Bisheng branch: `linx64-linx-none-elf`
- The checked-in compiler currently registers `linx64` / `linx64be`; older `linx32` references are archived bring-up history, not an active required gate.
- Compile test suite entrypoint: `avs/compiler/linx-llvm/tests/run.sh`
diff --git a/docs/change_log/isa/blockIntro/inline_block.md b/docs/change_log/isa/blockIntro/inline_block.md
new file mode 100644
index 00000000..991d6135
--- /dev/null
+++ b/docs/change_log/isa/blockIntro/inline_block.md
@@ -0,0 +1,3 @@
+# Imported Placeholder
+
+This compatibility page is retained so older internal references continue to resolve while the standalone manual structure stays stable.
diff --git a/docs/change_log/update_v0.12.md b/docs/change_log/update_v0.12.md
new file mode 100644
index 00000000..56478e15
--- /dev/null
+++ b/docs/change_log/update_v0.12.md
@@ -0,0 +1,2 @@
+# 0.12版本更新
+
diff --git a/docs/change_log/update_v0.13.md b/docs/change_log/update_v0.13.md
new file mode 100644
index 00000000..abd1dff7
--- /dev/null
+++ b/docs/change_log/update_v0.13.md
@@ -0,0 +1 @@
+# 0.12版本更新
diff --git a/docs/change_log/update_v0.16.md b/docs/change_log/update_v0.16.md
new file mode 100644
index 00000000..f1791293
--- /dev/null
+++ b/docs/change_log/update_v0.16.md
@@ -0,0 +1 @@
+# 0.16版本更新
diff --git a/docs/change_log/update_v0.20.md b/docs/change_log/update_v0.20.md
new file mode 100644
index 00000000..43cec398
--- /dev/null
+++ b/docs/change_log/update_v0.20.md
@@ -0,0 +1,416 @@
+# Version 0.20 update
+
+Update date: 2023-02-01
+
+The following are the specific changes in the instructions in version 0.20:
+
+## 1. Changes in microinstruction structure
+
+Most microinstructions can access both the T register and the SR register. For example:
+
+- **Mode A**: Both sources are registers: add a0 a1.
+- **Mode B**: Two sources are SR registers, and one source is T register: add t#1 a0.
+- **Mode C**: The two sources are T registers: add t#1 t#2.
+
+!!! note "Note! The following instructions only support T register index"
+
+ MUL/DIV/REM encoding is insufficient and only T register index is supported.
+ Floating point instructions only support T register indexing.
+
+## 2.GET/SET semantic modification
+
+- SET is renamed to SET.G, and global/local GPR is updated at the same time.
+- SGET/SSET renamed to GET/SET.
+- GET/SET and SET.C/SET.TGT share encoding space 4'b0110/4'b0111.
+
+### 2.1 New MV (Move command)
+
+**MV R1, R2** Move R2 to R1. This instruction is used for register migration in Calling Convention.
+**MV.G R1, R2** Move R2 to R1 and broadcast R1. This instruction is used to migrate the value of PHI node in if-else.
+The hardware executes this instruction simultaneously as a GET and SET instruction.
+The MV instruction serves as the absolute register version of the set instruction **set a0/t#m a1**
+
+### 2.2 Remove ADDSP/ADDSPI instructions
+
+Due to the modified GET/SET semantics, the ADDSP instruction is less necessary.
+In addition to affecting the code size, the following two instructions can be used instead of ADD SP t#1, SET.G t#1 SP.
+The main reason for removing this instruction is that this instruction is a calculation instruction with side effects. We hope that only SET/MV has side effects, and other instructions cannot modify GPR, which is good for hardware implementation (simplifying intra-block Rename).
+
+### 2.3 Added GETspecial register
+
+- GET TID: Get thread ID
+- GET CPUID: Get CPU ID
+- GET HDS: Get the size of the current header
+
+## 3. CONST instruction imm is increased from 11bit to 12bit
+
+Original immediate range -1024-1023
+Existing immediate range -2048-2047
+Reason: 12-bit immediate data is at the same level as RISV's ADDI. In this case
+
+`ADDI rd, rs0, imm(12bit)`
+
+Equivalent to the following:
+
+```c
+const imm(12bit)
+addi rs0, t#1
+```
+If there is a SET, then an additional SET is needed.
+```c
+const imm(12bit)
+addi rs0, t#1
+set rd, t#1
+```
+
+## 4. Added new HYPER Block type
+
+The new version v0.20 indicates whether there is a jump within the block on header
+Added new Block attribute b.hyper in parallel with the type of block
+
+## 5. Added TRAP jump type
+
+Tell the hardware that the current header is a TRAP jump type block, and the subsequent hardware is ready to make a system call.
+This header is used when the program ends/system call is made.
+
+## 6. LOAD/STORE instruction addressing mode optimization
+
+### Load instruction addressing:
+
+- **Mode A**: Link + Imm (signed 5bit) Assembly format: ld [t#1, 8]
+```c
+LB：ADDR = Link + Imm
+LH：ADDR = Link + Imm<<1
+LW：ADDR = Link + Imm<<2
+LD：ADDR = Link + Imm<<3
+LBU：ADDR = Link + Imm
+LHU：ADDR = Link + Imm<<1
+LWU：ADDR = Link + Imm<<2
+```
+Note: The range of immediate data is -16 to 16
+
+- **Mode B**: Register + Imm (signed 4bit) Assembly format: ld [a0, 8]
+```c
+LB：ADDR = Register + Imm
+LH：ADDR = Register + Imm<<1
+LW：ADDR = Register + Imm<<2
+LD：ADDR = Register + Imm<<3
+LBU：ADDR = Register + Imm
+LHU：ADDR = Register + Imm<<1
+LWU：ADDR = Register + Imm<<2
+```
+Note: The range of immediate data is -8 to 8
+
+- **Mode C**: SP + Imm (signed 8bit) Assembly format: ld [sp, 8]
+```c
+LB：ADDR = SP + Imm
+LH：ADDR = SP + Imm<<1
+LW：ADDR = SP + Imm<<2
+LD：ADDR = SP + Imm<<3
+LBU：ADDR = SP + Imm
+LHU：ADDR = SP + Imm<<1
+LWU：ADDR = SP + Imm<<2
+```
+Note: The range of immediate data is -128 to 128- **Mode D**: IP + Imm (unsigned 8bit) Assembly format: ld [ip, 8]
+```c
+LW：ADDR = TPC_END + Imm<<2
+LD：ADDR = TPC_END + Imm<<3
+LWU：ADDR = TPC_END + Imm<<2
+```
+Note: This instruction is used to access the long immediate number placed after body. Can also be used for PC-relative loads. The immediate range is 0 to 256.
+
+Using the above addressing modes, most load scenarios can be efficiently covered, such as pointer addressing:
+```
+ld [a0]
+ld [t#1, 8]
+```
+### Store instruction addressing
+
+Due to the 16-bit encoding limitation, the Store needs to index additional data, so it cannot have complex addressing modes.
+
+- **Mode E**: [Link0 + Imm (unsigned 3bit)] = link1 Assembly format: sd [t#1, 8], t#2
+
+SB: [ADDR = Link0]=DATA=Link1 Note: store byte does not have immediate encoding, write ADDR back to T register
+SH: [ADDR = Link0]=DATA=Link1 Note: store half word does not have immediate encoding, write ADDR back to T register
+SW: [ADDR = Link0 + Imm<<2]=DATA=Link1, the immediate data only has 3 bit space, takes the value 0/4/8/12/16/20/24/28, and writes ADDR back to the T register
+SD: [ADDR = Link0 + Imm<<3]=DATA=Link1, the immediate data only has 3 bit space, takes the value 0/8/16/24/32/40/48/56, and writes ADDR back to the T register
+Example: If you want to encode array[i] = a0+a1
+```c
+add a0, a1
+ag.uxtw array, i
+sd [t#1], t#2
+```
+
+- **Mode F**: [Link + Imm (unsigned 2bit)] = register assembly format: sd [t#1, 8], a0
+
+SB: [ADDR = Link0]=DATA=Reg Note: store byte does not have immediate encoding, write ADDR back to T register
+SH: [ADDR = Link0]=DATA=Reg Note: store half word does not have immediate encoding, write ADDR back to T register
+SW: [ADDR = Link0 + Imm<<2]=DATA=Reg, the immediate data only has 2 bit space, takes the value 0/4/8/12, and writes ADDR back to the T register
+SD: [ADDR = Link0 + Imm<<3]=DATA=Reg, the immediate data only has 2 bit space, takes the value 0/8/16/24, and writes ADDR back to the T register
+Example: If you implement a store quart instruction
+```c
+sd [a4], a0
+sd [t#1, 4], a1
+sd [t#1, 4], a2
+sd [t#1, 4], a3
+```
+
+- **Mode G**: [Register + Imm (unsigned 2bit)] = link assembly format: sd [a0, 8], t#1
+
+SB: [ADDR = Register]=DATA=Link Note: store byte does not have immediate encoding.
+SH: [ADDR = Register]=DATA=Link Note: store half word does not have immediate encoding.
+SW: [ADDR = Register + Imm<<2]=DATA=Link, the immediate data only has 3 bit space, takes the value 0/4/8/12/, and writes ADDR back to the T register
+SD: [ADDR = Register + Imm<<3]=DATA=Link, the immediate data only has 3 bit space, takes the value 0/8/16/24/, and writes ADDR back to the T register
+Example: Another implementation method of store quard instruction
+```c
+ld [s0]
+sd [a0], t#1
+sd [a0, 8], t#2
+sd [a0, 16], t#3
+sd [a0, 24], t#4
+```
+If the immediate number is too long, or is not within 0/4/8/12, then you have to use the following method:
+```c
+const imm
+ag.td a0, t#1
+sd [t#1], a1
+```
+- **Mode H**: [Register + Imm (unsigned 1bit)] = link assembly format: sd [a0, 8], a1SB: [ADDR = Register]=DATA=Register Note: store byte does not have immediate encoding, write ADDR back to T register
+SH: [ADDR = Register]=DATA=Register Note: store half word does not have immediate encoding, write ADDR back to T register
+SW: [ADDR = Register + Imm<<2]=DATA=Register, the immediate data only has 1 bit space, takes the value 0/4, and writes ADDR back to the T register
+SD: [ADDR = Register + Imm<<3]=DATA=Register, the immediate data only has 1 bit space, takes the value 0/8, and writes ADDR back to the T register
+Example: An implementation method of the store pair instruction
+```c
+sd [a0], a1
+sd [a0,8], a2
+```
+The two register codes already occupy 8 bits, and the Opcode is 7 bits, so there is no coding space for immediate data.
+
+Why can't it be made like this? :
+```
+const offset
+sd [a0, t#1], a2
+```
+Because this instruction becomes a 3-operand instruction, it violates the principle of simplifying hardware.
+
+How to solve the problem of insufficient register encoding? ->Use AG-address gen command
+```
+const offset
+ag.td a0, t#1
+sd [t#1], a2
+```
+
+## AG instruction addressing
+
+In order to solve the problem of significant insufficient Store encoding space in pure 16-bit encoding space, we introduced the AG:address generation instruction.
+
+AG was originally called LEA:load effective address. In order to avoid duplication with x86, it was changed to AG.
+The AG instruction is specially used for complex addressing modes and can be used together with the Load/Store instructions, but it is mainly used for stores.
+Due to insufficient coding space of the Store, additional instructions had to be introduced to generate the store address.
+AG is mainly used for the access mode array[i] = b.
+The AG command formula is as follows:
+
+`R0 + convert(R1) << scale`
+
+Convert refers to a transformation function, which has the following three types:
+
+1. If the R1 type is unsigned int, then zero extend first, and shift left by 2/3
+2. If the R1 type is signed int, then sign extend first and shift left by 2/3
+3. If the R1 type is long int, then shift left by 1/2/3
+
+As an opcode extension of AG, convert has the following modes:
+
+- AG.TW: Equivalent to R0 + R1<<2 Assembly format: ag.tw a0, a1
+- AG.TD: Equivalent to R0 + R1<<3 Assembly format: ag.td a0, a1
+- AG.UXTW: Equivalent to R0 + ((unsigned int)R1)<<2 Assembly format: ag.uxtw a0, a1
+- AG.SXTW: Equivalent to R0 + ((signed int)R1)<<2 Assembly format: ag.sxtw a0, a1
+- AG.UXTD: Equivalent to R0 + ((unsigned int)R1)<<3 Assembly format: ag.uxtd a0, a1
+- AG.SXTD: Equivalent to R0 + ((signed int)R1)<<3 Assembly format: ag.sxtd a0, a1
+
+The AG instruction supports three index modes, single and mixed, for Link and Register.
+
+### LD/ST directive
+
+For assembly readability, we need to introduce the ld/st pseudo-instruction, which can be split into the AG+LD/ST microinstruction sequence at the back end.
+
+load directive format:
+
+`ld [(reg0/t#m), (reg1/t#n), imm, {TW/TD/UXTW/SXTW/UXTD/SXTD}]`
+For example, when reading array[i].field, i is int, array is 64bit, and field offset is 24, it can be written as the following pseudo-instruction
+
+`ld [a0, a1, 24, uxtd]`
+It will expand into the following instructions:
+```c
+ag.uxtw a0, a1
+ld [t#1, 24]
+```
+store directive format:
+
+`sd [(reg0/t#m), (reg1/t#n), imm, {TW/TD/UXTW/SXTW/UXTD/SXTD}], (reg2/t#k)`
+For example, to assign a value to array[i].field = x, it can be written as the following pseudo-instruction`sw [a0, a1, 24, sxtw], a3`
+It will expand into the following instructions:
+```c
+ag.sxtw a0, a1
+addi t#1, 24
+sw [t#1], a3
+```
+Among them, ag.sxtw can be replaced by the following instructions:
+```c
+getw a1
+slli t#1, 2
+add a2, t#1
+addi t#1, 24
+sw [t#1], a3
+```
+
+# LinxISA0.21 update introduction
+
+LinxISA v0.21 mainly solves the problems we encountered in v0.20 compilation and model joint debugging implementation. The main changes are:
+
+1. Fine-tuning the coding field of some instructions with the goal of further reducing the Code Size.
+2. Some immediate instructions can only index the results of previous instructions, increasing the coding space for immediate instructions.
+3. Reconstructed the encoding of Store instructions. The encoding and decoding of v0.20 is too complicated.
+4. Added SET Imm command.
+5. Refer to RISCV and complete the Zba/Zbb/Zbc/Zbd extension.
+
+The following are the specific changes to the directive:
+
+## 1. Added Local Zero register
+
+The Local GPR of BISA v0.21 defines a total of 17 registers, **Zero** and **R0-R15**. But there is no Zero register definition in Global GPR.
+
+!!! note "note"
+ The Local RA register has not been removed and can only be read by GET instructions and written by SET instructions.
+
+The parsing of R0 in GET/SET in microinstructions is different:
+
+GET Rx in the microinstruction can index R0-R15, where x==0 represents the index R0 (Local RA) register.
+In microinstructions, SET R0, R0 represents SET Zero, RA. The same goes for SET.G/SET.GL.
+SET Rx, Ry in the microinstruction. Rx can index Zero, R1-R15, Ry can index R0, R1-R15.
+R0 in the remaining microinstructions all represent Zero registers.
+
+The above directly indexed registers become Zero registers.
+
+## 2. Index preorder instruction results
+
+We found that most instructions use T#1 much more frequently than other T#2-T#8. For ADDI t#l, imm instructions, there are no non-t#1 scenarios.
+
+Therefore, we give up the encoding of the Link field segment to the immediate value. Under V0.21, the following instructions can only use t#1:
+
+ADDI,SUBI,ANDI,ORI,XORI,SRLI,SRAI,SLLI - addi t#1, imm where t#1 is not encoded.
+
+!!! info "LOAD/STORE command"
+ Due to insufficient original coding space, the Store instruction needs to be reconstructed using this design.
+
+## 3.REG+IMM immediate encoding reconstruction
+
+Due to the introduction of the Zero register, the ADDI class immediate data Imm does not need to express Imm with a value of 0, so Imm 0 is given the encoding of a larger value number.
+
+The original command ADDI R0, 0 can be used as GET. BISA V0.21 needs to be changed to ADD R0, zero.
+The original code of the original instruction ADDI R0, 0 needs to be parsed into ADDI R0, 16.
+
+!!! note "note"
+
+ The immediate encoding +1 of SRL/SRA/SLL will be uniformly changed to the following mapping in 0.21:
+ The mapping of immediate encoding becomes one-to-one correspondence, and for immediate 0, it is decoded into a larger overflow value.
+
+This immediate mapping applies to:
+
+ADDI,SUBI,ANDI,ORI,XORI,SRLI,SRAI,SLLI
+ADDIW,SUBIW,ANDIW,ORIW,XORIW,SRLIW,SRAIW,SLLIW
+CMP.EQI,CMP.NEI,CMP.LTI,CMP.LTUI,CMP.GEI,CMP.GEUI
+SETC.EQI,SETC.NEI,SETC.LTI,SETC.LTUI,SETC.GEI,SETC.GEUI
+
+Immediate values of Load/Store type instructions are not applicable.
+
+## 4. Complete the AG command
+
+The AG instruction version 0.21 completes all possibilities and can be unified into the following form, with a total of 2x2x3x4=48 expression forms.
+The reason for the completion instruction: Shift 1 operations will be used more frequently (half-precision) in AI programs in the future.
+
+`AG {LREG/TREG}, {LREG,TREG}, {DW, SW, UW} << {0,1,2,3}`
+
+Improvements in assembly writing:
+
+In order to avoid conflicts with ARM patents, the name UXTW will be attacked, so we redesigned the assembly writing method```c
+ ag a0, a1, uw /* 代表计算a0 + ((unsigned int)a1) */
+ ag a0, a1, uw << 1 /* 代表计算a0 + ((unsigned int)a1)<<1 */
+ ag a0, t#1, sw << 2 /* 代表计算a0 + ((signed int)t#1)<<2 */
+ ag t#2, t#1 << 3 /* 代表计算t#2 + (t#1<<3) */
+```
+
+## 5. New growth instruction encoding
+
+In order to solve the problem of insufficient 16bit instruction encoding, BISA v0.21 introduced long instruction encoding. The principle of long instruction encoding is similar to CONCATheader.
+
+- Long instruction encoding fixedly occupies 1/16 of the encoding space.
+- The long instruction occupies the position of a T register, and the encoding length is 32 bits.
+- Long instructions only appear in **auxiliary block AUX**, **system block SYS**, **floating point block FP**, and do not appear in standard blocks.
+
+
+The encoding of the following instructions is transferred to the long instruction space, and relative indexing/absolute indexing/mixed indexing is also supported.
+
+- `mul a0, a1`, `mul a0, t#1`, `mul t#1, a1`, `mul t#1, t#2`, `mulh, mulhu, mulhsu, mulw `
+- `div a0, a1`, `div a0, t#1`, `div t#1, a1`, `div t#1, t#2`, `divu, divuw`
+- `rem a0, a1`, `remu a0, t#1`, `remuw t#1, a1`, `remw t#1, t#2`, `remu, remuw`
+- `bxu a0, imml-u6, immr-u6`, `bxu t#1, imml-u6, immr-u6`
+- `bxs a0, imml-u6, immr-u6`, `bxs t#1, imml-u6, immr-u6`
+
+## 6. Added three-operand instruction
+
+In order to reduce hardware complexity, the third operand of the three-operand instruction must be the T register.
+BISA v0.21 adds two three-operand instructions in the auxiliary block:
+- **SELECT**：select t#c, a0/t#1, a1/t#2
+Among them, t#c indexes the condition
+
+- **BFM**: bfm t#c, a0/t#1, a1/t#2 - The original BAM+BMG instructions are merged.
+Among them, t#c indexes the bitfield mask.
+
+The value of a1 and Mask are covered to get value -- BMG
+Overwrite value onto a0 and write to T register - BAM
+
+## 7. Reconstructed floating point encoding
+
+In the SPEC2006 FP example, floating point multiplication/floating point are hot instructions and need to be assigned two encoding formats: absolute/relative.
+
+Allocating absolute/relative encoding space to all floating point instructions has exceeded the 16bit encoding space.
+
+Therefore, in 0.21, we only give 16 bits of space for floating point multiplication, addition and floating point conversion.
+
+FADD.H, FADD.S, FADD.D represent half-precision, single-precision and full-precision floating point addition respectively.
+
+FMUL.H, FMUL.S, FMUL.D represent half-precision, single-precision and full-precision floating point multiplication respectively
+
+The hardware will combine the following combinations of instructions into multiply-accumulate instructions:
+```
+FADD.D R0, R1
+FMUL.D t#1, R3
+```
+
+The FGET instruction supports mutual conversion of five formats: **64bit Integer**, **32bit signed/unsigned**, **half precision**, **single precision**, and **double precision**.
+A total of 24 mode conversions.- FGET.L.H: 64-bit long integer to 16-bit half float
+- FGET.L.S: 64-bit long integer to 32-bit single float
+- FGET.L.D: 64-bit long integer to 64-bit double
+- FGET.W.H: 32-bit signed integer to 16-bit half float
+- FGET.W.S: 32-bit signed integer to 32-bit single float
+- FGET.W.D: 32-bit signed integer to 64-bit double
+- FGET.WU.H: 32-bit unsigned integer to 16-bit half float
+- FGET.WU.S: 32-bit unsigned integer to 32-bit single float
+- FGET.WU.D: 32-bit unsigned integer to 64-bit double
+- FGET.H.L: 16-bit half float to 64-bit long integer
+- FGET.H.W: 16-bit half float to 32-bit signed integer
+- FGET.H.WU: 16-bit half float to 32-bit unsigned integer
+- FGET.H.S: 16-bit half float to 32-bit single float
+- FGET.H.D: 16-bit half float to 64-bit double
+- FGET.S.L: 32-bit single float to 64-bit long integer
+- FGET.S.W: 32-bit single float to 32-bit signed integer
+- FGET.S.WU: 32-bit single float to 32-bit unsigned integer
+- FGET.S.H: 32-bit single float to 16-bit half float
+- FGET.S.D: 32-bit single float to 64-bit double
+- FGET.D.L: 64-bit double to 64-bit long integer
+- FGET.D.W: 64-bit double to 32-bit signed integer
+- FGET.D.WU: 64-bit double to 32-bit unsigned integer
+- FGET.D.H: 64-bit double to 16-bit half float
+- FGET.D.S: 64-bit double to 32-bit single float
+
+## 7. All remaining system blocks and floating point block instruction are moved to the long immediate space
\ No newline at end of file
diff --git a/docs/change_log/update_v0.30.md b/docs/change_log/update_v0.30.md
new file mode 100644
index 00000000..a95634b9
--- /dev/null
+++ b/docs/change_log/update_v0.30.md
@@ -0,0 +1,94 @@
+# 0.30 version update
+
+Date: August 18, 2023
+
+For the path to the web version of the instruction encoding design document, please see [LinxISA Encoding-v0.30](http://dbox.huawei.com/detaildocs?oid=VR%3Awt.doc.WTDocument%3A100255877291)
+
+### 32bit encoding format changes
+
+v0.30 reconstructs the 32bit encoding format. Reasons for reconstruction:
+
+- The current coding of BISA microinstructions is not optimal, and CodeSize and fetching FootPrint are too large.
+- BISA is about to be officially commercialized. An optimal and universal instruction code needs to be determined as soon as possible, and no major changes will be made in the future.
+- To upgrade BISA to 1.0, you need to reserve instruction space and lay out the 32bit encoding space in advance.
+
+Coding format changes:
+
+- In an encoding format, the source register can be expressed as a T register or a block-private register (flag bit judgment).
+- Add additional destination register, which can be block-private register or shared architectural register (flag bit judgment).
+- Improved the encoding space of immediate data.
+
+### Directive implementation changes
+
+- Most instructions are merged with the set/set.g instructions, the results are selectively updated to the destination register, and the design of writing the results to the T register by default remains unchanged.
+- The multiplication instruction writes the high and low bits of the result to the destination T register and destination register respectively.
+- The division/remainder instruction writes the quotient and remainder to the destination T register and destination register respectively.
+- The load class instruction writes the loaded data and access address to the destination T register and destination register respectively.
+
+### Add new command
+
+#### Jump class within block
+
+- b.eq: jump when equal
+- b.ne: jump without waiting
+- b.lt: jump when less than (signed comparison)
+- b.ge: Jump when greater than or equal to (signed comparison)
+- b.ltu: jump if less than (unsigned comparison)
+- b.geu: jump when greater than or equal to (unsigned comparison)
+
+#### Integer general calculation class:
+
+- addc: addition with carry;
+- subc: borrow subtraction;
+
+#### Memory access class
+
+- PRF: Prefetch memory (first fetch the memory block containing the access address into the cache).
+
+#### Bit operation class
+
+- ctz: Count the number of zeros following the least significant bit in the register;
+- concat: concatenation (circular shift)
+
+#### Floating point calculation class
+
+- fmadd: floating-point multiply-accumulate instruction;
+- fabs: find the absolute value of floating point;
+
+#### Immediate type
+
+- lui: high-bit immediate data loading.
+
+#### Block input/output Class
+
+- bend: used as an instruction to end the execution of block instruction. It belongs to the input/output instruction in the standard block.
+
+#### System command class- BSE: After the current block is submitted, custom event information is sent to the external system.
+- BC.IVA: The virtual address corresponding to the memory address of invalid SrcL in Block Header Cache.
+- BC.IALL: Invalidate all Cachelines in Block Cache.
+- IC.IVA: The virtual address corresponding to the memory address of invalid SrcL in the Instruction Cache.
+- IC.IALL: Invalidate all Cachelines in the Instruction Cache.
+- DC.IVA: The virtual address corresponding to the memory address of invalid SrcL in Data Cache.
+- DC.CVA: Write the virtual address corresponding to the memory address of SrcL in the Data Cache back to the next level cache or the main processor.
+- DC.CIVA: Write the virtual address corresponding to the memory address of SrcL in the Data Cache back to the next level cache or the main processor, and mark the corresponding Cacheline as invalid.
+- DC.ISW: The Cacheline corresponding to the Set/Way indicated in the invalid SrcL in the Data Cache.
+- DC.CSW: Write the Cacheline corresponding to the Set/Way indicated in SrcL in the Data Cache back to the next level cache or main processor.
+- DC.CISW: Write the Cacheline corresponding to the Set/Way indicated in SrcL in the Data Cache back to the next level cache or main processor, and mark the corresponding Cacheline as invalid.
+- TLBGET: Privilege level: Read the page table and set the corresponding SSR register.
+- TLBSET: Privilege level: Read the SSR register and set the corresponding page table.
+- TLBI: Clear the page table corresponding to the ASID stored in Src in the TLB.
+- FENCE.D: Data barrier.
+- FENCE.I: Command barrier.
+
+### Other changes
+
+- Added `基址寄存器+变址寄存器` addressing mode to memory access instructions;
+- The sel command is changed to **csel** (conditional selection command)
+- Floating point instructions are merged (for example: fdiv.h, fdiv.s, fdiv.d are changed into one instruction fdiv) to achieve the same operation of different precision operands in one instruction.
+- The fget instruction adds conversion between 64-bit unsigned long integer and [half/single/double] precision floating point numbers, and the name of the fget instruction is changed to **fcvt**.
+- Microinstructions in the system block: SSRGET, SSRSET, lr.d, lr.w, sc.d, sc.w are retained; trap, wfe, wfi, fence, fence.i are merged into SSRCRLT instructions.
+- Change the CARG.FLAG field of the submission parameter register to a 1-bit flag. The setc.eq class instruction sets CARG.FLAG.
+- Support the ssrget instruction in the standard block, that is, read-only system register is implemented in the standard block.
+- Changes to multiplication instructions:
+
+Previous versions used mul,mulh,mulhsu,mulhu,mulw; v0.30 used mul,mulu,mulw,muluw,mulh,mulhu. At the same time, the output of the destination T register of the mul/mulu instruction and the RegDst register are changed to be consistent (the low bits of the multiplication result are retained).
\ No newline at end of file
diff --git a/docs/change_log/update_v0.31.md b/docs/change_log/update_v0.31.md
new file mode 100644
index 00000000..b7f72a80
--- /dev/null
+++ b/docs/change_log/update_v0.31.md
@@ -0,0 +1,32 @@
+# 0.31 version update
+
+Date: September 18, 2023
+
+For the path to the web version of the instruction encoding design document, please see [LinxISA Encoding-v0.31](http://dbox.huawei.com/detaildocs?oid=VR%3Awt.doc.WTDocument%3A100255902243)
+
+The v0.31 version is mainly an update to the header encoding.
+
+## header changes
+
+v0.31 defines 10 types of block instructionheader instruction including **standard block**, **standard super block**, **standard compression fast**, **standard super compression block**, **standard floating point block**, **standard floating point super block**, **inline block**, **control block**, **template block** and **system block**.
+
+- Put instructions in the 16-bit encoding space into standard compression blocks and standard super compression blocks for execution.
+- Add inline block to embed instructions in header.
+- The concat block is removed and the LBREF block is added to realize long jump, long index and loop control.
+- Delete the auxiliary block, and move the microinstructions in the original auxiliary block to the standard block for execution.
+
+block type defined in v0.31 is as follows:
+
+| block type | Explanation | Assembly Identification |
+|---------------------|---------------------|-------------|
+| Standard Block | Standard Block | b.std |
+| Standard Hyper Block | Standard Hyper Block | b.stdh |
+| Standard Compressd Block | Standard Compressed Block | b.stdc |
+| Standard Compressd Hyper Block | Standard Compressed Hyper Block | b.stdhc |
+| Floating-point Block | Standard floating-point block | b.fp |
+| FP Hyper Block | Standard floating point super block | b.fph |
+| Inline Block | Inline block | b.inl |
+| Control Block | Control Block | See specific block instruction |
+| Template Block | template block | See specific block instruction |
+| System Block | System Block | b.sys |
+| System Hyper Block | System Hyper Block | b.sysh |
\ No newline at end of file
diff --git a/docs/change_log/update_v0.32.md b/docs/change_log/update_v0.32.md
new file mode 100644
index 00000000..e04c743d
--- /dev/null
+++ b/docs/change_log/update_v0.32.md
@@ -0,0 +1,66 @@
+# 0.32 version update
+
+Date: September 28, 2023
+
+For the path to the web version of the instruction encoding design document, please see [LinxISA Encoding-v0.32](http://dbox.huawei.com/detaildocs?oid=VR%3Awt.doc.WTDocument%3A100255827005)
+
+The most important change in the v0.32 version is the change to the store command.
+
+## Directive implementation changes
+
+### Store command changes
+
+1. Since the DecodeType decoding type of the hardware decoder does not match, the **opcode** of the Store instruction (sb/sh/sw/sd) needs to be adjusted:
+ - Reg + Reg format: opcode 7'b0010110 -> 7'b0010100 /* Change the RegDst field to all zeros */
+ - Reg + imm format: opcode 7'b0010111 -> 7'b0010101
+2. In order to simplify the writing port of the hardware register of the Store instruction and reduce the complexity of hardware implementation. Modify the execution operation of instructions such as sb/sh/sw/sd to: do not output the destination address, that is, do not write the T register and RegDst register.
+3. In order to improve the efficiency of continuous memory writing, the sb.a/sh.a/sw.a/sd.a instruction is added. Based on the corresponding sb/sh/sw/sd function, the operation of writing addresses to the destination T and RegDst registers is added.
+
+
+
+### Instruction operand increases TP/GP/CP
+
+In v0.32, the source register of each microinstruction can index the TP/GP/CP register in system register.
+
+- In order to improve the efficiency of hardware access to private variables, the operation of microinstruction index TP register is added.
+- In order to improve the efficiency of hardware access to global variables, the operation of microinstruction index GP register has been added.
+- In order to improve the efficiency of hardware state migration, the operation of microinstruction index CP register is added.
+
+### Changes in bit operation instructions
+
+#### In order to improve the efficiency of string library processing, new bit manipulation instructions are added
+
+- ctzw: Count trailing zeros within the least significant word.
+- clz: Count leading zeros within the entire 64bit.
+- clzw: Count leading zeros within the least significant word.
+
+#### In order to reduce the complexity of hardware implementation. The bit operation instruction bfi encoding update: changed to a two-input instruction, M/N is expressed in the instruction encoding.
+
+Before update:
+
+
+
+After update:
+
+
+
+!!! info "Coding changes bring about partial changes in instruction implementation"
+
+ After the update, the G/L field and RegDst field are occupied by the M field, so the result is only written to the T register.
+ Before the update, it was a three-input instruction. In order to simplify the hardware implementation, SrcR was restricted to only index the block-private register. After updating to two inputs, this restriction is removed, and SrcR can index the T register and the newly added TP/GP/CPsystem register
+
+#### In order to adapt to the modification of bfi encoding, the bxu and concat encodings have been updated:
+
+Before update:
+
+
+
+After update:
+
+
+
+#### The bxu/bxs/bfi command implements the processing of adding winding situations.
+
+By adding winding, these instructions can be used to implement circular shift operations (ror, rol) on the operands.
+
+For the modified instruction implementation, please see: [bxu](../isa/inst/misa_g/BXU.md), [bxs](../isa/inst/misa_g/BXS.md), bfi.
\ No newline at end of file
diff --git a/docs/change_log/update_v0.33.md b/docs/change_log/update_v0.33.md
new file mode 100644
index 00000000..154d0654
--- /dev/null
+++ b/docs/change_log/update_v0.33.md
@@ -0,0 +1,181 @@
+# 0.33 version update
+
+Date: November 3, 2023
+
+For the path to the web version of the instruction encoding design document, please see [LinxISA Encoding-v0.33](http://dbox.huawei.com/detaildocs?oid=VR%3Awt.doc.WTDocument%3A100255827005)
+
+## Change 1: LD/ST adds Scale and Unscale modes
+
+Scaled/Unscaled refers to whether the right source operand SrcR is shifted according to the memory access bit width.
+
+- **Scaled:** Address = SrcL + SrcR << size
+- **Unscaled:** Address = SrcL + SrcR
+
+Scaled and Unscaled are applicable to both `Reg+Reg` and `Reg+Imm`.
+
+- **Scaled:** Address = SrcL + imm << size
+- **Unscaled:** Address = SrcL + imm
+
+In 0.33, LD uses an additional 1 bit in the Opcode to distinguish between scale and unscale. This 1 bit represents whether to shift.
+The advantage of this change is that the scaled expression range is larger and the data structure is increased from 2MB (12bit) to 16MB (15bit). At the same time, it gives the software more choices in misaligned scenarios.
+
+Load class instruction (Reg+imm) scaled mode encoding:
+
+
+
+Load class instruction (Reg+imm) unscaled mode encoding:
+
+
+
+Load.a class instruction (Reg+imm) scaled mode encoding:
+
+
+
+Load.a class instruction (Reg+imm) unscaled mode encoding:
+
+
+
+1. The original load/store encoding becomes scaled by default, and unscaled load and store are added in the new opcode space. Therefore, only new codes are added and the original codes remain unchanged.
+2. Since there are few usage scenarios for SrcL-SrcR calculation addresses, the original ScaledLoad (Opcode = 7'b001_00X0) and ScaledStore (Opcode = 7'b001_01X0), that is, when Reg+Reg addressing is performed, the right source register no longer supports the inversion operation (.neg), and the low word interception signed/unsigned extension implementation (.sw and .uw) is retained.
+3. The execution semantics of the original ScaledLoad (Opcode = 7'b001_00X1) and ScaledStore (Opcode = 7'b001_01X1), that is, Reg+Imm addressing, have changed: the immediate data is shifted according to the memory access bit width.
+4. The encoding format of the original prf/prf.a instruction (Opcode = 7'b001_00X1) is removed, that is, the Reg+Imm format, and the corresponding execution semantics are implemented in the prf.ui/prf.uia instruction (Opcode = 7'b001_10X1).
+5. The highest 3 bits in the encoding of the prf/prf.a instruction (Opcode = 7'b001_00X0) are defined as the `model` field, which is used to implement cache level settings for prefetch purposes.
+
+Before update:
+
+
+
+After update:
+
+
+
+prefetch Model: 000: L1 Cache; 001: L2 Cache; 010: L3 Cache;
+
+After adding unscaled mode, the comparison of immediate data shifts between scaled and unscaled load/store instructions is as follows:| Scaled Load | Scaled | Unscaled Load | Unscaled |
+|-------------|-------------|------------|------------|
+| lh | SrcL+simm<<1 | lh.ui | SrcL+simm |
+| lw | SrcL+simm<<2 | lw.ui | SrcL+simm |
+| ld | SrcL+simm<<3 | ld.ui | SrcL+simm |
+| lhu | SrcL+simm<<1 | lhu.ui | SrcL+simm |
+| lwu | SrcL+simm<<2 | lwu.ui | SrcL+simm |
+| lh.a | SrcL+simm<<1 | lhu.uia | SrcL+simm |
+| lw.a | SrcL+simm<<2 | lw.uia | SrcL+simm |
+| ld.a | SrcL+simm<<3 | ld.uia | SrcL+simm |
+| lhu.a | SrcL+simm<<1 | lhu.uia | SrcL+simm |
+| lwu.a | SrcL+simm<<2 | lwu.uia | SrcL+simm |
+
+| Scaled Store | Scaled | Unscaled Store | Unscaled |
+|-------------|-------------|------------|------------|
+| sh | SrcL+SrcR<<1 | sh.ur | SrcL+SrcR |
+| sw | SrcL+SrcR<<2 | sw.ur | SrcL+SrcR |
+| sd | SrcL+SrcR<<3 | sd.ur | SrcL+SrcR |
+| sh.a | SrcL+SrcR<<1 | sh.ura | SrcL+SrcR |
+| sw.a | SrcL+SrcR<<2 | sw.ura | SrcL+SrcR |
+| sd.a | SrcL+SrcR<<3 | sd.ura | SrcL+SrcR |
+| sh | SrcL+simm<<1 | sh.ui | SrcL+simm |
+| sw | SrcL+simm<<2 | sw.ui | SrcL+simm |
+| sd | SrcL+simm<<3 | sd.ui | SrcL+simm |
+| sh.a | SrcL+simm<<1 | sh.uia | SrcL+simm |
+| sw.a | SrcL+simm<<2 | sw.uia | SrcL+simm |
+| sd.a | SrcL+simm<<3 | sd.uia | SrcL+simm |
+
+Modify the assembly format of scaled mode load/store instructions,| Microinstructions | Assembly before update | Assembly after update |
+|---------------|---------------|--------------------------------------------------------------------------------------------------|
+| LH | lh \[SrcL, simm<<1\]<, {=>, ->}RegDst> | lh \[SrcL, simm\]<, {=>, ->}RegDst> |
+| LW | lw \[SrcL, simm<<2\]<, {=>, ->}RegDst> | lw \[SrcL, simm\]<, {=>, ->}RegDst> |
+| LD | ld \[SrcL, simm<<3\]<, {=>, ->}RegDst> | ld \[SrcL, simm\]<, {=>, ->}RegDst> |
+| LBU | lbu \[SrcL, simm<<1\]<, {=>, ->}RegDst> | lbu \[SrcL, simm\]<, {=>, ->}RegDst> |
+| LHU | lhu \[SrcL, simm<<2\]<, {=>, ->}RegDst> | lhu \[SrcL, simm\]<, {=>, ->}RegDst> |
+| LWU | lwu \[SrcL, simm<<3\]<, {=>, ->}RegDst> | lwu \[SrcL, simm\]<, {=>, ->}RegDst> |
+| LH.A | lh.a \[SrcL, simm<<1\]<, {=>, ->}RegDst> | lh.a \[SrcL, simm\]<, {=>, ->}RegDst> |
+| LW.A | lw.a \[SrcL, simm<<2\]<, {=>, ->}RegDst> | lw.a \[SrcL, simm\]<, {=>, ->}RegDst> |
+| LD.A | ld.a \[SrcL, simm<<3\]<, {=>, ->}RegDst> | ld.a \[SrcL, simm\]<, {=>, ->}RegDst> |
+| LHU.A | lhu.a \[SrcL, simm<<1\]<, {=>, ->}RegDst> | lhu.a \[SrcL, simm\]<, {=>, ->}RegDst> |
+| LWU.A | lwu.a \[SrcL, simm<<2\]<, {=>, ->}RegDst> | lhu.a \[SrcL, simm\]<, {=>, ->}RegDst> || Microinstructions | Assembly before update | Assembly after update |
+|---------------|---------------------|--------------------------------------------------------------------------------|
+| SH | sh SrcD, \[SrcL, SrcR<{.sw,.uw}><<1\] | sh SrcD, \[SrcL, SrcR<{.sw,.uw}>\] |
+| SW | sw SrcD, \[SrcL, SrcR<{.sw,.uw}><<2\] | sw SrcD, \[SrcL, SrcR<{.sw,.uw}>\] |
+| SD | sd SrcD, \[SrcL, SrcR<{.sw,.uw}><<3\] | sd SrcD, \[SrcL, SrcR<{.sw,.uw}>\] |
+| SH.A | sh.a SrcD, \[SrcL, SrcR<{.sw,.uw}><<1\]<, {=>, ->}RegDst> | sh.a SrcD, \[SrcL, SrcR<{.sw,.uw}>\]<, {=>, ->}RegDst> |
+| SW.A | sw.a SrcD, \[SrcL, SrcR<{.sw,.uw}><<2\]<, {=>, ->}RegDst> | sw.a SrcD, \[SrcL, SrcR<{.sw,.uw}>\]<, {=>, ->}RegDst> |
+| SD.A | sd.a SrcD, \[SrcL, SrcR<{.sw,.uw}><<3\]<, {=>, ->}RegDst> | sd.a SrcD, \[SrcL, SrcR<{.sw,.uw}>\]<, {=>, ->}RegDst> || Microinstructions | Assembly before update | Assembly after update |
+|---------------|---------------------|--------------------------------------------------------------------------------|
+| SH | sh SrcL, [SrcR, simm<<1] | sh SrcL, [SrcR, simm] |
+| SW | sw SrcL, [SrcR, simm<<2] | sw SrcL, [SrcR, simm] |
+| SD | sd SrcL, [SrcR, simm<<3] | sd SrcL, [SrcR, simm] |
+| SH.A | sh.a SrcL, [SrcR, simm<<1]<, {=>, ->}RegDst> | sh.a SrcL, [SrcR, simm]<, {=>, ->}RegDst> |
+| SW.A | sw.a SrcL, [SrcR, simm<<2]<, {=>, ->}RegDst> | sw.a SrcL, [SrcR, simm]<, {=>, ->}RegDst> |
+| SD.A | sd.a SrcL, [SrcR, simm<<3]<, {=>, ->}RegDst> | sd.a SrcL, [SrcR, simm]<, {=>, ->}RegDst> |
+
+!!! note "note"
+ The above are only modifications to the assembly format of the instructions, and the instruction semantics have not changed.
+
+## Control block type to add BLB and BSBblock instruction
+
+The purpose of adding BLB instructions is to improve memory access efficiency, and adding BSB instructions can reduce Load/Store conflicts.
+
+For detailed introduction, you can view the implementation of each instruction.
+
+- **BLBAR**: Memory load speculation barrier (Block Load Speculation Barrier).
+- **BSBAR**: Memory write speculation barrier (Block Store Speculation Barrier).
+
+!!! note "note"
+ When a block instruction has memory to write a store, BSBblock instruction must be added. Without the block instruction, it means that there is no memory write in the current block.
+
+## JR adds immediate data - multiplexes BCOND encoding
+
+The JR instruction execution semantics and encoding have changed. For the updated instruction implementation and encoding, please see [JR](../isa/inst/misa_g/JR.md).
+
+This change to the JR instruction is an optimization scenario for intra-block jumps. If you need to jump to the location of a symbol and the j instruction encoding is insufficient, you only need one addtpc and jr to complete it.
+
+```
+jmp_label:
+ ......
+
+addtpc %top_20bit(jmp_label)
+jr t#1, %bottom_12bit(jmp_label)
+```
+
+Before updating, you need to use three instructions to complete:
+```
+jmp_label:
+ ......
+
+addtpc %top_20bit(jmp_label)
+addi t#1, %bottom_12bit(jmp_label)
+jr t#1
+```
+
+## Added ADDBPCN instruction and ADDBPCF instruction
+
+Under CALLBLOCK, obtaining the BPC of the current or next header is a frequently used command. However, due to encoding restrictions, Next Block PC does not want to occupy the immediate field segment. Therefore, we added the ADDBPCF instruction. (Note: The lowest bit of Opcode of instructions using immediate data must be 1). Adding this instruction can speed up the access speed of CALL block.
+
+- ADDBPCF: Add Block PC Fall Through, import the delayed BPC of the current block into the T register or RegDst register.
+
+Under PGO and performance Debug, we need to obtain the PC value predicted by the current jump prediction. Achieve the effect of Branch Record.- ADDBPCN: Add Block PC Next, import the predicted next BPC of the current block into the T register or RegDst register.
+
+After adding the ADDBPCN and ADDBPCF instructions, the opcode of the original ADDBPC instruction was adjusted:
+
+Before modification:
+
+
+
+After modification:
+
+
+
+Due to encoding conflicts, `opcode` of the three instructions ADDBPC, ADDBPCN, and ADDBPCF has been readjusted.
+
+Corrected encoding:
+
+
+
+## ADD/ADDW encoding adjustment
+
+1. In order to avoid conflicts with all-0 encoding (illegal instructions), the add instruction encoding is adjusted: the high 3 bits of the instruction encoding (func field) are changed from 3’b000 to 3’b001.
+
+
+
+2. In order to adapt to the modification of the add instruction, the same adjustment is made to the addw encoding.
+
+
\ No newline at end of file
diff --git a/docs/change_log/update_v0.34.md b/docs/change_log/update_v0.34.md
new file mode 100644
index 00000000..f0ef4c96
--- /dev/null
+++ b/docs/change_log/update_v0.34.md
@@ -0,0 +1,276 @@
+# 0.34 version update
+
+Date: December 6, 2023
+
+For the path to the web version of the instruction encoding design document, please see [LinxISA Encoding-v0.34](http://dbox.huawei.com/detaildocs?oid=VR%3Awt.doc.WTDocument%3A100258403959)
+
+## General description of version update
+
+1. Added implementation of 13 floating point instructions.
+2. Updates to load/store instructions: (1) Split of address offset shift type (scaled) load/store instructions; (2) Address offset non-shift type (unscaled) load/store instruction assembly name modification (3) Add an empty store instruction.
+3. Some instruction encoding adjustments: (1) System instruction encoding adjustment; (2) Arithmetic operation shift instruction encoding adjustment; (3) Partial template block instruction encoding adjustment; (4) Conditional selection instruction CSEL encoding adjustment
+4. Some instruction assembly format modifications: (1) l1/l2/l3 Cache identifiers are added to the prefetch instruction assembly format; (2) the destination register is removed from the template block instructionB.MCOPY and B.MSET assembly formats
+5. The CARG register removes the BSET/BGET/MSG field segments and changes it to a 64bit register.
+
+## Modification 1: Add floating point instruction implementation
+
+**Floating point calculation class**
+
+| Microinstructions | Assembly format | Description |
+|--------------|-------------------------------------------------|----------------|
+| fadd | fadd{.d,.s,.h} SrcL, SrcR<, {=>, ->}RegDst> | Floating point addition |
+| fsub | fsub{.d,.s,.h} SrcL, SrcR<, {=>, ->}RegDst> | Floating point subtraction |
+| fmul | fmul{.d,.s,.h} SrcL, SrcR<, {=>, ->}RegDst> | Floating point multiplication |
+| fmadd | fmadd{.d,.s,.h} SrcL, RSR, t#c<, {=>, ->}RegDst> | Floating point multiply and add |
+| fdiv | fdiv{.d,.s,.h} SrcL, SrcR<, {=>, ->}RegDst> | Floating point division |
+| fabs | fabs{.d,.s,.h} SrcL<, {=>, ->}RegDst> | Floating point absolute value |
+| fsqrt | fsqrt{.d,.s,.h} SrcL<, {=>, ->}RegDst> | Floating point square root |
+
+**Floating point conversion class**
+
+| Microinstructions | Assembly format | Description |
+|----------|----------------------------------|--------------|
+| fcvt | fcvt.dstT SrcL.srcT<, {=>, ->}RegDst> | Floating point conversion |
+
+**Floating point comparison class**| Microinstructions | Assembly format | Description |
+|--------------|------------------|---------------------------------|
+| feq | feq{.d,.s,.h} srcL, srcR<, {=>, ->}RegDst> | Floating point equality comparison |
+| fle | fle{.d,.s,.h} srcL, srcR<, {=>, ->}RegDst> | Floating point less than or equal to comparison |
+| flt | flt{.d,.s,.h} srcL, srcR<, {=>, ->}RegDst> | Floating point less than comparison |
+
+**Maximum value class**
+
+| Microinstructions | Assembly format | Description |
+|--------------|------------------|---------------------------------|
+| fmax | fmax{.d,.s,.h} srcL, srcR<, {=>, ->}RegDst> | Floating point maximum value |
+| fmin | fmin{.d,.s,.h} srcL, srcR<, {=>, ->}RegDst> | Floating point minimum value |
+
+## Modification 2, Load/Store command changes
+
+1. The load/store instructions of the addressing offset shift class (scaled mode) are split into two instructions according to the two encoding formats `Reg + Reg` and `Reg + Imm`.
+
+- `Reg + Reg` encoding format: keep the original command name unchanged.
+- `Reg + Imm` encoding format: Add "**I**" to the original instruction name to indicate that the instruction is a load/store instruction using immediate offset, adding an instruction. For example: `LB -> LBI`, `SD -> SDI`, `LW.A -> LWI.A`, `SD.A -> SDI.A`
+
+**Modification of Load command**| Original instruction name | Split instruction name | Assembly example | Explanation |
+|-----------|---------------|---------------------|-----------------------------------------------------------------------------|
+| LB | LB
LBI | lb [a1, a2 << shamt]
lbi [a1, imm] | The memory access address is a1 + (a2 << shamt), no fixed shift
The memory access address is a1 + imm, no shift by default |
+| LH | LH
LHI | lh [a1, a2 << shamt]
lhi [a1, imm] | The access address is a1 + (a2 << shamt), no fixed shift
The access address is a1 + (imm << 1), the default left shift is 1 bit |
+| LW | LW
LWI | lw [a1, a2 << shamt]
lwi [a1, imm] | The access address is a1 + (a2 << shamt), no fixed shift
The access address is a1 + (imm << 2), the default left shift is 2 bits |
+| LD | LD
LDI | ld [a1, a2 << shamt]
ldi [a1, imm] | The access address is a1 + (a2 << shamt), no fixed shift
The access address is a1 + (imm << 3), the default left shift is 3 bits |
+| LBU | LBU
LBUI | lbu [a1, a2 << shamt]
lbui [a1, imm] | The access address is a1 + (a2 << shamt), no fixed shift
The access address is a1 + imm, no shift by default |
+| LHU | LHU
LHUI | lhu [a1, a2 << shamt]
lhui [a1, imm] | The access address is a1 + (a2 << shamt), no fixed shift
The access address is a1 + (imm << 1), the default left shift is 1 bit |
+| LWU | LWU
LWUI | lwu [a1, a2 << shamt]
lwui [a1, imm] | The access address is a1 + (a2 << shamt), no fixed shift
The access address is a1 + (imm << 2), the default left shift is 2 bits |
+| LB.A | LB.A
LBI.A | lb.a [a1, a2 << shamt]
lbi.a [a1, imm] | The memory access address is a1 + (a2 << shamt), no fixed shift
The memory access address is a1 + imm, no shift by default |
+| LH.A | LH.A
LHI.A | lh.a [a1, a2 << shamt]
lhi.a [a1, imm] | The access address is a1 + (a2 << shamt), no fixed shift
The access address is a1 + (imm << 1), the default left shift is 1 bit |
+| LW.A | LW.A
LWI.A | lw.a [a1, a2 << shamt]
lwi.a [a1, imm] | The access address is a1 + (a2 << shamt), no fixed shift
The access address is a1 + (imm << 2), the default left shift is 2 bits || LD.A | LD.A
LDI.A | ld.a [a1, a2 << shamt]
ldi.a [a1, imm] | Access address is a1 + (a2 << shamt), no fixed shift
Access address is a1 + (imm << 3), default left shift is 3 bits |
+| LBU.A | LBU.A
LBUI.A | lbu.a [a1, a2 << shamt]
lbui.a [a1, imm] | The memory access address is a1 + (a2 << shamt), no fixed shift
The memory access address is a1 + imm, no shift by default |
+| LHU.A | LHU.A
LHUI.A | lhu.a [a1, a2 << shamt]
lhui.a [a1, imm] | The access address is a1 + (a2 << shamt), no fixed shift
The access address is a1 + (imm << 1), the default left shift is 1 bit |
+| LWU.A | LWU.A
LWUI.A | lwu.a [a1, a2 << shamt]
lwui.a [a1, imm] | The access address is a1 + (a2 << shamt), no fixed shift
The access address is a1 + (imm << 2), the default left shift is 2 bits |
+
+**Modification of Store directive**| Original instruction name | Split instruction name | Assembly example | Explanation |
+|-----------|---------------|---------------------|-----------------------------------------------------------------------------|
+| SB | SB
SBI | sb a0, [a1, a2]
sbi a0, [a1, imm] | The access address is a1 + a2, not shifted by default
The access address is a1 + imm, not shifted by default |
+| SH | SH
SHI | sh a0, [a1, a2]
shi a0, [a1, imm] | The memory access address is a1 + (a2 << 1), the default left shift is 1 bit
The memory access address is a1 + (imm << 1), the default left shift is 1 bit |
+| SW | SW
SWI | sw a0, [a1, a2]
swi a0, [a1, imm] | The memory access address is a1 + (a2 << 2), the default left shift is 2 bits
The memory access address is a1 + (imm << 2), the default left shift is 2 bits |
+| SD | SD
SDI | sd a0, [a1, a2]
sdi a0, [a1, imm] | The memory access address is a1 + (a2 << 3), the default left shift is 3 bits
The memory access address is a1 + (imm << 3), the default left shift is 3 bits |
+| SB.A | SB.A
SBI.A | sb.a a0, [a1, a2]
sbi.a a0, [a1, imm] | The memory access address is a1 + a2, not shifted by default
The memory access address is a1 + imm, not shifted by default |
+| SH.A | SH.A
SHI.A | sh.a a0, [a1, a2]
shi.a a0, [a1, imm] | The access address is a1 + (a2 << 1), the default left shift is 1 bit
The access address is a1 + (imm << 1), the default left shift is 1 bit |
+| SW.A | SW.A
SWI.A | sw.a a0, [a1, a2]
swi.a a0, [a1, imm] | The memory access address is a1 + (a2 << 2), the default left shift is 2 bits
The memory access address is a1 + (imm << 2), the default left shift is 2 bits |
+| SD.A | SD.A
SDI.A | sd.a a0, [a1, a2]
sdi.a a0, [a1, imm] | The memory access address is a1 + (a2 << 3), the default left shift is 3 bits
The memory access address is a1 + (imm << 3), the default left shift is 3 bits |
+
+2. In order to unify the naming format, modify the load/store instruction name of the addressing offset non-shift class (unscaled mode).
+
+**Modification of Load command**| Original instruction name | Modified name | Assembly example | Explanation |
+|----------|-------------|------------------------|---------------------------------------------|
+| LH.UI | LHI.U | lhi.u [a1, imm] | The access address is a1 + imm, no default shift is performed |
+| LW.UI | LWI.U | lwi.u [a1, imm] | The access address is a1 + imm, no default shift is performed |
+| LD.UI | LDI.U | ldi.u [a1, imm] | The access address is a1 + imm, no default shift is performed |
+| LHU.UI | LHUI.U | lhui.u [a1, imm] | The access address is a1 + imm, no default shift is performed |
+| LWU.UI | LWUI.U | lwui.u [a1, imm] | The access address is a1 + imm, no default shift is performed |
+| PRF.UI | PRFI.U | prfi.u.l1 [a1, imm] | The access address is a1 + imm, no default shift is performed |
+| LB.UIA | LBI.UA | lbi.ua [a1, imm] | The access address is a1 + imm, no default shift is performed |
+| LH.UIA | LHI.UA | lhi.ua [a1, imm] | The access address is a1 + imm, no default shift is performed |
+| LW.UIA | LWI.UA | lwi.ua [a1, imm] | The access address is a1 + imm, no default shift is performed |
+| LD.UIA | LDI.UA | ldi.ua [a1, imm] | The access address is a1 + imm, no default shift is performed |
+| LHU.UIA | LHUI.UA | lhui.ua [a1, imm] | The access address is a1 + imm, no default shift is performed |
+| LWU.UIA | LWUI.UA | lwui.ua [a1, imm] | The access address is a1 + imm, no default shift is performed |
+| PRF.UIA | PRFI.UA | prfi.ua.l1 [a1, imm] | The access address is a1 + imm, no default shift is performed |
+
+**Modification of Store directive**| Original instruction name | Modified name | Assembly example | Explanation |
+|----------|-------------|------------------------|---------------------------------------------|
+| SH.UR | SH.U | sh.u a0, [a1, a2] | The access address is a1 + a2, no default shift is performed |
+| SW.UR | SW.U | sw.u a0, [a1, a2] | The access address is a1 + a2, no default shift is performed |
+| SD.UR | SD.U | sd.u a0, [a1, a2] | The access address is a1 + a2, no default shift is performed |
+| SH.URA | SH.UA | sh.ua a0, [a1, a2] | The access address is a1 + a2, no default shift is performed |
+| SW.URA | SW.UA | sw.ua a0, [a1, a2] | The access address is a1 + a2, no default shift is performed |
+| SD.URA | SD.UA | sd.ua a0, [a1, a2] | The access address is a1 + a2, no default shift is performed |
+| SH.UI | SHI.U | shi.u a0, [a1, imm] | The access address is a1 + imm, no default shift is performed |
+| SW.UI | SWI.U | swi.u a0, [a1, imm] | The access address is a1 + imm, no default shift is performed |
+| SD.UI | SDI.U | sdi.u a0, [a1, imm] | The access address is a1 + imm, no default shift is performed |
+| SH.UIA | SHI.UA | shi.ua a0, [a1, imm] | The access address is a1 + imm, no default shift is performed |
+| SW.UIA | SWI.UA | swi.ua a0, [a1, imm] | The access address is a1 + imm, no default shift is performed |
+| SD.UIA | SDI.UA | sdi.ua a0, [a1, imm] | The access address is a1 + imm, no default shift is performed |
+
+3. Add a store instruction SNOP (Store NOP)
+
+This store instruction **does not write memory** and only occupies Store Buffer Entry (used with BSBAR memory write barrier block instruction).
+
+The instructions are encoded as follows:
+
+
+
+## Modification 3. Instruction encoding adjustment
+
+### System block instruction encoding adjustment
+
+In order to facilitate hardware decoding implementation and standardize the encoding and decoding format, we hope that the lowest bit of the **Opcode** field segment in the instruction encoding using immediate data is **1**. Therefore, the encoding of system instructions including SSRGET, SSRSET, SSRCRLT (and its expansion instructions) has been adjusted.
+
+Specifically: change the Opcode from the original `7'b100_0000` to `7'b100_0001`.
+
+Updated encoding:
+
+
+
+### Shift instruction encoding adjustment
+
+In order to improve the standardization of the instruction encoding and decoding format, firstly, the high-order bits of the shift instructions are divided into more clear geographical segments. At the same time, the func fields (encoded 12-14 bits) of the SRA{I,W,IW} instructions and the SRL{I,W,IW} instructions use the same encoding, and are distinguished in the high-order func fields. This can reserve space for adding shift instructions in future versions. The func field (encoded 12-14bit) of the SLL{I,W,IW} instruction has been modified accordingly.
+
+Coding before modification:
+
+
+
+Modified encoding:
+
+### Template block instruction encoding adjustment
+
+In the current version, saving the status of B.MCOPY and B.MSET when they are interrupted during execution can be implemented using the exception block, so these two instructions do not require the encoding of the output register. Therefore, the RegDst0-RegDst2 field segments in the B.MCOPY and B.MSET instruction codes are deleted and replaced with the placeholder value 4’b0000.
+
+Coding before modification:
+
+
+
+Modified encoding:
+
+
+
+In the previous version, the immediate value of template block was encoded as 15 bits (the lower three bits were 0). However, when the instruction was implemented, the 15-bit immediate value could not be expressed in a microinstruction, so the implementation of template block was modified. When the effective bits of the immediate data exceed 12 bits, a combination of three instructions is used to splice the long immediate data in header. Since the modified implementation can handle more than 12-bit immediate numbers, it is better to expand the range of immediate numbers at the same time and encode all 16-31 bits encoded by block instruction as immediate numbers. In this way, 19-bit immediate numbers can be expressed, and the stack space available for instructions is larger. Therefore, adjustments are made to the immediate field segments of the three block instruction codes: template blockfentry, fexit, and ftexit.
+
+Coding before modification:
+
+
+
+Modified encoding:
+
+
+
+After the block instruction encoding is modified, the immediate number in header can express a 19-bit immediate number (the lower three bits default to 0). When the effective digits of the immediate data expressed by header exceed 12 bits, a combination of multiple instructions is used to splice the long immediate data expressed by header. The following uses the F.ENTRY instruction as an example to illustrate this modification:
+
+- Execution method before modification:
+```c
+subi RegPtr, imm, => RegPtr
+
+sd RegSrc0, [RegPtr, -8]
+sd RegSrc1, [RegPtr, -16]
+sd RegSrc2, [RegPtr, -24]
+...
+sd RegSrcn, [RegPtr, -8*m]
+```
+- Modified execution method:
+```c
+if uimm19[18:12] != 0:
+ lui {13'b0 + uimm19[18:12]}
+ addi t#1, uimm19[11:0]
+ sub RegPtr, t#1, => RegPtr
+else:
+ subi RegPtr, uimm19[11:0], => RegPtr
+
+sd RegSrc0, [RegPtr, -8]
+sd RegSrc1, [RegPtr, -16]
+sd RegSrc2, [RegPtr, -24]
+...
+sd RegSrcn, [RegPtr, -8*m]
+```
+
+### Control block instruction encoding adjustment
+
+#### BLBARblock instruction encoding adjustment
+
+In the encoding format of BLBARheader, the high 16 bits of BInst[63:32] are used to encode the input of block instruction, and the low 16 bits are used to encode the output of block instruction. In order to unify the encoding format, the LoadBase0 field segment encoding is changed to the BInst[51:48] position and renamed `RegPtr`. This field segment is used to store the first layer architectural registerID and index the first layer architectural registerR0-R15.
+
+At the same time, the prefetch size of this instruction is based on one Cacheline (64byte), so the BlockSize field segment in the original header encoding is changed to the fixed encoding **2'b01**.
+
+Before coding update:
+
+
+
+After coding update:
+
+
+
+#### BSBARblock instruction encoding adjustment
+
+Before coding update:
+
+
+
+After coding update:
+
+
+
+!!! note "note"
+
+ In order to eliminate the BSBAR blocks before the store instruction: BSBAR 0 format blocks and reduce the occupation of hardware BROB, this instruction prohibits store_count from being 0.
+
+### CSEL/ADDC/SUBC instruction encoding adjustmentThe CSEL/ADDC/SUBC instructions are three-input instructions. In order to simplify the hardware read port design, in the previous version, at the instruction design level, the third source register was limited to the T register, the second source register was limited to the Local GPR, and the first source register was not limited. This achieves the purpose of having at most two T register inputs or at most two Local Reg register inputs at the same time.
+
+In the current version, at the instruction encoding level, the restriction that the second source register is fixed to Local GPR is cancelled, that is, the second source register can be either a T register or a Local GPR.
+
+Previous version encoding:
+
+
+
+Current version encoding:
+
+
+
+## Modification 4. Modification of assembly format
+
+1. Modification of microinstruction assembly format
+
+In the previous version, the model field was added to the encoding format of the prefetch instructions prf and prf.a to indicate which level of cache the instruction prefetched, but the assembly format was not modified. In order for assembly programmers to clearly indicate the cache level of instruction prefetching, the suffix ".l1/.l2/.l3" is added to the assembly names of the prf and prf.a instructions. The prfi.u and prfi.ua instructions are prefetched to the L1 Cache by default. To unify the format, the suffix ".l1" is added to the assembly names of these two instructions. The modified assembly format is as follows:
+
+| Instructions | Original assembly format | Modified assembly format |
+|------|------------------------------------------------|------------------------------------------------|
+| prf | prf [SrcL, srcR<{.sw,.uw}><<] | prf{.l1,.l2,.l3} [SrcL, SrcR<{.sw,.uw}><<] |
+| prf.a | prf [SrcL, SrcR<{.sw,.uw}><<]<, {=>, ->}RegDst> | prf.a{.l1,.l2,.l3} [SrcL, SrcR<{.sw,.uw}><<]<, {=>, ->}RegDst> |
+| prfi.u | prfi.u [SrcL, simm] | prfi.u.l1 [SrcL, simm] |
+| prfi.ua | prfi.ua [SrcL, simm]<, {=>, ->}RegDst> | prfi.ua.l1 [SrcL, simm]<, {=>, ->}RegDst> |
+
+2.block instruction assembly format modification
+
+As mentioned above, the RegDst0-RegDst2 fields are deleted in the encoding of template blockB.MCOPY and B.MSET instructions, so the expressions of RegDst0-RegDst2 are also deleted in the assembly format.
+
+After B.MCOPY modification:
+```
+ b.mcopy [RegSrc0, RegSrc1, RegSrc2]
+```
+After B.MSET modification:
+```
+ b.mset [RegSrc0, RegSrc1, RegSrc2]
+```
+
+## Modification 5, CARGsystem register modification
+
+1. The CARG register deletes the MSG/BGET/BSET field segment.
+2. The setc.msg instruction needs to be replaced by the alias instruction [BSE] (../isa/inst/misa_s/BSE.md).
+3. The current version uses the B.EXCEPTIONexception block to save the BGET/BSET status within the block.
+4. Messages sent within the block are saved in the message buffer register.
+
+Previous version register field segment:
+
+
+
+Current version register field segment:
+
+
\ No newline at end of file
diff --git a/docs/change_log/update_v0.35.md b/docs/change_log/update_v0.35.md
new file mode 100644
index 00000000..b4ff7555
--- /dev/null
+++ b/docs/change_log/update_v0.35.md
@@ -0,0 +1,95 @@
+# Version 0.35 update
+
+Date: December 11, 2023
+
+For the path to the web version of the instruction encoding design document, please see [LinxISA Encoding-v0.35](http://dbox.huawei.com/detaildocs?oid=VR%3Awt.doc.WTDocument%3A100261469689)
+
+## General description of version update
+
+1. The main update of this version of the instruction set is the addition of inline block design.
+2. The LBREFheader`BTextStartOffset` field is multiplexed into the LCONST field.
+3. Encoding adjustment of BLBARblock instruction.
+4. Addc, subc, fmadd instruction encoding adjustment.
+
+## Add inline block
+
+The layered design of the Header Body not only causes the expansion of the CodeSize but also hinders further improvement of performance when faced with smaller Blocks. For this reason, in LinxISA-0.35, we refer to CISC instructions. For small blocks, we directly use Header to express the semantics of microinstructions + jumps at the same time. The benefits of this design are: for small pieces of pure data movement, the efficiency of data movement directly in the Header will be higher. For small blocks that are larger than 2 (32bits) instructions and can be encoded into Inline Block, the benefits of CodeSize will be obtained.
+
+### 1.header encoding
+
+The header encoding of inline block instruction is shown below:
+
+
+
+### 2. Introduction to intra-block microinstructions
+
+- Inline block instruction set uses 12bit encoding space.
+- Microinstructions are embedded in header. Each header can express up to 4 microinstructions and 1 inter-block jump instruction.
+- If the code is less than 4 microinstructions, the inl.nop instruction must be used to occupy the free position.
+- In header, bget/bset does not require explicit declaration.
+- Microinstructions within the block need to be prefixed with `inl.`.
+- Inline blocks can inherit the T register of the previous block.
+
+The inline block microinstruction assembly format and explanation are as follows:| Opcode | Assembly Syntax | Explanation |
+|----------|--------------------------------|---------------------|
+| INL.CONST | inl.const simm8 | Load the sign-extended 8-bit signed immediate number and write it to the destination T register |
+| INL.MOVI | inl.movi simm4, => RegDst | Load 4-bit signed immediate data and write to the destination T register and RegDst register |
+| INL.ADDI | inl.addi RegSrc, simm4 | Calculate the value of the register plus the immediate number and write it to the destination T register |
+| INL.MOVR | inl.movr RegSrc, => RegDst | Copy the value of the source register to the destination T register and RegDst register |
+| INL.LOADI | inl.loadi [t#1, uimm5] | Load the corresponding byte data from the address of the previous instruction result plus the shifted immediate offset and write it to the destination T register |
+| INL.MOVT | inl.movt t#l, => RegDst | The results of the previous 1-4 instructions are written to the destination T register and RegDst register |
+| INL.LOADR | inl.loadr [RegSrc, t#1] | Load the corresponding byte of data from the left source register plus the address memory of the result of the previous instruction and write it to the destination T register |
+| INL.ADD | inl.add RegSrc, t#1, => RegDst | Add the result of the previous instruction to the left source register and write it to the destination T register and RegDst register |
+| INL.BINOPI | inl.binopi t#1, simm4 | Two-input short instruction, one register and one immediate input |
+| INL.LOADI | inl.loadi [t#1, 0], => RegDst | Load the corresponding byte data from the address memory corresponding to the result of the previous instruction and write it to the destination T register and RegDst register |
+| INL.BINOP | inl.binop RegSrc, t#1 | Two-register input short instruction |
+| INL.SUB | inl.sub RegSrc, t#1, => RegDst | Subtract the result of the previous instruction from the left source register and write it to the destination T register and RegDst register |
+| INL.ALLOP | inl.allop t#1, t#r | Instructions containing most of the two T register inputs |
+| INL.MOV2NI | inl.mov2ni simm, => RegDst | Write the immediate number to the Nth power of 2 as the exponent to the destination T register and RegDst register |
+| INL.STORE | inl.store t#2, [RegSrc, t#1] | Write the result of the second previous instruction to the memory where the destination address is located |
+| INL.LD | inl.ld [RegSrc, t#1], => RegDst | Load 8 bytes of data from the source address and write to the destination T register and RegDst register |
+
+
+
+## Control block instructionLBREFheader to add LCONST domain segment
+
+In order to adapt to the inl.lconst, inl.addbpc and other micro-instructions added in the inline block, the **LCONST** field segment reuses the original **BTextStartOffset** field segment of the LBREFheader. That is, when the LBREF block is followed by an Inline Block, this segment is used to store the 32-bit LCONST long immediate number, which can be indexed by the lconst instruction in the following Inline Block.
+
+
+
+## Instruction encoding modification
+
+### 1. Adjustment of BLBAR instruction encoding in control blockAfter version 0.31 updates the encoding of header, the high 16 bits of headerBInst[63:32] are used to encode the input of block instruction (BGET MASK), and the low 16 bits are used to encode the output of block instruction (BSET MASK). In order to unify the encoding format, the LoadBase0 field segment encoding is changed to the BInst[51:48] position in the upper 16 bits. At the same time, it is renamed RegPtr to avoid misleading. This field segment is used to store the first layer architectural registerID and index the first layer architectural registerR0-R15.
+
+In the initial version definition, block_size in BLBARheader encoding: 2’b00 means prefetching data in 32byte units; 2’b01 means prefetching data in 64byte units. But in fact, hardware prefetching is based on Cacheline (64byte), so the BlockSize field segment in the header encoding is changed to the fixed encoding 2'b01.
+
+Before coding update:
+
+
+
+After coding update:
+
+
+
+### 2. ADDC, SUBC, FMADD instruction encoding and semantic adjustment
+
+Like the conditional selection instruction csel, addc, subc and fmadd are also three-register input instructions. In order to simplify the compiler implementation, these instructions cancel the restriction of the second source register in the current version (in previous versions, the R/L before the SrcR field in the instruction encoding was fixedly encoded as 0, that is, SrcR can only index the global register R0 and private registers R1-R15). The csel, addc, subc and fmadd instructions now allow all three register inputs to be T registers. The hardware will split the third T register into a Dummy Local GPR mov plus a normal three-input instruction.
+
+For example, a `csel t#l, t#r, t#c` instruction is split into:
+```asm
+addi t#c, 0, -> r0
+csel t#l, t#r, r0
+```
+where r0 is a hardware-defined Local R0 register.
+
+Coding before modification:
+
+
+
+
+Coding before modification:
+
+
+
\ No newline at end of file
diff --git a/docs/change_log/update_v0.36.md b/docs/change_log/update_v0.36.md
new file mode 100644
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--- /dev/null
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+# 0.36 version update
+
+Update date: December 29, 2023
+
+For the path to the web version of the instruction encoding design document, please see [LinxISA Encoding-0.36](https://dbox.huawei.com/detaildocs?oid=VR%3Awt.doc.WTDocument%3A100298001623)
+
+## General description of version update| Change items | Change content | Reason for change |
+|------------|---------------------------------|----------------------------------|
+| header encoding | BrTypeExtend: 4bit->3bit; BlockOpcode: 7bit->8bit. | Reduce decoding complexity. |
+| Standard Block | 1. BrTypeExtend of ECALL jump block: 4'b1011->3'b101;
2. BrTypeExtend of ERET jump block: 4'b1100->3'b110. | header encoding is adjusted uniformly to reduce decoding complexity; reserve space is reserved. |
+| Standard block stdlp | 1. Added new standard block stdlp: BlockType: 3'b001;
2. No bitmask (default is all 1), extended field lengths such as BText/BNext Offset;
3. Added BranchHint field segment;
4. Added Likely BNextOffset to IND and INDCALL blocks for jump prediction. | 1. Expand the length of fields such as BText/BNext Offset to reduce the number of lbref blocks;
2. Add the BranchHint field segment for branch and jump prediction enhancement. |
+| Standard Super Block stdh | BlockType: 3'b001 -> 3'b010. | To remain consistent with the 6188 implementation version, the BlockType of the stdlp block is set to 3'b001, so the BlockType of the stdh block is adjusted to 3'b010. |
+| Standard floating-point block fp | Floating-point Block | 1. The standard floating-point block supports intra-block jump instructions;
2. Delete the floating-point super block fph. | Standard floating point blocks and floating point super blocks are combined into one block to save coding space. |
+| Inline Block Inline Block | BlockType: 3'b110 -> 3'b101. | header encoding is adjusted uniformly to reduce decoding complexity. |
+| template blockTemplate Block | 1. BlockType: 3'b111 -> 3'b110;
2. Add SrcVld and DstVld domain segments;
3. The BLBAR block is adjusted from controlling block type to template block;
4. mpush/mpopheader adds MemBitMask and signed imm fields. | 1. header encoding is adjusted uniformly to reduce decoding complexity.
2. The BLBAR block itself is a template instruction, so it is adjusted to template block.
3. mpush/mpop is modified to be used for push/pop of discontinuous memory to improve the efficiency of data processing. |
+| Complex CISC blocks | Added 5 new types of CISC blocks: B.MOV, B.ADD, B.LJMP, B.COND, B.CALL | Only used to reserve encoding space. |
+| System Block System Block | 1. header encoding removes the bitmask, which is used for long indexes and long jump offsets;
2. Add ECALL blocks and ERET blocks.
3. The system block supports intra-block jump instructions and deletes the system super block sysh. | 1. Same as standard block stdlp
2. Add ECALL and ERET: in order to maintain alignment with version 6188 1.0. || Control Block | 1. The BNextOffset domain range of the LBREF block is reduced to 16 bits;
2. Delete the BSBAR block, and the StoreBarrier feature is placed in LBREFheader;
3. Remove the BLBAR block and add it to the template block type. | The StoreBarrier feature is placed on LBREFheader, which can significantly reduce Codesize. |
+| Newly added microinstructions | 1. Added new comparison and jump microinstructions: setc.and and setc.or. | 1. Statistics show that Specint accounts for 5% and is a hot scene command. Using this compound instruction can effectively reduce Codesize. |
+| Delete instructions | Inline block microinstructions delete inl.lconst/inl.lconstu/inl.addbpc and other instructions. | The statistics are incorrect. inl.lconst/inl.lconstu/inl.addbpc is a false hotspot instruction, so it is removed. |
+| system register | 1. system register adds: CID (physical core ID) and SYSCNT (local timestamp);
2. Modify the register ID of system registerBREF to 0x000F;
3. Modify the register ID of system registerCYCLE to 0x0C00. | 1. Product OR requirements;
2. The original BREF register ID conflicts with the added CID register ID.
3. Keep consistent with the 6188 landing version. |
+
+## Change details
+
+### 1.header encoding unified adjustment
+
+In version 0.36, the BrTypeExtend field of header encoding is adjusted from the original 4bit to 3bit, and the BlockOpcode field is adjusted from the original 7bit to 8bit.
+
+Version 0.35 header encoding format:
+
+
+
+Version 0.36 header encoding format:
+
+
+
+### 2. Standard block std
+
+To adapt to the unified adjustment of header encoding, the BrTypeExtend encoding of ECALL and ERET blocks in the standard block is modified as follows:
+
+ECALL block: **4'b1011** modified to **3'b101**; ERET block: **4'b1100** modified to **3'b110**
+
+Version 0.35 ECALL and ERET block encoding:
+
+
+
+Version 0.36 ECALL and ERET block encoding:
+
+
+
+### 3. Add standard block stdlp
+
+Standard block stdlp (Standard Block with Long Pointer): headerbody of the standard block is separated and has no bitmask (the default bitmask is all 1). It is mainly used to jump and identify the range of block instruction.
+
+- Microinstructions within the block use 32bit encoding space.
+- The range of BTextStartOffset is extended to **26bit**, the range of BNextOffset is extended to **25bit**, and the range of BEndOffset is extended to **10bit**.
+- The LikelyBNextOffset field is added to the two jump type blocks of IND and INDCALL, and the range is extended to 22bit for jump prediction.
+- Added the BranchHint field, which is used to jump to information prompts. For specific definitions, see the table below.
+
+
+
+headerBranchHint field segment description
+
+
+
+### 4. Standard super block stdhIn order to remain consistent with version 6188-1.0, the BlockType of the stdlp block is set to 3'b001, so the BlockType of the stdh block is adjusted to **3'b010**.
+
+Version 0.35 stdh block encoding:
+
+
+
+Version 0.36 stdh block encoding:
+
+
+
+### 5. Standard floating point block
+
+In order to save block instruction encoding space, in this version we choose to delete the standard floating point super block fph, leaving the standard floating point block fp. At the same time, it is defined that the standard floating point block supports intra-block jump instructions, that is, in terms of the function of the block engine, the current version of the fp block is equivalent to the previous version of the fph block, but the encoding space of the previous version of the fp block is still used.
+
+Version 0.36 fp block encoding:
+
+
+
+### 6. Inline block modification
+
+The BlockType of the inline block block instruction is adjusted from **3'b110** to **3'b101**.
+
+Version 0.36 inline block header encoding:
+
+
+
+### 7.template block adjustment
+
+- Unified modification of template block encoding:
+ * The BlockType of template blockblock instruction is adjusted from 3'b111 to 3'b110.
+ * Unified adjustment to adapt to header encoding: BrTypeExtend field (header[8:5]->header[7:5]) is changed from 4bit to 3bit.
+ * Add SrcVld and DstVld field segments to quickly determine dependencies between blocks and reduce hardware decoding complexity.
+- FENTRY, FEXIT, FTEXIT block: After adding the encoding space of SrcVld and DstVld, the position conflicts with unsigned imm[18:11] of the immediate high bit, so the position of the immediate high bit is adjusted.
+- The jump type of the FTEXIT block is adjusted to the IND (Indirect) type (3’b100 -> 3’b010). This modification is used to improve the accuracy of hardware RAS jump prediction.
+- BLBAR block changed from controlling block type to template block:
+ * BlockOpcode changed from **4'b0001** to **4'b0010**.
+ * After uniformly increasing the coding space of SrcVld and DstVld, the coding positions of fields such as prefetch_count/offset/prefetch Model were adjusted.
+ * MPUSH/MPOP adds the MemBitMask field for push and pop of discontinuous memory; adds the Store/Load Offset (i.e. igned imm) field for the offset of address calculation.
+
+Version 0.35 template block encoding:
+
+
+
+Version 0.36 template block encoding:
+
+
+
+Additional modifications:
+
+#### template blockFEXIT Adjustment
+
+FEXIT modified usage scenario
+
+Scenario 1: The function ends with a function call f.exit+bnext.direct
+```c
+extern int add(int, int);
+int f1(int a, int b) {
+return add(a, b);
+}
+```
+Scenario 2: The function ends with a function pointer call f.exit+bnext.indirect
+```c
+extern int add(int, int);
+extern int sub(int, int);
+int f2(int a, int b, int cond) {
+int (*functionPtr)(int, int);
+functionPtr = cond > 0 ? add : sub;
+return functionPtr(a, b);
+}
+```
+FEXIT instruction encoding adjustment
+
+The jump type is changed from Return to Fall, and the BrTypeExtend field encoding is changed to 3’b001.
+
+Original code:
+
+
+
+Updated coding:
+
+
+
+Modify the microinstruction sequence of FEXIT block expansion
+
+The jump type is changed from the original Return to the Fall type, so there is no need to set CARG.TGT in the block, that is, the setc.tgt instruction expanded in the block is deleted.Take the microinstruction sequence expanded by block instruction f.exit [ra, s0, s1, s2, s3, s4, s5], sp!, 144 as an example:
+```asm
+addi sp, 144, => sp
+ldi [sp, 136], => ra
+setc.tgt t#1 ------->去掉该指令
+ldi [sp, 128], => s0
+ldi [sp, 120], => s1
+ldi [sp, 112], => s2
+ldi [sp, 104], => s3
+ldi [sp, 96], => s4
+ldi [sp, 88], => s5
+```
+
+2. Adjustment of template blockFTEXIT
+
+The FTEXIT instruction name is changed to **FRET**, and the assembly identifier is `f.ret`.
+
+FRET(FTEXIT) is adjusted to be used in the scenario of normal return at the end of the function:
+
+Scenario 1: The function ends with ret normally, and there are no sub-functions inside the function, f.ret (RA reads directly)
+```c
+extern int symbol;
+int f3() {
+return symbol;
+}
+```
+Scenario 2: The function ends with ret normally, and there are sub-functions inside the function, f.ret (RA loads from the stack)
+```c
+# include "stdio.h"
+extern int symbol;
+int f4(int a, int b) {
+printf("Linx\n");
+return symbol;
+}
+```
+
+FRET (FTEXIT) encoding adjustment
+
+* The FRET block jump type is changed from IND (indirect) to RETURN, and the BrTypeExtend field encoding is changed to 3’b100.
+* The default encoding of the RegRet field segment is 4’b0000 (corresponding to the Ra/R0 register)
+* srcvld[1] is modified to be codable: encoding is 1, indicating that the instruction input contains the Ra register; encoding is 0, indicating that the instruction input does not include the Ra register.
+
+
+
+Updated coding:
+
+
+
+3. Modification of assembly syntax
+
+Original assembly format: `f.texit [RegDst0, RegDst1, RegDst2, ..., RegDstn], RegPtr!, RegRet, uimm19`
+Modified assembly format: `f.ret [RegDst0, RegDst1, RegDst2, ..., RegDstn], RegPtr!, , uimm19`
+
+ in assembly format: Indicates whether Ra is optional as block instruction input. That is:
+
+`f.ret [RegDst0, RegDst1, RegDst2, ..., RegDstn], RegPtr!, Ra, uimm19` indicates that the instruction input includes the RegPtr and Ra registers, and the return address is obtained by directly reading the Ra register.
+`f.ret [RegDst0, RegDst1, RegDst2, ..., RegDstn], RegPtr!, uimm19` means that the instruction input is only the RegPtr register, and the return address is loaded from the stack.
+
+Adjustment of FRET block microinstruction expansion sequence
+
+If header.vld is marked as 1, it means directly reading the Ra register value as the return address. The corresponding microinstruction expansion sequence takes block instruction `f.ret [s0, s1, s2], sp!, ra, 24` as an example:
+```asm
+setc.tgt ra
+addi sp, 24, => sp
+ldi [sp, 16], => s0
+ldi [sp, 8], => s1
+ldi [sp, 0], => s2
+```
+If the header.vld mark is 0, it means that the instruction input does not contain Ra, and the return address needs to be loaded from the stack (at this time, bsetmask bit[0] needs to be set).
+The corresponding microinstruction expansion sequence takes block instruction `f.ret [ra, s0, s1, s2], sp!, 32` as an example:
+```asm
+addi sp, 32, => sp
+ldi [sp, 24], => ra
+setc.tgt t#1
+ldi [sp, 16], => s0
+ldi [sp, 8], => s1
+ldi [sp, 0], => s2
+```
+
+template block modified encoding
+
+
+
+### 8. Added complex CISC blocks
+
+The new CISC block BlockType uses **3'b110** encoding space and shares this space with template block.
+
+
+
+### 9. System block modification
+
+1. System block instruction adds two jump type blocks, ECALL and ERET, among which the ECALL block is used to end the program.
+2. The system header encoding removes the bitmask and adds long index and long jump offset encoding space.
+3. The BranchHint field is added to the system block header, and the definition is the same as described in the previous standard block stdlp.
+4. Delete the system super block sysh
+
+Note: The system block does not support inter-block jumps other than the FALL type, but supports intra-block jumps (when accessing system register, spin lock, CMO instructions, if a jump instruction is required, intra-block jumps can be used).
+
+
+
+### 10. Control block encoding adjustment
+
+In order to reduce hardware Load/Store conflicts, version 0.33 adds a BSBAR block in the control block type. In this way, a BSBAR block needs to be added before all blocks containing store instructions. If the jump offset or index offset of the block is not enough, an LBREF block needs to be added before the block to store the additional offset, which causes the code size to expand.Therefore, in version 0.36, we deleted the encoding of BSBARblock instruction, retained its characteristics, and placed the characteristics of BSBAR on LBREFheader. The specific modifications to LBREF are as follows:
+
+1. Added the store_count and SpecType fields of the original BSBARheader (using space Header[15:10] and Header[9:8] respectively)
+2. Reduced the space of BNextOffset field from the original 23bit to **16bit**.
+
+Coding before update:
+
+
+
+Updated coding:
+
+
+
+### 11. New microinstructions
+
+Add a system block instruction[DC.ZVA](../isa/inst/misa_s/DC.ZVA.md) to clear the cacheline.
+
+### 12. Delete command
+
+Version 0.35 is updated and released with the inline block and the 120+ microinstructions it supports.
+
+However, during subsequent verification, it was found that i**nl.lconst**, **inl.lconstu**, and **inl.addbpc** were false hotspot instructions. At the same time, the hardware's processing of these instructions was relatively complex, so these three instructions were removed from the current version.
+
+### 13.Changes of system register
+
+- In order to meet product OR requirements, add two system register:
+ * CID (Physical Core ID) - SSR ID is **0x0030**
+ * SYSCNT (local timestamp) - SSR ID is **0x0C01**
+- Modify the original register ID:
+ * The SSR ID of the original BREF register conflicts with the new CID register. In order to be consistent with the 6188 landing version, the ID of the BREF register is modified to 0x000F.
+ * In order to be consistent with the 6188 landing version, modify the ID of the CYCLE register to **0x0C00**.
\ No newline at end of file
diff --git a/docs/change_log/update_v0.40.md b/docs/change_log/update_v0.40.md
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+# Version 0.40 update
+
+Update date: June 5, 2024
+
+For the path to the web version of the instruction encoding design document, please see [LinxISA Encoding-0.40](https://dbox.huawei.com/detaildocs?oid=VR:wt.doc.WTDocument:100421282855)
+
+Problems to be solved by LinxISA V0.40:
+
+1. V0.3X architecture scalability problem: fixed-length 64bitheader cannot expand registers and other description information.
+2. V0.3X instruction encoding problem: headerbody does not share a set of encoding, causing the hardware and compiler implementation complexity to be too high.
+3. V0.3X codesize problem: The instruction expansion caused by header is too large, about 50% compared to ARM.
+
+## General description of version update
+
+- **architectural state/ABI changes**
+
+| Change content | Reason |
+|----------------------------------|----------------------------------|
+| 1. The first layer architectural registerUL_GPR is increased to 24 | Optimize the register allocation algorithm, reduce the Spill overhead of block instruction, and improve performance. |
+| 2. Deleting LL_GPR in the second layer architectural register | LL_GPR will significantly increase the complexity of hardware renaming. |
+| 3. The T register index distance in the second layer architectural register is reduced to 4 | T#5-T#8 has a low usage rate and takes up hardware ROB space. |
+| 4. Add U relative index register in the second layer architectural register, the index distance is 1-4 | Enable long-distance relative index, greatly reducing the number of copy instructions. |
+| 5. Modify the register mapping relationship: R1 maps to SP, R2 to R9 maps to A0 to A7, R10 maps to RA | Adapt to the new version of fentry, fexit, fret and other template block designs. |
+
+- **block instruction form**
+
+Added architecture definitions for integrated blocks and separate blocks. An integrated block can significantly eliminate header overhead, and small blocks can reduce the information redundancy of header.
+
+Note: Version 0.40 only supports one block definition
+
+- **header encoding reconstruction**
+
+The header encoding is completely reconstructed and split into header composed of multiple 16bit and 32bit instruction descriptors. By splitting the 64-bit fixed-length header into multiple header instruction combinations, the amount of program code can be effectively reduced and the expansion capability of header can be enhanced.
+
+| header instruction | List |
+|--------|----------|
+| Added 16bitheader instruction | C.BSTART of general block, C.BSTART, C.LBREF, C.BSTOP of hotspot scalar block |
+| Added 32bitheader instruction | BSTART of general block, BSTART, LBREF, BATTR, BSTOP of hotspot scalar block |
+| Template instructions changed to 32bit encoding | MCOPY, MSET, FENTRY, FEXIT, FRET.RA, FRET.STK (MPUSH, MPOP, BLBAR are not supported in the current version) |
+
+- **DELETED block instruction**
+
+Remove Inline Block and BSBAR blocks. Inline instruction design is not efficient enough. In most scenarios, there are only 1-2 microinstructions in the Inline block.
+
+- **Microinstructions**
+
+The microinstruction coding is completely reconstructed, the definition of existing instructions remains unchanged, and all coding is adjusted. The microinstruction coding space is shared with the header coding space, which is conducive to disassembly and hardware decoder implementation, making the execution environment safer.
+
+After upgrading to version 0.4, the microinstruction encoding method is adjusted as follows:1. Since headerbody is coded together, the lower 7-bit Opcode field of the original 32-bit instruction is adjusted.
+2. After deleting LL_GPR, the input/output register field is changed to 5bit unified encoding.
+3. Extend the shamt domain of instructions such as add to support a wider range of offsets.
+4. Registerless output instructions do not occupy the T register slot, reducing register allocation.
+5. Cancel the restriction of three-input instructions. For specific three-input instructions, one of the inputs is no longer required to be fixed to the T register in the block.
+6. The M and N parameters of the bit field insertion instruction bfi are changed to be encoded with byte granularity.
+7. The SrcRType field is added to the cmp and setc instructions to extend the instruction implementation.
+8. Due to the limitation of encoding format, the floating point instruction FCVT is split into multiple instructions.
+9. Following the ABI changes, the encoding method of the instruction input/output register has been adjusted.
+
+The list of microinstructions added or deleted in the current version is as follows:
+
+| Command List | Reason |
+|--------|----------|
+| **New 32bit instruction** | |
+| 1. addpc
2. cmp.and, cmp.or, cmp.andi, cmp.ori
3. setc.and, setc.or, setc.andi, setc.ori, setc.tgt
4. bic, bis, ccatw
5. madd, maddw
6. tc.iva, tc.iall
7. lr.b, lr.h, sc.b, sc.h, swapb, swaph | 1. Based on the codesize analysis of the compiler and model team, new instructions are used to reduce the amount of program code.
2. tc.iva, tc.iall are the operating system OS kernel development requirements. |
+| **New 16bit instruction** | |
+| 1 movr, movi
2. c.add, c.sub, c.and, c.or
3. c.addi, c.slli, c.srli
4. c.setc.eq, c.setc.ne
5. c.lwi, c.ldi, c.swi, c.sdi
6. c.cmp.eqi, c.cmp.nei
7. sext.b, sext.h, sext.w, zext.b, zext.h, zext.w
8. c.ssrget, c.addpc, c.addtpc | Add 16bit length C extension instructions to reduce Codesize and improve performance. |
+| **Name Adjustment Command** | |
+| 1. The name of the concat instruction is changed to ccat
2. The name of the rev instruction is changed to rev64 | Standardized instruction naming |
+| **The current version does not implement the command** | |
+| 1. mulh, mulhu
2. load.a, load.ua classes
3. addc, subc
4. casw, casd
5. gqm class and Cache maintenance instructions in the system block | The current version does not support dual output instructions, and system instructions such as gqm will be determined in later versions |
+| **Removed microinstructions** | |
+| 1. addbpcf, addbpcn
2. setc.trap, setc.msg
3. ssrcrlt
4. tlbget, tlbset, tlbi | Based on the architectural changes in version 0.40, some instructions are no longer used and therefore deleted. |
+
+## Change details
+
+### 1. architectural state changes
+
+The first layer architectural registerUL_GPR is increased to 24: R0 to R23. The dynamic instruction number benefit brought by increasing the number of GPRs in the SPEC test program is as shown in the figure below:
+
+
+
+As can be seen from the above figure, adding 8 GPRs can effectively reduce the number of dynamic instructions in the SPEC test program, and using two sets of relative index registers within the block brings greater benefits.Second layer architectural register modification:
+
+1. Delete LL_GPR of block-private;
+2. The number of relative index T registers is reduced to 4, and each instruction can index the results of the previous 4 instructions output to the T queue;
+3. Add 4 relative index U registers. Each instruction can index the results of the previous 4 instructions output to the U queue.
+
+| Register name | Register alias | Explanation |
+|-----------|-----------|--------|
+| TR1 | T#1 | The first instruction result output to the T queue in the previous sequence |
+| TR2 | T#2 | The result of the second previous instruction output to the T queue |
+| TR3 | T#3 | The result of the third previous instruction output to the T queue |
+| TR4 | T#4 | The result of the fourth previous instruction output to the T queue |
+| UR1 | U#1 | The first instruction result output to the U queue in the previous sequence |
+| UR2 | U#2 | The result of the second previous instruction output to the U queue |
+| UR3 | U#3 | The third instruction result output to the U queue in the previous sequence |
+| UR4 | U#4 | The result of the fourth previous instruction output to the U queue |
+
+The T register and the U register are indexed independently. The example is as follows:
+
+```asm
+ldi [a0, 0], ->t # inst0，指令结果写到T队列
+ldi [a1, 0], ->t # inst1，指令结果写到T队列
+ldi [a0, 8], ->u # inst3，指令结果写到U队列
+ldi [a1, 8], ->u # inst4，指令结果写到U队列
+addi t#2, t#1, ->t # 索引inst0和inst1的指令结果
+sd t#1，[a2, 0] # 指令无寄存器输出
+addi u#2 u#1, ->u # 索引inst3和inst4的指令结果
+sd u#1，[a2, 8] # 指令无寄存器输出
+```
+Assembly example of instruction output:
+
+- Instruction without register output: `Opcode SrcL, SrcR`
+- Instructions are output to the T queue: `Opcode SrcL, SrcR, ->t`
+- Instructions are output to the U queue: `Opcode SrcL, SrcR, ->u`
+- The command is output to the first layer architectural register: `Opcode SrcL, SrcR, =>a0`
+
+### 2. Change of instruction encoding space
+
+The instruction encoding space and characteristics are as follows:
+
+headerbody unified encoding, the encoding length uses 16bit and 32bit.
+
+
+
+Symbol description:
+
+- Size: Instruction word length, 0: 16bit instruction; 1: 32bit instruction.
+- L/Layer: Instruction level, 0: header instruction coding space; 1-3: Microinstruction coding space
+- Opcode: instruction operation code
+
+The combination space distribution is as follows:
+
+- Size=0: 16bit instruction
+ - layer=0 : 16bitheader instruction
+ - layer=1 : 16bitbody microinstruction
+- Size=1: 32bit instruction
+ - layer=0 : 32bitheader instruction
+ - layer=1-3: 32bitbody microinstructions
+
+### 3. header instruction changes
+
+The header encoding is completely reconstructed, introducing the concept and design of variable-length header, and splitting it into multiple header combinations of 16bit and 32bit instruction descriptors.
+
+The so-called variable length header encoding, in layman's terms, means splitting the entire information description field contained in header, and then combining some of the field segments into multiple block description instructions, which can be 16 bits long or 32 bits long. Therefore, in the new version, a header instruction is composed of multiple 16 or 32bit block descriptor instructions. The total encoding length of header is not fixed and is called variable length header.
+
+For an integrated block, the **header description instruction must precede the body instruction**. Decoding to the body instruction indicates the end of the current header description instruction.
+
+1. **New BSTART instruction**
+
+BSTART instruction semantics: Submit the previous block instruction and open the current block. BSTART is an instruction that must exist in block instructionheader and is also the first instruction in block instruction.The current version is designed with two BSTART instructions. One supports the full range of block type and jump type instructions for general scenarios. The other is an instruction mainly used for offset class jumps and block type defaults to the scalar block, also known as the hot scalar block.
+
+16bit BSTART：
+
+
+
+32bit BSTART：
+
+
+
+- BlockType field: used to encode block type.
+- DCP bit: integrated block and separated block flag bit: 0 represents an integrated block, 1 represents a separated block (the current version is fixedly coded as 0)
+- BrType field: used for encoding jump type: **0 is invalid encoding**.
+- PayLoad: When the jump mode is offset type jump, this field is used to encode the jump distance; other jump types are temporarily reserved.
+
+2. Added BATTR instruction
+
+The BATTR block is used to describe the attribute information of a block. The encoding is as follows:
+
+
+
+- T: Block submission trap flag T-trap, set to 1: indicates that the current block instruction will generate a trap after submission.
+- R: block instruction relay flag R-relay, set to 1: the private register of the current block is inherited to the next block instruction, otherwise it is not inherited.
+- F: exception normal processing flag F-fixup, some exception low privilege level processing.
+- H: Super block mark H-hyper, set to 1: indicates that jump instructions within the block are supported; otherwise, it is not supported.
+- atom: Atomic block flag bit, indicating that the current block is an atomic block.
+- far: Send the current block to multi-core remote execution.
+- aq/rl: identifies the fence attribute between block instruction.
+
+3. Added LBREF instruction
+
+The LBREF block is only used to express jump offsets between blocks. This instruction has two encoding formats, 16bit and 32bit.
+
+
+
+Jump offset reference instruction LBREF. The BNextOffset field in its encoding is used to splice with the BNextOffset in the subsequent BSTART/C.BSTART instructions to form a complete BNextOffset field.
+
+LBREF instruction description:
+
+- In storage logic, the lbref instruction of a block always precedes the bstart instruction.
+- If a block contains the lbref instruction, the hardware will use lbref as the starting instruction of the block.
+- 16bit and 32bit bstart and lbref instructions can be freely combined, for example: `c.lbref + c.bstart`, `c.lbref + bstart`, `lbref + c.bstart`, `lbref + bstart`.
+
+4. Added BSTOP instruction
+
+The lowest bit is 0 or 1, and the remaining bit codes are all 0, which is an invalid instruction. It is also used as a BSTOP instruction and can be used to submit the current block instruction.
+
+
+
+5. Added template block
+
+The design of template block is introduced to reduce CodeSize and improve performance. The template block instruction is defined as a block start instruction, which is used to submit the previous block instruction and open the current block. The Opcode for each template block acts as a special "BSTART", template blockheader describes the input/output of block instruction, and other implementation requirements.
+
+
+
+Instruction design description:
+
+- **MCOPY/MSET instruction**: Input instructions for three registers. The three inputs are transmitted using the first layer architectural registerRegSrc0, RegSrc1 and RegSrc2 respectively, where:| Memory copy instruction MCOPY | Memory assignment instruction MSET |
+|------------------|------------------------|
+| RegSrc0: used to transfer the destination memory address | RegSrc0: used to transfer the destination memory address |
+| RegSrc1: used to pass the source memory address | RegSrc1: used to pass the source data |
+| RegSrc2: used to pass the number of bytes copied | RegSrc2: used to pass the number of bytes assigned |
+
+- **FENTRY instruction**: This instruction is used to open the stack at function entry, **implying the input/output information of the stack pointer register sp**.
+- **FEXIT, FRET.RA, FRET.STK instructions**: These three instructions are used for the stack operation at function exit, and also **imply the input/output information of the stack pointer register sp**.
+
+The stack space size is encoded in unsigned immediate unsigned imm[14:3], in units of 8 Byte. The register information pushed onto the stack is expressed through SrcBegin and SrcEnd. SrcBegin and SrcEnd represent a continuous register in the first-level registers R0-R23. For example, if R2, R3, R4, R5, and R6 are pushed onto the stack, SrcBegin will be encoded as R2 and SrcEnd will be encoded as R6.
+
+The three stack stack instructions correspond to different scenarios of function exit, specifically:
+
+- The FEXIT instruction is used in scenarios where the function ends with a function call (including function pointer call), and the jump type defaults to Fall.
+- The FRET.RA instruction is used in scenarios where the function returns normally and there are no sub-functions inside the function. The return address is obtained by directly reading the Ra register. The default jump type is Return.
+- The FRET.STK instruction is used in scenarios where the function returns normally and there are sub-functions inside the function. The return address needs to be loaded from the stack, and the jump type defaults to Return.
+
+The assembly format is as follows:
+
+| Template instructions | Assembly format | Default jump method | Notes |
+|-----------|-----------|-----------|-----------|
+| MCOPY | b.mcopy [RegSrc0, RegSrc1, RegSrc2] | Defer Fall Through | Source and destination addresses do not overlap |
+| MSET | b.mset [RegSrc0, RegSrc1, RegSrc2] | Defer Fall Through | None |
+| FENTRY | f.entry [RegSrc0 ~ RegSrcn], sp!, uimm | Defer Fall Through | Imply sp register as input and output |
+| FEXIT | f.exit [RegDst0 ~ RegDstn], sp!, uimm | Defer Fall Through | Implicit sp register as input and output |
+| FRET.RA | f.ret.ra [RegDst0 ~ RegDstn], sp!, uimm | Return | Implies sp register as input and output |
+| FRET.STK | f.ret.stk [RegDst0 ~ RegDstn], sp!, uimm | Return | Implies sp register as input and output |
+
+6. Delete block instruction
+
+Remove Inline Block and BSBAR blocks.
+
+Inline instruction design is not efficient enough. In most scenarios, there are only 1-2 microinstructions in the Inline block. Therefore, delete the original Inline design and change the block structure form into an integrated block (dynamic Inline block)
+
+### 4. Microinstruction changes
+
+Based on the codesize analysis summary led by the compiler team and the analysis data of the model team, the following instructions are added to reduce the codesize gap with other architectures.
+
+1. Add movr/movi command
+
+The command encoding is as follows:
+
+Movr: Register movement, moves the source register value to the destination register, SrcL and RegDst can be repeated.
+Movi: Move immediate data, move immediate data in the range [-16,15] to registers R1-R23 or T/U queue.
+
+2. Add C.ADDPC instruction
+
+The c.addpc instruction is used to record the return address in a CALL type block. c.addpc is the alias instruction of movi. The instruction encoding is as follows:
+
+
+
+The output of the c.addpc instruction is fixed to the RA register, and the immediate value field is used as a signed immediate value.
+
+3. Add cmp and setc instructions
+
+Added cmp.{and, or, andi, ori} and setc.{and, or, andi, ori} commands
+
+
+
+cmp.and: RegDst = SrcL & SrcR
+cmp.or: RegDst = SrcL | SrcR
+
+
+
+cmp.andi: RegDst = SrcL & simm12
+cmp.ori: RegDst = SrcL | simm12
+
+
+
+setc.and: setc.flag = SrcL & SrcR
+setc.or: setc.flag = SrcL | SrcR
+
+
+
+cmp.andi: setc.flag = SrcL & simm
+cmp.ori:setc.flag = SrcL | simm
+
+4. Add BIC/BIS instructions
+
+In a large number of scenarios, we need to clear the lower 3 bits, lower 4 bits or lower 5 bits of the data. The original method is to use left shift and then right shift (or a combination of multiple instructions). After adding the BIC instruction, it can be implemented with one instruction.
+
+
+
+The following are the comparison results provided by the compiler team in the summary of comparative analysis between LinxISA and ARM codesize:
+
+
+
+5. Add MADD/MADDW instructions and MIADD/MISUB instructions
+
+Added multiply-accumulate instructions MADD/MADDW and multiply-add-multiply-subtract instructions with immediate values.
+
+
+
+| Command | Operation |
+|---------|----------------|
+| MADD | RegDst = SrcD+SrcL*SrcR |
+| MADDW | RegDst = SignExtend((SrcD+SrcL*SrcR)[31:0]) |
+| MIADD | RegDst = SrcL + SrcR * uimm |
+| MISUB | RegDst = SrcL - SrcR * uimm |
+
+The following are the comparison results provided by the compiler team in the analysis summary of LinxISA and ARM codesize:
+
+
+
+6. Add CCATW command
+
+
+
+Semantics: The lower 32 bits of the two source registers are concatenated and circularly shifted. The lower 32 bits and upper 32 bits of the result are sign-extended and written to RegDst and T respectively.
+
+7. Add TC.IVA/TC.IALL instructions
+
+This instruction is added to meet the operating system OS kernel development needs, and is coded as follows:
+
+TC.IVA instruction semantics: Invalidate the cache line copy where the memory address SrcL is located from the Translation Cache.
+TC.IALL instruction semantics: Invalidate the cache line copy contained in the Translation Cache.
+
+8. Add LR/SC/SWAP instructions
+
+Added LR/SC/SWAP instructions to operate in bytes and halfwords.
+
+
+
+| ATOMIC_SIZE | LR class instructions | SC class instructions | SWAP class instructions |
+|---|---|---|---|
+| 0 | LR.B | SC.B | SWAPB |
+| 1 | LR.H | SC.H | SWAPH |
+| 2 | LR.W | SC.W | SWAPW |
+| 3 | LR.D | SC.D | SWAPD |
+
+9. Add setc.tgt and addpc instructions
+
+Add the encoding of setc.tgt and addpc instructions in the 32bit public instruction space.
+
+
+
+addpc is an alias instruction of addtpc, the RegDst field is fixedly encoded as RA, and only the upper 12 bits of the immediate data field are valid.
+
+
+
+The SrcR field of the setc.tgt instruction is encoded as all zeros.
+
+10. Add C extension instructions
+
+According to the instruction usage popularity, the following 16-bit microinstructions are added to reduce the Codesize and improve performance in some scenarios.
+16bit microinstructions are basic instructions and can be used in any block type and body.
+
+
+
+Among the above instructions, special attention needs to be paid to the C.SSRGET instruction, whose SSRID requires an independent set of encoding. The encoding and decoding mapping relationship is as follows:
+
+
+
+Currently, only the commonly used TP, GP, and CP register codes have been added, and other spaces are temporarily reserved.
+
+---
+
+### Instruction encoding adjustment
+
+**Adjustment 1: Adjustment of the lower 7-bit Opcode field of the original instruction**
+
+The lower 7 bits of the current version of the instruction encoding contain three types of information:
+
+**MInst[0]**: Instruction length field Size, Size=0 indicates a 16-bit length instruction; Size=1 indicates a 32-bit length instruction.
+**MInst[2:1]**: Instruction level field Layer, Layer=0b01 and 0b10 belong to the public instruction encoding space; Layer=0b11 belongs to the private instruction encoding space (private space for each block type).
+**MInst[6:3]**: Instruction opcode Opcode.
+
+**Adjustment 2: Input/output register field adjustment**
+
+The R/L and Src fields in previous versions are merged and 5bit is coded together. Merge the G/L and RegDst fields in previous versions, and use 5 bits to code together.
+Version 0.3x:
+
+
+
+0.4x version:
+
+
+
+**Adjustment 3: Extend shamt domain**
+
+For add/sub/and/or/xor/load type instructions, extend the shamt field to 5 bits to meet the needs of large structs in programming languages and address offset shifts exceeding 3 bits.
+
+
+
+**Adjustment 4: No register output instructions**
+
+Registerless output instructions do not occupy the T register slot:
+
+setc class, intra-block jump class, ssrset, ssrwr, store does not update address class, prf class, execution control class (trap, bwe, etc.), Cache management class instructions do not occupy T register slot.
+
+**Adjustment 5: Three-input cancellation restriction**Three-register input instructions such as CSEL have no limit on the input register, which can be up to 3 GPR or 3 T REG or 3 S REG.
+
+
+
+**Tweak 6: SSRGET/SSRSET instructions within scalar block**
+
+In order to unify the encoding format and reduce the decoder complexity, adjust the SSR-ID of the SSRGET/SSRSET instructions in the scalar block to 12bit.
+At the same time, in order to adapt to the adjustment of the addpc command, the opcode field of the ssrget/ssrset command is modified: 4b1100 -> 4b1111
+
+
+
+**Tweak 7: SSRGET/SSRSET instructions within system blocks**
+
+The names of the SSRGET/SSRSET instructions in the system block are modified: SSRGET is changed to SSRRD; SSRSET is changed to SSRWR.
+
+
+
+#### Adjustment 8: CONCAT directive
+
+CONCAT name changed to CCAT.
+
+
+
+#### Adjustment 9: BFI command
+
+BFI changes to Byte as the granularity.
+
+The original instruction encoding is relatively special and requires a separate hardware decoding implementation, which increases the decoding complexity. Therefore, modify its granularity to BYTE, and the modification will make the processing of strings very efficient.
+Modify the instruction semantics as follows: intercept the lower N bytes from the right source register, replace the Mth to M+N-1th bytes of the left source register, and write the result to the destination register.
+
+
+
+**Tweak 10: SETC.TGT directive**
+
+SETC.TGT is added to the 16bit compressed instruction space.
+
+
+
+**Adjustment 11: CMP/SETC class instructions**
+
+CMP/SETC class instructions add SrcRType field.
+
+The encoding is as follows:
+
+
+
+The setc.{and, or} and cmp.{and, or} instructions are not completely consistent with the SrcRType parameters of other instructions, as follows:
+
+| SrcRType | setc.and, setc.or, cmp.and, cmp.or | Other setc, cmp instructions |
+|----------|----------------------------------------|-------------------|
+| 0 | No format conversion | No format conversion |
+| 1 | Intercept the lower 32 bits of the SrcR register with sign extension (.sw) | Intercept the lower 32 bits of the SrcR register with sign extension (.sw) |
+| 2 | Intercept the lower 32-bit unsigned extension of the SrcR register (.uw) | Intercept the lower 32-bit unsigned extension of the SrcR register (.uw) |
+| 3 | Invert SrcR register bit (.not) | Invalid encoding (N/A) |
+
+**Adjustment 12: Some SETC instructions**
+
+The immediate offset of SETC class instructions with immediate data needs to be left shifted by shamt bits. The specific encoding is as follows:
+
+
+
+The immediate value in the assembly syntax of the setc class instruction does not express shifting. The compiler will perform shift encoding based on the given immediate value. The specific compilation is as follows:
+
+
+
+**Adjustment 13: Division/Remainder Instructions**
+
+Division instruction DIV class: Modify the quotient of the division result and write it to the destination register.
+Remainder instruction REM class: Modify the remainder of the division result and write it to the destination register.
+
+**Tweak 14: Floating point instruction FCVT split**
+
+In order to unify the decoding format and reduce the complexity of hardware decoding, an FCVT instruction from the previous version was split. The results are as follows:
+
+SrcType of FCVT.H/ FCVT.S/ FCVT.D instruction: 0: uw; 1: sw; 2: sl; 3: ul
+
+FCVT.UW/ FCVT.SW/ FCVT.UL/ FCVT.SL instruction SrcType: 0: n/a; 1: h; 2: s; 3: d
+
+
+
+SrcType of FCVT.H/ FCVT.S/ FCVT.D instruction: 0: n/a; 1: h; 2: s; 3: d
+
+**Tweak 15: Command input/output encoding**
+
+After upgrading to version 0.40, the microinstruction input/output field encoding method is as follows:
+
+| Encoding | Input register field | Output register field |
+|------|-------------|-----------------|
+| 0 | R0 | Invalid output |
+| 1-23 | R1-R23 | R1-R23 |
+| 24-27 | T#1-T#4 | reserve reserve |
+| 28-29 | U#1-U#2 | reserve reserve |
+| 30 | U#3 | Uqueue |
+| 31 | U#4 | T queue |
+
+
+
+**Adjustment 16: Delete some instructions**
+
+Based on the architectural changes in version 0.40, the following instructions are no longer used and therefore deleted:
+
+**addbpcf**, **addbpcn**, **setc.trap**, **setc.msg**, **ssrcrlt**, **tlbget**, **tlbset**, **tlbi**
\ No newline at end of file
diff --git a/docs/change_log/update_v0.41.md b/docs/change_log/update_v0.41.md
new file mode 100644
index 00000000..d0b09c01
--- /dev/null
+++ b/docs/change_log/update_v0.41.md
@@ -0,0 +1,402 @@
+# 0.41 version update
+
+Update date: September 29, 2024
+
+For the path to the web version of the instruction encoding design document, please see [LinxISA Encoding-0.41](https://dbox.huawei.com/detaildocs?oid=VR:wt.doc.WTDocument:100519244765)
+
+## Version update background
+
+The next key goal of LinxISA is the integrated computing architecture of NPU and GPU, of which the most important instruction extension is SIMTexecution model. Version 0.41 is used to describe the extended implementation of SIMTexecution model based on block instruction.
+
+Unlike CPUs that process vector data through SIMD (Single Instruction Multiple Data), GPUs usually use SIMT. The advantage of SIMT is that developers do not need to work hard to fit the data into the appropriate vector length, and SIMT allows each thread to have different branches. Purely using SIMD cannot execute conditional jump functions in parallel, because conditional jumps will behave differently in different threads based on different input data. This can only be achieved by using SIMT.
+
+Under the LinxISA framework, we need to integrate the NPU and GPU architectures through a set of instruction sets to meet the new isomorphism requirements. Therefore, we introduce a parallel block engine under the existing framework, which can process N body identical block instruction at the same time to achieve the effect of efficient parallel execution of simple loops. We call this block engine SIMTblock instruction.
+
+The schematic diagram of SIMT block execution model is as follows:
+
+
+
+## General description of version update
+
+1. Added SIMTblock instruction definition
+ - Add microinstructions in SIMT blocks and uniformly use **64bit length encoding**
+ - Define **CSTK and PredM registers** within the SIMT block.
+ - **4 groups of relative index registers** are defined in the SIMT block, named T, U, M, N respectively, and each group contains 8 registers.
+2. Add BTEXT instruction to indicate the offset distance from header to body in the separation block
+3. Added loop.get and loop.set instructions in scalar block
+4. Added read-only register LaneNum in system register, used to store the number of parallel lanes of SIMT block engine
+5. Modify the assembly syntax of the load/store instructions of the immediate offset class.
+6. Introduce **floating point block** instructions and **in-block microinstructions** definitions
+
+## Change details
+
+### SIMTblock instruction definition
+
+Like the traditional scalar block, SIMTblock instruction also uses the BSTART instruction as the starting instruction of the block, and the necessary block description instructions are added to header to supplement the execution control information.
+
+1. **BSTART.SIMT**
+
+Instruction encoding:
+
+
+
+Among them:
+
+- block typeBlockType is encoded as 4b0011 to represent the SIMT block, and the **jump type is fixed as Fall** (encoded as 3b001).
+- The current version SIMT block is defined as **detached block** with DCP bit 1.
+
+2. **Add body pointer BTEXT instruction**
+
+In order to expand the coding space, SIMTbody uses 64-bit width microinstructions. If these 64-bit instructions are mixed with 32 or 16-bit instructions in one block, the hardware implementation complexity will be higher and the implementation cycle will be longer.
+Therefore, this version defines the SIMT block as a separate block, and the BText instruction for indicating the position of body needs to be added to header. This command is used to encode the offset distance from header to body of SIMTblock instruction.
+
+The instructions are encoded as follows:
+
+
+
+3. **SIMT BLOCK architectural state**- **Global Status**
+ * R0-R23: The SIMT block uses the same first layer architectural registerR0-R23 as the traditional scalarblock instruction.
+- **System Status**
+ * **LaneNum**: The SIMT block introduces a read-only system registerLaneNum in the first layer architecture, which is used to store the number of parallel Lanes supported by the current hardware. |
+ * **LB0, LB1, LB2**: SIMT block uses LB0, LB1, LB2 3 system register as the upper limit of parallel iteration. |
+ * LC0, LC1, LC2: The SIMT block uses LC0, LC1, LC2 3 system register for parallel iteration number control. |
+- **Intra-block state**
+ * **PredM**: A Predicate Mask register is added to the SIMT block to control whether each lane in the SIMT block engine is valid |
+ * **CSTK**: Control Stack register, used to store PC and mask when a branch occurs within the SIMT block |
+ * **4 sets of relative index registers**: TR1 to TR8, UR1 to UR8, MR1 to MR8, NR1 to NR8. The **register width of this type is not fixed** and can be 8, 16, 32 or 64 bits, which is determined by the register width expressed by the instruction.
+
+Note: The SSRID of LB and LC class system register has been adjusted in this version.
+
+4. **SIMT intra-block microinstructions**
+
+On the one hand, due to the introduction of more private registers in the SIMT block, all optional registers cannot be encoded in 5-bit space in the 32-bit space; on the other hand, the microinstructions in the SIMT block need to indicate the width information of the source and destination registers, and the types of instruction operands have been expanded. For these reasons, an instruction within the SIMT block cannot be encoded using 32bit.
+
+Therefore, in the current version, **microinstructions within the SIMT block uniformly use 64bit encoding length**. This 64-bit long instruction is defined as "the lower bit of a 32-bit standard instruction spliced into a 32-bit instruction LIEXT for expansion." The 32-bit standard instruction can be an instruction in the public coding space or a SIMTblock-private microinstruction.
+
+The Liext (full name: Long Instruction Extend) instruction is used to splice with subsequent basic instructions to form a 64-bit long instruction. The different field segments of this instruction serve as extension bits of the corresponding fields of the base instruction.
+
+The instructions are encoded as follows:
+
+
+
+Among them:
+
+- **dest-ext**: This field is used as the extension bit of the instruction's destination register field RegDst.
+- **func-ext**: This field is used as the extension bit of the func field in the instruction encoding.
+- **Src0-ext**: This field is used as an extension to the first source register field of the instruction.
+- **Src1-ext**: This field is used as an extension to the second source register field of the instruction.
+- **Src2-ext**: This field is used as an extension to the third source register field of the instruction.
+
+- **Floating point multi-operation instructions**| Instructions | Assembly syntax | Instruction definition |
+|------|-----------|---------|
+| FADD | fadd SrcL.{T}, SrcR.{T}, ->{t,u,m,n}.{w} | Floating point addition |
+| FSUB | fsub SrcL.{T}, SrcR.{T}, ->{t,u,m,n}.{w} | Floating point subtraction |
+| FMUL | fmul SrcL.{T}, SrcR.{T}, ->{t,u,m,n}.{w} | Floating point multiplication |
+| FDIV | fdiv SrcL.{T}, SrcR.{T}, ->{t,u,m,n}.{w} | Floating point division |
+| FMADD | fmadd SrcL.{T}, SrcR.{T}, SrcA.{T}, ->{t,u,m,n}.{w} | Floating point multiply and add |
+| FMSUB | fmsub SrcL.{T}, SrcR.{T}, SrcA.{T}, ->{t,u,m,n}.{w} | Floating point multiplication and subtraction |
+| FNMADD | fnmadd SrcL.{T}, SrcR.{T}, SrcA.{T}, ->{t,u,m,n}.{w} | Floating point multiplication and addition, negative |
+| FNMSUB | fnmsub SrcL.{T}, SrcR.{T}, SrcA.{T}, ->{t,u,m,n}.{w} | Floating point multiplication and subtraction, negative |
+
+- **Floating point unary operation instructions**
+
+| Instructions | Assembly syntax | Instruction definition |
+|------|-----------|---------|
+| FABS | fabs SrcL.{T}, ->{t,u,m,n}.{w} | Absolute value |
+| FSQRT | fsqrt SrcL.{T}, ->{t,u,m,n}.{w} | Square root |
+| FEXP | fexp SrcL.{T}, ->{t,u,m,n}.{w} | Exponent value with base e |
+| FLOG | flog SrcL.{T}, ->{t,u,m,n}.{w} | Base 2 logarithmic value |
+| FSIN | fsin SrcL.{T}, ->{t,u,m,n}.{w} | Sine value |
+| FCOS | fcos SrcL.{T}, ->{t,u,m,n}.{w} | Cosine value |
+| FRECIP | frecip SrcL.{T}, ->{t,u,m,n}.{w} | Find the reciprocal |
+
+- **Floating point type judgment instruction**
+
+| Instructions | Assembly syntax | Instruction definition |
+|------|-----------|---------|
+| FCLASS | fclass SrcL.{T}, ->{t,u,m,n}.{w} | Floating point type judgment |
+
+- **Floating Point Comparison Instructions**| Instructions | Assembly syntax | Instruction definition |
+|------|-----------|---------|
+| FEQ | feq.srcT SrcL.{T}, SrcR.{T}, ->{t,u,m,n}.{w} | Equality comparison (silent comparison) |
+| FNE | fne.srcT SrcL.{T}, SrcR.{T}, ->{t,u,m,n}.{w} | Unequal comparison (silent comparison) |
+| FLT | flt.srcT SrcL.{T}, SrcR.{T}, ->{t,u,m,n}.{w} | Less than comparison (silent comparison) |
+| FGE | fge.srcT SrcL.{T}, SrcR.{T}, ->{t,u,m,n}.{w} | Greater than or equal to comparison (silent comparison) |
+| FEQS | feqs.srcT SrcL.{T}, SrcR.{T}, ->{t,u,m,n}.{w} | Equality comparison (sending comparison) |
+| FNES | fnes.srcT SrcL.{T}, SrcR.{T}, ->{t,u,m,n}.{w} | Unequal comparison (sending comparison) |
+| FLTS | flts.srcT SrcL.{T}, SrcR.{T}, ->{t,u,m,n}.{w} | Less than comparison (sending comparison) |
+| FGES | fges.srcT SrcL.{T}, SrcR.{T}, ->{t,u,m,n}.{w} | Greater than or equal to comparison (sending comparison) |
+
+- **Floating point conditional jump instructions**
+
+| Instructions | Assembly syntax | Instruction definition |
+|------|-----------|---------|
+| B.FEQ | b.feq.srcT SrcL.{T}, SrcR.{T}, label | Equality jump, otherwise execute sequentially |
+| B.FNE | b.fne.srcT SrcL.{T}, SrcR.{T}, label | Jump if not equal, otherwise execute sequentially |
+| B.FLT | b.flt.srcT SrcL.{T}, SrcR.{T}, label | If less than jump, otherwise execute sequentially |
+| B.FGE | b.fge.srcT SrcL.{T}, SrcR.{T}, label | If greater than or equal to, jump, otherwise execute sequentially |
+
+- **data type conversion instruction**
+
+The data type conversion instruction is used to support conversion operations between floating point data formats and from floating point to integer data formats. The instructions are defined in the following table:
+
+| Instructions | Assembly Syntax | Description |
+|------|-----------|---------|
+| FCVT | fcvt SrcL.{srcT}, ->{t,u,m,n}.{w}.{dstT} | Format conversion between floating point data |
+| FCVTI | fcvti SrcL.{srcT}, ->{t,u,m,n}.{w}.{dstT} | Floating point to integer format conversion |
+| ICVT | icvt SrcL.{srcT}, ->{t,u,m,n}.{w}.{dstT} | Format conversion between integer data |
+| ICVTF | icvtf SrcL.{srcT}, ->{t,u,m,n}.{w}.{dstT} | Integer to floating point format conversion |
+
+- **Maximum and Minimum Value Instructions**| Instructions | Assembly syntax | Instruction definition |
+|------|-----------|---------|
+| MAX | max SrcL.{T}, SrcR{T}, ->{t,u,m,n}.{w} | signed integer maximum value |
+| MAXU | maxu SrcL.{T}, SrcR{T}, ->{t,u,m,n}.{w} | unsigned integer maximum value |
+| FMAX | fmax SrcL.{T}, SrcR{T}, ->{t,u,m,n}.{w} | Maximum floating point value |
+| MIN | min SrcL.{T}, SrcR{T}, ->{t,u,m,n}.{w} | signed integer minimum value |
+| MINU | minu SrcL.{T}, SrcR{T}, ->{t,u,m,n}.{w} | unsigned integer minimum value |
+| FMIN | fmin SrcL.{T}, SrcR{T}, ->{t,u,m,n}.{w} | Minimum floating point number |
+
+- **scalar operation instructions**
+
+| Instructions | Assembly syntax | Instruction definition |
+|------|-----------|---------|
+| DIV | div SrcL.{T}, SrcR{T}, ->{t,u,m,n}.{w} | Integer signed division |
+| DIVU | divide SrcL.{T}, SrcR{T}, ->{t,u,m,n}.{w} | Integer unsigned division |
+| REM | rem SrcL.{T}, SrcR{T}, ->{t,u,m,n}.{w} | Integer signed remainder |
+| REMU | remu SrcL.{T}, SrcR{T}, ->{t,u,m,n}.{w} | Integer unsigned remainder |
+
+- **Conditional selection instructions**
+
+| Instructions | Assembly Syntax | Instruction Definition
+|------|-----------|---------|
+| CSEL | CSEL SrcP.{T}, SrcL.{T}, SrcR{T}, ->{t,u,m,n}.{w} | Conditional selection instructions |
+
+- **bit-bit operation instructions**
+
+| Instructions | Assembly syntax | Instruction definition |
+|------|-----------|---------|
+| REV16 | rev16 SrcL.{T}, ->{t,u,m,n}.{w} | Big-endian conversion within every 16 bits |
+| REV32 | rev32 SrcL.{T}, ->{t,u,m,n}.{w} | Big-endian conversion within every 32 bits |
+| REV64 | rev64 SrcL.{T}, ->{t,u,m,n}.{w} | Big-endian conversion within 64bit |
+| CTZ | ctz SrcL.{T}, ->{t,u,m,n}.{w} | The effective bits are from low to high, counting the number of 0s before the first 1 |
+| CLZ | clz SrcL.{T}, ->{t,u,m,n}.{w} | The effective bits are from high to low, counting the number of 0s before the first 1 |
+
+- **Memory application and release instructions**
+
+| Instructions | Assembly syntax | Instruction definition |
+|------|-----------|---------|
+| ALLOC | alloc size, ->{t,u,m,n}.{W} | Apply to allocate memory space of a specified size |
+| FREE | free SrcL.d, size | Release the memory space where the address in the source register is located |
+
+- **Reduce instruction**
+
+The Reduce instruction is used to summarize the processing results in all Lanes of the hardware and output them to the global register Rd.| Instructions | Assembly syntax | Instruction definition |
+|------|-----------|---------|
+| RDADDU | rdaddu SrcL_v.{T}, =>Rd | Perform an unsigned addition operation on the values of SrcL_v in all lanes, and write the result to the global register Rd |
+| RDADDS | rdadds SrcL_v.{T}, =>Rd | Perform signed addition operation on the values of SrcL_v in all lanes, and write the result to the global register Rd |
+| RDAND | rdand SrcL_v.{T}, =>Rd | Bitwise AND the values of SrcL_v in all lanes, and the result is written to the global register Rd |
+| RDOR | rdor SrcL_v.{T}, =>Rd | Perform bitwise OR on the values of SrcL_v in all lanes, and write the result to the global register Rd |
+| RDXOR | rdxor SrcL_v.{T}, =>Rd | Perform bitwise XOR on the values of SrcL_v in all lanes, and write the result to the global register Rd |
+| RDFADD | rdfadd SrcL_v.{T}, =>Rd | Add the floating point numbers in SrcL_v in all lanes, and write the result to the global register Rd |
+
+- **Maximum/Minimum Value Comparison Instructions**
+
+| Instructions | Assembly syntax | Instruction definition |
+|------|-----------|---------|
+| RDMAXU | rdmaxu SrcL_v.{T}, =>Rd | **Unsigned** Compare the values of SrcL. in all lanes and write the maximum value to the global register Rd. |
+| RDMAXS | rdmaxs SrcL_v.{T}, =>Rd | **Signed** Compare the values of SrcL. in all lanes and write the maximum value to the global register Rd. |
+| RDMINU | rdminu SrcL_v.{T}, =>Rd | **Unsigned** Compare the values of SrcL. in all lanes and write the minimum value to the global register Rd. |
+| RDMINS | rdmins SrcL_v.{T}, =>Rd | **Signed** Compare the values of SrcL. in all lanes and write the minimum value to the global register Rd. |
+| RDFMAX | Rdfmax SrcL_v.{T}, =>Rd | Compare the floating point numbers in SrcL. in all lanes and write the maximum value to the global register Rd. |
+| RDFMIN | Rdfmin SrcL_v.{T}, =>Rd | Compare the floating point numbers in SrcL. in all lanes and write the minimum value to the global register Rd. |
+
+- **PC.PUSH/POP command**
+
+The pc.push and pc.pop instructions are used to save and restore the PC and mask of the re-convergence point when there is a fork in the execution path in different lanes within the SIMT block.
+
+| Instructions | Assembly Syntax | Description |
+|------|-----------|---------|
+| PC.PUSH | pc.push label | Push the address obtained by adding the offset to the instruction PC and the mask of the current lane into the Control Stack register. |
+| PC.POP | pc.pop | Pop the PC and mask from the Control Stack register and jump to the corresponding address and set the mask register. |
+
+- **QPUSH/QPOP command**
+
+| Instructions | Assembly Syntax | Description |
+|------|-----------|---------|
+| QPUSH | qpush SrcL.{T}, SrcR.{T}, ->{t,u,m,n}.{w} | Push the data in SrcR to the GQM queue specified by SrcL. If the writing is successful, 0 will be output, otherwise 1 will be output to the destination register. |
+| QPOP | qpop SrcL.{T}, ->{t,u,m,n}.{w} | Read the data of a specific width in the GQM queue specified by SrcL, and write the result to the destination register. |In addition to SIMT private instructions, some instructions in the public encoding space will be used in the SIMT block, and they are also encoded by splicing a LIEXT instruction before the original 32-bit encoding. The list of common instructions used within the current version of SIMT blocks is as follows:
+
+- **Arithmetic Operation Instructions**
+
+| Command List |
+|----------|
+| ADD, SUB, AND, OR, XOR, SRL, SRA, SLL |
+| ADDI, SUBI, ANDI, ORI, XORI, SRLI, SRAI, SLLI |
+
+- **Comparison Command**
+
+| Command |
+|------|
+| CMP.EQ, CMP.NE, CMP.AND, CMP.OR, CMP.LT, CMP.GE, CMP.LTU, CMP.GEU |
+| CMP.EQI, CMP.NEI, CMP.ANDI, CMP.ORI, CMP.LTI, CMP.GEI, CMP.LTUI, CMP.GEUI |
+
+- **Bit operation instructions**
+
+| Command |
+|------|
+| BXS, BXU, BIC, BIS |
+
+- **Multiplication Instructions**
+
+| Command |
+|------|
+| MUL, MULU, MADD |
+
+- **Intra-block jump instructions**
+
+| Command |
+|------|
+| JR, J |
+| B.EQ, B.NE, B.LT, B.GE, B.LTU, B.GEU |
+
+- **system register access command**
+
+| Command |
+|------|
+| SSRGET, SSRSET |
+
+- **Memory loading load command**
+
+| Command |
+|------|
+|LB, LH, LW, LD,LBU,LHU, LWU, LBI, LHI, LWI, LDI |
+| LBUI, LHUI, LWUI, LHI.U, LWI.U, LDI.U, LHUI.U, LWUI.U |
+
+- **Memory write Store command**
+
+| Command |
+|------|
+| SB, SH, SW, SD, SH.U, SW.U, SD.U |
+| SBI, SHI, SWI, SDI, SHI.U, SWI.U, SDI.U |
+
+- **Long immediate and PC relative addressing instructions**
+
+| Command |
+|------|
+| ADDTPC, LUI |
+
+## Add microinstructions
+
+In this version, the following microinstructions are added to the basic instruction set to set the loop register.
+
+| Instructions | Assembly Syntax | Description |
+|------|-----------|------|
+| LOOP.GET | loop.get LoopReg, ->{t,u,m,n}.{w} | Read the loop register value to the block-private register |
+| LOOP.SET | loop.set SrcL, uimm, => LoopReg | Set the result of register SrcL plus immediate uimm to the loop register |
+
+
+
+## Load/store instruction modification
+
+In order to distinguish the immediate address offset scaled and unscaled addressing modes of the load/store-imm instruction, this version makes the following modifications to this type of instruction:
+
+- Added constraints on immediate offset in load/store instruction assembly of scaled and unscaled classes.
+- Modify the expression form of immediate offset in instruction encoding to: simm12 or simm7. Among them, "simm" represents a signed immediate offset, and the following number represents the number of bits.| load command | assembly syntax | remarks |
+|------|-----------|----------|
+| LBI | lbi [SrcL, simm], {->t, ->u, =>Rd} | simm is a multiple of 1, simm12 is encoded as simm |
+| LHI | lhi [SrcL, simm], {->t, ->u, =>Rd} | simm must be a multiple of 2, simm12 is encoded as simm/2 |
+| LWI | lwi [SrcL, simm], {->t, ->u, =>Rd} | simm must be a multiple of 4, simm12 is encoded as simm/4 |
+| LDI | ldi [SrcL, simm], {->t, ->u, =>Rd} | simm must be a multiple of 8, simm12 is encoded as simm/8 |
+| LBUI | lbui [SrcL, simm], {->t, ->u, =>Rd} | simm is a multiple of 1, simm12 is encoded as simm |
+| LHUI | lhui [SrcL, simm], {->t, ->u, =>Rd} | simm must be a multiple of 2, simm12 is encoded as simm/2 |
+| LWUI | lwui [SrcL, simm], {->t, ->u, =>Rd} | simm must be a multiple of 4, simm12 is encoded as simm/4 |
+| LHI.U | lhi.u [SrcL, simm], {->t, ->u, =>Rd} | simm is a multiple of 1, simm12 is encoded as simm |
+| LWI.U | lwi.u [SrcL, simm], {->t, ->u, =>Rd} | simm is a multiple of 1, simm12 is encoded as simm |
+| LDI.U | ldi.u [SrcL, simm], {->t, ->u, =>Rd} | simm is a multiple of 1, simm12 is encoded as simm |
+| LHUI.U | lhui.u [SrcL, simm], {->t, ->u, =>Rd} | simm is a multiple of 1, simm12 is encoded as simm |
+| LWUI.U | lwui.u [SrcL, simm], {->t, ->u, =>Rd} | simm is a multiple of 1, simm12 is encoded as simm |
+
+The memory access address of the above load instruction is: `address = SrcL + simm`.
+
+The instructions are encoded as follows:
+
+
+
+| store command | Assembly syntax | Remarks |
+|------|-----------|----------|
+| SBI | sbi SrcL, [SrcR, simm] | simm is a multiple of 1, simm12 is encoded as simm |
+| SHI | shi SrcL, [SrcR, simm] | simm must be a multiple of 2, simm12 is encoded as simm/2 |
+| SWI | swi SrcL, [SrcR, simm] | simm must be a multiple of 4, simm12 is encoded as simm/4 |
+| SDI | sdi SrcL, [SrcR, simm] | simm must be a multiple of 8, simm12 is encoded as simm/8 |
+| SHI.U | shi.u SrcL, [SrcR, simm] | simm is a multiple of 1, simm12 is encoded as simm |
+| SWI.U | swi.u SrcL, [SrcR, simm] | simm is a multiple of 1, simm12 is encoded as simm |
+| SDI.U | sdi.u SrcL, [SrcR, simm] | simm is a multiple of 1, simm12 is encoded as simm |
+
+The instructions are encoded as follows:
+
+| store command | Assembly syntax | Remarks |
+|------|-----------|----------|
+| SBI.A | sbi.a SrcL, [SrcR, simm], {->t, ->u, =>Rd} | simm is a multiple of 1, simm7 is encoded as simm |
+| SHI.A | shi.a SrcL, [SrcR, simm], {->t, ->u, =>Rd} | simm must be a multiple of 2, simm7 is encoded as simm/2 |
+| SWI.A | swi.a SrcL, [SrcR, simm], {->t, ->u, =>Rd} | simm must be a multiple of 4, simm7 is encoded as simm/4 |
+| SDI.A | sdi.a SrcL, [SrcR, simm], {->t, ->u, =>Rd} | simm must be a multiple of 8, simm7 is encoded as simm/8 |
+| SHI.UA | shi.ua SrcL, [SrcR, simm], {->t, ->u, =>Rd} | simm is a multiple of 1, simm7 is encoded as simm |
+| SWI.UA | swi.ua SrcL, [SrcR, simm], {->t, ->u, =>Rd} | simm is a multiple of 1, simm7 is encoded as simm |
+| SDI.UA | sdi.ua SrcL, [SrcR, simm], {->t, ->u, =>Rd} | simm is a multiple of 1, simm7 is encoded as simm |
+
+The instructions are encoded as follows:
+
+
+
+The memory access address of the above store instruction is: `address = Srcr + simm`.
+
+## Introducing floating point blocks and floating point instructions
+
+In order to further optimize the amount of program code and reduce the expansion of Codesize, this version incorporates the design of the floating point block and adds related floating point instructions.
+
+The characteristics of the floating point block are as follows:
+
+- The starting instruction of the floating point block is BSTART, which also supports 32-bit and compressed version encoding.
+- The floating point block does not support the split block form and is identified by ".fp" in assembly.
+- The definition of registers within the floating point block is the same as that of the scalar block: **4 T + 4 U registers**.
+
+BSTART.fp encoding (32bit)
+
+
+
+C.BSTART.fp encoding (16bit)
+
+
+
+Floating point block instruction centrally defines the following instructions.
+
+- Division remainder instruction
+- Bit manipulation instructions
+- Maximum and minimum instructions
+- Conditional selection instructions
+- Floating point instructions
+- data type conversion instructions
+
+Among them:
+
+Floating point instructions support 4 types of floating point data type: 8bitlow-precision floating-point number, 16bit half-precision floating point number, 32bit single-precision floating point number and 64bit double-precision floating point number.
+
+The assembly format of floating point instructions is (taking fadd as an example): `fadd.{T} SrcL, SrcR, {->t, ->u, =>Rd}`
+
+- **{T}**: refers to the operand type of the floating point instruction, encoded in the "SrcType" field, the encoding method is shown in the following table:
+
+
+
+| SrcType | Assembly flag | Explanation |
+|------|-----------|----------|
+| 00 | fd | The operand is 64-bit double-precision floating point data |
+| 01 | fs | The operand is 32-bit single-precision floating point data |
+| 10 | fh | The operand is 16-bit half-precision floating point data |
+| 11 | fb | The operand is 8bitlow-precision floating-point type data |
+
+The assembly format of the data format conversion instruction cvt is: `cvt.srcT2dstT SrcL, {->t, ->u, =>Rd}`
+
+- srcT represents the input data format, encoded in the "SrcType" field.
+- dstT represents the converted data format, encoded in the "DstType" field.
+
+The instructions are encoded as follows:
\ No newline at end of file
diff --git a/docs/change_log/update_v0.42.md b/docs/change_log/update_v0.42.md
new file mode 100644
index 00000000..095fe887
--- /dev/null
+++ b/docs/change_log/update_v0.42.md
@@ -0,0 +1,258 @@
+# 0.42 version update
+
+Update date: September 30, 2024
+Corresponding to the instruction level definition version on DBOX [LinxISA Encoding-0.42] (https://dbox.huawei.com/detaildocs?oid=VR:wt.doc.WTDocument:100727107943)
+
+## General description of version update
+
+This version update mainly covers instruction naming conventions, optimization of long jump offsets, instruction dual or multi-output encoding methods, etc.
+
+| Change items | Change content | Reason for change |
+|------------|---------------------------------|----------------------------------|
+|system register|Supplement system registerCW,TR1,TR2|Supplement system register that was missing after upgrading to version 0.4x|
+|Instruction changes|**block instruction**:
1. Adjust the instruction naming
2. Modify the implementation of long jump
3. SIMTblock instruction supports serial execution mode
**Microinstruction**:
1. Instruction multi-output expression and encoding
2. Supplement the output register bit width identifier of the reduce instruction in the SIMT block
3. Implemented by merging pc.push and conditional jump instructions
4. Modify the expression of instruction encoding immediate field
5. Add b.cond instruction
6. Jump offset of J/JR instruction
7. Add atomic instructions in SIMT block
8. Modify instructions in SIMT block|**block instruction**：
1. In order to clearly distinguish header instruction from microinstructions and to distinguish the block start instruction in header from other description instructions
2. The BNextOffset field of the BSTART instruction may not be enough to encode the actual jump offset
3. Provide corresponding software interfaces for different scenarios in the program loop to facilitate software designers to flexibly write programs
**Microinstructions**:
1. Dual/multi-output instructions that need to be introduced later in LinxISA
3. Avoid adding redundant registers
5. Supplement the instruction definitions in the block to ensure functional completeness
2&4&6. Continuously optimize the instruction set |
+
+
+## Change details
+
+### 1. system register
+
+Added system register**CW**, **TR1**, **TR2**, these are the missing system register after upgrading to version 0.4x.
+
+### 2. Instruction changes
+
+**block instruction**
+
+In LinxISA, in order to clearly distinguish header instruction from microinstructions and to distinguish block start instructions from other description instructions in header, this version has made the following standardized adjustments to the instruction naming:
+
+- header instruction is expressed in uppercase letters; microinstructions are expressed in lowercase letters.
+- In addition to the block start instruction in header instruction, other header description instructions use "B." as a prefix to facilitate the distinction between block start instructions and other block description instructions in the assembler.
+- Compression instructions with a coding width of 16 bits are named with "C." as the prefix.
+
+#### Adjustment 1: Naming convention for header instruction
+
+Generally speaking, except for BSTART in header instruction of inline blocks and detached blocks, other description instructions are uniformly prefixed with B.. The specific modifications are as follows:
+
+
+
+#### Adjustment 2: Template block instruction naming modification
+
+In order to cooperate with the adjustment of the header instruction naming, the naming of the template block instruction has been modified simultaneously, as follows:
+
+#### Adjustment 3: Naming modification of compression instructions
+
+All 16-bit compression instructions are uniformly prefixed with "C.", and the related instructions are as follows:
+
+
+
+#### Adjustment 4: Modify the implementation of long jump
+
+Version 0.42 introduces the BSTART + B.NEXT encoding combination solution to solve the problem that the BNextOffset field of the BSTART instruction may not be enough to encode the actual required jump offset. The specific instructions are as follows:
+
+Among them:
+
+- BSTART is used to encode the low-order part of the jump offset, and B.NEXT is used to encode the high-order part.
+- Only the BSTART instruction with Opcode 4b0000 can be used in combination with B.NEXT. The B.NEXT instruction is invalid when placed in other header.
+- The B.NEXT code immediately follows the BSTART instruction.
+- EX: extend flag, setting it to 0 means that the jump offset in BSTART is complete (FF), setting it to 1 means it is incomplete (HF), and you need to wait for the subsequent B.NEXT instruction to form a complete jump distance.
+
+BSTART coding structure
+
+
+
+B.NEXT coding structure, BnextOffset[41:17] is used to encode the high-order part of the jump distance, and can be combined with BSTART to express the 42-bit jump distance.
+
+
+
+B.NEXT supports 16-bit compressed version B.NEXT.C, which can be combined to express 29-bit jump distance.
+
+
+
+#### Tweak 5: SIMTblock instruction supports serial execution mode
+
+**Execution Mode**
+
+For the different dependencies between each iteration of the loop, the instruction set provides the definition of three SIMT block execution modes.
+
+- BSTART.LOOP: Complete serial execution between all lanes. It is suitable for scenarios where there are memory access dependencies between iterations of a loop.
+- BSTART.VECT: Different lanes in the same group can be executed in parallel, but different groups need to be executed serially. It is suitable for scenarios where there are memory access dependencies between some iterations in the loop.
+- BSTART.SIMT: Parallel execution can be performed between different lanes in the same group, and parallel execution is also supported between different groups. Suitable for scenarios where there are no dependencies between all iterations in the loop.
+
+The schematic diagram of each execution mode is as follows:
+
+
+
+**Command definition**
+
+The BSTART definition of SIMTblock instruction is as follows:
+
+Assembly syntax:
+
+```asm
+C.BSTART.
+BSTART.
+```
+
+SIMTblock instruction defaults to FALL type jump.
+
+Encoding format:
+
+
+
+Compared with the previous version, the Parallel Mode field for encoding execution mode has been added. Among them:
+
+- 0: for encoding LOOP mode
+- 1: for encoding VECT mode
+- 2: For encoding SIMT mode
+- Other encodings are reserved.
+
+Note:
+
+The current version does not currently support the LOOP block implementation released in the V0.41 version. The corresponding encoding is temporarily deleted from the instruction set. The original LOOP block is encoded as follows:
+
+
+
+---
+
+**Microinstructions**
+
+#### Tweak 6: Directive multiple outputs and expressions
+
+In view of the dual/multi-output instructions that need to be introduced in LinxISA in the future, we first determined its encoding method in the current version and accordingly adjusted the assembly expression of output to the global register UL_GPR.
+
+Single output:
+
+```asm
+add SrcL，SrcR, ->t； #输出至T队列
+add SrcL，SrcR, ->u； #输出至U队列
+add SrcL，SrcR, ->Rx； #输出至UL_GPR
+```
+
+Multiple outputs:
+
+```asm
+mulh SrcL, SrcR, ->tx2； #输出到连续2个T队列
+ld [SrcL, SrcR<<3], ->tx4； #输出到连续4个T队列0
+```
+
+The input/output codec of the microinstruction register in the scalar block is as follows:
+
+
+
+Note:- Multi-output is only allowed for specific Opcodes. The output register (RegDst) field encoding of other single-output instructions is undefined, and the model or hardware execution results are not known.
+- Since the speed pointer attributes of T and U clock hands are different, one instruction is not supported to output to both T and U.
+- The UL_GPR written in the block is modified to be marked by "->", and the instruction in the block reads the register value to the updated value.
+- Retain the original restriction: "Each UL_GPR can only be written once in the same block."
+
+#### Adjustment 7: reduce instruction
+
+Supplement the output register bit width identifier of the reduce instruction in the SIMT block.
+
+#### Adjustment 8: pc.push and conditional jump instructions
+
+The pc.push instruction in the SIMT block is used to push the convergence point (reconverge) PC and thread mask onto the stack when the program execution flow diverges. However, to determine whether divergence occurs during program execution, you need to wait for the result of the subsequent conditional jump instruction, so you need to add a register to temporarily save the PC of the convergence point.
+
+In order to avoid increasing this register, it was decided to merge the pc.push and conditional jump instructions into one instruction in the current version. The specific modifications are as follows:
+
+**Modification 1: Remove pc.push instruction**
+
+**Modification 2: Update conditional jump instruction semantics**
+
+Based on the semantics of scalar, the execution process of conditional jump instructions in the modified SIMT block is as follows:
+
+- There is a diverge (the result of whether the effective lane jump in the current group is inconsistent): Store the reconvergence information and the diverge information of one side branch into the ControlStack register, and update the mask and PC of the other side branch to the current state for execution.
+- There is no diverge: no effect on the ControlStack register. And execute according to ordinary conditional jump instructions.
+
+Among them:
+
+- The mask of the current group is recorded as cur_mask.
+- Among the two branches, if the mask of the branch chosen to be executed first is recorded as cal_mask, it will be stored in save_mask=cur_mask &(~cal_mask) of the ControlStack register.
+- The condition for judging the existence of diverge is: ((cur_mask & cal_mask) != cur_mask) && ((cur_mask & ~cal_mask) != cur_mask)
+
+Assembly syntax:
+
+
+
+Among them:
+The calculation of the re-convergence point PC is: rpc = tpc + rc_offset<<3
+The calculation of the jump target address is: br_pc = tpc + br_offset<<3
+
+#### Adjustment 9: Add a b.cond instruction
+
+In order to avoid insufficient offset encoding space for conditional jump instructions in extreme scenarios, a B.COND instruction is added
+
+Assembly syntax:
+
+```asm
+b.cond SrcP., SrcL., SrcR.
+```
+Among them: the value of SrcP is used as the judgment condition; SrcL is used to store the jump target address; SrcR is used to store the re-convergence point PC.
+
+Instruction semantics:
+Determine the SrcP values in all valid lanes under the current group: if all are 0 or all 1, it means there is no diverge.
+**No diverge**: If all are 0, the execution will be postponed, if all are 1, the execution will be jumped.
+**Diverge exists**: First push the re-convergence point PC and the mask of the current Group in SrcR to the CSTK register, and then push the branch PC and branch mask on one side. And update the mask and PC of the other side branch to the current state for execution.
+
+Encoding format:
+
+
+
+This instruction needs to be used in conjunction with CMP instructions, see the assembly example below:
+
+```asm
+addtpc %hi(rc_label), ->t
+addi t#1, %lo(rc_label), ->t // 得到重汇聚点PC
+addtpc %hi(br_label), ->t
+addi t#1, %lo(br_label), ->t // 得到跳转目标PC
+cmp.eq a0, t#1, ->t
+b.cond t#1, t#2, t#4
+```
+
+#### Adjustment 10: Jump offset of J/JR instructions
+
+The jump offset of the J/JR instruction is modified to be encoded in 8-byte units.
+
+The execution semantics of the JR instruction in the SIMT block are: jump to tpc=SrcL+simm15<< 3
+
+
+
+The execution semantics of the J instruction in the SIMT block are: jump to tpc += simm25<<3
+
+#### Adjustment 11: Add atomic instructions in SIMT block
+
+The following atomic instructions are added to the SIMT block to implement atomic operations and store reduce operations.
+
+
+
+- The Load.op class instruction adds an optional attribute ".ne" based on the definition of scalar, indicating that the instruction implements non-atomic operations. Atomic operations are implemented by default.
+- The Store.op class instruction is based on the definition of scalar, with the optional suffix ".rd" added, indicating that the instruction has the same address in SrcL in all lanes and performs store reduce operations. Atomic operations are implemented by default.
+
+#### Adjustment 12: Modification of instructions in SIMT block
+
+**Supplement the assembly identification and encoding of sd and ud**
+
+- For data type conversion instructions, it is necessary to distinguish whether there are signs during the conversion process of 64-bit integer data and floating-point data;
+- Multiplication and division instructions need to distinguish whether they are signed or not when operating on 64-bit wide integer data.
+
+Therefore, the 64-bit source operands of SIMTblock instruction are uniformly modified to be represented by the suffix ".sd" or ".ud", and the encoding of 64-bit signed and unsigned integer data is supplemented.
+
+
+
+**Command adjustment**
+
+The data type, bit width, and presence or absence of signs operated by instructions in the SIMT block can be represented by the suffix of the operand, so instructions with sign information in some OPs are merged.
+These include: Reduce instructions and multiplication and division instructions
+
+
+
+At the same time, the reduce instruction encoding was modified. The modified encoding is as follows:
+
+
+
+The instruction encoding retains the original mul, div, and rem encoding.
+
+**Add lbstop encoding**
+
+Added the end instruction encoding in SIMTbody and named it lbstop to avoid ambiguity when the assembler generates binary files or model decoding.
+
+
\ No newline at end of file
diff --git a/docs/change_log/update_v0.43.md b/docs/change_log/update_v0.43.md
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--- /dev/null
+++ b/docs/change_log/update_v0.43.md
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+# Version 0.43 update
+
+Update date: November 25, 2024
+
+For the path to the web version of the instruction encoding design document, please see [LinxISA Encoding-0.43](https://dbox.huawei.com/detaildocs?oid=VR:wt.doc.WTDocument:100752712747)
+
+## General description of version update
+
+The update of this version is mainly divided into two parts. The first is the update of the global register read and write semantics during the execution of block instruction, and the second is the addition of some privilege level related instructions.1. Modify block instruction execution semantics
+ - To optimize register usage efficiency, the execution semantics of LinxISAblock instruction are improved. After the update, **block instruction output can directly overwrite the input value to avoid multiple sets of register status redundancy**.
+2. Introduce separation block definition
+ - Added Decoupled Block function to define header and body separately. **New B.IO instruction** was added to header instruction.
+ - The detached block defines the input and output registers through the **B.IO instruction**, and the **B.TEXT instruction** specifies the body location, which is applicable to the **fall jump type**.
+ - When block instruction is executed, the return address is recorded in CARG.LRA, allowing flexible orchestration and management of header and body.
+3. system-call block design
+ - system-call block** implements lightweight calls** from low-privilege ACR to high-privilege ACR, avoiding context saving overhead.
+ - Key instructions: XB {ACR-ID}, {C-ID} are used to specify the calling target ACR and function ID, combined with the B.IO instruction to define headerinput/output.
+ - The ACR layered mechanism supports permission management of different software roles to ensure safe invocation.
+4. Add system call instructions
+ - **System block renamed to auxiliary block (aux)**.
+ - Added new microinstructions **acrc** and **acre** in the auxiliary block, retaining the general system call function.
+5. Fixupexception self-processing mechanism
+ - Added a new Fixup attribute to enable the block to automatically jump to the specified repair location to continue execution when exception occurs (such as memory access exception, assertion failure).
+ - The Fixup mechanism optimizes exception processing and reduces system overhead.
+6. header supplements HINT instruction encoding
+ - Support software to proactively transmit block jump probability, block popularity, prefetch and other hint information to hardware.
+7. Add GQM instructions (belonging to system block instruction set)
+ - **Added GQM (General Queue Manager) command**, which provides cross-module asynchronous communication and supports remote access and message queue management.
+ - Contains qmt, qpush and qpop instructions for queue maintenance, enqueuing and dequeuing operations, and supports the atomicity of many-to-many communication.
+8. Added TLB maintenance instructions (belonging to system block instruction set)
+ - **Added TLB (Translation Lookaside Buffer) maintenance instructions**, including tlb.iall, tlb.ia, tlb.iv and tlb.iav, to clean up TLB data of different levels and ranges.
+ - This function enhances the system's management and control capabilities of virtual memory, effectively improving memory usage efficiency.
+9. Added atomic comparison and exchange instructions (belonging to system block instruction set)
+ - **Add casb, cash, casw, casd instructions** to optimize atomic comparison and exchange operations.
+10. Added the instruction lsrget to read the status register in the block
+ - Add an interface for reading the status in the block and saving the status when exception or interrupt.
+11. Added system register and L1 GPR atomic swap instructions ssrswap
+ - Supplementary function implementation to improve the exchange efficiency between system register and global registers to avoid occupying relative index registers within the block.
+12. Delete BSTART.ECALL and BSTART.ERET instructions
+ - Introduced XBsystem-call block and two methods of microinstructions acrc and acre system calls.
+13. Delete trap command
+ - The semantics are similar to the assert instruction, and LinxISA does not need to use the trap function to escape to an external debugger later.## Detailed introduction of changes
+
+This part mainly introduces the changes in the architecture and the design of important instructions. The addition, deletion and modification of instructions are not explained in detail here.
+
+### Modify block instruction execution semantics
+
+After this version, in the same block instruction, the previous instruction updated a global register. Then the subsequent instruction reads the register value which is the updated value.
+
+```asm
+ BSTART.STD fall
+ ldi [a0, 0], ->t
+ ldi [a0, 8], ->t
+ add t#1, t#2, ->a1
+ sdi a1, [a0, 0] # a1的值是上面add指令输出值
+ ...
+```
+As shown in the assembly example above: the result of the instruction `add t#1, t#2, ->a1` is written to the global register a1, and the value of a1 read by the subsequent sdi instruction is the value updated by the add instruction.
+
+### Separate blocks
+
+For the execution process of the separated block, please refer to [block instruction jump] (../isa/arch/branch.md).
\ No newline at end of file
diff --git a/docs/change_log/update_v0.50.md b/docs/change_log/update_v0.50.md
new file mode 100644
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--- /dev/null
+++ b/docs/change_log/update_v0.50.md
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+# Version 0.50 update
+
+Update date: May 26, 2025
+
+For the corresponding encoding overview in this repository, see [Instruction-Set Overview](../isa/encoding/overview.md).
+
+## Update background
+
+Earlier proprietary AI-processor instruction-set approaches exposed repeated evolution bottlenecks. Each architecture iteration forced operator-library rewrites because the abstraction layer did not cleanly separate mechanism (for example memory access mode) from strategy (for example data blocking policy), so hardware-specification changes directly destabilized the software stack.
+
+In this context, LinxISA is positioned as a heterogeneous computing architecture that aims to break out of the traditional GPU-only paradigm and stay competitive across artificial intelligence, graphics rendering, and high-performance computing. Existing full-stack ecosystems derive their moat not only from hardware performance, but also from long-accumulated compiler, library, and application integration. A follow-the-leader strategy would therefore inherit compatibility cost without creating differentiated architectural value.
+
+In order for LinxISA to complete this task, it first needs to further optimize the basic scalar instructions from the perspective of static code volume and dynamic instruction number to ensure that the instruction set base can reach a relatively high level in the industry. Based on this, we will expand to the fields of artificial intelligence, graphics rendering and high-performance computing, and gradually realize the integrated computing architecture of CPU, NPU and GPU.
+
+At present, LinxISA has reached a level similar to the ARM architecture in coding optimization, and the static code size (codesize) is approximately 0.9 times that of the ARM architecture. Although the static code has been relatively optimized, LinxISA still has about 40% more dynamic instructions than ARM. The expansion of the number of dynamic instructions directly affects execution efficiency and overall performance. Especially when facing computationally intensive tasks, the increase in the number of instructions will lead to additional processing delays and waste of computing resources. 2025 is regarded as a key year for LinxISA to be widely used in many fields. To stand out from the competition, we need an instruction set that can surpass existing mainstream architectures (such as ARM and x86) in performance, instruction count and code density. Although good progress has been made on the road to catch up, more efforts and innovation are needed to truly achieve transcendence, especially to achieve ultimate optimization in all aspects of instruction set design. Therefore, we are not satisfied with the design of v0.43. We hope that in the v0.5 version, we will focus on significantly reducing the number of dynamic instructions, further improving execution efficiency, and optimizing code density and variable-length encoding. Therefore, the core goal of this version is to reduce redundant instructions while ensuring performance and stability through targeted optimization, and ensure the efficient performance of the instruction set in practical applications.
+
+The following is the LinxISAV0.5 version evolution plan:
+
+{ width="800" }
+
+## Update Summary
+
+- Adjust the instruction encoding framework: Unify the planning of 16bit/32bit/48bit/64bit instruction formats and reasonably reserve encoding space;
+- Replan the instruction space, cancel the custom space of different block type in 32bit, and simplify the hardware decoding complexity.
+- Complete the scalar command function to ensure the perfection of the scalar base.
+- Added 48bit command support to improve parameter configuration efficiency in AI/rendering scenarios; including: dual output commands, Long Immediate loading commands, Load Literal commands, and complex operation commands.
+
+## Specific content
+
+### 1. Instruction encoding
+
+In order to solve the problem of encoding duplication in different blocks, we eliminated the encoding space in private blocks and restructured it. At the same time, the **prefix+suffix** encoding method is introduced to ensure that there is still enough instruction space and to improve the expressive ability of instructions within the block.- **48-bit instruction**: consists of a `16位前缀` plus a `32位主指令` or `32位后缀`. The prefix part is mainly used to expand the high-bit information of the opcode and immediate data to meet the needs of long immediate data loading and complex memory operations.
+- **64-bit instructions**: It consists of `32位前缀` and `32位主指令` or `32位后缀`, providing sufficient coding space for more extreme complex operations.
+
+{ width="800" }
+
+- Main directive: a directive that defines specific semantics independently without prefix.
+- Main instruction + prefix instruction: The prefix instruction only completes the information of the main instruction and does not affect the instruction semantics.
+- Prefix command: It must match the main command or suffix command to have meaning. Usually used to complete additional information.
+- Suffix command: It must match the prefix command to have meaning. The suffix command alone has no meaning.
+
+| Combination | 16bit instruction | 16bit prefix instruction | 32bit main instruction | 32bit suffix instruction | 32bit prefix instruction |
+|------|-----------|---------------|---------------|-----------|-------------|
+| 16bit instruction | - | × | - | × | × |
+| 16bit prefix instruction | × | × | √ | √ | × |
+| 32bit main instruction | - | × | - | × | × |
+| 32bit suffix instructions | × | × | × | × | × |
+| 32bit prefix instructions | × | × | √ | √ | × |
+
+This prefix + suffix structure not only effectively avoids duplication and conflicts of encoding between different instruction blocks, but also makes the instruction decoding process clearer and more modular, allowing the hardware to flexibly handle instructions of different lengths during parsing.
+
+### 2. Command naming
+
+Distinguish instructions with different word lengths through instruction prefixes and standardize instruction naming. Easy for programmers to understand and use.
+
+1. 16bit compression instructions are uniformly prefixed with "C." or "c.".
+2. 48bit enhanced instructions are uniformly prefixed with "HL." or "hl.".
+3. 64bit long instructions are uniformly prefixed with "L." or "l.".
+
+### 3. Command combination
+
+16bit, 32bit, 48bit and 64bit instructions with different word lengths are allowed to be mixed. All instructions use the same encoding space for encoding, so they can be mixed.
+
+### 4.16bit instruction
+
+1. Overall adjustment of 16bit instruction encoding
+2. Delete the B.NEXT.C instruction, and the long jump of header is encoded through the 48bit or 64bit version of the BSTART instruction.
+3. The c.addpc instruction was renamed to c.setret. The modification to c.setret is more consistent with the instruction semantics and is easier for programmers to use and understand.
+4. Delete the instruction c.addtpc and add the 48bit Load/Store PC-Relative instruction to replace this instruction function.
+
+{ width="800" }
+
+This version adds a 48-bit Load/Store PC-relative instruction, which can replace the combination of c.addtpc and load/store instructions to load symbols, so this instruction is deleted.
+
+The way to load symbols in previous versions:
+```asm
+ c.addtpc %hi(symbol), ->t
+ ldi [t#1, %lo(symbol)], ->t
+```
+Current version:
+```asm
+ hl.ld.pcr [symbol], ->t
+```
+
+### 5.32bitheader instruction1. The BSTART instruction **removes the EX bit** and the BlockType field is expanded to 5 bits. Subsequently, the 48bit and 64bit versions of the long jump headerBSTART are added, so the B.NEXT instruction is no longer needed. The 32bit version of the BSTART instruction does not need to use the EX bit to indicate the jump distance and splicing with B.NEXT.
+2. Delete the B.NEXT instruction
+3. The block input/output instruction B.IO is renamed to B.IOR to distinguish other B.IO instructions that will be expanded later.
+4. Add EBREAK instruction to provide software breakpoint function
+
+{ width="800" }
+
+### 6.32bit microinstructions
+
+The modified instructions in this version are as follows:
+
+1. The addpc command is renamed to setret and the code is reused with addtpc. Multiplexing encoding with addtpc can save Opcode space and reserve more space for subsequent expansion.
+2. Adjust the semantics of ctz and clz instructions, and add M and N parameters in assembly (compatible with the functions of ctzw and clzw). After the modification, the instruction implementation is more flexible, and the encoding method of bit operation instructions tends to be unified.
+3. rev16, rev32 and rev64 are combined into one rev instruction. The encoding format is unified, and the instruction implementation is more flexible.
+4. Add the bcnt instruction to supplement the scalar instruction function, which is used to count the number of bits in the register that are 1.
+5. The third input SrcR of the csel instruction adds the ".neg" optional parameter. After adding this parameter, the cneg operation can be implemented, and a register original value or a negative value can be selected according to conditions. The benefit of reducing the number of dynamic instructions can be obtained in the 525 subkey.
+6. Added 7 Load PC-Relative instructions and 4 Store PC-Relative instructions. Improve the efficiency of symbolic address loading, and further improve the performance and code density of the instruction set by reducing the frequency of use of the T register.
+7. The far parameter is added to the atomic instruction, and the encoding of the high-order command ID field is modified to provide atomic operations on a specific cache level.
+8. Add the bwt instruction in the system block to wake up the thread after waiting for the specified time.
+9. The parameter encoding position of the acrc and acre instructions has been adjusted, and the target ACR parameter of the acre instruction is deleted. The target ACR of the privilege level switch triggered by the acre instruction is specified by the ECSTATE register.
+10. The cvt instructions in the floating point block are split into fcvt, scvtf, ucvtf, fcvta, fcvtm, fcvtn, fcvtp, fcvtz and other instructions. Corresponding rounding modes are provided for different data format conversion scenarios.
+11. Add the BSTART.CALL instruction, specifically the pseudo-instruction expressed by the combination of the C.BSTART.CALL instruction and c.setret.
+
+After upgrading to version 0.50, the list of deleted 32bit instructions is as follows:
+
+| Command List | Description |
+|----------|-----------|
+| b.eq, b.ne, b.lt, b.ge, b.ltu, b.geu, j, jr | Intra-block jumps are not supported for the time being. Jump scenarios are uniformly implemented using inter-block jumps. (Reserve coding space if needed for subsequent verification) |
+| b.feq, b.fne, b.flt, b.fge | Intra-block jumps are not supported at the moment |
+| fsin, fcos, fclass, flog | The previous version has design content and is officially deleted. |
+
+Moved to 48bit extended space instruction list| Category | Command List | Description |
+|------|----------|---------|
+| 1. store.a class | sb.a, sh.a, sw.a sd.a, sh.ua, sw.ua, sd.ua
sbi.a, shi.a, swi.a sdi.a, shi.ua, swi.ua, sdi.ua | Supplement the destination register encoding and add the flag bit of Pre/Post Index by adding 16bit prefix. |
+| 2. system register access | ssrrd, ssrwr renamed to hl.ssrget and hl.ssrset. | Expand the SSR ID expression space by adding a 16-bit prefix. |
+| 3. With immediate multiplication and addition/subtraction | miadd, misub | Expand the range of immediate numbers by adding a 16bit prefix. |
+| 4. Bit operations | bfi, ccat, ccatw | Express dual output or extended parameter domain by adding 16bit prefix. |
+| 5. Prefetch operation | prf, prf.a, prfi.u, prfi.ua | By adding a 16-bit prefix, the field indicating the prefetch target cache can be uniformly encoded. |
+| 6. General queue management | qmt, qpush, qpop | By adding a 16bit prefix, dual output can be encoded. |
+| 7. Atomic comparison exchange | casb, cash, casw, casd | By adding a 16bit prefix, more register inputs can be encoded. |
+
+### 7. Add 48bit instructions| Category | Instruction List |
+|------|----------|
+| 1. Enhanced version of BSTART | HL.BSTART |
+| 2. CALL block header | HL.BSTART.CALL |
+| 3. Long immediate data loading | hl.lis, hl.liu, hl.lui |
+| 4. Multiplication double output | hl.mul, hl.mulu, hl.madd, hl.maddw |
+| 5. ALUI class | hl.addi, hl.subi, hl.andi, hl.ori, hl.xori |
+| 6. ALUWI class | hl.addiw, hl.subiw, hl.andiw, hl.oriw, hl.xoriw |
+| 7. CMPI class | hl.cmp.eqi, hl.cmp.nei, hl.cmp.andi, hl.cmp.ori, hl.cmp.lti, hl.cmp.gei, hl.cmp.ltui, hl.cmp.geui |
+| 8. SETCI class | hl.setc.eqi, hl.setc.nei, hl.setc.andi, hl.setc.ori, hl.setc.lti, hl.setc.gei, hl.setc.ltui, hl.setc.geui |
+| 9. TPC-Relative | hl.addtpc, hl.setret |
+| 10. Divide remainder | hl.div, hl.divu, hl.divw, hl.divuw, hl.rem, hl.remu, hl.remw, hl.remuw |
+| 11. Load long immediate offset | hl.lbi, hl.lhi, hl.lwi, hl.ldi, hl.lbui, hl.lhui, hl.lwui, hl.lhi.u, hl.lwi.u, hl.ldi.u, hl.lhui.u, hl.lwui.u |
+| 12. Load Pair (register base address + register offset) | hl.lbp, hl.lhp, hl.lwp, hl.ldp, hl.lbup, hl.lhup, hl.lwup |
+| 13. Load Pair (register base address + immediate offset) | hl.lbip, hl.lhip, hl.lwip, hl.ldip, hl.lbuip, hl.lhuip, hl.lwuip, hl.lhip.u, hl.lwip.u, hl.ldip.u, hl.lhuip.u, hl.lwuip.u |
+| 14. Load Pre-Index (register base address + register offset) | hl.lb.pr, hl.lh.pr, hl.lw.pr, hl.ld.pr, hl.lbu.pr, hl.lhu.pr, hl.lwu.pr |
+| 15. Load Pre-Index (register base address + immediate offset) | hl.lbi.pr, hl.lhi.pr, hl.lwi.pr, hl.ldi.pr, hl.lbui.pr, hl.lhui.pr, hl.lwui.pr, hl.lhi.upr, hl.lwi.upr, hl.ldi.upr, hl.lhui.upr, hl.lwui.upr |
+| 16. Load Post-Index (register base address + register offset) | hl.lb.po, hl.lh.po, hl.lw.po, hl.ld.po, hl.lbu.po, hl.lhu.po, hl.lwu.po || 17. Load Post-Index (register base address + immediate offset) | hl.lbi.po, hl.lhi.po, hl.lwi.po, hl.ldi.po, hl.lbui.po, hl.lhui.po, hl.lwui.po, hl.lhi.upo, hl.lwi.upo, hl.ldi.upo, hl.lhui.upo, hl.lwui.upo |
+| 18. Load PC-Relative addressing instructions | hl.lb.pcr, hl.lh.pcr, hl.lw.pcr, hl.ld.pcr, hl.lbu.pcr, hl.lhu.pcr, hl.lwu.pcr |
+| 19. Store long immediate offset | hl.sbi, hl.shi, hl.swi, hl.sdi, hl.shi.u, hl.swi.u, hl.sdi.u |
+| 17. Store Pair (register base address + register offset) | hl.sbp, hl.shp, hl.swp, hl.sdp, hl.shp.u, hl.swp.u, hl.sdp.u |
+| 18. Store Pair (register base address + immediate offset) | hl.sbip, hl.ship, hl.swip, hl.sdip, hl.ship.u, hl.swip.u, hl.sdip.u |
+| 13. Store Pre-Index (register base address + register offset) | hl.sb.pr, hl.sh.pr, hl.sw.pr, hl.sd.pr, hl.sh.upr, hl.sw.upr, hl.sd.upr |
+| 14. Store Pre-Index (register base address + immediate offset) | hl.sbi.pr, hl.shi.pr, hl.swi.pr, hl.sdi.pr, hl.shi.upr, hl.swi.upr, hl.sdi.upr |
+| 15. Store Post-Index (register base address + register offset) | hl.sb.po, hl.sh.po, hl.sw.po, hl.sd.po, hl.sh.upo, hl.sw.upo, hl.sd.upo |
+| 16. Store Post-Index (register base address + immediate offset) | hl.sbi.po, hl.shi.po, hl.swi.po, hl.sdi.po, hl.shi.upo, hl.swi.upo, hl.sdi.upo |
+| 21. Store PC-Relative | hl.sb.pcr, hl.sh.pcr, hl.sw.pcr, hl.sd.pcr |
+
+### 64bit instruction
+
+This version does not modify the 64-bit instructions in the original SIMT block for the time being, and will be modified uniformly in the subsequent version 0.51.| Classification | Command | Description |
+|------|-------|------|
+| 1. Added long jump header | L.BSTART | Used in ultra-long jump scenarios, supporting 42-bit jump offset. |
+| 2. Added CALL block header | L.BSTART.CALL | Provides a wider range of return address offsets than the HL.BSTART.CALL instruction |
+| 3. Add long immediate addition instruction | l.addli | Used in combination with hl.lui to load 64-bit long immediate. |
+| 4. Added Load PC-Relative addressing instructions | l.lb.pcr, l.lh.pcr, l.lw.pcr, l.ld.pcr, l.lbu.pcr, l.lhu.pcr, l.lwu.pcr | Improve the efficiency of symbol address loading and reduce the frequency of use of T register. Provides longer offset distance than 32bit and 48bit versions. |
+| 5. Added Store PC-Relative addressing instructions | l.sb.pcr, l.sh.pcr, l.sw.pcr, l.sd.pcr | Provide longer offset distance than 32bit and 48bit versions. |
+| 6. Added atomic comparison and exchange instructions | l.casbp, l.cashp, l.caswp, l.casdp | Provide atomic comparison and exchange operations for two elements |
\ No newline at end of file
diff --git a/docs/change_log/update_v0.51.md b/docs/change_log/update_v0.51.md
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+# 0.51 version update
+
+Update date: June 11, 2025
+
+For the path to the web version of the instruction encoding design document, please see [LinxISA Encoding-0.51](https://dbox.huawei.com/detaildocs?oid=VR:wt.doc.WTDocument:100980339929)
+
+The most important change in version LinxISA0.51 is the introduction of parallel block design and the supplement of the definition of architectural state around the content of parallel blocks.
+
+Parallel block instruction evolved from SIMTblock instruction in version 0.4. In order to avoid patent and intellectual property issues, the SIMT block naming in version 0.51 was changed to **Parallel Block**. On this basis, the design of Tile Register is added to architectural state and the definition of vector instructions is refreshed, so that the parallel block can more efficiently carry out large-scale computing tasks in the fields of artificial intelligence, graphics rendering and high-performance computing.
+
+
+
+## Update Summary
+
+| Classification | Description |
+|-------|-------|
+| First layer architectural state | Add 32 Tile Registers:
1.T#1-T#8
U#1-U#8
M#1-M#8
N#1-N#8 |
+| Status within the parallel block | Add 8 scalar registers: T#1-T#4, U#1-U#4 |
+| Status within the parallel block | vector registers reduced from 32 to 16: VT#1-VT#4, VU#1-VU#4, VM#1-VM#4, VN#1-VN#4 |
+| Parallel block internal status | Loop control register changed to block internal status: LB0-LB2, LC0-LC2 |
+| Parallel block internal status | Add mask register: P register |
+| Add header instruction | B.DIM, C.B.DIM, C.B.DIMI, B.IOT |
+| Recovery block jump instruction encoding | b.eq, b.ne, b.lt, bge, b.ltu, b.geu, jr, j |
+| Add two jump instructions | b.z, b.nz |
+| scalar register modification | T and U registers modified to non-fixed bit width |
+| Added 8 shuffle instructions | shfl.up, shfl.down, shfl.bfly, shfl.idx, shfli.up, shfli.down, shfli.bfly, shfli.idx |
+| Modification of ALU class instructions | Restore optional parameters for input (.neg and .not) |
+| Instruction input/output | Some instructions add P register input/output |
+| Instruction behavior definition | Reduce instruction output behavior redefinition |
+| Delete command | loop.get, loop.set |
+| Delete system register | LPCB0, LPCE0, LPCB1, LPCE1, LPCB2, LPCE2 |
\ No newline at end of file
diff --git a/docs/change_log/update_v0.52.md b/docs/change_log/update_v0.52.md
new file mode 100644
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+++ b/docs/change_log/update_v0.52.md
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+# 0.52 version update
+
+Update date: June 30, 2025
+
+For the path to the web version of the instruction encoding design document, please see [LinxISA Encoding-0.52](https://dbox.huawei.com/detaildocs?oid=VR:wt.doc.WTDocument:100994184997)
+
+## 1. Version update background
+
+LinxISA completes the complement of scalar and vector operation instructions in versions 0.50 and 0.51. The update of version 0.52 focuses on expanding and improving the computing instructions related to tensor, aiming to further improve the computing power in AI scenarios such as large-scale pre-training models. Through the block instruction framework built on the basis of version 0.5, LinxISA implements the supplement of data block operations (TileOP) and enhances the support for data blocks of different sizes, different dimensions and formats.
+
+This update introduces the new concept of data block instruction (TileOP), which enables the hardware to optimize the management of various calculation blocks, thereby processing multi-dimensional tensor operations more efficiently, especially when processing large-scale data sets and complex models. LinxISA further improves the flexibility and performance of LinxISA by extending the computing of tensor, especially its application in distributed AI computing tasks.
+
+## 2. Definition of basic concepts
+
+With the introduction of data block instruction, the implementation of TileOP will also involve some new concepts, as follows:
+
+- Tile: Data block refers to the smallest computing unit that can be processed.
+- Tile Register: The basic hardware unit for storing data blocks.
+- Tile Operation (TileOP): Data block instruction refers to instructions for processing and operating data blocks.
+- Tensor: tensor, usually consists of multi-dimensional data, has fixed data width and format, and can be segmented (Tiling) into multiple data blocks.
+- Tensor Operation: tensor calculation, covering basic operations from element-wise calculation to more complex matrix multiplication, extraction (Extract), split (Split), merge (Concat), transpose (Transpose) and other basic operations. They constitute the basic element calculation for tensor.
+- CodeGen (also called MicroCodeEngine): template block generation unit of Linx core. The unit generates the corresponding instruction sequence by receiving the template block header.
+- FixPipe: Non-detachable block instruction, usually performed by hardened pipelines, including CUBE and SORT units.
+
+Operation example for Tile:
+```c
+ Tile <16,16,16> a;
+ Tile <16,16,16> b;
+ Tile <32,16,16> c;
+ c = concat.row(a, b) # 将两个Tile按照行维度拼接
+```
+
+The introduction of new instructions can better support tensor segmentation and combination in large-scale AI operations, improving the computing efficiency of the instruction set.
+
+## 3. Detailed definition
+
+LinxISA version 0.52 extends metacomputing support for tensor by introducing template block. These template block appear as template instructions in assembly format, or macro instructions with header but no specific body. These block instruction are defined as data block instruction (Tile Block Instruction), which further enhances LinxISA's processing capabilities for large-scale data block calculations. The list of data block instruction provided in this version is as follows:
+
+**Category 1: Matrix Operations**
+
+| Data block name/TileOP | Description | Remarks |
+|------------------|-------|-----------|
+| MAMULB | A matrix times B matrix |
+| MAMULB.ACC | A matrix multiplied by B matrix, accumulated to C matrix |
+| MAMULBT | A matrix multiplied by transpose of B matrix |
+| MAMULBT.ACC | A matrix multiplied by the transpose of B matrix, accumulated to C matrix |**Category 2: vector operation**
+
+| Data block name/TileOP | Description | Remarks |
+|------------------|-------|-----------|
+| VCALL | Separation block, body definition function |
+| TADD | Element-wise addition of two data blocks |
+| TSUB | Subtract two data blocks element by element |
+| TMUL | Element-wise multiplication of two data blocks |
+| TDIV | Element-wise division of two data blocks |
+| TMAX | Compare the maximum value of two data blocks element by element |
+| TADDS | Add data block element by element with scalar |
+| TSUBS | Data block is subtracted element by element from scalar |
+| TMULS | Data block element-wise multiplication with scalar |
+| TDIVS | Data block element-wise division by scalar |
+| TMAXS | Data block element-by-element comparison with scalar for maximum value |
+| TEXP | Find the natural exponent of a data block element by element |
+| TSQRT | Find the square root of a data block element by element |
+| TRECIP | Find the reciprocal of data block element by element |
+| TABS | Find the absolute value of data block element by element |
+| TCAST | Data block element-by-element data format conversion |
+| TROWSUM | Data block row sum reduction |
+| TROWMAX | Data block row maximum reduction |
+| TROWSUMEXP | Data block row sum reduction then expansion |
+| TROWMAXEXP | Data block row maximum reduction then expansion |
+
+**Category Three: Data Transfer**
+
+| Data block name/TileOP | Description | Remarks |
+|------------------|-------|-----------|
+| MCALL | Separation block, body definition function |
+| TCOPYIN | Copy from memory ddr or remote to Tile Register |
+| TCOPYOUT | Copy from Tile Register to memory ddr or remote |
+| TCOPY | Copy between Tile Registers |
+
+In the above TileOP list, VCALL and MCALL are used to define separate blocks, which are sent to the Vector core and Memory core for execution respectively during hardware execution. The remaining TileOP is defined as template block.
+
+All data block instruction (TileOP) can be expressed using a complete assembly format, the format is as follows:
+```asm
+分离块：TileOP body_label, SrcTile0, SrcTile1, SrcTile2, [BGetList], ->DstTileType, [BSetList]
+ZXTERMZH36QXZ：TileOP SrcTile0, SrcTile1, SrcTile2, [BGetList], ->DstTileType, [BSetList]
+```
+A complete assembly can be broken down into the following instructions:
+
+- BSTART.PAR: Defines the starting position of parallel block instruction and the TileOP implemented by this block, etc.
+- B.DIM: Dimension information of the matrix or data block operated by this block.
+- B.IOT: Tile Registerinput/output of this block and the space for output Tile.
+- B.IOR: Global register input/output of this block.
+- B.TEXT: body location information.
\ No newline at end of file
diff --git a/docs/change_log/update_v0.53.md b/docs/change_log/update_v0.53.md
new file mode 100644
index 00000000..e8bff83d
--- /dev/null
+++ b/docs/change_log/update_v0.53.md
@@ -0,0 +1,605 @@
+# 0.53 version update
+
+Update date: August 4, 2025
+
+For the path to the web version of the instruction encoding design document, please see [LinxISA Encoding-0.53.2](https://dbox.huawei.com/detaildocs?oid=VR:wt.doc.WTDocument:101071672597)
+
+## 1. Update background description
+
+With the rapid development of artificial intelligence, especially large-model reasoning scenarios, the demand for computing resources is increasing day by day. AI chip architecture is facing multiple challenges such as computing power density, energy efficiency ratio, and diversified accuracy support. As a block-level instruction set for optimized design of AI chips, LinxISA needs to continue to adapt to emerging computing needs while maintaining efficient programmability.
+
+The update background of this version 0.53 mainly includes the following three aspects:
+
+1. **Increased demand for low-precision computing support for large model inference**: Current mainstream large model inference scenarios (such as LLM, CV model deployment) widely use low-bit precision data formats such as INT4, FP4, and FP6 to significantly compress the model volume and reduce storage bandwidth and power consumption. In order to adapt to this trend, LinxISA needs to expand its expression and operation support for a variety of non-standard low-precision data formats.
+2. **Block-level execution model has higher requirements for flexibility and efficiency**: In actual compilation and execution, the instruction model of the original Tile block has problems such as the rigidity of block structure restrictions, high ICache pressure, and difficulty in instruction reuse, making it difficult to support high-density parallel instruction fusion and more complex data flow graph scheduling. Therefore, it is necessary to decouple block execution semantics and structure to improve scheduling freedom and hardware execution efficiency.
+3. **AI computing core instruction requirements continue to increase**: As more and more matrix micro-kernels, multi-channel fusion, mixed-precision multiplication and addition, non-linear activation approximation (such as LUT) and other operations appear in large model inference, higher expression ability requirements are put forward for ISA. The instruction set needs to support:
+ - Composable matrix operation process (calculation + quantification + writing)
+ - Flexible preprocessing (such as Merge, Saturate, Round)
+ - Structural parallel operations such as dot product (dot)
+
+## 2. Summary of updated content
+
+Therefore, LinxISA 0.53.0 has made the following directional adjustments in design:
+
+- Introducing new parallel block execution model (multi-block fusion, formal parameter support)
+- Extended support for FP4, INT4, and FP6 data formats and matrix operations and conversion instructions
+- Streamline uncommonly used complex function instructions (such as sin, cos, log) and focus on high-frequency scenarios
+- Optimize the expression of register release information| Category | Matter | Description |
+|------|-------|--------|
+| **Changes in separated block execution model** | 1. The index global register within the block changes from actual parameters to formal parameters | Reduce the icache footprint pressure of vector PE and enable body merging of multiple blocks |
+| **Microinstruction changes within the parallel block** | 1. Data format conversion instruction extension | In order to support applications in a wider range of AI inference and edge computing scenarios |
+| | 2. Streamline instructions in parallel blocks | Delete complex operations such as sin, cos, log, etc. |
+| | 3. Delete the bf16 and flb type operands of general floating point calculation instructions | Special precision floating point numbers are expressed by specifying opcode |
+| | 4. The kill information of the vector register is changed to reuse | In most scenarios, registers are used once, so registers used multiple times are marked with reuse instead |
+| **Data block instruction modification** | 1. The kill information of Tile Register is changed to reuse | In most scenarios, registers are used once, so registers used multiple times are marked as reuse instead |
+| | 2. The data move instruction adds a relative index barrier | Used to solve the problem of out-of-order execution between COPYIN and COPYOUT being unable to express data dependencies. |
+| | 3. Revision of matrix operation instructions | Only output to ACC is allowed |
+| | 4. Delete the result matrix operation instructions with transpose | MAMULBT, MAMULBACT and MAMULB.ACCT. |
+| | 5. Added ACCCVT instruction | Used for FIXPIPE processing in the process of moving data from ACC register to T/U/M/N register. |
+| | 6. Added TCVT instruction | Used to convert the layout and element type of data in the T/U/M/N registers. |
+| | 7. B.ARG instruction adds SrcType field | Instruction design to adapt to TCVT |
+| | 8. Simplified implementation of TCOPY instruction | Only used for copying from Tile register to Tile register in scenarios without data format conversion |
+| | 9. TCOPYIN | Name changed to TLOAD, and support data layout transformation |
+| | 10. TCOPYOUT | Name changed to TSTORE and support data layout transformation |
+| | 11. B. ARG instruction adds PadValue field | Instruction design adapted to TLOAD |
+
+## 3. Update details
+
+### 1. Change the separated block to formal parameter index global register
+
+The implementation logic for body is the same, but the separate blocks of global registers used are different. If the global register used in body can be made into a formal parameter, then this body can be multiplexed by multiple block instruction, and then the header of multiple block instruction can be called by passing different actual parameters. This method can enable body merging of multiple blocks, effectively reducing PE's icache fetch pressure. Therefore, in the new version, we propose a definition of global registers indexed through formal parameters within the block.Example of detached blocks defined in previous versions:
+```asm
+BSTART.PAR MCALL .L1_body [a1, a2, s0], ->T<256B>
+BSTART.PAR MCALL .L2_body [a3, a4, a5], ->T<128B>
+...
+.L1_body:
+ l.madd lc0.uh, a1.uh, lc1.uh, ->vu.w
+ l.lw [a2.sd, vu#1.sw<<2], ->vt.w
+ l.madd lc1.uh, s0.uh, lc0.uh, ->vu.w
+ l.sw vt#1.sw, [to.ud, vu#1.sw<<2]
+ bstop
+.L2_body:
+ l.madd lc0.uh, a3.uh, lc1.uh, ->vu.w
+ l.lw [a4.sd, vu#1.sw<<2], ->vt.w
+ l.madd lc1.uh, a5.uh, lc0.uh, ->vu.w
+ l.sw vt#1.sw, [to.ud, vu#1.sw<<2]
+bstop
+```
+In previous versions, even if the body execution logic of the two blocks was the same, because the global registers used by the instructions were different, two body still needed to be defined, occupying two memory spaces.
+
+New version of detached block example:
+```asm
+BSTART.PAR MCALL .L1_body [a1, a2, s0], ->T<256B>
+BSTART.PAR MCALL .L1_body [a3, a4, a5], ->T<128B>
+...
+.L1_body:
+ l.madd lc0.uh, ri0.uh, lc1.uh, ->vu.w // ri0映射到ZXTERMZH32QXZ第1个输入GPR
+ l.lw [ri1.sd, vu#1.sw<<2], ->vt.w // ri1映射到ZXTERMZH32QXZ第2个输入GPR
+ l.madd lc1.uh, ri2.uh, lc0.uh, ->vu.w // ri2映射到ZXTERMZH32QXZ第3个输入GPR
+ l.sw vt#1.sw, [to.ud, vu#1.sw<<2]
+ bstop
+```
+
+In the new version, we require the use of formal parameters in the separated block body to index global registers, such as "ri0, ri1, ri2" in the above code. In this way, the two MCALL blocks above can use the same body, and flexibly specify which GPRs to enter as needed.
+
+- When the first MCALL is executed, ri0 is mapped to a1, ri1 is mapped to a2, and ri2 is mapped to s0.
+- When the second MCALL is executed, ri0 is mapped to a3, ri1 is mapped to a4, and ri2 is mapped to a5.
+
+Through this implementation method, the original two body can be merged into one to reduce the PE icache fetch pressure.
+
+In the new version, we have defined 16 formal parameter registers, including 12 inputs and 4 outputs:
+
+- The 12 input registers are named RI0-RI11. (RI – Register Input)
+- The 4 output registers are named RO0-RO3 respectively. (RO – Register Output)
+
+Example:
+```asm
+ BSTART.PAR MCALL .L1_body [a1, a2, a1], ->T<256B> ；允许输入GPR重复
+ BSTART.PAR MCALL .L3_body [a1, a2, a1], ->T<256B> [s0, s0, s1] ；不允许输出GPR重复
+```
+The register index encoding is modified as follows:
+
+{ width="800" }
+
+At the same time, in order to adapt to the above modifications, the index coding of the zero register by the instructions in the parallel block has also been updated. The coding modification is as follows:
+
+{ width="800" }
+
+### 2. Modification of data format conversion instructions
+
+In order to support the application of LinxISA in a wider range of AI inference and edge computing scenarios, especially the ability to deploy large models in resource-constrained environments, version 0.53 has systematically enhanced data format support and conversion instructions as well as its special decoding method.
+
+2.1 Supported formats
+
+In the previous version, LinxISA already supported the following mainstream data formats:
+
+| Format name | Format description |
+|---------|-------------|
+| FP64 | 64bit double precision floating point (e11m52) |
+| FP32 | 32bit single precision floating point number (e8m23) |
+| FP16 | 16bit half-precision floating point number (e5m10) |
+| FP8 | 8bit low-precision floating-point number (e4m3) |
+| BF16 | 16bit half-precision floating point number (e8m7) |
+| FP8 | 8bit low-precision floating-point number (e5m2) |
+| S64/32/16/8 | 64/32/16/8 bit signed integer |
+| U64/32/16/8 | 64/32/16/8bit unsigned integer |
+
+However, as inference models become increasingly larger, there is an increasingly urgent need to further compress model storage and reduce bandwidth pressure. To this end, the new version adds the following content:
+
+| Format name | Bit width | Structure | Description |
+|---------|-------|-----|-----------|
+| TF32 | 32b | e8m10 | High-speed training format |
+| HF32 | 32b | e8m11 | High dynamic range format |
+| HiF8 | 8b | vendor-specific low-precision data format | Specific model compression optimization |
+| SF8 | 8b | e8m0 | Dynamic range encoding, sparse representation |
+| FP6 | 6b | e3m2 / e2m3 | Extremely compressed floating point numbers |
+| FP4 | 4b | e2m1 / e1m2 | Super low-precision floating-point number |
+| HiF4 | 4b | vendor-specific low-precision data format | Specific model compression optimization |
+| S/U4 | 4b | Signed/unsigned integer | Commonly used for edge reasoning |For non-standard data formats, no special calculation instructions are provided. You can use the conversion command (Convert) to convert the non-standard data format into a standard format, perform calculations, and then convert it back to the original format.
+
+2.3 Data format conversion instruction type
+
+Linx supports the following four types of format conversion instructions, all of which support low-precision formats:
+
+- FCVT: floating point to floating point: `l.fcvt.{st2dt} SrcL., ->Dst.`
+- FCVTI: floating point to integer: `l.fcvti.{st2dt} SrcL., ->Dst.`
+- ICVTF: integer to floating point: `l.icvtf.{st2dt} SrcL., ->Dst.`
+- ICVT: integer to integer: `l.icvt.{st2dt} SrcL., ->Dst.`
+
+Assembly example:
+```asm
+ l.fcvt.f162f32 vt#1.fh, ->vt.w
+ l.fcvti.f322s8 vt#2.fs, ->vt.b
+ l.icvtf.s162f8 vu#3.sh, ->vt.b
+ l.icvt.s322s4 vu#4.sw, ->vt.b
+```
+
+2.4 Instruction encoding update
+
+- The SrcType and DstType fields have been expanded in the instruction encoding to support all new formats.
+- The function fields of L.ICVT and L.ICVTF have been updated.
+
+The instructions are encoded as follows:
+
+{ width="800" }
+
+2.5 Conversion example
+
+| Operation target | Assembly example |
+|----------|-------------|
+| FP32 → FP8 | `l.fcvt.f322f8 vt#1.fs, ->vt.b` |
+| FP8 → S8 | `l.fcvti.f82s8 vt#2.fb, ->vt.b` |
+| S8 → FP16 | `l.icvtf.s82f16 vt#3.sb, ->vt.h` |
+| S32 → S4 | `l.icvt.s322s4 vt#4.sw, ->vt.b` |
+
+### 3. Remove variant floating point calculations
+
+The current version deletes variant floating point calculations, including BF16, FP8 (E5M3) and other formats.
+
+{ width="800" }
+
+This version does not support floating point calculations in variant data formats, but provides the Convert instruction. Convert variant data format to standard data format for calculation.
+
+### 4. Streamlining instructions in parallel blocks
+
+After upgrading to version 0.5, the parallel block supports instruction mixing of different lengths. Address calculation and system register access operations can use the 32bit version, so the 64bit version is removed. On the other hand, the hardware implementation of operation instructions such as sine, cosine and logarithm is more difficult and can be implemented through other instruction combinations, so it is deleted.
+
+The list of deletion instructions is as follows:
+
+| Classification | Instructions |
+|--------------------|------------------|
+| Long immediate load/address calculation | l.addtpc, l.lui |
+| system register access | l.ssrget, l.ssrset |
+| Complex calculation class | l.fsin, l.fcos, l.flogb |
+
+The delete command is encoded as follows:
+
+{ width="800" }
+
+{ width="800" }
+
+{ width="800" }
+
+### 5. Change the kill information in the vector register to reuse information
+
+In the previous version, in order to improve register usage efficiency, the software can actively add ".kill" information to the vector register in the parallel block to indicate that the register is used for the last time and can be released after use.
+
+The new version is modified to specify that the register will still be used by adding ".reuse" information and is not allowed to be released temporarily. For the last used register, specify that the register can be released after use by not adding ".reuse".
+
+For example:
+```asm
+ l.add vt#1.sw, vt#2.reuse.sw, ->vt.w # 本指令提交后，不允许硬件释放掉vt#2寄存器。
+ l.ldi [vu#4.ud, 8], ->vt.d # 本指令提交后，允许硬件释放掉vu#4寄存器。
+```
+
+Things to note:- All instructions that support reading the vector register support actively releasing the vector register read by this instruction.
+- When it is uncertain whether subsequent instructions use this register, the reuse flag needs to be added.
+- The scalar register does not need to be marked with reuse information.
+- After the vector register is released, if there is a subsequent instruction to read the register, the hardware should generate exception. That is, only the last used register can be actively released.
+
+### 6.The kill information of Tile Register is changed to reuse information.
+
+In order to improve the utilization of Tile Register, the previous version provided the definition of actively releasing the Tile registers read by this block for the parallel block instruction, that is, adding kill information to the registers that are no longer used.
+
+In this version, we modified it to use ".reuse" information to specify which registers will still be used and do not allow hardware release. The assembly format is as follows:
+```asm
+分离块：TileOP body_label, SrcTile0<.reuse>, SrcTile1<.reuse>, SrcTile2<.reuse>, [BGetList], ->DstTileType, [BSetList]
+ZXTERMZH36QXZ：TileOP SrcTile0<.reuse>, SrcTile1<.reuse>, SrcTile2<.reuse>, [BGetList], ->DstTileType, [BSetList]
+```
+Example:
+```
+ TADD T#7.reuse, T#2, ->T<32KB> ; 本指令提交后T#2允许释放，T#7不允许。
+ TCOPYOUT U#4.reuse, [a0] ; 本指令提交后，U#4不允许释放
+```
+The information about whether the Tile Register is retained (reuse) is encoded in the B.IOT or B.IOTI instructions. The updated definitions of these two instructions are as follows:
+
+Assembly format:
+```asm
+ B.IOT [SrcTile0<.reuse>, SrcTile1<.reuse>], group={0,1}, ->DstTile # 通过寄存器RegSrc设置输出Tile的大小
+ B.IOTI [SrcTile0<.reuse>, SrcTile1<.reuse>], group={0,1}, ->DstTile # 通过立即数Size设置输出Tile的大小
+```
+
+Encoding format:
+
+{ width="800" }
+
+The instruction encoding method is modified as follows:
+
+- The S0K flag is modified to S0R (Reuse Source0): This flag is used to indicate whether SrcTile0 will be retained after this instruction is submitted. When coded as 1, it means that it is retained and no release is allowed; when coded as 0, it is allowed to be released.
+- The S1K flag is modified to S1R (Reuse Source1): This flag is used to indicate whether SrcTile1 will be retained after this instruction is submitted. When coded as 1, it means that it is retained and no release is allowed; when coded as 0, it is allowed to be released.
+- The DT bit and the DstTile field are jointly encoded to form a 3-bit output register field.
+
+| DT:DstTile | Encoding | Explanation |
+|-------------|---------|----------|
+| 3b000 | Output to T register queue |
+| 3b001 | Output to U register queue |
+| 3b010 | Output to M register queue |
+| 3b011 | Output to N register queue |
+| 3b100 | Output to ACC register queue |
+| 3b101 – 3b110 | Reserved |
+| 3b111 | Invalid output |
+
+### 7. block instruction increases relative index barrier
+
+In the previous design, if data movement instructions such as TCOPYIN and TCOPYOUT read and write the same memory space, but use different global registers to transfer the first memory address, the hardware implementation cannot determine the dependency relationship between the two instructions in advance. At this time, if they are executed out of order, execution errors will occur. For example:
+
+```asm
+ TADD T#1, U#1, ->T<8KB>
+ TCOPYOUT T#1, [a2] ;将tile寄存器内的数据搬移到a2指定的地址内存中
+ TCOPYIN [a1]，->T<4KB> ;将a1指定的地址内存中的数据搬移到tile寄存器中
+ ...
+```
+
+If the same first memory address is stored in a2 and a1, TCOPYIN should wait for TCOPYOUT to complete before executing.
+
+Therefore, in the new version, we add a barrier mechanism to indicate the dependencies between data movement instructions. Specifically, D (dependency) information is added to the instruction.
+
+```asm
+ MCALL label, SrcTile0, SrcTile1, SrcTile2, [BGetList], DepSrc, ->DstTileType, [BSetList], DepDst
+```
+
+Among them:
+
+- DepSrc expresses dependence on pre-order instructions, and can specify dependence on instructions with a pre-order D index distance of 1 to 8. For example, D#1 means that it must wait for the latest instruction written to D to be submitted before execution.
+- DepDst expresses the barrier to subsequent instructions, which is expressed as D in actual assembly.
+
+At the same time, a new instruction B.IOD (Block Input and Output Dependency) needs to be added to encode dependency information.
+
+Assembly format: `B.IOD DepSrc, ->DepDst`
+
+Instruction encoding:
+
+{ width="800" }
+
+The DepSrc and DepDst fields are encoded as shown in the following dependency table:| input/output encoding | DepSrc | DepDst |
+|-------------|---------|----------|
+| 5'b00000 | No dependencies | No output |
+| 5'b00001 | D#1 | D |
+| 5'b00010 | D#2 | reserve |
+| 5'b00011 | D#3 | reserve |
+| 5'b00100 | D#4 | reserve |
+| 5'b00101 | D#5 | reserve |
+| 5'b00110 | D#6 | reserve |
+| 5'b00111 | D#7 | reserve |
+| 5'b01000 | D#8 | reserve |
+| others | reserve | reserve |
+
+template blockTCOPYIN and TCOPYOUT can be expressed as:
+
+```asm
+TCOPYIN , [RegSrc], DepSrc, -> DstTileType, DepDst
+TCOPYOUT , SrcTile, [RegSrc], DepSrc, -> DstDep
+```
+
+Example:
+```asm
+TCOPYOUT t#1, [a2], ->d ; I0
+TCOPYIN [a3]，d#1, ->T ; I1, 等待I0提交后执行
+TCOPYOUT t#1, [a4], ->d ; I2
+TCOPYIN [a5]，d#2, ->T ; I3, 等待I0提交后执行
+TCOPYIN [a1]，d#1, ->T, d ; I4, 等待I2提交后执行
+TCOPYOUT t#1, [a0], d#1 ; I5, 等待I4提交后执行
+```
+
+- Submit means that Tcopyout writes all the data to memory.
+- TCopyout writes to memory in order, and the hardware memory model ensures that TCopyout will not execute out of order. Therefore, TCopyin D#1 relies on the pre-order Copyout, which means that execution starts after all copyouts in the pre-order copyin are written to the memory and submitted (Note: written to SCB).
+
+### 8. Supplementary definition of matrix operation instructions
+
+8.1 Revisions to existing matrix operation instructions
+
+- In order to simplify hardware implementation, in the new version, the results of matrix operation instructions are only allowed to be output to the ACC register, and are not supported to be directly written to Tile registers such as T/U/M/N.
+- The data format in ACC is **fixed to FP32 or INT32**, and the storage fractal format is **Large N Small Z**, **The size of Small Z is 1024Byte**.
+- To ensure design uniformity, matrix operation instructions no longer support storage transposition of the result matrix. Then add an ACCCVT instruction to export data from the ACC register to T/U/M/N, etc., while supporting FixPipe processing.
+
+After the above modifications, the original MAMULB, MAMULBAC, and MAMULB.ACC instructions are retained, and the three instructions MAMULBT, MAMULBACT, and MAMULB.ACCT** that transpose the result matrix are deleted.
+
+| Opcode | Function | TileOP | Description |
+|---------|----------|-----------|----------|
+| **2-CUBE** | 0 | MAMULB | Matrix multiplication: A matrix multiplies B matrix, and the result matrix is written to the ACC register |
+| | 1 | MAMULBAC | Matrix multiplication and addition: A matrix multiplies B matrix, adds C matrix, and the result matrix is written to the ACC register |
+| | 2 | MAMULB.ACC | Matrix multiplication and accumulation: A matrix multiplies B matrix, adds ACC matrix, and the result matrix is written to the ACC register |
+
+1) MAMULB
+
+Assembly format: `MAMULB SrcTile0<.reuse>, SrcTile1<.reuse>, ->ACC`
+This template block is split into the following instructions for encoding:
+```asm
+ BSTART.PAR MAMULB, DataType
+ B.DIM reg, imm, ->M
+ B.DIM reg, imm, ->N
+ B.DIM reg, imm, ->K
+ B.IOT [SrcTile0<.reuse>, SrcTile1<.reuse>], group=0, ->ACC
+```
+
+2) MAMULBAC
+
+Assembly format: `MAMULBAC SrcTile0<.reuse>, SrcTile1<.reuse>, SrcTile2<.reuse>, ->ACC`
+This template block is split into the following instructions for encoding:
+```asm
+ BSTART.PAR MAMULBAC, DataType
+ B.DIM reg, imm, ->M
+ B.DIM reg, imm, ->N
+ B.DIM reg, imm, ->K
+ B.IOT [SrcTile0<.reuse>, SrcTile1<.reuse>], group=0, ->ACC
+ B.IOT [SrcTile2<.reuse>], group=1
+```
+3) MAMULB.ACC
+
+Assembly format: `MAMULB.ACC SrcTile0<.reuse>, SrcTile1<.reuse>, ACC#1, ->ACC`
+This template block is split into the following instructions for encoding:
+```asm
+ BSTART.PAR MAMULB.ACC, DataType
+ B.DIM reg, imm, ->M
+ B.DIM reg, imm, ->N
+ B.DIM reg, imm, ->K
+ B.IOT [SrcTile0<.reuse>, SrcTile1<.reuse>], group=0, ->ACC
+```
+
+8.2 Matrix operations support low-precision data formats
+
+In this version, the instruction set reserves 3 pieces of data block instruction (TileOp) for matrix multiplication or multiplication and accumulation, and supports the following data formats:
+
+Therefore, in the new version, we have added more low-precision data type data support for matrix operation instructions, including INT4 and FP4.
+
+Example: `MAMULB T#1, U#1, ->ACC<64KB>`This matrix multiplication instruction is split into the following instructions for encoding:
+```asm
+ BSTART.PAR MAMULB, S4
+ B.DIM zero, 128, ->M
+ B.DIM zero, 32, ->N
+ B.DIM zero, 64, ->K
+ B.IOTI [T#1, U#1], ->T<64KB>
+```
+The element data type is encoded through the DataType field of the BSTART.PAR instruction, so the new version has adjusted the encoding method of this field. The modified definition is as follows:
+
+{ width="800" }
+
+| Encoding | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 |
+|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
+| DataType | FP64 | FP32 | TF32 | HF32 | FP16 | BF16 | HiF8 | e4m3 | e5m2 | e3m2 | e2m3 | e2m1 | e1m2 | e8m0 | HiF4 | reserve |
+| Coding | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 |
+| DataType | S64 | S32 | S16 | S8 | S4 | reserve | reserve | reserve | U64 | U32 | U16 | U8 | U4 | reserve | reserve | reserve |
+
+8.3 Storage format of CUBE input
+
+In the hardware implementation based on LinxISA, the input of the CUBE operation unit supports the following storage layout. Before the software performs matrix operations, it should ensure that the input must be arranged according to the following layout, otherwise the execution result will be unknown.
+
+- Matrix A: adopts a storage layout of large N and small z.
+- Matrix B: adopts a storage layout of large Z and small n.
+- Matrix C: adopts a storage layout of large Z and small z.
+
+The input diagram is as follows:
+
+{ width="900" }
+
+Among them, both matrix A and matrix C must be stored in a layout of **large N and small z**, and matrix B is stored in a layout of **large Z and small n**.
+
+Assume that S0 and K0 are the number of bytes and the number of elements of the K-dimensional fractal size respectively. Different hardware implementations have different sizes of S0 (S0 uses 32Byte by default, corresponding to a fractal size of 512Byte). Then:
+
+- The fractal matrix size of matrix A is `16 x K0`.
+- The fractal matrix size of matrix B is `K0 x 16`.
+- The fractal matrix size of matrix C is `16 x 16`.
+
+K0 can be calculated by the following formula: `K0 = S0 / sizeof(DataType)`; # DataType represents the element data type
+
+When the input is arranged according to the above storage layout, the default output format is large N and small z. If you want to change the storage layout of the result matrix to another format for subsequent instruction operations, you can use the TCVT instruction to change the storage layout and write the data to the T, U, M, and N registers.
+
+### 9.ACCCVT data movement and accompanying processing support
+
+In order to enhance LinxISA's support for operations such as data conversion and activation/quantization in the post-processing path, version 0.53 adds the ACCCVT instruction (AccTile Convert). This instruction is used to move the result of matrix multiplication calculation from the ACC register to an external Tile register (such as T/U/M/N), and integrates quantization, activation, element-by-element operations and other on-path processing capabilities in the moving process.
+
+9.1 Hardware path and execution mechanism
+
+The original intention of the ACCCVT instruction is to solve the performance bottleneck problem of "the matrix multiplication result still needs to perform a series of format conversion and processing before being written to the Tile Register".In the Linx architecture, the calculation results of the matrix multiplication unit CUBE Core are first written to the internal accumulation register ACC. On the transportation path from ACC to Tile Register, a programmable fixed function processing pipeline (FixPipe) is specially set up, that is, the accompanying processing path.
+
+FixPipe is a micro-pipeline composed of multiple tightly coupled hardware modules connected in series, supporting the following path-dependent computing capabilities:
+
+* Activation function unit (ReLU, ClipReLU)
+* Quantization module (supports INT4/INT8, fixed-point scale/zp)
+* Element-level calculation unit (Add, Mul, etc.)
+* Sparse data filtering and compression unit
+* Output bit mask control unit
+
+These modules are enabled on demand by the `ACCCVT` instruction through the `B.ARG` encoding. During the process of data output from the ACC to the Tile register, the corresponding format/structure/precision conversion is directly completed, with extremely high throughput.
+
+9.2 ACCCVT command
+
+Instruction format:
+```
+ACCCVT.{Layout.{canon, normal}} ACC, ->DstTileType
+```
+
+- Layout: Instructs the storage format conversion operation during data migration. The current version supports NORM, NZ2ND, NZ2DN, etc.
+- DstType: data type representing the element in the Tile after format conversion.
+- DstTileType: used to indicate the destination register, optional T/U/M/N, etc.
+
+The opcode for this instruction is defined as follows:
+
+| Opcode | Function | TileOP | Description |
+|--------|----------|---------|--------|
+| 2-CUBE | 8 | ACCCVT | Move data from ACC register to external T, U, M, N registers. Supports transformation operations during data movement. |
+
+The ACCCVT instruction only supports ACC input and does not support T/U/M/N register input.
+
+```asm
+ BSTART.PAR ACCCVT, DstType # 隐含包含ACC输入
+ B.ARG Layout.{canon, normal}
+ B.DIM reg, imm, ->ROW
+ B.DIM reg, imm, ->COL
+ B.IOT [], group=0, ->{T, U, M, N}
+```
+
+Operation configuration: Set the functional mode of ACCCVT through the B.ARG instruction to avoid using SSR register configuration and improve code clarity and instruction set consistency.
+
+Assembly format: `B.ARG Layout.{canon, normal}`
+
+- canon(canonicalize): Convert the fractal of the matrix input into ACC into the standard left matrix format (the fractal capacity of the standard left matrix is 512 bytes, which is a Z fractal), and merge or split the original fractals of ACC based on different data formats.
+- normal: Do not transform the original fractal of the matrix in the input ACC.
+
+The schematic diagram of canon operation is as follows:
+
+{ width="700" }
+
+Example: `矩阵Q x (矩阵K^T) x 矩阵V `
+```asm
+COPYIN [a0], ->T<4KB> # 矩阵Q（row major）
+COPYIN [a1], ->T<4KB> # 矩阵K (column major)
+COPYIN [a2], ->T<4KB> # 矩阵V (row major)
+MAMULB T#3, T#2, ->ACC<4KB>
+ACCCVT.NORM.canon ACC, ->T<4KB> # 将ACC矩阵标准化，并写入T寄存器。
+MAMULB T#1, T#2, ->ACC<4KB>
+ACCCVT.NZ2ND.normal ACC, ->T<4KB> # 将ACC矩阵转换为ND格式，并写入T寄存器。
+COPYOUT T#1, [a4]
+```
+
+### 10.TCVT conversion operation
+
+10.1 Instruction format:
+```
+TCVT.{Layout}, SrcType, SrcTile., ->DstTileType
+```
+- Layout: Instructs the storage format conversion operation during data migration.
+- SrcType: Indicates data type of the element in the input Tile.
+- DstType: Indicates the data type of the elements in the Tile output after format conversion.
+- SrcTile: Input Tile register, ACC register is not allowed.
+- DstTileType: output Tile register, ACC register is not allowed.
+
+The TCVT instruction is split into the following instructions for encoding:
+```asm
+BSTART.PAR TCVT, DstType
+B.ARG Layout, SrcType
+B.DIM reg, imm, ->ROW
+B.DIM reg, imm, ->COL
+B.IOT [SrcTile.], group=0, ->{T, U, M, N}
+```
+
+10.2 B.ARG modification
+
+In order to adapt to the instruction function of TCVT, the B.ARG instruction adds a SrcType field (encoding method is as follows), which is used to specify the data format of the elements in the input Tile.
+
+{ width="700" }
+
+The SrcType field is encoded as follows:| Encoding | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 |
+|------|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
+| SrcType | FP64 | FP32 | TF32 | HF32 | FP16 | BF16 | HiF8 | e4m3 | e5m2 | e3m2 | e2m3 | e2m1 | e1m2 | e8m0 | HiF4 | reserve |
+| Coding | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 |
+| SrcType | S64 | S32 | S16 | S8 | S4 | reserve | reserve | reserve | U64 | U32 | U16 | U8 | U4 | reserve | reserve | invalid |
+
+### 11.TCOPY modification
+
+After the update, the TCOPY instruction is used to copy data from Tile register to Tile register in unformatted conversion scenarios.
+
+11.1 Assembly format
+
+```asm
+TCOPY SrcTile., ->DstTileType
+```
+
+The template block is split into the following instructions for encoding:
+```asm
+BSTART.PAR TCOPY
+B.IOT [SrcTile.], group=0, -> DstTileType #如果通过立即数指定输出大小，需使用B.IOTI指令
+```
+
+### 12.TCOPYIN modification
+
+In order to align with the definition of the PTO instruction set, the TCOPYIN instruction naming was changed to **TLOAD** in version 0.53.2. The TLOAD instruction is used to copy data from memory to the Tile register. During the copy process, it supports modifying the storage layout of the data.
+
+In the current version, the TLOAD instruction only supports loading of one to two dimensions of data in memory.
+
+12.1 Assembly format
+
+```asm
+TLOAD.Layout , [RegSrc0, RegSrc1], DepSrc, -> DstTileType, DepDst
+```
+The template block is split into the following instructions for encoding:
+```asm
+BSTART.PAR TLOAD, DataType
+B.ARG Layout, PadValue
+B.DIM reg, imm, ->LB0 # ColValid
+B.DIM reg, imm, ->LB1 # RowValid
+B.DIM reg, imm, ->LB2 # Col
+B.IOT group=0, ->DstTileType #如果通过立即数指定输出大小，需使用B.IOTI指令
+B.IOR RegSrc0, RegSrc1
+B.IOD DepSrc, ->DepDst
+```
+
+12.2 B.ARG instruction modification
+
+In order to adapt to the design of TLOAD, the new version of the B.ARG instruction adds the PadValue parameter. This parameter is encoded as follows:
+
+| PadValue encoding | Description |
+|-------------|-------|
+| 0 | Zero |
+| 1 | Max |
+| 2 | Min |
+| 3 | Null |
+| others | reserved |
+
+The modified B.ARG instruction encoding is as follows:
+
+{ width="700" }
+
+### 13.TCOPYOUT modification
+
+In order to align with the definition of the PTO instruction set, the TCOPYOUT instruction naming is changed to **TSTORE** in version 0.53.2.
+
+The TSTORE instruction is used to copy data from the Tile register to the memory. During the copy process, it supports modifying the storage layout of the data to facilitate flexible application in different scenarios.
+
+13.1 Assembly format
+
+```asm
+TSTORE.Layout , SrcTile, [RegSrc0, RegSrc1], DepSrc, -> DepDst
+```
+
+The template block is split into the following instructions for encoding:
+```asm
+BSTART.PAR TSTORE, DataType
+B.ARG Layout
+B.DIM reg, imm, ->LB0 # ColValid
+B.DIM reg, imm, ->LB1 # RowValid
+B.DIM reg, imm, ->LB2 # Col
+B.IOT SrcTile, group=0
+B.IOR RegSrc0, RegSrc1
+B.IOD DepSrc, ->DepDst
+```
\ No newline at end of file
diff --git a/docs/change_log/update_v0.54.md b/docs/change_log/update_v0.54.md
new file mode 100644
index 00000000..b4c2d9aa
--- /dev/null
+++ b/docs/change_log/update_v0.54.md
@@ -0,0 +1,555 @@
+# 0.54 version update
+
+Update date: October 24, 2025
+
+For the path to the web version of the instruction encoding design document, please see [LinxISA Encoding-0.54](https://dbox.huawei.com/detaildocs?oid=VR:wt.doc.WTDocument:101014747097)
+
+## 1. Update background
+
+This version 0.54 is mainly used to improve the existing Tile block execution model, update the naming of existing instructions, add specific constraints in details and solve problems in some scenarios.
+
+1. Strengthen the definition and constraints of block type by refining the Tile block classification
+2. By adding spill to the S-tile register, the problem of insufficient number of vector registers in some scenarios is solved.
+3. Reduce the number of block-private registers by increasing the block-private register number option to solve the resource waste problem caused by too many vector registers in some scenarios.
+4. By adding instructions for dual-output Tile registers, the demand for the number of input/outputTiles when integrating Tileop in high-performance scenarios is met.
+5. By adding empty Tile register definition implementation, the problem of different index distances of Tile registers in different branches in intensive control flow scenarios is solved.
+6. Simplify the implementation of hardware identification of continuous Load/Store by enhancing the definition of address continuous Load/Store.
+7. Added a new dimensionality reduction mode switch, and the software can choose whether to optimize the performance of specific scenarios through dimensionality reduction mode.
+8. By adjusting the naming of vector instructions, it is easier for software or programmers to distinguish vector instructions.
+9. By adding the Load/Store Local or Global flag, it is easier for the hardware to identify memory or Tile register access in advance.
+10. By adding the v.psel instruction, the controllability of invalid Lane results is enhanced and the optimization of unilateral branch data merging operations is realized.
+11. Solve the problems found in corner scenes by adding instruction constraints.
+
+## 2. Summary of updated content
+
+LinxISA version 0.54 has made the following design adjustments:| Category | Updates | Description |
+|-----|--------|---------|
+| 1. Tile block design changes | 1.1 Update Tile block classification and definition | Used to refine Tile block classification and strengthen block type definition. |
+| | 1.2 Added the option of the number of block-private registers | Reduce the waste of vector register resources in some scenarios. |
+| | 1.3 Add private Tile register definition | Tile block can apply for a private Tile Register for register spill within the block. |
+| | 1.4 New empty Tile register definition | Used to align the index distance when the compiler allocates registers. |
+| | 1.5 New Tile register dual output definition (added TO1) | Meet the demand for the number of input/outputTiles when integrating Tileop in high-performance scenarios. |
+| | 1.6 The B.ATTR instruction flag bit is adjusted and merged with the B.ARG instruction | Merge instructions of the same type to streamline the coding space. (Note: Delete the B.ARG instruction) |
+| | 1.7 Added dimensionality reduction (DR) mode | to meet the needs of different scenarios. |
+| 2. Instruction design expansion | 2.1 vector instruction naming adjustment | Used to distinguish vector operations and scalar operations |
+| | 2.2 Strengthen the definition of continuous address load/store | Constrain the base address and offset register of continuous load/store to be the scalar register |
+| | 2.3 Load/Store Bridge instruction adds address continuity flag | Used to provide address continuity flag while using bridged memory access instruction |
+| | 2.4 Load/Store instructions add identification to distinguish access to local/global | The hardware identifies memory or Tile register access in advance, without waiting for the address to be calculated before making a judgment, thereby improving performance. |
+| | 2.5 Added V.PSEL instruction | Used to optimize data merging in unilateral branch scenarios. |
+| | 2.6 Add instruction constraints | setret must be placed after BSTART to ensure the performance of the hardware predictor |
+| 3. System block definition | 3.1 System block instruction only supports FALL type | Delete BSTART codes corresponding to other jump methods |
+
+## 3. Update details
+
+### 1. Tile block design extension
+
+Tile blocks are a type of block instruction that can access Tile registers. This type of block instruction was introduced to achieve large-scale tensor operations, and by decomposing large operators into Tile-level operations, combined with hardware vectorization/hardening processing and other execution capabilities, it improves the performance of intensive computing tasks such as matrix operations or vector operations.
+
+**1.1 Tile block classification**
+
+In the new version, Tile blocks are divided into the following specific block type according to dimensions such as whether they can access memory, whether there is body and execution mode, so as to provide targeted definitions or constraints for each type of block type.
+
+Tile blocks are classified as follows:| Category/dimension | Whether memory can be accessed | Whether there is body | Whether groups are parallel (whether internal calculations can be parallelized) | Remarks |
+|----------|------------|------------|-------------------------------------|---------|
+| **Memory Parallel Block (MPAR)** | Can | Yes | Yes | Corresponds to the previous version of MCALL, and Parallel mode |
+| **Memory access serial block (MSEQ)** | Can | Yes | No | Corresponds to the previous version of MCALL, and Vector mode |
+| **vector Parallel Block (VPAR)** | No | Yes | Yes | Corresponds to the previous version of VCALL, and Parallel mode |
+| **vector serial block (VSEQ)** | No | Yes | No | Corresponds to the previous version of VCALL, and Vector mode |
+| **Data Movement Block (TMA)** | Yes | No | Yes | Corresponds to TLoad/TStore/TCopy |
+| **Matrix Data Block (CUBE)** | No | No | Yes | Corresponds to matrix operations and ACCCVT, etc. |
+
+Different types of Tile blocks can have different block parameter instructions, which are used to configure the execution parameters of this block. See the following table for details:
+
+| Block parameters | B.ATTR | B.DIM | B.IOT/B.IOTI | B.IOR | B.IOD | B.TEXT | B.HINT |
+|-------|--------|-------|-------|------|-------|--------|----------|
+| MPAR | Support | Support | Support | Support | Support | Support | Not support |
+| MSEQ | Support | Support | Support | Support | Support | Support | Not support |
+| VPAR | Supported | Supported | Supported | Supported | Supported | Supported | Not Supported |
+| VSEQ | Support | Support | Support | Support | Support | Support | Not support |
+| TMA | Support | Support | Support | Support | Support | Not support | Not support |
+| CUBE | Support | Support | Support | Not support | Not support | Not support | Not support |
+
+BSTART assembly format:
+
+```asm
+BSTART.MPAR
+BSTART.MSEQ
+BSTART.VPAR
+BSTART.VSEQ
+BSTART.TMA TileOp, DataType
+BSTART.CUBE TileOP, DataType
+```
+
+In terms of encoding, the BlockType field of the Tile block is uniformly encoded as "5b00011", and the BSTART encoding of different types of Tile blocks is as follows:
+
+
+
+For Tile blocks with body, a 16bit BSTART version is also provided.
+
+
+
+**1.2 Added option for the number of vector registers used**
+
+The current version has body Tile blocks (including MPAR/MSEQ/VPAR/VSEQ). We provide 4 sets of vector registers (vt/vu/vm/vn) within the block, each set of 4. These vector registers will occupy a large amount of physical register resources. And in some scenarios, the Tile block only uses one or two sets of vector registers, causing register resource congestion and affecting the execution efficiency of the Tile block.
+
+Therefore, in the new version, we provide an option for the number of vector registers used for these four Tile blocks. The software can use this option to indicate the number of vector registers used by this block, so that the hardware can reasonably allocate register resources.
+
+This information is expressed on the BSTART instruction of the Tile block, and the assembly format is as follows:
+```asm
+BSTART.MPAR
+BSTART.MSEQ
+BSTART.VPAR
+BSTART.VSEQ
+BSTART.MPAR
+BSTART.MSEQ
+BSTART.VPAR
+BSTART.VSEQ
+```Among them, parameters such as "VS" are used to express the number of vector registers used in the block (VS is the abbreviation of Vector Size).
+
+Encoding method:
+
+
+
+This parameter is encoded in the Mode field of the BSTART instruction, and the encoding method is as follows:
+
+| Mode encoding | Meaning | Description |
+|----------|-------|------|
+| 0 | **VS8** | 2 sets of vector registers are required in the block, 4 in each set (8 in total) |
+| 1 | **VS16** | 4 groups of vector registers are required in the block, 4 in each group (16 in total) |
+| 2 | VS32 (not supported by the current version) | 4 groups of vector registers are required in the block, 8 in each group (32 in total) |
+| 3 | VS64 (not supported by the current version) | 4 groups of vector registers are required in the block, 16 in each group (64 in total) |
+
+Things to note:
+
+- The number of vector registers requested by the software must be greater than or equal to the actual number used, otherwise the hardware will report the illegal parameter exception.
+- The 16bit version of C.BSTART.MPAR, etc. does not have a Mode field and uses the full vector register by default.
+
+**1.3 Add private Tile register**
+
+Since the vector parallel block and vector serial block do not allow direct access to the memory space, there is no concept of a thread stack. Therefore, functions that rely on stack space such as function calls and register spills cannot be implemented, which seriously limits the computing power and ease of use of block instruction. To address this problem, we propose the following design extensions:
+
+**1.3.1 Add S register**
+
+Add a type of Tile Register to the first-layer architecture, named S (full name: Stack Tile Register). This register is specially used for Tileblock instruction function call parameter storage or stack space for register spill.
+
+**1.3.2 How to use S register**
+
+- Like other types of Tile registers, Tileblock instruction applies to use the S register through the B.IOT/B.IOTI instruction.
+- The difference is that the S register is private to the block instruction that applies for it. The S register is only visible to this block and can be read and written within the block. And this register is released with the submission of block instruction.
+- The B.IOT instruction applies for the stack space size used within a Group, and the total space size of the S register requires hardware calculation.
+- Note: The total space size of the S register is obtained by multiplying the S register Group capacity by the number of Groups, and **the space size cannot exceed 512KB**.
+
+Example:
+```asm
+BSTART.VPAR , T#1, U#1, ->T<16KB>, S<8KB>
+// 展开形式
+BSTART.VPAR FP16
+B.DIM zero, 64, ->Row
+B.DIM zero, 64, ->Col
+B.IOTI T#1, U#1, group=0, ->S<8KB> # 每个group申请的空间8KB
+B.IOTI group=1, ->T<16KB>
+BSTART.VPAR , T#1, U#1, ->T<16KB>, S<8KB>
+// 展开形式
+BSTART.VPAR FP16
+B.DIM zero, 64, ->Row
+B.DIM zero, 64, ->Col
+B.IOTI T#1, U#1, group=0, ->S<8KB> # 每个group申请的空间8KB
+B.IOTI group=1, ->T<16KB>
+```
+
+**1.3.3 Formal parameter register**
+
+A Tile type formal parameter register TS is added to the block, which is mapped to the S register applied for by header. TS points to the corresponding stack space in the current group.
+
+Register spill example:
+```
+// Spill
+l.sd vt#1.ud, [TS, lc0<<3]
+// Reload
+l.ld [TS, LC0<<3], ->vt.d
+// Spill
+l.sd vt#1.ud, [TS, lc0<<3]
+// Reload
+l.ld [TS, LC0<<3], ->vt.d
+```
+Note: If an uninitialized TS is read within the block, a random value will be returned.
+
+**1.4 Added empty Tile register definition**
+
+Tileblock instruction allows output to empty Tile registers, which is used to align the index distance when the compiler allocates registers.
+
+**1.4.1 Scenario Example**
+
+Under the relative index register design, after the life cycle of a variable spans the control flow, since different control flow paths may write different times to the hand to which the variable register belongs, there may be multiple index distances when the control flow convergence point uses the variable.
+```
+if.entry:
+ BSTART.VPAR -> T<1KB>
+ BSTART.COND if.then, if.end
+if.then:
+ BSTART.MPAR -> T<2KB>
+ BSTART.MPAR -> T<2KB>
+ BSTART DIRECT if.end
+if.end:
+ TSTORE T#?, [a0] # 将VCALL结果写回内存，此处存在2种索引距离
+if.entry:
+ BSTART.VPAR -> T<1KB>
+ BSTART.COND if.then, if.end
+if.then:
+ BSTART.MPAR -> T<2KB>
+ BSTART.MPAR -> T<2KB>
+ BSTART DIRECT if.end
+if.end:
+ TSTORE T#?, [a0] # 将VCALL结果写回内存，此处存在2种索引距离
+```
+
+In order to solve the above problem, it is necessary to insert some additional instructions to output to the empty Tile in the if.entry code segment to adjust the index distance so that the two index distances at if.end are equal.
+```asm
+if.entry:
+ BSTART.VPAR -> T<1KB>
+ BSTART.VPAR -> T # 输出至空Tile寄存器
+ BSTART.VPAR -> T # 输出至空Tile寄存器
+ BSTART.COND if.then, if.end
+if.then:
+ BSTART.MPAR -> T<2KB>
+ BSTART.MPAR -> T<2KB>
+ BSTART DIRECT if.end
+if.end:
+ TSTORE T#3, [a0]
+if.entry:
+ BSTART.VPAR -> T<1KB>
+ BSTART.VPAR -> T # 输出至空Tile寄存器
+ BSTART.VPAR -> T # 输出至空Tile寄存器
+ BSTART.COND if.then, if.end
+if.then:
+ BSTART.MPAR -> T<2KB>
+ BSTART.MPAR -> T<2KB>
+ BSTART DIRECT if.end
+if.end:
+ TSTORE T#3, [a0]
+```
+
+**1.4.2 Empty Tile register allocation method**If Tileblock instruction needs to apply for an empty Tile register for placeholder, it must use the B.IOT instruction to indicate that the output Tile register space is 0. Information with space 0 is expressed through the zero register.
+
+Example:
+```asm
+BSTART.VPAR ->T
+BSTART.VPAR ->T
+```
+This instruction expands into the following instruction encoding:
+```asm
+BSTART.VPAR VCALL
+B.IOT group=0, ->T # 通过zero寄存器表达申请空Tile reg
+BSTART.VPAR VCALL
+B.IOT group=0, ->T # 通过zero寄存器表达申请空Tile reg
+```
+
+Encoding method: The RegSrc field is encoded as a zero register.
+
+
+
+**1.5 B.ATTR and B.ARG instructions are merged**
+
+In order to simplify the instruction coding, the B.ATTR instruction is modified as follows in the new version:
+
+- Delete the hyper flag bit. The current version only supports intra-block jumps in Tile blocks, and there is no need to specify the hyper attribute.
+- Delete the relay flag bit. By default, all block instruction do not relay.
+- Delete the scall flag bit, which has the same meaning as TRAP.
+- TRAP marker bit encoding position adjustment.
+- Incorporate the parameters of the B.ARG instruction.
+- Added DR flag (dimensionality reduction mode, see section 1.7 for details)
+
+After the relevant parameters of the B.ARG instruction are merged into B.ATTR, delete the B.ARG instruction.
+
+Assembly format:
+```asm
+B.ATTR {trap, atomic, , far, Layout.{canon, normal}, SrcType, PadValue, DR}
+B.ATTR {trap, atomic, , far, Layout.{canon, normal}, SrcType, PadValue, DR}
+```
+
+encoding format
+
+
+
+Among them, the encoding method of the newly added dimensionality reduction mode flag DR is:
+
+| DR | Meaning |
+|----|-------|
+| 0 | Multidimensional mode |
+| 1 | Dimensionality reduction mode |
+
+**1.6 New dimensionality reduction (DR) mode**
+
+In the new version, we provide two ways to expand the three-layer loop of Tileblock instruction.
+
+- Dimension Reduction mode: The three-layer iterations of body are all flattened and unfolded. Every 64 (corresponding to the laneNum of the next Group in the current design) iterations are allocated to a Group for execution until the end of the iteration.
+- Multi-Dimension mode (Multi Dimension): Groups are divided into groups based on the number of innermost iterations of body. The two innermost iterations are not allowed to be assigned to the same Group.
+
+The loop expansion of body is implemented as:
+```asm
+parallel_for（lc2 = 0; lc2 < lb2; lc2++）
+ parallel_for（lc1 = 0; lc1 < lb1; lc1++）
+ parallel_for（lc0 = 0; lc0 < lb0; lc0++）
+ kernel(lane_id);
+ end for
+ end for
+end for
+parallel_for（lc2 = 0; lc2 < lb2; lc2++）
+ parallel_for（lc1 = 0; lc1 < lb1; lc1++）
+ parallel_for（lc0 = 0; lc0 < lb0; lc0++）
+ kernel(lane_id);
+ end for
+ end for
+end for
+```
+
+The schematic diagram of the dimensionality reduction mode is as follows:
+
+Assuming that the number of innermost loops is 32, the hardware will schedule the two inner loop iterations to be executed in the same group.
+
+
+
+The schematic diagram of the multidimensional mode is as follows:
+
+Scenario 1: The upper limit value of the innermost loop (LB0) is less than or equal to 64. The diagram is as follows:
+
+
+
+Scenario 2: The upper limit value of the innermost loop (LB0) is greater than 64. The diagram is as follows:
+
+
+
+Under the multidimensional model, it must be ensured:
+
+- The value of LC0 within a Group must be continuous;
+- The value of LC1 within a Group must remain unchanged;
+- The value of LC2 within a Group must remain unchanged;
+
+Under this model, the calculation formula for the number of Groups split from a Tile block is:
+```asm
+if (LB0 % 64 > 0)
+ innerNum = LB0 / 64 +1;
+else
+ innerNum = LB0 / 64;
+GroupNumber = LB2 * LB1 * innerNum;
+if (LB0 % 64 > 0)
+ innerNum = LB0 / 64 +1;
+else
+ innerNum = LB0 / 64;
+GroupNumber = LB2 * LB1 * innerNum;
+```
+Multidimensional mode is more suitable for usage scenarios where addresses are continuously loaded/stored, ensuring that lc0 is continuously incremented within a Group.
+
+### 2. Instruction design extension
+
+**2.1 vector instruction assembly renaming**
+
+In the new version, in order to easily distinguish scalar and vector operations, the vector instruction naming in the Tile block is uniformly modified to use "V." as the prefix, and the scalar instruction still uses "L." as the prefix.
+
+The command list is as follows:| Original naming | vector command naming | Remarks | Original naming | vector command naming | Remarks |
+|--------|----------------|------|--------|-------------|---------|
+| L.ADD,L.SUB,L.AND,L.OR,L.XOR
L.SRL,L.SRA,L.SLL
L.ADDI,L.SUBI,L.ANDI,L.ORI
L.XORI,L.SRLI,L.SRAI,L.SLLI | V.ADD,V.SUB,V.AND,V.OR
V.XOR,V.SRL,V.SRA,V.SLL
V.ADDI,V.SUBI,V.ANDI,V.ORI,
V.XORI,V.SRLI,V.SRAI,V.SLLI | vector: vt/vu/vm/vn
scalar: t/u, p | L.LW.ADD,L.LW.AND,L.LW.OR
L.LW.XOR,L.LW.MAX,L.LW.MIN
L.LD.ADD,L.LD.AND,L.LD.OR
L.LD.XOR,L.LD.MAX,L.LD.MIN | V.LW.ADD,V.LW.AND,V.LW.OR
V.LW.XOR,V.LW.MAX,V.LW.MIN
V.LD.ADD,V.LD.AND,V.LD.OR
V.LD.XOR,V.LD.MAX,V.LD.MIN | vector: vt/vu/vm/vn
scalar: t/u, p |
+| L.CMP.EQ,L.CMP.NE,L.CMP.AND
L.CMP.ORL.CMP.LT,L.CMP.GE
L.CMP.LTU,L.CMP.GEU,L.CMP .EQI
L.CMP.NEI,L.CMP.ANDI,L.CMP.ORI
L.CMP.LTI,L.CMP.GEI,L.CMP.LTUI
L.CMP.GEUI | V.CMP.EQ,V.CMP.NE,V.CMP.AND
V.CMP.ORV.CMP.LT,V.CMP.GE
V.CMP.LTU,V.CMP.GEU,V.CMP .EQI
V.CMP.NEI,V.CMP.ANDI,V.CMP.ORI
V.CMP.LTI,V.CMP.GEI,V.CMP.LTUI
V.CMP.GEUI | vector: vt/vu/vm/vn,p
scalar: t/u
When outputting P, it is vector | L.SW.ADD,L.SW.AND,L.SW.OR
L.SW.XOR,L.SW.MAX,L.SW.MIN
L.SD.ADD,L.SD.AND,L.SD.OR
L.SD.XOR,L.SD.MAX,L.SD.MIN | V.SW.ADD,V.SW.AND,V.SW.OR
V.SW.XOR,V.SW.MAXV.SW.MIN
V.SD.ADD,V.SD.AND,V.SD.OR
V.SD.XOR,V.SD.MAX,V.SD.MIN | Any input to the vector register is vector || L.MUL, L.MADD, L.DIV, L.REM | V.MUL, V.MADD, V.DIV, V.REM | vector: vt/vu/vm/vn
scalar: t/u, p | L.FADD,L.FSUB,L.FMUL,L.FDIV
L.FMADD,L.FMSUB,L.FNMADD
L.FNMSUB | vt/vu/vm/vn
scalar: t/u, p |
+| L.BXS,L.BXU,L.BIC,L.BIS,L.CTZ,L.CLS
L.BCNT,L.REV | V.BXS,V.BXU,V.BIC,V.BIS,V.CTZ,V.CLS
V.BCNT,V.REV | vector: vt/vu/vm/vn
scalar: t/u, p | L.FEQ,L.FNE,L.FLT,L.FGE,L.FEQU
L.FNEUL.FLTU,L.FGEU
L.MAX,L.MIN,L.FMAX,L.FMIN | V.FEQ,V.FNE,V.FLT,V.FGE,V.FEQU
V.FNEUV.FLTU,V.FGEU
V.MAX,V.MIN,V.FMAX,V.FMIN | vector: vt/vu/vm/vn
scalar: t/u, p |
+| L.CSEL | V.CSEL | vector: vt/vu/vm/vn
scalar: t/u, p | L.FCVT,L.FCVTI,L.ICVT,L.ICVTF | V.FCVT,V.FCVTI,V.ICVT,V.ICVTF | vector: vt/vu/vm/vn
scalar: t/u, p |
+| L.LB,L.LH,L.LW,L.LD,L.LBU,L.LHU
L.LWU,L.LBI,L.LHI,L.LWI,L.LDI,L.LBUI
L.LHUI,L.LWUIL.LHI.U,L.LWI.U,L.LDI.U
L.LHUI.U,L.LWUI.U | V.LB,V.LH,V.LW,V.LD,V.LBU,V.LHU
V.LWU,V.LBI,V.LHI,V.LWI,V.LDI,V.LBUI
V.LHUI,V.LWUIV.LHI.U,V.LWI.U,V.LDI.U
V.LHUI.U,V.LWUI.U | vector: vt/vu/vm/vn
scalar: t/u, p | L.FABS,L.FSQRT,L.FRECIP,L.FEXP
L.FLN,L.FCLASS | vector: vt/vu/vm/vn
scalar: t/u, p || L.SB,L.SH,L.SW,L.SD,L.SH.U,L.SW.U
L.SD.U,L.SBI,L.SHI,L.SWI,L.SDI,L.SHI.U
L.SWI.U,L.SDI.U | V.SB,V.SH,V.SW,V.SD,V.SH.U,V.SW.U
V.SD.U,V.SBI,V.SHI,V.SWI,V.SDI,V.SHI.U
V.SWI.U,V.SDI.U | Any input to the vector register is vector | L.RDADD,L.RDAND,L.RDOR
L.RDXOR,L.RDFADD,L.RDMAX
L.RDMIN,L.RDFMAX,L.RDFMIN | V.RDADD,V.RDAND,V.RDOR
V.RDXOR,V.RDFADD,V.RDMAX
V.RDMIN,V.RDFMAX,V.RDFMIN | Only vector version |
+| L.LB.BRG,L.LH.BRG,L.LW.BRG,L.LD.BRG,
L.LBU.BRG,L.LHU.BRG,L.LWU.BRG
L.LBI.BRG,L.LHI.BRG,L.LWI.BRG
L. LDI.BRG,L.LBUI.BRG,L.LHUI.BRG
L.LWUI.BRG,L.LHI.U.BRG,L.LWI.U.BRG
L.LDI.U.BRG,L.LHUI.U.BRG,L.LWUI.U.BRG | V.LB.BRG,V.LH.BRG,V.LW.BRG,V.LD.BRG,
V.LBU.BRG,V.LHU.BRG,V.LWU.BRG
V.LBI.BRG,V.LHI.BRG,V.LWI.BRG
V. LDI.BRG,V.LBUI.BRG,V.LHUI.BRG
V.LWUI.BRG,V.LHI.U.BRG,V.LWI.U.BRG
V.LDI.U.BRG,V.LHUI.U.BRG,V.LWUI.U.BRG | Only version vector | L.SHFL.UP,L.SHFL.DOWN
L.SHFL.BFLY,L.SHFL.IDX
L.SHFLI.UP,L.SHFLI.DOWN
L.SHFLI.BFLY,L.SHFLI.IDX | V.SHFL.UP,V.SHFL.DOWN
V.SHFL.BFLY,V.SHFL.IDX
V.SHFLI.UP,V.SHFLI.DOWN
V.SHFLI.BFLY,V.SHFLI.IDX | vector version only |
+| L.SB.BRG,L.SH.BRG,L.SW.BRG,L.SD.BRG
L.SH.U.BRG,L.SW.U.BRG,L.SD.U,L.SBI.BRG
L.SHI.BRG,L.SWI.BRG,L.SDI.BRG
L.SHI.U.BRG,L.SWI.U,L.SDI.U.BRG | V.SB.BRG,V.SH.BRG,V.SW.BRG,V.SD.BRG
V.SH.U.BRG,V.SW.U.BRG,V.SD.U,V.SBI.BRG
V.SHI.BRG,V.SWI.BRG,V.SDI.BRG
V.SHI.U.BRG,V.SWI.U,V.SDI.U.BRG | Only vector version | L.QPUSH,L.QPOP | V.QPUSH,V.QPOP | vector: vt/vu/vm/vn
scalar: t/u, p |
+
+Example:
+```asm
+# ZXTERMZH45QXZ指令
+l.add t#1, u#1, ->t
+l.add t#1, p, ->p
+l.ld [TS, offset], ->u
+l.ld [TS, offset], ->p
+l.sd t#1, [TO, offset]
+l.sd p#1, [TO, offset]
+# ZXTERMZH43QXZ指令：
+v.add vt#1.uh, vu#1.uh, ->vt.h
+v.add t#1, vu#1.uh, ->vt.h
+v.sw vt#1.uw, [TO, lc0<<2]
+v.ld [TA, lc0<<3], ->vt.d
+```
+
+**2.2 Strengthen the definition of continuous Load/Store**In version 0.52.1, in order to simplify the hardware address calculation process and perform address access efficiently. The instruction set provides a Load/Store instruction with continuous addresses. The address of this type of instruction is calculated from three parts: "base address register", "LC0 register offset" and "offset register or immediate offset".
+
+We expect that the "base address register" and "offset register or immediate offset" are invariants, and LC0 is a variable that increases sequentially following lane expansion. In this way, the continuity of memory access addresses within the group is achieved.
+
+The assembly format of some of the instructions:
+```asm
+v.lw [srcL., lc0<<2, srcR.], ->dst.w
+v.lwi [srcL., lc0<<2, imm], ->dst.w
+v.sw srcD.uw, [srcL., lc0<<2, srcR.]
+v.swi srcD.uw, [srcL., lc0<<2, imm]
+v.lw [srcL., lc0<<2, srcR.], ->dst.w
+v.lwi [srcL., lc0<<2, imm], ->dst.w
+v.sw srcD.uw, [srcL., lc0<<2, srcR.]
+v.swi srcD.uw, [srcL., lc0<<2, imm]
+```
+
+**2.2.1 Instruction constraints**
+
+In order to ensure the continuity of memory access addresses within a group, on the one hand, the architecture design is required to be divided into groups according to the definition in Section 1.3 above. On the other hand, it is also necessary to add constraints on the use of "base address register SrcL" and "offset register SrcR" for such memory access instructions:
+
+- The base address register of memory access instructions with consecutive addresses must be the scalar register or the Tile register, otherwise an illegal instruction exception will be reported.
+- The offset register of memory access instructions with consecutive addresses must be the scalar register, otherwise an illegal instruction exception will be reported.
+- If the value of the offset register is calculated from LC1/LC2, then this type of instruction should be ensured to be used in multi-dimensional mode to ensure that LC1 and LC2 remain unchanged within a Group.
+
+Example:
+```asm
+v.lw [ri0, lc0<<2, t#1], ->vt.w
+v.lwi [TA, lc0<<2, 8], ->vu.w
+v.sw vt#1.uw, [TO, lc0<<2, ri1]
+v.swi vu#1.uw, [ri2, lc0<<2, 8]
+v.lw [ri0, lc0<<2, t#1], ->vt.w
+v.lwi [TA, lc0<<2, 8], ->vu.w
+v.sw vt#1.uw, [TO, lc0<<2, ri1]
+v.swi vu#1.uw, [ri2, lc0<<2, 8]
+```
+
+The diagram is as follows:
+
+
+
+**2.2.2 Instruction encoding**
+
+This version has no changes to the encoding of Load/Store instructions with consecutive addresses. The 12th bit of the memory access instruction is the flag bit for continuous address. When the code is 1, the software should ensure that the addresses in each group must be continuous, otherwise the addresses are allowed to be discontinuous.
+
+
+
+**2.3 Load/Store bridge command adds a mark with consecutive addresses**
+
+In order to meet the needs of software using Load/Store bridge operations at the same time and providing Load/Store with consecutive addresses, the new version adds a continuous address mark to the Load/Store bridge instruction. Reduce the overhead of hardware address calculations with this flag.
+
+**2.3.1 Assembly format**
+
+Like ordinary Load/Store instructions, Load/Store bridge instructions with consecutive addresses pass a fixed LC0 input as part of the addressing offset in assembly.|Instructions | Assembly format |
+|------|--------|
+| V.LB.BRG | `v.lb.brg<.local> [SrcL<.ud>, , SrcR.<<], ->Dst.` |
+| V.LH.BRG | `v.lh.brg<.local> [SrcL<.ud>, , SrcR.<<], ->Dst.` |
+| V.LW.BRG | `v.lw.brg<.local> [SrcL<.ud>, , SrcR.<<], ->Dst.` |
+| V.LD.BRG | `v.ld.brg<.local> [SrcL<.ud>, , SrcR.<<], ->Dst.` |
+| V.LBU.BRG | `v.lbu.brg<.local> [SrcL<.ud>, , SrcR.<<], ->Dst.` |
+| V.LHU.BRG | `v.lhu.brg<.local> [SrcL<.ud>, , SrcR.<<], ->Dst.` |
+| V.LWU.BRG | `v.lwu.brg<.local> [SrcL<.ud>, , SrcR.<<], ->Dst.` |
+| V.LBI.BRG | `v.lbi.brg<.local> [SrcL<.ud>, , simm], ->Dst.` |
+| V.LHI.BRG | `v.lhi.brg<.local> [SrcL<.ud>, , simm], ->Dst.` |
+| V.LWI.BRG | `v.lwi.brg<.local> [SrcL<.ud>, , simm], ->Dst.` |
+| V.LDI.BRG | `v.ldi.brg<.local> [SrcL<.ud>, , simm], ->Dst.` |
+| V.LBUI.BRG | `v.lbui.brg<.local> [SrcL<.ud>, , simm], ->Dst.` |
+| V.LHUI.BRG | `v.lhui.brg<.local> [SrcL<.ud>, , simm], ->Dst.` |
+| V.LWUI.BRG | `v.lwui.brg<.local> [SrcL<.ud>, , simm], ->Dst.` |
+| V.LHI.UBRG | `v.lhi.ubrg<.local> [SrcL<.ud>, , simm], ->Dst.` |
+| V.LWI.UBRG | `v.lwi.ubrg<.local> [SrcL<.ud>, , simm], ->Dst.` |
+| V.LDI.UBRG | `v.ldi.ubrg<.local> [SrcL<.ud>, , simm], ->Dst.` |
+| V.LHUI.UBRG | `v.lhui.ubrg<.local> [SrcL<.ud>, , simm], ->Dst.` |
+| V.LWUI.UBRG | `v.lwui.ubrg<.local> [SrcL<.ud>, , simm], ->Dst.` |
+| V.SB.BRG | `v.sb.brg<.local> SrcD., [SrcL<.ud>, , SrcR.]` |
+| V.SH.BRG | `v.sh.brg<.local> SrcD., [SrcL<.ud>, , SrcR.<<1]` |
+| V.SW.BRG | `v.sw.brg<.local> SrcD., [SrcL<.ud>, , SrcR.<<2]` |
+| V.SD.BRG | `v.sd.brg<.local> SrcD., [SrcL<.ud>, , SrcR.<<3]` |
+| V.SH.UBRG | `v.sh.ubrg<.local> SrcD., [SrcL<.ud>, , SrcR.]` |
+| V.SW.UBRG | `v.sw.ubrg<.local> SrcD., [SrcL<.ud>, , SrcR.]` |
+| V.SD.UBRG | `v.sd.ubrg<.local> SrcD., [SrcL<.ud>, , SrcR.]` |
+| V.SBI.BRG | `v.sbi.brg<.local> SrcL., [SrcR<.ud>, , simm]` |
+| V.SHI.BRG | `v.shi.brg<.local> SrcL., [SrcR<.ud>, , simm]` |
+| V.SWI.BRG | `v.swi.brg<.local> SrcL., [SrcR<.ud>, , simm]` |
+| V.SDI.BRG | `v.sdi.brg<.local> SrcL., [SrcR<.ud>, , simm]` |
+| V.SHI.UBRG | `v.shi.ubrg<.local> SrcL., [SrcR<.ud>, , simm]` |
+| V.SWI.UBRG | `v.swi.ubrg<.local> SrcL., [SrcR<.ud>, , simm]` |
+| V.SDI.UBRG | `v.sdi.ubrg<.local> SrcL., [SrcR<.ud>, , simm]` |
+
+When using Load/Store bridge instructions with consecutive addresses, you must also ensure that the requirements for continuous Load/Store instructions in 2.2 are met.
+
+**2.3.2 Instruction encoding**
+
+Like ordinary Load/Store instructions, the Load/Store bridge instruction uses the "C" flag bit to indicate whether the addresses are continuous.
+
+
+
+Please see the ISA Encoding Excel document for full instruction encoding.
+
+**2.4 Distinguish between Local/Global access**
+
+In order for the hardware to identify Tile Reg or Global Memory access in advance, there is no need to wait for the address to be calculated before making a judgment, thereby improving performance. In version 0.54, the Load/Store command adds a logo that expresses the Tile Reg access.
+
+The specific modifications are as follows:
+
+- The address is the Load/Store instruction of Tile Register, and the ".local" suffix is added to the assembly.
+- The address is the Load/Store instruction of Global Memory, and no additional suffix is added in the assembly. (Default access to shared memory)
+
+Assembly syntax:
+```asm
+v.loadop<.local> [baseReg, offset], ->dstReg
+v.storeop<.local> dataReg, [baseReg, offset]
+v.loadop<.local> [baseReg, offset], ->dstReg
+v.storeop<.local> dataReg, [baseReg, offset]
+```
+Among them, ".local" is an optional suffix, and the software chooses whether to add the suffix based on whether the access address is a Tile Register.
+
+Note: Software/programmers should ensure that the addresses accessed by instructions are classified correctly. If the address is wrong, the hardware reports exception.In the instruction encoding, a 1bit **L (local)** flag is added. The code is 1 when accessing the Tile Register, otherwise the code is 0. The encoding is as follows:
+
+
+
+
+
+Only part of the load/store instruction encoding is pasted here. Please see the ISA Encoding Excel document for the full content.
+
+**2.5 Add V.PSEL instruction**
+
+In vector calculations, some lanes may be marked as invalid due to mask control, boundary crossing, or branch masking. How to handle the output values of these invalid channels is of great significance for controlling numerical correctness, storage consistency, and subsequent calculation behavior.
+
+In order to enhance the ability to control calculation results, a new Predication Mode (pmode) definition is added to Tileblock instruction, which is used to specify how to handle calculation results of invalid channels. Two pmode mode definitions:
+
+- merging mode: The result of the invalid channel will remain as the original value of the input register, which is suitable for situations where you want to retain the original data without causing mutations.
+- zeroing mode: The result of an invalid channel is forced to be written as 0, suitable for scenarios where old values need to be cleared or output initialized.
+
+This mechanism allows developers to clearly control how instructions handle invalid channels based on specific application requirements, avoiding reliance on default behaviors and improving code controllability and portability.
+
+Under the current definition, the instruction calculation result in the invalid lane of the Tile block defaults to the clear mode, that is, the destination register is filled with 0. Therefore, the new version implements the merge mode by adding an L.PSEL instruction. The directive is defined as follows:
+
+**2.5.1 Instruction definition**
+
+Instruction semantics: According to each bit mask in register SrcP, select the value of the left source register or the right source register to be written to the destination register. A mask of 1 selects the left source register SrcL; a mask of 0 selects the right source register SrcR.
+
+Assembly syntax:
+```asm
+v.psel SrcP, SrcL., SrcR.<.neg>, ->Dst.
+v.psel SrcP, SrcL., SrcR.<.neg>, ->Dst.
+```
+
+- SrcP can be the P register or the scalar register (each bit in the scalar register is read as a lane condition mask).
+- SrcR supports the optional ".neg" parameter, which is used to add one to the bitwise negation of the SrcR operand.
+
+The instructions are encoded as follows:
+
+
+
+**2.6 Add instruction constraints**
+
+The setret instruction is used in the CAL block or ICALL block to record the return address to the ra register. In the previous design, this instruction could be placed anywhere in body, and the return address was calculated by adding offset to the current TPC.
+
+However, the following problems were found during the implementation of the microarchitecture:
+
+- setret triggers the call_ret prediction address to be pushed into the predictor when the IFU is retrieved.
+- If setret is not the first microinstruction in the block, and nuke_flush occurs before the setret instruction, it will cause the call_ret prediction address to be pushed into the predictor repeatedly, and eventually the call_ret prediction function will fail.
+
+
+
+Therefore, the new version adds the following constraints: **In block instruction of CALL or ICALL type, the setret or c.setret instruction must be placed after BSTART**. Otherwise, the hardware triggers the illegal instruction exception.
+
+**3. System block changes**
+
+In the new version, system block instruction only supports the FALL extension type inter-block jump method, so the codes corresponding to other jump types are deleted. Conditional jumps or function calls in the program can be implemented through the integer scalar block or the floating point scalar block.
+
+32bit encoding:
+
+
+
+48t encoding:
+
+
+
+64bit encoding:
+
+
\ No newline at end of file
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+# 0.55 version update
+
+Update date: November 17, 2025
+
+For the path to the web version of the instruction encoding design document, please see [LinxISA Encoding-0.55](https://dbox.huawei.com/detaildocs?oid=VR:wt.doc.WTDocument:101082569709)
+
+## 1. Update background
+
+- exception processing and debugging: The exception/interrupt processing flow has been improved, and the debugging function support has been strengthened.
+- Instruction set expansion: V.MOV instructions, scaling matrix multiplication instructions (MAMULBMX series) and DMA instructions have been added to optimize the vector processing and matrix operation capabilities.
+- Register adjustment: The functions of the BARG register have been expanded, and the EBPCN register has been added, which improves the control capabilities of block instruction and the processing capabilities of exception.
+- Architecture support: Added a new template block instruction based on the PTO instruction set, which provides support for the evaluation of the first layer architectural state.
+
+## 2. Update summary
+
+LinxISA0.55 version includes three sub-versions (0.55.0, 0.55.1, 0.55.2), each sub-version is optimized and enhanced for different functional modules. The following are the main updates in each sub-version:
+
+### Version 0.55.0
+
+| Category | Modifications | Description |
+|------|---------|---------|
+| 1. **exception processing related** | 1.1 BSTATE definitions of different block type | Used to refine the design of different block type in the current version |
+| | 1.2 Update EBSTATE implementation | Adapt the design of some Tile blocks that cannot access memory |
+| | 1.3 Strengthen exception processing design | Add exception storage processing of Tile block |
+| | 1.4 Updated privilege level switching design | Added processing of Tile blocks during privilege level switching |
+| | 1.5 Modify part of system register | Adapt the design saved and restored by the current version block instructionexception |
+| | 1.6 Revised acrc/acre command definition | exception is triggered immediately after acrc/acre is submitted to achieve accurate exception |
+| 2. **Software debugging related** | 2.2 Enhanced definition of EBREAK instruction | Add immediate parameters to support other debugging capabilities such as kprobe/uprobe outside GDB. The meaning of immediate data is defined by the kernel |
+| | 2.2 Add the 16bit version of the C.EBREAK instruction | The 16bit version can safely replace the instruction at any address without destroying the next instruction when used for GDB debugging |
+
+### Version 0.55.1| Category | Modifications | Description |
+|------|---------|---------|
+| 1. **New instruction** | V.MOV instruction | Add a new vector instruction that is not controlled by the global P-Mask and is used to fully copy the register contents in the control flow branch. |
+| | Scaling matrix multiplication instructions | Added MAMULBMX, MAMULBMXAC and MAMULBMX.ACC instructions to support the micro-scaling mechanism and improve the numerical dynamic range and expression capabilities of matrix multiplication. |
+| | DMA command | Added MCOPY.D command and dma command to support memory data transfer through DMA. |
+| 2. **Instruction revision** | FENCE instruction | Synchronize the instruction design of version 0.43-Beta, rename FENCE.D to DSB, FENCE.I to ISB, and add the flag bit M of the DSB instruction. |
+| | ESAVE and ERCOV instructions | Revised to multiple input multiple output instructions, support saving and restoring context within the block, and add saving and restoring body starting TPC. |
+| 3. **Register Adjustment** | BARG Register | Expand the BPC and BPCN fields to 64 bits, add BlockType, Type, Taken, AQ, RL and other fields to improve the control capabilities of block instruction and exception processing. |
+| | Newly added EBPCN register | Used to save the next block instructionBPC after exception occurs in block instruction, ensuring that the program can resume execution correctly after exception is processed. |
+
+### Version 0.55.2
+
+1. **New template block instruction**: The new 70+ template block instruction is designed to optimize the state management of the first-layer architecture and improve the flexibility and scalability of the instruction set.
+
+---
+
+## 3. Detailed description
+
+### **1.1 BSTATE enhanced definition**
+
+In LinxISA, the internal state of a block execution unit is called BSTATE. BSTATE is a set of registers related to block execution. Different block execution units (block type) may use different formats of BSTATE. BSTATE is divided into three parts: BARG, TPC and LPR. Among them, BARG represents the control and status register related to instruction scheduling and execution, TPC points to the address of the body instruction being executed within the block, and LPR represents the private register group of the current block. BSTATE is defined as follows:
+
+| Name | Description |
+|------|-------|
+| BARG (Block Arguments Register Group) | Used to record the scheduling and execution information of block instruction in the first-layer architecture and the status information inside the block. |
+| TPC (Temporal Program Counter) | Microinstruction pointer register, used to indicate the address of the microinstruction within the block being executed. |
+| LPR (Local Purpose Register) | general-purpose register inside block instruction. |
+
+**1.1.1 Definition of BARG**
+
+BARG is a register group that evolved from the previous version of CARG. In the current design, BARG not only contains the information when block instruction is submitted, but also stores the scheduling information and execution attributes of block instruction, so renaming it BARG is more consistent with the definition.
+The BARG register contains a series of different fields, each of which allows it to be set independently by the corresponding instruction. And each field is allowed to be valid under a specific block type, as follows:| Field | Bitwidth | Description | Valid block type |
+|------|------|------|----------|
+| BPC | 64 | BPC for current block instruction | All block type |
+| BPCN | 64 | The offset of the BPC of the next block instruction in the execution logic relative to the BPC of this block. | STD, FP |
+| LRA | - | The offset of the local return address in the detached block relative to the BPC of this block. (Multiple BPCN field) | MPAR, MSEQ, VPAR, VSEQ |
+| BlockType | 5 | Current block's block type | All block type |
+| Type | 2 | Jump method | STD, FP |
+| Taken | 1 | Jump to the taken flag bit | STD, FP |
+| AQ,RL | 2 | Execution sequence attributes | STD, SYS, FP, VPAR, VSEQ |
+| RegDst0 | 5 | Record the first output of the split block GGPR | MPAR, MSEQ, VPAR, VSEQ |
+| RegDst1 | 5 | Record the second output of the split block GGPR | MPAR, MSEQ, VPAR, VSEQ |
+| RegDst2 | 5 | Record the 3rd output of the split block GGPR | MPAR, MSEQ, VPAR, VSEQ |
+| RegDst3 | 5 | Record the 4th output of the split block GGPR | MPAR, MSEQ, VPAR, VSEQ |
+
+Description:
+
+- MPAR, MSEQ, VPAR, VARQ, etc. are defined as separate block structure, so the LRA field is valid.
+- STD and FP blocks support full jump mode, so the BPCN, TYPE, and TAKEN fields are valid.
+- TMA and CUBE blocks are hardened implementations of block instruction and cannot be programmed internally. So there is only BPC.
+- MPAR and MSEQ blocks have AQ and RL attributes by default (see memory model MCALL mode for details).
+- The RegDst0~RegDst3 fields are initialized by the B.IOR instruction in header. If the field is invalid, it is encoded as 0.
+
+The domain segment definition of BARG is as shown in the figure below:
+
+
+
+Among them, BPCN_OFFSET and LRA_OFFSET multiplex the same field, and the storage content of this field is determined by block type.
+
+**1.1.2 TPC definition**
+
+TPC is used to record the address of the microinstruction executed within the block.
+
+- For integer scalar blocks, system blocks and scalar floating point blocks, there is only one TPC within the block.
+- For memory access parallel blocks and vector parallel blocks, there is an independent TPC in each parallel group.
+- For memory access serial blocks and vector serial blocks, groups within the blocks are serialized, so there is only one TPC.
+- For TMA and CUBE blocks, the block interior is not programmable, so there is no TPC.
+
+**1.1.3 LPR definition**
+
+Similarly, LPR also contains a series of registers, and the contents are different in different block type:| Register | Register bit width | Description | Valid block type |
+|-------|-----------|------|------------|
+| **T/U** | 64bit | scalar register | STD, SYS, FP, MPAR, MSEQ, VPAR, VSEQ |
+| **RI/RO** | 64bit | Formal parameter register | MPAR, MSEQ, VPAR, VSEQ |
+| **PRED(P)** | 64bit | Mask register | MPAR, MSEQ, VPAR, VSEQ |
+| **LB** | 16x4 bit | Lane total counter | MPAR, MSEQ, VPAR, VSEQ |
+| **LC** | 16x4 bit | Lane counter | MPAR, MSEQ, VPAR, VSEQ |
+| **VT/VU/VM/VN** | 32bit x LaneNum | vector register | MPAR, MSEQ, VPAR, VSEQ |
+| **Output Tile** | 512Byte ~ 32KB | Output Tile register | MPAR, MSEQ, VPAR, VSEQ, TMA, CUBE |
+
+### **1.2 EBSTATE update definition**
+
+The state within the block where exception occurs or is interrupt is called EBSTATE. In previous versions, EBSTATE was stored in the memory space pointed to by EBSTATEP. Since version 0.5 introduced Tile blocks and some Tile blocks do not allow access to memory, the storage method of EBSATE is adjusted as follows.
+
+**1.2.1 EBSTATE save and restore**
+
+In the new version, the storage methods of EBSTATE of different block type are defined as follows:| block type | Save BSTATE to EBSTATE | Restore from EBSTATE |
+|--------|------------------------|----------------|
+| STD, SYS, FP | Hardware saving required:
Save BPC to SSR:EBPC;
Save the rest of the information in BARG to SSR:EBARG;
Save TPC to SSR:ETPC;
Software selective saving:
Save scalar registers such as T/U to Memory. | Requires hardware recovery:
Recover BPC from SSR:EBPC;
Recover jump information from SSR:EBARG and wait until BARG;
Recover TPC from SSR:ETPC;
Software selective recovery:
Recover T/U and other scalar registers from Memory. |
+| VPAR, VSEQ;
MPAR, MSEQ | Hardware saving required:
Save BPC to SSR:EBPC;
Save the remaining information in BARG to SSR:EBARG;
Record the GroupID of the Group that triggered exception in SSR: EBARG;
Software selective saving:
Save all or a certain type of Tile registers to memory by calling the TSTORE instruction;
Save the TPC and LPR of the Group to the Tile register by calling ESAVEtemplate block;
Save the contents of the Tile register output by ESAVE to memory by calling the TSTORE instruction. | Hardware recovery required:
Recover BPC from SSR:EBPC;
Recover BARG from SSR:EBARG;
Software selective recovery:
Load LPR from memory to the Tile register by calling the TLOAD instruction.
Restore the status of the Group by calling ERCOVtemplate block;
Load the contents of the Tile register back from memory by calling the TLOAD instruction. |
+
+**1.2.2 Added system register**
+
+In the new version, a group of system register is added for the hardware to store the exception address, block instruction internal status and block type when the hardware actively generates exception and passively generates interrupt, and updates the block type that triggered this hardware update. After the exception or interrupt processing is completed, restore from this set of registers.
+
+EBPC and ETPC, etc.:
+
+| SSR_ID | Register | Bit width | Description |
+|--------|---------|------|------|
+| 0xnf0b | EBPC | 64 | Used to record block instructionBPC and BPCN_OFFSET when exception occurs. |
+| 0xnf0c | EBARG | 64 | Used to save the block instruction jump mode, block type and output register parameters when exception occurs. |
+| 0xnf0d | ETPC | 64 | Microinstruction TPC used to record the occurrence of exception. |
+| 0xnf0e | EBPCN | 64 | Used to record the BPC of the next block of block instruction where exception occurs. |
+
+Among them, the format of the EBPC register is defined as follows:
+
+
+
+The format of the EBARG register is defined as follows:
+
+
+
+The format of the ETPC register is defined as follows:
+
+
+
+The format of the EBPCN register is defined as follows:
+
+
+
+**1.2.3 Added ESAVE and ERCOVtemplate block**As mentioned in 1.2.1 above, when exception or interrupt occurs in a Tile block such as VPAR/VSEQ/MPAR/MSEQ, the software can call ESAVEtemplate block to save the LPR content in the block to the Tile register. When exception is restored, the state of the registers in the block is restored from the Tile register by calling ERCOVtemplate block.
+
+The two template block are defined as follows:
+
+exception save block-ESAVE is used for vector data block or access data block. When exception or interrupt is encountered during execution, all contexts in the block are saved to the specified Tile register. ESAVE is a multi-output instruction, where:
+
+- The first output Tile register is used to save the private registers within the exception block, including LB/LC registers, scalar registers, vector registers, mask registers, etc.
+- Other output Tile registers are used to save the contents of the output Tile of the exception block itself.
+
+In the current version, since the vector data block and memory access Tile block can have up to 4 output Tile registers, the ESAVE instruction can have up to 5 output Tile registers.
+
+Assembly format: `ESAVE , ->DstTile0<32KB>, DstTile1<32KB>, ..., DstTile4<32KB>`
+
+exception recovery block-ERCOV is used for vector data block or access data block. After exception or interrupt processing is completed, all context states in the block are restored from the specified Tile register.
+
+ERCOV is a multi-input instruction where:
+
+- The first input Tile register is used to restore the private registers within the exception block, including LB/LC registers, scalar registers, vector registers, mask registers, etc.
+- Other input Tile registers are used to restore the output Tile register contents of the exception block itself.
+
+Matching the number of output Tiles of the ESAVE instruction, the current version of the ERCOV instruction has up to 5 input Tile registers.
+Assembly format: `ERCOV SrcTile0, SrcTile1, ..., SrcTile4`
+
+The encoding of BSTART.TEPLblock instruction is as follows:
+
+
+
+Function field encoding mapping table:
+
+| Function | TileOp | Description |
+|----------|--------|--------|
+| 0-29 | RESERVE | Reserved |
+| 30 | **ESAVE** | exception save block, used to save the block state of the Tile block where exception occurs. |
+| 31 | **ERCOV** | exception recovery block, used to restore the block state of the Tile block where exception occurred. By default, it has inheritable attributes, and the subsequent sequence block instruction can inherit the internal state of this block. |
+
+### 1.3 exception processing
+
+**1.3.1exception**
+
+exception is an event that is detected synchronously in the instruction pipeline. This kind of event usually causes the pipeline to be logically unable to continue (for example, the requirements of the instruction cannot be met), and must be immediately transferred to other instruction sequences.
+exception can occur synchronously during the execution of the instruction. During this process, part of the behavior of the instruction may have taken effect, may not have taken effect, or may have all taken effect. The specific situation and specific instructions are related to the type of exception. If there is no special explanation, by default the specific instruction exception occurs, then all actions required by the instruction will not take effect, and the exception instruction pointer will still stay on the instruction where exception occurred.LinxISA supports the exact exception of header instruction and body instructions. Regardless of the header instruction or body instruction exception, the exceptionblock instruction pointer EBPC always points to the block instructionBSTART where exception occurs, and ETPC always points to the address of the exception instruction. If it is body instruction exception, the processor needs to set the exception status register ECSTATE_ACRn.BI (BI means BlockI nner) is set to 1; on the contrary, if it is header instructionexception, the exception status register ECSTATE_ACRn.BI needs to be set to 0. The software can decide whether to save and restore the intra-block status of the exception block through BI information.
+
+Special note:
+
+- If exception occurs in the middle of a block, the hardware must ensure that the contents of all registers inside the exception block are retained and resources are not released. This ensures that the software can save the internal state of the exception block through a new block (such as ESAVEtemplate block).
+- exception is not supported during CUBE block execution.
+- Generating exception is not supported internally in the TMA block.
+
+**1.3.2 Added block instructionexception type**
+
+When scheduling is triggered, in order for the kernel (ACR1) to determine whether the user mode uses VECTOR or CUBE type block instruction, the corresponding context can be saved and scheduled. The current version adds the following control mechanisms:
+
+- When the core (ACR1) is initialized, configure the exception enable bit in the SCONFIG_ACR1 register to 1;
+- When the user mode (ACR2) process uses VECTOR or CUBE type block instruction, the corresponding exception is triggered to fall into ACR1, exception code TRAPNUM=0, CAUSE=4. The kernel performs corresponding processing:
+ * Configure the exception enable bit of different block type in the ECONFIG_ACR1 register to 0 to ensure that subsequent use of VECTOR and CUBE instructions in user mode will not trigger exception;
+ * Record that the current process has used VECTOR and CUBE marks TIF_VECTOR/TIF_CUBE;
+ * Allocate VECTOR and CUBE block context to save address space.
+- When subsequent user mode falls into the kernel again (interrupt or other exception), if scheduling is triggered, the kernel checks the prev process TIF_VECTOR/TIF_CUBE flag. If it is set, the kernel saves the prev process context.
+
+The above is only used to briefly explain the exception processing method of VECTOR or CUBEblock instruction. The specific implementation process kernel can be adjusted and designed.
+
+Added exception types as follows:
+
+| TrapNum | Reason code (Cause) | exception parameter code | Trigger command |
+|---------------------|-----------------|-------------|---------------|
+| E_INST(0) | E_PEREM(4) | 0 | MPAR/MSEQ/VPAR/VSEQ |
+| | | 1 | CUBE |
+
+Note: The ECONFIG register is modified from the IENABLE register, and the V and C flag bits are added based on the original fields of IENABLE as the exception enable bits of the VCETOR and CUBE instructions.
+
+Register format:
+
+**1.3.3 Status Migration**
+
+The operating system OS’s solution for context switching (Context Switch) on different processing units of Janus Core is designed as follows:
+
+* **BCC Context Switch**
+ *Context saving:
+ 1. Save EBARG to memory
+ 2. If context switch occurs in body, save LPR to memory
+ *Context recovery:
+ 1. Restore EBARG from memory
+ 2. If context switch occurs in body, restore the status of LPR in the block
+ 3. Execute the ACRE instruction (if the context switch occurs in body, the ACRE parameter must be 1.
+* **VECTOR/MTC Context Switch**
+ *Context saving:
+ 1. Save EBARG to memory
+ 2. If context switch occurs in body, save LPR to memory:
+ 1. If necessary, save all Tile registers to memory: TSTORE T#1~T#8, U#1~U#8, M#1~M#8, N#1~N#8;
+ 2. Save the LPR to the Tile register through ESAVE, and then save the Tile register to memory through TSTORE.
+ *Context recovery:
+ 1. If context switch occurs in body, restore LPR from memory:
+ 1. Load the LPR content into the Tile register through TLOAD, and then restore the LPR status through ERCOV;
+ 1. If necessary, restore the contents of all Tile registers from memory: TLOAD T#1~T#8; TLOAD U#1~U#8; TLOAD M#1~M#8; TLOAD N#1~N#8;
+ 1. Restore EBARG from memory;
+ 2. Execute the ACRE instruction (if the context switch occurs in body, the ACRE parameter must be 1.)
+* **CUBE Context Switch for ACC**
+ *Context saving:
+ 1. Copy the contents of the ACC register to the general Tile register: ACCCVT ACC, ->dstTile;
+ 2. Save the contents of the Tile register to memory: TSTORE srcTile;
+ *Context recovery:
+ 1. Restore the contents of the Tile register from memory through the TLOAD instruction; example: TLOAD ->T
+ 2. Construct a matrix (identity matrix) with a main diagonal of 1 through the BSTART.VPAR block; example: VPAR ->T
+ 3. Restore the contents of the ACC register through the MAMULB instruction. Example: MAMULB T#2, T#1, ->ACC
+
+### **1.4 Privilege Level (ACR) Switch**
+
+ACR switching allows active triggering by internal or external requests from the Linx core (LxLC). The request sources are divided into exception, interrupt, system-call block instructions, ACRC and ACRE microinstructions, etc.*exception, the system switches to the target ACR state. Mainly used by the managed software to return control of the Linx core (LxLC) to the management software. The ACRC instruction belongs to the body microinstruction.
+*interrupt includes external interrupt (EI) and Timerinterrupt (TI)
+* The ACRE microinstruction only takes effect within the system block. Submission of this instruction will immediately submit the current block and enter the target ACR. Mainly used for management software to actively hand over control of the Linx core (LxLC) to the managed software.
+* system-call block, the system switches to the target ACR state when the block is called, and returns to the ACR before the switch after the block is submitted. Mainly used for efficient invocation of critical cross-privilege level requests.
+
+**1.4.1 SERVICE_REQUEST**
+
+SERVICE_REQUEST can only be driven by exception or interrupt. exception are all synchronous and are called SYNC_SERVICE_REQUEST. interrupt is asynchronous and called ASYNC_SERVICE_REQUEST.
+SYNC_SERVICE_REQUEST and ASYNC_SERVICE_REQUEST are collectively called traps in Linx Instruction Set Architecture, and the process of entering the trap is called falling into. SERVICE_REQUEST process is as follows:
+
+For any SERVICE_REQUEST from ACRn to ACRm, the specific behavior is:
+
+* If it is related to exception generated by floating point operation, set the corresponding flag bit in CSTATE.flags.
+* The current SSR:CSTATE is saved to SSR:ECSTATE_ACRm. If the triggering instruction is header instruction, set SSR:ECSTATE_ACRm.BI to 0, otherwise set to 1;
+* The BPC of exception block is saved to EBPC_ACRm;
+* Save the BARG content of exception block to EBARG_ACRm and set EBARG_ACRm.BlockType to trigger block type.
+* If the exception block is an STD, SYS or FP block, save the TPC that triggered the exception instruction to ETPC;
+* If the exception block is an MPAR or VPAR block, save the GroupID that triggered the exception to the GroupID field of EBARG.
+* CSTATE.I is set to 0; # interrupt enable bit
+* CSTATE.ACR position is m;
+* BARG reset to initial value;
+* BPC is set to EVBASE_ACRm;
+* For SYNC_SERVICE_REQUEST:
+ * TRAPNO_ACRm.E is set to 1; # Synchronize exception flag
+ * Set SSR:TRAPNO_ACRm and SSR:TRAPARG0_ACRm according to the trap code and parameters.
+* For ASYNC_SERVICE_REQUEST:
+ * TRAPNO_ACRm.E is set to 0;
+ * Set SSR:TRAPNO_ACRm and SSR:TRAPARG0_ACRm according to interrupt type.
+The above actions are completed once inside the Linx logic core (LxLC), and there will be no other actions that change the state of the Linx logic core (LxLC).
+
+**1.4.2 ACR_ENTER**
+
+ACR_ENTER is requested through the ACRE instruction and is fired when the instruction is submitted. For an ACR_ENTER initiated from ACRn, the specific process is:* The ACR state of Linx logic core (LxLC) switches to system registerECSTATE_ACRn.ACR. The target ACR must be comparable to the current ACRn, and ACRn p>= ECSTATE_ACRn.ACR. Otherwise this step itself triggers E_INST(EC_PARAM)exception;
+* Use the contents of SSR:ECSTATE_ACRn to restore the current SSR:CSTATE state;
+* Use SSR:EBPC_ACRn to restore the contents of BPC and schedule the execution of the block where BPC is located;
+* According to the ACRE.RRA parameter, select whether to use the contents of SSR: EBARG_ACRn to restore BARG.
+* If the block type recorded in EBARG is STD, SYS or FP, use the contents of SSR:ETPC_ACRn to resume TPC execution;
+
+### **1.5 Partial modifications of system register**
+
+In order to adapt to the design of the existing exception processing flow, some system register have been deleted as a whole and some fields have been modified.
+
+1.5.1 Delete the ebv bit of CSTATE register
+
+Before modification:
+
+
+
+After modification:
+
+
+
+**1.5.2 Modify the ebv bit of ECSTATE**
+
+The ebv bit of ECSTATE is changed to BI, which is used to identify whether the exception block service request SERVICE_REQUEST occurs in the middle of the block. If it occurs within body, this bit is set to 1, otherwise it is cleared.
+
+Before modification:
+
+
+
+After modification:
+
+
+
+The software can decide whether to save and restore the state in the block based on whether the BI bit of ECSTATE is set.
+
+**1.5.3 Delete the BI flag of TRAPNO**
+
+Duplicate with the BI definition in ECSTATE, so deleted.
+
+
+
+After modification:
+
+
+
+**1.5.4 Delete ELINK and EBSTATEP registers**
+
+In the original design, ELINK is used to save the BPC of the exception block when the exception service request SERVICE_REQUEST processing occurs. EBSTATEP is used to store the memory pointer of EBSTATE. Under the new design, the BPC of the exception block is saved to EBPC, so ELINK is deleted. Part of EBSTATE is saved in the register and the other part of the software decides whether to save it instead of saving it uniformly in the memory, so EBSTATEP is deleted.
+
+
+
+### 1.6 Update ACRC and ACRE instruction definitions
+
+**1.6.1 Enhanced definition of acrc execution semantics**
+
+In the new version, acrc execution semantics are modified to: immediately submit the current block and initiate a system request. The request type is specified by the request_type parameter. Other definitions remain unchanged.
+
+Constraints: The arcc instruction is an instruction with BSTOP semantics, so it must be the last microinstruction of block instruction.
+
+After this command triggers a system request, the processing is the same as that of ordinary exception. The hardware saves the BPC to EBPC of the block where acrc is located and the TPC of acrc to ETPC. Then before returning to user mode:
+
+- If the software is not modified, it will return to the original acrc address and re-initiate a system request. (redo syscall)
+- If you expect to return to the next instruction of acrc to continue execution, then the software needs to change the addresses in EBPC and ETPC to the original value of ETPC plus 4 (that is, the instruction length of acrc).
+
+Example:
+```asm
+ BSTART.SYS <--- BPC
+ B.ATTR TRAP
+ ldi [a0, 8], ->t
+ ldi [a0, 16], ->t
+ mul t#1, t#2, ->t
+ acrc SCT_SYS <--- TPC
+ BSTART.STD <--- NextBPC
+ ...
+```
+
+How to continue execution after ACRC triggers the system call is explained as follows:| exception Save Register (SSR) | Contents saved by hardware | Software does not modify, re-initiate request | Software modify, continue execution from the next instruction of ACRC |
+|-------------------------|--------------|--------------------------|----------------------------------|
+| EBPC | BPC | BPC | TPC+4 |
+| ETPC | TPC | TPC | TPC+4 |
+
+**1.6.2 Modification of acre command**
+
+The acre instruction is used to set the ACR switching requirements of the current block, immediately submit the current block and execute the ACR_ENTER process to switch the current ARC to the target ACR. The target ACR is specified by the ECSTATE register of the privilege level in which the acre instruction is executed.
+The acre command has a Return Request Argument parameter, referred to as RRA, which is used to specify the status of exception when it is submitted.
+
+Instruction assembly: `acre RRA_Type`
+
+In the current version, the value range of RRA_Type includes:
+
+- RRAT_DEFAULT(0): BSTATE is reset to the default state when submitted.
+- RRAT_RESTORE(1): Initialize BSTATE with EBSTATE.
+- Other values are reserved. If other values are encountered during execution, the illegal instruction exception will be triggered when submitting.
+
+Modification point: Delete the RRAT_REDO_ECALL type when RRA_Type is 2. The software can perform the REDO_ECALL operation by modifying the values of EBPC and ETPC.
+
+Things to note:
+
+- After this instruction is submitted, the current block instruction will be submitted immediately. Therefore, this instruction must be used as the last microinstruction of block instruction.
+- block instruction where acre is located is inheritable, and the subsequent sequence block instruction can inherit the internal state of this block.
+
+Example of using acre:
+```asm
+# ZXTERMZH41QXZ恢复时特权态：
+ERCOV <- 恢复ZXTERMZH41QXZ块的块内状态
+BSTART.SYS
+acre RRAT_RESTORE <- 返回指定特权级
+# 返回用户态执行BPC指示的块
+BSTART.xx # 新块继承恢复的状态
+inst <- 从ETPC恢复的TPC指示的指令
+```
+
+### **2.1 Update EBREAK command**
+
+The EBREAK (Exception break) instruction is used to trigger software breakpoint. This instruction requests the debugger by throwing the breakpoint exceptionE_BREAKPOINT and writes the immediate value to the low bit of the cause field of the SSR:TRAPNO register.
+
+Assembly format: `ebreak imm`
+
+In order to meet the needs of kernel debugging, the new version revise the ebreak instruction as follows:
+
+- Added immediate parameter for kernel debugging, the meaning of immediate is defined by the kernel.
+- Delete CMT parameters and process them in the same way as ordinary exception.
+- Adjust the encoding. The modified instruction encoding is shown in the figure below.
+
+Instruction encoding:
+
+
+
+### **2.2 Add C.EBREAK command**
+
+Because in LinxISA, the minimum instruction length is 16 bits. Therefore, a c.break instruction is added to the new version so that the debugger can safely replace the instruction at any address without destroying the next instruction.
+
+Assembly format: `c.ebreak imm`
+
+The encoding format is as follows:
+
+
+
+During hardware execution, the immediate value also needs to be written to the low bits of the cause field of the SSR:TRAPNO register.
+
+### V.MOV instruction
+
+- **Background**: In the control flow branch, due to the limited relative index distance of the registers, an instruction that is not controlled by the global P-Mask is required to implement a full copy of the data.
+- **Definition**: The assembly format is `v.mov SrcL., ->RegDst.`, which implements a full copy of the input register SrcL and writes the result to the destination register RegDst.
+- **Example**: Use `v.mov vt#1, ->vt` in the else branch to fully copy the register contents in the if branch.
+
+### MAMULBMX scaling matrix multiplication instructions and micro-scaling mechanism- **Purpose**: Improve the numerical dynamic range and expressive capabilities of matrix multiplication, and support approximate operations under FP32 precision or precision compensation for low bit-width multiplication.
+- **Command Type**:
+ - **MAMULBMX**: Perform scaled matrix multiplication and write the result to the ACC register.
+ - **MAMULBMXAC**: Perform scaled matrix multiplication and addition operations, and write the results to the ACC register.
+ - **MAMULBMX.ACC**: Execute the scaled matrix multiply and accumulate operation, and write the result to the ACC register.
+- **Micro-zooming mechanism**:
+ - **Hardware Basics**: CUBE Core's 16×16×16 Tile-level matrix multiplication unit, the scaling unit is located in the input multiplication path of Tile A and Tile B, and the scaling factors are stored in ScaleTileA and ScaleTileB.
+ - **Calculation method**:
+ 1. Scale the input Tile element by element:
+ - Tile A: `A_scaled[i][j] = A[i][j] * ScaleA[i][j]`
+ - Tile B: `B_scaled[i][j] = B[i][j] * ScaleB[i][j]`
+ 2. Perform scaled matrix multiplication: `ACC[M][N] += MAMULB(A_scaled[M][K], B_scaled[K][N])`
+ - **Key Features**: K dimensions share scaling factors, each row of ScaleA shares a factor, and each column of ScaleB shares a factor, reducing storage and transmission overhead.
+
+### DMA instructions
+
+- **MCOPY.D instruction**: Added a new instruction that supports DMA copy. When the hardware does not support DMA, it is equivalent to the original MCOPY instruction.
+- **dma command**: Copy 64 bytes of data from the source address to the destination address. Submit the command after the copy is completed.
+
+### FENCE directive revision
+
+- **FENCE.D command**: Name changed to DSB. Add the flag bit M, M=0 indicates the system default synchronization method, and M1 indicates the user-defined synchronization method.
+- **FENCE.I command**: Name changed to ISB.
+
+### Add TEPL class TileOp definition
+
+This type of TileOp is uniformly opened by the "BSTART.TEPL" instruction, and then the specific TileOp is specified through the "Mode" and "Function" field codes. The encoding of the "BSTART.TEPL" instruction is as follows:
+
+
+
+The list of new TileOps is as follows:| Mode | Function | TileOp | Description |
+|------|----------|--------|------|
+| 0 | 0 | TADD | Element-wise addition of two Tiles. dst = src0 + src1 |
+| 0 | 1 | TSUB | Element-wise subtraction of two Tiles. dst = src0 - src1 |
+| 0 | 2 | TMUL | Element-wise multiplication of two Tiles. dst = src0 * src1 |
+| 0 | 3 | TDIV | Element-wise division of two Tiles. dst = src0 / src1 |
+| 0 | 4 | TREM | The element-wise remainder of two Tiles, with the remainder sign being the same as the divisor. dst = remainder(src0, src1) |
+| 0 | 5 | TFMOD | The element-wise remainder of two Tiles, with the remainder sign being the same as the dividend. dst = fmod(src0, src1) |
+| 0 | 6 | TAND | Element-wise bitwise AND of two Tiles. dst = src0 & src1 |
+| 0 | 7 | TOR | Element-wise bitwise OR of two Tiles. dst = src0 | src1 |
+| 0 | 8 | TXOR | Element-wise bitwise XOR of two Tiles. dst = src0 ^ src1 |
+| 0 | 9 | TSHL | Element-wise left shift of two Tiles. dst = src0 << src1 |
+| 0 | 10 | TSHR | Element-wise right shift of two Tiles. dst = src0 >> src1 |
+| 0 | 11 | TMAX | The element-wise maximum value of two Tiles. dst = max(src0, src1) |
+| 0 | 12 | TMIN | The element-wise minimum value of two Tiles. dst = min(src0, src1) |
+| 0 | 13 | TCMP | Compares two Tiles and writes a packed predicate mask. dst = cmp.xx(src0, src1) |
+| 0 | 14 | TPRELU | Element-wise parameterized ReLU with element-wise slope Tile. dst = (src0 > 0 ? src0 : src1 * src0) |
+| 0 | 15 | TABS | The element-wise absolute value of the Tile. |
+| 0 | 16 | TNOT | Element-wise bitwise negation of Tile. |
+| 0 | 17 | TNEG | Element-wise negation of Tile. |
+| 0 | 18 | TEXP | Element-wise exponential operation. |
+| 0 | 19 | TLOG | The element-wise natural logarithm of Tile. |
+| 0 | 20 | TRECIP | The element-wise reciprocal of Tile. |
+| 0 | 21 | TSQRT | Element-wise square root. |
+| 0 | 22 | TRSQRT | Element-wise reciprocal square root. |
+| 0 | 23 | TRELU | The element-wise ReLU of the Tile. dst = src0 > 0 ? src0 : 0 |
+| 0 | 24 | TADDC | Ternary element-wise addition: dst = src0 + src1 + src2. || 0 | 25 | TSUBC | Ternary element-wise subtraction: dst = src0 - src1 + src2. |
+| 0 | 26 | TSEL | Use a masked Tile to select between two Tiles (element-wise selection). dst = (mask > 0 ? src0 : src1) |
+| 0 | 27-31 | RESERVE| Reserved |
+| 1 | 0 | TADDS | Element-wise addition of Tile with scalar. |
+| 1 | 1 | TSUBS | Subtract a scalar element-wise from the Tile. |
+| 1 | 2 | TMULS | Element-wise multiplication of Tile with scalar. |
+| 1 | 3 | TDIVS | Element-wise division with scalar (Tile/scalar or scalar/Tile). |
+| 1 | 4 | TREMS | Element-wise remainder of scalar. dst = remainder(src, scalar) |
+| 1 | 5 | TFMODS | Element-wise remainder with scalar. dst = fmod(src, scalar) |
+| 1 | 6 | TANDS | Element-wise bitwise AND of Tile with scalar. |
+| 1 | 7 | TORS | Element-wise bitwise OR of Tile with scalar. |
+| 1 | 8 | TXORS | Element-wise bitwise XOR of Tile and scalar. |
+| 1 | 9 | TSHLS | Tile moves left element by element according to scalar. |
+| 1 | 10 | TSHRS | Tile is shifted to the right element by element according to scalar. |
+| 1 | 11 | TMAXS | Element-wise maximum value of Tile and scalar. |
+| 1 | 12 | TMINS | Element-wise minimum of Tile and scalar. |
+| 1 | 13 | TCMPS | Compare Tile to scalar element-by-element. |
+| 1 | 14 | TLRELU | LeakyReLU with scalar slope. |
+| 1 | 15-23 | RESERVE| Reserved code |
+| 1 | 24 | TADDSC | With scalar fusion element-wise addition operation. dst = src0 + scalar + src1. |
+| 1 | 25 | TSUBSC | With scalar fusion element-wise subtraction operation. dst = src0 - scalar + src1. |
+| 1 | 26 | TSELS | Use mask tile to select between source tile and scalar (element-wise selection). dst = (mask > 0 ? src0 : scalar) |
+| 1 | 27 | TEXPANDS| Broadcast scalar to the target Tile. |
+| 1 | 28-31 | RESERVE| Reserved code |
+| 2 | 0 | TROWSUM| Reduce each row by summing the columns. || 2 | 1 | TROWMAX| Reduce each row by taking the maximum value between columns. |
+| 2 | 2 | TROWMIN| Reduce each row by taking the minimum value between columns. |
+| 2 | 3 | TROWPROD| Reduce each row by multiplying across columns. |
+| 2 | 4 | TROWEXPAND| Broadcasts the first element of each source row into the target row. |
+| 2 | 5 | TROWEXPANDADD| Line broadcast addition: Add one per line scalarvector. |
+| 2 | 6 | TROWEXPANDSUB| Row broadcast subtraction: subtract one per row of scalarvectorsrc1 from each row of src0. |
+| 2 | 7 | TROWEXPANDMUL| Row broadcast multiplication: Multiply each row of src0 by one per row scalarvectorsrc1. |
+| 2 | 8 | TROWEXPANDDIV| Row broadcast division: Divide each row of src0 by one per row scalarvectorsrc1. |
+| 2 | 9 | TROWEXPANDMAX| Row broadcast maximum value: Take the maximum value with each row scalarvector. |
+| 2 | 10 | TROWEXPANDMIN| Row broadcast minimum value: Take the minimum value with each row scalarvector. |
+| 2 | 11 | TROWEXPANDEXPDIF| Row exponential difference operation: calculate exp(src0 - src1), where src1 is scalar per row. |
+| 2 | 11-15 | RESERVE| Reserved encoding |
+| 2 | 16 | TCOLSUM| Reduce each column by summing the rows. |
+| 2 | 17 | TCOLMAX| Reduce each column by taking the maximum value between rows. |
+| 2 | 18 | TCOLMIN| Reduce each column by taking the minimum value between rows. |
+| 2 | 19 | TCOLPROD| Reduce each column by multiplying across rows. |
+| 2 | 20 | TCOLEXPAND| Broadcasts the first element of each source column into the target column. |
+| 2 | 21 | TCOLEXPANDADD| Column broadcast addition: Add each column scalarvector to each column. |
+| 2 | 22 | TCOLEXPANDSUB| Column broadcast subtraction: subtract one per column scalarvector from each column. |
+| 2 | 23 | TCOLEXPANDMUL| Column broadcast multiplication: Multiply each column by one per column scalarvector. |
+| 2 | 24 | TCOLEXPANDDIV| Column broadcast division: Divide each column by one per column scalarvector. |
+| 2 | 25 | TCOLEXPANDMAX| Column broadcast maximum value: Take the maximum value with each column scalarvector. |
+| 2 | 26 | TCOLEXPANDMIN| Column broadcast minimum value: Take the minimum value with each column scalarvector. || 2 | 27 | TCOLEXPANDEXPDIF| Column exponential difference operation: calculate exp(src0 - src1), where src1 is scalar for each column. |
+| 2 | 28-31 | RESERVE| Reserved encoding |
+| 3 | 0-29 | RESERVE| Reserved code |
+| 3 | 30 | ESAVE | exception save block, used to save the block state of the Tile block where exception occurs |
+| 3 | 31 | ERCOV | exception recovery block, used to restore the intra-block state of the Tile block where exception occurred |
\ No newline at end of file
diff --git a/docs/change_log/update_v0.56.md b/docs/change_log/update_v0.56.md
new file mode 100644
index 00000000..804349fc
--- /dev/null
+++ b/docs/change_log/update_v0.56.md
@@ -0,0 +1,491 @@
+# 0.56 version update
+
+Update date: March 26, 2026
+
+For the path to the web version of the instruction encoding design document, please see [LinxISA Encoding-0.56](https://dbox.huawei.com/detaildocs?oid=VR:wt.doc.WTDocument:101184990659)
+
+---
+
+## 1. Version Overview
+
+Based on version 0.55, LinxISA (LinxISA) **0.56.0** version has been significantly updated regarding the use of **Tile registers, the encoding of block operation instructions, and the Tile capacity model**. Version **0.56.1** further aligns the **PTO instruction set** design, supplements and adjusts the definition of **TileOp**, focusing on improving instruction semantic clarity, numerical control capabilities, flexibility and hardware efficiency in complex programming modes. The two versions together constitute an important evolution of LinxISA in Tile data processing capabilities.
+
+---
+
+## 2. Key points of version changes| Serial number | Change matters | Reasons and goals of change | Introduction version |
+|------|-----------------------------------|------------------------------------------------------------------|----------|
+| 1 | **Increase the number of Tile registers (32 -> 64)** | By reducing the default/typical capacity of a single Tile and increasing the number of available Tiles, it aims to reduce the latency of frequent small data block accesses, improve the concurrency of fine-grained data operations, and support deeper software pipelines, double buffering and complex dependency chains. | 0.56.0 |
+| 2 | **Adjust the `B.IOT` / `B.IOTI` instructions** | Adapt to the newly added 32 Tile register codes, converge the `B.IOT`/`B.IOTI` dual descriptor model into the unified `B.IOT` instruction, provide a unified block operation interface, simplify the programming model and tool chain implementation. **This instruction encoding will be further optimized in 0.56.1**. | 0.56.0 |
+| 3 | **Tile capacity model changed to dynamic upper limit** | Support software to flexibly configure the size of each Tile (256B ~ 256KB) under the total capacity limit to achieve the trade-off between "more small Tiles" and "few large Tiles" to meet the needs of different computing stages and avoid low resource utilization caused by the static upper limit model. | 0.56.0 |
+| 4 | **Adjust `TCVT` instruction encoding and semantics** | 1) Align with `TCVT` definition in PTO instruction set.
2) The function focuses on **Tile element-by-element data format conversion**, removing support for data storage layout (fractal) transformation.
3) Added **rounding mode (`RMode`)** and **saturation mode (`Sat`)** parameters to enhance numerical control capabilities.
4) The ownership is adjusted to the **`TEPL` type** block. | 0.56.1 |
+| 5 | **`TCOPY` instruction is renamed to `TMOV`** | 1) Aligned with PTO instruction set naming convention.
2) The core functions remain unchanged: used to move/copy data between **Tile registers** and support **data storage layout (fractal) transformation**.
3) Reserved in **`TMA` type** block. | 0.56.1 || 6 | **Revised `B.IOT` instruction encoding (improved flexibility)** | 1) The original encoding forces the two source operands (`SrcTile0`, `SrcTile1`) to belong to the same index distance category (both "near" or "far"), which limits the free combination of Tile registers as parameters in templated assembly.
2) **Remove this restriction**: The `SrcTile0` and `SrcTile1` fields are each independently expanded to **6 bit**, and up to 64 Tile registers can be independently encoded (16 each for `T#`, `U#`, `M#`, `N#`).
3) Introduce **`function` field** to distinguish input modes (`3b100`: two inputs, `3b101`: single input, `3b110`: no input).
4 Tile Size immediate field (`imm4`) is reduced to 4 bit (still covering 32B ~ 512KB). | 0.56.1 |
+| 7 | The CUBE command **supports dtypex2 packaging format** and **HiF4 scaling** (HiF Microscaling) | Introduces a new low-precision format to adapt to more model data requirements and improve computing adaptability. | 0.56.2 |
+| 8 | CUBE instruction** supports mixed-precision input operations** | Supports left and right matrix operations in different formats, enhancing operator flexibility and compatibility. | 0.56.2 |
+| 9 | Format conversion instructions** support the conversion and quantization/dequantization of dtypex2 format data** | Improve the conversion and quantification link of low-precision data to improve end-to-end processing efficiency. | 0.56.2 |
+| 10 | Update PRED register definition (changed to 6-bit for each lane) | Adapt to the design of multi-element packing type (dtypex2, dtypex4). | 0.56.2 |
+| 11 | Floating point/integer operation instructions **Add optional rounding mode and saturation calculation** | Enhance the controllability of calculation results and improve the instruction definition. | 0.56.2 |
+| 12 | **Added BLOCKNUM and BLOCKIDsystem register** | Used for system debugging in multi-thread programming and identifying different execution modules in Trace. | 0.56.2 |
+| 13 | New TileOp instruction - **THistogram** | In order to support hardware acceleration of sorting algorithms such as topk, the THistogram instruction needs to be used to achieve efficient histogram statistics | 0.56.3 |
+| 14 | Enhanced vector data format support | 1) Added bf16 format floating point operation support
2) Explicitly declare the packaging format (such as bf16x2) through the instruction opcode and reconstruct the data calculation mechanism | 0.56.3 |
+
+---
+
+## 3. Update details
+
+### 1. Increase the number of Tile registers
+
+#### 1.1 Reasons for changes
+
+The original 32 Tile registers are difficult to support deeper software pipelines and complex Tile dependency chains (such as loop unrolling, double buffering, and multi-stage intermediate result retention). Increasing the number reduces premature collections and duplicate loads, and sets the stage for more fine-grained scheduling and complex inter-block expression.
+
+#### 1.2 Changes
+
+Expand the number of T/U/M/N type Tile registers from 32 to **64**, and the number of registers for each queue from 8 to **16**.
+
+**First layer architectural state (Tile Register)**| Register name | Explanation | Register name | Explanation |
+|------------------|----------------------------------|------------------|--------------------------------|
+| **T#1~T#8** | The results of the 1st~8th instructions before the T result queue | **M#1~M#8** | The results of the 1st~8th instructions before the M result queue |
+| **T#9~T#16** | T The result of the 9th~16th instruction before the queue | **M#9~M#16** | M The result of the 9th~16th instruction before the queue|
+| **U#1~U#8** | The results of the 1st~8th instructions before the U result queue | **N#1~N#8** | The results of the 1st~8th instructions before the N result queue |
+| **U#9~U#16** | The results of the 9th~16th instructions before the U result queue | **N#9~N#16** | The results of the 9th~16th instructions before the N result queue|
+| **ACC** | Matrix multiply-accumulate register | **S** | Stack space register |
+
+---
+
+### 2. `B.IOT` instruction modification (0.56.0 basic + 0.56.1 optimization)
+
+#### 2.1 0.56.0 Base changes
+
+* Use the `B.IOT` instruction uniformly (the original `B.IOTI` is obsolete).
+* Output Tile's **`Size`** via **`imm5`** immediate static encoding.
+* Introduced **`H` bit** to distinguish the index distance category of the source Tile register (near: 0~8 / far: 9~16).
+* Introduced **`L` bit** to mark whether it is the last `B.IOT` instruction in the block.
+* **SrcTile0/1 (3 bits each + shared H bit):** Encoded input Tile index (0-7 or 8-15).
+* **DstTile (3 bit):** Encoded output Tile target queue (T, U, M, N, S).
+
+#### 2.2 0.56.1 Optimization changes* **Core problem:** The original shared `H` bit forces the two source Tiles to belong to the same near or far category and cannot be freely combined (such as `T#1` (near) + `N#13` (far)).
+* **Solution:**
+ * **Independent encoding:** Extend the `SrcTile0` and `SrcTile1` fields** to 6 bits** each (12 bits in total), and can independently encode values 0-63, corresponding to 64 Tile registers.
+ * Remove the `H` bit concept, indexes 1-16 directly correspond to registers `T#1`-`T#16`, etc.
+ * **Input mode:** Introduced **`function` field (3 bit, command bits 12-14)**:
+ * `3b100`: Both inputs are valid (both `SrcTile0` and `SrcTile1` are valid)
+ * `3b101`: Only valid for `SrcTile0`
+ * `3b110`: No input (only output `DstTile`)
+ * *(Remove `S0V/S1V` flag)*
+ * **Tile Size:** Reduce `imm5` to **`imm4` (4 bit)**, still covering the required size range (see table below).
+
+**`imm4` encoding (0.56.1):**
+
+| imm4 | Size | imm4 | Size | imm4 | Size | imm4 | Size |
+|------|-------|------|-------|------|-------|------|-------|
+| 0 | 0B | 4 | 256B | 8 | 4KB | 12 | 64KB |
+| 1 | 32B | 5 | 512B | 9 | 8KB | 13 | 128KB |
+| 2 | 64B | 6 | 1KB | 10 | 16KB | 14 | 256KB |
+| 3 | 128B | 7 | 2KB | 11 | 32KB | 15 | 512KB |
+
+**Advantages:** Improved **flexibility and expressiveness** in scenarios where templated assembly and Tile registers are passed as parameters. Compilers/developers do not need to predetermine the allocation distance category of parameter registers and can freely combine any `T#`/`U#`/`M#`/`N#` registers (1-16).
+
+For example:
+```assembly
+B.IOT T#1, U#4, ->T<1KB> // OK (0.56.0 & 0.56.1)
+B.IOT T#1, N#13, ->U<1KB> // **0.56.1 OK** (0.56.0 受限：需同属近或远)
+B.IOT T#14, U#2, ->T<1KB> // **0.56.1 OK** (0.56.0 受限)
+B.IOT M#15, N#9, ->T<1KB> // **0.56.1 OK** (0.56.0 受限)
+```
+
+---
+
+### 3. Tile capacity model changed to dynamic allocation model (0.56.0)
+
+#### 3.1 Reasons for changes
+
+A static capped model (fixed quantity * fixed maximum capacity) overestimates actual demand and limits optimization. The dynamic model allows the compiler to flexibly trade off capacity and number based on algorithm stages (e.g. 10 4KB Tiles vs 2 64KB Tiles).
+
+#### 3.2 Changes
+
+* **Single Tile capacity range:** **256B** to **256KB**.
+* **Single-threaded active Tile total capacity limit:** **512KB**.
+* **Tile internal data storage:** **Physically contiguous**.
+
+The software can dynamically apply for different sizes in different blocks for different Tiles under the total capacity constraint.
+
+---
+
+### 4. Adjust `TCVT` command (0.56.1)
+
+#### 4.1 Changes* **Feature Focus:** **Only perform Tile element-by-element data format conversion**. **Removed** support for data storage layout (fractal) transformations (this feature is assumed by `TMOV`).
+* **Official changes:** The command type is adjusted to **`TEPL`** (`BSTART.TEPL` is turned on), classified under "Tile element-by-element operation".
+* **New parameters:**
+ * **Rounding Mode (`RMode`):** Controls rounding behavior when converting.
+ * **Saturation Mode (`Sat`):** Controls whether the results are limited to the target data type range.
+ * **Valid area (`ValidCol`, `ValidRow`):** Specifies the area in the source Tile that actually contains valid data.
+ * **Total number of columns (`Col`):** Specifies the number of logical columns of the source Tile (optional, default equals `ValidCol`).
+ * **Padding value (`PadValue`): ** Specify the value of the Padding area in the target Tile (`Null`, `Zero`, `Max`, `Min`, the default is `Null`).
+
+**Assembly format:**
+```assembly
+TCVT , SrcTile<.reuse>, ->DstTile
+```
+Encoded as the following sequence of instructions:
+```assembly
+BSTART.TEPL TCVT, SrcType
+B.ATTR DstType, RMode, Sat // RMode复用Layout字段；Sat复用Canon (C) 标志位
+B.DIM reg, imm, ->LB0 // ValidCol
+B.DIM reg, imm, ->LB1 // ValidRow
+B.DIM reg, imm, ->LB2 // Col
+B.IOT SrcTile<.reuse>, last, ->DstTile
+```
+
+**Rounding mode (`RMode`) encoding (B.ATTR multiplexed Layout field):**
+
+| Encoding | Rounding mode | Meaning |
+|------|--------------------------|---------------------------------------|
+| 0 | RNONE | Not specified (default behavior determined by hardware/implementation) |
+| 1 | RNE | Round to nearest even number (most common) |
+| 2 | RTZ | Round toward zero (truncation) |
+| 3 | RDN | Round toward negative infinity |
+| 4 | RUP | Round toward positive infinity |
+| 5 | RNA | Round toward nearest value (away from zero) |
+| 6 | RTO | Round to nearest odd number |
+| 7 | RHB | Mixed Rounding Mode |
+| >7 | reserve | reserve |
+
+Saturation flag (`Sat`) encoding (B.ATTR bit 25 `C`):
+
+| S bit | Meaning |
+|-----|--------------|
+| 0 | No saturation (default) |
+| 1 | Enable saturation |
+
+**Assembly example:**
+```assembly
+// fp32 -> fp16 ; RNE; 饱和
+TCVT , T#3, ->T<4KB>
+// fp16 -> e2m1x2 ; RNA
+TCVT , T#2, ->T<256B> // LB2(Col) 可缺省
+```
+
+---### 5. `TCOPY` instruction renamed to `TMOV` (0.56.1)
+
+#### 5.1 Changes
+
+* **Name changed:** `TCOPY` -> `TMOV`.
+* **Function remains unchanged:** The core function is still to move/copy data between **Tile registers** and support **data storage layout (fractal) transformation** (e.g., `ND2NZ`, `NZ2ZN`). *Data format conversion functionality has been moved to `TCVT`*.
+* **The ownership remains unchanged:** Still belongs to the **`TMA` type** (`BSTART.TMA` is turned on), and the Function code inherits the `2` of the original `TCOPY`.
+* **Parameter refinement:** Similar to `TCVT`, it is required to specify:
+ * **Conversion method (`Layout`):** e.g., `NORM`, `NZ2ND`, `NZ2DN`, `NZ2ZN`, `ND2NZ`, etc.
+ * **Valid area (`ValidCol`, `ValidRow`)**.
+ * **Total number of columns (`Col`)**.
+ * **data type (`DataType`)**.
+ * **Padding value (`PadValue`)**.
+
+**Assembly format:**
+```assembly
+TMOV Layout, , SrcTile<.reuse>, ->DstTile
+```
+Encoded as the following sequence of instructions:
+```assembly
+BSTART.TMA TMOV, DataType
+B.ATTR Layout, PadValue
+B.DIM reg, imm, ->LB0 // ValidCol
+B.DIM reg, imm, ->LB1 // ValidRow
+B.DIM reg, imm, ->LB2 // Col
+B.IOT SrcTile<.reuse>, last, ->DstTile
+```
+
+### 6. CUBE supports low-precision packed data format (0.56.2)
+
+#### Reason for change
+
+Low-precision types have become an unavoidable core requirement in AI computing. If ISA only supports 4-bit data at the underlying encoding level and does not provide clear naming at the software visible level, it will be difficult for compilers and programmers to uniformly understand the relationship between "an element" and "a packed byte". The new x2 series type is added to officially upgrade this packaging relationship to the software semantic layer.
+
+#### Changes
+
+**Support low-precision packaging data type**
+
+In order to enhance tensor calculation and data handling support for low-precision formats, 0.56 adds the following software visible type names:
+
+- `e2m1x2`, `e1m2x2`, `hif4x2`
+- `s4x2`, `u4x2`
+
+Among them, `x2` represents two 4-bit logical elements packed into one byte. Therefore, it is not a regular 8-bit scalar, but a packed two-element type. And when the data format of the input element is `dtypex2` type, the row and column parameters of the input matrix are passed according to the actual number of elements.
+
+The DataType field is encoded as follows:| DataType | Data Format | DataType | Data Format | DataType | Data Format | DataType | Data Format |
+|----------|-----------|----------|-----------|----------|-----------|----------|-----------|
+| 0 | FP64 | 8 | E5M2 | 16 | S64 | 24 | U64 |
+| 1 | FP32 | 9 | E3M2 | 17 | S32 | 25 | U32 |
+| 2 | TF32 | 10 | E2M3 | 18 | S16 | 26 | U16 |
+| 3 | HF32 | 11 | **E2M1x2** | 19 | S8 | 27 | U8 |
+| 4 | FP16 | 12 | **E1M2x2** | 20 | **S4x2** | 28 | **U4x2** |
+| 5 | BF16 | 13 | E8M0 | 21 | reserve | 29 | reserve |
+| 6 | HiF8 | 14 | **HiF4x2** | 22 | reserve | 30 | reserve |
+| 7 | E4M3 | 15 | reserve | 23 | reserve | 31 | invalid |
+
+**Support HiF Microscaling**
+
+The scale factor X of the HiF4 data format is a 32-bit data format consisting of 3 parts and a total of 64 elements shared. Among them, an 8-bit decimal E6M2 is shared by all 64 elements, the 8 1-bit exponents E1_8 are each shared by 8 elements, and the 16 1-bit exponents E1_16 are each shared by 4 elements. Encoding rules:
+
+- E6M2 8-bit, denoted as Ea.
+- E1_8 has a total of 8 bits, each of which corresponds to 1 bit of Ebi (i ∈ {0,..., 7}).
+- E1_16 has a total of 16 bits, each of which corresponds to 1 bit Ecj (j ∈ {0,..., 15}).
+
+The final scaling factor can be calculated as `X = Ea * 2^(Ebi + Ecj)` (i = N/8; j = N/4). Please refer to [HiF Microscaling](../isa/datatype/HiF_SCALE.md) for more details.
+
+### 7. CUBE supports mixed precision operations (0.56.2)
+
+#### Reason for change
+
+In the current version, the CUBE instruction only supports input elements with the same precision for the left and right matrices. As business demands for computing power efficiency and accuracy flexibility increase, we have added mixed-precision input support in the new version, allowing the left and right matrix input to use different precision configurations. This change can take into account computing performance and accuracy requirements, providing more flexible options for different application scenarios.
+
+#### Changes
+
+Mixed precision support:
+
+- The new version allows the left and right matrices to select different input precision types (such as FP16, BF16, etc.), and complete compatible conversion and calculation on hardware.
+- The user needs to clearly specify the input precision of the left matrix and the right matrix in the command configuration to ensure the correct calculation process.
+
+Instruction assembly format:
+```assembly
+TMATMUL SrcTile0<.reuse>, SrcTile1<.reuse>, ->ACC
+TMATMUL.ACC SrcTile0<.reuse>, SrcTile1<.reuse>, ACC, ->ACC
+TMATMUL.BIAS SrcTile0<.reuse>, SrcTile1<.reuse>, SrcTile2<.reuse>, ->ACC
+```
+
+Compared with the previous version, the assembly format adds the DataTypeB parameter, but there are no other changes. Parameter description:
+
+- **DataTypeA**: Indicates the data format of the elements in the input A matrix.
+- **DataTypeB**: Indicates the data format of the elements in the input B matrix. (Default is allowed if same as DataTypeA)
+
+Among them, the newly added DataTypeB parameter encoding and B.DATR instruction (indicated by TMATMUL):
+```assembly
+BSTART.CUBE TMATMUL DataTypeA
+B.DATR DataTypeB （注：如果和DataTypeA相同时可缺省该指令）
+B.DIM reg, imm ->LB0 （注：M）
+B.DIM reg, imm ->LB1 （注：N）
+B.DIM reg, imm ->LB2 （注：K）
+B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, last, ->ACC
+```
+Compatibility Notes:
+
+- The default configuration is still the same precision input to ensure that existing applications are not affected.
+- For performance and numerical stability considerations, it is recommended to evaluate the benefits and risks of using mixed precision based on actual business scenarios.
+
+### 8. Improve the format conversion command (0.56.2)
+
+#### Modification matters
+
+In the new version, the modifications to the scalar/vectorConvert instruction are as follows:- Supports conversion from high-precision (such as fp32, fp16, etc.) to low-precision dtypex2 format;
+- Added SrcR input for converting/quantizing two high-precision elements into dtypex2 format;
+- In order to adapt to the new SrcR, the encoding position of the SrcType field has been adjusted;
+- Added rounding mode rm field and saturated calculation sat flag bit to improve calculation stability and result controllability.
+- Added mode field to distinguish operations such as normal format conversion/quantization/inverse quantization.
+
+After modification, the assembly format is as follows (taking v.fcvt and l.fcvt as examples):
+
+v.fcvt.{st2dt} SrcL., SrcR., ->RegDst., rm, sat
+l.fcvt.{st2dt} SrcL, SrcR, ->RegDst, rm, sat
+
+The assembly symbols are explained as follows:
+
+- st (srouce type) indicates the source data format;
+- dt (destination type) represents the converted target data format.
+- rm (rounding mode) rounding mode marker.
+- sat (saturation) Flag to support saturation calculations.
+
+The vector instruction encoding is modified as follows:
+
+{ width="800" }
+
+{ width="800" }
+
+1) Rounding mode rm field
+
+| Encoding | Rounding mode | Meaning |
+|------|---------|--------|
+| 0 | RNONE | No Rounding (no rounding mode specified, default behavior determined by hardware/implementation) can be defaulted |
+| 1 | RNE | Round to Nearest, ties to Even (round to nearest even number; most common) |
+| 2 | RTZ | Round Toward Zero (round towards zero, truncate the decimal part) |
+| 3 | RDN | Round Down (rounding towards negative infinity) |
+| 4 | RUP | Round Up (rounding towards positive infinity) |
+| 5 | RNA | Round to Nearest, ties Away from Zero (away from zero) |
+| 6 | RTO | Round to Odd (round to the nearest odd number) |
+| 7 | RHB | Hybrid Rounding (Hybrid Rounding Mode) |
+| >7 | reserve | reserve |
+
+2) Saturation calculation sat bit
+
+| sat | meaning |
+|-----|--------|
+| 0 | No saturation calculation (default) |
+| 1 | Enable saturation calculation |
+
+### 9. PRED mask register modification (0.56.2)
+
+In the new version, in order to adapt to the design of "multiple data packed into vector registers" in one lane (such as fp16x2, fp8x4, etc.), pred is changed to 4-bit per lane, as follows:
+
+- p0 (1-bit): whether the first element is a valid mask
+- p1 (1-bit): whether the second element is a valid mask
+- p2 (1-bit): whether the third element is a valid mask
+- p3 (1-bit): Whether the fourth element is a valid mask
+
+### 10. Add rounding mode and saturation function (0.56.2)
+
+In the new version, the following instructions add optional rounding mode and saturation function:
+
+- `l.add / l.sub / v.add / v.sub`: Integer addition and subtraction, only supports saturation function
+- `l.fadd / l.fsub / l.fmul / l.fdiv / v.fadd / v.fsub / v.fmul / v.fdiv`: Floating point addition, subtraction, multiplication and division
+- `l.fmadd / l.fmsub / l.fnmadd / l.fnmsub / v.fmadd / v.fmsub / v.fnmadd / v.fnmsub`: Floating point multiplication, addition, multiplication and subtraction ternary floating point instructions
+
+The rounding mode and saturation function definition and encoding methods are the same as those introduced by the Convert command above. Example:
+```assembly
+v.fadd vu#1.fh, vt#1.fh, ->vt.h, rtz, sat // 使用向零舍入，并启用饱和限制
+v.fmul vt#1.fh, vu#1.fh, ->vt.h, rtz // 使用向零舍入，不使用饱和限制
+v.fdiv vt#1.fh, vu#1.fh, ->vt.h, sat // 缺省舍入模式（由实现决定舍入规则），并启用饱和限制
+v.fsub vu#1.fs, vt#1.fs, ->vt.w // 缺省舍入模式（由实现决定舍入规则），不使用饱和限制
+```
+
+### 11. Add system register (0.56.2)
+
+The new version adds two system register, namely BLOCKNUM and BLOCKID.- **blockid** indicates which block the current execution unit is.
+- **blocknum** indicates how many blocks are executing in parallel.
+
+The two are often used together to describe block-level parallel task division.
+
+| SSR ID | Abbreviation | Name | Explanation |
+|--------|--------|-------|-------|
+| 0x0050 | BLOCKNUM | Logical core total register (Block Number) | This SSR is configured by the system controller before the kernel starts and is not expected to be modified while the kernel is running. If modifications are made while the kernel is running, consistency cannot be guaranteed. |
+| 0x0051 | BLOCKID | Logic core ID register (Block ID) | Used to uniquely identify different modules (Blocks) in the system during system debugging (System Debug) or tracing (Trace). This SSR is configured by the system controller before the kernel starts, and it is not recommended to modify it while the kernel is running. If modifications are made while the kernel is running, consistency is not guaranteed. |
+
+### 12. Add Histogram command
+
+The new version adds a THistogram instruction for histogram statistics, which is often used for byte-based radix bucketing/sorting to calculate bucket offsets. The definition is as follows:
+
+#### Description
+
+The THistogram instruction is used to perform histogram statistics by bytes on the elements of each row in the source tile, and convert the statistical results into prefix cumulative counts and write them into the dst tile. Each output row corresponds to an input valid row, the output column represents 256 possible values of a byte, 0..255, and the kth column holds the cumulative count of values 0..k.
+
+This command is commonly used in scenarios such as byte-based bucketing and radix sort staged statistics. For multi-byte elements, THistogram can choose to count one of the bytes; when counting low-order bytes, you can use idx tile to provide high-order byte prefix filtering conditions, so that the instruction only counts elements that meet the specified prefix.
+
+Function overview:
+
+- Count each valid line of src independently.
+- Iterate over the valid column elements of src for each row.
+- Extracts the specified Byte field from the element.
+- Determine whether the element participates in counting based on the Byte mode and the filter value provided by idx.
+- Perform a prefix sum on the counting results of 256 byte values.
+- Write cumulative count to dst[row, 0..255].
+
+The assembly format of THISTOGRAM is as follows:
+```assembly
+THISTOGRAM , SrcTile<.reuse>, IdxTile<.reuse>, ->DstTile
+```
+
+Among them:- `LB0`: validCol specifies the number of valid columns of the source SrcTile, that is, the number of elements participating in statistics in each valid row.
+- `LB1`: validRow specifies the number of valid rows in the source SrcTile, that is, the number of rows that independently generate a cumulative count.
+- `LB2`: Col specifies the total number of columns or tile column span of the source SrcTile. The total row count of the source SrcTile Row can be calculated from the source tile size and Col.
+- `SrcType` specifies the source element type, the current version only supports u16 or u32.
+- `DstType` specifies the output cumulative count element type, which is used to describe the storage type of the cumulative count in DstTile, supporting u8/u16/u32/u64.
+- `ByteId` specifies the target byte to be counted, which can be Byte0, Byte1, Byte2, Byte3 (only Byte0 and Byte1 are valid when u16 is input).
+- `SrcTile` is the input source tile, and .reuse means that the tile can be retained for subsequent use by subsequent instructions according to reuse semantics.
+- `IdxTile` is the index/filter tile.
+ - The idx element represents the byte value used for filtering.
+ - For uint16 + Byte0, idx[row,0] saves the high byte filter value of the row.
+ - For uint32, idx stores high-order prefix filtered values row by row:
+ - idx[0, 0]: used to filter Byte3.
+ - idx[1, 0]: used to filter Byte2.
+ - idx[2, 0]: used to filter Byte1.
+ - No filtering is required when counting Byte3, IdxTile can be used as a placeholder operand.
+- `DstTile` is the output tile, and Size represents the target size configuration of the output tile.
+
+The ByteId field is a new content, encoded in the B.DATR instruction, used to specify the target bytes extracted and counted from the SrcTile element.
+
+{ width="800" }
+
+### 13. Enhanced vector data format support
+
+In order to enhance operator compatibility and expand calculation support for BF16/FP16 and its packaging format, this version implements the following key optimizations for the vector instruction system:
+
+#### Floating point calculation instructions support bf type operands
+
+In order to natively support BF16 data operations in the vector computing unit, the source operand of the floating point instruction has a new bf type identifier, which is clearly distinguished from the existing FP16 format, for example:
+```assembly
+v.fadd vt#1.bf, vu#1.bf, ->vt.h ；两个bf16的数据相加
+v.fadd vt#1.fh, vu#1.fh, ->vt.h ；两个fp16的数据相加
+```
+Identifiers such as bf/fh are encoded in the high 3-bits of the instruction source register.
+
+{ width="800" }
+
+{ width="800" }
+
+The instructions involved are as follows:- V.FADD, V.FSUB, V.FMUL, V.FDIV, V.FMADD, V.FMSUB, V.FNMADD, V.FNMSUB
+- V.FEQ, V.FNE, V.FLT, V.FGE, V.FEQS, V.FNES, V.FLTS, V.FGES
+- V.FMAX, V.FMIN
+- V.FABS, V.FSQRT, V.FRECIP, V.FEXP, V.FCLASS
+- V.RDFADD, V.RDFMAX, V.RDFMIN
+- L.FADD, L.FSUB, L.FMUL, L.FDIV, L.FMADD, L.FMSUB, L.FNMADD, L.FNMSUB
+- L.FEQ, L.FNE, L.FLT, L.FGE, L.FEQS, L.FNES, L.FLTS, L.FGES
+- L.FABS, L.FSQRT, L.FRECIP, L.FEXP, L.FCLASS
+- L.FMAX, L.FMIN
+- L.RDFADD, L.RDFMAX, L.RDFMIN
+
+#### vector instruction adds vlen field
+
+In order to maximize the bandwidth utilization of the vector computing unit, new support for packaged data formats such as fp16x2 / bf16x2 / fp8x4 / u16x2 has been added. The original version records packaging information through the PLEN field of the PRED register (set by instructions such as v.fcvt), but there are limitations: **Data loaded directly from Tile memory or global memory (GM) cannot pass packaging format metadata**. Therefore, the new version encodes packing information into the instruction opcode:
+
+- Old mechanism: Packing information is stored in the PRED.PLEN register
+- New mechanism: packed types are explicitly declared via instruction opcodes
+
+The vector instruction adds a 2-bit VLEN field to indicate whether the data in the input register is a multi-element packed type, as follows:
+
+| vlen encoding | meaning |
+|----------|--------|
+| 0 | Each Lane contains 1 element |
+| 1 | Each Lane contains 2 elements |
+| 2 | Each Lane contains 4 elements |
+| 3 | Reserved |
+
+For example:
+```assembly
+v.fadd vt#1.bfx2, vu#1.bfx2, ->vt.w ；两个bf16x2的数据相加
+v.fsub vt#1.fhx2, vu#1.fhx2, ->vt.w ；两个fp16x2的数据相减
+v.add vm#2.shx2, vn#1.shx2, ->vt.w ；两个s16x2的数据相加
+v.fadd vt#1.fbx4, vu#1.fbx4, ->vt.w ；两个fp8x4的数据相加
+```
+
+Things to note:
+
+- The number of elements in the two source registers of an instruction must be the same, otherwise the compiler reports an illegal instruction.
+- 32bit operands (such as fs/sw/uw, etc.) do not support x2 and x4 parameters, otherwise an illegal instruction will be reported.
+- 64bit operands (such as fd/sd/ud, etc.) do not support x2 and x4 parameters, otherwise an illegal instruction will be reported.
+
+For example:
+```assembly
+v.fadd vt#1.fhx2, vt#2.fh, ->vt.w ；编译期报非法指令
+v.fadd vt#1.fdx2, vt#2.fdx2, ->vt.d ；编译期报非法指令
+```
+
+#### Format conversion command enhancement
+
+Extended format conversion instructions support for packaging data type:
+
+1. Added bf16x2 format conversion
+ - For example bf16 + bf16 -> bf16x2 packaging format
+ - For example, bf16x2 <--> fp16x2 precision migration
+2. Added e5m2x4 format conversion
+ - For example, fp16x2 + fp16x2 -> fp8(e5m2)x4 conversion
+
+#### Supplementary rounding mode and saturation calculation
+
+The following instructions in the new version add rounding mode and saturation calculation: `V.FABS` / `V.FSQRT` / `V.FRECIP` / `V.FEXP` / `L.FABS` / `L.FSQRT` / `L.FRECIP` / `L.FEXP`
+
+---
+
+## 4. Summary
+
+The LinxISA 0.56.x series has completed the continuous evolution from "resource expansion and model reconstruction" to "semantics/encoding standardization" to "low-precision mixed-precision capabilities and dedicated operator completion":1. Resource layer: 64 Tile + dynamic capacity model significantly improves resource utilization and scheduling flexibility.
+2. Instruction layer: B.IOT, TCVT, TMOV, etc. have completed semantic convergence and PTO alignment, and the coding composability has been significantly improved.
+3. Numerical layer: rounding/saturation, dtypexN, HiF micro-scaling, and mixed precision together form a more complete low-precision calculation system.
+4. System layer: BLOCKNUM/BLOCKID and subsequent algorithm TileOp (THistogram) enhance project debuggability and algorithm implementation capabilities.
+
+Overall, 0.56.x has improved the flexibility, programmability, numerical controllability and performance scalability of LinxISA in AI/tensor computing scenarios to a more mature stage, while maintaining synergy with the PTO instruction ecosystem.
\ No newline at end of file
diff --git a/docs/compiler/Calling-Convention.md b/docs/compiler/Calling-Convention.md
new file mode 100644
index 00000000..583f035a
--- /dev/null
+++ b/docs/compiler/Calling-Convention.md
@@ -0,0 +1,65 @@
+# Calling convention
+
+This chapter describes the standard calling conventions of C/C++ compilers for Linx programs.
+
+## data type aligned with
+
+The following table summarizes the data type natively supported by Linx.
+
+| C type | Description | Linx bytes |
+| -- | -- | -- |
+| char | character/byte value | 1 |
+| short | short integer | 2 |
+| int | integer | 4 |
+| long | long integer | 8 |
+| long long | long integer | 8 |
+| void* | pointer | 8 |
+| float | single precision floating point number | 4 |
+| double | double precision floating point number | 8 |
+| long double | extended precision floating point number | 16 |
+
+* char and unsigned char are 8-bit unsigned integer, which are zero-extended when stored in Linx integer registers. The unsigned short is 16-bit unsigned integer, which is also zero-extended when stored in the register.
+* signed char is 8-bit signed integer, which is sign-extended when stored in the register (that is, the high-order 63 to 7 bits are all filled with sign bits)
+* short is 16-bit signed integer, which is sign extended when stored in the register.
+* When a 32-bit type (such as int) is stored in an integer register, it will be stored as a sign extension of the 32-bit value, that is, bits 63 to 31 are the same as the sign bit. **This restriction also applies to unsigned 32-bit types**. Compilers and compliance software maintain natural alignment when storing the above data type in memory.
+
+## Calling Convention
+
+The Linx calling convention prefers passing arguments via registers, using up to 8 integer registers (a0–a7). If the function parameters are regarded as C structure fields with pointer alignment, the parameter register corresponds to the first 5 pointer words of the structure. However, the floating point fields in the union or array in the structure need to be passed through integer registers. In addition, floating-point arguments to variadic functions (other than explicitly declared arguments) are also passed through integer registers.
+
+Parameters smaller than the pointer word length are stored in the low bits of the parameter register. In little-endian memory systems, such arguments passed on the stack are aligned at the lower address of the pointer word.
+
+Basic type parameters with double pointer word length are naturally aligned when passed on the stack; when passed in an integer register, an aligned odd and even register pair needs to be occupied, and the even register stores the low bits.
+
+Parameters that exceed double pointer word length are passed by reference. The parameters that are not passed through registers are passed through the stack, and the stack pointer sp points to the first parameter that is not passed through registers.
+
+The function return value passes through the integer registers a0 and a1. Other values up to two pointer words are returned through a0 and a1. Larger return values are passed through memory: the caller allocates memory and passes the pointer through the implicit first parameter.
+
+In the standard Linx calling convention, the stack grows downward and the stack pointer always remains 16-byte aligned.
+
+In addition to the parameter and return value registers, the three integer registers x0–x3 may become invalid after the call and need to be saved by the caller; the eight integer registers s0–s7 are reserved registers and need to be saved by the callee. The following table details the calling convention roles of registers.| Register | ABI Name | Description |
+| ------- | ----------- | ----------------------- |
+| r0 | zero | zero register |
+| r1 | sp | stack pointer register |
+| r2 | a0 | function parameter 0 |
+| r3 | a1 | function parameter 1 |
+| r4 | a2 | function parameter 2 |
+| r5 | a3 | function parameter 3 |
+| r6 | a4 | function parameter 4 |
+| r7 | a5 | function parameter 5 |
+| r8 | a6 | function parameter 6 |
+| r9 | a7 | Function parameter 7 |
+| r10 | ra | Return address register |
+| r11 | fp(s0) | Frame register/sub-function register 0 |
+| r12 | s1 | Sub-function register 1 |
+| r13 | s2 | Sub-function register 2 |
+| r14 | s3 | Sub-function register 3 |
+| r15 | s4 | Sub-function register 4 |
+| r16 | s5 | Sub-function register 5 |
+| r17 | s6 | Sub-function register 6 |
+| r18 | s7 | Subfunction register 7 |
+| r19 | s8 | Subfunction register 8 |
+| r20 | x0 | The parent function saves other registers 0 |
+| r21 | x1 | The parent function saves other registers 1 |
+| r22 | x2 | The parent function saves other registers 2 |
+| r23 | x3 | The parent function saves other registers 3 |
\ No newline at end of file
diff --git a/docs/compiler/assembly_manual/Architecture_Register.md b/docs/compiler/assembly_manual/Architecture_Register.md
new file mode 100644
index 00000000..655e5a6a
--- /dev/null
+++ b/docs/compiler/assembly_manual/Architecture_Register.md
@@ -0,0 +1 @@
+详见[架构寄存器](../../isa/register/common/intro.md)
diff --git a/docs/compiler/assembly_manual/Assemble_syntax.md b/docs/compiler/assembly_manual/Assemble_syntax.md
new file mode 100644
index 00000000..9b8bc363
--- /dev/null
+++ b/docs/compiler/assembly_manual/Assemble_syntax.md
@@ -0,0 +1,25 @@
+The LinxISA assembler source file consists of a series of assembly statements, one statement per line. Each line of statement has three optional parts, in the following order:
+
+```
+标签: 指令 /* 注释 */
+
+```
+
+**Tag** identifies the address of this instruction and is then used as the target for branch instructions or load and store instructions. **Instructions** can be LinxISA assembly instructions or assembler built-in instructions (the assembler built-in instructions are pseudo-instructions used to tell the assembler itself to perform segment alignment or create data, see the assembler built-in instructions section below for details). Use "/*" and "*/" as comment separators.
+
+As shown in the following block assembly statement:
+
+```
+.Ltmp0: /* 标签 */
+...
+BSTART.STD COND, .Ltmp0 /* 指令 */
+addi zero,32, ->t
+sll t#1, a0, ->t
+sra t#1,t#2, ->u
+addi zero,32, ->t
+sll u#1, t#1, ->t
+srli t#1,30, ->u
+1: addi a1,4,->a3 /* 数字标签 + 指令 */
+...
+BSTOP
+```
\ No newline at end of file
diff --git a/docs/compiler/assembly_manual/BlockISA_assemble_difference.md b/docs/compiler/assembly_manual/BlockISA_assemble_difference.md
new file mode 100644
index 00000000..8459895c
--- /dev/null
+++ b/docs/compiler/assembly_manual/BlockISA_assemble_difference.md
@@ -0,0 +1,45 @@
+Linx Instruction Set Architectureblock instruction is a two-layer architecture, consisting of header and optional microinstructions (see example (1) below). For other architectures, usually one assembly statement corresponds to one instruction, see example (2) below.
+
+(1)*LinxISA compilation*
+
+The attributes of the current block instruction (type, jump type, input, output, microinstruction storage address, etc.) are expressed through the pseudo-instruction sequence of header. There are two block instruction assembly layouts of LinxISA:
+
+- Integrated block or template block: When block instruction has specific calculations, the body instructions are arranged immediately after header instruction.
+
+```
+BSTART.STD FALL
+addi zero,32,->t
+sll t#1, a0,->t
+sra t#1,t#2,->t
+addi zero,32,->t
+sll t#2, t#1,->t
+srli t#1,30,->a3
+MCOPY [a0,a1,a2]
+BSTART.STD FALL
+...
+```
+
+- Separate block: When there is a specific calculation for block instruction, use the *B.TEXT* instruction to specify the starting address of the body instruction, and use *bstop* to indicate the end position of the body instruction. The separation block provides greater freedom in the arrangement of body.
+```
+BSTART.STD FALL
+B.TEXT .Ltmp0.bstart
+BSTART.STD FALL
+...
+
+.Ltmp0.bstart:
+addi zero,32,->t
+sll t#1, a0,->t
+sra t#1,t#2,->t
+addi zero,32,->t
+sll t#2, t#1,->t
+srli t#1,30,->a3
+bstop
+```
+
+(2) *Other architecture compilation*
+
+```
+x86: add eax, #100
+68K: ADD #100, D0
+ARM: add r0, r0, 100
+```
\ No newline at end of file
diff --git a/docs/compiler/assembly_manual/Compressed_Instruction.md b/docs/compiler/assembly_manual/Compressed_Instruction.md
new file mode 100644
index 00000000..7af637b3
--- /dev/null
+++ b/docs/compiler/assembly_manual/Compressed_Instruction.md
@@ -0,0 +1,13 @@
+# Compression instructions
+
+Compressed instructions are public microinstructions, which help optimize code density and cover some functions of 32-bit public microinstructions. All compressed microinstructions start with 'c.'. For a detailed list of compressed microinstructions, please refer to the chapter [Compressed Instructions] (https://openx.huawei.com/mkdocs/project/1410/blockisa-doc/docs/site/docs/isa/blockIntro/common/compress/) in the manual.
+
+- Programmers can handwrite compression instructions on demand.
+- Enable the compiler's compression instruction function, which can automatically optimize optimizable assembly into compression instructions. This function is currently enabled by default in the compiler.
+
+## Assembly example:
+
+```
+c.add t#1, t#2, ->t /*两个块内寄存器相加写到t标度尺寄存器上*/
+c.lwi [t#1, 4], ->u /*从地址为t#1+4的内存中加载一个字的数据到u标度尺寄存器上*/
+```
\ No newline at end of file
diff --git a/docs/compiler/assembly_manual/Conditional_execution.md b/docs/compiler/assembly_manual/Conditional_execution.md
new file mode 100644
index 00000000..292dbd73
--- /dev/null
+++ b/docs/compiler/assembly_manual/Conditional_execution.md
@@ -0,0 +1,25 @@
+# Status flags and conditional execution
+
+Microinstructions of the 'setc' class are used to modify the CARG register. When block instruction is submitted, the corresponding path is executed based on the jump type of block instruction and the value in the CARG register. When the jump of block instruction is 'COND', 'IND', or 'ICALL', body needs to use the 'setc' microinstruction.
+
+For example, you want to make a block jump to another block when a condition is met, and fall through to the next block if the condition is not met. The jump type and jump target address should be specified in header, which can be expressed with the 'BSTART. COND, label' pseudo-instruction, and the 'setc' instruction of the conditional class is added to the body microinstruction to set the conditional state. For details of the CARG register, see [CARG register] (https://openx.huawei.com/mkdocs/project/1410/blockisa-doc/docs/site/docs/isa/register/common/bstate_com/?h=carg#carg). Examples are given below:
+
+```
+ ...
+.Lblock1:
+ BSTART COND, .Lblock2
+ 微指令
+ setc.eq t#1, zero
+ BSTART IND
+ 微指令
+ setc.tgt t#1
+ ...
+ BSTART ICALL
+ 微指令
+ addpc t#1,4,->ra
+.Lblock2:
+ BSTART
+ ...
+ BSTOP
+ ...
+```
\ No newline at end of file
diff --git a/docs/compiler/assembly_manual/Constant_Immediate_Value.md b/docs/compiler/assembly_manual/Constant_Immediate_Value.md
new file mode 100644
index 00000000..38c5e887
--- /dev/null
+++ b/docs/compiler/assembly_manual/Constant_Immediate_Value.md
@@ -0,0 +1,74 @@
+# Constant values and immediate values
+
+The encoding length of the microinstruction of LinxISA is 16/32/48/64bit. In LinxISA, 32-bit constant values and immediate values are split into high 20-bit and low 12-bit parts. These constant values and immediate values can be encoded into opcodes, or 64-bit instructions can be used to load the immediate values. If it is a value with a larger bit width, it is necessary to further combine the ALU instructions for data splicing. The following mainly introduces the instruction expressions for 32/64bit constants and immediate numbers.
+
+Use the lui or addtpc instruction to encode the higher 20-bit value, and the addi or subi instruction to encode the lower 12-bit value. Use constant value and immediate value operations to tell the assembly to obtain the corresponding value.
+
+Immediate number:
+
+```
+if (0 <= imm <= 4095)
+ addi zero,imm, ->t
+else if (-4095 <= imm < 0)
+ subi zero,-imm, ->t
+else if (isInt<32>(imm))
+ lui (imm & 0xffffff000), ->t
+ addi t#1,(imm & 0x00000fff), ->t
+ /* 或者使用一条64bit指令 */
+ l.addli zero,imm, ->t
+else
+ subi zero, 1, ->t /* 需要进行立即数拼接，如表达0xffffffff */
+ zext.w t#1, ->t
+```
+
+For example, to assign a value of 0x3fa80 to the T register, you need to write:
+
+```
+lui 0x3f, ->t
+addi t#1,0xa80, ->t
+```
+Or use the value operation of constant value and immediate number to obtain the high 20 bits and low 12 bits of the immediate number.
+
+```
+lui %hi(0x3fa80), ->t
+addi t#1,%lo(0x3fa80), ->t
+```
+
+Constant value: The address of a variable cannot be determined during assembly programming, but it can be determined when the final binary is generated, and this part of the address is encoded in the instruction opcode and will not change, so it is called a constant value.
+
+```
+if (使用符号绝对地址)
+ lui %hi(symbol), ->t
+ addi t#1,%lo(symbol), ->t
+else if (使用符号相对当前TPC的相对地址)
+ if (相对地址isInt<32>)
+ label:
+ addtpc %tpcrel_hi(symbol), ->t /* 获得symbol的地址相对于当前微指令tpc的偏移值，高20位编码 */
+ addi t#1,%tpcrel_lo(label), ->t /* 获得symbol的地址相对于微指令addtpc的地址（等于标签label的地址）的偏移值，低12位编码 */
+ else
+ label:
+ addtpc %got_tpcrel_hi(symbol), ->t /* 获得symbol的GOT表的地址相对于当前微指令tpc的偏移值，高20位编码 */
+ addi t#1, %tpcrel_lo(label), ->t /* 获得symbol的GOT表的地址相对于微指令addtpc的地址（等于标签label的地址）的偏移值，低12位编码 */
+else if (对于线程Local的变量，使用符号相对于TP（线程寄存器）的相对地址)
+ if（TLS变量的访问,当前仅支持Local Exec的模式）
+ lui %tprel_hi(symbol), ->t
+ ssrget 0x0010, ->t
+ add t#1,t#2, ->t
+ addi t#1, %tprel_lo(symbol), ->t
+else if (对于全局变量，使用符号相对于GP(全局寄存器)的相对地址)
+ if (全局变量的访问)
+ lui %gprel_hi(symbol), ->t
+ ssrget 0x0011, ->t
+ add t#1, t#2, ->t
+ addi t#1, %gprel_lo(symbol), ->t
+```
+
+For example, if I want to access a TLS variable errno, I need to first get the relative address of the errno variable to TP (thread register)
+
+```
+lui %tprel_hi(errno), ->t /* 获得errno相对TP寄存器的偏移值 */
+ssrget 0x0010, ->t /* 获得tpZXTERMZH6QXZ的值 */
+add t#1,t#2, ->t /* TP + OFFSET */
+addi t#1,%tprel_lo(errno), ->t /* 获得errno相对TP寄存器的偏移值的低12位， 最终的结果为 TP + OFFSET */
+
+```
\ No newline at end of file
diff --git a/docs/compiler/assembly_manual/Function_alignment.md b/docs/compiler/assembly_manual/Function_alignment.md
new file mode 100644
index 00000000..e3e4f9ef
--- /dev/null
+++ b/docs/compiler/assembly_manual/Function_alignment.md
@@ -0,0 +1,89 @@
+The assembly file is compiled and encoded to generate a binary object file, and the required binary object files are linked to generate the final binary executable file.
+
+The simplest link command is as follows:
+```
+ld.lld tmp.o -o tmp.out
+```
+Or use the clang command directly:
+```
+clang --target=linx64v4-linux-musl tmp.o -o tmp.out
+```
+
+Use the default linker script and do not link any libraries or start functions. For linker usage, please refer to: https://lld.llvm.org/.
+
+## How the segments in the assembly file affect the layout of the final binary content
+
+From the above discussion, in the same assembly file, the contents in the same segment are spatially continuous in the final generated binary (binary is used to represent the binary executable file in the following text). The arrangement of sections with different names in the same assembly file and sections in different assembly files is determined by the link order and link script.
+
+Sections with different names in the same assembly file:
+
+- When the position of the section is not specified in the linker script, it will be sorted according to the lexicographic order of the section name
+- When the order of specific sections of a specific file is specified in the linker script, the specified sections are arranged in the order specified by the linker script
+
+Segments in different assembly files:
+
+- When the order of specific sections of a specific file is not specified in the linker script (the current default linker script), the order in which sections in different assembly files are arranged in the binary follows the linker order. In the link command, one file is written before another file, which will be placed at the front position in the binary
+- Specify the order of specific sections of a specific file in the link script, and the specified sections are arranged in the order specified by the link script
+
+
+Therefore, for LinxISA, the currently supported integrated blocks and separated blocks have different binary arrangement requirements:
+- For one-piece blocks, there is no additional arrangement operation for header and body
+- For separate blocks, if you want to change the arrangement of header and microinstruction content in the binary, you need to:
+ 1. Distinguish segments in the assembly file as needed.
+ 2. Change the linker script to arrange the segments as needed.
+
+
+The following introduces three binary arrangement schemes in the form of separated blocks.
+### Scheme 1 (ELF arrangement): header in the entire binary is in a continuous area, and the microinstructions are in another continuous area.
+
+- In all assembly files, place header in section A and microinstructions in section B.
+- In the linker script, place section A in the output section A-OUT and section B in the output section B-OUT.
+
+Features: Different sections of the same file are not continuous, but sections of the same name in different files are continuous and arranged according to the link script. The distance between header is the smallest, and the distance between header microinstructions is the largest.
+
+### Option 2 (.o arrangement): header and the microinstructions in the same assembly file are in a continuous area, and header and the microinstructions in another assembly file are in another continuous area.
+
+- In the assembly file, put header in section A and the microinstructions in section B.
+- In the link script, the A and B sections in the same assembly file are placed in the same output section AB-OUT in order.
+
+Features: Different segments of the same file are continuous, and different files are arranged in link order. The distance between header inside the file is small, and the distance between header microinstructions is small.
+
+### Option 3 (Function Arrangement): The header and microinstructions of the same function are in a continuous area, and the header and microinstructions of another function are in another continuous area.
+
+- Place the header of function A in section A, and the microinstructions of function A in section A.body. Place the header of function B in section B, and the microinstructions of function B in section B.body. Other functions follow the same rules and so on.
+- In the link script, place the sections in the same output section AB-OUT in the order of A, A.body, B, B.body.
+
+Features: Different sections of the same file are arranged according to the order in the link script, and different files are arranged according to the link order. header microinstructions are the smallest apart.
+
+The comparison between different solutions is shown in the table below:
| Scheme | header distance between files | header distance within files | header distance within functions | header distance between microinstructions |
+| ---------- | ---------- | ---------- | ---------- | ---------- |
+| Option 1 | Minimum | Minimum | Equal | Maximum |
+| Option 2 | Maximum | Minimum | Equal | Less than Option 1, Greater than Option 3 |
+| Option 3 | Greater than Option 1, less than Option 2 | Maximum | Equal | Minimum |
+
+
+The syntax of link scripts is not explained in detail in this article. Please refer to https://ftp.gnu.org/old-gnu/Manuals/ld-2.9.1/html_chapter/ld_3.html
+
+### Function Alignment
+
+Linx Instruction Set Architecture defines header and body. In order to support the alternate arrangement of header and body at the plan three function or plan two file level during the link stage, the assembly needs to ensure that the start of each function is 8byte aligned. The ‘.align 3’ alignment command needs to be added before each header.
+
+header：
+```
+.section .text
+.align 3 //保证main函数的header是8B对齐
+main：
+ BSTART.SIMT FALL
+ B.TEXT main.bstart
+ BSTOP
+```
+
+Microinstructions:
+
+```
+.section .text.body
+main.bstart:
+ addi zero,0, ->t
+ ...
+ lbstop
+```
\ No newline at end of file
diff --git a/docs/compiler/assembly_manual/Inline_Assembly.md b/docs/compiler/assembly_manual/Inline_Assembly.md
new file mode 100644
index 00000000..28e1a292
--- /dev/null
+++ b/docs/compiler/assembly_manual/Inline_Assembly.md
@@ -0,0 +1,75 @@
+# Inline assembly
+In general, clang is highly compatible with GCC's inline assembly extensions, allowing the same constraints, modifiers, and operands as GCC's inline assembly. This section mainly introduces the common writing methods of inline assembly based on LinxISA. Generic inline assembly format:
+
+```
+ asm [ volatile ] (
+ 汇编序列
+ [ : 输出操作数 ] /* 可选 */
+ [ : 输入操作数 ] /* 可选 */
+ [ : list of clobbered registers ] /* 可选 */
+ );
+```
+
+The basic format mainly includes four parts, which must contain assembly sequences, and other parts are optional. The assembly diagram is as follows:
+
+```
+void foo(void)
+{
+ int output, val1, val2;
+ ...
+ asm volatile ("BSTART\n"
+ "sub %1, %2, ->t\n"
+ "add a1, t#1, ->%0\n"
+ "BSTOP\n"
+ :"=r"(output):"r"(val1),"r"(val2):);
+ ...
+ return;
+}
+```
+
+'volatile' is an optional keyword, indicating that the compiler does not require any optimization of the following assembly code. The keyword also supports the writing methods of '__asm__' and '__volatile__'. The following table shows the operand type description and modification of the output operand:
+
+| Operand constraints | Description |
+|------------|--------------------------|
+| r | Operand of register type |
+| i | Operand of immediate type |
+| m | Operand of memory type |
+
+
+| Modification Constraints | Description |
+|------------|--------------------------|
+| = | Output operand (write only) |
+| + | Input/output operands (read and write) |
+
+# Parallel block inline assembly
+Supports writing single-instruction parallel block inline assembly. The purpose is to facilitate support for fp8 type conversion, so that it can be supported by just modifying the library.
+
+Input:
+
+```c
+void __vec__ foo(...) {
+ asm volatile ("l.fcvt %1.fd, ->%0.fb" : "=vr"(to) : "vr"(from));
+ p[...] = to;
+}
+```
+
+Output:
+
+```s
+foo:
+ l.fcvt vt#1.fd, ->vt.fb
+ l.sb vt#1.sb, [...]
+```
+
+**Constraints:** Only a single microinstruction is supported. If multiple microinstructions are written, the backend will have an error when calculating the register index.
+
+---
+
+Inline assembly error reporting rules:
+
+1. Standard block: Inline assembly starting with scalarBSTART or template block. No special checks are performed for the time being, and you can write casually.
+2. Tile instruction: Inline assembly starting with Tile pseudo-instruction or BSTART.PAR. Only block modification instructions are received. When encountering microinstructions or non-block modification instructions such as the new header, an error will be reported directly.
+3. Parallel block instruction multiple instructions: Start with a microinstruction. If there are multiple microinstructions, they must end with bstop. Used to hand-write complete parallel block function bodies through inline assembly
+4. Parallel block instruction single instruction: only one microinstruction
+5. Escape: The error reporting rules may be expanded or changed in the future. First provide the `.unsafeasm` directive to ensure that these rules can be bypassed.
+> If you have any questions about parallel block inline assembly, please contact Mou Liangyu 30030301
\ No newline at end of file
diff --git a/docs/compiler/assembly_manual/Introduct_BlockISA_assemble_tool.md b/docs/compiler/assembly_manual/Introduct_BlockISA_assemble_tool.md
new file mode 100644
index 00000000..19c90a3d
--- /dev/null
+++ b/docs/compiler/assembly_manual/Introduct_BlockISA_assemble_tool.md
@@ -0,0 +1,18 @@
+# Introduction to assembly link tools
+
+The LLVM built-in assembler is a member of the LLVM tool component and its function is to convert assembly files into binary object files. Regarding the use of clang, please see: [https://clang.llvm.org/](https://clang.llvm.org/)
+
+The LinxISA assembler is implemented by enabling the built-in assembler of Linx-LLVM and supports the common functions of the LLVM built-in assembler. Therefore, in the following description, the use of the Linx instruction set will be focused on.
+
+## Use LinxISA assembler
+
+You can directly use the clang tool to assemble the LinxISA assembly file.
+
+```
+clang --target=linx64v5-linux-musl -c tmp.S -o tmp.o
+```
+
+When all source files have been assembled into binary object files (files with a .o suffix), the GNU linker can be used to generate the final executable file (default is ELF format).
+```
+clang --target=linx64v5-linux-musl tmp.o -o tmp.out
+```
\ No newline at end of file
diff --git a/docs/compiler/assembly_manual/Introduction.md b/docs/compiler/assembly_manual/Introduction.md
new file mode 100644
index 00000000..2ca8c20d
--- /dev/null
+++ b/docs/compiler/assembly_manual/Introduction.md
@@ -0,0 +1,2 @@
+# Introduction
+This article describes some syntax and options related to the assembler and linker implemented based on llvm's built-in assembly link tool under Linx Instruction Set Architecture, so that users can better handwrite assembly or use the assembler and linker.
\ No newline at end of file
diff --git a/docs/compiler/assembly_manual/Introduction_assemble_language.md b/docs/compiler/assembly_manual/Introduction_assemble_language.md
new file mode 100644
index 00000000..ee93562a
--- /dev/null
+++ b/docs/compiler/assembly_manual/Introduction_assemble_language.md
@@ -0,0 +1 @@
+Assembly language is a low-level programming language, and its statements usually have a one-to-one correspondence with the instructions actually executed by the hardware. Programmers who develop applications usually do not need to pay attention to the underlying assembly language, but in some specific situations, programmers need to use assembly language for development, such as when we need to pursue ultimate performance and develop certain Driver or OS functions that cannot be expressed in C language. In addition, understanding assembly language can help us quickly locate problems in the program.
\ No newline at end of file
diff --git a/docs/compiler/assembly_manual/Micro-Instruction.md b/docs/compiler/assembly_manual/Micro-Instruction.md
new file mode 100644
index 00000000..d917caae
--- /dev/null
+++ b/docs/compiler/assembly_manual/Micro-Instruction.md
@@ -0,0 +1,103 @@
+# microinstructions
+In the architectural definition of LinxISA, block instruction and body are composed of a series of microinstructions to complete specific computing tasks. The assembly instructions of microinstructions may be as shown below.
+
+```
+Opcode
+Opcode Operand0
+Opcode Operand0,Operand1
+Opcode Operand0,Operand1,Operand2
+Opcode Operand0,->{UL_GPR, LL_GPR}
+Opcode Operand0,Operand1,->{UL_GPR, LL_GPR}
+Opcode Operand0,Operand1,Operand2,->{UL_GPR, LL_GPR}
+```
+
+1. Microinstructions may have input and output calculation results during specific calculations. When writing Operand operation objects, the order is first the left source operation object, the right source operation object, and then output. In the following text, Operand0 is the left source operation object, and Operand1 is the right source operation object.
+2. The input of the microinstruction may be a register, a label, or an immediate value. If the input is a register, it may be LL_GPR or UL_GPR. It supports using zero to represent a register operand whose value is always 0. For system register, for example, to access ebstatep (architectural state base address register), tp (thread private variable base address register), gp (static global variable base address register), etc., use system registerID for microinstruction access. The specific register operand names can be found in the chapter [Architecture and Registers] (./Architecture_Register.md), and the ID list of system register can be found in the chapter [system register] (../../isa/register/ssr/ssrintro.md).
+3. The microinstruction may have no output. If there is output, it can only be a register, which may be output to {UL_GPR, LL_GPR}
+
+ - Adding `->` indicates that the microinstruction has output, which can be output to UL_GPR or LL_GPR
+ - Output to the zero register, the instruction execution result has no effect.
+ - The default indicates no output.
+
+The following table lists the input and output formats of register operands:| Input register operand | Output register operand |
+|--------------------|-----------------------|
+| r0 or zero | r0 or zero |
+| r1 or sp | r1 or sp |
+| r2 or a0 | r2 or a0 |
+| r3 or a1 | r3 or a1 |
+| r4 or a2 | r4 or a2 |
+| r5 or a3 | r5 or a3 |
+| r6 or a4 | r6 or a4 |
+| r7 or a5 | r7 or a5 |
+| r8 or a6 | r8 or a6 |
+| r9 or a7 | r9 or a7 |
+| r10 or ra | r10 or ra |
+| r11 or fp(s0) | r11 or fp(s0) |
+| r12 or s1 | r12 or s1 |
+| r13 or s2 | r13 or s2 |
+| r14 or s3 | r14 or s3 |
+| r15 or s4 | r15 or s4 |
+| r16 or s5 | r16 or s5 |
+| r17 or s6 | r17 or s6 |
+| r18 or s7 | r18 or s7 |
+| r19 or s8 | r19 or s8 |
+| r20 or x0 | r20 or x0 |
+| r21 or x1 | r21 or x1 |
+| r22 or x2 | r22 or x2 |
+| r23 or x3 | r23 or x3 |
+| t#1~t#4 | t |
+| u#1~u#4 | u |
+| LB0~LB2 | LB0~LB2 |
+| LC0~LC2 | LC0~LC2 |
+
+**Note**:
+
+For LB0~LB2, LC0~LC2 these system register
+
+- Non-PAR blocks require ssrget/ssrset to access.
+- In the PAR block, it can be directly accessed using the private microinstructions of the SIMT block.
+- The current version of microinstructions does not support multiple outputs.
+
+## Microinstruction output specifications:
+
+ - The Opcode of the microinstruction determines whether the microinstruction has output
+ - The output part of the microinstruction with output cannot be left out by default, otherwise the assembler will report an instruction format error.
+
+## Opcode identification
+For the identification of Opcode, first determine the block type where it is located, and then expand the Opcode to distinguish different instructions, floating point instructions of different precisions, and different operations of atomic instructions, etc.- Adding `w`:Opcode{w} after Opcode indicates low 32bit signed extension
+- Add `u`:Opcode{u} after Opcode to indicate unsigned operation
+- Adding `i`:Opcode{i} after Opcode indicates that the right source operation object is an immediate number
+- Add `{.eq, .ne, .lt, .ge, .ltu, .geu, .and, .or}` after Opcode: Opcode{.eq, .ne, .lt, .ge, .ltu, .geu, .and, .or} to indicate the conditions for the judgment to be established. `.eq` means that if they are equal, the judgment will be true. `.ne` means that if they are not equal, the judgment will be true. `.lt` means that if the signed left source is smaller than the signed right source, then the condition will be true. `ge` means that the condition is true if the signed left source is greater than the signed right source. Adding `u` to `.lt` and `.ge` indicates unsigned comparison, `.and` and `.or` respectively indicate logical AND and logical OR, and `i` indicates that the right source operation object is an immediate comparison
+- Adding `c.`:c.Opcode in front of Opcode indicates that the instruction is a compressed instruction, and the encoding length is 16 bits
+- Floating point precision: Opcode{.fd, .fs, .fh, fb}, `.fd` represents 64bit double precision floating point type, `.fs` represents 32bit single precision floating point type, `.fh` represents the 16-bit half-precision floating point type, and `.fb` represents the 8-bit low-precision floating-point type, which is limited to floating-point instructions
+- Atomic operations: Opcode{.aq, .rl, .aqrl}, `.aq` represents Acquire, `.rl` represents Release, `.aqrl` represents AcquireRelease, only atomic instructions
+
+## Operand operation
+Supports operations such as Operand's shifting, address calculation, address fetching, arithmetic operations, logical operations, etc.
+
+- When the type of Operand is a register, the following operations are supported:
+ - Arithmetic operation `Operand{.sw, .uw, .neg}` can only be performed on registers. `sw` means intercepting the lower 32 bits of the operand and doing signed extension. `uw` means intercepting the lower 32 bits of the operand and doing unsigned extension. `neg` means inverting the operand and adding 1.
+ - The logical operation `Operand{.sw, .uw, .not}` can only be performed on the register. `.not` means inverting the operand.
+ - Shift operation: `Operand1<- When the Operand is an immediate value and a label, it can support constant value and immediate value acquisition operations. It is limited to integer calculation instructions, memory access instructions, and constant instructions:
+ - Use absolute values: `%hi(表达式)` means to get the high 20 bits of the expression calculation result, `%lo(表达式)` means to get the low 12 bits of the expression calculation result.
+ - Use relative TPC values: `%tpcrel_hi(symbol)` means to get the symbol address relative to the high 20 bits of the current TPC, `%got_tpcrel_hi(symbol)` means to get the symbol address in the GOT table relative to the high 20 bits of the current TPC, `%tpcrel_lo(label)` needs to get the high symbol address relative to the low 12 bits of the label address.
+ - Use the value relative to the Thread Pointer: `%tprel_hi` means to obtain the high 20 bits of the TLS variable relative to the Thead Pointer register, and `%tprel_lo` means to obtain the low 12 bits of the TLS variable relative to the Thead Pointer register.
+ - Use the value relative to the Global Pointer: `%gprel_hi` means to obtain the high 20 bits of the global variable relative to the Global Pointer register, and `gprel_lo` means to obtain the low 12 bits of the global variable relative to the Global Pointer register.
+
+- Address calculation operation: `[Operand0]` or `[Operand0,Operand1]`, address calculation can only be performed on registers or immediate numbers Operand. Operand0 is a register and Operand1 can be a register or immediate number. For details, see memory access instructions
+
+Multiple operations can be performed on the same Operand, such as `[Operand1, Operand2.sw<
+
+## Operand extension design of register type
+The register type Operand is designed to add a bit width indication. The purpose is to give hardware prompts to improve the utilization of register resources in the SIMT block. How to use it:
+
+- Output operand identification: Operand{.b, .h, .w, .d}, `.b, .h, .w, .d` indicates that the register operand width is 8bit, 16bit, 32bit, 64bit respectively. This extension design can be used in conjunction with other basic operations of Operand, such as shifting, which are determined according to specific instructions.
+- Input operand identifier: Operand{.fd, .fs, .fh, .fb, .bf, .flb, .d, .uw, .uh, .ub, .sw, .sh, .sb}, where `.fd, .fs, .fh, .fb, .bf, .flb` is used to indicate the floating point type of the register operand type and the corresponding bit width, and `.d, .uw, .uh, .ub, .sw, .sh, .sb` is used to indicate that the register operand is an integer type and the corresponding bit width.
+
+
+## Use of body microinstructions
+body microinstructions are divided into two categories: public microinstructions and private microinstructions. Normally, the body microinstructions of block instruction are composed of public microinstructions and some private microinstructions.
+
+- Public microinstructions: Indicates that all types of block instruction can be used. For specific microinstructions, please refer to the chapter [Basic Instruction Set] (https://openx.huawei.com/mkdocs/project/1410/blockisa-doc/docs/site/docs/isa/instset/baseInstrs/)
+- Private microinstructions: Indicates that only the corresponding type of block instruction can be used. For specific microinstructions, please refer to [scalarblock instruction Set] (https://openx.huawei.com/mkdocs/project/1410/blockisa-doc/docs/site/docs/isa/blockIntro/std_block/intro/), [System ZXTERM ZH32QXZ set] (https://openx.huawei.com/mkdocs/project/1410/blockisa-doc/docs/site/docs/isa/blockIntro/sys_block/intro/), [Floating point block instruction set] (https://openx.huawei.com/mkdocs/project/1410/blockisa-doc/docs/site/docs/isa/blockIntro/fp_block/intro/), [Parallel block instruction set] (https://openx.huawei.com/mkdocs/project/1410/blockisa-doc/docs/site/docs/isa/blockIntro/simt_block/intro/).
+- The body microinstructions of the parallel block are all composed of private microinstructions.
\ No newline at end of file
diff --git a/docs/compiler/assembly_manual/Micro-assemble-instruction.md b/docs/compiler/assembly_manual/Micro-assemble-instruction.md
new file mode 100644
index 00000000..3e2e3aae
--- /dev/null
+++ b/docs/compiler/assembly_manual/Micro-assemble-instruction.md
@@ -0,0 +1,11 @@
+# Microinstruction assembly instructions
+
+For the assembly syntax of microinstructions, please see: [LinxISA Manual] (https://openx.huawei.com/mkdocs/project/1410/blockisa-doc/docs/site/docs/). The following is a detailed description based on public microinstructions and private microinstructions: public microinstructions refer to those that can be used in all basic block type, and private microinstructions refer to those that can only be used in the corresponding block type.
+
+**Note**: In the description of microinstruction assembly syntax
+
+- SrcL represents the left source operation object, the syntax type is a register, which may be either LL_GPR or UL_GPR
+- SrcR represents the right source operation object, the syntax type is a register, which may be either LL_GPR or UL_GPR
+- shamt represents the offset value, and the syntax type is immediate.
+- simm represents signed immediate value, and the syntax type is expression (immediate value or label)
+- uimm represents unsigned immediate value, and the syntax type is expression (immediate value or label)
\ No newline at end of file
diff --git a/docs/compiler/assembly_manual/PC_value.md b/docs/compiler/assembly_manual/PC_value.md
new file mode 100644
index 00000000..7d789132
--- /dev/null
+++ b/docs/compiler/assembly_manual/PC_value.md
@@ -0,0 +1,29 @@
+# PC calculation instructions
+
+```
+Opcode Operand0,->{LL_GPR, UL_GPR} /* 输出到LL_GPR或者是UL_GPR */
+```
+
+- When calculating TPC, the operation object Operand0 is an immediate number, which supports the value operation of constant values and immediate numbers. Obtain the relative TPC value: '%tpcrel_hi(symbol)' means to obtain the symbol address that is 20 bits higher than the current TPC, and '%got_tpcrel_hi(symbol)' means to obtain the symbol's entry address in the GOT table that is 20 bits higher than the current TPC
+- For blocks with a jump type of 'call', the 'addpc' instruction needs to be added to body to update ra to indicate the return address of 'call'
+
+For specific microinstruction descriptions, please refer to the chapter [PC Computing Instructions] (https://openx.huawei.com/mkdocs/project/1410/blockisa-doc/docs/site/docs/isa/blockIntro/common/pc_arithmetic/).
+
+Assembly instructions
+
+(0)
+
+```
+addtpc %tpcrel_hi(symbol),->t /* 获得symbol的地址相对于当前微指令tpc的偏移值，高20位编码 */
+```
+
+(1)
+
+```
+addtpc %got_tpcrel_hi(symbol),->t /* 获得symbol的GOT表的地址相对于当前微指令tpc的偏移值，高20位编码 */
+```
+
+(2)
+```
+addpc 4, ->ra /* 当前微指令的tpc+4写到ra寄存器中*/
+```
\ No newline at end of file
diff --git a/docs/compiler/assembly_manual/Pseudo_instruction.md b/docs/compiler/assembly_manual/Pseudo_instruction.md
new file mode 100644
index 00000000..9274b9b2
--- /dev/null
+++ b/docs/compiler/assembly_manual/Pseudo_instruction.md
@@ -0,0 +1,40 @@
+# 汇编器内置指令
+
+汇编器提供一系列的架构无关的指令来以方便操作，所有的汇编器内置的指令都以'.'开头。 完整的列表请见GNU文档，下表中是部分常用的汇编器内置指令。
+
+| Directive | Arguments | Description |
+|--|--|--|
+| .align |integer |align to power of 2 (alias for .p2align)|
+| .file |"filename" |emit filename FILE LOCAL symbol table|
+| .globl |symbol_name |emit symbol_name to symbol table (scope GLOBAL)|
+| .local |symbol_name |emit symbol_name to symbol table (scope LOCAL)|
+| .comm |symbol_name,size,align |emit common object to .bss section|
+| .common |symbol_name,size,align |emit common object to .bss section|
+| .ident |"string" |accepted for source compatibility|
+| .section |[{.text,.data,.rodata,.bss}] |emit section (if not present, default .text) and make current|
+| .size |symbol, symbol |accepted for source compatibility|
+| .text ||emit .text section (if not present) and make current|
+| .data ||emit .data section (if not present) and make current|
+| .rodata ||emit .rodata section (if not present) and make current|
+| .bss ||emit .bss section (if not present) and make current|
+| .string |"string" |emit string|
+| .asciz |"string" |emit string (alias for .string)|
+| .equ |name, value |constant definition|
+| .macro |name arg1 [, argn] |begin macro definition \argname to substitute|
+| .endm ||end macro definition|
+| .type |symbol, @function |accepted for source compatibility|
+| .option |{relax,norelax,push,pop} |Refer to .option for a more detailed description.|
+| .byte |expression [, expression]* |8-bit comma separated words|
+| .2byte |expression [, expression]* |16-bit comma separated words|
+| .half |expression [, expression]* |16-bit comma separated words|
+| .short |expression [, expression]* |16-bit comma separated words|
+| .4byte |expression [, expression]* |32-bit comma separated words|
+| .word |expression [, expression]* |32-bit comma separated words|
+| .long |expression [, expression]* |32-bit comma separated words|
+| .8byte |expression [, expression]* |64-bit comma separated words|
+| .dword |expression [, expression]* |64-bit comma separated words|
+| .quad |expression [, expression]* |64-bit comma separated words|
+| .dtprelword |expression [, expression]* |32-bit thread local word|
+| .dtpreldword |expression [, expression]* |64-bit thread local word|
+| .p2align |p2,[pad_val=0],max |align to power of 2|
+| .balign |b,[pad_val=0] |byte align|
diff --git a/docs/compiler/assembly_manual/SIMT_instruction.md b/docs/compiler/assembly_manual/SIMT_instruction.md
new file mode 100644
index 00000000..a1a3b098
--- /dev/null
+++ b/docs/compiler/assembly_manual/SIMT_instruction.md
@@ -0,0 +1,120 @@
+# SIMT command
+
+SIMT instructions can only be used in SIMT blocks. Operation types include: covering existing scalar operations, reduce operations, floating point operations, and diverge processing operations. The register operands of SIMT instructions all need to be expressed in bit width. The general assembly format is as follows:
+
+```
+Opcode /*表示指令无输出*/
+Opcode Operand0., ->{LL_GPR, UL_GPR}. /*输出到块内寄存器，SIMT块中有U/T/M/N四组刻度尺寄存器*/
+Opcode Operand0., Operand1. /*表示指令无输出*/
+Opcode Operand0., Operand1., ->{LL_GPR}. /*输出到块内寄存器，SIMT块中有U/T/M/N四组刻度尺寄存器*/
+Opcode Operand0., Operand1., Operand2. /*表示指令无输出*/
+Opcode Operand0., Operand1., Operand2., ->{LL_GPR}. /*输出到块内寄存器，SIMT块中有U/T/M/N四组刻度尺寄存器*/
+Opcode Operand0., Operand1., Operand2, Operand3 /*表示指令无输出*/
+```
+
+In general, the bit width expressions of input and output register operands include:
+
+- '.fd': Input bit width identifier, indicating that the input is a double-precision floating point type with a bit width of 64 bits.
+- '.fs': Input bit width identifier, indicating that the input is a single-precision floating point type with a bit width of 32 bits.
+- '.fh': Input bit width identifier, indicating that the input is a half-precision floating point type with a bit width of 16 bits.
+- '.fb': Input bit width identifier, indicating that the input is an fp8 floating point type with a bit width of 8 bits.
+- '.bf': Input bit width identifier, indicating that the input is a bf16 floating point type with a bit width of 16 bits.
+- '.flb': Input bit width identifier, indicating that the input is an fp8.1 floating point type with a bit width of 8 bits.
+- '.ud': Input bit width identifier, indicating that the input is an unsigned integer with a bit width of 64 bits.
+- '.uw': Input bit width identifier, indicating that the input is an unsigned integer with a bit width of 32 bits.
+- '.uh': Input bit width identifier, indicating that the input is an unsigned integer with a bit width of 16 bits.
+- '.ub': Input bit width identifier, indicating that the input is an unsigned integer with a bit width of 8 bits.
+- '.sd': Input bit width identifier, indicating that the input is a signed integer with a bit width of 64 bits.
+- '.sw': Input bit width identifier, indicating that the input is a signed integer with a bit width of 32 bits.
+- '.sh': Input bit width identifier, indicating that the input is a signed integer with a bit width of 16 bits.
+- '.sb': Input bit width identifier, indicating that the input is a signed integer with a bit width of 8 bits.
+- '.d': Output bit width identifier, indicating that the output bit width is 64bit.
+- '.w': Output bit width identifier, indicating that the output bit width is 32bit.
+- '.h': Output bit width identifier, indicating that the output bit width is 16bit.
+- '.b': Output bit width identifier, indicating that the output bit width is 8 bits.
+
+
+For **cvt** class instructions, the input and output bit width identification range is: .fd, .fs, .fh, .fb, .bf, .flb, .ud, .uw, .uh, .ub, .sd, .sw, .sh, .sb. For example:
+
+```
+fcvt t#1.fs, ->t.fd /*浮点类型间的转换，将单精度浮点数转换成双精度浮点数*/
+fcvti t#1.fh, ->t.sw /*浮点到整型的转换，将半精度浮点数转换成有符号字*/
+icvt t#1.uh, ->t.sw /*整型类型间的转换，将无符号半字转换成有符号字*/
+icvtf t#1.sw, ->t.fs /*整型到浮点的转换，将有符号半字转成成单精度浮点数*/
+```
+
+**Usage restrictions:**- Instructions output to global registers are currently limited to reduction instructions, and the output bit width of this type of microinstruction is limited to 64 bits. If the protocol access is required, the corresponding protocol access command must be used.
+- The global register represents the scalar value, which is a constant for the SIMT block, while the register within the block represents the vector value, that is, the value within the block can change.
+- The input bit width identifier of floating point operands needs to be **.fd, .fs, .fh, .fb, .bf, .flb**, and the input bit width identifier of integer operands needs to be **.ud, .uw, .uh, .ub, .sd, .sw, .sh, .sb**. (1)
+- For non-memory access integer operation microinstructions, the register operands need to carry bit width information and the bit width information of the register operands needs to be consistent. The current assembly requires that **the input bit width identifiers are consistent**. Microinstructions with inconsistent bit width identifiers have unpredictable running behavior. At the same time, the input bit width identifiers correspond to the output bit width identifiers. (1)
+- For memory access microinstructions, the bit width of the base address part of address calculation defaults to 64 bits, and the bit width of the address offset part is not limited. The output bit width of the memory access read instruction is consistent with the data bit width loaded by the memory access instruction, and the data register bit width of the memory access write instruction is consistent with the data bit width to be stored by the memory access instruction. (2)
+- When the current microinstruction directly refers to the result of the previous microinstruction, the bit width needs to be kept consistent, otherwise the execution result will be unpredictable. (3)
+- However, for sign-sensitive operations, the use of the main sign bit is required when using the input bit width identifier. When the operation result is inconsistent with the output bit width identifier, and the input bit width is smaller than the output bit width, the corresponding expansion operation is performed according to the sign of the input bit width identifier. (4)
+- When there are branches in SIMTblock instruction, you need to use the microinstruction guarantee function related to SIMT stack. (5)
+- Except for the address calculation of memory access instructions/**cvt** class microinstructions/floating point microinstructions, the bit width identifier contains the meaning of data type. In other scenarios, it is only used for bit width expression.
+- LC, LBsystem register can be indexed directly using SIMT instructions.
+
+
+For detailed microinstructions, please refer to the chapter [vector instructions] (../../isa/blockIntro/vecinstrs/instIntro.md) in the manual.
+
+Basic instruction example:
+
+(0) Reduce operation assembly diagram
+
+```
+rdadd t#1.uh, ->x1.d /*寄存器reduce指令，将SIMT块中所有线程的rdadd中16位宽的t#1的值累加，最终的累加值无符号扩展到64bit，写到x1寄存器中*/
+rdadd t#1.sw, ->x1.d /*寄存器reduce指令，将SIMT块中所有线程的rdadd中32位宽的t#1的值累加，最终的累加值有符号扩展到64bit，写到x1寄存器中*/
+sw.add.rd [t#1.d], t#2.w /*访存reduce指令，将SIMT块中所有线程的sw.add对应的t#2.w的值累加，再与访存地址t#1中的值累加，再存回地址t#1中*/
+```
+
+(1) Assembly diagram of arithmetic and logic operations
+
+```
+add t#1.sw, t#2.sw, ->t.w /*将整型的32bit的t#1与32bit的t#2相加写到t刻度尺寄存器中，且输出位宽为32bit，汇编要求用sw表示输入位宽时，都采用sw*/
+add a0.uw, t#2.uw, ->t.w /*uw的写法与sw的写法，输入位宽表达上含义一致*/
+fadd t#1.fs, t#2.fs, ->t.w /*两个单精度浮点数相加，结果写到t刻度尺寄存器中，输出位宽为32bit，输入位宽与输出位宽对应*/
+```
+
+(2) Assembly instructions for memory access operations
+
+```
+lb [a0.sd, t#1.sw], ->t.b /*基址a0的位宽要求64bit，地址偏移t#1由32bit有符号扩展到64bit后与基址相加得到64bit访存地址，目的寄存器位宽与lb的加载的数据位宽一致，为8bit*/
+lw [a1.sd, t#1.sb], ->t.w /*基址a1的位宽要求64bit，地址偏移t#1由8bit有符号扩展到64bit后与基址相加得到64bit访存地址，目的寄存器位宽与lw的加载的数据位宽一致，为32bit*/
+sw t#1.sw, [a2.ud, lc0.ud] /*sw微指令的数据寄存器位宽与sw的存储数据位宽一致，均为32bit宽度*/
+icvt t#1.sw, ->t.sd
+sd t#1.sd, [a3.sd, t#2.sb] /*sd微指令的数据寄存器位宽为64bit，因此需要先将lw的结果通过icvt转换成64bit宽度后才能使用*/
+```
+(3) There are dependency assembly instructions between instructions
+
+```
+sub t#1.sw, t#2.sw, ->t.w
+add a0.sw, t#1.sw, ->t.w /*add指令使用sub的结果，保持位宽都是32bit*/
+icvt t#1.sw, ->t.sd
+and t#1.sd, x1.sd, ->t.d /索引前序指令的结果时，需要位宽一致，and使用add的结果，为保持位宽一致，需要使用icvt指令进行转换，将32bit的位宽转成64bbit*/
+```
+
+(4)
+
+```
+div t#1.sw, t#2.sw, ->t.w /*位宽为32bit的有符号除法操作*/
+div t#1.uw, t#2.uw, ->t.w /*位宽为32bit的无符号除法操作*/
+mul t#1.sd, t#2.sd, ->t.d /*位宽为64bit的有符号乘法*/
+mul t#1.ud, t#2.ud, ->t.d /*位宽为64bit的无符号乘法*/
+```
+
+(5) dive command instructions:
+
+In order to handle the diverge situation in the parallel block, you need to pay attention to the increase in the label of the convergence point of the conditional instruction in the block and the pc.pop of the convergence point. All conditional jump instructions in the current block, including integer comparison jumps and floating point comparison jumps, require label descriptions of the convergence points. For convergence point addresses or jump target addresses that exceed the encoding range, the compiler will convert them to **b.cond** for processing.
+
+```
+...
+lw [a1.ud, lc0.ud<<2], ->t.w
+b.eq t#1.sw, t#2.sw, _block_D, _converge_E_ /*指示该分支的converge点为_converge_E_*/
+addi zero.uw, 2, ->m.w
+j _converge_E
+_block_D:
+addi zero.uw, 1, ->u.w
+_converge_E:
+pc.pop /*converge点pop决定是否还有另一侧的分支待执行，还是顺序往下执行*/
+...
+```
\ No newline at end of file
diff --git a/docs/compiler/assembly_manual/Standard_binary_interge_instruction.md b/docs/compiler/assembly_manual/Standard_binary_interge_instruction.md
new file mode 100644
index 00000000..5140ad4a
--- /dev/null
+++ b/docs/compiler/assembly_manual/Standard_binary_interge_instruction.md
@@ -0,0 +1,27 @@
+# Standard binary integer arithmetic
+
+Usually there are two input operation objects, left source and right source, and one output.
+
+```
+Opcode Operand0,Operand1,->{LL_GPR, UL_GPR} /* 输出到块内寄存器或者全局寄存器 */
+```
+
+- Adding ‘w’ after Opcode indicates lower 32bit signed extension
+- Adding ‘i’ after Opcode indicates that the right source operation object is an immediate value
+- For arithmetic instructions, {.sw, .uw, .neg} extension can be added after the right source register. 'sw' means intercepting the lower 32 bits of the operand and doing signed extension. 'uw' means intercepting the lower 32 bits of the operand and doing unsigned extension. 'neg' means inverting the operand and adding 1
+- For logical logic operations, you can add {.sw, .uw, .not} extension after the right source register, '.not' means inverting the operand.
+- You can add '<<' after the right source register to indicate a shift operation on the right source register. The possible left shift values are {0, 1, 2, 3}. A left shift of 0 bits means no shift, which can be defaulted.
+- When the right source operation object Operaand1 is an immediate number, the value operation of constant value and immediate number is supported: '%lo(expression)' means to obtain the lower 12 bits of the expression value, '%tpcrel_lo(label)' means to obtain the lower 12 bits of the symbol address relative to the label, which represents the lower 12 bits of the TPC offset value, and the '%tprel_lo(symbl)' table is to obtain the lower 12 bits of the TLS variable relative to the Thead Pointer register
+
+For detailed microinstructions, please refer to the chapter [Arithmetic Instructions] (https://openx.huawei.com/mkdocs/project/1410/blockisa-doc/docs/site/docs/isa/blockIntro/common/arithmetic/) in the manual.
+
+## Assembly examples are as follows:
+
+```
+add a1,a2, ->t /* LL_GPR的R寄存器a1 + a2, 输出到LL_GPR的T寄存器 */
+addi a1,4, ->t /* LL_GPR的R寄存器a1 + 4, 输出到LL_GPR的T寄存器 */
+add a1,a2.sw, ->t /* 寄存器a1的值 + 寄存器a2截取寄存器的低32bit做有符号扩展的值, 输出到T寄存器 */
+add a1,a2<<1, ->t /* 寄存器a1的值 + 寄存器a2左移一位的值, 输出到T寄存器 */
+add a1,a2.sw<<1,->t /* 寄存器a1的值 + a2截取寄存器的低32bit做有符号扩展后左移一位的值， 输出到第二层的T寄存器 */
+add a1,a2.sw<<1,->a1 /* 寄存器a1的值 + a2截取寄存器的低32bit做有符号扩展后左移一位的值， 输出到第一层GPR的a1寄存器 */
+```
\ No newline at end of file
diff --git a/docs/compiler/assembly_manual/Std_Extern.md b/docs/compiler/assembly_manual/Std_Extern.md
new file mode 100644
index 00000000..2802ef52
--- /dev/null
+++ b/docs/compiler/assembly_manual/Std_Extern.md
@@ -0,0 +1,11 @@
+## scalar block private microinstructions
+
+These microinstructions are only used by the scalar block. For a detailed description of the microinstructions, please refer to the chapter **scalarblock instruction Set**. The general assembly is as follows:
+
+```
+Opcode Operand0, Operand1, ->{LL_GPR, UL_GPR}
+Opcode Operand0, Operand1, Operand2, ->{LL_GPR, UL_GPR}
+Opcode Operand0, Operand1, Operand2, Operand3, ->{LL_GPR, UL_GPR}
+Opcode [Operand0, Operand1]
+Opcode [Operand0, Operand1], ->{LL_GPR, UL_GPR}
+```
\ No newline at end of file
diff --git a/docs/compiler/assembly_manual/assemble_instruction.md b/docs/compiler/assembly_manual/assemble_instruction.md
new file mode 100644
index 00000000..01114e27
--- /dev/null
+++ b/docs/compiler/assembly_manual/assemble_instruction.md
@@ -0,0 +1,37 @@
+The LinxISA assembly instruction format is specified as follows:
+
+```
+Opcode operand0,operand1,... {->destination}
+```
+
+- Opcode is the name of the instruction, which is an identifier unique to different instructions.
+- Operand is the operation object of the instruction, which can be a register, immediate value, or label
+- Opcode and Operand are separated by spaces. Multiple Operands can be separated by ',', such as Opcode operand0, operand1
+- Two Opcode instruction identifiers cannot appear in the same instruction.
+- ...means there may be 0 or more Operands
+- {->destination} means that when there is output, -> needs to be used to indicate the output to the corresponding global or block register. The block register supports dual output, and supports up to 2 block registers.
+
+## Operation object
+Operand operation objects have three forms: register, immediate value, and label.
+
+- The naming of registers has been explained in the previous register chapter.
+- The writing method of immediate data is the same as other architectures: supports signed/unsigned immediate data, supports decimal (1234)/hexadecimal (0x4d2)/binary (0b100 1101 0010)
+- The usage of tags has been explained in the previous tags chapter.
+
+The assembly instructions of header and microinstructions will be introduced below. When reading the assembly instructions below: the {} symbol indicates the use of any string separated by ',' in {}, and <> indicates that the content within <> may not be written by default.
+
+### Expression
+In the assembler, immediate and label type operands are treated as an expression. The assembler will convert immediate values and labels into the required numeric values. Therefore, when an assembly instruction or assembly pseudo-instruction requires an integer, we can usually write it as an immediate number and label any of the two operation objects:
+1. Directly use an immediate value specified in decimal, hexadecimal (with 0x prefix), or binary (with 0b prefix). (0)
+2. Use mathematical and logical expressions consisting of labels and other predefined values. These expressions produce absolute or relative values. The absolute value is position independent and constant. Relative values are specified relative to some linker-defined address that is determined when the binary executable is generated,
+For example, the target address of the branch. (1)
+
+(0)
+```
+BSTART.STD COND, 0x200000 /* 当前ZXTERMZH39QXZ的跳转目标地址为0x200000 */
+```
+
+(1)
+```
+BSTART.STD COND, .LBBO /* 当前ZXTERMZH39QXZ的跳转目标地址为标签LBBO所指示的地址，在生成二进制执行文件时确定*/
+```
\ No newline at end of file
diff --git a/docs/compiler/assembly_manual/atomic_instruction.md b/docs/compiler/assembly_manual/atomic_instruction.md
new file mode 100644
index 00000000..47e9f124
--- /dev/null
+++ b/docs/compiler/assembly_manual/atomic_instruction.md
@@ -0,0 +1,107 @@
+# System block private microinstructions
+
+The private microinstructions of the system block include system register operations, execution control, cache management operations, atomic operations, etc. For detailed microinstruction description, please refer to the chapter [System Block Private Instructions] (../../isa/blockIntro/sys_block/instlist.md).
+
+## Atomic instructions
+
+### Atomic access calculation instructions
+
+```
+Opcode [Operand0],Operand1 /* 无输出 */
+Opcode [Operand0],Operand1,->{LL_GPR, UL_GPR} /* 输出到LL_GPR的T/U寄存器 */
+```
+
+- Add the extension after Opcode: Opcode{.aq, .rl, .aqrl} to specify the access sequence restriction.
+ - '.aq': Sequential restrictions on subsequent instructions accessing storage. (0)
+ - '.rl': Sequential restrictions on accessing storage by previous instructions. (1)
+ - '.aqrl': The order in which post-order and pre-order instructions access storage is restricted. (2)
+- '[]' means using the register value as the address
+
+Example:
+(0)
+```
+ld.add.aq [a1],a2,->t /* 以寄存器a2的值为地址的内存中加载64bit的数据与右源操作数相加，将结果写回到以左源寄存器的值为地址的内存中，将加载的数据写到目的T寄存器中 */
+```
+
+(1)
+```
+ld.add.rl [a1],a2,->t
+```
+
+(2)
+```
+ld.add.aqrl [a1],a2,->a2
+```
+### Atomic storage calculation instructions
+
+```
+Opcode [Operand0],Operand1 /* 无输出 */
+```
+
+- Atomic storage calculation instructions can only use ‘.rl’ (0)
+- '[]' means using the register value as the address
+
+(0)
+```
+sw.add.rl [a1],a2 /* 从以寄存器a1的值为地址的内存原子加载32bit的数据，与右源寄存器低32bit的值相加后，将结果写回到以左源寄存器的值为地址的内存中 */
+```
+
+### Atomic memory access instructions
+
+```
+Opcode [Operand0], ->{LL_GPR, UL_GPR} /* 原子内存访问(0) */
+Opcode Operand0,[Operand1] /* 原子内存存储(1) */
+```
+
+- '[]' means using the register value as the address
+
+(0)
+```
+lr.w.aqrl [t#1], ->t
+```
+
+(1)
+
+```
+sc.d.aqrl t#1,[t#2],->s2
+```
+
+## CMO (Cache Management Operation)
+
+```
+Opcode
+Opcode Operand0 /*带操作数的CMO指令*/
+```
+
+Assembly instructions:
+```
+dc.iva a0 /*根据a0中的地址无效cache中地址对应的cacheline*/
+ic.iall /*无效微指令cache中的数据*/
+```
+
+## system register operation
+
+```
+Opcode Operand0, ->{LL_GPR, UL_GPR}
+Opcode Operand0, Operand1
+```
+
+Assembly example:
+
+```
+ssrget 0x0010, ->t /*加载tp寄存器的值到t刻度尺寄存器
+```
+
+## Execution control class
+
+```
+Opcode
+Opcode Operand0
+Opcode Operand0, Operand1
+```
+
+Assembly instructions:
+
+```
+bse t#1 /*发送t#1中的事件*/
+```
\ No newline at end of file
diff --git a/docs/compiler/assembly_manual/battr.md b/docs/compiler/assembly_manual/battr.md
new file mode 100644
index 00000000..32c44baf
--- /dev/null
+++ b/docs/compiler/assembly_manual/battr.md
@@ -0,0 +1,18 @@
+# Block attribute directive: **B.CATR**
+
+```
+B.CATR {TRAP, ATOMIC, , FAR}
+```
+
+The 'B.CATR' directive tells the assembler about block attributes:
+
+- The default writing method is not supported and there is no additional block attribute, so there is no need to use this command.
+- Only encodings for the above block attributes are supported
+
+Supported operation objects are {TRAP, ATOMIC, , FAR}. For a detailed explanation of atomic attributes, please see [Block Attributes](https://openx.huawei.com/mkdocs/project/1410/blockisa-doc/docs/site/docs/isa/header/B.CATR/)
+
+Example:
+
+```
+B.CATR ATOMIC, AQ /* 表示该ZXTERMZH32QXZ的属性是atomic+acquire属性，如果有多个属性，则用逗号进行分割*/
+```
\ No newline at end of file
diff --git a/docs/compiler/assembly_manual/bend.md b/docs/compiler/assembly_manual/bend.md
new file mode 100644
index 00000000..6c933ee6
--- /dev/null
+++ b/docs/compiler/assembly_manual/bend.md
@@ -0,0 +1,17 @@
+# bodyEND
+Each body of LinxISA uses the 'bend' instruction to mark the end of body execution.
+
+During the execution of the following body, when encountering the first bend instruction, the current body will be submitted, and microinstruction 2 will not be executed. Therefore, the position of the bend instruction is the last instruction expected to be executed.
+Microinstructions:
+```
+...
+...
+.Lbody.bstart:
+ 微指令 1
+ bend /* 第一个bend */
+ 微指令 2
+.Lbody.bstop:
+ bend /* 第二个bend */
+...
+...
+```
\ No newline at end of file
diff --git a/docs/compiler/assembly_manual/bget.md b/docs/compiler/assembly_manual/bget.md
new file mode 100644
index 00000000..fda72141
--- /dev/null
+++ b/docs/compiler/assembly_manual/bget.md
@@ -0,0 +1,9 @@
+# Input register directive: **BGET**
+
+```
+bget {第一层架构GPR寄存器}*
+```
+
+The BGET instruction is used to tell the assembler which UL_GPRs will be read in block instruction. The default value is 0. When block instruction is initialized, the block processor copies the corresponding register in UL_GPR to the R register of its own LL_GPR in the block according to the BGET mask.
+The assembler will encode a 16-bit mask in sequence. Each bit in the mask represents a register, 1 means it will be read, and 0 means it will not be read. The default value of mask is 0x0, which means no BGET descriptor is written. When a BGET descriptor is recognized, the assembler will set the corresponding bit in the Mask of the register represented by its parameter list to 1, and only one BGET is allowed to exist at most.
+The parameter list accepted by BGET is a register list, separated by ",", and must be one of the UL_GPR registers.
\ No newline at end of file
diff --git a/docs/compiler/assembly_manual/bhint.md b/docs/compiler/assembly_manual/bhint.md
new file mode 100644
index 00000000..0c3b21eb
--- /dev/null
+++ b/docs/compiler/assembly_manual/bhint.md
@@ -0,0 +1,6 @@
+# 提示信息伪指令：**BHINT**
+
+```
+b.hint {Reserved} /* Block Hint指令，先预留*/
+```
+
diff --git a/docs/compiler/assembly_manual/bitmanipulate_instruction.md b/docs/compiler/assembly_manual/bitmanipulate_instruction.md
new file mode 100644
index 00000000..61af685f
--- /dev/null
+++ b/docs/compiler/assembly_manual/bitmanipulate_instruction.md
@@ -0,0 +1,13 @@
+# bit operation instructions
+
+```
+Opcode Operand0,Operand1,Operand2,->{LL_GPR,UL_GPR} /* 输出到LL_GPR或者UL_GPR寄存器 */
+```
+
+Among them, Operand0 is the register operand, Operand1 and Operand2 are immediate operations. For detailed microinstruction description, please refer to the chapter [Bit Operation Instructions] (https://openx.huawei.com/mkdocs/project/1410/blockisa-doc/docs/site/docs/isa/blockIntro/common/bitmanip/) in the manual.
+
+Example:
+
+```
+bxu a2,2,18,->a1 /*从a2寄存器中的第2位开始，截取18bit的数，即a2[19:2]，并无符号扩展到64bit，然后写入到a1寄存器*/
+```
\ No newline at end of file
diff --git a/docs/compiler/assembly_manual/block_header.md b/docs/compiler/assembly_manual/block_header.md
new file mode 100644
index 00000000..77bf52e4
--- /dev/null
+++ b/docs/compiler/assembly_manual/block_header.md
@@ -0,0 +1,18 @@
+header contains the attributes of the current block instruction (block instruction type, jump type, input, output, microinstruction storage address and other information). The final header information is expressed through the accumulation of one or more pieces of header instruction information. Different header assembly instructions convey different block instruction information. Programmers use the corresponding header instruction according to code requirements. For the general form of header instruction, it must start with the **BSTART** command and cooperate with other header instruction to express a complete header. The currently supported header instruction and its meaning are shown in the table below. The template block instruction is defined in LinxISA, which does not explicitly include microinstructions. The specific microinstruction form is determined by the hardware implementation. For detailed template block instruction, see [template block instruction set](https://openx.huawei.com/mkdocs/project/1410/blockisa-doc/docs/site/docs/isa/blockIntro/temp_block/intro/):
+
+| header directive | Operand | Description |
+|----------------------------------|--------------------------------------------------------|--------------------------------|
+| BSTART. ,