From cfcde9c5ebc21965c2f703b8bb1370a45d05e22b Mon Sep 17 00:00:00 2001 From: "Maksimova, Viktoria" Date: Fri, 3 Jul 2026 09:13:44 -0700 Subject: [PATCH 1/8] Represent FP4 E2M1 with SPV_EXT_ocp_microscaling_types Add the multi-vendor SPV_EXT_ocp_microscaling_types extension as the preferred representation for the FP4 (E2M1) type, alongside the existing Intel-only SPV_INTEL_float4 extension. Plain FP4 conversion builtins are recognized with both the EXT postfix (e.g. ConvertE2M1ToFP16EXT, mapping to the Float4E2M1EXT encoding and Float4EXT capability) and the INTEL postfix (ConvertE2M1ToFP16INTEL, mapping to the Float4E2M1INTEL encoding and capability). The two encodings translate independently in both directions, so a module using either extension round-trips to the matching builtin. Stochastic-rounding builtins keep the INTEL postfix as their operation belongs to SPV_INTEL_fp_conversions. The Float4EXT capability and the Float4E2M1EXT floating-point encoding are published in the core enums by SPV_EXT_ocp_microscaling_types, so bump the SPIRV-Headers pin to that revision and reference the published symbols directly instead of internal copies, matching how the other EXT float encodings are used. AI-assisted: Claude Opus 4.8 (commercial SaaS) --- docs/OCPTypesRepresentationInLLVM.rst | 22 +++--- include/LLVMSPIRVExtensions.inc | 1 + lib/SPIRV/SPIRVInternal.h | 27 +++++-- lib/SPIRV/SPIRVReader.cpp | 6 +- lib/SPIRV/SPIRVWriter.cpp | 18 +++-- lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h | 1 + lib/SPIRV/libSPIRV/SPIRVType.h | 25 +++--- spirv-headers-tag.conf | 2 +- .../conversions_intel_encoding.ll | 61 ++++++++++++++ .../SPV_INTEL_float4/conversions_packed.ll | 68 ++++++++-------- .../conversions_scalar_vector.ll | 79 ++++++++++--------- .../legacy_intel_encoding_read.spt | 36 +++++++++ .../INTEL/SPV_INTEL_float4/upscale_o0.ll | 18 ++--- .../INTEL/SPV_INTEL_float4/upscale_o2.ll | 22 +++--- .../spv_intel_fp_conversions.ll | 7 +- 15 files changed, 263 insertions(+), 130 deletions(-) create mode 100644 test/extensions/INTEL/SPV_INTEL_float4/conversions_intel_encoding.ll create mode 100644 test/extensions/INTEL/SPV_INTEL_float4/legacy_intel_encoding_read.spt diff --git a/docs/OCPTypesRepresentationInLLVM.rst b/docs/OCPTypesRepresentationInLLVM.rst index 220aa37894..089dc7516a 100644 --- a/docs/OCPTypesRepresentationInLLVM.rst +++ b/docs/OCPTypesRepresentationInLLVM.rst @@ -40,8 +40,8 @@ SPIR-V conversion instructions Most conversions will be represented by standard SPIR-V conversion instructions (*OpFConvert*, *OpConvertSToF*, *OpConvertFToS*, *OpConvertUToF*, *OpConvertFToU*, *OpSConvert*), which don't carry information about floating-point value's width and encoding. This document adds a new set of external function calls, each of which has a name that is formed from encoding a specific conversion -that it performs. This name has a *__builtin_spirv_* prefix and a postfix indicating the extension (e.g., *EXT* from SPV_EXT_float8, -*INTEL* from SPV_INTEL_int4/SPV_INTEL_float4/SPV_INTEL_fp_conversions). These calls will be translated to SPIR-V conversion +that it performs. This name has a *__builtin_spirv_* prefix and a postfix indicating the extension (e.g., *EXT* from SPV_EXT_float8 +and SPV_EXT_ocp_microscaling_types, *INTEL* from SPV_INTEL_int4, SPV_INTEL_float4 and SPV_INTEL_fp_conversions). These calls will be translated to SPIR-V conversion instructions operating over the appropriate types. These functions are expected to be mangled following Itanium C++ ABI. SPIR-V consumer will apply Itanium mangling during translation to LLVM IR as well. @@ -82,16 +82,19 @@ SPV_INTEL_int4 Conversions __builtin_spirv_ConvertInt4ToInt8INTEL -SPV_INTEL_float4 Conversions ------------------------------ +SPV_EXT_ocp_microscaling_types Conversions +------------------------------------------- **Translated to OpFConvert:** .. code-block:: C - __builtin_spirv_ConvertE2M1ToE4M3INTEL, __builtin_spirv_ConvertE2M1ToE5M2INTEL, - __builtin_spirv_ConvertE2M1ToFP16INTEL, __builtin_spirv_ConvertE2M1ToBF16INTEL, - __builtin_spirv_ConvertFP16ToE2M1INTEL, __builtin_spirv_ConvertBF16ToE2M1INTEL + __builtin_spirv_ConvertE2M1ToE4M3EXT, __builtin_spirv_ConvertE2M1ToE5M2EXT, + __builtin_spirv_ConvertE2M1ToFP16EXT, __builtin_spirv_ConvertE2M1ToBF16EXT, + __builtin_spirv_ConvertFP16ToE2M1EXT, __builtin_spirv_ConvertBF16ToE2M1EXT + +For backward compatibility the equivalent INTEL-postfix builtins (e.g. *__builtin_spirv_ConvertE2M1ToFP16INTEL*) +are also accepted and map to SPV_INTEL_float4; new producers should use the EXT form above. SPV_INTEL_fp_conversions ------------------------- @@ -107,8 +110,9 @@ This extension provides conversions with specialized rounding modes for improved The result is decorated with *SaturatedToLargestFloat8NormalConversionEXT* (SPV_EXT_float8). -ClampConvert*ToE2M1INTEL builtins are not provided: fp4 (E2M1) saturation is unconditional, -so they collapse into the plain *Convert\*ToE2M1INTEL* form listed under SPV_INTEL_float4. +ClampConvert*ToE2M1 builtins are not provided: fp4 (E2M1) saturation is unconditional, +so they collapse into the plain *Convert\*ToE2M1EXT* / *Convert\*ToE2M1INTEL* form listed under +SPV_EXT_ocp_microscaling_types / SPV_INTEL_float4. **Translated to OpClampConvertFToSINTEL (clamp rounding to signed integer):** diff --git a/include/LLVMSPIRVExtensions.inc b/include/LLVMSPIRVExtensions.inc index 213a8fb47c..d9743efa02 100644 --- a/include/LLVMSPIRVExtensions.inc +++ b/include/LLVMSPIRVExtensions.inc @@ -95,6 +95,7 @@ EXT(SPV_EXT_float8) EXT(SPV_INTEL_predicated_io) EXT(SPV_INTEL_sigmoid) EXT(SPV_INTEL_float4) +EXT(SPV_EXT_ocp_microscaling_types) EXT(SPV_INTEL_fp_conversions) EXT(SPV_KHR_float_controls2) EXT(SPV_INTEL_rounded_divide_sqrt) diff --git a/lib/SPIRV/SPIRVInternal.h b/lib/SPIRV/SPIRVInternal.h index e6514ff1df..b7555e6b52 100644 --- a/lib/SPIRV/SPIRVInternal.h +++ b/lib/SPIRV/SPIRVInternal.h @@ -1035,7 +1035,8 @@ enum FPEncodingWrap { BF16 = FPEncoding::FPEncodingBFloat16KHR, E4M3 = FPEncoding::FPEncodingFloat8E4M3EXT, E5M2 = FPEncoding::FPEncodingFloat8E5M2EXT, - E2M1 = internal::FPEncodingFloat4E2M1INTEL, + E2M1 = FPEncoding::FPEncodingFloat4E2M1EXT, + E2M1INTEL = internal::FPEncodingFloat4E2M1INTEL, }; // Structure describing non-trivial conversions (FP8, FP4 and int4) @@ -1072,14 +1073,22 @@ typedef SPIRVMap FPConvertToEncodingMap; // clang-format off template <> inline void FPConvertToEncodingMap::init() { // 4-bit conversions - add("ConvertE2M1ToE4M3INTEL", + add("ConvertE2M1ToE4M3EXT", {FPEncodingWrap::E2M1, FPEncodingWrap::E4M3, OpFConvert}); - add("ConvertE2M1ToE5M2INTEL", + add("ConvertE2M1ToE5M2EXT", {FPEncodingWrap::E2M1, FPEncodingWrap::E5M2, OpFConvert}); - add("ConvertE2M1ToFP16INTEL", + add("ConvertE2M1ToFP16EXT", {FPEncodingWrap::E2M1, FPEncodingWrap::IEEE754, OpFConvert}); - add("ConvertE2M1ToBF16INTEL", + add("ConvertE2M1ToBF16EXT", {FPEncodingWrap::E2M1, FPEncodingWrap::BF16, OpFConvert}); + add("ConvertE2M1ToE4M3INTEL", + {FPEncodingWrap::E2M1INTEL, FPEncodingWrap::E4M3, OpFConvert}); + add("ConvertE2M1ToE5M2INTEL", + {FPEncodingWrap::E2M1INTEL, FPEncodingWrap::E5M2, OpFConvert}); + add("ConvertE2M1ToFP16INTEL", + {FPEncodingWrap::E2M1INTEL, FPEncodingWrap::IEEE754, OpFConvert}); + add("ConvertE2M1ToBF16INTEL", + {FPEncodingWrap::E2M1INTEL, FPEncodingWrap::BF16, OpFConvert}); add("ConvertInt4ToE4M3INTEL", {FPEncodingWrap::Integer, FPEncodingWrap::E4M3, OpConvertSToF}); @@ -1092,10 +1101,14 @@ template <> inline void FPConvertToEncodingMap::init() { add("ConvertInt4ToInt8INTEL", {FPEncodingWrap::Integer, FPEncodingWrap::Integer, OpSConvert}); - add("ConvertFP16ToE2M1INTEL", + add("ConvertFP16ToE2M1EXT", {FPEncodingWrap::IEEE754, FPEncodingWrap::E2M1, OpFConvert}); - add("ConvertBF16ToE2M1INTEL", + add("ConvertBF16ToE2M1EXT", {FPEncodingWrap::BF16, FPEncodingWrap::E2M1, OpFConvert}); + add("ConvertFP16ToE2M1INTEL", + {FPEncodingWrap::IEEE754, FPEncodingWrap::E2M1INTEL, OpFConvert}); + add("ConvertBF16ToE2M1INTEL", + {FPEncodingWrap::BF16, FPEncodingWrap::E2M1INTEL, OpFConvert}); add("ConvertFP16ToInt4INTEL", {FPEncodingWrap::IEEE754, FPEncodingWrap::Integer, OpConvertFToS}); add("ConvertBF16ToInt4INTEL", diff --git a/lib/SPIRV/SPIRVReader.cpp b/lib/SPIRV/SPIRVReader.cpp index ec28a691ea..3c5b7d3fc0 100644 --- a/lib/SPIRV/SPIRVReader.cpp +++ b/lib/SPIRV/SPIRVReader.cpp @@ -1042,7 +1042,9 @@ Value *SPIRVToLLVM::transConvertInst(SPIRVValue *BV, Function *F, auto IsFP4OrFP8Encoding = [](FPEncodingWrap Encoding) -> bool { return Encoding == FPEncodingWrap::E4M3 || - Encoding == FPEncodingWrap::E5M2 || Encoding == FPEncodingWrap::E2M1; + Encoding == FPEncodingWrap::E5M2 || + Encoding == FPEncodingWrap::E2M1 || + Encoding == FPEncodingWrap::E2M1INTEL; }; switch (static_cast(BC->getOpCode())) { @@ -3145,6 +3147,8 @@ Value *SPIRVToLLVM::transValueWithoutDecoration(SPIRVValue *BV, Function *F, OutMatrixElementTy->isTypeFloat(8, FPEncodingFloat8E5M2EXT) || InMatrixElementTy->isTypeFloat(8, FPEncodingFloat8E4M3EXT) || InMatrixElementTy->isTypeFloat(8, FPEncodingFloat8E5M2EXT) || + OutMatrixElementTy->isTypeFloat(4, FPEncodingFloat4E2M1EXT) || + InMatrixElementTy->isTypeFloat(4, FPEncodingFloat4E2M1EXT) || OutMatrixElementTy->isTypeFloat( 4, internal::FPEncodingFloat4E2M1INTEL) || InMatrixElementTy->isTypeFloat(4, diff --git a/lib/SPIRV/SPIRVWriter.cpp b/lib/SPIRV/SPIRVWriter.cpp index c6f48667a2..8fe6c9a24b 100644 --- a/lib/SPIRV/SPIRVWriter.cpp +++ b/lib/SPIRV/SPIRVWriter.cpp @@ -923,11 +923,14 @@ SPIRVFunction *LLVMToSPIRVBase::transFunctionDecl(Function *F) { // generation. if (!BM->isAllowedToUseExtension(ExtensionID::SPV_EXT_float8) && !BM->isAllowedToUseExtension(ExtensionID::SPV_INTEL_int4) && - !BM->isAllowedToUseExtension(ExtensionID::SPV_INTEL_float4)) { - std::string ErrorStr = "One of the following extensions: " - "SPV_EXT_float8, SPV_INTEL_float4, " - "SPV_INTEL_int4 should be enabled to process " - "conversion builtins"; + !BM->isAllowedToUseExtension(ExtensionID::SPV_INTEL_float4) && + !BM->isAllowedToUseExtension( + ExtensionID::SPV_EXT_ocp_microscaling_types)) { + std::string ErrorStr = + "One of the following extensions: " + "SPV_EXT_float8, SPV_EXT_ocp_microscaling_types, " + "SPV_INTEL_float4, SPV_INTEL_int4 should be enabled to process " + "conversion builtins"; getErrorLog().checkError(false, SPIRVEC_RequiresExtension, F, ErrorStr); } return nullptr; @@ -5717,8 +5720,9 @@ processMiniFPOrInt4Type(Type *LLVMTy, FPEncodingWrap Encoding, unsigned TyWidth = cast(ScalarTy)->getBitWidth(); unsigned VecSize = 0; - bool IsPacked = - Encoding == FPEncodingWrap::E2M1 || Encoding == FPEncodingWrap::Integer; + bool IsPacked = Encoding == FPEncodingWrap::E2M1 || + Encoding == FPEncodingWrap::E2M1INTEL || + Encoding == FPEncodingWrap::Integer; if (IsPacked && (TyWidth == 8 || TyWidth == 16 || TyWidth == 32 || TyWidth == 64)) { // Int4 or FP4 packed in an integer: each N-bit integer holds N/4 values. diff --git a/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h b/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h index 800f5f8c56..83fc3ec3ab 100644 --- a/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h +++ b/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h @@ -705,6 +705,7 @@ template <> inline void SPIRVMap::init() { add(internal::CapabilityFloat4E2M1INTEL, "Float4E2M1INTEL"); add(internal::CapabilityFloat4E2M1CooperativeMatrixINTEL, "Float4E2M1CooperativeMatrixINTEL"); + add(CapabilityFloat4EXT, "Float4EXT"); add(internal::CapabilityFloatConversionsFtoFINTEL, "FloatConversionsFtoFINTEL"); add(internal::CapabilityFloatConversionsFtoSINTEL, diff --git a/lib/SPIRV/libSPIRV/SPIRVType.h b/lib/SPIRV/libSPIRV/SPIRVType.h index a8b690f564..99279b23d4 100644 --- a/lib/SPIRV/libSPIRV/SPIRVType.h +++ b/lib/SPIRV/libSPIRV/SPIRVType.h @@ -250,6 +250,8 @@ class SPIRVTypeFloat : public SPIRVType { if (isTypeFloat(8, FPEncodingFloat8E4M3EXT) || isTypeFloat(8, FPEncodingFloat8E5M2EXT)) return ExtensionID::SPV_EXT_float8; + if (isTypeFloat(4, FPEncodingFloat4E2M1EXT)) + return ExtensionID::SPV_EXT_ocp_microscaling_types; if (isTypeFloat(4, internal::FPEncodingFloat4E2M1INTEL)) return ExtensionID::SPV_INTEL_float4; return {}; @@ -270,6 +272,8 @@ class SPIRVTypeFloat : public SPIRVType { } else if (isTypeFloat(8, FPEncodingFloat8E4M3EXT) || isTypeFloat(8, FPEncodingFloat8E5M2EXT)) { CV.push_back(CapabilityFloat8EXT); + } else if (isTypeFloat(4, FPEncodingFloat4E2M1EXT)) { + CV.push_back(CapabilityFloat4EXT); } else if (isTypeFloat(4, internal::FPEncodingFloat4E2M1INTEL)) { CV.push_back(internal::CapabilityFloat4E2M1INTEL); } @@ -298,14 +302,16 @@ class SPIRVTypeFloat : public SPIRVType { assert((BitWidth == 4 || BitWidth == 8 || BitWidth == 16 || BitWidth == 32 || BitWidth == 64) && "Invalid bit width"); - assert( - (FloatingPointEncoding == FPEncodingMax || - (BitWidth == 16 && FloatingPointEncoding == FPEncodingBFloat16KHR) || - (BitWidth == 8 && FloatingPointEncoding == FPEncodingFloat8E4M3EXT) || - (BitWidth == 8 && FloatingPointEncoding == FPEncodingFloat8E5M2EXT) || - (BitWidth == 4 && - FloatingPointEncoding == internal::FPEncodingFloat4E2M1INTEL)) && - "Invalid floating point encoding"); + bool ValidEncoding = + FloatingPointEncoding == FPEncodingMax || + (BitWidth == 16 && FloatingPointEncoding == FPEncodingBFloat16KHR) || + (BitWidth == 8 && FloatingPointEncoding == FPEncodingFloat8E4M3EXT) || + (BitWidth == 8 && FloatingPointEncoding == FPEncodingFloat8E5M2EXT) || + (BitWidth == 4 && FloatingPointEncoding == FPEncodingFloat4E2M1EXT) || + (BitWidth == 4 && + FloatingPointEncoding == internal::FPEncodingFloat4E2M1INTEL); + assert(ValidEncoding && "Invalid floating point encoding"); + (void)ValidEncoding; } private: @@ -1224,7 +1230,8 @@ class SPIRVTypeCooperativeMatrixKHR : public SPIRVType { else if (CompType->isTypeFloat(8, FPEncodingFloat8E4M3EXT) || CompType->isTypeFloat(8, FPEncodingFloat8E5M2EXT)) CV.push_back(CapabilityFloat8CooperativeMatrixEXT); - else if (CompType->isTypeFloat(4, internal::FPEncodingFloat4E2M1INTEL)) + else if (CompType->isTypeFloat(4, FPEncodingFloat4E2M1EXT) || + CompType->isTypeFloat(4, internal::FPEncodingFloat4E2M1INTEL)) CV.push_back(internal::CapabilityFloat4E2M1CooperativeMatrixINTEL); return CV; } diff --git a/spirv-headers-tag.conf b/spirv-headers-tag.conf index 47d1501785..708c8a3749 100644 --- a/spirv-headers-tag.conf +++ b/spirv-headers-tag.conf @@ -1 +1 @@ -5c50cbd25a40f8b60e44a2ccc2f1ba3c9e0d0299 +575b6512579ebde466ed3dfc04e413439d14d95d diff --git a/test/extensions/INTEL/SPV_INTEL_float4/conversions_intel_encoding.ll b/test/extensions/INTEL/SPV_INTEL_float4/conversions_intel_encoding.ll new file mode 100644 index 0000000000..87e014b512 --- /dev/null +++ b/test/extensions/INTEL/SPV_INTEL_float4/conversions_intel_encoding.ll @@ -0,0 +1,61 @@ +; Checks that FP4 (E2M1) conversion builtins with the INTEL postfix are +; translated using the SPV_INTEL_float4 extension: the Float4E2M1INTEL +; encoding (6214) and capability, independently of the Float4E2M1EXT encoding +; from SPV_EXT_ocp_microscaling_types. Round-trips back to the INTEL builtins. + +; RUN: llvm-spirv %s -o %t.spv --spirv-ext=+SPV_INTEL_float4,+SPV_INTEL_int4,+SPV_KHR_bfloat16 +; RUN: llvm-spirv %t.spv -o %t.spt --to-text +; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV +; RUN: llvm-spirv %t.spv -o %t.rev.bc -r --spirv-target-env=SPV-IR +; RUN: llvm-dis %t.rev.bc -o %t.rev.ll +; RUN: FileCheck < %t.rev.ll %s --check-prefix=CHECK-LLVM + +; CHECK-SPIRV-DAG: Capability Int4TypeINTEL +; CHECK-SPIRV-DAG: Capability Float4E2M1INTEL +; CHECK-SPIRV-DAG: Extension "SPV_INTEL_float4" +; CHECK-SPIRV-DAG: Extension "SPV_INTEL_int4" + +; CHECK-SPIRV-DAG: Name [[#fp4e2m1_hf16_scalar:]] "fp4e2m1_hf16_scalar" +; CHECK-SPIRV-DAG: Name [[#hf16_fp4e2m1_scalar:]] "hf16_fp4e2m1_scalar" + +; CHECK-SPIRV-DAG: TypeInt [[#Int4Ty:]] 4 0 +; CHECK-SPIRV-DAG: Constant [[#Int4Ty]] [[#Int4Const:]] 1 +; CHECK-SPIRV-DAG: TypeFloat [[#HFloat16Ty:]] 16 {{$}} +; CHECK-SPIRV-DAG: TypeFloat [[#E2M1Ty:]] 4 6214 + +target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024" +target triple = "spir-unknown-unknown" + +; CHECK-SPIRV: Function [[#]] [[#fp4e2m1_hf16_scalar]] [[#]] +; CHECK-SPIRV: Bitcast [[#E2M1Ty]] [[#Cast:]] [[#Int4Const]] +; CHECK-SPIRV: FConvert [[#HFloat16Ty]] [[#Conv:]] [[#Cast]] +; CHECK-SPIRV: ReturnValue [[#Conv]] + +; CHECK-LLVM-LABEL: fp4e2m1_hf16_scalar +; CHECK-LLVM: %[[#Call:]] = call spir_func half @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELi(i4 1) +; CHECK-LLVM: ret half %[[#Call]] + +define spir_func half @fp4e2m1_hf16_scalar() { +entry: + %0 = call spir_func half @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELi(i4 1) + ret half %0 +} + +declare dso_local spir_func half @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELi(i4) + +; CHECK-SPIRV: Function [[#]] [[#hf16_fp4e2m1_scalar]] [[#]] +; CHECK-SPIRV: FConvert [[#E2M1Ty]] [[#Conv:]] [[#]] +; CHECK-SPIRV: Bitcast [[#Int4Ty]] [[#Cast:]] [[#Conv]] +; CHECK-SPIRV: ReturnValue [[#Cast]] + +; CHECK-LLVM-LABEL: hf16_fp4e2m1_scalar +; CHECK-LLVM: %[[#Call:]] = call spir_func i4 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDh(half 1.000000e+00) +; CHECK-LLVM: ret i4 %[[#Call]] + +define spir_func i4 @hf16_fp4e2m1_scalar() { +entry: + %0 = call spir_func i4 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDh(half 1.0) + ret i4 %0 +} + +declare dso_local spir_func i4 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDh(half) diff --git a/test/extensions/INTEL/SPV_INTEL_float4/conversions_packed.ll b/test/extensions/INTEL/SPV_INTEL_float4/conversions_packed.ll index 5ca310089d..17d04de69d 100644 --- a/test/extensions/INTEL/SPV_INTEL_float4/conversions_packed.ll +++ b/test/extensions/INTEL/SPV_INTEL_float4/conversions_packed.ll @@ -15,7 +15,7 @@ ; d. packed in 64-bit ; e. packed in vector of 8-bit integers -; RUN: llvm-spirv %s -o %t.spv --spirv-ext=+SPV_EXT_float8,+SPV_INTEL_float4,+SPV_INTEL_int4,+SPV_KHR_bfloat16 +; RUN: llvm-spirv %s -o %t.spv --spirv-ext=+SPV_EXT_float8,+SPV_EXT_ocp_microscaling_types,+SPV_INTEL_int4,+SPV_KHR_bfloat16 ; RUN: llvm-spirv %t.spv -o %t.spt --to-text ; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV ; RUN: llvm-spirv %t.spv -o %t.rev.bc -r --spirv-target-env=SPV-IR @@ -23,8 +23,8 @@ ; RUN: FileCheck < %t.rev.ll %s --check-prefix=CHECK-LLVM ; CHECK-SPIRV-DAG: Capability Float8EXT -; CHECK-SPIRV-DAG: Capability Float4E2M1INTEL -; CHECK-SPIRV-DAG: Extension "SPV_INTEL_float4" +; CHECK-SPIRV-DAG: Capability Float4EXT +; CHECK-SPIRV-DAG: Extension "SPV_EXT_ocp_microscaling_types" ; CHECK-SPIRV-DAG: Extension "SPV_EXT_float8" ; CHECK-SPIRV-DAG: Name [[#fp4e2m1_hf8_32:]] "fp4e2m1_hf8_32" @@ -53,7 +53,7 @@ ; CHECK-SPIRV-DAG: Constant [[#Int64Ty]] [[#Int64Const:]] 1 ; CHECK-SPIRV-DAG: ConstantComposite [[#Int8Vec2Ty]] [[#Int8Vec2Const:]] [[#Int8Const]] [[#Int8Const]] -; CHECK-SPIRV-DAG: TypeFloat [[#E2M1Ty:]] 4 6214 +; CHECK-SPIRV-DAG: TypeFloat [[#E2M1Ty:]] 4 4225 ; CHECK-SPIRV-DAG: TypeVector [[#E2M1Vec8Ty:]] [[#E2M1Ty]] 8 ; CHECK-SPIRV-DAG: TypeVector [[#E2M1Vec2Ty:]] [[#E2M1Ty]] 2 ; CHECK-SPIRV-DAG: TypeVector [[#E2M1Vec4Ty:]] [[#E2M1Ty]] 4 @@ -89,16 +89,16 @@ target triple = "spir-unknown-unknown" ; CHECK-LLVM-LABEL: fp4e2m1_hf8_32 ; CHECK-LLVM: %[[#Cast:]] = bitcast i32 1 to <8 x i4> -; CHECK-LLVM: %[[#Call:]] = call spir_func <8 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELDv8_i(<8 x i4> %[[#Cast]]) +; CHECK-LLVM: %[[#Call:]] = call spir_func <8 x i8> @_Z36__builtin_spirv_ConvertE2M1ToE4M3EXTDv8_i(<8 x i4> %[[#Cast]]) ; CHECK-LLVM: ret <8 x i8> %[[#Call]] define spir_func <8 x i8> @fp4e2m1_hf8_32() { entry: - %0 = call spir_func <8 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELi(i32 1) + %0 = call spir_func <8 x i8> @_Z36__builtin_spirv_ConvertE2M1ToE4M3EXTi(i32 1) ret <8 x i8> %0 } -declare dso_local spir_func <8 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELi(i32) +declare dso_local spir_func <8 x i8> @_Z36__builtin_spirv_ConvertE2M1ToE4M3EXTi(i32) ; CHECK-SPIRV: Function [[#]] [[#hf16_fp4e2m1_32]] [[#]] ; CHECK-SPIRV: FConvert [[#E2M1Vec8Ty]] [[#Conv:]] [[#HFloat16Vec8Const]] @@ -106,17 +106,17 @@ declare dso_local spir_func <8 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTEL ; CHECK-SPIRV: ReturnValue [[#Cast2]] ; CHECK-LLVM-LABEL: hf16_fp4e2m1_32 -; CHECK-LLVM: %[[#Call:]] = call spir_func <8 x i4> @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv8_Dh(<8 x half> splat (half 1.000000e+00)) +; CHECK-LLVM: %[[#Call:]] = call spir_func <8 x i4> @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTDv8_Dh(<8 x half> splat (half 1.000000e+00)) ; CHECK-LLVM: %[[#Cast:]] = bitcast <8 x i4> %[[#Call]] to i32 ; CHECK-LLVM: ret i32 %[[#Cast]] define spir_func i32 @hf16_fp4e2m1_32() { entry: - %0 = call spir_func i32 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv8_Dh(<8 x half> ) + %0 = call spir_func i32 @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTDv8_Dh(<8 x half> ) ret i32 %0 } -declare dso_local spir_func i32 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv8_Dh(<8 x half>) +declare dso_local spir_func i32 @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTDv8_Dh(<8 x half>) ; Packed in 8-bit integer @@ -128,16 +128,16 @@ declare dso_local spir_func i32 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv8_D ; CHECK-LLVM-LABEL: fp4e2m1_hf8_8 ; CHECK-LLVM: %[[#Cast:]] = bitcast i8 1 to <2 x i4> -; CHECK-LLVM: %[[#Call:]] = call spir_func <2 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELDv2_i(<2 x i4> %[[#Cast]]) +; CHECK-LLVM: %[[#Call:]] = call spir_func <2 x i8> @_Z36__builtin_spirv_ConvertE2M1ToE4M3EXTDv2_i(<2 x i4> %[[#Cast]]) ; CHECK-LLVM: ret <2 x i8> %[[#Call]] define spir_func <2 x i8> @fp4e2m1_hf8_8() { entry: - %0 = call spir_func <2 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELc(i8 1) + %0 = call spir_func <2 x i8> @_Z36__builtin_spirv_ConvertE2M1ToE4M3EXTc(i8 1) ret <2 x i8> %0 } -declare dso_local spir_func <2 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELc(i8) +declare dso_local spir_func <2 x i8> @_Z36__builtin_spirv_ConvertE2M1ToE4M3EXTc(i8) ; CHECK-SPIRV: Function [[#]] [[#hf16_fp4e2m1_8]] [[#]] ; CHECK-SPIRV: FConvert [[#E2M1Vec2Ty]] [[#Conv:]] [[#HFloat16Vec2Const]] @@ -145,17 +145,17 @@ declare dso_local spir_func <2 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTEL ; CHECK-SPIRV: ReturnValue [[#Cast2]] ; CHECK-LLVM-LABEL: hf16_fp4e2m1_8 -; CHECK-LLVM: %[[#Call:]] = call spir_func <2 x i4> @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv2_Dh(<2 x half> splat (half 1.000000e+00)) +; CHECK-LLVM: %[[#Call:]] = call spir_func <2 x i4> @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTDv2_Dh(<2 x half> splat (half 1.000000e+00)) ; CHECK-LLVM: %[[#Cast:]] = bitcast <2 x i4> %[[#Call]] to i8 ; CHECK-LLVM: ret i8 %[[#Cast]] define spir_func i8 @hf16_fp4e2m1_8() { entry: - %0 = call spir_func i8 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv2_Dh(<2 x half> ) + %0 = call spir_func i8 @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTDv2_Dh(<2 x half> ) ret i8 %0 } -declare dso_local spir_func i8 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv2_Dh(<2 x half>) +declare dso_local spir_func i8 @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTDv2_Dh(<2 x half>) ; Packed in 16-bit integer @@ -167,16 +167,16 @@ declare dso_local spir_func i8 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv2_Dh ; CHECK-LLVM-LABEL: fp4e2m1_hf8_16 ; CHECK-LLVM: %[[#Cast:]] = bitcast i16 1 to <4 x i4> -; CHECK-LLVM: %[[#Call:]] = call spir_func <4 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELDv4_i(<4 x i4> %[[#Cast]]) +; CHECK-LLVM: %[[#Call:]] = call spir_func <4 x i8> @_Z36__builtin_spirv_ConvertE2M1ToE4M3EXTDv4_i(<4 x i4> %[[#Cast]]) ; CHECK-LLVM: ret <4 x i8> %[[#Call]] define spir_func <4 x i8> @fp4e2m1_hf8_16() { entry: - %0 = call spir_func <4 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELs(i16 1) + %0 = call spir_func <4 x i8> @_Z36__builtin_spirv_ConvertE2M1ToE4M3EXTs(i16 1) ret <4 x i8> %0 } -declare dso_local spir_func <4 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELs(i16) +declare dso_local spir_func <4 x i8> @_Z36__builtin_spirv_ConvertE2M1ToE4M3EXTs(i16) ; Packed in 64-bit integer @@ -188,16 +188,16 @@ declare dso_local spir_func <4 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTEL ; CHECK-LLVM-LABEL: fp4e2m1_hf8_64 ; CHECK-LLVM: %[[#Cast:]] = bitcast i64 1 to <16 x i4> -; CHECK-LLVM: %[[#Call:]] = call spir_func <16 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELDv16_i(<16 x i4> %[[#Cast]]) +; CHECK-LLVM: %[[#Call:]] = call spir_func <16 x i8> @_Z36__builtin_spirv_ConvertE2M1ToE4M3EXTDv16_i(<16 x i4> %[[#Cast]]) ; CHECK-LLVM: ret <16 x i8> %[[#Call]] define spir_func <16 x i8> @fp4e2m1_hf8_64() { entry: - %0 = call spir_func <16 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELl(i64 1) + %0 = call spir_func <16 x i8> @_Z36__builtin_spirv_ConvertE2M1ToE4M3EXTl(i64 1) ret <16 x i8> %0 } -declare dso_local spir_func <16 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELl(i64) +declare dso_local spir_func <16 x i8> @_Z36__builtin_spirv_ConvertE2M1ToE4M3EXTl(i64) ; Packed in vector of 8-bit integers @@ -209,16 +209,16 @@ declare dso_local spir_func <16 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTE ; CHECK-LLVM-LABEL: fp4e2m1_hf8_vec2xi8 ; CHECK-LLVM: %[[#Cast:]] = bitcast <2 x i8> splat (i8 1) to <4 x i4> -; CHECK-LLVM: %[[#Call:]] = call spir_func <4 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELDv4_i(<4 x i4> %[[#Cast]]) +; CHECK-LLVM: %[[#Call:]] = call spir_func <4 x i8> @_Z36__builtin_spirv_ConvertE2M1ToE4M3EXTDv4_i(<4 x i4> %[[#Cast]]) ; CHECK-LLVM: ret <4 x i8> %[[#Call]] define spir_func <4 x i8> @fp4e2m1_hf8_vec2xi8() { entry: - %0 = call spir_func <4 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELDv4_i(<2 x i8> ) + %0 = call spir_func <4 x i8> @_Z36__builtin_spirv_ConvertE2M1ToE4M3EXTDv4_i(<2 x i8> ) ret <4 x i8> %0 } -declare dso_local spir_func <4 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELDv4_i(<2 x i8>) +declare dso_local spir_func <4 x i8> @_Z36__builtin_spirv_ConvertE2M1ToE4M3EXTDv4_i(<2 x i8>) ; To packed in 16-bit integer @@ -228,17 +228,17 @@ declare dso_local spir_func <4 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTEL ; CHECK-SPIRV: ReturnValue [[#Cast2]] ; CHECK-LLVM-LABEL: hf16_fp4e2m1_16 -; CHECK-LLVM: %[[#Call:]] = call spir_func <4 x i4> @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv4_Dh(<4 x half> splat (half 1.000000e+00)) +; CHECK-LLVM: %[[#Call:]] = call spir_func <4 x i4> @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTDv4_Dh(<4 x half> splat (half 1.000000e+00)) ; CHECK-LLVM: %[[#Cast:]] = bitcast <4 x i4> %[[#Call]] to i16 ; CHECK-LLVM: ret i16 %[[#Cast]] define spir_func i16 @hf16_fp4e2m1_16() { entry: - %0 = call spir_func i16 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv4_Dh(<4 x half> ) + %0 = call spir_func i16 @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTDv4_Dh(<4 x half> ) ret i16 %0 } -declare dso_local spir_func i16 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv4_Dh(<4 x half>) +declare dso_local spir_func i16 @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTDv4_Dh(<4 x half>) ; To packed in 64-bit integer @@ -248,17 +248,17 @@ declare dso_local spir_func i16 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv4_D ; CHECK-SPIRV: ReturnValue [[#Cast2]] ; CHECK-LLVM-LABEL: hf16_fp4e2m1_64 -; CHECK-LLVM: %[[#Call:]] = call spir_func <16 x i4> @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv16_Dh(<16 x half> splat (half 1.000000e+00)) +; CHECK-LLVM: %[[#Call:]] = call spir_func <16 x i4> @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTDv16_Dh(<16 x half> splat (half 1.000000e+00)) ; CHECK-LLVM: %[[#Cast:]] = bitcast <16 x i4> %[[#Call]] to i64 ; CHECK-LLVM: ret i64 %[[#Cast]] define spir_func i64 @hf16_fp4e2m1_64() { entry: - %0 = call spir_func i64 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv16_Dh(<16 x half> ) + %0 = call spir_func i64 @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTDv16_Dh(<16 x half> ) ret i64 %0 } -declare dso_local spir_func i64 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv16_Dh(<16 x half>) +declare dso_local spir_func i64 @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTDv16_Dh(<16 x half>) ; To packed in vector of 8-bit integers @@ -268,14 +268,14 @@ declare dso_local spir_func i64 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv16_ ; CHECK-SPIRV: ReturnValue [[#Cast]] ; CHECK-LLVM-LABEL: hf16_fp4e2m1_vec2xi8 -; CHECK-LLVM: %[[#Call:]] = call spir_func <4 x i4> @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv4_Dh(<4 x half> splat (half 1.000000e+00)) +; CHECK-LLVM: %[[#Call:]] = call spir_func <4 x i4> @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTDv4_Dh(<4 x half> splat (half 1.000000e+00)) ; CHECK-LLVM: %[[#Cast:]] = bitcast <4 x i4> %[[#Call]] to <2 x i8> ; CHECK-LLVM: ret <2 x i8> %[[#Cast]] define spir_func <2 x i8> @hf16_fp4e2m1_vec2xi8() { entry: - %0 = call spir_func <2 x i8> @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELKDv4_Dh(<4 x half> ) + %0 = call spir_func <2 x i8> @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTKDv4_Dh(<4 x half> ) ret <2 x i8> %0 } -declare dso_local spir_func <2 x i8> @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELKDv4_Dh(<4 x half>) +declare dso_local spir_func <2 x i8> @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTKDv4_Dh(<4 x half>) diff --git a/test/extensions/INTEL/SPV_INTEL_float4/conversions_scalar_vector.ll b/test/extensions/INTEL/SPV_INTEL_float4/conversions_scalar_vector.ll index e9524aa5fc..c5a3855696 100644 --- a/test/extensions/INTEL/SPV_INTEL_float4/conversions_scalar_vector.ll +++ b/test/extensions/INTEL/SPV_INTEL_float4/conversions_scalar_vector.ll @@ -3,7 +3,7 @@ ; include Clamp*, Biased*, ClampBiased* conversions (it's part of another test ; file). -; RUN: llvm-spirv %s -o %t.spv --spirv-ext=+SPV_EXT_float8,+SPV_INTEL_float4,+SPV_INTEL_int4,+SPV_KHR_bfloat16 +; RUN: llvm-spirv %s -o %t.spv --spirv-ext=+SPV_EXT_float8,+SPV_EXT_ocp_microscaling_types,+SPV_INTEL_int4,+SPV_KHR_bfloat16 ; RUN: llvm-spirv %t.spv -o %t.spt --to-text ; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV ; RUN: llvm-spirv %t.spv -o %t.rev.bc -r --spirv-target-env=SPV-IR @@ -12,10 +12,11 @@ ; CHECK-SPIRV-DAG: Capability Int4TypeINTEL ; CHECK-SPIRV-DAG: Capability Float8EXT +; CHECK-SPIRV-DAG: Capability Float4EXT ; CHECK-SPIRV-DAG: Extension "SPV_INTEL_int4" ; CHECK-SPIRV-DAG: Extension "SPV_EXT_float8" -; CHECK-SPIRV-DAG: Extension "SPV_INTEL_float4" +; CHECK-SPIRV-DAG: Extension "SPV_EXT_ocp_microscaling_types" ; CHECK-SPIRV-DAG: Name [[#fp4e2m1_hf8_scalar:]] "fp4e2m1_hf8_scalar" ; CHECK-SPIRV-DAG: Name [[#fp4e2m1_hf8_vector:]] "fp4e2m1_hf8_vector" @@ -39,7 +40,7 @@ ; CHECK-SPIRV-DAG: Constant [[#Int4Ty]] [[#Int4Const:]] 1 ; CHECK-SPIRV-DAG: ConstantComposite [[#Int4VecTy]] [[#Int4VecConst:]] [[#Int4Const]] [[#Int4Const]] [[#Int4Const]] [[#Int4Const]] [[#Int4Const]] [[#Int4Const]] [[#Int4Const]] [[#Int4Const]] -; CHECK-SPIRV-DAG: TypeFloat [[#E2M1Ty:]] 4 6214 +; CHECK-SPIRV-DAG: TypeFloat [[#E2M1Ty:]] 4 4225 ; CHECK-SPIRV-DAG: TypeVector [[#E2M1VecTy:]] [[#E2M1Ty]] 8 ; CHECK-SPIRV-DAG: TypeFloat [[#HFloat8Ty:]] 8 4214 @@ -70,16 +71,16 @@ target triple = "spir-unknown-unknown" ; CHECK-SPIRV: ReturnValue [[#Cast2]] ; CHECK-LLVM-LABEL: fp4e2m1_hf8_scalar -; CHECK-LLVM: %[[#Call:]] = call spir_func i8 @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELi(i4 1) +; CHECK-LLVM: %[[#Call:]] = call spir_func i8 @_Z36__builtin_spirv_ConvertE2M1ToE4M3EXTi(i4 1) ; CHECK-LLVM: ret i8 %[[#Call]] define spir_func i8 @fp4e2m1_hf8_scalar() { entry: - %0 = call spir_func i8 @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELi(i4 1) + %0 = call spir_func i8 @_Z36__builtin_spirv_ConvertE2M1ToE4M3EXTi(i4 1) ret i8 %0 } -declare dso_local spir_func i8 @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELi(i4) +declare dso_local spir_func i8 @_Z36__builtin_spirv_ConvertE2M1ToE4M3EXTi(i4) ; CHECK-SPIRV: Function [[#]] [[#fp4e2m1_hf8_vector]] [[#]] ; CHECK-SPIRV: Bitcast [[#E2M1VecTy]] [[#Cast1:]] [[#Int4VecConst]] @@ -88,16 +89,16 @@ declare dso_local spir_func i8 @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELi(i4) ; CHECK-SPIRV: ReturnValue [[#Cast2]] ; CHECK-LLVM-LABEL: fp4e2m1_hf8_vector -; CHECK-LLVM: %[[#Call:]] = call spir_func <8 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELDv8_i(<8 x i4> splat (i4 1)) +; CHECK-LLVM: %[[#Call:]] = call spir_func <8 x i8> @_Z36__builtin_spirv_ConvertE2M1ToE4M3EXTDv8_i(<8 x i4> splat (i4 1)) ; CHECK-LLVM: ret <8 x i8> %[[#Call]] define spir_func <8 x i8> @fp4e2m1_hf8_vector() { entry: - %0 = call spir_func <8 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELDv8_i(<8 x i4> ) + %0 = call spir_func <8 x i8> @_Z36__builtin_spirv_ConvertE2M1ToE4M3EXTDv8_i(<8 x i4> ) ret <8 x i8> %0 } -declare dso_local spir_func <8 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELDv8_i(<8 x i4>) +declare dso_local spir_func <8 x i8> @_Z36__builtin_spirv_ConvertE2M1ToE4M3EXTDv8_i(<8 x i4>) ; CHECK-SPIRV: Function [[#]] [[#fp4e2m1_bf8_scalar]] [[#]] ; CHECK-SPIRV: Bitcast [[#E2M1Ty]] [[#Cast1:]] [[#Int4Const]] @@ -106,16 +107,16 @@ declare dso_local spir_func <8 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTEL ; CHECK-SPIRV: ReturnValue [[#Cast2]] ; CHECK-LLVM-LABEL: fp4e2m1_bf8_scalar -; CHECK-LLVM: %[[#Call:]] = call spir_func i8 @_Z38__builtin_spirv_ConvertE2M1ToE5M2INTELi(i4 1) +; CHECK-LLVM: %[[#Call:]] = call spir_func i8 @_Z36__builtin_spirv_ConvertE2M1ToE5M2EXTi(i4 1) ; CHECK-LLVM: ret i8 %[[#Call]] define spir_func i8 @fp4e2m1_bf8_scalar() { entry: - %0 = call spir_func i8 @_Z38__builtin_spirv_ConvertE2M1ToE5M2INTELi(i4 1) + %0 = call spir_func i8 @_Z36__builtin_spirv_ConvertE2M1ToE5M2EXTi(i4 1) ret i8 %0 } -declare dso_local spir_func i8 @_Z38__builtin_spirv_ConvertE2M1ToE5M2INTELi(i4) +declare dso_local spir_func i8 @_Z36__builtin_spirv_ConvertE2M1ToE5M2EXTi(i4) ; CHECK-SPIRV: Function [[#]] [[#fp4e2m1_bf8_vector]] [[#]] ; CHECK-SPIRV: Bitcast [[#E2M1VecTy]] [[#Cast1:]] [[#Int4VecConst]] @@ -124,16 +125,16 @@ declare dso_local spir_func i8 @_Z38__builtin_spirv_ConvertE2M1ToE5M2INTELi(i4) ; CHECK-SPIRV: ReturnValue [[#Cast2]] ; CHECK-LLVM-LABEL: fp4e2m1_bf8_vector -; CHECK-LLVM: %[[#Call:]] = call spir_func <8 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE5M2INTELDv8_i(<8 x i4> splat (i4 1)) +; CHECK-LLVM: %[[#Call:]] = call spir_func <8 x i8> @_Z36__builtin_spirv_ConvertE2M1ToE5M2EXTDv8_i(<8 x i4> splat (i4 1)) ; CHECK-LLVM: ret <8 x i8> %[[#Call]] define spir_func <8 x i8> @fp4e2m1_bf8_vector() { entry: - %0 = call spir_func <8 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE5M2INTELDv8_i(<8 x i4> ) + %0 = call spir_func <8 x i8> @_Z36__builtin_spirv_ConvertE2M1ToE5M2EXTDv8_i(<8 x i4> ) ret <8 x i8> %0 } -declare dso_local spir_func <8 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE5M2INTELDv8_i(<8 x i4>) +declare dso_local spir_func <8 x i8> @_Z36__builtin_spirv_ConvertE2M1ToE5M2EXTDv8_i(<8 x i4>) ; CHECK-SPIRV: Function [[#]] [[#fp4e2m1_hf16_scalar]] [[#]] ; CHECK-SPIRV: Bitcast [[#E2M1Ty]] [[#Cast1:]] [[#Int4Const]] @@ -141,16 +142,16 @@ declare dso_local spir_func <8 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE5M2INTEL ; CHECK-SPIRV: ReturnValue [[#Conv]] ; CHECK-LLVM-LABEL: fp4e2m1_hf16_scalar -; CHECK-LLVM: %[[#Call:]] = call spir_func half @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELi(i4 1) +; CHECK-LLVM: %[[#Call:]] = call spir_func half @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTi(i4 1) ; CHECK-LLVM: ret half %[[#Call]] define spir_func half @fp4e2m1_hf16_scalar() { entry: - %0 = call spir_func half @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELi(i4 1) + %0 = call spir_func half @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTi(i4 1) ret half %0 } -declare dso_local spir_func half @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELi(i4) +declare dso_local spir_func half @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTi(i4) ; CHECK-SPIRV: Function [[#]] [[#fp4e2m1_hf16_vector]] [[#]] ; CHECK-SPIRV: Bitcast [[#E2M1VecTy]] [[#Cast1:]] [[#Int4VecConst]] @@ -158,16 +159,16 @@ declare dso_local spir_func half @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELi(i4 ; CHECK-SPIRV: ReturnValue [[#Conv]] ; CHECK-LLVM-LABEL: fp4e2m1_hf16_vector -; CHECK-LLVM: %[[#Call:]] = call spir_func <8 x half> @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELDv8_i(<8 x i4> splat (i4 1)) +; CHECK-LLVM: %[[#Call:]] = call spir_func <8 x half> @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTDv8_i(<8 x i4> splat (i4 1)) ; CHECK-LLVM: ret <8 x half> %[[#Call]] define spir_func <8 x half> @fp4e2m1_hf16_vector() { entry: - %0 = call spir_func <8 x half> @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELDv8_i(<8 x i4> ) + %0 = call spir_func <8 x half> @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTDv8_i(<8 x i4> ) ret <8 x half> %0 } -declare dso_local spir_func <8 x half> @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELDv8_i(<8 x i4>) +declare dso_local spir_func <8 x half> @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTDv8_i(<8 x i4>) ; CHECK-SPIRV: Function [[#]] [[#fp4e2m1_bf16_scalar]] [[#]] ; CHECK-SPIRV: Bitcast [[#E2M1Ty]] [[#Cast1:]] [[#Int4Const]] @@ -175,16 +176,16 @@ declare dso_local spir_func <8 x half> @_Z38__builtin_spirv_ConvertE2M1ToFP16INT ; CHECK-SPIRV: ReturnValue [[#Conv]] ; CHECK-LLVM-LABEL: fp4e2m1_bf16_scalar -; CHECK-LLVM: %[[#Call:]] = call spir_func bfloat @_Z38__builtin_spirv_ConvertE2M1ToBF16INTELi(i4 1) +; CHECK-LLVM: %[[#Call:]] = call spir_func bfloat @_Z36__builtin_spirv_ConvertE2M1ToBF16EXTi(i4 1) ; CHECK-LLVM: ret bfloat %[[#Call]] define spir_func bfloat @fp4e2m1_bf16_scalar() { entry: - %0 = call spir_func bfloat @_Z38__builtin_spirv_ConvertE2M1ToBF16INTELi(i4 1) + %0 = call spir_func bfloat @_Z36__builtin_spirv_ConvertE2M1ToBF16EXTi(i4 1) ret bfloat %0 } -declare dso_local spir_func bfloat @_Z38__builtin_spirv_ConvertE2M1ToBF16INTELi(i4) +declare dso_local spir_func bfloat @_Z36__builtin_spirv_ConvertE2M1ToBF16EXTi(i4) ; CHECK-SPIRV: Function [[#]] [[#fp4e2m1_bf16_vector]] [[#]] ; CHECK-SPIRV: Bitcast [[#E2M1VecTy]] [[#Cast1:]] [[#Int4VecConst]] @@ -192,16 +193,16 @@ declare dso_local spir_func bfloat @_Z38__builtin_spirv_ConvertE2M1ToBF16INTELi( ; CHECK-SPIRV: ReturnValue [[#Conv]] ; CHECK-LLVM-LABEL: fp4e2m1_bf16_vector -; CHECK-LLVM: %[[#Call:]] = call spir_func <8 x bfloat> @_Z38__builtin_spirv_ConvertE2M1ToBF16INTELDv8_i(<8 x i4> splat (i4 1)) +; CHECK-LLVM: %[[#Call:]] = call spir_func <8 x bfloat> @_Z36__builtin_spirv_ConvertE2M1ToBF16EXTDv8_i(<8 x i4> splat (i4 1)) ; CHECK-LLVM: ret <8 x bfloat> %[[#Call]] define spir_func <8 x bfloat> @fp4e2m1_bf16_vector() { entry: - %0 = call spir_func <8 x bfloat> @_Z38__builtin_spirv_ConvertE2M1ToBF16INTELDv8_i(<8 x i4> ) + %0 = call spir_func <8 x bfloat> @_Z36__builtin_spirv_ConvertE2M1ToBF16EXTDv8_i(<8 x i4> ) ret <8 x bfloat> %0 } -declare dso_local spir_func <8 x bfloat> @_Z38__builtin_spirv_ConvertE2M1ToBF16INTELDv8_i(<8 x i4>) +declare dso_local spir_func <8 x bfloat> @_Z36__builtin_spirv_ConvertE2M1ToBF16EXTDv8_i(<8 x i4>) ; Following tests are for 4-bit roundings @@ -211,16 +212,16 @@ declare dso_local spir_func <8 x bfloat> @_Z38__builtin_spirv_ConvertE2M1ToBF16I ; CHECK-SPIRV: ReturnValue [[#Cast]] ; CHECK-LLVM-LABEL: hf16_fp4e2m1_scalar -; CHECK-LLVM: %[[#Call:]] = call spir_func i4 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDh(half 1.000000e+00) +; CHECK-LLVM: %[[#Call:]] = call spir_func i4 @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTDh(half 1.000000e+00) ; CHECK-LLVM: ret i4 %[[#Call]] define spir_func i4 @hf16_fp4e2m1_scalar() { entry: - %0 = call spir_func i4 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDh(half 1.0) + %0 = call spir_func i4 @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTDh(half 1.0) ret i4 %0 } -declare dso_local spir_func i4 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDh(half) +declare dso_local spir_func i4 @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTDh(half) ; CHECK-SPIRV: Function [[#]] [[#hf16_fp4e2m1_vector]] [[#]] ; CHECK-SPIRV: FConvert [[#E2M1VecTy]] [[#Conv:]] [[#HalfVecConst]] @@ -228,16 +229,16 @@ declare dso_local spir_func i4 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDh(hal ; CHECK-SPIRV: ReturnValue [[#Cast]] ; CHECK-LLVM-LABEL: hf16_fp4e2m1_vector -; CHECK-LLVM: %[[#Call:]] = call spir_func <8 x i4> @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv8_Dh(<8 x half> splat (half 1.000000e+00)) +; CHECK-LLVM: %[[#Call:]] = call spir_func <8 x i4> @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTDv8_Dh(<8 x half> splat (half 1.000000e+00)) ; CHECK-LLVM: ret <8 x i4> %[[#Call]] define spir_func <8 x i4> @hf16_fp4e2m1_vector() { entry: - %0 = call spir_func <8 x i4> @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv8_Dh(<8 x half> ) + %0 = call spir_func <8 x i4> @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTDv8_Dh(<8 x half> ) ret <8 x i4> %0 } -declare dso_local spir_func <8 x i4> @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv8_Dh(<8 x half>) +declare dso_local spir_func <8 x i4> @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTDv8_Dh(<8 x half>) ; CHECK-SPIRV: Function [[#]] [[#bf16_fp4e2m1_scalar]] [[#]] ; CHECK-SPIRV: FConvert [[#E2M1Ty]] [[#Conv:]] [[#BfloatConst]] @@ -245,16 +246,16 @@ declare dso_local spir_func <8 x i4> @_Z38__builtin_spirv_ConvertFP16ToE2M1INTEL ; CHECK-SPIRV: ReturnValue [[#Cast]] ; CHECK-LLVM-LABEL: bf16_fp4e2m1_scalar -; CHECK-LLVM: %[[#Call:]] = call spir_func i4 @_Z38__builtin_spirv_ConvertBF16ToE2M1INTELDF16b(bfloat 1.000000e+00) +; CHECK-LLVM: %[[#Call:]] = call spir_func i4 @_Z36__builtin_spirv_ConvertBF16ToE2M1EXTDF16b(bfloat 1.000000e+00) ; CHECK-LLVM: ret i4 %[[#Call]] define spir_func i4 @bf16_fp4e2m1_scalar() { entry: - %0 = call spir_func i4 @_Z38__builtin_spirv_ConvertBF16ToE2M1INTELDF16b(bfloat 1.0) + %0 = call spir_func i4 @_Z36__builtin_spirv_ConvertBF16ToE2M1EXTDF16b(bfloat 1.0) ret i4 %0 } -declare dso_local spir_func i4 @_Z38__builtin_spirv_ConvertBF16ToE2M1INTELDF16b(bfloat) +declare dso_local spir_func i4 @_Z36__builtin_spirv_ConvertBF16ToE2M1EXTDF16b(bfloat) ; CHECK-SPIRV: Function [[#]] [[#bf16_fp4e2m1_vector]] [[#]] ; CHECK-SPIRV: FConvert [[#E2M1VecTy]] [[#Conv:]] [[#BfloatVecConst]] @@ -262,14 +263,14 @@ declare dso_local spir_func i4 @_Z38__builtin_spirv_ConvertBF16ToE2M1INTELDF16b( ; CHECK-SPIRV: ReturnValue [[#Cast]] ; CHECK-LLVM-LABEL: bf16_fp4e2m1_vector -; CHECK-LLVM: %[[#Call:]] = call spir_func <8 x i4> @_Z38__builtin_spirv_ConvertBF16ToE2M1INTELDv8_DF16b(<8 x bfloat> splat (bfloat 1.000000e+00)) +; CHECK-LLVM: %[[#Call:]] = call spir_func <8 x i4> @_Z36__builtin_spirv_ConvertBF16ToE2M1EXTDv8_DF16b(<8 x bfloat> splat (bfloat 1.000000e+00)) ; CHECK-LLVM: ret <8 x i4> %[[#Call]] define spir_func <8 x i4> @bf16_fp4e2m1_vector() { entry: - %0 = call spir_func <8 x i4> @_Z38__builtin_spirv_ConvertBF16ToE2M1INTELDv8_DF16b(<8 x bfloat> ) + %0 = call spir_func <8 x i4> @_Z36__builtin_spirv_ConvertBF16ToE2M1EXTDv8_DF16b(<8 x bfloat> ) ret <8 x i4> %0 } -declare dso_local spir_func <8 x i4> @_Z38__builtin_spirv_ConvertBF16ToE2M1INTELDv8_DF16b(<8 x bfloat>) +declare dso_local spir_func <8 x i4> @_Z36__builtin_spirv_ConvertBF16ToE2M1EXTDv8_DF16b(<8 x bfloat>) diff --git a/test/extensions/INTEL/SPV_INTEL_float4/legacy_intel_encoding_read.spt b/test/extensions/INTEL/SPV_INTEL_float4/legacy_intel_encoding_read.spt new file mode 100644 index 0000000000..5c76e5350d --- /dev/null +++ b/test/extensions/INTEL/SPV_INTEL_float4/legacy_intel_encoding_read.spt @@ -0,0 +1,36 @@ +; Verify that SPIR-V using the Float4E2M1INTEL encoding (6214) from +; SPV_INTEL_float4 is consumed and round-trips back to the INTEL builtin, +; independently of the Float4E2M1EXT encoding from SPV_EXT_ocp_microscaling_types. + +; RUN: llvm-spirv %s -to-binary -o %t.spv +; RUN: llvm-spirv %t.spv -r --spirv-target-env=SPV-IR -o %t.rev.bc +; RUN: llvm-dis %t.rev.bc -o - | FileCheck %s --check-prefix=CHECK-LLVM + +; CHECK-LLVM: call spir_func half @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELi(i4 1) + +119734787 65536 393230 11 0 +2 Capability Addresses +2 Capability Linkage +2 Capability Kernel +2 Capability Float16Buffer +2 Capability Float4E2M1INTEL +2 Capability Int4TypeINTEL +6 Extension "SPV_INTEL_float4" +5 Extension "SPV_INTEL_int4" +5 ExtInstImport 1 "OpenCL.std" +3 MemoryModel 1 2 +3 Source 0 0 +3 Name 4 "f" +4 Name 5 "entry" +5 Decorate 4 LinkageAttributes "f" Export +4 TypeInt 6 4 0 +4 Constant 6 7 1 +3 TypeFloat 2 16 +3 TypeFunction 3 2 +4 TypeFloat 8 4 6214 +5 Function 2 4 0 3 +2 Label 5 +4 Bitcast 8 9 7 +4 FConvert 2 10 9 +2 ReturnValue 10 +1 FunctionEnd diff --git a/test/extensions/INTEL/SPV_INTEL_float4/upscale_o0.ll b/test/extensions/INTEL/SPV_INTEL_float4/upscale_o0.ll index cc8d57c9a4..7af9874d09 100644 --- a/test/extensions/INTEL/SPV_INTEL_float4/upscale_o0.ll +++ b/test/extensions/INTEL/SPV_INTEL_float4/upscale_o0.ll @@ -25,25 +25,25 @@ ; clang -cl-std=cl3.0 -target spir -emit-llvm -Xclang -finclude-default-header -g0 -O0 ; RUN: llvm-as %s -o %t.bc -; RUN: llvm-spirv %t.bc -o %t.spv --spirv-ext=+SPV_INTEL_float4,+SPV_INTEL_int4 +; RUN: llvm-spirv %t.bc -o %t.spv --spirv-ext=+SPV_EXT_ocp_microscaling_types,+SPV_INTEL_int4 ; RUN: llvm-spirv %t.spv -o %t.spt --to-text ; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV ; RUN: llvm-spirv %t.spv -o %t.rev.bc -r --spirv-target-env=SPV-IR ; RUN: llvm-dis %t.rev.bc -o %t.rev.ll ; RUN: FileCheck < %t.rev.ll %s --check-prefix=CHECK-LLVM -; CHECK-SPIRV-NOT: _Z38__builtin_spirv_ConvertE2M1ToFP16INTELDv2_i +; CHECK-SPIRV-NOT: _Z36__builtin_spirv_ConvertE2M1ToFP16EXTDv2_i ; CHECK-SPIRV-DAG: Capability Float16Buffer ; CHECK-SPIRV-DAG: Capability Int4TypeINTEL -; CHECK-SPIRV-DAG: Capability Float4E2M1INTEL +; CHECK-SPIRV-DAG: Capability Float4EXT ; CHECK-SPIRV-DAG: TypeInt [[#Int4Ty:]] 4 0 ; CHECK-SPIRV-DAG: TypeVector [[#VecInt4Ty:]] [[#Int4Ty]] 2 ; CHECK-SPIRV-DAG: TypePointer [[#PtrVecInt4Ty:]] 7 [[#VecInt4Ty]] ; CHECK-SPIRV-DAG: TypeFloat [[#HalfTy:]] 16 ; CHECK-SPIRV-DAG: TypeVector [[#VecHalfTy:]] [[#HalfTy]] 2 -; CHECK-SPIRV-DAG: TypeFloat [[#FP4Ty:]] 4 6214 +; CHECK-SPIRV-DAG: TypeFloat [[#FP4Ty:]] 4 4225 ; CHECK-SPIRV-DAG: TypeVector [[#VecFP4Ty:]] [[#FP4Ty]] 2 ; CHECK-SPIRV: Load [[#VecInt4Ty]] [[#VecInt4Val1:]] [[#]] 2 2 @@ -56,9 +56,9 @@ ; CHECK-SPIRV: FConvert [[#VecHalfTy]] [[#Conv2:]] [[#Cast2]] ; CHECK-SPIRV: Store [[#]] [[#Conv2]] 2 4 -; CHECK-LLVM: %[[#Conv1:]] = call spir_func <2 x half> @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELDv2_i(<2 x i4> %[[#]]) +; CHECK-LLVM: %[[#Conv1:]] = call spir_func <2 x half> @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTDv2_i(<2 x i4> %[[#]]) ; CHECK-LLVM: store <2 x half> %[[#Conv1]], ptr %[[#]] -; CHECK-LLVM: %[[#Conv2:]] = call spir_func <2 x half> @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELDv2_i(<2 x i4> %[[#]]) +; CHECK-LLVM: %[[#Conv2:]] = call spir_func <2 x half> @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTDv2_i(<2 x i4> %[[#]]) ; CHECK-LLVM: store <2 x half> %[[#Conv2]], ptr %[[#]] target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024" @@ -109,10 +109,10 @@ define dso_local spir_func void @__clang_ocl_kern_imp_quant_add(ptr addrspace(3) %26 = shufflevector <2 x i4> %25, <2 x i4> poison, <2 x i32> zeroinitializer store <2 x i4> %26, ptr %9, align 2 %27 = load <2 x i4>, ptr %8, align 2 - %28 = call spir_func <2 x half> @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELDv2_i(<2 x i4> noundef %27) #5 + %28 = call spir_func <2 x half> @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTDv2_i(<2 x i4> noundef %27) #5 store <2 x half> %28, ptr %10, align 4 %29 = load <2 x i4>, ptr %9, align 2 - %30 = call spir_func <2 x half> @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELDv2_i(<2 x i4> noundef %29) #5 + %30 = call spir_func <2 x half> @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTDv2_i(<2 x i4> noundef %29) #5 store <2 x half> %30, ptr %11, align 4 %31 = load <2 x half>, ptr %10, align 4 %32 = load <2 x half>, ptr %11, align 4 @@ -126,7 +126,7 @@ define dso_local spir_func void @__clang_ocl_kern_imp_quant_add(ptr addrspace(3) declare dso_local spir_func i32 @_Z13get_global_idj(i32 noundef) #1 -declare dso_local spir_func <2 x half> @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELDv2_i(<2 x i4> noundef) #2 +declare dso_local spir_func <2 x half> @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTDv2_i(<2 x i4> noundef) #2 attributes #0 = { convergent noinline norecurse nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size"="false" } attributes #1 = { convergent nounwind willreturn memory(none) "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } diff --git a/test/extensions/INTEL/SPV_INTEL_float4/upscale_o2.ll b/test/extensions/INTEL/SPV_INTEL_float4/upscale_o2.ll index 64e097a2c4..cb8ef41c6b 100644 --- a/test/extensions/INTEL/SPV_INTEL_float4/upscale_o2.ll +++ b/test/extensions/INTEL/SPV_INTEL_float4/upscale_o2.ll @@ -25,24 +25,24 @@ ; clang -cl-std=cl3.0 -target spir -emit-llvm -Xclang -finclude-default-header -g0 -O2 ; RUN: llvm-as %s -o %t.bc -; RUN: llvm-spirv %t.bc -o %t.spv --spirv-ext=+SPV_INTEL_float4,+SPV_INTEL_int4 +; RUN: llvm-spirv %t.bc -o %t.spv --spirv-ext=+SPV_EXT_ocp_microscaling_types,+SPV_INTEL_int4 ; RUN: llvm-spirv %t.spv -o %t.spt --to-text ; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV ; RUN: llvm-spirv %t.spv -o %t.rev.bc -r --spirv-target-env=SPV-IR ; RUN: llvm-dis %t.rev.bc -o %t.rev.ll ; RUN: FileCheck < %t.rev.ll %s --check-prefix=CHECK-LLVM -; CHECK-SPIRV-NOT: _Z38__builtin_spirv_ConvertE2M1ToFP16INTELDv2_i +; CHECK-SPIRV-NOT: _Z36__builtin_spirv_ConvertE2M1ToFP16EXTDv2_i ; CHECK-SPIRV-DAG: Capability Float16Buffer ; CHECK-SPIRV-DAG: Capability Int4TypeINTEL -; CHECK-SPIRV-DAG: Capability Float4E2M1INTEL +; CHECK-SPIRV-DAG: Capability Float4EXT ; CHECK-SPIRV-DAG: TypeInt [[#Int4Ty:]] 4 0 ; CHECK-SPIRV-DAG: TypeVector [[#VecInt4Ty:]] [[#Int4Ty]] 2 ; CHECK-SPIRV-DAG: TypeFloat [[#HalfTy:]] 16 ; CHECK-SPIRV-DAG: TypeVector [[#VecHalfTy:]] [[#HalfTy]] 2 -; CHECK-SPIRV-DAG: TypeFloat [[#FP4Ty:]] 4 6214 +; CHECK-SPIRV-DAG: TypeFloat [[#FP4Ty:]] 4 4225 ; CHECK-SPIRV-DAG: TypeVector [[#VecFP4Ty:]] [[#FP4Ty]] 2 ; CHECK-SPIRV: Load [[#VecInt4Ty]] [[#VecInt4Val1:]] [[#]] 2 1 @@ -53,8 +53,8 @@ ; CHECK-SPIRV: FConvert [[#VecHalfTy]] [[#Conv2:]] [[#Cast2]] ; CHECK-SPIRV: FAdd [[#VecHalfTy]] [[#]] [[#Conv1]] [[#Conv2]] -; CHECK-LLVM: %[[#in1:]] = call spir_func <2 x half> @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELDv2_i(<2 x i4> %[[#]]) -; CHECK-LLVM: %[[#in2:]] = call spir_func <2 x half> @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELDv2_i(<2 x i4> %[[#]]) +; CHECK-LLVM: %[[#in1:]] = call spir_func <2 x half> @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTDv2_i(<2 x i4> %[[#]]) +; CHECK-LLVM: %[[#in2:]] = call spir_func <2 x half> @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTDv2_i(<2 x i4> %[[#]]) ; CHECK-LLVM: fadd <2 x half> %[[#in1]], %[[#in2]] target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024" @@ -66,8 +66,8 @@ define dso_local spir_kernel void @quant_add(ptr addrspace(3) noundef readonly a %6 = load <2 x i4>, ptr addrspace(3) %5, align 1 %7 = getelementptr inbounds i8, ptr addrspace(3) %1, i32 %4 %8 = load <2 x i4>, ptr addrspace(3) %7, align 1 - %9 = tail call spir_func <2 x half> @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELDv2_i(<2 x i4> noundef %6) #5 - %10 = tail call spir_func <2 x half> @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELDv2_i(<2 x i4> noundef %8) #5 + %9 = tail call spir_func <2 x half> @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTDv2_i(<2 x i4> noundef %6) #5 + %10 = tail call spir_func <2 x half> @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTDv2_i(<2 x i4> noundef %8) #5 %11 = fadd <2 x half> %9, %10 %12 = getelementptr inbounds <2 x half>, ptr addrspace(3) %2, i32 %4 store <2 x half> %11, ptr addrspace(3) %12, align 4 @@ -80,8 +80,8 @@ define dso_local spir_func void @__clang_ocl_kern_imp_quant_add(ptr addrspace(3) %6 = load <2 x i4>, ptr addrspace(3) %5, align 1 %7 = getelementptr inbounds i8, ptr addrspace(3) %1, i32 %4 %8 = load <2 x i4>, ptr addrspace(3) %7, align 1 - %9 = tail call spir_func <2 x half> @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELDv2_i(<2 x i4> noundef %6) #5 - %10 = tail call spir_func <2 x half> @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELDv2_i(<2 x i4> noundef %8) #5 + %9 = tail call spir_func <2 x half> @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTDv2_i(<2 x i4> noundef %6) #5 + %10 = tail call spir_func <2 x half> @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTDv2_i(<2 x i4> noundef %8) #5 %11 = fadd <2 x half> %9, %10 %12 = getelementptr inbounds <2 x half>, ptr addrspace(3) %2, i32 %4 store <2 x half> %11, ptr addrspace(3) %12, align 4 @@ -90,7 +90,7 @@ define dso_local spir_func void @__clang_ocl_kern_imp_quant_add(ptr addrspace(3) declare dso_local spir_func i32 @_Z13get_global_idj(i32 noundef) local_unnamed_addr #2 -declare dso_local spir_func <2 x half> @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELDv2_i(<2 x i4> noundef) local_unnamed_addr #3 +declare dso_local spir_func <2 x half> @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTDv2_i(<2 x i4> noundef) local_unnamed_addr #3 attributes #0 = { convergent norecurse nounwind "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size"="false" } attributes #1 = { alwaysinline convergent norecurse nounwind "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size"="false" } diff --git a/test/extensions/INTEL/SPV_INTEL_fp_conversions/spv_intel_fp_conversions.ll b/test/extensions/INTEL/SPV_INTEL_fp_conversions/spv_intel_fp_conversions.ll index 9dc747f312..deaa5c3a0b 100644 --- a/test/extensions/INTEL/SPV_INTEL_fp_conversions/spv_intel_fp_conversions.ll +++ b/test/extensions/INTEL/SPV_INTEL_fp_conversions/spv_intel_fp_conversions.ll @@ -4,7 +4,7 @@ ; Packed and vector conversions are tested for general case, this test is only ; for scalar -; RUN: llvm-spirv %s -o %t.spv --spirv-ext=+SPV_EXT_float8,+SPV_INTEL_float4,+SPV_INTEL_int4,+SPV_KHR_bfloat16,+SPV_INTEL_fp_conversions +; RUN: llvm-spirv %s -o %t.spv --spirv-ext=+SPV_EXT_float8,+SPV_EXT_ocp_microscaling_types,+SPV_INTEL_int4,+SPV_KHR_bfloat16,+SPV_INTEL_fp_conversions ; RUN: llvm-spirv %t.spv -o %t.spt --to-text ; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV ; RUN: llvm-spirv %t.spv -o %t.rev.bc -r @@ -13,12 +13,13 @@ ; CHECK-SPIRV-DAG: Capability Int4TypeINTEL ; CHECK-SPIRV-DAG: Capability Float8EXT +; CHECK-SPIRV-DAG: Capability Float4EXT ; CHECK-SPIRV-DAG: Capability FloatConversionsFtoFINTEL ; CHECK-SPIRV-DAG: Capability FloatConversionsFtoSINTEL ; CHECK-SPIRV-DAG: Extension "SPV_INTEL_int4" ; CHECK-SPIRV-DAG: Extension "SPV_EXT_float8" -; CHECK-SPIRV-DAG: Extension "SPV_INTEL_float4" +; CHECK-SPIRV-DAG: Extension "SPV_EXT_ocp_microscaling_types" ; CHECK-SPIRV-DAG: Extension "SPV_INTEL_fp_conversions" ; CHECK-SPIRV-DAG: Name [[#hf16_hf8_clamp:]] "hf16_hf8_clamp" @@ -60,7 +61,7 @@ ; CHECK-SPIRV-DAG: Constant [[#Int32Ty]] [[#Int32Const:]] 1 ; CHECK-SPIRV-DAG: TypeInt [[#Int4Ty:]] 4 0 -; CHECK-SPIRV-DAG: TypeFloat [[#E2M1Ty:]] 4 6214 +; CHECK-SPIRV-DAG: TypeFloat [[#E2M1Ty:]] 4 4225 ; CHECK-SPIRV-DAG: TypeFloat [[#HFloat8Ty:]] 8 4214 ; CHECK-SPIRV-DAG: TypeFloat [[#BFloat8Ty:]] 8 4215 From 28ac54bd933060a98705c850fdaa03fc6ca0feaf Mon Sep 17 00:00:00 2001 From: "Maksimova, Viktoria" Date: Sat, 4 Jul 2026 04:14:22 -0700 Subject: [PATCH 2/8] Drop the SPV_INTEL_float4 representation of the FP4 E2M1 type Complete the switch to SPV_EXT_ocp_microscaling_types by removing the SPV_INTEL_float4 representation of the FP4 (E2M1) type: the Float4E2M1INTEL encoding (6214) and capability (6212), the INTEL-postfix conversion builtins, and the reader paths that recognized them. FP4 values are now represented exclusively with the Float4E2M1EXT encoding; FP4 matrix operands are still passed as packed integers. Float4E2M1CooperativeMatrixINTEL is retained: it gates FP4 cooperative-matrix component types, which use the Float4E2M1EXT encoding. AI-assisted: Claude Opus 4.8 (commercial SaaS) --- docs/OCPTypesRepresentationInLLVM.rst | 9 +-- lib/SPIRV/SPIRVInternal.h | 13 ---- lib/SPIRV/SPIRVReader.cpp | 10 +-- lib/SPIRV/SPIRVWriter.cpp | 8 +-- lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h | 1 - lib/SPIRV/libSPIRV/SPIRVType.h | 11 +--- lib/SPIRV/libSPIRV/spirv_internal.hpp | 7 --- .../conversions_intel_encoding.ll | 61 ------------------- .../legacy_intel_encoding_read.spt | 36 ----------- 9 files changed, 10 insertions(+), 146 deletions(-) delete mode 100644 test/extensions/INTEL/SPV_INTEL_float4/conversions_intel_encoding.ll delete mode 100644 test/extensions/INTEL/SPV_INTEL_float4/legacy_intel_encoding_read.spt diff --git a/docs/OCPTypesRepresentationInLLVM.rst b/docs/OCPTypesRepresentationInLLVM.rst index 089dc7516a..5f219f7477 100644 --- a/docs/OCPTypesRepresentationInLLVM.rst +++ b/docs/OCPTypesRepresentationInLLVM.rst @@ -41,7 +41,7 @@ Most conversions will be represented by standard SPIR-V conversion instructions *OpConvertUToF*, *OpConvertFToU*, *OpSConvert*), which don't carry information about floating-point value's width and encoding. This document adds a new set of external function calls, each of which has a name that is formed from encoding a specific conversion that it performs. This name has a *__builtin_spirv_* prefix and a postfix indicating the extension (e.g., *EXT* from SPV_EXT_float8 -and SPV_EXT_ocp_microscaling_types, *INTEL* from SPV_INTEL_int4, SPV_INTEL_float4 and SPV_INTEL_fp_conversions). These calls will be translated to SPIR-V conversion +and SPV_EXT_ocp_microscaling_types, *INTEL* from SPV_INTEL_int4 and SPV_INTEL_fp_conversions). These calls will be translated to SPIR-V conversion instructions operating over the appropriate types. These functions are expected to be mangled following Itanium C++ ABI. SPIR-V consumer will apply Itanium mangling during translation to LLVM IR as well. @@ -93,9 +93,6 @@ SPV_EXT_ocp_microscaling_types Conversions __builtin_spirv_ConvertE2M1ToFP16EXT, __builtin_spirv_ConvertE2M1ToBF16EXT, __builtin_spirv_ConvertFP16ToE2M1EXT, __builtin_spirv_ConvertBF16ToE2M1EXT -For backward compatibility the equivalent INTEL-postfix builtins (e.g. *__builtin_spirv_ConvertE2M1ToFP16INTEL*) -are also accepted and map to SPV_INTEL_float4; new producers should use the EXT form above. - SPV_INTEL_fp_conversions ------------------------- @@ -111,8 +108,8 @@ This extension provides conversions with specialized rounding modes for improved The result is decorated with *SaturatedToLargestFloat8NormalConversionEXT* (SPV_EXT_float8). ClampConvert*ToE2M1 builtins are not provided: fp4 (E2M1) saturation is unconditional, -so they collapse into the plain *Convert\*ToE2M1EXT* / *Convert\*ToE2M1INTEL* form listed under -SPV_EXT_ocp_microscaling_types / SPV_INTEL_float4. +so they collapse into the plain *Convert\*ToE2M1EXT* form listed under +SPV_EXT_ocp_microscaling_types. **Translated to OpClampConvertFToSINTEL (clamp rounding to signed integer):** diff --git a/lib/SPIRV/SPIRVInternal.h b/lib/SPIRV/SPIRVInternal.h index b7555e6b52..e1b7aab0d7 100644 --- a/lib/SPIRV/SPIRVInternal.h +++ b/lib/SPIRV/SPIRVInternal.h @@ -1036,7 +1036,6 @@ enum FPEncodingWrap { E4M3 = FPEncoding::FPEncodingFloat8E4M3EXT, E5M2 = FPEncoding::FPEncodingFloat8E5M2EXT, E2M1 = FPEncoding::FPEncodingFloat4E2M1EXT, - E2M1INTEL = internal::FPEncodingFloat4E2M1INTEL, }; // Structure describing non-trivial conversions (FP8, FP4 and int4) @@ -1081,14 +1080,6 @@ template <> inline void FPConvertToEncodingMap::init() { {FPEncodingWrap::E2M1, FPEncodingWrap::IEEE754, OpFConvert}); add("ConvertE2M1ToBF16EXT", {FPEncodingWrap::E2M1, FPEncodingWrap::BF16, OpFConvert}); - add("ConvertE2M1ToE4M3INTEL", - {FPEncodingWrap::E2M1INTEL, FPEncodingWrap::E4M3, OpFConvert}); - add("ConvertE2M1ToE5M2INTEL", - {FPEncodingWrap::E2M1INTEL, FPEncodingWrap::E5M2, OpFConvert}); - add("ConvertE2M1ToFP16INTEL", - {FPEncodingWrap::E2M1INTEL, FPEncodingWrap::IEEE754, OpFConvert}); - add("ConvertE2M1ToBF16INTEL", - {FPEncodingWrap::E2M1INTEL, FPEncodingWrap::BF16, OpFConvert}); add("ConvertInt4ToE4M3INTEL", {FPEncodingWrap::Integer, FPEncodingWrap::E4M3, OpConvertSToF}); @@ -1105,10 +1096,6 @@ template <> inline void FPConvertToEncodingMap::init() { {FPEncodingWrap::IEEE754, FPEncodingWrap::E2M1, OpFConvert}); add("ConvertBF16ToE2M1EXT", {FPEncodingWrap::BF16, FPEncodingWrap::E2M1, OpFConvert}); - add("ConvertFP16ToE2M1INTEL", - {FPEncodingWrap::IEEE754, FPEncodingWrap::E2M1INTEL, OpFConvert}); - add("ConvertBF16ToE2M1INTEL", - {FPEncodingWrap::BF16, FPEncodingWrap::E2M1INTEL, OpFConvert}); add("ConvertFP16ToInt4INTEL", {FPEncodingWrap::IEEE754, FPEncodingWrap::Integer, OpConvertFToS}); add("ConvertBF16ToInt4INTEL", diff --git a/lib/SPIRV/SPIRVReader.cpp b/lib/SPIRV/SPIRVReader.cpp index 3c5b7d3fc0..bdaee852b7 100644 --- a/lib/SPIRV/SPIRVReader.cpp +++ b/lib/SPIRV/SPIRVReader.cpp @@ -1042,9 +1042,7 @@ Value *SPIRVToLLVM::transConvertInst(SPIRVValue *BV, Function *F, auto IsFP4OrFP8Encoding = [](FPEncodingWrap Encoding) -> bool { return Encoding == FPEncodingWrap::E4M3 || - Encoding == FPEncodingWrap::E5M2 || - Encoding == FPEncodingWrap::E2M1 || - Encoding == FPEncodingWrap::E2M1INTEL; + Encoding == FPEncodingWrap::E5M2 || Encoding == FPEncodingWrap::E2M1; }; switch (static_cast(BC->getOpCode())) { @@ -3148,11 +3146,7 @@ Value *SPIRVToLLVM::transValueWithoutDecoration(SPIRVValue *BV, Function *F, InMatrixElementTy->isTypeFloat(8, FPEncodingFloat8E4M3EXT) || InMatrixElementTy->isTypeFloat(8, FPEncodingFloat8E5M2EXT) || OutMatrixElementTy->isTypeFloat(4, FPEncodingFloat4E2M1EXT) || - InMatrixElementTy->isTypeFloat(4, FPEncodingFloat4E2M1EXT) || - OutMatrixElementTy->isTypeFloat( - 4, internal::FPEncodingFloat4E2M1INTEL) || - InMatrixElementTy->isTypeFloat(4, - internal::FPEncodingFloat4E2M1INTEL)) + InMatrixElementTy->isTypeFloat(4, FPEncodingFloat4E2M1EXT)) Inst = transConvertInst(BV, F, BB); else Inst = transSPIRVBuiltinFromInst(BI, BB); diff --git a/lib/SPIRV/SPIRVWriter.cpp b/lib/SPIRV/SPIRVWriter.cpp index 8fe6c9a24b..019178d4ae 100644 --- a/lib/SPIRV/SPIRVWriter.cpp +++ b/lib/SPIRV/SPIRVWriter.cpp @@ -923,13 +923,12 @@ SPIRVFunction *LLVMToSPIRVBase::transFunctionDecl(Function *F) { // generation. if (!BM->isAllowedToUseExtension(ExtensionID::SPV_EXT_float8) && !BM->isAllowedToUseExtension(ExtensionID::SPV_INTEL_int4) && - !BM->isAllowedToUseExtension(ExtensionID::SPV_INTEL_float4) && !BM->isAllowedToUseExtension( ExtensionID::SPV_EXT_ocp_microscaling_types)) { std::string ErrorStr = "One of the following extensions: " "SPV_EXT_float8, SPV_EXT_ocp_microscaling_types, " - "SPV_INTEL_float4, SPV_INTEL_int4 should be enabled to process " + "SPV_INTEL_int4 should be enabled to process " "conversion builtins"; getErrorLog().checkError(false, SPIRVEC_RequiresExtension, F, ErrorStr); } @@ -5720,9 +5719,8 @@ processMiniFPOrInt4Type(Type *LLVMTy, FPEncodingWrap Encoding, unsigned TyWidth = cast(ScalarTy)->getBitWidth(); unsigned VecSize = 0; - bool IsPacked = Encoding == FPEncodingWrap::E2M1 || - Encoding == FPEncodingWrap::E2M1INTEL || - Encoding == FPEncodingWrap::Integer; + bool IsPacked = + Encoding == FPEncodingWrap::E2M1 || Encoding == FPEncodingWrap::Integer; if (IsPacked && (TyWidth == 8 || TyWidth == 16 || TyWidth == 32 || TyWidth == 64)) { // Int4 or FP4 packed in an integer: each N-bit integer holds N/4 values. diff --git a/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h b/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h index 83fc3ec3ab..767a47e5ae 100644 --- a/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h +++ b/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h @@ -702,7 +702,6 @@ template <> inline void SPIRVMap::init() { add(CapabilityFloat8CooperativeMatrixEXT, "Float8CooperativeMatrixEXT"); add(internal::CapabilitySigmoidINTEL, "SigmoidINTEL"); add(internal::CapabilityDeviceBarrierINTEL, "DeviceBarrierINTEL"); - add(internal::CapabilityFloat4E2M1INTEL, "Float4E2M1INTEL"); add(internal::CapabilityFloat4E2M1CooperativeMatrixINTEL, "Float4E2M1CooperativeMatrixINTEL"); add(CapabilityFloat4EXT, "Float4EXT"); diff --git a/lib/SPIRV/libSPIRV/SPIRVType.h b/lib/SPIRV/libSPIRV/SPIRVType.h index 99279b23d4..827f4b679c 100644 --- a/lib/SPIRV/libSPIRV/SPIRVType.h +++ b/lib/SPIRV/libSPIRV/SPIRVType.h @@ -252,8 +252,6 @@ class SPIRVTypeFloat : public SPIRVType { return ExtensionID::SPV_EXT_float8; if (isTypeFloat(4, FPEncodingFloat4E2M1EXT)) return ExtensionID::SPV_EXT_ocp_microscaling_types; - if (isTypeFloat(4, internal::FPEncodingFloat4E2M1INTEL)) - return ExtensionID::SPV_INTEL_float4; return {}; } @@ -274,8 +272,6 @@ class SPIRVTypeFloat : public SPIRVType { CV.push_back(CapabilityFloat8EXT); } else if (isTypeFloat(4, FPEncodingFloat4E2M1EXT)) { CV.push_back(CapabilityFloat4EXT); - } else if (isTypeFloat(4, internal::FPEncodingFloat4E2M1INTEL)) { - CV.push_back(internal::CapabilityFloat4E2M1INTEL); } return CV; } @@ -307,9 +303,7 @@ class SPIRVTypeFloat : public SPIRVType { (BitWidth == 16 && FloatingPointEncoding == FPEncodingBFloat16KHR) || (BitWidth == 8 && FloatingPointEncoding == FPEncodingFloat8E4M3EXT) || (BitWidth == 8 && FloatingPointEncoding == FPEncodingFloat8E5M2EXT) || - (BitWidth == 4 && FloatingPointEncoding == FPEncodingFloat4E2M1EXT) || - (BitWidth == 4 && - FloatingPointEncoding == internal::FPEncodingFloat4E2M1INTEL); + (BitWidth == 4 && FloatingPointEncoding == FPEncodingFloat4E2M1EXT); assert(ValidEncoding && "Invalid floating point encoding"); (void)ValidEncoding; } @@ -1230,8 +1224,7 @@ class SPIRVTypeCooperativeMatrixKHR : public SPIRVType { else if (CompType->isTypeFloat(8, FPEncodingFloat8E4M3EXT) || CompType->isTypeFloat(8, FPEncodingFloat8E5M2EXT)) CV.push_back(CapabilityFloat8CooperativeMatrixEXT); - else if (CompType->isTypeFloat(4, FPEncodingFloat4E2M1EXT) || - CompType->isTypeFloat(4, internal::FPEncodingFloat4E2M1INTEL)) + else if (CompType->isTypeFloat(4, FPEncodingFloat4E2M1EXT)) CV.push_back(internal::CapabilityFloat4E2M1CooperativeMatrixINTEL); return CV; } diff --git a/lib/SPIRV/libSPIRV/spirv_internal.hpp b/lib/SPIRV/libSPIRV/spirv_internal.hpp index ef20f56bb0..2dcbd467d2 100644 --- a/lib/SPIRV/libSPIRV/spirv_internal.hpp +++ b/lib/SPIRV/libSPIRV/spirv_internal.hpp @@ -102,7 +102,6 @@ enum InternalCapability { ICapabilitySigmoidINTEL = 6167, ICapabilityDeviceBarrierINTEL = 6185, ICapabilityCooperativeMatrixCheckedInstructionsINTEL = 6192, - ICapabilityFloat4E2M1INTEL = 6212, ICapabilityFloat4E2M1CooperativeMatrixINTEL = 6213, ICapabilityFloatConversionsFtoFINTEL = 6215, ICapabilityFloatConversionsFtoSINTEL = 6216, @@ -138,11 +137,6 @@ enum InternalJointMatrixLayout { PackedB = 3 }; -enum InternalFPEncoding { - FPEncodingFloat4E2M1INTEL = 6214, - FPEncodingMax = 0x7fffffff, -}; - enum InternalBuiltIn { IBuiltInSubDeviceIDINTEL = 6135, IBuiltInGlobalHWThreadIDINTEL = 6136, @@ -214,7 +208,6 @@ _SPIRV_OP(Capability, AtomicBFloat16MinMaxINTEL) _SPIRV_OP(Capability, SigmoidINTEL) _SPIRV_OP(Op, FSigmoidINTEL) -_SPIRV_OP(Capability, Float4E2M1INTEL) _SPIRV_OP(Capability, Float4E2M1CooperativeMatrixINTEL) _SPIRV_OP(Capability, FloatConversionsFtoFINTEL) diff --git a/test/extensions/INTEL/SPV_INTEL_float4/conversions_intel_encoding.ll b/test/extensions/INTEL/SPV_INTEL_float4/conversions_intel_encoding.ll deleted file mode 100644 index 87e014b512..0000000000 --- a/test/extensions/INTEL/SPV_INTEL_float4/conversions_intel_encoding.ll +++ /dev/null @@ -1,61 +0,0 @@ -; Checks that FP4 (E2M1) conversion builtins with the INTEL postfix are -; translated using the SPV_INTEL_float4 extension: the Float4E2M1INTEL -; encoding (6214) and capability, independently of the Float4E2M1EXT encoding -; from SPV_EXT_ocp_microscaling_types. Round-trips back to the INTEL builtins. - -; RUN: llvm-spirv %s -o %t.spv --spirv-ext=+SPV_INTEL_float4,+SPV_INTEL_int4,+SPV_KHR_bfloat16 -; RUN: llvm-spirv %t.spv -o %t.spt --to-text -; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV -; RUN: llvm-spirv %t.spv -o %t.rev.bc -r --spirv-target-env=SPV-IR -; RUN: llvm-dis %t.rev.bc -o %t.rev.ll -; RUN: FileCheck < %t.rev.ll %s --check-prefix=CHECK-LLVM - -; CHECK-SPIRV-DAG: Capability Int4TypeINTEL -; CHECK-SPIRV-DAG: Capability Float4E2M1INTEL -; CHECK-SPIRV-DAG: Extension "SPV_INTEL_float4" -; CHECK-SPIRV-DAG: Extension "SPV_INTEL_int4" - -; CHECK-SPIRV-DAG: Name [[#fp4e2m1_hf16_scalar:]] "fp4e2m1_hf16_scalar" -; CHECK-SPIRV-DAG: Name [[#hf16_fp4e2m1_scalar:]] "hf16_fp4e2m1_scalar" - -; CHECK-SPIRV-DAG: TypeInt [[#Int4Ty:]] 4 0 -; CHECK-SPIRV-DAG: Constant [[#Int4Ty]] [[#Int4Const:]] 1 -; CHECK-SPIRV-DAG: TypeFloat [[#HFloat16Ty:]] 16 {{$}} -; CHECK-SPIRV-DAG: TypeFloat [[#E2M1Ty:]] 4 6214 - -target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024" -target triple = "spir-unknown-unknown" - -; CHECK-SPIRV: Function [[#]] [[#fp4e2m1_hf16_scalar]] [[#]] -; CHECK-SPIRV: Bitcast [[#E2M1Ty]] [[#Cast:]] [[#Int4Const]] -; CHECK-SPIRV: FConvert [[#HFloat16Ty]] [[#Conv:]] [[#Cast]] -; CHECK-SPIRV: ReturnValue [[#Conv]] - -; CHECK-LLVM-LABEL: fp4e2m1_hf16_scalar -; CHECK-LLVM: %[[#Call:]] = call spir_func half @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELi(i4 1) -; CHECK-LLVM: ret half %[[#Call]] - -define spir_func half @fp4e2m1_hf16_scalar() { -entry: - %0 = call spir_func half @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELi(i4 1) - ret half %0 -} - -declare dso_local spir_func half @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELi(i4) - -; CHECK-SPIRV: Function [[#]] [[#hf16_fp4e2m1_scalar]] [[#]] -; CHECK-SPIRV: FConvert [[#E2M1Ty]] [[#Conv:]] [[#]] -; CHECK-SPIRV: Bitcast [[#Int4Ty]] [[#Cast:]] [[#Conv]] -; CHECK-SPIRV: ReturnValue [[#Cast]] - -; CHECK-LLVM-LABEL: hf16_fp4e2m1_scalar -; CHECK-LLVM: %[[#Call:]] = call spir_func i4 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDh(half 1.000000e+00) -; CHECK-LLVM: ret i4 %[[#Call]] - -define spir_func i4 @hf16_fp4e2m1_scalar() { -entry: - %0 = call spir_func i4 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDh(half 1.0) - ret i4 %0 -} - -declare dso_local spir_func i4 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDh(half) diff --git a/test/extensions/INTEL/SPV_INTEL_float4/legacy_intel_encoding_read.spt b/test/extensions/INTEL/SPV_INTEL_float4/legacy_intel_encoding_read.spt deleted file mode 100644 index 5c76e5350d..0000000000 --- a/test/extensions/INTEL/SPV_INTEL_float4/legacy_intel_encoding_read.spt +++ /dev/null @@ -1,36 +0,0 @@ -; Verify that SPIR-V using the Float4E2M1INTEL encoding (6214) from -; SPV_INTEL_float4 is consumed and round-trips back to the INTEL builtin, -; independently of the Float4E2M1EXT encoding from SPV_EXT_ocp_microscaling_types. - -; RUN: llvm-spirv %s -to-binary -o %t.spv -; RUN: llvm-spirv %t.spv -r --spirv-target-env=SPV-IR -o %t.rev.bc -; RUN: llvm-dis %t.rev.bc -o - | FileCheck %s --check-prefix=CHECK-LLVM - -; CHECK-LLVM: call spir_func half @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELi(i4 1) - -119734787 65536 393230 11 0 -2 Capability Addresses -2 Capability Linkage -2 Capability Kernel -2 Capability Float16Buffer -2 Capability Float4E2M1INTEL -2 Capability Int4TypeINTEL -6 Extension "SPV_INTEL_float4" -5 Extension "SPV_INTEL_int4" -5 ExtInstImport 1 "OpenCL.std" -3 MemoryModel 1 2 -3 Source 0 0 -3 Name 4 "f" -4 Name 5 "entry" -5 Decorate 4 LinkageAttributes "f" Export -4 TypeInt 6 4 0 -4 Constant 6 7 1 -3 TypeFloat 2 16 -3 TypeFunction 3 2 -4 TypeFloat 8 4 6214 -5 Function 2 4 0 3 -2 Label 5 -4 Bitcast 8 9 7 -4 FConvert 2 10 9 -2 ReturnValue 10 -1 FunctionEnd From 64b8507fe9d07fe3cf27dcf4a3a0c53ffc8115d4 Mon Sep 17 00:00:00 2001 From: "Ye, Qi" Date: Wed, 8 Jul 2026 08:06:37 -0700 Subject: [PATCH 3/8] Revert "Drop the SPV_INTEL_float4 representation of the FP4 E2M1 type" This reverts commit 28ac54bd933060a98705c850fdaa03fc6ca0feaf. --- docs/OCPTypesRepresentationInLLVM.rst | 9 ++- lib/SPIRV/SPIRVInternal.h | 13 ++++ lib/SPIRV/SPIRVReader.cpp | 10 ++- lib/SPIRV/SPIRVWriter.cpp | 8 ++- lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h | 1 + lib/SPIRV/libSPIRV/SPIRVType.h | 11 +++- lib/SPIRV/libSPIRV/spirv_internal.hpp | 7 +++ .../conversions_intel_encoding.ll | 61 +++++++++++++++++++ .../legacy_intel_encoding_read.spt | 36 +++++++++++ 9 files changed, 146 insertions(+), 10 deletions(-) create mode 100644 test/extensions/INTEL/SPV_INTEL_float4/conversions_intel_encoding.ll create mode 100644 test/extensions/INTEL/SPV_INTEL_float4/legacy_intel_encoding_read.spt diff --git a/docs/OCPTypesRepresentationInLLVM.rst b/docs/OCPTypesRepresentationInLLVM.rst index 5f219f7477..089dc7516a 100644 --- a/docs/OCPTypesRepresentationInLLVM.rst +++ b/docs/OCPTypesRepresentationInLLVM.rst @@ -41,7 +41,7 @@ Most conversions will be represented by standard SPIR-V conversion instructions *OpConvertUToF*, *OpConvertFToU*, *OpSConvert*), which don't carry information about floating-point value's width and encoding. This document adds a new set of external function calls, each of which has a name that is formed from encoding a specific conversion that it performs. This name has a *__builtin_spirv_* prefix and a postfix indicating the extension (e.g., *EXT* from SPV_EXT_float8 -and SPV_EXT_ocp_microscaling_types, *INTEL* from SPV_INTEL_int4 and SPV_INTEL_fp_conversions). These calls will be translated to SPIR-V conversion +and SPV_EXT_ocp_microscaling_types, *INTEL* from SPV_INTEL_int4, SPV_INTEL_float4 and SPV_INTEL_fp_conversions). These calls will be translated to SPIR-V conversion instructions operating over the appropriate types. These functions are expected to be mangled following Itanium C++ ABI. SPIR-V consumer will apply Itanium mangling during translation to LLVM IR as well. @@ -93,6 +93,9 @@ SPV_EXT_ocp_microscaling_types Conversions __builtin_spirv_ConvertE2M1ToFP16EXT, __builtin_spirv_ConvertE2M1ToBF16EXT, __builtin_spirv_ConvertFP16ToE2M1EXT, __builtin_spirv_ConvertBF16ToE2M1EXT +For backward compatibility the equivalent INTEL-postfix builtins (e.g. *__builtin_spirv_ConvertE2M1ToFP16INTEL*) +are also accepted and map to SPV_INTEL_float4; new producers should use the EXT form above. + SPV_INTEL_fp_conversions ------------------------- @@ -108,8 +111,8 @@ This extension provides conversions with specialized rounding modes for improved The result is decorated with *SaturatedToLargestFloat8NormalConversionEXT* (SPV_EXT_float8). ClampConvert*ToE2M1 builtins are not provided: fp4 (E2M1) saturation is unconditional, -so they collapse into the plain *Convert\*ToE2M1EXT* form listed under -SPV_EXT_ocp_microscaling_types. +so they collapse into the plain *Convert\*ToE2M1EXT* / *Convert\*ToE2M1INTEL* form listed under +SPV_EXT_ocp_microscaling_types / SPV_INTEL_float4. **Translated to OpClampConvertFToSINTEL (clamp rounding to signed integer):** diff --git a/lib/SPIRV/SPIRVInternal.h b/lib/SPIRV/SPIRVInternal.h index e1b7aab0d7..b7555e6b52 100644 --- a/lib/SPIRV/SPIRVInternal.h +++ b/lib/SPIRV/SPIRVInternal.h @@ -1036,6 +1036,7 @@ enum FPEncodingWrap { E4M3 = FPEncoding::FPEncodingFloat8E4M3EXT, E5M2 = FPEncoding::FPEncodingFloat8E5M2EXT, E2M1 = FPEncoding::FPEncodingFloat4E2M1EXT, + E2M1INTEL = internal::FPEncodingFloat4E2M1INTEL, }; // Structure describing non-trivial conversions (FP8, FP4 and int4) @@ -1080,6 +1081,14 @@ template <> inline void FPConvertToEncodingMap::init() { {FPEncodingWrap::E2M1, FPEncodingWrap::IEEE754, OpFConvert}); add("ConvertE2M1ToBF16EXT", {FPEncodingWrap::E2M1, FPEncodingWrap::BF16, OpFConvert}); + add("ConvertE2M1ToE4M3INTEL", + {FPEncodingWrap::E2M1INTEL, FPEncodingWrap::E4M3, OpFConvert}); + add("ConvertE2M1ToE5M2INTEL", + {FPEncodingWrap::E2M1INTEL, FPEncodingWrap::E5M2, OpFConvert}); + add("ConvertE2M1ToFP16INTEL", + {FPEncodingWrap::E2M1INTEL, FPEncodingWrap::IEEE754, OpFConvert}); + add("ConvertE2M1ToBF16INTEL", + {FPEncodingWrap::E2M1INTEL, FPEncodingWrap::BF16, OpFConvert}); add("ConvertInt4ToE4M3INTEL", {FPEncodingWrap::Integer, FPEncodingWrap::E4M3, OpConvertSToF}); @@ -1096,6 +1105,10 @@ template <> inline void FPConvertToEncodingMap::init() { {FPEncodingWrap::IEEE754, FPEncodingWrap::E2M1, OpFConvert}); add("ConvertBF16ToE2M1EXT", {FPEncodingWrap::BF16, FPEncodingWrap::E2M1, OpFConvert}); + add("ConvertFP16ToE2M1INTEL", + {FPEncodingWrap::IEEE754, FPEncodingWrap::E2M1INTEL, OpFConvert}); + add("ConvertBF16ToE2M1INTEL", + {FPEncodingWrap::BF16, FPEncodingWrap::E2M1INTEL, OpFConvert}); add("ConvertFP16ToInt4INTEL", {FPEncodingWrap::IEEE754, FPEncodingWrap::Integer, OpConvertFToS}); add("ConvertBF16ToInt4INTEL", diff --git a/lib/SPIRV/SPIRVReader.cpp b/lib/SPIRV/SPIRVReader.cpp index bdaee852b7..3c5b7d3fc0 100644 --- a/lib/SPIRV/SPIRVReader.cpp +++ b/lib/SPIRV/SPIRVReader.cpp @@ -1042,7 +1042,9 @@ Value *SPIRVToLLVM::transConvertInst(SPIRVValue *BV, Function *F, auto IsFP4OrFP8Encoding = [](FPEncodingWrap Encoding) -> bool { return Encoding == FPEncodingWrap::E4M3 || - Encoding == FPEncodingWrap::E5M2 || Encoding == FPEncodingWrap::E2M1; + Encoding == FPEncodingWrap::E5M2 || + Encoding == FPEncodingWrap::E2M1 || + Encoding == FPEncodingWrap::E2M1INTEL; }; switch (static_cast(BC->getOpCode())) { @@ -3146,7 +3148,11 @@ Value *SPIRVToLLVM::transValueWithoutDecoration(SPIRVValue *BV, Function *F, InMatrixElementTy->isTypeFloat(8, FPEncodingFloat8E4M3EXT) || InMatrixElementTy->isTypeFloat(8, FPEncodingFloat8E5M2EXT) || OutMatrixElementTy->isTypeFloat(4, FPEncodingFloat4E2M1EXT) || - InMatrixElementTy->isTypeFloat(4, FPEncodingFloat4E2M1EXT)) + InMatrixElementTy->isTypeFloat(4, FPEncodingFloat4E2M1EXT) || + OutMatrixElementTy->isTypeFloat( + 4, internal::FPEncodingFloat4E2M1INTEL) || + InMatrixElementTy->isTypeFloat(4, + internal::FPEncodingFloat4E2M1INTEL)) Inst = transConvertInst(BV, F, BB); else Inst = transSPIRVBuiltinFromInst(BI, BB); diff --git a/lib/SPIRV/SPIRVWriter.cpp b/lib/SPIRV/SPIRVWriter.cpp index 019178d4ae..8fe6c9a24b 100644 --- a/lib/SPIRV/SPIRVWriter.cpp +++ b/lib/SPIRV/SPIRVWriter.cpp @@ -923,12 +923,13 @@ SPIRVFunction *LLVMToSPIRVBase::transFunctionDecl(Function *F) { // generation. if (!BM->isAllowedToUseExtension(ExtensionID::SPV_EXT_float8) && !BM->isAllowedToUseExtension(ExtensionID::SPV_INTEL_int4) && + !BM->isAllowedToUseExtension(ExtensionID::SPV_INTEL_float4) && !BM->isAllowedToUseExtension( ExtensionID::SPV_EXT_ocp_microscaling_types)) { std::string ErrorStr = "One of the following extensions: " "SPV_EXT_float8, SPV_EXT_ocp_microscaling_types, " - "SPV_INTEL_int4 should be enabled to process " + "SPV_INTEL_float4, SPV_INTEL_int4 should be enabled to process " "conversion builtins"; getErrorLog().checkError(false, SPIRVEC_RequiresExtension, F, ErrorStr); } @@ -5719,8 +5720,9 @@ processMiniFPOrInt4Type(Type *LLVMTy, FPEncodingWrap Encoding, unsigned TyWidth = cast(ScalarTy)->getBitWidth(); unsigned VecSize = 0; - bool IsPacked = - Encoding == FPEncodingWrap::E2M1 || Encoding == FPEncodingWrap::Integer; + bool IsPacked = Encoding == FPEncodingWrap::E2M1 || + Encoding == FPEncodingWrap::E2M1INTEL || + Encoding == FPEncodingWrap::Integer; if (IsPacked && (TyWidth == 8 || TyWidth == 16 || TyWidth == 32 || TyWidth == 64)) { // Int4 or FP4 packed in an integer: each N-bit integer holds N/4 values. diff --git a/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h b/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h index 767a47e5ae..83fc3ec3ab 100644 --- a/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h +++ b/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h @@ -702,6 +702,7 @@ template <> inline void SPIRVMap::init() { add(CapabilityFloat8CooperativeMatrixEXT, "Float8CooperativeMatrixEXT"); add(internal::CapabilitySigmoidINTEL, "SigmoidINTEL"); add(internal::CapabilityDeviceBarrierINTEL, "DeviceBarrierINTEL"); + add(internal::CapabilityFloat4E2M1INTEL, "Float4E2M1INTEL"); add(internal::CapabilityFloat4E2M1CooperativeMatrixINTEL, "Float4E2M1CooperativeMatrixINTEL"); add(CapabilityFloat4EXT, "Float4EXT"); diff --git a/lib/SPIRV/libSPIRV/SPIRVType.h b/lib/SPIRV/libSPIRV/SPIRVType.h index 827f4b679c..99279b23d4 100644 --- a/lib/SPIRV/libSPIRV/SPIRVType.h +++ b/lib/SPIRV/libSPIRV/SPIRVType.h @@ -252,6 +252,8 @@ class SPIRVTypeFloat : public SPIRVType { return ExtensionID::SPV_EXT_float8; if (isTypeFloat(4, FPEncodingFloat4E2M1EXT)) return ExtensionID::SPV_EXT_ocp_microscaling_types; + if (isTypeFloat(4, internal::FPEncodingFloat4E2M1INTEL)) + return ExtensionID::SPV_INTEL_float4; return {}; } @@ -272,6 +274,8 @@ class SPIRVTypeFloat : public SPIRVType { CV.push_back(CapabilityFloat8EXT); } else if (isTypeFloat(4, FPEncodingFloat4E2M1EXT)) { CV.push_back(CapabilityFloat4EXT); + } else if (isTypeFloat(4, internal::FPEncodingFloat4E2M1INTEL)) { + CV.push_back(internal::CapabilityFloat4E2M1INTEL); } return CV; } @@ -303,7 +307,9 @@ class SPIRVTypeFloat : public SPIRVType { (BitWidth == 16 && FloatingPointEncoding == FPEncodingBFloat16KHR) || (BitWidth == 8 && FloatingPointEncoding == FPEncodingFloat8E4M3EXT) || (BitWidth == 8 && FloatingPointEncoding == FPEncodingFloat8E5M2EXT) || - (BitWidth == 4 && FloatingPointEncoding == FPEncodingFloat4E2M1EXT); + (BitWidth == 4 && FloatingPointEncoding == FPEncodingFloat4E2M1EXT) || + (BitWidth == 4 && + FloatingPointEncoding == internal::FPEncodingFloat4E2M1INTEL); assert(ValidEncoding && "Invalid floating point encoding"); (void)ValidEncoding; } @@ -1224,7 +1230,8 @@ class SPIRVTypeCooperativeMatrixKHR : public SPIRVType { else if (CompType->isTypeFloat(8, FPEncodingFloat8E4M3EXT) || CompType->isTypeFloat(8, FPEncodingFloat8E5M2EXT)) CV.push_back(CapabilityFloat8CooperativeMatrixEXT); - else if (CompType->isTypeFloat(4, FPEncodingFloat4E2M1EXT)) + else if (CompType->isTypeFloat(4, FPEncodingFloat4E2M1EXT) || + CompType->isTypeFloat(4, internal::FPEncodingFloat4E2M1INTEL)) CV.push_back(internal::CapabilityFloat4E2M1CooperativeMatrixINTEL); return CV; } diff --git a/lib/SPIRV/libSPIRV/spirv_internal.hpp b/lib/SPIRV/libSPIRV/spirv_internal.hpp index 2dcbd467d2..ef20f56bb0 100644 --- a/lib/SPIRV/libSPIRV/spirv_internal.hpp +++ b/lib/SPIRV/libSPIRV/spirv_internal.hpp @@ -102,6 +102,7 @@ enum InternalCapability { ICapabilitySigmoidINTEL = 6167, ICapabilityDeviceBarrierINTEL = 6185, ICapabilityCooperativeMatrixCheckedInstructionsINTEL = 6192, + ICapabilityFloat4E2M1INTEL = 6212, ICapabilityFloat4E2M1CooperativeMatrixINTEL = 6213, ICapabilityFloatConversionsFtoFINTEL = 6215, ICapabilityFloatConversionsFtoSINTEL = 6216, @@ -137,6 +138,11 @@ enum InternalJointMatrixLayout { PackedB = 3 }; +enum InternalFPEncoding { + FPEncodingFloat4E2M1INTEL = 6214, + FPEncodingMax = 0x7fffffff, +}; + enum InternalBuiltIn { IBuiltInSubDeviceIDINTEL = 6135, IBuiltInGlobalHWThreadIDINTEL = 6136, @@ -208,6 +214,7 @@ _SPIRV_OP(Capability, AtomicBFloat16MinMaxINTEL) _SPIRV_OP(Capability, SigmoidINTEL) _SPIRV_OP(Op, FSigmoidINTEL) +_SPIRV_OP(Capability, Float4E2M1INTEL) _SPIRV_OP(Capability, Float4E2M1CooperativeMatrixINTEL) _SPIRV_OP(Capability, FloatConversionsFtoFINTEL) diff --git a/test/extensions/INTEL/SPV_INTEL_float4/conversions_intel_encoding.ll b/test/extensions/INTEL/SPV_INTEL_float4/conversions_intel_encoding.ll new file mode 100644 index 0000000000..87e014b512 --- /dev/null +++ b/test/extensions/INTEL/SPV_INTEL_float4/conversions_intel_encoding.ll @@ -0,0 +1,61 @@ +; Checks that FP4 (E2M1) conversion builtins with the INTEL postfix are +; translated using the SPV_INTEL_float4 extension: the Float4E2M1INTEL +; encoding (6214) and capability, independently of the Float4E2M1EXT encoding +; from SPV_EXT_ocp_microscaling_types. Round-trips back to the INTEL builtins. + +; RUN: llvm-spirv %s -o %t.spv --spirv-ext=+SPV_INTEL_float4,+SPV_INTEL_int4,+SPV_KHR_bfloat16 +; RUN: llvm-spirv %t.spv -o %t.spt --to-text +; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV +; RUN: llvm-spirv %t.spv -o %t.rev.bc -r --spirv-target-env=SPV-IR +; RUN: llvm-dis %t.rev.bc -o %t.rev.ll +; RUN: FileCheck < %t.rev.ll %s --check-prefix=CHECK-LLVM + +; CHECK-SPIRV-DAG: Capability Int4TypeINTEL +; CHECK-SPIRV-DAG: Capability Float4E2M1INTEL +; CHECK-SPIRV-DAG: Extension "SPV_INTEL_float4" +; CHECK-SPIRV-DAG: Extension "SPV_INTEL_int4" + +; CHECK-SPIRV-DAG: Name [[#fp4e2m1_hf16_scalar:]] "fp4e2m1_hf16_scalar" +; CHECK-SPIRV-DAG: Name [[#hf16_fp4e2m1_scalar:]] "hf16_fp4e2m1_scalar" + +; CHECK-SPIRV-DAG: TypeInt [[#Int4Ty:]] 4 0 +; CHECK-SPIRV-DAG: Constant [[#Int4Ty]] [[#Int4Const:]] 1 +; CHECK-SPIRV-DAG: TypeFloat [[#HFloat16Ty:]] 16 {{$}} +; CHECK-SPIRV-DAG: TypeFloat [[#E2M1Ty:]] 4 6214 + +target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024" +target triple = "spir-unknown-unknown" + +; CHECK-SPIRV: Function [[#]] [[#fp4e2m1_hf16_scalar]] [[#]] +; CHECK-SPIRV: Bitcast [[#E2M1Ty]] [[#Cast:]] [[#Int4Const]] +; CHECK-SPIRV: FConvert [[#HFloat16Ty]] [[#Conv:]] [[#Cast]] +; CHECK-SPIRV: ReturnValue [[#Conv]] + +; CHECK-LLVM-LABEL: fp4e2m1_hf16_scalar +; CHECK-LLVM: %[[#Call:]] = call spir_func half @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELi(i4 1) +; CHECK-LLVM: ret half %[[#Call]] + +define spir_func half @fp4e2m1_hf16_scalar() { +entry: + %0 = call spir_func half @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELi(i4 1) + ret half %0 +} + +declare dso_local spir_func half @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELi(i4) + +; CHECK-SPIRV: Function [[#]] [[#hf16_fp4e2m1_scalar]] [[#]] +; CHECK-SPIRV: FConvert [[#E2M1Ty]] [[#Conv:]] [[#]] +; CHECK-SPIRV: Bitcast [[#Int4Ty]] [[#Cast:]] [[#Conv]] +; CHECK-SPIRV: ReturnValue [[#Cast]] + +; CHECK-LLVM-LABEL: hf16_fp4e2m1_scalar +; CHECK-LLVM: %[[#Call:]] = call spir_func i4 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDh(half 1.000000e+00) +; CHECK-LLVM: ret i4 %[[#Call]] + +define spir_func i4 @hf16_fp4e2m1_scalar() { +entry: + %0 = call spir_func i4 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDh(half 1.0) + ret i4 %0 +} + +declare dso_local spir_func i4 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDh(half) diff --git a/test/extensions/INTEL/SPV_INTEL_float4/legacy_intel_encoding_read.spt b/test/extensions/INTEL/SPV_INTEL_float4/legacy_intel_encoding_read.spt new file mode 100644 index 0000000000..5c76e5350d --- /dev/null +++ b/test/extensions/INTEL/SPV_INTEL_float4/legacy_intel_encoding_read.spt @@ -0,0 +1,36 @@ +; Verify that SPIR-V using the Float4E2M1INTEL encoding (6214) from +; SPV_INTEL_float4 is consumed and round-trips back to the INTEL builtin, +; independently of the Float4E2M1EXT encoding from SPV_EXT_ocp_microscaling_types. + +; RUN: llvm-spirv %s -to-binary -o %t.spv +; RUN: llvm-spirv %t.spv -r --spirv-target-env=SPV-IR -o %t.rev.bc +; RUN: llvm-dis %t.rev.bc -o - | FileCheck %s --check-prefix=CHECK-LLVM + +; CHECK-LLVM: call spir_func half @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELi(i4 1) + +119734787 65536 393230 11 0 +2 Capability Addresses +2 Capability Linkage +2 Capability Kernel +2 Capability Float16Buffer +2 Capability Float4E2M1INTEL +2 Capability Int4TypeINTEL +6 Extension "SPV_INTEL_float4" +5 Extension "SPV_INTEL_int4" +5 ExtInstImport 1 "OpenCL.std" +3 MemoryModel 1 2 +3 Source 0 0 +3 Name 4 "f" +4 Name 5 "entry" +5 Decorate 4 LinkageAttributes "f" Export +4 TypeInt 6 4 0 +4 Constant 6 7 1 +3 TypeFloat 2 16 +3 TypeFunction 3 2 +4 TypeFloat 8 4 6214 +5 Function 2 4 0 3 +2 Label 5 +4 Bitcast 8 9 7 +4 FConvert 2 10 9 +2 ReturnValue 10 +1 FunctionEnd From b5a581ea23f280d507874faa9860e47cbeebb449 Mon Sep 17 00:00:00 2001 From: "Ye, Qi" Date: Fri, 10 Jul 2026 08:33:14 -0700 Subject: [PATCH 4/8] Improve tests --- .../conversions_both_encodings.ll | 58 +++++++++++++++++ .../conversions_cooperative_matrix.ll | 65 +++++++++++++++++++ .../conversions_packed.ll | 1 + .../conversions_scalar_vector.ll | 1 + .../negative/no-intel-float4.ll | 18 +++++ .../negative/no-microscaling-ext.ll | 18 +++++ .../upscale_o0.ll | 1 + .../upscale_o2.ll | 1 + .../conversions_intel_encoding.ll | 2 + 9 files changed, 165 insertions(+) create mode 100644 test/extensions/EXT/SPV_EXT_ocp_microscaling_types/conversions_both_encodings.ll create mode 100644 test/extensions/EXT/SPV_EXT_ocp_microscaling_types/conversions_cooperative_matrix.ll rename test/extensions/{INTEL/SPV_INTEL_float4 => EXT/SPV_EXT_ocp_microscaling_types}/conversions_packed.ll (99%) rename test/extensions/{INTEL/SPV_INTEL_float4 => EXT/SPV_EXT_ocp_microscaling_types}/conversions_scalar_vector.ll (99%) create mode 100644 test/extensions/EXT/SPV_EXT_ocp_microscaling_types/negative/no-intel-float4.ll create mode 100644 test/extensions/EXT/SPV_EXT_ocp_microscaling_types/negative/no-microscaling-ext.ll rename test/extensions/{INTEL/SPV_INTEL_float4 => EXT/SPV_EXT_ocp_microscaling_types}/upscale_o0.ll (99%) rename test/extensions/{INTEL/SPV_INTEL_float4 => EXT/SPV_EXT_ocp_microscaling_types}/upscale_o2.ll (99%) diff --git a/test/extensions/EXT/SPV_EXT_ocp_microscaling_types/conversions_both_encodings.ll b/test/extensions/EXT/SPV_EXT_ocp_microscaling_types/conversions_both_encodings.ll new file mode 100644 index 0000000000..420d6fa129 --- /dev/null +++ b/test/extensions/EXT/SPV_EXT_ocp_microscaling_types/conversions_both_encodings.ll @@ -0,0 +1,58 @@ +; Checks that both the EXT builtins (SPV_EXT_ocp_microscaling_types, +; Float4E2M1EXT encoding 4225) and the INTEL builtins (SPV_INTEL_float4, +; Float4E2M1INTEL encoding 6214) can coexist in one module with both +; extensions enabled, and that each conversion round-trips back to its own +; builtin. + +; RUN: llvm-spirv %s -o %t.spv --spirv-ext=+SPV_INTEL_float4,+SPV_EXT_ocp_microscaling_types,+SPV_INTEL_int4 +; TODO: re-enable spirv-val once it can recognize Float4E2M1INTEL capability (6212). +; RUNx: spirv-val %t.spv +; RUN: llvm-spirv %t.spv -o %t.spt --to-text +; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV +; RUN: llvm-spirv %t.spv -o %t.rev.bc -r --spirv-target-env=SPV-IR +; RUN: llvm-dis %t.rev.bc -o %t.rev.ll +; RUN: FileCheck < %t.rev.ll %s --check-prefix=CHECK-LLVM + +; CHECK-SPIRV-DAG: Capability Float4EXT +; CHECK-SPIRV-DAG: Capability Float4E2M1INTEL +; CHECK-SPIRV-DAG: Extension "SPV_EXT_ocp_microscaling_types" +; CHECK-SPIRV-DAG: Extension "SPV_INTEL_float4" + +; CHECK-SPIRV-DAG: Name [[#ext_conv:]] "ext_conv" +; CHECK-SPIRV-DAG: Name [[#intel_conv:]] "intel_conv" + +; CHECK-SPIRV-DAG: TypeFloat [[#E2M1ExtTy:]] 4 4225 +; CHECK-SPIRV-DAG: TypeFloat [[#E2M1IntelTy:]] 4 6214 + +target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024" +target triple = "spir-unknown-unknown" + +; CHECK-SPIRV: Function [[#]] [[#ext_conv]] [[#]] +; CHECK-SPIRV: Bitcast [[#E2M1ExtTy]] [[#ExtCast:]] [[#]] +; CHECK-SPIRV: FConvert [[#]] [[#]] [[#ExtCast]] + +; CHECK-LLVM-LABEL: ext_conv +; CHECK-LLVM: call spir_func half @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTi(i4 1) + +define spir_func half @ext_conv() { +entry: + %r = call spir_func half @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTi(i4 1) + ret half %r +} + +declare dso_local spir_func half @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTi(i4) + +; CHECK-SPIRV: Function [[#]] [[#intel_conv]] [[#]] +; CHECK-SPIRV: Bitcast [[#E2M1IntelTy]] [[#IntelCast:]] [[#]] +; CHECK-SPIRV: FConvert [[#]] [[#]] [[#IntelCast]] + +; CHECK-LLVM-LABEL: intel_conv +; CHECK-LLVM: call spir_func half @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELi(i4 1) + +define spir_func half @intel_conv() { +entry: + %r = call spir_func half @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELi(i4 1) + ret half %r +} + +declare dso_local spir_func half @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELi(i4) diff --git a/test/extensions/EXT/SPV_EXT_ocp_microscaling_types/conversions_cooperative_matrix.ll b/test/extensions/EXT/SPV_EXT_ocp_microscaling_types/conversions_cooperative_matrix.ll new file mode 100644 index 0000000000..e2b14cb8d1 --- /dev/null +++ b/test/extensions/EXT/SPV_EXT_ocp_microscaling_types/conversions_cooperative_matrix.ll @@ -0,0 +1,65 @@ +; Checks that Float4E2M1EXT works as a cooperative-matrix component type: an +; fp16 cooperative matrix is converted to an FP4 (E2M1) cooperative matrix and +; the conversion round-trips back to the __builtin_spirv_ConvertFP16ToE2M1EXT +; builtin. + +; RUN: llvm-spirv %s -o %t.spv --spirv-ext=+SPV_EXT_ocp_microscaling_types,+SPV_KHR_cooperative_matrix,+SPV_INTEL_int4 +; TODO: re-enable spirv-val once it can recognize Float4E2M1CooperativeMatrixINTEL capability (6213). +; RUNx: spirv-val %t.spv +; RUN: llvm-spirv %t.spv -o %t.spt --to-text +; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV +; RUN: llvm-spirv %t.spv -o %t.rev.bc -r --spirv-target-env=SPV-IR +; RUN: llvm-dis %t.rev.bc -o %t.rev.ll +; RUN: FileCheck < %t.rev.ll %s --check-prefix=CHECK-LLVM + +; CHECK-SPIRV-DAG: Capability CooperativeMatrixKHR +; CHECK-SPIRV-DAG: Capability Float4EXT +; CHECK-SPIRV-DAG: Capability Float4E2M1CooperativeMatrixINTEL +; CHECK-SPIRV-DAG: Extension "SPV_EXT_ocp_microscaling_types" +; CHECK-SPIRV-DAG: Extension "SPV_KHR_cooperative_matrix" + +; CHECK-SPIRV-DAG: TypeInt [[#Int4Ty:]] 4 0 +; CHECK-SPIRV-DAG: TypeFloat [[#FP16Ty:]] 16 +; CHECK-SPIRV-DAG: TypeFloat [[#FP4Ty:]] 4 4225 +; CHECK-SPIRV-DAG: TypeCooperativeMatrixKHR [[#Int4MatrixTy:]] [[#Int4Ty]] +; CHECK-SPIRV-DAG: TypeCooperativeMatrixKHR [[#FP16MatrixTy:]] [[#FP16Ty]] +; CHECK-SPIRV-DAG: TypeCooperativeMatrixKHR [[#FP4MatrixTy:]] [[#FP4Ty]] + +; CHECK-SPIRV: CompositeConstruct [[#FP16MatrixTy]] [[#M:]] [[#]] +; CHECK-SPIRV: FConvert [[#FP4MatrixTy]] [[#Conv:]] [[#M]] +; CHECK-SPIRV: Bitcast [[#Int4MatrixTy]] [[#]] [[#Conv]] + +; CHECK-LLVM: %[[#M:]] = call spir_func target("spirv.CooperativeMatrixKHR", half, 3, 12, 12, 2) @_Z26__spirv_CompositeConstructDh(half 0.000000e+00) +; CHECK-LLVM: call spir_func target("spirv.CooperativeMatrixKHR", i4, 3, 12, 12, 2) @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTPU3AS144__spirv_CooperativeMatrixKHR__half_3_12_12_2(target("spirv.CooperativeMatrixKHR", half, 3, 12, 12, 2) %[[#M]]) + +; ModuleID = 'test.bc' +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-G1" +target triple = "spir-unknown-unknown" + +; Function Attrs: nounwind +define spir_func void @fp16_fp4_matrix() #0 { +entry: + %0 = call spir_func target("spirv.CooperativeMatrixKHR", half, 3, 12, 12, 2) @_Z26__spirv_CompositeConstructDh(half 0.0) #0 + %1 = call spir_func target("spirv.CooperativeMatrixKHR", i4, 3, 12, 12, 2) @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTPU3AS144__spirv_CooperativeMatrixKHR__half_3_12_12_2(target("spirv.CooperativeMatrixKHR", half, 3, 12, 12, 2) %0) + ret void +} + +; Function Attrs: nounwind +declare spir_func target("spirv.CooperativeMatrixKHR", half, 3, 12, 12, 2) @_Z26__spirv_CompositeConstructDh(half) #0 + +declare spir_func target("spirv.CooperativeMatrixKHR", i4, 3, 12, 12, 2) @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTPU3AS144__spirv_CooperativeMatrixKHR__half_3_12_12_2(target("spirv.CooperativeMatrixKHR", half, 3, 12, 12, 2)) + +attributes #0 = { nounwind } + +!spirv.MemoryModel = !{!0} +!opencl.enable.FP_CONTRACT = !{} +!spirv.Source = !{!1} +!opencl.spir.version = !{!0} +!opencl.used.extensions = !{!2} +!opencl.used.optional.core.features = !{!2} +!spirv.Generator = !{!3} + +!0 = !{i32 1, i32 2} +!1 = !{i32 0, i32 0} +!2 = !{} +!3 = !{i16 6, i16 14} diff --git a/test/extensions/INTEL/SPV_INTEL_float4/conversions_packed.ll b/test/extensions/EXT/SPV_EXT_ocp_microscaling_types/conversions_packed.ll similarity index 99% rename from test/extensions/INTEL/SPV_INTEL_float4/conversions_packed.ll rename to test/extensions/EXT/SPV_EXT_ocp_microscaling_types/conversions_packed.ll index 17d04de69d..8dd8424bbc 100644 --- a/test/extensions/INTEL/SPV_INTEL_float4/conversions_packed.ll +++ b/test/extensions/EXT/SPV_EXT_ocp_microscaling_types/conversions_packed.ll @@ -16,6 +16,7 @@ ; e. packed in vector of 8-bit integers ; RUN: llvm-spirv %s -o %t.spv --spirv-ext=+SPV_EXT_float8,+SPV_EXT_ocp_microscaling_types,+SPV_INTEL_int4,+SPV_KHR_bfloat16 +; RUN: spirv-val %t.spv ; RUN: llvm-spirv %t.spv -o %t.spt --to-text ; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV ; RUN: llvm-spirv %t.spv -o %t.rev.bc -r --spirv-target-env=SPV-IR diff --git a/test/extensions/INTEL/SPV_INTEL_float4/conversions_scalar_vector.ll b/test/extensions/EXT/SPV_EXT_ocp_microscaling_types/conversions_scalar_vector.ll similarity index 99% rename from test/extensions/INTEL/SPV_INTEL_float4/conversions_scalar_vector.ll rename to test/extensions/EXT/SPV_EXT_ocp_microscaling_types/conversions_scalar_vector.ll index c5a3855696..de0ef5ba02 100644 --- a/test/extensions/INTEL/SPV_INTEL_float4/conversions_scalar_vector.ll +++ b/test/extensions/EXT/SPV_EXT_ocp_microscaling_types/conversions_scalar_vector.ll @@ -4,6 +4,7 @@ ; file). ; RUN: llvm-spirv %s -o %t.spv --spirv-ext=+SPV_EXT_float8,+SPV_EXT_ocp_microscaling_types,+SPV_INTEL_int4,+SPV_KHR_bfloat16 +; RUN: spirv-val %t.spv ; RUN: llvm-spirv %t.spv -o %t.spt --to-text ; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV ; RUN: llvm-spirv %t.spv -o %t.rev.bc -r --spirv-target-env=SPV-IR diff --git a/test/extensions/EXT/SPV_EXT_ocp_microscaling_types/negative/no-intel-float4.ll b/test/extensions/EXT/SPV_EXT_ocp_microscaling_types/negative/no-intel-float4.ll new file mode 100644 index 0000000000..7410952123 --- /dev/null +++ b/test/extensions/EXT/SPV_EXT_ocp_microscaling_types/negative/no-intel-float4.ll @@ -0,0 +1,18 @@ +; Checks that an *INTEL FP4 conversion builtin fails to translate when +; SPV_INTEL_float4 is not enabled. + +; RUN: not llvm-spirv %s -o %t.spv --spirv-ext=+SPV_INTEL_int4 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR + +; CHECK-ERROR: RequiresExtension: Feature requires the following SPIR-V extension: +; CHECK-ERROR-NEXT: SPV_INTEL_float4 + +target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024" +target triple = "spir-unknown-unknown" + +define spir_func half @intel_conv() { +entry: + %r = call spir_func half @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELi(i4 1) + ret half %r +} + +declare dso_local spir_func half @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELi(i4) diff --git a/test/extensions/EXT/SPV_EXT_ocp_microscaling_types/negative/no-microscaling-ext.ll b/test/extensions/EXT/SPV_EXT_ocp_microscaling_types/negative/no-microscaling-ext.ll new file mode 100644 index 0000000000..e19e540bb1 --- /dev/null +++ b/test/extensions/EXT/SPV_EXT_ocp_microscaling_types/negative/no-microscaling-ext.ll @@ -0,0 +1,18 @@ +; Checks that an *EXT FP4 conversion builtin fails to translate when +; SPV_EXT_ocp_microscaling_types is not enabled. + +; RUN: not llvm-spirv %s -o %t.spv --spirv-ext=+SPV_INTEL_int4 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR + +; CHECK-ERROR: RequiresExtension: Feature requires the following SPIR-V extension: +; CHECK-ERROR-NEXT: SPV_EXT_ocp_microscaling_types + +target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024" +target triple = "spir-unknown-unknown" + +define spir_func half @ext_conv() { +entry: + %r = call spir_func half @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTi(i4 1) + ret half %r +} + +declare dso_local spir_func half @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTi(i4) diff --git a/test/extensions/INTEL/SPV_INTEL_float4/upscale_o0.ll b/test/extensions/EXT/SPV_EXT_ocp_microscaling_types/upscale_o0.ll similarity index 99% rename from test/extensions/INTEL/SPV_INTEL_float4/upscale_o0.ll rename to test/extensions/EXT/SPV_EXT_ocp_microscaling_types/upscale_o0.ll index 7af9874d09..7ecba5425c 100644 --- a/test/extensions/INTEL/SPV_INTEL_float4/upscale_o0.ll +++ b/test/extensions/EXT/SPV_EXT_ocp_microscaling_types/upscale_o0.ll @@ -26,6 +26,7 @@ ; RUN: llvm-as %s -o %t.bc ; RUN: llvm-spirv %t.bc -o %t.spv --spirv-ext=+SPV_EXT_ocp_microscaling_types,+SPV_INTEL_int4 +; RUN: spirv-val %t.spv ; RUN: llvm-spirv %t.spv -o %t.spt --to-text ; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV ; RUN: llvm-spirv %t.spv -o %t.rev.bc -r --spirv-target-env=SPV-IR diff --git a/test/extensions/INTEL/SPV_INTEL_float4/upscale_o2.ll b/test/extensions/EXT/SPV_EXT_ocp_microscaling_types/upscale_o2.ll similarity index 99% rename from test/extensions/INTEL/SPV_INTEL_float4/upscale_o2.ll rename to test/extensions/EXT/SPV_EXT_ocp_microscaling_types/upscale_o2.ll index cb8ef41c6b..3451f24ba8 100644 --- a/test/extensions/INTEL/SPV_INTEL_float4/upscale_o2.ll +++ b/test/extensions/EXT/SPV_EXT_ocp_microscaling_types/upscale_o2.ll @@ -26,6 +26,7 @@ ; RUN: llvm-as %s -o %t.bc ; RUN: llvm-spirv %t.bc -o %t.spv --spirv-ext=+SPV_EXT_ocp_microscaling_types,+SPV_INTEL_int4 +; RUN: spirv-val %t.spv ; RUN: llvm-spirv %t.spv -o %t.spt --to-text ; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV ; RUN: llvm-spirv %t.spv -o %t.rev.bc -r --spirv-target-env=SPV-IR diff --git a/test/extensions/INTEL/SPV_INTEL_float4/conversions_intel_encoding.ll b/test/extensions/INTEL/SPV_INTEL_float4/conversions_intel_encoding.ll index 87e014b512..5ac7987d29 100644 --- a/test/extensions/INTEL/SPV_INTEL_float4/conversions_intel_encoding.ll +++ b/test/extensions/INTEL/SPV_INTEL_float4/conversions_intel_encoding.ll @@ -4,6 +4,8 @@ ; from SPV_EXT_ocp_microscaling_types. Round-trips back to the INTEL builtins. ; RUN: llvm-spirv %s -o %t.spv --spirv-ext=+SPV_INTEL_float4,+SPV_INTEL_int4,+SPV_KHR_bfloat16 +; TODO: re-enable spirv-val once it can recognize Float4E2M1INTEL capability (6212). +; RUNx: spirv-val %t.spv ; RUN: llvm-spirv %t.spv -o %t.spt --to-text ; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV ; RUN: llvm-spirv %t.spv -o %t.rev.bc -r --spirv-target-env=SPV-IR From ce3f22034b28c90cab1a876a235070ed8f930824 Mon Sep 17 00:00:00 2001 From: "Ye, Qi" Date: Fri, 10 Jul 2026 08:39:32 -0700 Subject: [PATCH 5/8] Fix test file locations and names --- .../{negative/no-microscaling-ext.ll => no_microscaling_ext.ll} | 0 .../SPV_INTEL_float4/no_intel_float4.ll} | 0 2 files changed, 0 insertions(+), 0 deletions(-) rename test/extensions/EXT/SPV_EXT_ocp_microscaling_types/{negative/no-microscaling-ext.ll => no_microscaling_ext.ll} (100%) rename test/extensions/{EXT/SPV_EXT_ocp_microscaling_types/negative/no-intel-float4.ll => INTEL/SPV_INTEL_float4/no_intel_float4.ll} (100%) diff --git a/test/extensions/EXT/SPV_EXT_ocp_microscaling_types/negative/no-microscaling-ext.ll b/test/extensions/EXT/SPV_EXT_ocp_microscaling_types/no_microscaling_ext.ll similarity index 100% rename from test/extensions/EXT/SPV_EXT_ocp_microscaling_types/negative/no-microscaling-ext.ll rename to test/extensions/EXT/SPV_EXT_ocp_microscaling_types/no_microscaling_ext.ll diff --git a/test/extensions/EXT/SPV_EXT_ocp_microscaling_types/negative/no-intel-float4.ll b/test/extensions/INTEL/SPV_INTEL_float4/no_intel_float4.ll similarity index 100% rename from test/extensions/EXT/SPV_EXT_ocp_microscaling_types/negative/no-intel-float4.ll rename to test/extensions/INTEL/SPV_INTEL_float4/no_intel_float4.ll From 214e0679d40562aadd501d19118a0f3e0aac2195 Mon Sep 17 00:00:00 2001 From: "Ye, Qi" Date: Fri, 10 Jul 2026 12:57:48 -0700 Subject: [PATCH 6/8] Fix comments --- .../conversions_both_encodings.ll | 2 -- .../SPV_INTEL_float4}/conversions_cooperative_matrix.ll | 0 .../INTEL/SPV_INTEL_float4/conversions_intel_encoding.ll | 2 -- 3 files changed, 4 deletions(-) rename test/extensions/{EXT/SPV_EXT_ocp_microscaling_types => INTEL/SPV_INTEL_float4}/conversions_cooperative_matrix.ll (100%) diff --git a/test/extensions/EXT/SPV_EXT_ocp_microscaling_types/conversions_both_encodings.ll b/test/extensions/EXT/SPV_EXT_ocp_microscaling_types/conversions_both_encodings.ll index 420d6fa129..ac85576d81 100644 --- a/test/extensions/EXT/SPV_EXT_ocp_microscaling_types/conversions_both_encodings.ll +++ b/test/extensions/EXT/SPV_EXT_ocp_microscaling_types/conversions_both_encodings.ll @@ -5,8 +5,6 @@ ; builtin. ; RUN: llvm-spirv %s -o %t.spv --spirv-ext=+SPV_INTEL_float4,+SPV_EXT_ocp_microscaling_types,+SPV_INTEL_int4 -; TODO: re-enable spirv-val once it can recognize Float4E2M1INTEL capability (6212). -; RUNx: spirv-val %t.spv ; RUN: llvm-spirv %t.spv -o %t.spt --to-text ; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV ; RUN: llvm-spirv %t.spv -o %t.rev.bc -r --spirv-target-env=SPV-IR diff --git a/test/extensions/EXT/SPV_EXT_ocp_microscaling_types/conversions_cooperative_matrix.ll b/test/extensions/INTEL/SPV_INTEL_float4/conversions_cooperative_matrix.ll similarity index 100% rename from test/extensions/EXT/SPV_EXT_ocp_microscaling_types/conversions_cooperative_matrix.ll rename to test/extensions/INTEL/SPV_INTEL_float4/conversions_cooperative_matrix.ll diff --git a/test/extensions/INTEL/SPV_INTEL_float4/conversions_intel_encoding.ll b/test/extensions/INTEL/SPV_INTEL_float4/conversions_intel_encoding.ll index 5ac7987d29..87e014b512 100644 --- a/test/extensions/INTEL/SPV_INTEL_float4/conversions_intel_encoding.ll +++ b/test/extensions/INTEL/SPV_INTEL_float4/conversions_intel_encoding.ll @@ -4,8 +4,6 @@ ; from SPV_EXT_ocp_microscaling_types. Round-trips back to the INTEL builtins. ; RUN: llvm-spirv %s -o %t.spv --spirv-ext=+SPV_INTEL_float4,+SPV_INTEL_int4,+SPV_KHR_bfloat16 -; TODO: re-enable spirv-val once it can recognize Float4E2M1INTEL capability (6212). -; RUNx: spirv-val %t.spv ; RUN: llvm-spirv %t.spv -o %t.spt --to-text ; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV ; RUN: llvm-spirv %t.spv -o %t.rev.bc -r --spirv-target-env=SPV-IR From e57917aaca248da1c5355a340c3b5cfba8793d57 Mon Sep 17 00:00:00 2001 From: Qi Ye Date: Mon, 13 Jul 2026 10:40:32 -0400 Subject: [PATCH 7/8] Apply nit fix Co-authored-by: Yury Plyakhin --- docs/OCPTypesRepresentationInLLVM.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/OCPTypesRepresentationInLLVM.rst b/docs/OCPTypesRepresentationInLLVM.rst index 089dc7516a..9881b56361 100644 --- a/docs/OCPTypesRepresentationInLLVM.rst +++ b/docs/OCPTypesRepresentationInLLVM.rst @@ -93,7 +93,7 @@ SPV_EXT_ocp_microscaling_types Conversions __builtin_spirv_ConvertE2M1ToFP16EXT, __builtin_spirv_ConvertE2M1ToBF16EXT, __builtin_spirv_ConvertFP16ToE2M1EXT, __builtin_spirv_ConvertBF16ToE2M1EXT -For backward compatibility the equivalent INTEL-postfix builtins (e.g. *__builtin_spirv_ConvertE2M1ToFP16INTEL*) +For backward compatibility, the equivalent INTEL-postfix builtins (e.g. *__builtin_spirv_ConvertE2M1ToFP16INTEL*) are also accepted and map to SPV_INTEL_float4; new producers should use the EXT form above. SPV_INTEL_fp_conversions From 07fc433104640001d7553926ef5b7cfd3b5f2349 Mon Sep 17 00:00:00 2001 From: "Ye, Qi" Date: Mon, 13 Jul 2026 10:05:42 -0700 Subject: [PATCH 8/8] Add missing spirv-val check --- .../INTEL/SPV_INTEL_fp_conversions/spv_intel_fp_conversions.ll | 2 ++ 1 file changed, 2 insertions(+) diff --git a/test/extensions/INTEL/SPV_INTEL_fp_conversions/spv_intel_fp_conversions.ll b/test/extensions/INTEL/SPV_INTEL_fp_conversions/spv_intel_fp_conversions.ll index deaa5c3a0b..2479fbab71 100644 --- a/test/extensions/INTEL/SPV_INTEL_fp_conversions/spv_intel_fp_conversions.ll +++ b/test/extensions/INTEL/SPV_INTEL_fp_conversions/spv_intel_fp_conversions.ll @@ -5,6 +5,8 @@ ; for scalar ; RUN: llvm-spirv %s -o %t.spv --spirv-ext=+SPV_EXT_float8,+SPV_EXT_ocp_microscaling_types,+SPV_INTEL_int4,+SPV_KHR_bfloat16,+SPV_INTEL_fp_conversions +; TODO: re-enable spirv-val once it recognizes the FloatConversionsFtoFINTEL capability (6215) +; RUNx: spirv-val %t.spv ; RUN: llvm-spirv %t.spv -o %t.spt --to-text ; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV ; RUN: llvm-spirv %t.spv -o %t.rev.bc -r