diff --git a/docs/OCPTypesRepresentationInLLVM.rst b/docs/OCPTypesRepresentationInLLVM.rst
index 220aa37894..9881b56361 100644
--- a/docs/OCPTypesRepresentationInLLVM.rst
+++ b/docs/OCPTypesRepresentationInLLVM.rst
@@ -40,8 +40,8 @@ SPIR-V conversion instructions
 Most conversions will be represented by standard SPIR-V conversion instructions (*OpFConvert*, *OpConvertSToF*, *OpConvertFToS*,
 *OpConvertUToF*, *OpConvertFToU*, *OpSConvert*), which don't carry information about floating-point value's width and encoding.
 This document adds a new set of external function calls, each of which has a name that is formed from encoding a specific conversion
-that it performs. This name has a *__builtin_spirv_* prefix and a postfix indicating the extension (e.g., *EXT* from SPV_EXT_float8,
-*INTEL* from SPV_INTEL_int4/SPV_INTEL_float4/SPV_INTEL_fp_conversions). These calls will be translated to SPIR-V conversion
+that it performs. This name has a *__builtin_spirv_* prefix and a postfix indicating the extension (e.g., *EXT* from SPV_EXT_float8
+and SPV_EXT_ocp_microscaling_types, *INTEL* from SPV_INTEL_int4, SPV_INTEL_float4 and SPV_INTEL_fp_conversions). These calls will be translated to SPIR-V conversion
 instructions operating over the appropriate types. These functions are expected to be mangled following Itanium C++ ABI. SPIR-V consumer
 will apply Itanium mangling during translation to LLVM IR as well.
 
@@ -82,16 +82,19 @@ SPV_INTEL_int4 Conversions
 
   __builtin_spirv_ConvertInt4ToInt8INTEL
 
-SPV_INTEL_float4 Conversions
------------------------------
+SPV_EXT_ocp_microscaling_types Conversions
+-------------------------------------------
 
 **Translated to OpFConvert:**
 
 .. code-block:: C
 
-  __builtin_spirv_ConvertE2M1ToE4M3INTEL, __builtin_spirv_ConvertE2M1ToE5M2INTEL,
-  __builtin_spirv_ConvertE2M1ToFP16INTEL, __builtin_spirv_ConvertE2M1ToBF16INTEL,
-  __builtin_spirv_ConvertFP16ToE2M1INTEL, __builtin_spirv_ConvertBF16ToE2M1INTEL
+  __builtin_spirv_ConvertE2M1ToE4M3EXT, __builtin_spirv_ConvertE2M1ToE5M2EXT,
+  __builtin_spirv_ConvertE2M1ToFP16EXT, __builtin_spirv_ConvertE2M1ToBF16EXT,
+  __builtin_spirv_ConvertFP16ToE2M1EXT, __builtin_spirv_ConvertBF16ToE2M1EXT
+
+For backward compatibility, the equivalent INTEL-postfix builtins (e.g. *__builtin_spirv_ConvertE2M1ToFP16INTEL*)
+are also accepted and map to SPV_INTEL_float4; new producers should use the EXT form above.
 
 SPV_INTEL_fp_conversions
 -------------------------
@@ -107,8 +110,9 @@ This extension provides conversions with specialized rounding modes for improved
 
 The result is decorated with *SaturatedToLargestFloat8NormalConversionEXT* (SPV_EXT_float8).
 
-ClampConvert*ToE2M1INTEL builtins are not provided: fp4 (E2M1) saturation is unconditional,
-so they collapse into the plain *Convert\*ToE2M1INTEL* form listed under SPV_INTEL_float4.
+ClampConvert*ToE2M1 builtins are not provided: fp4 (E2M1) saturation is unconditional,
+so they collapse into the plain *Convert\*ToE2M1EXT* / *Convert\*ToE2M1INTEL* form listed under
+SPV_EXT_ocp_microscaling_types / SPV_INTEL_float4.
 
 **Translated to OpClampConvertFToSINTEL (clamp rounding to signed integer):**
 
diff --git a/include/LLVMSPIRVExtensions.inc b/include/LLVMSPIRVExtensions.inc
index 213a8fb47c..d9743efa02 100644
--- a/include/LLVMSPIRVExtensions.inc
+++ b/include/LLVMSPIRVExtensions.inc
@@ -95,6 +95,7 @@ EXT(SPV_EXT_float8)
 EXT(SPV_INTEL_predicated_io)
 EXT(SPV_INTEL_sigmoid)
 EXT(SPV_INTEL_float4)
+EXT(SPV_EXT_ocp_microscaling_types)
 EXT(SPV_INTEL_fp_conversions)
 EXT(SPV_KHR_float_controls2)
 EXT(SPV_INTEL_rounded_divide_sqrt)
diff --git a/lib/SPIRV/SPIRVInternal.h b/lib/SPIRV/SPIRVInternal.h
index e6514ff1df..b7555e6b52 100644
--- a/lib/SPIRV/SPIRVInternal.h
+++ b/lib/SPIRV/SPIRVInternal.h
@@ -1035,7 +1035,8 @@ enum FPEncodingWrap {
   BF16 = FPEncoding::FPEncodingBFloat16KHR,
   E4M3 = FPEncoding::FPEncodingFloat8E4M3EXT,
   E5M2 = FPEncoding::FPEncodingFloat8E5M2EXT,
-  E2M1 = internal::FPEncodingFloat4E2M1INTEL,
+  E2M1 = FPEncoding::FPEncodingFloat4E2M1EXT,
+  E2M1INTEL = internal::FPEncodingFloat4E2M1INTEL,
 };
 
 // Structure describing non-trivial conversions (FP8, FP4 and int4)
@@ -1072,14 +1073,22 @@ typedef SPIRVMap<llvm::StringRef, FPConversionDesc> FPConvertToEncodingMap;
 // clang-format off
 template <> inline void FPConvertToEncodingMap::init() {
   // 4-bit conversions
-  add("ConvertE2M1ToE4M3INTEL",
+  add("ConvertE2M1ToE4M3EXT",
       {FPEncodingWrap::E2M1,      FPEncodingWrap::E4M3,         OpFConvert});
-  add("ConvertE2M1ToE5M2INTEL",
+  add("ConvertE2M1ToE5M2EXT",
       {FPEncodingWrap::E2M1,      FPEncodingWrap::E5M2,         OpFConvert});
-  add("ConvertE2M1ToFP16INTEL",
+  add("ConvertE2M1ToFP16EXT",
       {FPEncodingWrap::E2M1,      FPEncodingWrap::IEEE754,      OpFConvert});
-  add("ConvertE2M1ToBF16INTEL",
+  add("ConvertE2M1ToBF16EXT",
       {FPEncodingWrap::E2M1,      FPEncodingWrap::BF16,         OpFConvert});
+  add("ConvertE2M1ToE4M3INTEL",
+      {FPEncodingWrap::E2M1INTEL, FPEncodingWrap::E4M3,         OpFConvert});
+  add("ConvertE2M1ToE5M2INTEL",
+      {FPEncodingWrap::E2M1INTEL, FPEncodingWrap::E5M2,         OpFConvert});
+  add("ConvertE2M1ToFP16INTEL",
+      {FPEncodingWrap::E2M1INTEL, FPEncodingWrap::IEEE754,      OpFConvert});
+  add("ConvertE2M1ToBF16INTEL",
+      {FPEncodingWrap::E2M1INTEL, FPEncodingWrap::BF16,         OpFConvert});
 
   add("ConvertInt4ToE4M3INTEL",
       {FPEncodingWrap::Integer,      FPEncodingWrap::E4M3,      OpConvertSToF});
@@ -1092,10 +1101,14 @@ template <> inline void FPConvertToEncodingMap::init() {
   add("ConvertInt4ToInt8INTEL",
       {FPEncodingWrap::Integer,      FPEncodingWrap::Integer,   OpSConvert});
 
-  add("ConvertFP16ToE2M1INTEL",
+  add("ConvertFP16ToE2M1EXT",
       {FPEncodingWrap::IEEE754,      FPEncodingWrap::E2M1,      OpFConvert});
-  add("ConvertBF16ToE2M1INTEL",
+  add("ConvertBF16ToE2M1EXT",
       {FPEncodingWrap::BF16,         FPEncodingWrap::E2M1,      OpFConvert});
+  add("ConvertFP16ToE2M1INTEL",
+      {FPEncodingWrap::IEEE754,      FPEncodingWrap::E2M1INTEL, OpFConvert});
+  add("ConvertBF16ToE2M1INTEL",
+      {FPEncodingWrap::BF16,         FPEncodingWrap::E2M1INTEL, OpFConvert});
   add("ConvertFP16ToInt4INTEL",
       {FPEncodingWrap::IEEE754,      FPEncodingWrap::Integer,   OpConvertFToS});
   add("ConvertBF16ToInt4INTEL",
diff --git a/lib/SPIRV/SPIRVReader.cpp b/lib/SPIRV/SPIRVReader.cpp
index ec28a691ea..3c5b7d3fc0 100644
--- a/lib/SPIRV/SPIRVReader.cpp
+++ b/lib/SPIRV/SPIRVReader.cpp
@@ -1042,7 +1042,9 @@ Value *SPIRVToLLVM::transConvertInst(SPIRVValue *BV, Function *F,
 
   auto IsFP4OrFP8Encoding = [](FPEncodingWrap Encoding) -> bool {
     return Encoding == FPEncodingWrap::E4M3 ||
-           Encoding == FPEncodingWrap::E5M2 || Encoding == FPEncodingWrap::E2M1;
+           Encoding == FPEncodingWrap::E5M2 ||
+           Encoding == FPEncodingWrap::E2M1 ||
+           Encoding == FPEncodingWrap::E2M1INTEL;
   };
 
   switch (static_cast<unsigned>(BC->getOpCode())) {
@@ -3145,6 +3147,8 @@ Value *SPIRVToLLVM::transValueWithoutDecoration(SPIRVValue *BV, Function *F,
             OutMatrixElementTy->isTypeFloat(8, FPEncodingFloat8E5M2EXT) ||
             InMatrixElementTy->isTypeFloat(8, FPEncodingFloat8E4M3EXT) ||
             InMatrixElementTy->isTypeFloat(8, FPEncodingFloat8E5M2EXT) ||
+            OutMatrixElementTy->isTypeFloat(4, FPEncodingFloat4E2M1EXT) ||
+            InMatrixElementTy->isTypeFloat(4, FPEncodingFloat4E2M1EXT) ||
             OutMatrixElementTy->isTypeFloat(
                 4, internal::FPEncodingFloat4E2M1INTEL) ||
             InMatrixElementTy->isTypeFloat(4,
diff --git a/lib/SPIRV/SPIRVWriter.cpp b/lib/SPIRV/SPIRVWriter.cpp
index c6f48667a2..8fe6c9a24b 100644
--- a/lib/SPIRV/SPIRVWriter.cpp
+++ b/lib/SPIRV/SPIRVWriter.cpp
@@ -923,11 +923,14 @@ SPIRVFunction *LLVMToSPIRVBase::transFunctionDecl(Function *F) {
       // generation.
       if (!BM->isAllowedToUseExtension(ExtensionID::SPV_EXT_float8) &&
           !BM->isAllowedToUseExtension(ExtensionID::SPV_INTEL_int4) &&
-          !BM->isAllowedToUseExtension(ExtensionID::SPV_INTEL_float4)) {
-        std::string ErrorStr = "One of the following extensions: "
-                               "SPV_EXT_float8, SPV_INTEL_float4, "
-                               "SPV_INTEL_int4 should be enabled to process "
-                               "conversion builtins";
+          !BM->isAllowedToUseExtension(ExtensionID::SPV_INTEL_float4) &&
+          !BM->isAllowedToUseExtension(
+              ExtensionID::SPV_EXT_ocp_microscaling_types)) {
+        std::string ErrorStr =
+            "One of the following extensions: "
+            "SPV_EXT_float8, SPV_EXT_ocp_microscaling_types, "
+            "SPV_INTEL_float4, SPV_INTEL_int4 should be enabled to process "
+            "conversion builtins";
         getErrorLog().checkError(false, SPIRVEC_RequiresExtension, F, ErrorStr);
       }
       return nullptr;
@@ -5717,8 +5720,9 @@ processMiniFPOrInt4Type(Type *LLVMTy, FPEncodingWrap Encoding,
   unsigned TyWidth = cast<IntegerType>(ScalarTy)->getBitWidth();
   unsigned VecSize = 0;
 
-  bool IsPacked =
-      Encoding == FPEncodingWrap::E2M1 || Encoding == FPEncodingWrap::Integer;
+  bool IsPacked = Encoding == FPEncodingWrap::E2M1 ||
+                  Encoding == FPEncodingWrap::E2M1INTEL ||
+                  Encoding == FPEncodingWrap::Integer;
   if (IsPacked &&
       (TyWidth == 8 || TyWidth == 16 || TyWidth == 32 || TyWidth == 64)) {
     // Int4 or FP4 packed in an integer: each N-bit integer holds N/4 values.
diff --git a/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h b/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h
index 800f5f8c56..83fc3ec3ab 100644
--- a/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h
+++ b/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h
@@ -705,6 +705,7 @@ template <> inline void SPIRVMap<Capability, std::string>::init() {
   add(internal::CapabilityFloat4E2M1INTEL, "Float4E2M1INTEL");
   add(internal::CapabilityFloat4E2M1CooperativeMatrixINTEL,
       "Float4E2M1CooperativeMatrixINTEL");
+  add(CapabilityFloat4EXT, "Float4EXT");
   add(internal::CapabilityFloatConversionsFtoFINTEL,
       "FloatConversionsFtoFINTEL");
   add(internal::CapabilityFloatConversionsFtoSINTEL,
diff --git a/lib/SPIRV/libSPIRV/SPIRVType.h b/lib/SPIRV/libSPIRV/SPIRVType.h
index a8b690f564..99279b23d4 100644
--- a/lib/SPIRV/libSPIRV/SPIRVType.h
+++ b/lib/SPIRV/libSPIRV/SPIRVType.h
@@ -250,6 +250,8 @@ class SPIRVTypeFloat : public SPIRVType {
     if (isTypeFloat(8, FPEncodingFloat8E4M3EXT) ||
         isTypeFloat(8, FPEncodingFloat8E5M2EXT))
       return ExtensionID::SPV_EXT_float8;
+    if (isTypeFloat(4, FPEncodingFloat4E2M1EXT))
+      return ExtensionID::SPV_EXT_ocp_microscaling_types;
     if (isTypeFloat(4, internal::FPEncodingFloat4E2M1INTEL))
       return ExtensionID::SPV_INTEL_float4;
     return {};
@@ -270,6 +272,8 @@ class SPIRVTypeFloat : public SPIRVType {
     } else if (isTypeFloat(8, FPEncodingFloat8E4M3EXT) ||
                isTypeFloat(8, FPEncodingFloat8E5M2EXT)) {
       CV.push_back(CapabilityFloat8EXT);
+    } else if (isTypeFloat(4, FPEncodingFloat4E2M1EXT)) {
+      CV.push_back(CapabilityFloat4EXT);
     } else if (isTypeFloat(4, internal::FPEncodingFloat4E2M1INTEL)) {
       CV.push_back(internal::CapabilityFloat4E2M1INTEL);
     }
@@ -298,14 +302,16 @@ class SPIRVTypeFloat : public SPIRVType {
     assert((BitWidth == 4 || BitWidth == 8 || BitWidth == 16 ||
             BitWidth == 32 || BitWidth == 64) &&
            "Invalid bit width");
-    assert(
-        (FloatingPointEncoding == FPEncodingMax ||
-         (BitWidth == 16 && FloatingPointEncoding == FPEncodingBFloat16KHR) ||
-         (BitWidth == 8 && FloatingPointEncoding == FPEncodingFloat8E4M3EXT) ||
-         (BitWidth == 8 && FloatingPointEncoding == FPEncodingFloat8E5M2EXT) ||
-         (BitWidth == 4 &&
-          FloatingPointEncoding == internal::FPEncodingFloat4E2M1INTEL)) &&
-        "Invalid floating point encoding");
+    bool ValidEncoding =
+        FloatingPointEncoding == FPEncodingMax ||
+        (BitWidth == 16 && FloatingPointEncoding == FPEncodingBFloat16KHR) ||
+        (BitWidth == 8 && FloatingPointEncoding == FPEncodingFloat8E4M3EXT) ||
+        (BitWidth == 8 && FloatingPointEncoding == FPEncodingFloat8E5M2EXT) ||
+        (BitWidth == 4 && FloatingPointEncoding == FPEncodingFloat4E2M1EXT) ||
+        (BitWidth == 4 &&
+         FloatingPointEncoding == internal::FPEncodingFloat4E2M1INTEL);
+    assert(ValidEncoding && "Invalid floating point encoding");
+    (void)ValidEncoding;
   }
 
 private:
@@ -1224,7 +1230,8 @@ class SPIRVTypeCooperativeMatrixKHR : public SPIRVType {
     else if (CompType->isTypeFloat(8, FPEncodingFloat8E4M3EXT) ||
              CompType->isTypeFloat(8, FPEncodingFloat8E5M2EXT))
       CV.push_back(CapabilityFloat8CooperativeMatrixEXT);
-    else if (CompType->isTypeFloat(4, internal::FPEncodingFloat4E2M1INTEL))
+    else if (CompType->isTypeFloat(4, FPEncodingFloat4E2M1EXT) ||
+             CompType->isTypeFloat(4, internal::FPEncodingFloat4E2M1INTEL))
       CV.push_back(internal::CapabilityFloat4E2M1CooperativeMatrixINTEL);
     return CV;
   }
diff --git a/spirv-headers-tag.conf b/spirv-headers-tag.conf
index 47d1501785..708c8a3749 100644
--- a/spirv-headers-tag.conf
+++ b/spirv-headers-tag.conf
@@ -1 +1 @@
-5c50cbd25a40f8b60e44a2ccc2f1ba3c9e0d0299
+575b6512579ebde466ed3dfc04e413439d14d95d
diff --git a/test/extensions/EXT/SPV_EXT_ocp_microscaling_types/conversions_both_encodings.ll b/test/extensions/EXT/SPV_EXT_ocp_microscaling_types/conversions_both_encodings.ll
new file mode 100644
index 0000000000..ac85576d81
--- /dev/null
+++ b/test/extensions/EXT/SPV_EXT_ocp_microscaling_types/conversions_both_encodings.ll
@@ -0,0 +1,56 @@
+; Checks that both the EXT builtins (SPV_EXT_ocp_microscaling_types,
+; Float4E2M1EXT encoding 4225) and the INTEL builtins (SPV_INTEL_float4,
+; Float4E2M1INTEL encoding 6214) can coexist in one module with both
+; extensions enabled, and that each conversion round-trips back to its own
+; builtin.
+
+; RUN: llvm-spirv %s -o %t.spv --spirv-ext=+SPV_INTEL_float4,+SPV_EXT_ocp_microscaling_types,+SPV_INTEL_int4
+; RUN: llvm-spirv %t.spv -o %t.spt --to-text
+; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
+; RUN: llvm-spirv %t.spv -o %t.rev.bc -r --spirv-target-env=SPV-IR
+; RUN: llvm-dis %t.rev.bc -o %t.rev.ll
+; RUN: FileCheck < %t.rev.ll %s --check-prefix=CHECK-LLVM
+
+; CHECK-SPIRV-DAG: Capability Float4EXT
+; CHECK-SPIRV-DAG: Capability Float4E2M1INTEL
+; CHECK-SPIRV-DAG: Extension "SPV_EXT_ocp_microscaling_types"
+; CHECK-SPIRV-DAG: Extension "SPV_INTEL_float4"
+
+; CHECK-SPIRV-DAG: Name [[#ext_conv:]] "ext_conv"
+; CHECK-SPIRV-DAG: Name [[#intel_conv:]] "intel_conv"
+
+; CHECK-SPIRV-DAG: TypeFloat [[#E2M1ExtTy:]] 4 4225
+; CHECK-SPIRV-DAG: TypeFloat [[#E2M1IntelTy:]] 4 6214
+
+target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+target triple = "spir-unknown-unknown"
+
+; CHECK-SPIRV: Function [[#]] [[#ext_conv]] [[#]]
+; CHECK-SPIRV: Bitcast [[#E2M1ExtTy]] [[#ExtCast:]] [[#]]
+; CHECK-SPIRV: FConvert [[#]] [[#]] [[#ExtCast]]
+
+; CHECK-LLVM-LABEL: ext_conv
+; CHECK-LLVM: call spir_func half @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTi(i4 1)
+
+define spir_func half @ext_conv() {
+entry:
+  %r = call spir_func half @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTi(i4 1)
+  ret half %r
+}
+
+declare dso_local spir_func half @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTi(i4)
+
+; CHECK-SPIRV: Function [[#]] [[#intel_conv]] [[#]]
+; CHECK-SPIRV: Bitcast [[#E2M1IntelTy]] [[#IntelCast:]] [[#]]
+; CHECK-SPIRV: FConvert [[#]] [[#]] [[#IntelCast]]
+
+; CHECK-LLVM-LABEL: intel_conv
+; CHECK-LLVM: call spir_func half @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELi(i4 1)
+
+define spir_func half @intel_conv() {
+entry:
+  %r = call spir_func half @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELi(i4 1)
+  ret half %r
+}
+
+declare dso_local spir_func half @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELi(i4)
diff --git a/test/extensions/INTEL/SPV_INTEL_float4/conversions_packed.ll b/test/extensions/EXT/SPV_EXT_ocp_microscaling_types/conversions_packed.ll
similarity index 71%
rename from test/extensions/INTEL/SPV_INTEL_float4/conversions_packed.ll
rename to test/extensions/EXT/SPV_EXT_ocp_microscaling_types/conversions_packed.ll
index 5ca310089d..8dd8424bbc 100644
--- a/test/extensions/INTEL/SPV_INTEL_float4/conversions_packed.ll
+++ b/test/extensions/EXT/SPV_EXT_ocp_microscaling_types/conversions_packed.ll
@@ -15,7 +15,8 @@
 ;   d. packed in 64-bit
 ;   e. packed in vector of 8-bit integers
 
-; RUN: llvm-spirv %s -o %t.spv --spirv-ext=+SPV_EXT_float8,+SPV_INTEL_float4,+SPV_INTEL_int4,+SPV_KHR_bfloat16
+; RUN: llvm-spirv %s -o %t.spv --spirv-ext=+SPV_EXT_float8,+SPV_EXT_ocp_microscaling_types,+SPV_INTEL_int4,+SPV_KHR_bfloat16
+; RUN: spirv-val %t.spv
 ; RUN: llvm-spirv %t.spv -o %t.spt --to-text
 ; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
 ; RUN: llvm-spirv %t.spv -o %t.rev.bc -r --spirv-target-env=SPV-IR
@@ -23,8 +24,8 @@
 ; RUN: FileCheck < %t.rev.ll %s --check-prefix=CHECK-LLVM
 
 ; CHECK-SPIRV-DAG: Capability Float8EXT
-; CHECK-SPIRV-DAG: Capability Float4E2M1INTEL
-; CHECK-SPIRV-DAG: Extension "SPV_INTEL_float4"
+; CHECK-SPIRV-DAG: Capability Float4EXT
+; CHECK-SPIRV-DAG: Extension "SPV_EXT_ocp_microscaling_types"
 ; CHECK-SPIRV-DAG: Extension "SPV_EXT_float8"
 
 ; CHECK-SPIRV-DAG: Name [[#fp4e2m1_hf8_32:]] "fp4e2m1_hf8_32"
@@ -53,7 +54,7 @@
 ; CHECK-SPIRV-DAG: Constant [[#Int64Ty]] [[#Int64Const:]] 1
 ; CHECK-SPIRV-DAG: ConstantComposite [[#Int8Vec2Ty]] [[#Int8Vec2Const:]] [[#Int8Const]] [[#Int8Const]]
 
-; CHECK-SPIRV-DAG: TypeFloat [[#E2M1Ty:]] 4 6214
+; CHECK-SPIRV-DAG: TypeFloat [[#E2M1Ty:]] 4 4225
 ; CHECK-SPIRV-DAG: TypeVector [[#E2M1Vec8Ty:]] [[#E2M1Ty]] 8
 ; CHECK-SPIRV-DAG: TypeVector [[#E2M1Vec2Ty:]] [[#E2M1Ty]] 2
 ; CHECK-SPIRV-DAG: TypeVector [[#E2M1Vec4Ty:]] [[#E2M1Ty]] 4
@@ -89,16 +90,16 @@ target triple = "spir-unknown-unknown"
 
 ; CHECK-LLVM-LABEL: fp4e2m1_hf8_32
 ; CHECK-LLVM: %[[#Cast:]] = bitcast i32 1 to <8 x i4>
-; CHECK-LLVM: %[[#Call:]] = call spir_func <8 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELDv8_i(<8 x i4> %[[#Cast]])
+; CHECK-LLVM: %[[#Call:]] = call spir_func <8 x i8> @_Z36__builtin_spirv_ConvertE2M1ToE4M3EXTDv8_i(<8 x i4> %[[#Cast]])
 ; CHECK-LLVM: ret <8 x i8> %[[#Call]]
 
 define spir_func <8 x i8> @fp4e2m1_hf8_32() {
 entry:
-  %0 = call spir_func <8 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELi(i32 1)
+  %0 = call spir_func <8 x i8> @_Z36__builtin_spirv_ConvertE2M1ToE4M3EXTi(i32 1)
   ret <8 x i8> %0
 }
 
-declare dso_local spir_func <8 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELi(i32)
+declare dso_local spir_func <8 x i8> @_Z36__builtin_spirv_ConvertE2M1ToE4M3EXTi(i32)
 
 ; CHECK-SPIRV: Function [[#]] [[#hf16_fp4e2m1_32]] [[#]]
 ; CHECK-SPIRV: FConvert [[#E2M1Vec8Ty]] [[#Conv:]] [[#HFloat16Vec8Const]]
@@ -106,17 +107,17 @@ declare dso_local spir_func <8 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTEL
 ; CHECK-SPIRV: ReturnValue [[#Cast2]]
 
 ; CHECK-LLVM-LABEL: hf16_fp4e2m1_32
-; CHECK-LLVM: %[[#Call:]] = call spir_func <8 x i4> @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv8_Dh(<8 x half> splat (half 1.000000e+00))
+; CHECK-LLVM: %[[#Call:]] = call spir_func <8 x i4> @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTDv8_Dh(<8 x half> splat (half 1.000000e+00))
 ; CHECK-LLVM: %[[#Cast:]] = bitcast <8 x i4> %[[#Call]] to i32
 ; CHECK-LLVM: ret i32 %[[#Cast]]
 
 define spir_func i32 @hf16_fp4e2m1_32() {
 entry:
-  %0 = call spir_func i32 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv8_Dh(<8 x half> <half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0>)
+  %0 = call spir_func i32 @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTDv8_Dh(<8 x half> <half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0>)
   ret i32 %0
 }
 
-declare dso_local spir_func i32 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv8_Dh(<8 x half>)
+declare dso_local spir_func i32 @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTDv8_Dh(<8 x half>)
 
 ; Packed in 8-bit integer
 
@@ -128,16 +129,16 @@ declare dso_local spir_func i32 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv8_D
 
 ; CHECK-LLVM-LABEL: fp4e2m1_hf8_8
 ; CHECK-LLVM: %[[#Cast:]] = bitcast i8 1 to <2 x i4>
-; CHECK-LLVM: %[[#Call:]] = call spir_func <2 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELDv2_i(<2 x i4> %[[#Cast]])
+; CHECK-LLVM: %[[#Call:]] = call spir_func <2 x i8> @_Z36__builtin_spirv_ConvertE2M1ToE4M3EXTDv2_i(<2 x i4> %[[#Cast]])
 ; CHECK-LLVM: ret <2 x i8> %[[#Call]]
 
 define spir_func <2 x i8> @fp4e2m1_hf8_8() {
 entry:
-  %0 = call spir_func <2 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELc(i8 1)
+  %0 = call spir_func <2 x i8> @_Z36__builtin_spirv_ConvertE2M1ToE4M3EXTc(i8 1)
   ret <2 x i8> %0
 }
 
-declare dso_local spir_func <2 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELc(i8)
+declare dso_local spir_func <2 x i8> @_Z36__builtin_spirv_ConvertE2M1ToE4M3EXTc(i8)
 
 ; CHECK-SPIRV: Function [[#]] [[#hf16_fp4e2m1_8]] [[#]]
 ; CHECK-SPIRV: FConvert [[#E2M1Vec2Ty]] [[#Conv:]] [[#HFloat16Vec2Const]]
@@ -145,17 +146,17 @@ declare dso_local spir_func <2 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTEL
 ; CHECK-SPIRV: ReturnValue [[#Cast2]]
 
 ; CHECK-LLVM-LABEL: hf16_fp4e2m1_8
-; CHECK-LLVM: %[[#Call:]] = call spir_func <2 x i4> @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv2_Dh(<2 x half> splat (half 1.000000e+00))
+; CHECK-LLVM: %[[#Call:]] = call spir_func <2 x i4> @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTDv2_Dh(<2 x half> splat (half 1.000000e+00))
 ; CHECK-LLVM: %[[#Cast:]] = bitcast <2 x i4> %[[#Call]] to i8
 ; CHECK-LLVM: ret i8 %[[#Cast]]
 
 define spir_func i8 @hf16_fp4e2m1_8() {
 entry:
-  %0 = call spir_func i8 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv2_Dh(<2 x half> <half 1.0, half 1.0>)
+  %0 = call spir_func i8 @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTDv2_Dh(<2 x half> <half 1.0, half 1.0>)
   ret i8 %0
 }
 
-declare dso_local spir_func i8 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv2_Dh(<2 x half>)
+declare dso_local spir_func i8 @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTDv2_Dh(<2 x half>)
 
 ; Packed in 16-bit integer
 
@@ -167,16 +168,16 @@ declare dso_local spir_func i8 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv2_Dh
 
 ; CHECK-LLVM-LABEL: fp4e2m1_hf8_16
 ; CHECK-LLVM: %[[#Cast:]] = bitcast i16 1 to <4 x i4>
-; CHECK-LLVM: %[[#Call:]] = call spir_func <4 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELDv4_i(<4 x i4> %[[#Cast]])
+; CHECK-LLVM: %[[#Call:]] = call spir_func <4 x i8> @_Z36__builtin_spirv_ConvertE2M1ToE4M3EXTDv4_i(<4 x i4> %[[#Cast]])
 ; CHECK-LLVM: ret <4 x i8> %[[#Call]]
 
 define spir_func <4 x i8> @fp4e2m1_hf8_16() {
 entry:
-  %0 = call spir_func <4 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELs(i16 1)
+  %0 = call spir_func <4 x i8> @_Z36__builtin_spirv_ConvertE2M1ToE4M3EXTs(i16 1)
   ret <4 x i8> %0
 }
 
-declare dso_local spir_func <4 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELs(i16)
+declare dso_local spir_func <4 x i8> @_Z36__builtin_spirv_ConvertE2M1ToE4M3EXTs(i16)
 
 ; Packed in 64-bit integer
 
@@ -188,16 +189,16 @@ declare dso_local spir_func <4 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTEL
 
 ; CHECK-LLVM-LABEL: fp4e2m1_hf8_64
 ; CHECK-LLVM: %[[#Cast:]] = bitcast i64 1 to <16 x i4>
-; CHECK-LLVM: %[[#Call:]] = call spir_func <16 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELDv16_i(<16 x i4> %[[#Cast]])
+; CHECK-LLVM: %[[#Call:]] = call spir_func <16 x i8> @_Z36__builtin_spirv_ConvertE2M1ToE4M3EXTDv16_i(<16 x i4> %[[#Cast]])
 ; CHECK-LLVM: ret <16 x i8> %[[#Call]]
 
 define spir_func <16 x i8> @fp4e2m1_hf8_64() {
 entry:
-  %0 = call spir_func <16 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELl(i64 1)
+  %0 = call spir_func <16 x i8> @_Z36__builtin_spirv_ConvertE2M1ToE4M3EXTl(i64 1)
   ret <16 x i8> %0
 }
 
-declare dso_local spir_func <16 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELl(i64)
+declare dso_local spir_func <16 x i8> @_Z36__builtin_spirv_ConvertE2M1ToE4M3EXTl(i64)
 
 ; Packed in vector of 8-bit integers
 
@@ -209,16 +210,16 @@ declare dso_local spir_func <16 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTE
 
 ; CHECK-LLVM-LABEL: fp4e2m1_hf8_vec2xi8
 ; CHECK-LLVM: %[[#Cast:]] = bitcast <2 x i8> splat (i8 1) to <4 x i4>
-; CHECK-LLVM: %[[#Call:]] = call spir_func <4 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELDv4_i(<4 x i4> %[[#Cast]])
+; CHECK-LLVM: %[[#Call:]] = call spir_func <4 x i8> @_Z36__builtin_spirv_ConvertE2M1ToE4M3EXTDv4_i(<4 x i4> %[[#Cast]])
 ; CHECK-LLVM: ret <4 x i8> %[[#Call]]
 
 define spir_func <4 x i8> @fp4e2m1_hf8_vec2xi8() {
 entry:
-  %0 = call spir_func <4 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELDv4_i(<2 x i8> <i8 1, i8 1>)
+  %0 = call spir_func <4 x i8> @_Z36__builtin_spirv_ConvertE2M1ToE4M3EXTDv4_i(<2 x i8> <i8 1, i8 1>)
   ret <4 x i8> %0
 }
 
-declare dso_local spir_func <4 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELDv4_i(<2 x i8>)
+declare dso_local spir_func <4 x i8> @_Z36__builtin_spirv_ConvertE2M1ToE4M3EXTDv4_i(<2 x i8>)
 
 ; To packed in 16-bit integer
 
@@ -228,17 +229,17 @@ declare dso_local spir_func <4 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTEL
 ; CHECK-SPIRV: ReturnValue [[#Cast2]]
 
 ; CHECK-LLVM-LABEL: hf16_fp4e2m1_16
-; CHECK-LLVM: %[[#Call:]] = call spir_func <4 x i4> @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv4_Dh(<4 x half> splat (half 1.000000e+00))
+; CHECK-LLVM: %[[#Call:]] = call spir_func <4 x i4> @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTDv4_Dh(<4 x half> splat (half 1.000000e+00))
 ; CHECK-LLVM: %[[#Cast:]] = bitcast <4 x i4> %[[#Call]] to i16
 ; CHECK-LLVM: ret i16 %[[#Cast]]
 
 define spir_func i16 @hf16_fp4e2m1_16() {
 entry:
-  %0 = call spir_func i16 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv4_Dh(<4 x half> <half 1.0, half 1.0, half 1.0, half 1.0>)
+  %0 = call spir_func i16 @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTDv4_Dh(<4 x half> <half 1.0, half 1.0, half 1.0, half 1.0>)
   ret i16 %0
 }
 
-declare dso_local spir_func i16 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv4_Dh(<4 x half>)
+declare dso_local spir_func i16 @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTDv4_Dh(<4 x half>)
 
 ; To packed in 64-bit integer
 
@@ -248,17 +249,17 @@ declare dso_local spir_func i16 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv4_D
 ; CHECK-SPIRV: ReturnValue [[#Cast2]]
 
 ; CHECK-LLVM-LABEL: hf16_fp4e2m1_64
-; CHECK-LLVM: %[[#Call:]] = call spir_func <16 x i4> @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv16_Dh(<16 x half> splat (half 1.000000e+00))
+; CHECK-LLVM: %[[#Call:]] = call spir_func <16 x i4> @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTDv16_Dh(<16 x half> splat (half 1.000000e+00))
 ; CHECK-LLVM: %[[#Cast:]] = bitcast <16 x i4> %[[#Call]] to i64
 ; CHECK-LLVM: ret i64 %[[#Cast]]
 
 define spir_func i64 @hf16_fp4e2m1_64() {
 entry:
-  %0 = call spir_func i64 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv16_Dh(<16 x half> <half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0>)
+  %0 = call spir_func i64 @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTDv16_Dh(<16 x half> <half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0>)
   ret i64 %0
 }
 
-declare dso_local spir_func i64 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv16_Dh(<16 x half>)
+declare dso_local spir_func i64 @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTDv16_Dh(<16 x half>)
 
 ; To packed in vector of 8-bit integers
 
@@ -268,14 +269,14 @@ declare dso_local spir_func i64 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv16_
 ; CHECK-SPIRV: ReturnValue [[#Cast]]
 
 ; CHECK-LLVM-LABEL: hf16_fp4e2m1_vec2xi8
-; CHECK-LLVM: %[[#Call:]] = call spir_func <4 x i4> @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv4_Dh(<4 x half> splat (half 1.000000e+00))
+; CHECK-LLVM: %[[#Call:]] = call spir_func <4 x i4> @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTDv4_Dh(<4 x half> splat (half 1.000000e+00))
 ; CHECK-LLVM: %[[#Cast:]] = bitcast <4 x i4> %[[#Call]] to <2 x i8>
 ; CHECK-LLVM: ret <2 x i8> %[[#Cast]]
 
 define spir_func <2 x i8> @hf16_fp4e2m1_vec2xi8() {
 entry:
-  %0 = call spir_func <2 x i8> @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELKDv4_Dh(<4 x half> <half 1.0, half 1.0, half 1.0, half 1.0>)
+  %0 = call spir_func <2 x i8> @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTKDv4_Dh(<4 x half> <half 1.0, half 1.0, half 1.0, half 1.0>)
   ret <2 x i8> %0
 }
 
-declare dso_local spir_func <2 x i8> @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELKDv4_Dh(<4 x half>)
+declare dso_local spir_func <2 x i8> @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTKDv4_Dh(<4 x half>)
diff --git a/test/extensions/INTEL/SPV_INTEL_float4/conversions_scalar_vector.ll b/test/extensions/EXT/SPV_EXT_ocp_microscaling_types/conversions_scalar_vector.ll
similarity index 66%
rename from test/extensions/INTEL/SPV_INTEL_float4/conversions_scalar_vector.ll
rename to test/extensions/EXT/SPV_EXT_ocp_microscaling_types/conversions_scalar_vector.ll
index e9524aa5fc..de0ef5ba02 100644
--- a/test/extensions/INTEL/SPV_INTEL_float4/conversions_scalar_vector.ll
+++ b/test/extensions/EXT/SPV_EXT_ocp_microscaling_types/conversions_scalar_vector.ll
@@ -3,7 +3,8 @@
 ; include Clamp*, Biased*, ClampBiased* conversions (it's part of another test
 ; file).
 
-; RUN: llvm-spirv %s -o %t.spv --spirv-ext=+SPV_EXT_float8,+SPV_INTEL_float4,+SPV_INTEL_int4,+SPV_KHR_bfloat16
+; RUN: llvm-spirv %s -o %t.spv --spirv-ext=+SPV_EXT_float8,+SPV_EXT_ocp_microscaling_types,+SPV_INTEL_int4,+SPV_KHR_bfloat16
+; RUN: spirv-val %t.spv
 ; RUN: llvm-spirv %t.spv -o %t.spt --to-text
 ; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
 ; RUN: llvm-spirv %t.spv -o %t.rev.bc -r --spirv-target-env=SPV-IR
@@ -12,10 +13,11 @@
 
 ; CHECK-SPIRV-DAG: Capability Int4TypeINTEL
 ; CHECK-SPIRV-DAG: Capability Float8EXT
+; CHECK-SPIRV-DAG: Capability Float4EXT
 
 ; CHECK-SPIRV-DAG: Extension "SPV_INTEL_int4"
 ; CHECK-SPIRV-DAG: Extension "SPV_EXT_float8"
-; CHECK-SPIRV-DAG: Extension "SPV_INTEL_float4"
+; CHECK-SPIRV-DAG: Extension "SPV_EXT_ocp_microscaling_types"
 
 ; CHECK-SPIRV-DAG: Name [[#fp4e2m1_hf8_scalar:]] "fp4e2m1_hf8_scalar"
 ; CHECK-SPIRV-DAG: Name [[#fp4e2m1_hf8_vector:]] "fp4e2m1_hf8_vector"
@@ -39,7 +41,7 @@
 ; CHECK-SPIRV-DAG: Constant [[#Int4Ty]] [[#Int4Const:]] 1
 ; CHECK-SPIRV-DAG: ConstantComposite [[#Int4VecTy]] [[#Int4VecConst:]] [[#Int4Const]] [[#Int4Const]] [[#Int4Const]] [[#Int4Const]] [[#Int4Const]] [[#Int4Const]] [[#Int4Const]] [[#Int4Const]]
 
-; CHECK-SPIRV-DAG: TypeFloat [[#E2M1Ty:]] 4 6214
+; CHECK-SPIRV-DAG: TypeFloat [[#E2M1Ty:]] 4 4225
 ; CHECK-SPIRV-DAG: TypeVector [[#E2M1VecTy:]] [[#E2M1Ty]] 8
 
 ; CHECK-SPIRV-DAG: TypeFloat [[#HFloat8Ty:]] 8 4214
@@ -70,16 +72,16 @@ target triple = "spir-unknown-unknown"
 ; CHECK-SPIRV: ReturnValue [[#Cast2]]
 
 ; CHECK-LLVM-LABEL: fp4e2m1_hf8_scalar
-; CHECK-LLVM: %[[#Call:]] = call spir_func i8 @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELi(i4 1)
+; CHECK-LLVM: %[[#Call:]] = call spir_func i8 @_Z36__builtin_spirv_ConvertE2M1ToE4M3EXTi(i4 1)
 ; CHECK-LLVM: ret i8 %[[#Call]]
 
 define spir_func i8 @fp4e2m1_hf8_scalar() {
 entry:
-  %0 = call spir_func i8 @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELi(i4 1)
+  %0 = call spir_func i8 @_Z36__builtin_spirv_ConvertE2M1ToE4M3EXTi(i4 1)
   ret i8 %0
 }
 
-declare dso_local spir_func i8 @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELi(i4)
+declare dso_local spir_func i8 @_Z36__builtin_spirv_ConvertE2M1ToE4M3EXTi(i4)
 
 ; CHECK-SPIRV: Function [[#]] [[#fp4e2m1_hf8_vector]] [[#]]
 ; CHECK-SPIRV: Bitcast [[#E2M1VecTy]] [[#Cast1:]] [[#Int4VecConst]]
@@ -88,16 +90,16 @@ declare dso_local spir_func i8 @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELi(i4)
 ; CHECK-SPIRV: ReturnValue [[#Cast2]]
 
 ; CHECK-LLVM-LABEL: fp4e2m1_hf8_vector
-; CHECK-LLVM: %[[#Call:]] = call spir_func <8 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELDv8_i(<8 x i4> splat (i4 1))
+; CHECK-LLVM: %[[#Call:]] = call spir_func <8 x i8> @_Z36__builtin_spirv_ConvertE2M1ToE4M3EXTDv8_i(<8 x i4> splat (i4 1))
 ; CHECK-LLVM: ret <8 x i8> %[[#Call]]
 
 define spir_func <8 x i8> @fp4e2m1_hf8_vector() {
 entry:
-  %0 = call spir_func <8 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELDv8_i(<8 x i4> <i4 1, i4 1, i4 1, i4 1, i4 1, i4 1, i4 1, i4 1>)
+  %0 = call spir_func <8 x i8> @_Z36__builtin_spirv_ConvertE2M1ToE4M3EXTDv8_i(<8 x i4> <i4 1, i4 1, i4 1, i4 1, i4 1, i4 1, i4 1, i4 1>)
   ret <8 x i8> %0
 }
 
-declare dso_local spir_func <8 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTELDv8_i(<8 x i4>)
+declare dso_local spir_func <8 x i8> @_Z36__builtin_spirv_ConvertE2M1ToE4M3EXTDv8_i(<8 x i4>)
 
 ; CHECK-SPIRV: Function [[#]] [[#fp4e2m1_bf8_scalar]] [[#]]
 ; CHECK-SPIRV: Bitcast [[#E2M1Ty]] [[#Cast1:]] [[#Int4Const]]
@@ -106,16 +108,16 @@ declare dso_local spir_func <8 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE4M3INTEL
 ; CHECK-SPIRV: ReturnValue [[#Cast2]]
 
 ; CHECK-LLVM-LABEL: fp4e2m1_bf8_scalar
-; CHECK-LLVM: %[[#Call:]] = call spir_func i8 @_Z38__builtin_spirv_ConvertE2M1ToE5M2INTELi(i4 1)
+; CHECK-LLVM: %[[#Call:]] = call spir_func i8 @_Z36__builtin_spirv_ConvertE2M1ToE5M2EXTi(i4 1)
 ; CHECK-LLVM: ret i8 %[[#Call]]
 
 define spir_func i8 @fp4e2m1_bf8_scalar() {
 entry:
-  %0 = call spir_func i8 @_Z38__builtin_spirv_ConvertE2M1ToE5M2INTELi(i4 1)
+  %0 = call spir_func i8 @_Z36__builtin_spirv_ConvertE2M1ToE5M2EXTi(i4 1)
   ret i8 %0
 }
 
-declare dso_local spir_func i8 @_Z38__builtin_spirv_ConvertE2M1ToE5M2INTELi(i4)
+declare dso_local spir_func i8 @_Z36__builtin_spirv_ConvertE2M1ToE5M2EXTi(i4)
 
 ; CHECK-SPIRV: Function [[#]] [[#fp4e2m1_bf8_vector]] [[#]]
 ; CHECK-SPIRV: Bitcast [[#E2M1VecTy]] [[#Cast1:]] [[#Int4VecConst]]
@@ -124,16 +126,16 @@ declare dso_local spir_func i8 @_Z38__builtin_spirv_ConvertE2M1ToE5M2INTELi(i4)
 ; CHECK-SPIRV: ReturnValue [[#Cast2]]
 
 ; CHECK-LLVM-LABEL: fp4e2m1_bf8_vector
-; CHECK-LLVM: %[[#Call:]] = call spir_func <8 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE5M2INTELDv8_i(<8 x i4> splat (i4 1))
+; CHECK-LLVM: %[[#Call:]] = call spir_func <8 x i8> @_Z36__builtin_spirv_ConvertE2M1ToE5M2EXTDv8_i(<8 x i4> splat (i4 1))
 ; CHECK-LLVM: ret <8 x i8> %[[#Call]]
 
 define spir_func <8 x i8> @fp4e2m1_bf8_vector() {
 entry:
-  %0 = call spir_func <8 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE5M2INTELDv8_i(<8 x i4> <i4 1, i4 1, i4 1, i4 1, i4 1, i4 1, i4 1, i4 1>)
+  %0 = call spir_func <8 x i8> @_Z36__builtin_spirv_ConvertE2M1ToE5M2EXTDv8_i(<8 x i4> <i4 1, i4 1, i4 1, i4 1, i4 1, i4 1, i4 1, i4 1>)
   ret <8 x i8> %0
 }
 
-declare dso_local spir_func <8 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE5M2INTELDv8_i(<8 x i4>)
+declare dso_local spir_func <8 x i8> @_Z36__builtin_spirv_ConvertE2M1ToE5M2EXTDv8_i(<8 x i4>)
 
 ; CHECK-SPIRV: Function [[#]] [[#fp4e2m1_hf16_scalar]] [[#]]
 ; CHECK-SPIRV: Bitcast [[#E2M1Ty]] [[#Cast1:]] [[#Int4Const]]
@@ -141,16 +143,16 @@ declare dso_local spir_func <8 x i8> @_Z38__builtin_spirv_ConvertE2M1ToE5M2INTEL
 ; CHECK-SPIRV: ReturnValue [[#Conv]]
 
 ; CHECK-LLVM-LABEL: fp4e2m1_hf16_scalar
-; CHECK-LLVM: %[[#Call:]] = call spir_func half @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELi(i4 1)
+; CHECK-LLVM: %[[#Call:]] = call spir_func half @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTi(i4 1)
 ; CHECK-LLVM: ret half %[[#Call]]
 
 define spir_func half @fp4e2m1_hf16_scalar() {
 entry:
-  %0 = call spir_func half @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELi(i4 1)
+  %0 = call spir_func half @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTi(i4 1)
   ret half %0
 }
 
-declare dso_local spir_func half @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELi(i4)
+declare dso_local spir_func half @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTi(i4)
 
 ; CHECK-SPIRV: Function [[#]] [[#fp4e2m1_hf16_vector]] [[#]]
 ; CHECK-SPIRV: Bitcast [[#E2M1VecTy]] [[#Cast1:]] [[#Int4VecConst]]
@@ -158,16 +160,16 @@ declare dso_local spir_func half @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELi(i4
 ; CHECK-SPIRV: ReturnValue [[#Conv]]
 
 ; CHECK-LLVM-LABEL: fp4e2m1_hf16_vector
-; CHECK-LLVM: %[[#Call:]] = call spir_func <8 x half> @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELDv8_i(<8 x i4> splat (i4 1))
+; CHECK-LLVM: %[[#Call:]] = call spir_func <8 x half> @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTDv8_i(<8 x i4> splat (i4 1))
 ; CHECK-LLVM: ret <8 x half> %[[#Call]]
 
 define spir_func <8 x half> @fp4e2m1_hf16_vector() {
 entry:
-  %0 = call spir_func <8 x half> @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELDv8_i(<8 x i4> <i4 1, i4 1, i4 1, i4 1, i4 1, i4 1, i4 1, i4 1>)
+  %0 = call spir_func <8 x half> @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTDv8_i(<8 x i4> <i4 1, i4 1, i4 1, i4 1, i4 1, i4 1, i4 1, i4 1>)
   ret <8 x half> %0
 }
 
-declare dso_local spir_func <8 x half> @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELDv8_i(<8 x i4>)
+declare dso_local spir_func <8 x half> @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTDv8_i(<8 x i4>)
 
 ; CHECK-SPIRV: Function [[#]] [[#fp4e2m1_bf16_scalar]] [[#]]
 ; CHECK-SPIRV: Bitcast [[#E2M1Ty]] [[#Cast1:]] [[#Int4Const]]
@@ -175,16 +177,16 @@ declare dso_local spir_func <8 x half> @_Z38__builtin_spirv_ConvertE2M1ToFP16INT
 ; CHECK-SPIRV: ReturnValue [[#Conv]]
 
 ; CHECK-LLVM-LABEL: fp4e2m1_bf16_scalar
-; CHECK-LLVM: %[[#Call:]] = call spir_func bfloat @_Z38__builtin_spirv_ConvertE2M1ToBF16INTELi(i4 1)
+; CHECK-LLVM: %[[#Call:]] = call spir_func bfloat @_Z36__builtin_spirv_ConvertE2M1ToBF16EXTi(i4 1)
 ; CHECK-LLVM: ret bfloat %[[#Call]]
 
 define spir_func bfloat @fp4e2m1_bf16_scalar() {
 entry:
-  %0 = call spir_func bfloat @_Z38__builtin_spirv_ConvertE2M1ToBF16INTELi(i4 1)
+  %0 = call spir_func bfloat @_Z36__builtin_spirv_ConvertE2M1ToBF16EXTi(i4 1)
   ret bfloat %0
 }
 
-declare dso_local spir_func bfloat @_Z38__builtin_spirv_ConvertE2M1ToBF16INTELi(i4)
+declare dso_local spir_func bfloat @_Z36__builtin_spirv_ConvertE2M1ToBF16EXTi(i4)
 
 ; CHECK-SPIRV: Function [[#]] [[#fp4e2m1_bf16_vector]] [[#]]
 ; CHECK-SPIRV: Bitcast [[#E2M1VecTy]] [[#Cast1:]] [[#Int4VecConst]]
@@ -192,16 +194,16 @@ declare dso_local spir_func bfloat @_Z38__builtin_spirv_ConvertE2M1ToBF16INTELi(
 ; CHECK-SPIRV: ReturnValue [[#Conv]]
 
 ; CHECK-LLVM-LABEL: fp4e2m1_bf16_vector
-; CHECK-LLVM: %[[#Call:]] = call spir_func <8 x bfloat> @_Z38__builtin_spirv_ConvertE2M1ToBF16INTELDv8_i(<8 x i4> splat (i4 1))
+; CHECK-LLVM: %[[#Call:]] = call spir_func <8 x bfloat> @_Z36__builtin_spirv_ConvertE2M1ToBF16EXTDv8_i(<8 x i4> splat (i4 1))
 ; CHECK-LLVM: ret <8 x bfloat> %[[#Call]]
 
 define spir_func <8 x bfloat> @fp4e2m1_bf16_vector() {
 entry:
-  %0 = call spir_func <8 x bfloat> @_Z38__builtin_spirv_ConvertE2M1ToBF16INTELDv8_i(<8 x i4> <i4 1, i4 1, i4 1, i4 1, i4 1, i4 1, i4 1, i4 1>)
+  %0 = call spir_func <8 x bfloat> @_Z36__builtin_spirv_ConvertE2M1ToBF16EXTDv8_i(<8 x i4> <i4 1, i4 1, i4 1, i4 1, i4 1, i4 1, i4 1, i4 1>)
   ret <8 x bfloat> %0
 }
 
-declare dso_local spir_func <8 x bfloat> @_Z38__builtin_spirv_ConvertE2M1ToBF16INTELDv8_i(<8 x i4>)
+declare dso_local spir_func <8 x bfloat> @_Z36__builtin_spirv_ConvertE2M1ToBF16EXTDv8_i(<8 x i4>)
 
 ; Following tests are for 4-bit roundings
 
@@ -211,16 +213,16 @@ declare dso_local spir_func <8 x bfloat> @_Z38__builtin_spirv_ConvertE2M1ToBF16I
 ; CHECK-SPIRV: ReturnValue [[#Cast]]
 
 ; CHECK-LLVM-LABEL: hf16_fp4e2m1_scalar
-; CHECK-LLVM: %[[#Call:]] = call spir_func i4 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDh(half 1.000000e+00)
+; CHECK-LLVM: %[[#Call:]] = call spir_func i4 @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTDh(half 1.000000e+00)
 ; CHECK-LLVM: ret i4 %[[#Call]]
 
 define spir_func i4 @hf16_fp4e2m1_scalar() {
 entry:
-  %0 = call spir_func i4 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDh(half 1.0)
+  %0 = call spir_func i4 @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTDh(half 1.0)
   ret i4 %0
 }
 
-declare dso_local spir_func i4 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDh(half)
+declare dso_local spir_func i4 @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTDh(half)
 
 ; CHECK-SPIRV: Function [[#]] [[#hf16_fp4e2m1_vector]] [[#]]
 ; CHECK-SPIRV: FConvert [[#E2M1VecTy]] [[#Conv:]] [[#HalfVecConst]]
@@ -228,16 +230,16 @@ declare dso_local spir_func i4 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDh(hal
 ; CHECK-SPIRV: ReturnValue [[#Cast]]
 
 ; CHECK-LLVM-LABEL: hf16_fp4e2m1_vector
-; CHECK-LLVM: %[[#Call:]] = call spir_func <8 x i4> @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv8_Dh(<8 x half> splat (half 1.000000e+00))
+; CHECK-LLVM: %[[#Call:]] = call spir_func <8 x i4> @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTDv8_Dh(<8 x half> splat (half 1.000000e+00))
 ; CHECK-LLVM: ret <8 x i4> %[[#Call]]
 
 define spir_func <8 x i4> @hf16_fp4e2m1_vector() {
 entry:
-  %0 = call spir_func <8 x i4> @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv8_Dh(<8 x half> <half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0>)
+  %0 = call spir_func <8 x i4> @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTDv8_Dh(<8 x half> <half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0>)
   ret <8 x i4> %0
 }
 
-declare dso_local spir_func <8 x i4> @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDv8_Dh(<8 x half>)
+declare dso_local spir_func <8 x i4> @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTDv8_Dh(<8 x half>)
 
 ; CHECK-SPIRV: Function [[#]] [[#bf16_fp4e2m1_scalar]] [[#]]
 ; CHECK-SPIRV: FConvert [[#E2M1Ty]] [[#Conv:]] [[#BfloatConst]]
@@ -245,16 +247,16 @@ declare dso_local spir_func <8 x i4> @_Z38__builtin_spirv_ConvertFP16ToE2M1INTEL
 ; CHECK-SPIRV: ReturnValue [[#Cast]]
 
 ; CHECK-LLVM-LABEL: bf16_fp4e2m1_scalar
-; CHECK-LLVM: %[[#Call:]] = call spir_func i4 @_Z38__builtin_spirv_ConvertBF16ToE2M1INTELDF16b(bfloat 1.000000e+00)
+; CHECK-LLVM: %[[#Call:]] = call spir_func i4 @_Z36__builtin_spirv_ConvertBF16ToE2M1EXTDF16b(bfloat 1.000000e+00)
 ; CHECK-LLVM: ret i4 %[[#Call]]
 
 define spir_func i4 @bf16_fp4e2m1_scalar() {
 entry:
-  %0 = call spir_func i4 @_Z38__builtin_spirv_ConvertBF16ToE2M1INTELDF16b(bfloat 1.0)
+  %0 = call spir_func i4 @_Z36__builtin_spirv_ConvertBF16ToE2M1EXTDF16b(bfloat 1.0)
   ret i4 %0
 }
 
-declare dso_local spir_func i4 @_Z38__builtin_spirv_ConvertBF16ToE2M1INTELDF16b(bfloat)
+declare dso_local spir_func i4 @_Z36__builtin_spirv_ConvertBF16ToE2M1EXTDF16b(bfloat)
 
 ; CHECK-SPIRV: Function [[#]] [[#bf16_fp4e2m1_vector]] [[#]]
 ; CHECK-SPIRV: FConvert [[#E2M1VecTy]] [[#Conv:]] [[#BfloatVecConst]]
@@ -262,14 +264,14 @@ declare dso_local spir_func i4 @_Z38__builtin_spirv_ConvertBF16ToE2M1INTELDF16b(
 ; CHECK-SPIRV: ReturnValue [[#Cast]]
 
 ; CHECK-LLVM-LABEL: bf16_fp4e2m1_vector
-; CHECK-LLVM: %[[#Call:]] = call spir_func <8 x i4> @_Z38__builtin_spirv_ConvertBF16ToE2M1INTELDv8_DF16b(<8 x bfloat> splat (bfloat 1.000000e+00))
+; CHECK-LLVM: %[[#Call:]] = call spir_func <8 x i4> @_Z36__builtin_spirv_ConvertBF16ToE2M1EXTDv8_DF16b(<8 x bfloat> splat (bfloat 1.000000e+00))
 ; CHECK-LLVM: ret <8 x i4> %[[#Call]]
 
 define spir_func <8 x i4> @bf16_fp4e2m1_vector() {
 entry:
-  %0 = call spir_func <8 x i4> @_Z38__builtin_spirv_ConvertBF16ToE2M1INTELDv8_DF16b(<8 x bfloat> <bfloat 1.0, bfloat 1.0, bfloat 1.0, bfloat 1.0, bfloat 1.0, bfloat 1.0, bfloat 1.0, bfloat 1.0>)
+  %0 = call spir_func <8 x i4> @_Z36__builtin_spirv_ConvertBF16ToE2M1EXTDv8_DF16b(<8 x bfloat> <bfloat 1.0, bfloat 1.0, bfloat 1.0, bfloat 1.0, bfloat 1.0, bfloat 1.0, bfloat 1.0, bfloat 1.0>)
   ret <8 x i4> %0
 }
 
-declare dso_local spir_func <8 x i4> @_Z38__builtin_spirv_ConvertBF16ToE2M1INTELDv8_DF16b(<8 x bfloat>)
+declare dso_local spir_func <8 x i4> @_Z36__builtin_spirv_ConvertBF16ToE2M1EXTDv8_DF16b(<8 x bfloat>)
 
diff --git a/test/extensions/EXT/SPV_EXT_ocp_microscaling_types/no_microscaling_ext.ll b/test/extensions/EXT/SPV_EXT_ocp_microscaling_types/no_microscaling_ext.ll
new file mode 100644
index 0000000000..e19e540bb1
--- /dev/null
+++ b/test/extensions/EXT/SPV_EXT_ocp_microscaling_types/no_microscaling_ext.ll
@@ -0,0 +1,18 @@
+; Checks that an *EXT FP4 conversion builtin fails to translate when
+; SPV_EXT_ocp_microscaling_types is not enabled.
+
+; RUN: not llvm-spirv %s -o %t.spv --spirv-ext=+SPV_INTEL_int4 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
+
+; CHECK-ERROR: RequiresExtension: Feature requires the following SPIR-V extension:
+; CHECK-ERROR-NEXT: SPV_EXT_ocp_microscaling_types
+
+target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+target triple = "spir-unknown-unknown"
+
+define spir_func half @ext_conv() {
+entry:
+  %r = call spir_func half @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTi(i4 1)
+  ret half %r
+}
+
+declare dso_local spir_func half @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTi(i4)
diff --git a/test/extensions/INTEL/SPV_INTEL_float4/upscale_o0.ll b/test/extensions/EXT/SPV_EXT_ocp_microscaling_types/upscale_o0.ll
similarity index 87%
rename from test/extensions/INTEL/SPV_INTEL_float4/upscale_o0.ll
rename to test/extensions/EXT/SPV_EXT_ocp_microscaling_types/upscale_o0.ll
index cc8d57c9a4..7ecba5425c 100644
--- a/test/extensions/INTEL/SPV_INTEL_float4/upscale_o0.ll
+++ b/test/extensions/EXT/SPV_EXT_ocp_microscaling_types/upscale_o0.ll
@@ -25,25 +25,26 @@
 ; clang -cl-std=cl3.0 -target spir -emit-llvm -Xclang -finclude-default-header -g0 -O0
 
 ; RUN: llvm-as %s -o %t.bc
-; RUN: llvm-spirv %t.bc -o %t.spv --spirv-ext=+SPV_INTEL_float4,+SPV_INTEL_int4
+; RUN: llvm-spirv %t.bc -o %t.spv --spirv-ext=+SPV_EXT_ocp_microscaling_types,+SPV_INTEL_int4
+; RUN: spirv-val %t.spv
 ; RUN: llvm-spirv %t.spv -o %t.spt --to-text
 ; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
 ; RUN: llvm-spirv %t.spv -o %t.rev.bc -r --spirv-target-env=SPV-IR
 ; RUN: llvm-dis %t.rev.bc -o %t.rev.ll
 ; RUN: FileCheck < %t.rev.ll %s --check-prefix=CHECK-LLVM
 
-; CHECK-SPIRV-NOT: _Z38__builtin_spirv_ConvertE2M1ToFP16INTELDv2_i
+; CHECK-SPIRV-NOT: _Z36__builtin_spirv_ConvertE2M1ToFP16EXTDv2_i
 
 ; CHECK-SPIRV-DAG: Capability Float16Buffer
 ; CHECK-SPIRV-DAG: Capability Int4TypeINTEL
-; CHECK-SPIRV-DAG: Capability Float4E2M1INTEL
+; CHECK-SPIRV-DAG: Capability Float4EXT
 
 ; CHECK-SPIRV-DAG: TypeInt [[#Int4Ty:]] 4 0
 ; CHECK-SPIRV-DAG: TypeVector [[#VecInt4Ty:]] [[#Int4Ty]] 2
 ; CHECK-SPIRV-DAG: TypePointer [[#PtrVecInt4Ty:]] 7 [[#VecInt4Ty]]
 ; CHECK-SPIRV-DAG: TypeFloat [[#HalfTy:]] 16
 ; CHECK-SPIRV-DAG: TypeVector [[#VecHalfTy:]] [[#HalfTy]] 2
-; CHECK-SPIRV-DAG: TypeFloat [[#FP4Ty:]] 4 6214
+; CHECK-SPIRV-DAG: TypeFloat [[#FP4Ty:]] 4 4225
 ; CHECK-SPIRV-DAG: TypeVector [[#VecFP4Ty:]] [[#FP4Ty]] 2
 
 ; CHECK-SPIRV: Load [[#VecInt4Ty]] [[#VecInt4Val1:]] [[#]] 2 2
@@ -56,9 +57,9 @@
 ; CHECK-SPIRV: FConvert [[#VecHalfTy]] [[#Conv2:]] [[#Cast2]]
 ; CHECK-SPIRV: Store [[#]] [[#Conv2]] 2 4
 
-; CHECK-LLVM: %[[#Conv1:]] = call spir_func <2 x half> @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELDv2_i(<2 x i4> %[[#]])
+; CHECK-LLVM: %[[#Conv1:]] = call spir_func <2 x half> @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTDv2_i(<2 x i4> %[[#]])
 ; CHECK-LLVM: store <2 x half> %[[#Conv1]], ptr %[[#]]
-; CHECK-LLVM: %[[#Conv2:]] = call spir_func <2 x half> @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELDv2_i(<2 x i4> %[[#]])
+; CHECK-LLVM: %[[#Conv2:]] = call spir_func <2 x half> @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTDv2_i(<2 x i4> %[[#]])
 ; CHECK-LLVM: store <2 x half> %[[#Conv2]], ptr %[[#]]
 
 target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
@@ -109,10 +110,10 @@ define dso_local spir_func void @__clang_ocl_kern_imp_quant_add(ptr addrspace(3)
   %26 = shufflevector <2 x i4> %25, <2 x i4> poison, <2 x i32> zeroinitializer
   store <2 x i4> %26, ptr %9, align 2
   %27 = load <2 x i4>, ptr %8, align 2
-  %28 = call spir_func <2 x half> @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELDv2_i(<2 x i4> noundef %27) #5
+  %28 = call spir_func <2 x half> @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTDv2_i(<2 x i4> noundef %27) #5
   store <2 x half> %28, ptr %10, align 4
   %29 = load <2 x i4>, ptr %9, align 2
-  %30 = call spir_func <2 x half> @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELDv2_i(<2 x i4> noundef %29) #5
+  %30 = call spir_func <2 x half> @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTDv2_i(<2 x i4> noundef %29) #5
   store <2 x half> %30, ptr %11, align 4
   %31 = load <2 x half>, ptr %10, align 4
   %32 = load <2 x half>, ptr %11, align 4
@@ -126,7 +127,7 @@ define dso_local spir_func void @__clang_ocl_kern_imp_quant_add(ptr addrspace(3)
 
 declare dso_local spir_func i32 @_Z13get_global_idj(i32 noundef) #1
 
-declare dso_local spir_func <2 x half> @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELDv2_i(<2 x i4> noundef) #2
+declare dso_local spir_func <2 x half> @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTDv2_i(<2 x i4> noundef) #2
 
 attributes #0 = { convergent noinline norecurse nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size"="false" }
 attributes #1 = { convergent nounwind willreturn memory(none) "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
diff --git a/test/extensions/INTEL/SPV_INTEL_float4/upscale_o2.ll b/test/extensions/EXT/SPV_EXT_ocp_microscaling_types/upscale_o2.ll
similarity index 80%
rename from test/extensions/INTEL/SPV_INTEL_float4/upscale_o2.ll
rename to test/extensions/EXT/SPV_EXT_ocp_microscaling_types/upscale_o2.ll
index 64e097a2c4..3451f24ba8 100644
--- a/test/extensions/INTEL/SPV_INTEL_float4/upscale_o2.ll
+++ b/test/extensions/EXT/SPV_EXT_ocp_microscaling_types/upscale_o2.ll
@@ -25,24 +25,25 @@
 ; clang -cl-std=cl3.0 -target spir -emit-llvm -Xclang -finclude-default-header -g0 -O2
 
 ; RUN: llvm-as %s -o %t.bc
-; RUN: llvm-spirv %t.bc -o %t.spv --spirv-ext=+SPV_INTEL_float4,+SPV_INTEL_int4
+; RUN: llvm-spirv %t.bc -o %t.spv --spirv-ext=+SPV_EXT_ocp_microscaling_types,+SPV_INTEL_int4
+; RUN: spirv-val %t.spv
 ; RUN: llvm-spirv %t.spv -o %t.spt --to-text
 ; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
 ; RUN: llvm-spirv %t.spv -o %t.rev.bc -r --spirv-target-env=SPV-IR
 ; RUN: llvm-dis %t.rev.bc -o %t.rev.ll
 ; RUN: FileCheck < %t.rev.ll %s --check-prefix=CHECK-LLVM
 
-; CHECK-SPIRV-NOT: _Z38__builtin_spirv_ConvertE2M1ToFP16INTELDv2_i
+; CHECK-SPIRV-NOT: _Z36__builtin_spirv_ConvertE2M1ToFP16EXTDv2_i
 
 ; CHECK-SPIRV-DAG: Capability Float16Buffer
 ; CHECK-SPIRV-DAG: Capability Int4TypeINTEL
-; CHECK-SPIRV-DAG: Capability Float4E2M1INTEL
+; CHECK-SPIRV-DAG: Capability Float4EXT
 
 ; CHECK-SPIRV-DAG: TypeInt [[#Int4Ty:]] 4 0
 ; CHECK-SPIRV-DAG: TypeVector [[#VecInt4Ty:]] [[#Int4Ty]] 2
 ; CHECK-SPIRV-DAG: TypeFloat [[#HalfTy:]] 16
 ; CHECK-SPIRV-DAG: TypeVector [[#VecHalfTy:]] [[#HalfTy]] 2
-; CHECK-SPIRV-DAG: TypeFloat [[#FP4Ty:]] 4 6214
+; CHECK-SPIRV-DAG: TypeFloat [[#FP4Ty:]] 4 4225
 ; CHECK-SPIRV-DAG: TypeVector [[#VecFP4Ty:]] [[#FP4Ty]] 2
 
 ; CHECK-SPIRV: Load [[#VecInt4Ty]] [[#VecInt4Val1:]] [[#]] 2 1
@@ -53,8 +54,8 @@
 ; CHECK-SPIRV: FConvert [[#VecHalfTy]] [[#Conv2:]] [[#Cast2]]
 ; CHECK-SPIRV: FAdd [[#VecHalfTy]] [[#]] [[#Conv1]] [[#Conv2]]
 
-; CHECK-LLVM: %[[#in1:]] = call spir_func <2 x half> @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELDv2_i(<2 x i4> %[[#]])
-; CHECK-LLVM: %[[#in2:]] = call spir_func <2 x half> @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELDv2_i(<2 x i4> %[[#]])
+; CHECK-LLVM: %[[#in1:]] = call spir_func <2 x half> @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTDv2_i(<2 x i4> %[[#]])
+; CHECK-LLVM: %[[#in2:]] = call spir_func <2 x half> @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTDv2_i(<2 x i4> %[[#]])
 ; CHECK-LLVM: fadd <2 x half> %[[#in1]], %[[#in2]]
 
 target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
@@ -66,8 +67,8 @@ define dso_local spir_kernel void @quant_add(ptr addrspace(3) noundef readonly a
   %6 = load <2 x i4>, ptr addrspace(3) %5, align 1
   %7 = getelementptr inbounds i8, ptr addrspace(3) %1, i32 %4
   %8 = load <2 x i4>, ptr addrspace(3) %7, align 1
-  %9 = tail call spir_func <2 x half> @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELDv2_i(<2 x i4> noundef %6) #5
-  %10 = tail call spir_func <2 x half> @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELDv2_i(<2 x i4> noundef %8) #5
+  %9 = tail call spir_func <2 x half> @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTDv2_i(<2 x i4> noundef %6) #5
+  %10 = tail call spir_func <2 x half> @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTDv2_i(<2 x i4> noundef %8) #5
   %11 = fadd <2 x half> %9, %10
   %12 = getelementptr inbounds <2 x half>, ptr addrspace(3) %2, i32 %4
   store <2 x half> %11, ptr addrspace(3) %12, align 4
@@ -80,8 +81,8 @@ define dso_local spir_func void @__clang_ocl_kern_imp_quant_add(ptr addrspace(3)
   %6 = load <2 x i4>, ptr addrspace(3) %5, align 1
   %7 = getelementptr inbounds i8, ptr addrspace(3) %1, i32 %4
   %8 = load <2 x i4>, ptr addrspace(3) %7, align 1
-  %9 = tail call spir_func <2 x half> @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELDv2_i(<2 x i4> noundef %6) #5
-  %10 = tail call spir_func <2 x half> @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELDv2_i(<2 x i4> noundef %8) #5
+  %9 = tail call spir_func <2 x half> @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTDv2_i(<2 x i4> noundef %6) #5
+  %10 = tail call spir_func <2 x half> @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTDv2_i(<2 x i4> noundef %8) #5
   %11 = fadd <2 x half> %9, %10
   %12 = getelementptr inbounds <2 x half>, ptr addrspace(3) %2, i32 %4
   store <2 x half> %11, ptr addrspace(3) %12, align 4
@@ -90,7 +91,7 @@ define dso_local spir_func void @__clang_ocl_kern_imp_quant_add(ptr addrspace(3)
 
 declare dso_local spir_func i32 @_Z13get_global_idj(i32 noundef) local_unnamed_addr #2
 
-declare dso_local spir_func <2 x half> @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELDv2_i(<2 x i4> noundef) local_unnamed_addr #3
+declare dso_local spir_func <2 x half> @_Z36__builtin_spirv_ConvertE2M1ToFP16EXTDv2_i(<2 x i4> noundef) local_unnamed_addr #3
 
 attributes #0 = { convergent norecurse nounwind "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size"="false" }
 attributes #1 = { alwaysinline convergent norecurse nounwind "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "uniform-work-group-size"="false" }
diff --git a/test/extensions/INTEL/SPV_INTEL_float4/conversions_intel_encoding.ll b/test/extensions/INTEL/SPV_INTEL_float4/conversions_intel_encoding.ll
new file mode 100644
index 0000000000..231b846359
--- /dev/null
+++ b/test/extensions/INTEL/SPV_INTEL_float4/conversions_intel_encoding.ll
@@ -0,0 +1,61 @@
+; Checks that FP4 (E2M1) conversion builtins with the INTEL postfix are
+; translated using the SPV_INTEL_float4 extension: the Float4E2M1INTEL
+; encoding (6214) and capability, rather than the Float4E2M1EXT encoding
+; from SPV_EXT_ocp_microscaling_types. Round-trips back to the INTEL builtins.
+
+; RUN: llvm-spirv %s -o %t.spv --spirv-ext=+SPV_INTEL_float4,+SPV_INTEL_int4,+SPV_KHR_bfloat16
+; RUN: llvm-spirv %t.spv -o %t.spt --to-text
+; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
+; RUN: llvm-spirv %t.spv -o %t.rev.bc -r --spirv-target-env=SPV-IR
+; RUN: llvm-dis %t.rev.bc -o %t.rev.ll
+; RUN: FileCheck < %t.rev.ll %s --check-prefix=CHECK-LLVM
+
+; CHECK-SPIRV-DAG: Capability Int4TypeINTEL
+; CHECK-SPIRV-DAG: Capability Float4E2M1INTEL
+; CHECK-SPIRV-DAG: Extension "SPV_INTEL_float4"
+; CHECK-SPIRV-DAG: Extension "SPV_INTEL_int4"
+
+; CHECK-SPIRV-DAG: Name [[#fp4e2m1_hf16_scalar:]] "fp4e2m1_hf16_scalar"
+; CHECK-SPIRV-DAG: Name [[#hf16_fp4e2m1_scalar:]] "hf16_fp4e2m1_scalar"
+
+; CHECK-SPIRV-DAG: TypeInt [[#Int4Ty:]] 4 0
+; CHECK-SPIRV-DAG: Constant [[#Int4Ty]] [[#Int4Const:]] 1
+; CHECK-SPIRV-DAG: TypeFloat [[#HFloat16Ty:]] 16 {{$}}
+; CHECK-SPIRV-DAG: TypeFloat [[#E2M1Ty:]] 4 6214
+
+target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+target triple = "spir-unknown-unknown"
+
+; CHECK-SPIRV: Function [[#]] [[#fp4e2m1_hf16_scalar]] [[#]]
+; CHECK-SPIRV: Bitcast [[#E2M1Ty]] [[#Cast:]] [[#Int4Const]]
+; CHECK-SPIRV: FConvert [[#HFloat16Ty]] [[#Conv:]] [[#Cast]]
+; CHECK-SPIRV: ReturnValue [[#Conv]]
+
+; CHECK-LLVM-LABEL: fp4e2m1_hf16_scalar
+; CHECK-LLVM: %[[#Call:]] = call spir_func half @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELi(i4 1)
+; CHECK-LLVM: ret half %[[#Call]]
+
+define spir_func half @fp4e2m1_hf16_scalar() {
+entry:
+  %0 = call spir_func half @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELi(i4 1)
+  ret half %0
+}
+
+declare dso_local spir_func half @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELi(i4)
+
+; CHECK-SPIRV: Function [[#]] [[#hf16_fp4e2m1_scalar]] [[#]]
+; CHECK-SPIRV: FConvert [[#E2M1Ty]] [[#Conv:]] [[#]]
+; CHECK-SPIRV: Bitcast [[#Int4Ty]] [[#Cast:]] [[#Conv]]
+; CHECK-SPIRV: ReturnValue [[#Cast]]
+
+; CHECK-LLVM-LABEL: hf16_fp4e2m1_scalar
+; CHECK-LLVM: %[[#Call:]] = call spir_func i4 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDh(half 1.000000e+00)
+; CHECK-LLVM: ret i4 %[[#Call]]
+
+define spir_func i4 @hf16_fp4e2m1_scalar() {
+entry:
+  %0 = call spir_func i4 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDh(half 1.0)
+  ret i4 %0
+}
+
+declare dso_local spir_func i4 @_Z38__builtin_spirv_ConvertFP16ToE2M1INTELDh(half)
diff --git a/test/extensions/INTEL/SPV_INTEL_float4/cooperative_matrix.ll b/test/extensions/INTEL/SPV_INTEL_float4/cooperative_matrix.ll
new file mode 100644
index 0000000000..e9b09e5dac
--- /dev/null
+++ b/test/extensions/INTEL/SPV_INTEL_float4/cooperative_matrix.ll
@@ -0,0 +1,63 @@
+; Checks that Float4E2M1EXT encoding is preserved through a round-trip
+; translation when it's used as a cooperative-matrix component type.
+
+; RUN: llvm-spirv %s -o %t.spv --spirv-ext=+SPV_EXT_ocp_microscaling_types,+SPV_KHR_cooperative_matrix,+SPV_INTEL_int4
+; TODO: re-enable spirv-val once it can recognize Float4E2M1CooperativeMatrixINTEL capability (6213).
+; RUNx: spirv-val %t.spv
+; RUN: llvm-spirv %t.spv -o %t.spt --to-text
+; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
+; RUN: llvm-spirv %t.spv -o %t.rev.bc -r --spirv-target-env=SPV-IR
+; RUN: llvm-dis %t.rev.bc -o %t.rev.ll
+; RUN: FileCheck < %t.rev.ll %s --check-prefix=CHECK-LLVM
+
+; CHECK-SPIRV-DAG: Capability CooperativeMatrixKHR
+; CHECK-SPIRV-DAG: Capability Float4EXT
+; CHECK-SPIRV-DAG: Capability Float4E2M1CooperativeMatrixINTEL
+; CHECK-SPIRV-DAG: Extension "SPV_EXT_ocp_microscaling_types"
+; CHECK-SPIRV-DAG: Extension "SPV_KHR_cooperative_matrix"
+
+; CHECK-SPIRV-DAG: TypeInt [[#Int4Ty:]] 4 0
+; CHECK-SPIRV-DAG: TypeFloat [[#FP16Ty:]] 16
+; CHECK-SPIRV-DAG: TypeFloat [[#FP4Ty:]] 4 4225
+; CHECK-SPIRV-DAG: TypeCooperativeMatrixKHR [[#Int4MatrixTy:]] [[#Int4Ty]]
+; CHECK-SPIRV-DAG: TypeCooperativeMatrixKHR [[#FP16MatrixTy:]] [[#FP16Ty]]
+; CHECK-SPIRV-DAG: TypeCooperativeMatrixKHR [[#FP4MatrixTy:]] [[#FP4Ty]]
+
+; CHECK-SPIRV: CompositeConstruct [[#FP16MatrixTy]] [[#M:]] [[#]]
+; CHECK-SPIRV: FConvert [[#FP4MatrixTy]] [[#Conv:]] [[#M]]
+; CHECK-SPIRV: Bitcast [[#Int4MatrixTy]] [[#]] [[#Conv]]
+
+; CHECK-LLVM: %[[#M:]] = call spir_func target("spirv.CooperativeMatrixKHR", half, 3, 12, 12, 2) @_Z26__spirv_CompositeConstructDh(half 0.000000e+00)
+; CHECK-LLVM: call spir_func target("spirv.CooperativeMatrixKHR", i4, 3, 12, 12, 2) @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTPU3AS144__spirv_CooperativeMatrixKHR__half_3_12_12_2(target("spirv.CooperativeMatrixKHR", half, 3, 12, 12, 2) %[[#M]])
+
+; ModuleID = 'test.bc'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-G1"
+target triple = "spir-unknown-unknown"
+
+; Function Attrs: nounwind
+define spir_func void @fp16_fp4_matrix() #0 {
+entry:
+  %0 = call spir_func target("spirv.CooperativeMatrixKHR", half, 3, 12, 12, 2) @_Z26__spirv_CompositeConstructDh(half 0.0) #0
+  %1 = call spir_func target("spirv.CooperativeMatrixKHR", i4, 3, 12, 12, 2) @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTPU3AS144__spirv_CooperativeMatrixKHR__half_3_12_12_2(target("spirv.CooperativeMatrixKHR", half, 3, 12, 12, 2) %0)
+  ret void
+}
+
+; Function Attrs: nounwind
+declare spir_func target("spirv.CooperativeMatrixKHR", half, 3, 12, 12, 2) @_Z26__spirv_CompositeConstructDh(half) #0
+
+declare spir_func target("spirv.CooperativeMatrixKHR", i4, 3, 12, 12, 2) @_Z36__builtin_spirv_ConvertFP16ToE2M1EXTPU3AS144__spirv_CooperativeMatrixKHR__half_3_12_12_2(target("spirv.CooperativeMatrixKHR", half, 3, 12, 12, 2))
+
+attributes #0 = { nounwind }
+
+!spirv.MemoryModel = !{!0}
+!opencl.enable.FP_CONTRACT = !{}
+!spirv.Source = !{!1}
+!opencl.spir.version = !{!0}
+!opencl.used.extensions = !{!2}
+!opencl.used.optional.core.features = !{!2}
+!spirv.Generator = !{!3}
+
+!0 = !{i32 1, i32 2}
+!1 = !{i32 0, i32 0}
+!2 = !{}
+!3 = !{i16 6, i16 14}
diff --git a/test/extensions/INTEL/SPV_INTEL_float4/legacy_intel_encoding_read.spt b/test/extensions/INTEL/SPV_INTEL_float4/legacy_intel_encoding_read.spt
new file mode 100644
index 0000000000..45b41f9c2f
--- /dev/null
+++ b/test/extensions/INTEL/SPV_INTEL_float4/legacy_intel_encoding_read.spt
@@ -0,0 +1,36 @@
+; Verify that SPIR-V using the Float4E2M1INTEL encoding (6214) from
+; SPV_INTEL_float4 is consumed and round-trips back to the INTEL builtin,
+; rather than the Float4E2M1EXT encoding from SPV_EXT_ocp_microscaling_types.
+
+; RUN: llvm-spirv %s -to-binary -o %t.spv
+; RUN: llvm-spirv %t.spv -r --spirv-target-env=SPV-IR -o %t.rev.bc
+; RUN: llvm-dis %t.rev.bc -o - | FileCheck %s --check-prefix=CHECK-LLVM
+
+; CHECK-LLVM: call spir_func half @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELi(i4 1)
+
+119734787 65536 393230 11 0
+2 Capability Addresses
+2 Capability Linkage
+2 Capability Kernel
+2 Capability Float16Buffer
+2 Capability Float4E2M1INTEL
+2 Capability Int4TypeINTEL
+6 Extension "SPV_INTEL_float4"
+5 Extension "SPV_INTEL_int4"
+5 ExtInstImport 1 "OpenCL.std"
+3 MemoryModel 1 2
+3 Source 0 0
+3 Name 4 "f"
+4 Name 5 "entry"
+5 Decorate 4 LinkageAttributes "f" Export
+4 TypeInt 6 4 0
+4 Constant 6 7 1
+3 TypeFloat 2 16
+3 TypeFunction 3 2
+4 TypeFloat 8 4 6214
+5 Function 2 4 0 3
+2 Label 5
+4 Bitcast 8 9 7
+4 FConvert 2 10 9
+2 ReturnValue 10
+1 FunctionEnd
diff --git a/test/extensions/INTEL/SPV_INTEL_float4/no_intel_float4.ll b/test/extensions/INTEL/SPV_INTEL_float4/no_intel_float4.ll
new file mode 100644
index 0000000000..7410952123
--- /dev/null
+++ b/test/extensions/INTEL/SPV_INTEL_float4/no_intel_float4.ll
@@ -0,0 +1,18 @@
+; Checks that an *INTEL FP4 conversion builtin fails to translate when
+; SPV_INTEL_float4 is not enabled.
+
+; RUN: not llvm-spirv %s -o %t.spv --spirv-ext=+SPV_INTEL_int4 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
+
+; CHECK-ERROR: RequiresExtension: Feature requires the following SPIR-V extension:
+; CHECK-ERROR-NEXT: SPV_INTEL_float4
+
+target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+target triple = "spir-unknown-unknown"
+
+define spir_func half @intel_conv() {
+entry:
+  %r = call spir_func half @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELi(i4 1)
+  ret half %r
+}
+
+declare dso_local spir_func half @_Z38__builtin_spirv_ConvertE2M1ToFP16INTELi(i4)
diff --git a/test/extensions/INTEL/SPV_INTEL_fp_conversions/spv_intel_fp_conversions.ll b/test/extensions/INTEL/SPV_INTEL_fp_conversions/spv_intel_fp_conversions.ll
index 9dc747f312..2479fbab71 100644
--- a/test/extensions/INTEL/SPV_INTEL_fp_conversions/spv_intel_fp_conversions.ll
+++ b/test/extensions/INTEL/SPV_INTEL_fp_conversions/spv_intel_fp_conversions.ll
@@ -4,7 +4,9 @@
 ; Packed and vector conversions are tested for general case, this test is only
 ; for scalar
 
-; RUN: llvm-spirv %s -o %t.spv --spirv-ext=+SPV_EXT_float8,+SPV_INTEL_float4,+SPV_INTEL_int4,+SPV_KHR_bfloat16,+SPV_INTEL_fp_conversions
+; RUN: llvm-spirv %s -o %t.spv --spirv-ext=+SPV_EXT_float8,+SPV_EXT_ocp_microscaling_types,+SPV_INTEL_int4,+SPV_KHR_bfloat16,+SPV_INTEL_fp_conversions
+; TODO: re-enable spirv-val once it recognizes the FloatConversionsFtoFINTEL capability (6215)
+; RUNx: spirv-val %t.spv
 ; RUN: llvm-spirv %t.spv -o %t.spt --to-text
 ; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
 ; RUN: llvm-spirv %t.spv -o %t.rev.bc -r
@@ -13,12 +15,13 @@
 
 ; CHECK-SPIRV-DAG: Capability Int4TypeINTEL
 ; CHECK-SPIRV-DAG: Capability Float8EXT
+; CHECK-SPIRV-DAG: Capability Float4EXT
 ; CHECK-SPIRV-DAG: Capability FloatConversionsFtoFINTEL
 ; CHECK-SPIRV-DAG: Capability FloatConversionsFtoSINTEL
 
 ; CHECK-SPIRV-DAG: Extension "SPV_INTEL_int4"
 ; CHECK-SPIRV-DAG: Extension "SPV_EXT_float8"
-; CHECK-SPIRV-DAG: Extension "SPV_INTEL_float4"
+; CHECK-SPIRV-DAG: Extension "SPV_EXT_ocp_microscaling_types"
 ; CHECK-SPIRV-DAG: Extension "SPV_INTEL_fp_conversions"
 
 ; CHECK-SPIRV-DAG: Name [[#hf16_hf8_clamp:]] "hf16_hf8_clamp"
@@ -60,7 +63,7 @@
 ; CHECK-SPIRV-DAG: Constant [[#Int32Ty]] [[#Int32Const:]] 1
 ; CHECK-SPIRV-DAG: TypeInt [[#Int4Ty:]] 4 0
 
-; CHECK-SPIRV-DAG: TypeFloat [[#E2M1Ty:]] 4 6214
+; CHECK-SPIRV-DAG: TypeFloat [[#E2M1Ty:]] 4 4225
 ; CHECK-SPIRV-DAG: TypeFloat [[#HFloat8Ty:]] 8 4214
 ; CHECK-SPIRV-DAG: TypeFloat [[#BFloat8Ty:]] 8 4215