diff --git a/.gitattributes b/.gitattributes new file mode 100644 index 00000000..dfe07704 --- /dev/null +++ b/.gitattributes @@ -0,0 +1,2 @@ +# Auto detect text files and perform LF normalization +* text=auto diff --git a/.gitignore b/.gitignore new file mode 100644 index 00000000..cf6289bd --- /dev/null +++ b/.gitignore @@ -0,0 +1,167 @@ +################# +## Eclipse +################# + +*.pydevproject +.project +.metadata +bin/ +tmp/ +*.tmp +*.bak +*.swp +*~.nib +local.properties +.classpath +.settings/ +.loadpath + +# External tool builders +.externalToolBuilders/ + +# Locally stored "Eclipse launch configurations" +*.launch + +# CDT-specific +.cproject + +# PDT-specific +.buildpath + + +################# +## Visual Studio +################# + +## Ignore Visual Studio temporary files, build results, and +## files generated by popular Visual Studio add-ons. + +# User-specific files +*.suo +*.user +*.sln.docstates + +# Build results +[Dd]ebug/ +[Rr]elease/ +*_i.c +*_p.c +*.ilk +*.meta +*.obj +*.pch +*.pdb +*.pgc +*.pgd +*.rsp +*.sbr +*.tlb +*.tli +*.tlh +*.tmp +*.vspscc +.builds +*.dotCover + +## TODO: If you have NuGet Package Restore enabled, uncomment this +#packages/ + +# Visual C++ cache files +ipch/ +*.aps +*.ncb +*.opensdf +*.sdf + +# Visual Studio profiler +*.psess +*.vsp + +# ReSharper is a .NET coding add-in +_ReSharper* + +# Installshield output folder +[Ee]xpress + +# DocProject is a documentation generator add-in +DocProject/buildhelp/ +DocProject/Help/*.HxT +DocProject/Help/*.HxC +DocProject/Help/*.hhc +DocProject/Help/*.hhk +DocProject/Help/*.hhp +DocProject/Help/Html2 +DocProject/Help/html + +# Click-Once directory +publish + +# Others +[Bb]in +[Oo]bj +sql +TestResults +*.Cache +ClientBin +stylecop.* +~$* +*.dbmdl +Generated_Code #added for RIA/Silverlight projects + +# Backup & report files from converting an old project file to a newer +# Visual Studio version. Backup files are not needed, because we have git ;-) +_UpgradeReport_Files/ +Backup*/ +UpgradeLog*.XML + + + +############ +## Windows +############ + +# Windows image file caches +Thumbs.db + +# Folder config file +Desktop.ini + + +############# +## Python +############# + +*.py[co] + +# Packages +*.egg +*.egg-info +dist +build +eggs +parts +bin +var +sdist +develop-eggs +.installed.cfg + +# Installer logs +pip-log.txt + +# Unit test / coverage reports +.coverage +.tox + +#Translations +*.mo + +#Mr Developer +.mr.developer.cfg + +# Mac crap +.DS_Store + + + +prototype/firmware/EDBG UART erert/EDBG UART erert/.atmel-start-backup/* diff --git a/BaseStation.md b/BaseStation.md new file mode 100644 index 00000000..3a1bf26d --- /dev/null +++ b/BaseStation.md @@ -0,0 +1,103 @@ +# Ideas for Imperial College HAB Ground Station + + + +The HAB base station is proposed to be installed on the roof of the 10 story Electrical Engineering Building at Imperial College South Kensington. +It will be used to receive and transmit telemetry with high altitude balloons. + +## Objectives +* Safe, secure, and College Approved installation +* High reliability - 12 month preventative maintenance cycle +* Remote controlled and managed +* Improve logistics for Wormwood Scrubs launches. Reduce need for launch site tracking +* Support of Open HAB community by tracking balloons in UK near-space +* Establish Imperial College Base Station as a high quality and trusted monitoring station for near space activity in the UK Region. + +## Applications +* To track balloons launched by the Imperial College Space Society, especially during launches from London +* To track radiosondes launched by the Meterological service and add to a central database, [sondehub.org](https://tracker.sondehub.org) + +## Frequencies and Modes + +### Receive +* 70cm Amateur Band +* License exempt 433.05 - 434.79 MHz. All Modes, including LoRa. +* ??? 2m Amateur band, APRS mode +* ??? License exempt 868 MHz +### Transmit +* License exempt 434.040– 434.790 MHz 10 mW ERP 25 kHz bandwidth and 433.05 - 434.79 MHz 1mW ERP 25kHz bandwidth. All Modes, including LoRa. +* No transmission in Amateur Bands + + + +## Radio Hardware +* SDR Radio on Raspberry Pi +* LoRa shield on Raspberry Pi + +## Radio Firmware +* Multi channel RTTY reception +* Remote tuning +* Interface to HAB Hub + +## Antenna +* 434MHz colinear +* ??? one or two, amplifier and splitter? Front end SAW filters ? TX/RX switching? +* ??? 2m +* ??? 868MHz +* Do we need lightening protection ? + + +## Utilities +* Power over Ethernet +* 10/100 Mbps Ethernet on IC network + +## Physical +* IP68 Enclosure +* ??? Cabling +* ??Mounting hardware + + + +## License + +Hardware is Licensed under CERN OHL v.1.2 or later https://www.ohwr.org/documents/294 No warranty is provided for this documentation implied or otherwise. + +Software is licensed under MIT License. + +MIT License + +Copyright (c) 2018 Imperial College Space Society + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/README.md b/README.md new file mode 100644 index 00000000..45cb114f --- /dev/null +++ b/README.md @@ -0,0 +1 @@ +# Pico Balloon Tracker Version 2.0 ## Objectives This Pico balloon tracker is the second version to be designed by Imperial College Space Society. It is intended to offer an easy to build and low cost entry for people who want to launch small Helium filled balloons with a small tracking payload. While the previous version used already built commercial modules for the radio, GPS and power supply, this version is built from basic components. Ideally, it should be able to fly around the world on board a small balloon. ## License Hardware is Licensed under CERN OHL v.1.2 or later https://www.ohwr.org/documents/294 No warranty is provided for this documentation implied or otherwise. Software is licensed under MIT License. MIT License Copyright (c) 2018 Imperial College Space Society Derived Software Copyright (c) 2014 Richard Meadows Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. \ No newline at end of file diff --git a/References.md b/References.md new file mode 100644 index 00000000..8f7efae4 --- /dev/null +++ b/References.md @@ -0,0 +1,90 @@ +# Links to Useful Documents + +## SAM L21 +[Datasheet and Reference manual](https://www.farnell.com/datasheets/2014285.pdf) + +[Atmel� Software Framework (ASF) Reference Manual](http://ww1.microchip.com/downloads/en/AppNotes/Atmel-42699-ASF-Manual-(SAML21)_ApplicationNote_AT11513.pdf) + +[Getting started guidelines](http://ww1.microchip.com/downloads/en/AppNotes/atmel-42410-getting-started-with-saml21_application%20note_at03975.pdf) + +[SAM L21 Xplained Pro manual](http://ww1.microchip.com/downloads/en/devicedoc/atmel-42405-saml21-xplained-pro_user-guide.pdf) + + + + +## Si4468 +[Datasheet](https://www.silabs.com/documents/public/data-sheets/Si4464-63-61-60.pdf) + +[Programming Guide](https://www.silabs.com/documents/public/application-notes/AN633.pdf) + +[API Documentation](http://www.silabs.com/documents/public/application-notes/EZRadioPRO_REVB1_API.zip) + + + + + +## Bristol SEDS + +[Main Page](http://www.bristol-seds.co.uk/) + +[PicoTracker GitHub](https://github.com/bristol-seds/pico-tracker) + + + +## HAB + +[UKHAS Google Group](https://groups.google.com/forum/#!forum/ukhas%5B261-280%5D) + + + +## uBlox + + +[BN-220](https://surehobby.com/desc/HR/HR5512/BN_220_GPS_Antenna_datasheet.pdf) + +[UBX-M8030 Specification](https://www.u-blox.com/sites/default/files/products/documents/UBX-M8030-KT-FT_ProductSummary_%28UBX-14001605%29.pdf) + +[Protocol Specification](https://www.u-blox.com/sites/default/files/products/documents/u-blox8-M8_ReceiverDescrProtSpec_%28UBX-13003221%29_Public.pdf) + +## BME280 + + +[BME280 Data Sheet](https://www.embeddedadventures.com/datasheets/BME280.pdf) + +[Official Bosch C Driver](https://github.com/BoschSensortec/BME280_driver) + +[Larry Banks C library](https://github.com/bitbank2/bme280) + + +## RFM98W + + +[Datasheet](http://www.farnell.com/datasheets/1870822.pdf) + +[SX127x Datasheet](https://cdn-shop.adafruit.com/product-files/3179/sx1276_77_78_79.pdf) + +[C Code example](https://github.com/wdomski/SX1278-example) + + +## UKHAS Lora + + +[Tracking Guide](https://ukhas.org.uk/guides:lora_tracking_guide) + +## Stuart Robinsons Tracker + +[Lora Tracker](http://www.loratracker.uk/?p=30) + +[Github](https://github.com/LoRaTracker) + +## TomasTT7 Trackers + +[TT7B Tracker Blog](http://tt7hab.blogspot.com/2018/09/the-tt7b-tracker.html) + +[tt7B Github](https://github.com/TomasTT7/TT7B-Tracker) + + +## Pi in the Sky + + +[Lora Tracker](http://www.pi-in-the-sky.com/index.php?id=making-a-lora-tracker) diff --git a/Spice/SX1276144M.asc b/Spice/SX1276144M.asc new file mode 100644 index 00000000..44f1352f --- /dev/null +++ b/Spice/SX1276144M.asc @@ -0,0 +1,82 @@ +Version 4 +SHEET 1 880 680 +WIRE 48 112 0 112 +WIRE 128 112 112 112 +WIRE 176 112 128 112 +WIRE 256 112 240 112 +WIRE -320 208 -368 208 +WIRE -128 208 -240 208 +WIRE 0 208 0 112 +WIRE 0 208 -48 208 +WIRE 32 208 0 208 +WIRE 128 208 128 112 +WIRE 128 208 112 208 +WIRE 160 208 128 208 +WIRE 256 208 256 112 +WIRE 256 208 240 208 +WIRE 432 208 256 208 +WIRE -368 240 -368 208 +WIRE 432 256 432 208 +WIRE 0 272 0 208 +WIRE 128 272 128 208 +WIRE 256 272 256 208 +WIRE -368 368 -368 320 +WIRE 0 368 0 336 +WIRE 128 368 128 336 +WIRE 256 368 256 336 +WIRE 432 368 432 336 +FLAG 0 368 0 +FLAG 128 368 0 +FLAG 256 368 0 +FLAG 432 368 0 +FLAG -368 368 0 +SYMBOL cap -16 272 R0 +SYMATTR InstName C1 +SYMATTR Value 47p +SYMBOL cap 112 272 R0 +SYMATTR InstName C2 +SYMATTR Value 47p +SYMBOL cap 240 272 R0 +SYMATTR InstName C3 +SYMATTR Value 27p +SYMBOL ind 16 224 R270 +WINDOW 0 32 56 VTop 2 +WINDOW 3 5 56 VBottom 2 +SYMATTR InstName L1 +SYMATTR Value 39n +SYMBOL ind 144 224 R270 +WINDOW 0 32 56 VTop 2 +WINDOW 3 5 56 VBottom 2 +SYMATTR InstName L2 +SYMATTR Value 39n +SYMBOL cap 240 96 R90 +WINDOW 0 0 32 VBottom 2 +WINDOW 3 32 32 VTop 2 +SYMATTR InstName C5 +SYMATTR Value 0p +SYMBOL res 416 240 R0 +SYMATTR InstName R1 +SYMATTR Value 50 +SYMBOL res -224 192 R90 +WINDOW 0 0 56 VBottom 2 +WINDOW 3 32 56 VTop 2 +SYMATTR InstName R2 +SYMATTR Value 50 +SYMBOL voltage -368 224 R0 +WINDOW 123 24 124 Left 2 +WINDOW 39 0 0 Left 0 +SYMATTR InstName V1 +SYMATTR Value SINE() +SYMATTR Value2 AC 1 +SYMBOL cap 112 96 R90 +WINDOW 0 0 32 VBottom 2 +WINDOW 3 32 32 VTop 2 +SYMATTR InstName C4 +SYMATTR Value 4p7 +SYMBOL ind -144 224 R270 +WINDOW 0 32 56 VTop 2 +WINDOW 3 5 56 VBottom 2 +SYMATTR InstName L3 +SYMATTR Value 39n +TEXT 272 416 Left 2 !.ac dec 100 100Meg 1000Meg +TEXT -432 56 Left 2 ;SX1276 144MHz Low Pass Filter diff --git a/Spice/SX1276144MHz.JPG b/Spice/SX1276144MHz.JPG new file mode 100644 index 00000000..045ad207 Binary files /dev/null and b/Spice/SX1276144MHz.JPG differ diff --git a/Spice/SX1276434M.asc b/Spice/SX1276434M.asc new file mode 100644 index 00000000..332d2349 --- /dev/null +++ b/Spice/SX1276434M.asc @@ -0,0 +1,82 @@ +Version 4 +SHEET 1 880 680 +WIRE 48 112 0 112 +WIRE 128 112 112 112 +WIRE 176 112 128 112 +WIRE 256 112 240 112 +WIRE -320 208 -368 208 +WIRE -128 208 -240 208 +WIRE 0 208 0 112 +WIRE 0 208 -48 208 +WIRE 32 208 0 208 +WIRE 128 208 128 112 +WIRE 128 208 112 208 +WIRE 160 208 128 208 +WIRE 256 208 256 112 +WIRE 256 208 240 208 +WIRE 432 208 256 208 +WIRE -368 240 -368 208 +WIRE 432 256 432 208 +WIRE 0 272 0 208 +WIRE 128 272 128 208 +WIRE 256 272 256 208 +WIRE -368 368 -368 320 +WIRE 0 368 0 336 +WIRE 128 368 128 336 +WIRE 256 368 256 336 +WIRE 432 368 432 336 +FLAG 0 368 0 +FLAG 128 368 0 +FLAG 256 368 0 +FLAG 432 368 0 +FLAG -368 368 0 +SYMBOL cap -16 272 R0 +SYMATTR InstName C1 +SYMATTR Value 15p +SYMBOL cap 112 272 R0 +SYMATTR InstName C2 +SYMATTR Value 12p +SYMBOL cap 240 272 R0 +SYMATTR InstName C3 +SYMATTR Value 4p7 +SYMBOL ind 16 224 R270 +WINDOW 0 32 56 VTop 2 +WINDOW 3 5 56 VBottom 2 +SYMATTR InstName L1 +SYMATTR Value 12n +SYMBOL ind 144 224 R270 +WINDOW 0 32 56 VTop 2 +WINDOW 3 5 56 VBottom 2 +SYMATTR InstName L2 +SYMATTR Value 18n +SYMBOL cap 240 96 R90 +WINDOW 0 0 32 VBottom 2 +WINDOW 3 32 32 VTop 2 +SYMATTR InstName C5 +SYMATTR Value 0p +SYMBOL res 416 240 R0 +SYMATTR InstName R1 +SYMATTR Value 50 +SYMBOL res -224 192 R90 +WINDOW 0 0 56 VBottom 2 +WINDOW 3 32 56 VTop 2 +SYMATTR InstName R2 +SYMATTR Value 50 +SYMBOL voltage -368 224 R0 +WINDOW 123 24 124 Left 2 +WINDOW 39 0 0 Left 0 +SYMATTR Value2 AC 1 +SYMATTR InstName V1 +SYMATTR Value SINE() +SYMBOL cap 112 96 R90 +WINDOW 0 0 32 VBottom 2 +WINDOW 3 32 32 VTop 2 +SYMATTR InstName C4 +SYMATTR Value 2p7 +SYMBOL ind -144 224 R270 +WINDOW 0 32 56 VTop 2 +WINDOW 3 5 56 VBottom 2 +SYMATTR InstName L3 +SYMATTR Value 22n +TEXT 272 416 Left 2 !.ac dec 100 100Meg 1000Meg +TEXT -432 56 Left 2 ;SX1276 434MHz Low Pass Filter diff --git a/Spice/SX1276434MHz.JPG b/Spice/SX1276434MHz.JPG new file mode 100644 index 00000000..0ab6dafa Binary files /dev/null and b/Spice/SX1276434MHz.JPG differ diff --git a/Spice/SX1276868M.asc b/Spice/SX1276868M.asc new file mode 100644 index 00000000..8d7e254b --- /dev/null +++ b/Spice/SX1276868M.asc @@ -0,0 +1,82 @@ +Version 4 +SHEET 1 880 680 +WIRE 48 112 0 112 +WIRE 128 112 112 112 +WIRE 176 112 128 112 +WIRE 256 112 240 112 +WIRE -320 208 -368 208 +WIRE -128 208 -240 208 +WIRE 0 208 0 112 +WIRE 0 208 -48 208 +WIRE 32 208 0 208 +WIRE 128 208 128 112 +WIRE 128 208 112 208 +WIRE 160 208 128 208 +WIRE 256 208 256 112 +WIRE 256 208 240 208 +WIRE 432 208 256 208 +WIRE -368 240 -368 208 +WIRE 432 256 432 208 +WIRE 0 272 0 208 +WIRE 128 272 128 208 +WIRE 256 272 256 208 +WIRE -368 368 -368 320 +WIRE 0 368 0 336 +WIRE 128 368 128 336 +WIRE 256 368 256 336 +WIRE 432 368 432 336 +FLAG 0 368 0 +FLAG 128 368 0 +FLAG 256 368 0 +FLAG 432 368 0 +FLAG -368 368 0 +SYMBOL cap -16 272 R0 +SYMATTR InstName C1 +SYMATTR Value 8p2 +SYMBOL cap 112 272 R0 +SYMATTR InstName C2 +SYMATTR Value 3p3 +SYMBOL cap 240 272 R0 +SYMATTR InstName C3 +SYMATTR Value 0p +SYMBOL ind 16 224 R270 +WINDOW 0 32 56 VTop 2 +WINDOW 3 5 56 VBottom 2 +SYMATTR InstName L1 +SYMATTR Value 4n7 +SYMBOL ind 144 224 R270 +WINDOW 0 32 56 VTop 2 +WINDOW 3 5 56 VBottom 2 +SYMATTR InstName L2 +SYMATTR Value 0n +SYMBOL cap 240 96 R90 +WINDOW 0 0 32 VBottom 2 +WINDOW 3 32 32 VTop 2 +SYMATTR InstName C5 +SYMATTR Value 0p +SYMBOL res 416 240 R0 +SYMATTR InstName R1 +SYMATTR Value 50 +SYMBOL res -224 192 R90 +WINDOW 0 0 56 VBottom 2 +WINDOW 3 32 56 VTop 2 +SYMATTR InstName R2 +SYMATTR Value 50 +SYMBOL voltage -368 224 R0 +WINDOW 123 24 124 Left 2 +WINDOW 39 0 0 Left 0 +SYMATTR Value2 AC 1 +SYMATTR InstName V1 +SYMATTR Value SINE() +SYMBOL cap 112 96 R90 +WINDOW 0 0 32 VBottom 2 +WINDOW 3 32 32 VTop 2 +SYMATTR InstName C4 +SYMATTR Value 1p5 +SYMBOL ind -144 224 R270 +WINDOW 0 32 56 VTop 2 +WINDOW 3 5 56 VBottom 2 +SYMATTR InstName L3 +SYMATTR Value 5n6 +TEXT 272 416 Left 2 !.ac dec 100 100Meg 2000Meg +TEXT -432 56 Left 2 ;SX1276 434MHz Low Pass Filter diff --git a/Spice/SX1276868MHz.JPG b/Spice/SX1276868MHz.JPG new file mode 100644 index 00000000..ba9b760e Binary files /dev/null and b/Spice/SX1276868MHz.JPG differ diff --git a/prototype/Prototype.md b/prototype/Prototype.md new file mode 100644 index 00000000..e079168e --- /dev/null +++ b/prototype/Prototype.md @@ -0,0 +1 @@ +# Prototype It was decided to prototype key features of the new tracker on develop board before starting detail of hardware and firmware design. We choose the Atmel ATSAML21 processor for the design, so used the ATSAML21-XPRO-B development board under Atmel Studio Version 7. The development board has powerful debug capability including power profiling. \ No newline at end of file diff --git a/prototype/firmware/BME280/.vs/BME280/v14/.atsuo b/prototype/firmware/BME280/.vs/BME280/v14/.atsuo new file mode 100644 index 00000000..18205857 Binary files /dev/null and b/prototype/firmware/BME280/.vs/BME280/v14/.atsuo differ diff --git a/prototype/firmware/BME280/BME280.atsln b/prototype/firmware/BME280/BME280.atsln new file mode 100644 index 00000000..5b3f417e --- /dev/null +++ b/prototype/firmware/BME280/BME280.atsln @@ -0,0 +1,22 @@ + +Microsoft Visual Studio Solution File, Format Version 12.00 +# Atmel Studio Solution File, Format Version 11.00 +VisualStudioVersion = 14.0.23107.0 +MinimumVisualStudioVersion = 10.0.40219.1 +Project("{54F91283-7BC4-4236-8FF9-10F437C3AD48}") = "BME280", "BME280\BME280.cproj", "{DCE6C7E3-EE26-4D79-826B-08594B9AD897}" +EndProject +Global + GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug|ARM = Debug|ARM + Release|ARM = Release|ARM + EndGlobalSection + GlobalSection(ProjectConfigurationPlatforms) = postSolution + {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|ARM.ActiveCfg = Debug|ARM + {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|ARM.Build.0 = Debug|ARM + {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|ARM.ActiveCfg = Release|ARM + {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|ARM.Build.0 = Release|ARM + EndGlobalSection + GlobalSection(SolutionProperties) = preSolution + HideSolutionNode = FALSE + EndGlobalSection +EndGlobal diff --git a/prototype/firmware/BME280/BME280/.atmelstart/AtmelStart.env_conf b/prototype/firmware/BME280/BME280/.atmelstart/AtmelStart.env_conf new file mode 100644 index 00000000..ecbeeb71 --- /dev/null +++ b/prototype/firmware/BME280/BME280/.atmelstart/AtmelStart.env_conf @@ -0,0 +1,6 @@ + + + + + + diff --git a/prototype/firmware/BME280/BME280/.atmelstart/AtmelStart.gpdsc b/prototype/firmware/BME280/BME280/.atmelstart/AtmelStart.gpdsc new file mode 100644 index 00000000..a3591632 --- /dev/null +++ b/prototype/firmware/BME280/BME280/.atmelstart/AtmelStart.gpdsc @@ -0,0 +1,207 @@ + + Atmel + My Project + Project generated by Atmel Start + http://start.atmel.com/ + + Initial version + + + Configuration Files generated by Atmel Start + + + + Atmel Start + + http://start.atmel.com/ + + + + + + + + + Dependency on CMSIS core and Device Startup components + + + + + + + + + + + + + + + + + Atmel Start Framework + #define ATMEL_START + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/.atmelstart/atmel_start_config.atstart b/prototype/firmware/EDBG UART erert/EDBG UART erert/.atmelstart/atmel_start_config.atstart new file mode 100644 index 00000000..b1e7e76a --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/.atmelstart/atmel_start_config.atstart @@ -0,0 +1,803 @@ +format_version: '2' +name: My Project +versions: + api: '1.0' + backend: 1.5.122 + commit: 820baecf7dd115d94b0d42ee3b0b9d6ba2da7113 + content: 1.0.1498 + content_pack_name: acme-packs-all + format: '2' + frontend: 1.5.1877 +board: + identifier: SAML21XplainedPro + device: SAML21J18B-AU +details: null +application: null +middlewares: {} +drivers: + DMAC: + user_label: DMAC + definition: Atmel:SAML21_Drivers:0.0.1::SAML21J18B-AU::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC + functionality: System + api: HAL:HPL:DMAC + configuration: + dmac_beatsize_0: 8-bit bus transfer + dmac_beatsize_1: 8-bit bus transfer + dmac_beatsize_10: 8-bit bus transfer + dmac_beatsize_11: 8-bit bus transfer + dmac_beatsize_12: 8-bit bus transfer + dmac_beatsize_13: 8-bit bus transfer + dmac_beatsize_14: 8-bit bus transfer + dmac_beatsize_15: 8-bit bus transfer + dmac_beatsize_2: 8-bit bus transfer + dmac_beatsize_3: 8-bit bus transfer + dmac_beatsize_4: 8-bit bus transfer + dmac_beatsize_5: 8-bit bus transfer + dmac_beatsize_6: 8-bit bus transfer + dmac_beatsize_7: 8-bit bus transfer + dmac_beatsize_8: 8-bit bus transfer + dmac_beatsize_9: 8-bit bus transfer + dmac_blockact_0: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_1: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_10: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_11: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_12: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_13: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_14: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_15: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_2: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_3: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_4: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_5: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_6: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_7: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_8: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_9: Channel will be disabled if it is the last block transfer in + the transaction + dmac_channel_0_settings: false + dmac_channel_10_settings: false + dmac_channel_11_settings: false + dmac_channel_12_settings: false + dmac_channel_13_settings: false + dmac_channel_14_settings: false + dmac_channel_15_settings: false + dmac_channel_1_settings: false + dmac_channel_2_settings: false + dmac_channel_3_settings: false + dmac_channel_4_settings: false + dmac_channel_5_settings: false + dmac_channel_6_settings: false + dmac_channel_7_settings: false + dmac_channel_8_settings: false + dmac_channel_9_settings: false + dmac_dbgrun: false + dmac_dqos: Background (no sensitive operation) + dmac_dstinc_0: false + dmac_dstinc_1: false + dmac_dstinc_10: false + dmac_dstinc_11: false + dmac_dstinc_12: false + dmac_dstinc_13: false + dmac_dstinc_14: false + dmac_dstinc_15: false + dmac_dstinc_2: false + dmac_dstinc_3: false + dmac_dstinc_4: false + dmac_dstinc_5: false + dmac_dstinc_6: false + dmac_dstinc_7: false + dmac_dstinc_8: false + dmac_dstinc_9: false + dmac_enable: false + dmac_enable_0: false + dmac_enable_1: false + dmac_enable_10: false + dmac_enable_11: false + dmac_enable_12: false + dmac_enable_13: false + dmac_enable_14: false + dmac_enable_15: false + dmac_enable_2: false + dmac_enable_3: false + dmac_enable_4: false + dmac_enable_5: false + dmac_enable_6: false + dmac_enable_7: false + dmac_enable_8: false + dmac_enable_9: false + dmac_evact_0: No action + dmac_evact_1: No action + dmac_evact_10: No action + dmac_evact_11: No action + dmac_evact_12: No action + dmac_evact_13: No action + dmac_evact_14: No action + dmac_evact_15: No action + dmac_evact_2: No action + dmac_evact_3: No action + dmac_evact_4: No action + dmac_evact_5: No action + dmac_evact_6: No action + dmac_evact_7: No action + dmac_evact_8: No action + dmac_evact_9: No action + dmac_evie_0: false + dmac_evie_1: false + dmac_evie_10: false + dmac_evie_11: false + dmac_evie_12: false + dmac_evie_13: false + dmac_evie_14: false + dmac_evie_15: false + dmac_evie_2: false + dmac_evie_3: false + dmac_evie_4: false + dmac_evie_5: false + dmac_evie_6: false + dmac_evie_7: false + dmac_evie_8: false + dmac_evie_9: false + dmac_evoe_0: false + dmac_evoe_1: false + dmac_evoe_10: false + dmac_evoe_11: false + dmac_evoe_12: false + dmac_evoe_13: false + dmac_evoe_14: false + dmac_evoe_15: false + dmac_evoe_2: false + dmac_evoe_3: false + dmac_evoe_4: false + dmac_evoe_5: false + dmac_evoe_6: false + dmac_evoe_7: false + dmac_evoe_8: false + dmac_evoe_9: false + dmac_evosel_0: Event generation disabled + dmac_evosel_1: Event generation disabled + dmac_evosel_10: Event generation disabled + dmac_evosel_11: Event generation disabled + dmac_evosel_12: Event generation disabled + dmac_evosel_13: Event generation disabled + dmac_evosel_14: Event generation disabled + dmac_evosel_15: Event generation disabled + dmac_evosel_2: Event generation disabled + dmac_evosel_3: Event generation disabled + dmac_evosel_4: Event generation disabled + dmac_evosel_5: Event generation disabled + dmac_evosel_6: Event generation disabled + dmac_evosel_7: Event generation disabled + dmac_evosel_8: Event generation disabled + dmac_evosel_9: Event generation disabled + dmac_fqos: Background (no sensitive operation) + dmac_lvl_0: Channel priority 0 + dmac_lvl_1: Channel priority 0 + dmac_lvl_10: Channel priority 0 + dmac_lvl_11: Channel priority 0 + dmac_lvl_12: Channel priority 0 + dmac_lvl_13: Channel priority 0 + dmac_lvl_14: Channel priority 0 + dmac_lvl_15: Channel priority 0 + dmac_lvl_2: Channel priority 0 + dmac_lvl_3: Channel priority 0 + dmac_lvl_4: Channel priority 0 + dmac_lvl_5: Channel priority 0 + dmac_lvl_6: Channel priority 0 + dmac_lvl_7: Channel priority 0 + dmac_lvl_8: Channel priority 0 + dmac_lvl_9: Channel priority 0 + dmac_lvlen0: false + dmac_lvlen1: false + dmac_lvlen2: false + dmac_lvlen3: false + dmac_lvlpri0: 0 + dmac_lvlpri1: 0 + dmac_lvlpri2: 0 + dmac_lvlpri3: 0 + dmac_rrlvlen0: Static arbitration scheme for channel with priority 0 + dmac_rrlvlen1: Static arbitration scheme for channel with priority 1 + dmac_rrlvlen2: Static arbitration scheme for channel with priority 2 + dmac_rrlvlen3: Static arbitration scheme for channel with priority 3 + dmac_runstdby_0: false + dmac_runstdby_1: false + dmac_runstdby_10: false + dmac_runstdby_11: false + dmac_runstdby_12: false + dmac_runstdby_13: false + dmac_runstdby_14: false + dmac_runstdby_15: false + dmac_runstdby_2: false + dmac_runstdby_3: false + dmac_runstdby_4: false + dmac_runstdby_5: false + dmac_runstdby_6: false + dmac_runstdby_7: false + dmac_runstdby_8: false + dmac_runstdby_9: false + dmac_srcinc_0: false + dmac_srcinc_1: false + dmac_srcinc_10: false + dmac_srcinc_11: false + dmac_srcinc_12: false + dmac_srcinc_13: false + dmac_srcinc_14: false + dmac_srcinc_15: false + dmac_srcinc_2: false + dmac_srcinc_3: false + dmac_srcinc_4: false + dmac_srcinc_5: false + dmac_srcinc_6: false + dmac_srcinc_7: false + dmac_srcinc_8: false + dmac_srcinc_9: false + dmac_stepsel_0: Step size settings apply to the destination address + dmac_stepsel_1: Step size settings apply to the destination address + dmac_stepsel_10: Step size settings apply to the destination address + dmac_stepsel_11: Step size settings apply to the destination address + dmac_stepsel_12: Step size settings apply to the destination address + dmac_stepsel_13: Step size settings apply to the destination address + dmac_stepsel_14: Step size settings apply to the destination address + dmac_stepsel_15: Step size settings apply to the destination address + dmac_stepsel_2: Step size settings apply to the destination address + dmac_stepsel_3: Step size settings apply to the destination address + dmac_stepsel_4: Step size settings apply to the destination address + dmac_stepsel_5: Step size settings apply to the destination address + dmac_stepsel_6: Step size settings apply to the destination address + dmac_stepsel_7: Step size settings apply to the destination address + dmac_stepsel_8: Step size settings apply to the destination address + dmac_stepsel_9: Step size settings apply to the destination address + dmac_stepsize_0: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_1: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_10: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_11: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_12: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_13: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_14: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_15: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_2: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_3: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_4: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_5: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_6: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_7: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_8: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_9: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_trifsrc_0: Only software/event triggers + dmac_trifsrc_1: Only software/event triggers + dmac_trifsrc_10: Only software/event triggers + dmac_trifsrc_11: Only software/event triggers + dmac_trifsrc_12: Only software/event triggers + dmac_trifsrc_13: Only software/event triggers + dmac_trifsrc_14: Only software/event triggers + dmac_trifsrc_15: Only software/event triggers + dmac_trifsrc_2: Only software/event triggers + dmac_trifsrc_3: Only software/event triggers + dmac_trifsrc_4: Only software/event triggers + dmac_trifsrc_5: Only software/event triggers + dmac_trifsrc_6: Only software/event triggers + dmac_trifsrc_7: Only software/event triggers + dmac_trifsrc_8: Only software/event triggers + dmac_trifsrc_9: Only software/event triggers + dmac_trigact_0: One trigger required for each block transfer + dmac_trigact_1: One trigger required for each block transfer + dmac_trigact_10: One trigger required for each block transfer + dmac_trigact_11: One trigger required for each block transfer + dmac_trigact_12: One trigger required for each block transfer + dmac_trigact_13: One trigger required for each block transfer + dmac_trigact_14: One trigger required for each block transfer + dmac_trigact_15: One trigger required for each block transfer + dmac_trigact_2: One trigger required for each block transfer + dmac_trigact_3: One trigger required for each block transfer + dmac_trigact_4: One trigger required for each block transfer + dmac_trigact_5: One trigger required for each block transfer + dmac_trigact_6: One trigger required for each block transfer + dmac_trigact_7: One trigger required for each block transfer + dmac_trigact_8: One trigger required for each block transfer + dmac_trigact_9: One trigger required for each block transfer + dmac_wrbqos: Background (no sensitive operation) + optional_signals: [] + variant: null + clocks: + domain_group: null + GCLK: + user_label: GCLK + definition: Atmel:SAML21_Drivers:0.0.1::SAML21J18B-AU::GCLK::driver_config_definition::GCLK::HAL:HPL:GCLK + functionality: System + api: HAL:HPL:GCLK + configuration: + enable_gclk_gen_0: true + enable_gclk_gen_1: false + enable_gclk_gen_2: false + enable_gclk_gen_3: false + enable_gclk_gen_4: false + enable_gclk_gen_5: false + enable_gclk_gen_6: false + enable_gclk_gen_7: false + gclk_arch_gen_0_enable: true + gclk_arch_gen_0_idc: false + gclk_arch_gen_0_oe: false + gclk_arch_gen_0_oov: false + gclk_arch_gen_0_runstdby: false + gclk_arch_gen_1_enable: false + gclk_arch_gen_1_idc: false + gclk_arch_gen_1_oe: false + gclk_arch_gen_1_oov: false + gclk_arch_gen_1_runstdby: false + gclk_arch_gen_2_enable: false + gclk_arch_gen_2_idc: false + gclk_arch_gen_2_oe: false + gclk_arch_gen_2_oov: false + gclk_arch_gen_2_runstdby: false + gclk_arch_gen_3_enable: false + gclk_arch_gen_3_idc: false + gclk_arch_gen_3_oe: false + gclk_arch_gen_3_oov: false + gclk_arch_gen_3_runstdby: false + gclk_arch_gen_4_enable: false + gclk_arch_gen_4_idc: false + gclk_arch_gen_4_oe: false + gclk_arch_gen_4_oov: false + gclk_arch_gen_4_runstdby: false + gclk_arch_gen_5_enable: false + gclk_arch_gen_5_idc: false + gclk_arch_gen_5_oe: false + gclk_arch_gen_5_oov: false + gclk_arch_gen_5_runstdby: false + gclk_arch_gen_6_enable: false + gclk_arch_gen_6_idc: false + gclk_arch_gen_6_oe: false + gclk_arch_gen_6_oov: false + gclk_arch_gen_6_runstdby: false + gclk_arch_gen_7_enable: false + gclk_arch_gen_7_idc: false + gclk_arch_gen_7_oe: false + gclk_arch_gen_7_oov: false + gclk_arch_gen_7_runstdby: false + gclk_gen_0_div: 1 + gclk_gen_0_div_sel: false + gclk_gen_0_oscillator: 16MHz Internal Oscillator (OSC16M) + gclk_gen_1_div: 1 + gclk_gen_1_div_sel: false + gclk_gen_1_oscillator: 16MHz Internal Oscillator (OSC16M) + gclk_gen_2_div: 1 + gclk_gen_2_div_sel: false + gclk_gen_2_oscillator: 32kHz High Accuracy Internal Oscillator (OSC32K) + gclk_gen_3_div: 1 + gclk_gen_3_div_sel: false + gclk_gen_3_oscillator: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) + gclk_gen_4_div: 1 + gclk_gen_4_div_sel: false + gclk_gen_4_oscillator: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) + gclk_gen_5_div: 1 + gclk_gen_5_div_sel: false + gclk_gen_5_oscillator: 32kHz High Accuracy Internal Oscillator (OSC32K) + gclk_gen_6_div: 1 + gclk_gen_6_div_sel: false + gclk_gen_6_oscillator: 32kHz High Accuracy Internal Oscillator (OSC32K) + gclk_gen_7_div: 1 + gclk_gen_7_div_sel: false + gclk_gen_7_oscillator: 32kHz High Accuracy Internal Oscillator (OSC32K) + optional_signals: [] + variant: null + clocks: + domain_group: null + MCLK: + user_label: MCLK + definition: Atmel:SAML21_Drivers:0.0.1::SAML21J18B-AU::MCLK::driver_config_definition::MCLK::HAL:HPL:MCLK + functionality: System + api: HAL:HPL:MCLK + configuration: + cpu_clock_source: Generic clock generator 0 + cpu_div: '1' + enable_cpu_clock: true + mclk_arch_bupdiv: Divide by 8 + mclk_arch_lpdiv: Divide by 4 + nvm_wait_states: '0' + optional_signals: [] + variant: null + clocks: + domain_group: + nodes: + - name: CPU + input: CPU + external: false + external_frequency: 0 + configuration: {} + OSC32KCTRL: + user_label: OSC32KCTRL + definition: Atmel:SAML21_Drivers:0.0.1::SAML21J18B-AU::OSC32KCTRL::driver_config_definition::OSC32KCTRL::HAL:HPL:OSC32KCTRL + functionality: System + api: HAL:HPL:OSC32KCTRL + configuration: + enable_osc32k: false + enable_osculp32k: true + enable_rtc_source: false + enable_xosc32k: false + osc32k_arch_calib: 0 + osc32k_arch_calib_enable: false + osc32k_arch_en1k: false + osc32k_arch_en32k: false + osc32k_arch_enable: false + osc32k_arch_ondemand: false + osc32k_arch_runstdby: false + osc32k_arch_startup: 92us + osculp32k_calib: 0 + osculp32k_calib_enable: false + rtc_1khz_selection: false + rtc_source_oscillator: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) + xosc32k_arch_en1k: false + xosc32k_arch_en32k: false + xosc32k_arch_enable: false + xosc32k_arch_ondemand: true + xosc32k_arch_runstdby: false + xosc32k_arch_startup: 62592us + xosc32k_arch_xtalen: true + optional_signals: [] + variant: null + clocks: + domain_group: null + OSCCTRL: + user_label: OSCCTRL + definition: Atmel:SAML21_Drivers:0.0.1::SAML21J18B-AU::OSCCTRL::driver_config_definition::OSCCTRL::HAL:HPL:OSCCTRL + functionality: System + api: HAL:HPL:OSCCTRL + configuration: + dfll48m_arch_enable: false + dfll48m_mode: Open Loop Mode + dfll48m_mul: 0 + dfll48m_ref_clock: Generic clock generator 3 + dfll_arch_bplckc: false + dfll_arch_calibration: false + dfll_arch_ccdis: false + dfll_arch_coarse: 31 + dfll_arch_cstep: 1 + dfll_arch_fine: 512 + dfll_arch_fstep: 1 + dfll_arch_llaw: false + dfll_arch_ondemand: true + dfll_arch_qldis: false + dfll_arch_runstdby: false + dfll_arch_stable: false + dfll_arch_usbcrm: false + dfll_arch_waitlock: false + enable_dfll48m: false + enable_fdpll96m: false + enable_osc16m: true + enable_xosc: false + fdpll96m_arch_enable: false + fdpll96m_arch_filter: Default filter mode + fdpll96m_arch_lbypass: false + fdpll96m_arch_lpen: false + fdpll96m_arch_ltime: No time-out, automatic lock + fdpll96m_arch_ondemand: true + fdpll96m_arch_refclk: XOSC32K clock reference + fdpll96m_arch_runstdby: false + fdpll96m_arch_wuf: false + fdpll96m_clock_div: 0 + fdpll96m_ldr: 1463 + fdpll96m_ldrfrac: 13 + fdpll96m_presc: '1' + fdpll96m_ref_clock: 32kHz External Crystal Oscillator (XOSC32K) + osc16m_arch_12m_fcal: 0 + osc16m_arch_12m_tcal: 0 + osc16m_arch_16m_tcal: 0 + osc16m_arch_4m_fcal: 0 + osc16m_arch_4m_tcal: 0 + osc16m_arch_8m_fcal: 0 + osc16m_arch_8m_tcal: 0 + osc16m_arch_calib_enable: false + osc16m_arch_enable: true + osc16m_arch_fcal: 0 + osc16m_arch_ondemand: true + osc16m_arch_runstdby: false + osc16m_freq: '4' + xosc_arch_ampgc: false + xosc_arch_enable: false + xosc_arch_gain: 2MHz + xosc_arch_ondemand: true + xosc_arch_runstdby: false + xosc_arch_startup: 31us + xosc_arch_xtalen: false + xosc_frequency: 400000 + optional_signals: [] + variant: null + clocks: + domain_group: null + PORT: + user_label: PORT + definition: Atmel:SAML21_Drivers:0.0.1::SAML21J18B-AU::PORT::driver_config_definition::PORT::HAL:HPL:PORT + functionality: System + api: HAL:HPL:PORT + configuration: + enable_port_input_event_0: false + enable_port_input_event_1: false + enable_port_input_event_2: false + enable_port_input_event_3: false + porta_event_action_0: Output register of pin will be set to level of event + porta_event_action_1: Output register of pin will be set to level of event + porta_event_action_2: Output register of pin will be set to level of event + porta_event_action_3: Output register of pin will be set to level of event + porta_event_pin_identifier_0: 0 + porta_event_pin_identifier_1: 0 + porta_event_pin_identifier_2: 0 + porta_event_pin_identifier_3: 0 + porta_input_event_enable_0: false + porta_input_event_enable_1: false + porta_input_event_enable_2: false + porta_input_event_enable_3: false + portb_event_action_0: Output register of pin will be set to level of event + portb_event_action_1: Output register of pin will be set to level of event + portb_event_action_2: Output register of pin will be set to level of event + portb_event_action_3: Output register of pin will be set to level of event + portb_event_pin_identifier_0: 0 + portb_event_pin_identifier_1: 0 + portb_event_pin_identifier_2: 0 + portb_event_pin_identifier_3: 0 + portb_input_event_enable_0: false + portb_input_event_enable_1: false + portb_input_event_enable_2: false + portb_input_event_enable_3: false + optional_signals: [] + variant: null + clocks: + domain_group: null + USART_0: + user_label: USART_0 + definition: Atmel:SAML21_Drivers:0.0.1::SAML21J18B-AU::SERCOM1::driver_config_definition::UART::HAL:Driver:USART.Sync + functionality: USART + api: HAL:Driver:USART_Sync + configuration: + usart_advanced: false + usart_arch_clock_mode: USART with internal clock + usart_arch_cloden: false + usart_arch_dbgstop: Keep running + usart_arch_dord: LSB is transmitted first + usart_arch_enc: No encoding + usart_arch_fractional: 0 + usart_arch_ibon: false + usart_arch_lin_slave_enable: Disable + usart_arch_runstdby: false + usart_arch_sampa: 7-8-9 (3-4-5 8-bit over-sampling) + usart_arch_sampr: 16x arithmetic + usart_arch_sfde: false + usart_baud_rate: 9600 + usart_character_size: 8 bits + usart_parity: No parity + usart_rx_enable: true + usart_stop_bit: One stop bit + usart_tx_enable: true + optional_signals: [] + variant: + specification: TXPO=1, RXPO=3, CMODE=0 + required_signals: + - name: SERCOM1/PAD/2 + pad: PA18 + label: TX + - name: SERCOM1/PAD/3 + pad: PA19 + label: RX + clocks: + domain_group: + nodes: + - name: Core + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Slow + input: Generic clock generator 3 + external: false + external_frequency: 0 + configuration: + core_gclk_selection: Generic clock generator 0 + slow_gclk_selection: Generic clock generator 3 + I2C_0: + user_label: I2C_0 + definition: Atmel:SAML21_Drivers:0.0.1::SAML21J18B-AU::SERCOM2::driver_config_definition::I2C.Master.Standard~2FFast-mode::HAL:Driver:I2C.Master.Sync + functionality: I2C + api: HAL:Driver:I2C_Master_Sync + configuration: + i2c_master_advanced: false + i2c_master_arch_dbgstop: Keep running + i2c_master_arch_inactout: Disabled + i2c_master_arch_lowtout: false + i2c_master_arch_mexttoen: false + i2c_master_arch_runstdby: false + i2c_master_arch_sdahold: 300-600ns hold time + i2c_master_arch_sexttoen: false + i2c_master_arch_trise: 215 + i2c_master_baud_rate: 100000 + optional_signals: [] + variant: + specification: SDA=0, SCL=1 + required_signals: + - name: SERCOM2/PAD/0 + pad: PA08 + label: SDA + - name: SERCOM2/PAD/1 + pad: PA09 + label: SCL + clocks: + domain_group: + nodes: + - name: Core + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Slow + input: Generic clock generator 3 + external: false + external_frequency: 0 + configuration: + core_gclk_selection: Generic clock generator 0 + slow_gclk_selection: Generic clock generator 3 + EDBG_COM_1: + user_label: EDBG_COM_1 + definition: Atmel:SAML21_Drivers:0.0.1::SAML21J18B-AU::SERCOM3::driver_config_definition::UART::HAL:Driver:USART.Sync + functionality: USART + api: HAL:Driver:USART_Sync + configuration: + usart_advanced: false + usart_arch_clock_mode: USART with internal clock + usart_arch_cloden: false + usart_arch_dbgstop: Keep running + usart_arch_dord: LSB is transmitted first + usart_arch_enc: No encoding + usart_arch_fractional: 0 + usart_arch_ibon: false + usart_arch_lin_slave_enable: Disable + usart_arch_runstdby: false + usart_arch_sampa: 7-8-9 (3-4-5 8-bit over-sampling) + usart_arch_sampr: 16x arithmetic + usart_arch_sfde: false + usart_baud_rate: 9600 + usart_character_size: 8 bits + usart_parity: No parity + usart_rx_enable: true + usart_stop_bit: One stop bit + usart_tx_enable: true + optional_signals: [] + variant: + specification: TXPO=0, RXPO=1, CMODE=0 + required_signals: + - name: SERCOM3/PAD/0 + pad: PA22 + label: TX + - name: SERCOM3/PAD/1 + pad: PA23 + label: RX + clocks: + domain_group: + nodes: + - name: Core + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Slow + input: Generic clock generator 3 + external: false + external_frequency: 0 + configuration: + core_gclk_selection: Generic clock generator 0 + slow_gclk_selection: Generic clock generator 3 + SPI_0: + user_label: SPI_0 + definition: Atmel:SAML21_Drivers:0.0.1::SAML21J18B-AU::SERCOM5::driver_config_definition::SPI.Master::HAL:Driver:SPI.Master.Sync + functionality: SPI + api: HAL:Driver:SPI_Master_Sync + configuration: + spi_master_advanced: false + spi_master_arch_cpha: Sample input on leading edge + spi_master_arch_cpol: SCK is low when idle + spi_master_arch_dbgstop: Keep running + spi_master_arch_dord: MSB first + spi_master_arch_ibon: In data stream + spi_master_arch_runstdby: false + spi_master_baud_rate: 50000 + spi_master_character_size: 8 bits + spi_master_dummybyte: 511 + spi_master_rx_enable: true + optional_signals: [] + variant: + specification: TXPO=1, RXPO=0 + required_signals: + - name: SERCOM5/PAD/0 + pad: PB16 + label: MISO + - name: SERCOM5/PAD/2 + pad: PB22 + label: MOSI + - name: SERCOM5/PAD/3 + pad: PB23 + label: SCK + clocks: + domain_group: + nodes: + - name: Core + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Slow + input: Generic clock generator 4 + external: false + external_frequency: 0 + configuration: + core_gclk_selection: Generic clock generator 0 + slow_gclk_selection: Generic clock generator 4 +pads: + PA08: + name: PA08 + definition: Atmel:SAML21_Drivers:0.0.1::SAML21J18B-AU::pad::PA08 + mode: I2C + user_label: PA08 + configuration: null + PA09: + name: PA09 + definition: Atmel:SAML21_Drivers:0.0.1::SAML21J18B-AU::pad::PA09 + mode: I2C + user_label: PA09 + configuration: null + LED0: + name: PB10 + definition: Atmel:SAML21_Drivers:0.0.1::SAML21J18B-AU::pad::PB10 + mode: Digital output + user_label: LED0 + configuration: + pad_initial_level: High + PA18: + name: PA18 + definition: Atmel:SAML21_Drivers:0.0.1::SAML21J18B-AU::pad::PA18 + mode: Peripheral IO + user_label: PA18 + configuration: null + PA19: + name: PA19 + definition: Atmel:SAML21_Drivers:0.0.1::SAML21J18B-AU::pad::PA19 + mode: Peripheral IO + user_label: PA19 + configuration: null + PB16: + name: PB16 + definition: Atmel:SAML21_Drivers:0.0.1::SAML21J18B-AU::pad::PB16 + mode: Digital input + user_label: PB16 + configuration: null + PA22: + name: PA22 + definition: Atmel:SAML21_Drivers:0.0.1::SAML21J18B-AU::pad::PA22 + mode: Peripheral IO + user_label: PA22 + configuration: null + PA23: + name: PA23 + definition: Atmel:SAML21_Drivers:0.0.1::SAML21J18B-AU::pad::PA23 + mode: Peripheral IO + user_label: PA23 + configuration: null + PB22: + name: PB22 + definition: Atmel:SAML21_Drivers:0.0.1::SAML21J18B-AU::pad::PB22 + mode: Digital output + user_label: PB22 + configuration: null + PB23: + name: PB23 + definition: Atmel:SAML21_Drivers:0.0.1::SAML21J18B-AU::pad::PB23 + mode: Digital output + user_label: PB23 + configuration: null +toolchain_options: [] diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/BME280.c b/prototype/firmware/EDBG UART erert/EDBG UART erert/BME280.c new file mode 100644 index 00000000..622e7cf3 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/BME280.c @@ -0,0 +1,191 @@ +/* + * BME280.c + * + * Created: 05/05/2019 15:30:16 + * Author: richard + */ +// Derived Work from: +// BME280 temperature/pressure/humidity sensor +// prototyping code to read and calculate calibrated values +// from the I2C bus +// +// Written by Larry Bank - 2/1/2017 +// Copyright (c) 2017 BitBank Software, Inc. +// bitbank@pobox.com +// + +#include +#include +#include "driver_init.h" + +struct io_descriptor *I2C_0_io; + + +// Sensor calibration data +static int calT1,calT2,calT3; +static int calP1, calP2, calP3, calP4, calP5, calP6, calP7, calP8, calP9; +static int calH1, calH2, calH3, calH4, calH5, calH6; + +// +// Opens a file system handle to the I2C device +// reads the calibration data and sets the device +// into auto sensing mode +// +int BME280Init(int iAddr) +{ + int i, rc; + uint8_t ucTemp[32]; + unsigned char ucCal[36]; + + i2c_m_sync_get_io_descriptor(&I2C_0, &I2C_0_io); + i2c_m_sync_enable(&I2C_0); + i2c_m_sync_set_slaveaddr(&I2C_0, iAddr, I2C_M_SEVEN); + + ucTemp[0] = 0xd0; // get ID + rc = io_write(I2C_0_io, ucTemp, 1); + + i = io_read(I2C_0_io, ucTemp, 1); + + if (rc < 0 || i != 1 || ucTemp[0] != 0x60) + { + //printf("Error, ID doesn't match 0x60; wrong device?\n"); + return -1; + } + // Read 24 bytes of calibration data + ucTemp[0] = 0x88; // starting 4from register 0x88 + rc = io_write(I2C_0_io, ucTemp, 1); + i = io_read(I2C_0_io, ucCal, 24); + if (rc < 0 || i != 24) + { + //printf("calibration data not read correctly\n"); + return -1; + } + ucTemp[0] = 0xa1; // get humidity calibration byte + rc = io_write(I2C_0_io, ucTemp, 1); + i = io_read(I2C_0_io, &ucCal[24], 1); + ucTemp[0] = 0xe1; // get 7 more humidity calibration bytes + rc = io_write(I2C_0_io, ucTemp, 1); + i = io_read(I2C_0_io, &ucCal[25], 7); + if (rc < 0 || i < 0) // something went wrong + {} + // Prepare temperature calibration data + calT1 = ucCal[0] + (ucCal[1] << 8); + calT2 = ucCal[2] + (ucCal[3] << 8); + if (calT2 > 32767) calT2 -= 65536; // negative value + calT3 = ucCal[4] + (ucCal[5] << 8); + if (calT3 > 32767) calT3 -= 65536; + + // Prepare pressure calibration data + calP1 = ucCal[6] + (ucCal[7] << 8); + calP2 = ucCal[8] + (ucCal[9] << 8); + if (calP2 > 32767) calP2 -= 65536; // signed short + calP3 = ucCal[10] + (ucCal[11] << 8); + if (calP3 > 32767) calP3 -= 65536; + calP4 = ucCal[12] + (ucCal[13] << 8); + if (calP4 > 32767) calP4 -= 65536; + calP5 = ucCal[14] + (ucCal[15] << 8); + if (calP5 > 32767) calP5 -= 65536; + calP6 = ucCal[16] + (ucCal[17] << 8); + if (calP6 > 32767) calP6 -= 65536; + calP7 = ucCal[18] + (ucCal[19] << 8); + if (calP7 > 32767) calP7 -= 65536; + calP8 = ucCal[20] + (ucCal[21] << 8); + if (calP8 > 32767) calP8 -= 65536; + calP9 = ucCal[22] + (ucCal[23] << 8); + if (calP9 > 32767) calP9 -= 65536; + + // Prepare humidity calibration data + calH1 = ucCal[24]; + calH2 = ucCal[25] + (ucCal[26] << 8); + if (calH2 > 32767) calH2 -= 65536; + calH3 = ucCal[27]; + calH4 = (ucCal[28] << 4) + (ucCal[29] & 0xf); + if (calH4 > 2047) calH4 -= 4096; // signed 12-bit + calH5 = (ucCal[30] << 4) + (ucCal[29] >> 4); + if (calH5 > 2047) calH5 -= 4096; + calH6 = ucCal[31]; + if (calH6 > 127) calH6 -= 256; // signed char + + ucTemp[0] = 0xf2; // control humidity register + ucTemp[1] = 0x01; // humidity over sampling rate = 1 + rc = io_write(I2C_0_io, ucTemp, 2); + + ucTemp[0] = 0xf4; // control measurement register + ucTemp[1] = 0x27; // normal mode, temp and pressure over sampling rate=1 + rc = io_write(I2C_0_io, ucTemp, 2); + + ucTemp[0] = 0xf5; // CONFIG + ucTemp[1] = 0xa0; // set stand by time to 1 second + rc = io_write(I2C_0_io, ucTemp, 2); + if (rc < 0) {} // suppress warning + + return 0; + + } /* bme280Init() */ + + // + // Read the sensor register values + // and translate them into calibrated readings + // using the previously loaded calibration data + // Temperature is expressed in Celsius degrees as T * 100 (for 2 decimal places) + // Pressure is + // Humidity is express as H * 1024 (10 bit fraction) + // + int bme280ReadValues(int *T, int *P, int *H) + { + unsigned char ucTemp[16]; + int i,rc; + int t, p, h; // raw sensor values + int var1,var2,t_fine; + int64_t P_64; + int64_t var1_64, var2_64; + + ucTemp[0] = 0xf7; // start of data registers we want + rc = io_write(I2C_0_io, ucTemp, 1); // write address of register to read + i = io_read(I2C_0_io, ucTemp, 8); + if (rc < 0 || i != 8) + { + return -1; // something went wrong + } + p = (ucTemp[0] << 12) + (ucTemp[1] << 4) + (ucTemp[2] >> 4); + t = (ucTemp[3] << 12) + (ucTemp[4] << 4) + (ucTemp[5] >> 4); + h = (ucTemp[6] << 8) + ucTemp[7]; + // printf("raw values: p = %d, t = %d, h = %d\n", p, t, h); + // Calculate calibrated temperature value + // the value is 100x C (e.g. 2601 = 26.01C) + var1 = ((((t >> 3) - (calT1 <<1))) * (calT2)) >> 11; + var2 = (((((t >> 4) - (calT1)) * ((t>>4) - (calT1))) >> 12) * (calT3)) >> 14; + t_fine = var1 + var2; + *T = (t_fine * 5 + 128) >> 8; + + // Calculate calibrated pressure value + var1_64 = t_fine - 128000; + var2_64 = var1_64 * var1_64 * (int64_t)calP6; + var2_64 = var2_64 + ((var1_64 * (int64_t)calP5) << 17); + var2_64 = var2_64 + (((int64_t)calP4) << 35); + var1_64 = ((var1_64 * var1_64 * (int64_t)calP3)>>8) + ((var1_64 * (int64_t)calP2)<<12); + var1_64 = (((((int64_t)1)<<47)+var1_64))*((int64_t)calP1)>>33; + if (var1_64 == 0) + { + *P = 0; + } + else + { + P_64 = 1048576 - p; + P_64 = (((P_64<<31)-var2_64)*3125)/var1_64; + var1_64 = (((int64_t)calP9) * (P_64>>13) * (P_64>>13)) >> 25; + var2_64 = (((int64_t)calP8) * P_64) >> 19; + P_64 = ((P_64 + var1_64 + var2_64) >> 8) + (((int64_t)calP7)<<4); + *P = (int)P_64 / 100; + } + // Calculate calibrated humidity value + var1 = (t_fine - 76800); + var1 = (((((h << 14) - ((calH4) << 20) - ((calH5) * var1)) + + (16384)) >> 15) * (((((((var1 * (calH6)) >> 10) * (((var1 * (calH3)) >> 11) + (32768))) >> 10) + (2097152)) * (calH2) + 8192) >> 14)); + var1 = (var1 - (((((var1 >> 15) * (var1 >> 15)) >> 7) * (calH1)) >> 4)); + var1 = (var1 < 0? 0 : var1); + var1 = (var1 > 419430400 ? 419430400 : var1); + *H = var1 >> 12; + return 0; + + } /* bme280ReadValues() */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/BME280.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/BME280.h new file mode 100644 index 00000000..6a943a64 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/BME280.h @@ -0,0 +1,24 @@ +/* + * BME280.h + * + * Created: 05/05/2019 15:27:04 + * Author: richard + */ +// Derived Work from: +// BME280 temperature/pressure/humidity sensor +// prototyping code to read and calculate calibrated values +// from the I2C bus +// +// Written by Larry Bank - 2/1/2017 +// Copyright (c) 2017 BitBank Software, Inc. +// bitbank@pobox.com +// + + +#ifndef __BME280__ +#define __BME280__ + +int BME280Init(int iAddr); +int bme280ReadValues(int *T, int *P, int *H); + +#endif // __BME280__ \ No newline at end of file diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/Basic Tracker.componentinfo.xml b/prototype/firmware/EDBG UART erert/EDBG UART erert/Basic Tracker.componentinfo.xml new file mode 100644 index 00000000..41ca9852 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/Basic Tracker.componentinfo.xml @@ -0,0 +1,169 @@ + + + + + + + CMSIS + CORE + + + ARM + 5.1.2 + C:/Program Files (x86)\Atmel\Studio\7.0\Packs + + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\ARM\CMSIS\5.4.0\CMSIS\Documentation\Core\html\index.html + + doc + + Q8N76dSMXRCvBEtXHmDLig== + + CMSIS/Documentation/Core/html/index.html + + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\ARM\CMSIS\5.4.0\CMSIS\Core\Include\ + + include + + + + CMSIS/Core/Include/ + + + + + CMSIS + C:/Program Files (x86)/Atmel/Studio/7.0/Packs/ARM/CMSIS/5.4.0/ARM.CMSIS.pdsc + 5.4.0 + true + ARMv6_7_8-M Device + + + + Resolved + Fixed + true + + + + + Device + Startup + + + Atmel + 1.2.0 + C:/Program Files (x86)\Atmel\Studio\7.0\Packs + + + + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\Atmel\SAML21_DFP\1.2.125\saml21b\include + + include + C + + + saml21b/include + + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\Atmel\SAML21_DFP\1.2.125\saml21b\include\sam.h + + header + C + tUyaDQL2CUvpNPje1XBiew== + + saml21b/include/sam.h + + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\Atmel\SAML21_DFP\1.2.125\saml21b\templates\main.c + template + source + C Exe + yjvxrPQ62Enour/VlwLquA== + + saml21b/templates/main.c + Main file (.c) + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\Atmel\SAML21_DFP\1.2.125\saml21b\templates\main.cpp + template + source + C Exe + nU+WlKcYaWh0AWBBS+WVpA== + + saml21b/templates/main.cpp + Main file (.cpp) + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\Atmel\SAML21_DFP\1.2.125\saml21b\gcc\system_saml21.c + config + source + GCC Exe + U+bOrHkMSAjACDLHAKXn+Q== + + saml21b/gcc/system_saml21.c + + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\Atmel\SAML21_DFP\1.2.125\saml21b\gcc\gcc\startup_saml21.c + config + source + GCC Exe + zijEzWB7CmllWulJu1ACzw== + + saml21b/gcc/gcc/startup_saml21.c + + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\Atmel\SAML21_DFP\1.2.125\saml21b\gcc\gcc\saml21j18b_flash.ld + config + linkerScript + GCC Exe + 4Sn9xSQH3dWLaW/jxl0XUw== + + saml21b/gcc/gcc/saml21j18b_flash.ld + + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\Atmel\SAML21_DFP\1.2.125\saml21b\gcc\gcc\saml21j18b_sram.ld + config + other + GCC Exe + ftBhgaPqM4tW/jKmhVu3mg== + + saml21b/gcc/gcc/saml21j18b_sram.ld + + + + + SAML21_DFP + C:/Program Files (x86)/Atmel/Studio/7.0/Packs/Atmel/SAML21_DFP/1.2.125/Atmel.SAML21_DFP.pdsc + 1.2.125 + true + ATSAML21J18B + + + + Resolved + Fixed + true + + + \ No newline at end of file diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/Basic Tracker.cproj b/prototype/firmware/EDBG UART erert/EDBG UART erert/Basic Tracker.cproj new file mode 100644 index 00000000..049cb092 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/Basic Tracker.cproj @@ -0,0 +1,825 @@ + + + + 2.0 + 7.0 + com.Atmel.ARMGCC.C + dce6c7e3-ee26-4d79-826b-08594b9ad897 + ATSAML21J18B + none + Executable + C + $(MSBuildProjectName) + .elf + $(MSBuildProjectDirectory)\$(Configuration) + EDBG UART erert + Basic Tracker + EDBG UART erert + Native + true + false + true + true + 0x20000000 + + true + exception_table + 2 + 0 + 0 + + .atmelstart\atmel_start_config.atstart + .atmelstart\AtmelStart.gpdsc + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + com.atmel.avrdbg.tool.edbg + ATML2241051800001930 + 0x1081020F + SWD + + + + 2000000 + + SWD + + com.atmel.avrdbg.tool.edbg + ATML2241051800001930 + EDBG MSD + + 2000000 + + + + + True + True + True + True + True + + + NDEBUG + + + + + %24(PackRepoDir)\ARM\CMSIS\5.4.0\CMSIS\Core\Include\ + ../Config + ../ + ../examples + ../hal/include + ../hal/utils/include + ../hpl/core + ../hpl/dmac + ../hpl/gclk + ../hpl/mclk + ../hpl/osc32kctrl + ../hpl/oscctrl + ../hpl/pm + ../hpl/port + ../hpl/sercom + ../hri + %24(PackRepoDir)\Atmel\SAML21_DFP\1.2.125\saml21b\include + + + Optimize for size (-Os) + True + True + True + + + libm + + + + + %24(ProjectDir)\Device_Startup + + + True + -Tsaml21j18b_flash.ld + + + %24(PackRepoDir)\ARM\CMSIS\5.4.0\CMSIS\Core\Include\ + ../Config + ../ + ../examples + ../hal/include + ../hal/utils/include + ../hpl/core + ../hpl/dmac + ../hpl/gclk + ../hpl/mclk + ../hpl/osc32kctrl + ../hpl/oscctrl + ../hpl/pm + ../hpl/port + ../hpl/sercom + ../hri + %24(PackRepoDir)\Atmel\SAML21_DFP\1.2.125\saml21b\include + + + + + %24(PackRepoDir)\ARM\CMSIS\5.4.0\CMSIS\Core\Include\ + ../Config + ../ + ../examples + ../hal/include + ../hal/utils/include + ../hpl/core + ../hpl/dmac + ../hpl/gclk + ../hpl/mclk + ../hpl/osc32kctrl + ../hpl/oscctrl + ../hpl/pm + ../hpl/port + ../hpl/sercom + ../hri + %24(PackRepoDir)\Atmel\SAML21_DFP\1.2.125\saml21b\include + + + + + + + + + True + True + True + True + True + + + DEBUG + + + + + %24(PackRepoDir)\ARM\CMSIS\5.4.0\CMSIS\Core\Include\ + ../Config + ../ + ../examples + ../hal/include + ../hal/utils/include + ../hpl/core + ../hpl/dmac + ../hpl/gclk + ../hpl/mclk + ../hpl/osc32kctrl + ../hpl/oscctrl + ../hpl/pm + ../hpl/port + ../hpl/sercom + ../hri + %24(PackRepoDir)\Atmel\SAML21_DFP\1.2.125\saml21b\include + + + Optimize (-O1) + True + Maximum (-g3) + True + True + + + libm + + + + + %24(ProjectDir)\Device_Startup + + + True + -Tsaml21j18b_flash.ld + + + %24(PackRepoDir)\ARM\CMSIS\5.4.0\CMSIS\Core\Include\ + ../Config + ../ + ../examples + ../hal/include + ../hal/utils/include + ../hpl/core + ../hpl/dmac + ../hpl/gclk + ../hpl/mclk + ../hpl/osc32kctrl + ../hpl/oscctrl + ../hpl/pm + ../hpl/port + ../hpl/sercom + ../hri + %24(PackRepoDir)\Atmel\SAML21_DFP\1.2.125\saml21b\include + + + Default (-g) + + + %24(PackRepoDir)\ARM\CMSIS\5.4.0\CMSIS\Core\Include\ + ../Config + ../ + ../examples + ../hal/include + ../hal/utils/include + ../hpl/core + ../hpl/dmac + ../hpl/gclk + ../hpl/mclk + ../hpl/osc32kctrl + ../hpl/oscctrl + ../hpl/pm + ../hpl/port + ../hpl/sercom + ../hri + %24(PackRepoDir)\Atmel\SAML21_DFP\1.2.125\saml21b\include + + + Default (-Wa,-g) + + + + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + + + + + + + + + + + + + + + + + + + + + + + + + + + compile + + + compile + + + + \ No newline at end of file diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/Config/RTE_Components.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/Config/RTE_Components.h new file mode 100644 index 00000000..625f93c9 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/Config/RTE_Components.h @@ -0,0 +1,54 @@ + /** + * \file + * + * \brief Autogenerated API include file for the Atmel Configuration Management Engine (ACME) + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \acme_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \acme_license_stop + * + * Project: GPS driver test + * Target: ATSAML21J18B + * + **/ + + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +#define ATMEL_START + +#endif /* RTE_COMPONENTS_H */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/Config/hpl_dmac_config.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/Config/hpl_dmac_config.h new file mode 100644 index 00000000..78aed2d5 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/Config/hpl_dmac_config.h @@ -0,0 +1,3154 @@ +/* Auto-generated config file hpl_dmac_config.h */ +#ifndef HPL_DMAC_CONFIG_H +#define HPL_DMAC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// DMAC enable +// Indicates whether dmac is enabled or not +// dmac_enable +#ifndef CONF_DMAC_ENABLE +#define CONF_DMAC_ENABLE 0 +#endif + +// Priority Level 0 +// Indicates whether Priority Level 0 is enabled or not +// dmac_lvlen0 +#ifndef CONF_DMAC_LVLEN0 +#define CONF_DMAC_LVLEN0 0 +#endif + +// Level 0 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 0 +// <1=> Round-robin arbitration scheme for channel with priority 0 +// Defines Level 0 Arbitration for DMA channels +// dmac_rrlvlen0 +#ifndef CONF_DMAC_RRLVLEN0 +#define CONF_DMAC_RRLVLEN0 0 +#endif + +// Level 0 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri0 +#ifndef CONF_DMAC_LVLPRI0 +#define CONF_DMAC_LVLPRI0 0 +#endif + +// Priority Level 1 +// Indicates whether Priority Level 1 is enabled or not +// dmac_lvlen1 +#ifndef CONF_DMAC_LVLEN1 +#define CONF_DMAC_LVLEN1 0 +#endif + +// Level 1 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 1 +// <1=> Round-robin arbitration scheme for channel with priority 1 +// Defines Level 1 Arbitration for DMA channels +// dmac_rrlvlen1 +#ifndef CONF_DMAC_RRLVLEN1 +#define CONF_DMAC_RRLVLEN1 0 +#endif + +// Level 1 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri1 +#ifndef CONF_DMAC_LVLPRI1 +#define CONF_DMAC_LVLPRI1 0 +#endif + +// Priority Level 2 +// Indicates whether Priority Level 2 is enabled or not +// dmac_lvlen2 +#ifndef CONF_DMAC_LVLEN2 +#define CONF_DMAC_LVLEN2 0 +#endif + +// Level 2 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 2 +// <1=> Round-robin arbitration scheme for channel with priority 2 +// Defines Level 2 Arbitration for DMA channels +// dmac_rrlvlen2 +#ifndef CONF_DMAC_RRLVLEN2 +#define CONF_DMAC_RRLVLEN2 0 +#endif + +// Level 2 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri2 +#ifndef CONF_DMAC_LVLPRI2 +#define CONF_DMAC_LVLPRI2 0 +#endif + +// Priority Level 3 +// Indicates whether Priority Level 3 is enabled or not +// dmac_lvlen3 +#ifndef CONF_DMAC_LVLEN3 +#define CONF_DMAC_LVLEN3 0 +#endif + +// Level 3 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 3 +// <1=> Round-robin arbitration scheme for channel with priority 3 +// Defines Level 3 Arbitration for DMA channels +// dmac_rrlvlen3 +#ifndef CONF_DMAC_RRLVLEN3 +#define CONF_DMAC_RRLVLEN3 0 +#endif + +// Level 3 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri3 +#ifndef CONF_DMAC_LVLPRI3 +#define CONF_DMAC_LVLPRI3 0 +#endif + +// Data Transfer Quality of Service +// <0=> Background (no sensitive operation) +// <1=> Sensitive bandwidth +// <2=> Sensitive latency +// <3=> Critical latency +// Defines the memory priority access during the data transfer operation +// dmac_dqos +#ifndef CONF_DMAC_DQOS +#define CONF_DMAC_DQOS 0 +#endif + +// Fetch Quality of Service +// <0=> Background (no sensitive operation) +// <1=> Sensitive bandwidth +// <2=> Sensitive latency +// <3=> Critical latency +// Defines the memory priority access during the fetch operation +// dmac_fqos +#ifndef CONF_DMAC_FQOS +#define CONF_DMAC_FQOS 0 +#endif + +// Write-Back Quality of Service +// <0=> Background (no sensitive operation) +// <1=> Sensitive bandwidth +// <2=> Sensitive latency +// <3=> Critical latency +// Defines the memory priority access during the write-back operation +// dmac_wrbqos +#ifndef CONF_DMAC_WRBQOS +#define CONF_DMAC_WRBQOS 0 +#endif + +// Debug Run +// Indicates whether Debug Run is enabled or not +// dmac_dbgrun +#ifndef CONF_DMAC_DBGRUN +#define CONF_DMAC_DBGRUN 0 +#endif + +// Channel 0 settings +// dmac_channel_0_settings +#ifndef CONF_DMAC_CHANNEL_0_SETTINGS +#define CONF_DMAC_CHANNEL_0_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 0 is enabled or not +// dmac_enable_0 +#ifndef CONF_DMAC_ENABLE_0 +#define CONF_DMAC_ENABLE_0 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 0 is running in standby mode or not +// dmac_runstdby_0 +#ifndef CONF_DMAC_RUNSTDBY_0 +#define CONF_DMAC_RUNSTDBY_0 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_0 +#ifndef CONF_DMAC_TRIGACT_0 +#define CONF_DMAC_TRIGACT_0 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_0 +#ifndef CONF_DMAC_TRIGSRC_0 +#define CONF_DMAC_TRIGSRC_0 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_0 +#ifndef CONF_DMAC_LVL_0 +#define CONF_DMAC_LVL_0 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_0 +#ifndef CONF_DMAC_EVOE_0 +#define CONF_DMAC_EVOE_0 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_0 +#ifndef CONF_DMAC_EVIE_0 +#define CONF_DMAC_EVIE_0 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_0 +#ifndef CONF_DMAC_EVACT_0 +#define CONF_DMAC_EVACT_0 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_0 +#ifndef CONF_DMAC_STEPSIZE_0 +#define CONF_DMAC_STEPSIZE_0 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_0 +#ifndef CONF_DMAC_STEPSEL_0 +#define CONF_DMAC_STEPSEL_0 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_0 +#ifndef CONF_DMAC_SRCINC_0 +#define CONF_DMAC_SRCINC_0 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_0 +#ifndef CONF_DMAC_DSTINC_0 +#define CONF_DMAC_DSTINC_0 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_0 +#ifndef CONF_DMAC_BEATSIZE_0 +#define CONF_DMAC_BEATSIZE_0 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_0 +#ifndef CONF_DMAC_BLOCKACT_0 +#define CONF_DMAC_BLOCKACT_0 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_0 +#ifndef CONF_DMAC_EVOSEL_0 +#define CONF_DMAC_EVOSEL_0 0 +#endif +// + +// Channel 1 settings +// dmac_channel_1_settings +#ifndef CONF_DMAC_CHANNEL_1_SETTINGS +#define CONF_DMAC_CHANNEL_1_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 1 is enabled or not +// dmac_enable_1 +#ifndef CONF_DMAC_ENABLE_1 +#define CONF_DMAC_ENABLE_1 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 1 is running in standby mode or not +// dmac_runstdby_1 +#ifndef CONF_DMAC_RUNSTDBY_1 +#define CONF_DMAC_RUNSTDBY_1 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_1 +#ifndef CONF_DMAC_TRIGACT_1 +#define CONF_DMAC_TRIGACT_1 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_1 +#ifndef CONF_DMAC_TRIGSRC_1 +#define CONF_DMAC_TRIGSRC_1 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_1 +#ifndef CONF_DMAC_LVL_1 +#define CONF_DMAC_LVL_1 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_1 +#ifndef CONF_DMAC_EVOE_1 +#define CONF_DMAC_EVOE_1 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_1 +#ifndef CONF_DMAC_EVIE_1 +#define CONF_DMAC_EVIE_1 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_1 +#ifndef CONF_DMAC_EVACT_1 +#define CONF_DMAC_EVACT_1 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_1 +#ifndef CONF_DMAC_STEPSIZE_1 +#define CONF_DMAC_STEPSIZE_1 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_1 +#ifndef CONF_DMAC_STEPSEL_1 +#define CONF_DMAC_STEPSEL_1 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_1 +#ifndef CONF_DMAC_SRCINC_1 +#define CONF_DMAC_SRCINC_1 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_1 +#ifndef CONF_DMAC_DSTINC_1 +#define CONF_DMAC_DSTINC_1 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_1 +#ifndef CONF_DMAC_BEATSIZE_1 +#define CONF_DMAC_BEATSIZE_1 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_1 +#ifndef CONF_DMAC_BLOCKACT_1 +#define CONF_DMAC_BLOCKACT_1 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_1 +#ifndef CONF_DMAC_EVOSEL_1 +#define CONF_DMAC_EVOSEL_1 0 +#endif +// + +// Channel 2 settings +// dmac_channel_2_settings +#ifndef CONF_DMAC_CHANNEL_2_SETTINGS +#define CONF_DMAC_CHANNEL_2_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 2 is enabled or not +// dmac_enable_2 +#ifndef CONF_DMAC_ENABLE_2 +#define CONF_DMAC_ENABLE_2 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 2 is running in standby mode or not +// dmac_runstdby_2 +#ifndef CONF_DMAC_RUNSTDBY_2 +#define CONF_DMAC_RUNSTDBY_2 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_2 +#ifndef CONF_DMAC_TRIGACT_2 +#define CONF_DMAC_TRIGACT_2 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_2 +#ifndef CONF_DMAC_TRIGSRC_2 +#define CONF_DMAC_TRIGSRC_2 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_2 +#ifndef CONF_DMAC_LVL_2 +#define CONF_DMAC_LVL_2 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_2 +#ifndef CONF_DMAC_EVOE_2 +#define CONF_DMAC_EVOE_2 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_2 +#ifndef CONF_DMAC_EVIE_2 +#define CONF_DMAC_EVIE_2 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_2 +#ifndef CONF_DMAC_EVACT_2 +#define CONF_DMAC_EVACT_2 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_2 +#ifndef CONF_DMAC_STEPSIZE_2 +#define CONF_DMAC_STEPSIZE_2 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_2 +#ifndef CONF_DMAC_STEPSEL_2 +#define CONF_DMAC_STEPSEL_2 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_2 +#ifndef CONF_DMAC_SRCINC_2 +#define CONF_DMAC_SRCINC_2 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_2 +#ifndef CONF_DMAC_DSTINC_2 +#define CONF_DMAC_DSTINC_2 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_2 +#ifndef CONF_DMAC_BEATSIZE_2 +#define CONF_DMAC_BEATSIZE_2 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_2 +#ifndef CONF_DMAC_BLOCKACT_2 +#define CONF_DMAC_BLOCKACT_2 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_2 +#ifndef CONF_DMAC_EVOSEL_2 +#define CONF_DMAC_EVOSEL_2 0 +#endif +// + +// Channel 3 settings +// dmac_channel_3_settings +#ifndef CONF_DMAC_CHANNEL_3_SETTINGS +#define CONF_DMAC_CHANNEL_3_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 3 is enabled or not +// dmac_enable_3 +#ifndef CONF_DMAC_ENABLE_3 +#define CONF_DMAC_ENABLE_3 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 3 is running in standby mode or not +// dmac_runstdby_3 +#ifndef CONF_DMAC_RUNSTDBY_3 +#define CONF_DMAC_RUNSTDBY_3 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_3 +#ifndef CONF_DMAC_TRIGACT_3 +#define CONF_DMAC_TRIGACT_3 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_3 +#ifndef CONF_DMAC_TRIGSRC_3 +#define CONF_DMAC_TRIGSRC_3 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_3 +#ifndef CONF_DMAC_LVL_3 +#define CONF_DMAC_LVL_3 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_3 +#ifndef CONF_DMAC_EVOE_3 +#define CONF_DMAC_EVOE_3 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_3 +#ifndef CONF_DMAC_EVIE_3 +#define CONF_DMAC_EVIE_3 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_3 +#ifndef CONF_DMAC_EVACT_3 +#define CONF_DMAC_EVACT_3 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_3 +#ifndef CONF_DMAC_STEPSIZE_3 +#define CONF_DMAC_STEPSIZE_3 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_3 +#ifndef CONF_DMAC_STEPSEL_3 +#define CONF_DMAC_STEPSEL_3 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_3 +#ifndef CONF_DMAC_SRCINC_3 +#define CONF_DMAC_SRCINC_3 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_3 +#ifndef CONF_DMAC_DSTINC_3 +#define CONF_DMAC_DSTINC_3 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_3 +#ifndef CONF_DMAC_BEATSIZE_3 +#define CONF_DMAC_BEATSIZE_3 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_3 +#ifndef CONF_DMAC_BLOCKACT_3 +#define CONF_DMAC_BLOCKACT_3 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_3 +#ifndef CONF_DMAC_EVOSEL_3 +#define CONF_DMAC_EVOSEL_3 0 +#endif +// + +// Channel 4 settings +// dmac_channel_4_settings +#ifndef CONF_DMAC_CHANNEL_4_SETTINGS +#define CONF_DMAC_CHANNEL_4_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 4 is enabled or not +// dmac_enable_4 +#ifndef CONF_DMAC_ENABLE_4 +#define CONF_DMAC_ENABLE_4 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 4 is running in standby mode or not +// dmac_runstdby_4 +#ifndef CONF_DMAC_RUNSTDBY_4 +#define CONF_DMAC_RUNSTDBY_4 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_4 +#ifndef CONF_DMAC_TRIGACT_4 +#define CONF_DMAC_TRIGACT_4 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_4 +#ifndef CONF_DMAC_TRIGSRC_4 +#define CONF_DMAC_TRIGSRC_4 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_4 +#ifndef CONF_DMAC_LVL_4 +#define CONF_DMAC_LVL_4 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_4 +#ifndef CONF_DMAC_EVOE_4 +#define CONF_DMAC_EVOE_4 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_4 +#ifndef CONF_DMAC_EVIE_4 +#define CONF_DMAC_EVIE_4 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_4 +#ifndef CONF_DMAC_EVACT_4 +#define CONF_DMAC_EVACT_4 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_4 +#ifndef CONF_DMAC_STEPSIZE_4 +#define CONF_DMAC_STEPSIZE_4 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_4 +#ifndef CONF_DMAC_STEPSEL_4 +#define CONF_DMAC_STEPSEL_4 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_4 +#ifndef CONF_DMAC_SRCINC_4 +#define CONF_DMAC_SRCINC_4 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_4 +#ifndef CONF_DMAC_DSTINC_4 +#define CONF_DMAC_DSTINC_4 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_4 +#ifndef CONF_DMAC_BEATSIZE_4 +#define CONF_DMAC_BEATSIZE_4 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_4 +#ifndef CONF_DMAC_BLOCKACT_4 +#define CONF_DMAC_BLOCKACT_4 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_4 +#ifndef CONF_DMAC_EVOSEL_4 +#define CONF_DMAC_EVOSEL_4 0 +#endif +// + +// Channel 5 settings +// dmac_channel_5_settings +#ifndef CONF_DMAC_CHANNEL_5_SETTINGS +#define CONF_DMAC_CHANNEL_5_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 5 is enabled or not +// dmac_enable_5 +#ifndef CONF_DMAC_ENABLE_5 +#define CONF_DMAC_ENABLE_5 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 5 is running in standby mode or not +// dmac_runstdby_5 +#ifndef CONF_DMAC_RUNSTDBY_5 +#define CONF_DMAC_RUNSTDBY_5 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_5 +#ifndef CONF_DMAC_TRIGACT_5 +#define CONF_DMAC_TRIGACT_5 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_5 +#ifndef CONF_DMAC_TRIGSRC_5 +#define CONF_DMAC_TRIGSRC_5 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_5 +#ifndef CONF_DMAC_LVL_5 +#define CONF_DMAC_LVL_5 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_5 +#ifndef CONF_DMAC_EVOE_5 +#define CONF_DMAC_EVOE_5 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_5 +#ifndef CONF_DMAC_EVIE_5 +#define CONF_DMAC_EVIE_5 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_5 +#ifndef CONF_DMAC_EVACT_5 +#define CONF_DMAC_EVACT_5 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_5 +#ifndef CONF_DMAC_STEPSIZE_5 +#define CONF_DMAC_STEPSIZE_5 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_5 +#ifndef CONF_DMAC_STEPSEL_5 +#define CONF_DMAC_STEPSEL_5 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_5 +#ifndef CONF_DMAC_SRCINC_5 +#define CONF_DMAC_SRCINC_5 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_5 +#ifndef CONF_DMAC_DSTINC_5 +#define CONF_DMAC_DSTINC_5 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_5 +#ifndef CONF_DMAC_BEATSIZE_5 +#define CONF_DMAC_BEATSIZE_5 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_5 +#ifndef CONF_DMAC_BLOCKACT_5 +#define CONF_DMAC_BLOCKACT_5 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_5 +#ifndef CONF_DMAC_EVOSEL_5 +#define CONF_DMAC_EVOSEL_5 0 +#endif +// + +// Channel 6 settings +// dmac_channel_6_settings +#ifndef CONF_DMAC_CHANNEL_6_SETTINGS +#define CONF_DMAC_CHANNEL_6_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 6 is enabled or not +// dmac_enable_6 +#ifndef CONF_DMAC_ENABLE_6 +#define CONF_DMAC_ENABLE_6 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 6 is running in standby mode or not +// dmac_runstdby_6 +#ifndef CONF_DMAC_RUNSTDBY_6 +#define CONF_DMAC_RUNSTDBY_6 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_6 +#ifndef CONF_DMAC_TRIGACT_6 +#define CONF_DMAC_TRIGACT_6 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_6 +#ifndef CONF_DMAC_TRIGSRC_6 +#define CONF_DMAC_TRIGSRC_6 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_6 +#ifndef CONF_DMAC_LVL_6 +#define CONF_DMAC_LVL_6 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_6 +#ifndef CONF_DMAC_EVOE_6 +#define CONF_DMAC_EVOE_6 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_6 +#ifndef CONF_DMAC_EVIE_6 +#define CONF_DMAC_EVIE_6 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_6 +#ifndef CONF_DMAC_EVACT_6 +#define CONF_DMAC_EVACT_6 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_6 +#ifndef CONF_DMAC_STEPSIZE_6 +#define CONF_DMAC_STEPSIZE_6 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_6 +#ifndef CONF_DMAC_STEPSEL_6 +#define CONF_DMAC_STEPSEL_6 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_6 +#ifndef CONF_DMAC_SRCINC_6 +#define CONF_DMAC_SRCINC_6 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_6 +#ifndef CONF_DMAC_DSTINC_6 +#define CONF_DMAC_DSTINC_6 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_6 +#ifndef CONF_DMAC_BEATSIZE_6 +#define CONF_DMAC_BEATSIZE_6 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_6 +#ifndef CONF_DMAC_BLOCKACT_6 +#define CONF_DMAC_BLOCKACT_6 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_6 +#ifndef CONF_DMAC_EVOSEL_6 +#define CONF_DMAC_EVOSEL_6 0 +#endif +// + +// Channel 7 settings +// dmac_channel_7_settings +#ifndef CONF_DMAC_CHANNEL_7_SETTINGS +#define CONF_DMAC_CHANNEL_7_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 7 is enabled or not +// dmac_enable_7 +#ifndef CONF_DMAC_ENABLE_7 +#define CONF_DMAC_ENABLE_7 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 7 is running in standby mode or not +// dmac_runstdby_7 +#ifndef CONF_DMAC_RUNSTDBY_7 +#define CONF_DMAC_RUNSTDBY_7 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_7 +#ifndef CONF_DMAC_TRIGACT_7 +#define CONF_DMAC_TRIGACT_7 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_7 +#ifndef CONF_DMAC_TRIGSRC_7 +#define CONF_DMAC_TRIGSRC_7 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_7 +#ifndef CONF_DMAC_LVL_7 +#define CONF_DMAC_LVL_7 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_7 +#ifndef CONF_DMAC_EVOE_7 +#define CONF_DMAC_EVOE_7 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_7 +#ifndef CONF_DMAC_EVIE_7 +#define CONF_DMAC_EVIE_7 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_7 +#ifndef CONF_DMAC_EVACT_7 +#define CONF_DMAC_EVACT_7 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_7 +#ifndef CONF_DMAC_STEPSIZE_7 +#define CONF_DMAC_STEPSIZE_7 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_7 +#ifndef CONF_DMAC_STEPSEL_7 +#define CONF_DMAC_STEPSEL_7 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_7 +#ifndef CONF_DMAC_SRCINC_7 +#define CONF_DMAC_SRCINC_7 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_7 +#ifndef CONF_DMAC_DSTINC_7 +#define CONF_DMAC_DSTINC_7 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_7 +#ifndef CONF_DMAC_BEATSIZE_7 +#define CONF_DMAC_BEATSIZE_7 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_7 +#ifndef CONF_DMAC_BLOCKACT_7 +#define CONF_DMAC_BLOCKACT_7 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_7 +#ifndef CONF_DMAC_EVOSEL_7 +#define CONF_DMAC_EVOSEL_7 0 +#endif +// + +// Channel 8 settings +// dmac_channel_8_settings +#ifndef CONF_DMAC_CHANNEL_8_SETTINGS +#define CONF_DMAC_CHANNEL_8_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 8 is enabled or not +// dmac_enable_8 +#ifndef CONF_DMAC_ENABLE_8 +#define CONF_DMAC_ENABLE_8 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 8 is running in standby mode or not +// dmac_runstdby_8 +#ifndef CONF_DMAC_RUNSTDBY_8 +#define CONF_DMAC_RUNSTDBY_8 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_8 +#ifndef CONF_DMAC_TRIGACT_8 +#define CONF_DMAC_TRIGACT_8 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_8 +#ifndef CONF_DMAC_TRIGSRC_8 +#define CONF_DMAC_TRIGSRC_8 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_8 +#ifndef CONF_DMAC_LVL_8 +#define CONF_DMAC_LVL_8 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_8 +#ifndef CONF_DMAC_EVOE_8 +#define CONF_DMAC_EVOE_8 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_8 +#ifndef CONF_DMAC_EVIE_8 +#define CONF_DMAC_EVIE_8 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_8 +#ifndef CONF_DMAC_EVACT_8 +#define CONF_DMAC_EVACT_8 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_8 +#ifndef CONF_DMAC_STEPSIZE_8 +#define CONF_DMAC_STEPSIZE_8 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_8 +#ifndef CONF_DMAC_STEPSEL_8 +#define CONF_DMAC_STEPSEL_8 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_8 +#ifndef CONF_DMAC_SRCINC_8 +#define CONF_DMAC_SRCINC_8 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_8 +#ifndef CONF_DMAC_DSTINC_8 +#define CONF_DMAC_DSTINC_8 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_8 +#ifndef CONF_DMAC_BEATSIZE_8 +#define CONF_DMAC_BEATSIZE_8 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_8 +#ifndef CONF_DMAC_BLOCKACT_8 +#define CONF_DMAC_BLOCKACT_8 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_8 +#ifndef CONF_DMAC_EVOSEL_8 +#define CONF_DMAC_EVOSEL_8 0 +#endif +// + +// Channel 9 settings +// dmac_channel_9_settings +#ifndef CONF_DMAC_CHANNEL_9_SETTINGS +#define CONF_DMAC_CHANNEL_9_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 9 is enabled or not +// dmac_enable_9 +#ifndef CONF_DMAC_ENABLE_9 +#define CONF_DMAC_ENABLE_9 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 9 is running in standby mode or not +// dmac_runstdby_9 +#ifndef CONF_DMAC_RUNSTDBY_9 +#define CONF_DMAC_RUNSTDBY_9 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_9 +#ifndef CONF_DMAC_TRIGACT_9 +#define CONF_DMAC_TRIGACT_9 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_9 +#ifndef CONF_DMAC_TRIGSRC_9 +#define CONF_DMAC_TRIGSRC_9 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_9 +#ifndef CONF_DMAC_LVL_9 +#define CONF_DMAC_LVL_9 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_9 +#ifndef CONF_DMAC_EVOE_9 +#define CONF_DMAC_EVOE_9 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_9 +#ifndef CONF_DMAC_EVIE_9 +#define CONF_DMAC_EVIE_9 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_9 +#ifndef CONF_DMAC_EVACT_9 +#define CONF_DMAC_EVACT_9 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_9 +#ifndef CONF_DMAC_STEPSIZE_9 +#define CONF_DMAC_STEPSIZE_9 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_9 +#ifndef CONF_DMAC_STEPSEL_9 +#define CONF_DMAC_STEPSEL_9 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_9 +#ifndef CONF_DMAC_SRCINC_9 +#define CONF_DMAC_SRCINC_9 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_9 +#ifndef CONF_DMAC_DSTINC_9 +#define CONF_DMAC_DSTINC_9 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_9 +#ifndef CONF_DMAC_BEATSIZE_9 +#define CONF_DMAC_BEATSIZE_9 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_9 +#ifndef CONF_DMAC_BLOCKACT_9 +#define CONF_DMAC_BLOCKACT_9 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_9 +#ifndef CONF_DMAC_EVOSEL_9 +#define CONF_DMAC_EVOSEL_9 0 +#endif +// + +// Channel 10 settings +// dmac_channel_10_settings +#ifndef CONF_DMAC_CHANNEL_10_SETTINGS +#define CONF_DMAC_CHANNEL_10_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 10 is enabled or not +// dmac_enable_10 +#ifndef CONF_DMAC_ENABLE_10 +#define CONF_DMAC_ENABLE_10 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 10 is running in standby mode or not +// dmac_runstdby_10 +#ifndef CONF_DMAC_RUNSTDBY_10 +#define CONF_DMAC_RUNSTDBY_10 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_10 +#ifndef CONF_DMAC_TRIGACT_10 +#define CONF_DMAC_TRIGACT_10 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_10 +#ifndef CONF_DMAC_TRIGSRC_10 +#define CONF_DMAC_TRIGSRC_10 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_10 +#ifndef CONF_DMAC_LVL_10 +#define CONF_DMAC_LVL_10 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_10 +#ifndef CONF_DMAC_EVOE_10 +#define CONF_DMAC_EVOE_10 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_10 +#ifndef CONF_DMAC_EVIE_10 +#define CONF_DMAC_EVIE_10 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_10 +#ifndef CONF_DMAC_EVACT_10 +#define CONF_DMAC_EVACT_10 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_10 +#ifndef CONF_DMAC_STEPSIZE_10 +#define CONF_DMAC_STEPSIZE_10 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_10 +#ifndef CONF_DMAC_STEPSEL_10 +#define CONF_DMAC_STEPSEL_10 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_10 +#ifndef CONF_DMAC_SRCINC_10 +#define CONF_DMAC_SRCINC_10 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_10 +#ifndef CONF_DMAC_DSTINC_10 +#define CONF_DMAC_DSTINC_10 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_10 +#ifndef CONF_DMAC_BEATSIZE_10 +#define CONF_DMAC_BEATSIZE_10 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_10 +#ifndef CONF_DMAC_BLOCKACT_10 +#define CONF_DMAC_BLOCKACT_10 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_10 +#ifndef CONF_DMAC_EVOSEL_10 +#define CONF_DMAC_EVOSEL_10 0 +#endif +// + +// Channel 11 settings +// dmac_channel_11_settings +#ifndef CONF_DMAC_CHANNEL_11_SETTINGS +#define CONF_DMAC_CHANNEL_11_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 11 is enabled or not +// dmac_enable_11 +#ifndef CONF_DMAC_ENABLE_11 +#define CONF_DMAC_ENABLE_11 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 11 is running in standby mode or not +// dmac_runstdby_11 +#ifndef CONF_DMAC_RUNSTDBY_11 +#define CONF_DMAC_RUNSTDBY_11 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_11 +#ifndef CONF_DMAC_TRIGACT_11 +#define CONF_DMAC_TRIGACT_11 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_11 +#ifndef CONF_DMAC_TRIGSRC_11 +#define CONF_DMAC_TRIGSRC_11 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_11 +#ifndef CONF_DMAC_LVL_11 +#define CONF_DMAC_LVL_11 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_11 +#ifndef CONF_DMAC_EVOE_11 +#define CONF_DMAC_EVOE_11 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_11 +#ifndef CONF_DMAC_EVIE_11 +#define CONF_DMAC_EVIE_11 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_11 +#ifndef CONF_DMAC_EVACT_11 +#define CONF_DMAC_EVACT_11 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_11 +#ifndef CONF_DMAC_STEPSIZE_11 +#define CONF_DMAC_STEPSIZE_11 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_11 +#ifndef CONF_DMAC_STEPSEL_11 +#define CONF_DMAC_STEPSEL_11 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_11 +#ifndef CONF_DMAC_SRCINC_11 +#define CONF_DMAC_SRCINC_11 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_11 +#ifndef CONF_DMAC_DSTINC_11 +#define CONF_DMAC_DSTINC_11 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_11 +#ifndef CONF_DMAC_BEATSIZE_11 +#define CONF_DMAC_BEATSIZE_11 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_11 +#ifndef CONF_DMAC_BLOCKACT_11 +#define CONF_DMAC_BLOCKACT_11 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_11 +#ifndef CONF_DMAC_EVOSEL_11 +#define CONF_DMAC_EVOSEL_11 0 +#endif +// + +// Channel 12 settings +// dmac_channel_12_settings +#ifndef CONF_DMAC_CHANNEL_12_SETTINGS +#define CONF_DMAC_CHANNEL_12_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 12 is enabled or not +// dmac_enable_12 +#ifndef CONF_DMAC_ENABLE_12 +#define CONF_DMAC_ENABLE_12 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 12 is running in standby mode or not +// dmac_runstdby_12 +#ifndef CONF_DMAC_RUNSTDBY_12 +#define CONF_DMAC_RUNSTDBY_12 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_12 +#ifndef CONF_DMAC_TRIGACT_12 +#define CONF_DMAC_TRIGACT_12 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_12 +#ifndef CONF_DMAC_TRIGSRC_12 +#define CONF_DMAC_TRIGSRC_12 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_12 +#ifndef CONF_DMAC_LVL_12 +#define CONF_DMAC_LVL_12 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_12 +#ifndef CONF_DMAC_EVOE_12 +#define CONF_DMAC_EVOE_12 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_12 +#ifndef CONF_DMAC_EVIE_12 +#define CONF_DMAC_EVIE_12 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_12 +#ifndef CONF_DMAC_EVACT_12 +#define CONF_DMAC_EVACT_12 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_12 +#ifndef CONF_DMAC_STEPSIZE_12 +#define CONF_DMAC_STEPSIZE_12 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_12 +#ifndef CONF_DMAC_STEPSEL_12 +#define CONF_DMAC_STEPSEL_12 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_12 +#ifndef CONF_DMAC_SRCINC_12 +#define CONF_DMAC_SRCINC_12 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_12 +#ifndef CONF_DMAC_DSTINC_12 +#define CONF_DMAC_DSTINC_12 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_12 +#ifndef CONF_DMAC_BEATSIZE_12 +#define CONF_DMAC_BEATSIZE_12 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_12 +#ifndef CONF_DMAC_BLOCKACT_12 +#define CONF_DMAC_BLOCKACT_12 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_12 +#ifndef CONF_DMAC_EVOSEL_12 +#define CONF_DMAC_EVOSEL_12 0 +#endif +// + +// Channel 13 settings +// dmac_channel_13_settings +#ifndef CONF_DMAC_CHANNEL_13_SETTINGS +#define CONF_DMAC_CHANNEL_13_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 13 is enabled or not +// dmac_enable_13 +#ifndef CONF_DMAC_ENABLE_13 +#define CONF_DMAC_ENABLE_13 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 13 is running in standby mode or not +// dmac_runstdby_13 +#ifndef CONF_DMAC_RUNSTDBY_13 +#define CONF_DMAC_RUNSTDBY_13 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_13 +#ifndef CONF_DMAC_TRIGACT_13 +#define CONF_DMAC_TRIGACT_13 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_13 +#ifndef CONF_DMAC_TRIGSRC_13 +#define CONF_DMAC_TRIGSRC_13 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_13 +#ifndef CONF_DMAC_LVL_13 +#define CONF_DMAC_LVL_13 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_13 +#ifndef CONF_DMAC_EVOE_13 +#define CONF_DMAC_EVOE_13 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_13 +#ifndef CONF_DMAC_EVIE_13 +#define CONF_DMAC_EVIE_13 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_13 +#ifndef CONF_DMAC_EVACT_13 +#define CONF_DMAC_EVACT_13 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_13 +#ifndef CONF_DMAC_STEPSIZE_13 +#define CONF_DMAC_STEPSIZE_13 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_13 +#ifndef CONF_DMAC_STEPSEL_13 +#define CONF_DMAC_STEPSEL_13 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_13 +#ifndef CONF_DMAC_SRCINC_13 +#define CONF_DMAC_SRCINC_13 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_13 +#ifndef CONF_DMAC_DSTINC_13 +#define CONF_DMAC_DSTINC_13 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_13 +#ifndef CONF_DMAC_BEATSIZE_13 +#define CONF_DMAC_BEATSIZE_13 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_13 +#ifndef CONF_DMAC_BLOCKACT_13 +#define CONF_DMAC_BLOCKACT_13 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_13 +#ifndef CONF_DMAC_EVOSEL_13 +#define CONF_DMAC_EVOSEL_13 0 +#endif +// + +// Channel 14 settings +// dmac_channel_14_settings +#ifndef CONF_DMAC_CHANNEL_14_SETTINGS +#define CONF_DMAC_CHANNEL_14_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 14 is enabled or not +// dmac_enable_14 +#ifndef CONF_DMAC_ENABLE_14 +#define CONF_DMAC_ENABLE_14 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 14 is running in standby mode or not +// dmac_runstdby_14 +#ifndef CONF_DMAC_RUNSTDBY_14 +#define CONF_DMAC_RUNSTDBY_14 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_14 +#ifndef CONF_DMAC_TRIGACT_14 +#define CONF_DMAC_TRIGACT_14 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_14 +#ifndef CONF_DMAC_TRIGSRC_14 +#define CONF_DMAC_TRIGSRC_14 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_14 +#ifndef CONF_DMAC_LVL_14 +#define CONF_DMAC_LVL_14 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_14 +#ifndef CONF_DMAC_EVOE_14 +#define CONF_DMAC_EVOE_14 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_14 +#ifndef CONF_DMAC_EVIE_14 +#define CONF_DMAC_EVIE_14 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_14 +#ifndef CONF_DMAC_EVACT_14 +#define CONF_DMAC_EVACT_14 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_14 +#ifndef CONF_DMAC_STEPSIZE_14 +#define CONF_DMAC_STEPSIZE_14 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_14 +#ifndef CONF_DMAC_STEPSEL_14 +#define CONF_DMAC_STEPSEL_14 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_14 +#ifndef CONF_DMAC_SRCINC_14 +#define CONF_DMAC_SRCINC_14 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_14 +#ifndef CONF_DMAC_DSTINC_14 +#define CONF_DMAC_DSTINC_14 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_14 +#ifndef CONF_DMAC_BEATSIZE_14 +#define CONF_DMAC_BEATSIZE_14 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_14 +#ifndef CONF_DMAC_BLOCKACT_14 +#define CONF_DMAC_BLOCKACT_14 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_14 +#ifndef CONF_DMAC_EVOSEL_14 +#define CONF_DMAC_EVOSEL_14 0 +#endif +// + +// Channel 15 settings +// dmac_channel_15_settings +#ifndef CONF_DMAC_CHANNEL_15_SETTINGS +#define CONF_DMAC_CHANNEL_15_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 15 is enabled or not +// dmac_enable_15 +#ifndef CONF_DMAC_ENABLE_15 +#define CONF_DMAC_ENABLE_15 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 15 is running in standby mode or not +// dmac_runstdby_15 +#ifndef CONF_DMAC_RUNSTDBY_15 +#define CONF_DMAC_RUNSTDBY_15 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_15 +#ifndef CONF_DMAC_TRIGACT_15 +#define CONF_DMAC_TRIGACT_15 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_15 +#ifndef CONF_DMAC_TRIGSRC_15 +#define CONF_DMAC_TRIGSRC_15 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_15 +#ifndef CONF_DMAC_LVL_15 +#define CONF_DMAC_LVL_15 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_15 +#ifndef CONF_DMAC_EVOE_15 +#define CONF_DMAC_EVOE_15 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_15 +#ifndef CONF_DMAC_EVIE_15 +#define CONF_DMAC_EVIE_15 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_15 +#ifndef CONF_DMAC_EVACT_15 +#define CONF_DMAC_EVACT_15 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_15 +#ifndef CONF_DMAC_STEPSIZE_15 +#define CONF_DMAC_STEPSIZE_15 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_15 +#ifndef CONF_DMAC_STEPSEL_15 +#define CONF_DMAC_STEPSEL_15 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_15 +#ifndef CONF_DMAC_SRCINC_15 +#define CONF_DMAC_SRCINC_15 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_15 +#ifndef CONF_DMAC_DSTINC_15 +#define CONF_DMAC_DSTINC_15 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_15 +#ifndef CONF_DMAC_BEATSIZE_15 +#define CONF_DMAC_BEATSIZE_15 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_15 +#ifndef CONF_DMAC_BLOCKACT_15 +#define CONF_DMAC_BLOCKACT_15 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_15 +#ifndef CONF_DMAC_EVOSEL_15 +#define CONF_DMAC_EVOSEL_15 0 +#endif +// + +// + +// <<< end of configuration section >>> + +#endif // HPL_DMAC_CONFIG_H diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/Config/hpl_gclk_config.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/Config/hpl_gclk_config.h new file mode 100644 index 00000000..65b36a91 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/Config/hpl_gclk_config.h @@ -0,0 +1,616 @@ +/* Auto-generated config file hpl_gclk_config.h */ +#ifndef HPL_GCLK_CONFIG_H +#define HPL_GCLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Generic clock generator 0 configuration +// Indicates whether generic clock 0 configuration is enabled or not +// enable_gclk_gen_0 +#ifndef CONF_GCLK_GENERATOR_0_CONFIG +#define CONF_GCLK_GENERATOR_0_CONFIG 1 +#endif + +// Generic Clock Generator Control +// Generic clock generator 0 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 16MHz Internal Oscillator (OSC16M) +// Digital Frequency Locked Loop (DFLL48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 0 +// gclk_gen_0_oscillator +#ifndef CONF_GCLK_GEN_0_SOURCE +#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_OSC16M +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_0_runstdby +#ifndef CONF_GCLK_GEN_0_RUNSTDBY +#define CONF_GCLK_GEN_0_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_0_div_sel +#ifndef CONF_GCLK_GEN_0_DIVSEL +#define CONF_GCLK_GEN_0_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_0_oe +#ifndef CONF_GCLK_GEN_0_OE +#define CONF_GCLK_GEN_0_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_0_oov +#ifndef CONF_GCLK_GEN_0_OOV +#define CONF_GCLK_GEN_0_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_0_idc +#ifndef CONF_GCLK_GEN_0_IDC +#define CONF_GCLK_GEN_0_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_0_enable +#ifndef CONF_GCLK_GEN_0_GENEN +#define CONF_GCLK_GEN_0_GENEN 1 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 0 division <0x0000-0xFFFF> +// gclk_gen_0_div +#ifndef CONF_GCLK_GEN_0_DIV +#define CONF_GCLK_GEN_0_DIV 1 +#endif +// +// + +// Generic clock generator 1 configuration +// Indicates whether generic clock 1 configuration is enabled or not +// enable_gclk_gen_1 +#ifndef CONF_GCLK_GENERATOR_1_CONFIG +#define CONF_GCLK_GENERATOR_1_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 1 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 16MHz Internal Oscillator (OSC16M) +// Digital Frequency Locked Loop (DFLL48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 1 +// gclk_gen_1_oscillator +#ifndef CONF_GCLK_GEN_1_SOURCE +#define CONF_GCLK_GEN_1_SOURCE GCLK_GENCTRL_SRC_OSC16M +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_1_runstdby +#ifndef CONF_GCLK_GEN_1_RUNSTDBY +#define CONF_GCLK_GEN_1_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_1_div_sel +#ifndef CONF_GCLK_GEN_1_DIVSEL +#define CONF_GCLK_GEN_1_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_1_oe +#ifndef CONF_GCLK_GEN_1_OE +#define CONF_GCLK_GEN_1_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_1_oov +#ifndef CONF_GCLK_GEN_1_OOV +#define CONF_GCLK_GEN_1_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_1_idc +#ifndef CONF_GCLK_GEN_1_IDC +#define CONF_GCLK_GEN_1_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_1_enable +#ifndef CONF_GCLK_GEN_1_GENEN +#define CONF_GCLK_GEN_1_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 1 division <0x0000-0xFFFF> +// gclk_gen_1_div +#ifndef CONF_GCLK_GEN_1_DIV +#define CONF_GCLK_GEN_1_DIV 1 +#endif +// +// + +// Generic clock generator 2 configuration +// Indicates whether generic clock 2 configuration is enabled or not +// enable_gclk_gen_2 +#ifndef CONF_GCLK_GENERATOR_2_CONFIG +#define CONF_GCLK_GENERATOR_2_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 2 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 16MHz Internal Oscillator (OSC16M) +// Digital Frequency Locked Loop (DFLL48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 2 +// gclk_gen_2_oscillator +#ifndef CONF_GCLK_GEN_2_SOURCE +#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_OSC32K +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_2_runstdby +#ifndef CONF_GCLK_GEN_2_RUNSTDBY +#define CONF_GCLK_GEN_2_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_2_div_sel +#ifndef CONF_GCLK_GEN_2_DIVSEL +#define CONF_GCLK_GEN_2_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_2_oe +#ifndef CONF_GCLK_GEN_2_OE +#define CONF_GCLK_GEN_2_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_2_oov +#ifndef CONF_GCLK_GEN_2_OOV +#define CONF_GCLK_GEN_2_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_2_idc +#ifndef CONF_GCLK_GEN_2_IDC +#define CONF_GCLK_GEN_2_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_2_enable +#ifndef CONF_GCLK_GEN_2_GENEN +#define CONF_GCLK_GEN_2_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 2 division <0x0000-0xFFFF> +// gclk_gen_2_div +#ifndef CONF_GCLK_GEN_2_DIV +#define CONF_GCLK_GEN_2_DIV 1 +#endif +// +// + +// Generic clock generator 3 configuration +// Indicates whether generic clock 3 configuration is enabled or not +// enable_gclk_gen_3 +#ifndef CONF_GCLK_GENERATOR_3_CONFIG +#define CONF_GCLK_GENERATOR_3_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 3 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 16MHz Internal Oscillator (OSC16M) +// Digital Frequency Locked Loop (DFLL48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 3 +// gclk_gen_3_oscillator +#ifndef CONF_GCLK_GEN_3_SOURCE +#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_OSCULP32K +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_3_runstdby +#ifndef CONF_GCLK_GEN_3_RUNSTDBY +#define CONF_GCLK_GEN_3_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_3_div_sel +#ifndef CONF_GCLK_GEN_3_DIVSEL +#define CONF_GCLK_GEN_3_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_3_oe +#ifndef CONF_GCLK_GEN_3_OE +#define CONF_GCLK_GEN_3_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_3_oov +#ifndef CONF_GCLK_GEN_3_OOV +#define CONF_GCLK_GEN_3_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_3_idc +#ifndef CONF_GCLK_GEN_3_IDC +#define CONF_GCLK_GEN_3_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_3_enable +#ifndef CONF_GCLK_GEN_3_GENEN +#define CONF_GCLK_GEN_3_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 3 division <0x0000-0xFFFF> +// gclk_gen_3_div +#ifndef CONF_GCLK_GEN_3_DIV +#define CONF_GCLK_GEN_3_DIV 1 +#endif +// +// + +// Generic clock generator 4 configuration +// Indicates whether generic clock 4 configuration is enabled or not +// enable_gclk_gen_4 +#ifndef CONF_GCLK_GENERATOR_4_CONFIG +#define CONF_GCLK_GENERATOR_4_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 4 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 16MHz Internal Oscillator (OSC16M) +// Digital Frequency Locked Loop (DFLL48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 4 +// gclk_gen_4_oscillator +#ifndef CONF_GCLK_GEN_4_SOURCE +#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_OSCULP32K +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_4_runstdby +#ifndef CONF_GCLK_GEN_4_RUNSTDBY +#define CONF_GCLK_GEN_4_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_4_div_sel +#ifndef CONF_GCLK_GEN_4_DIVSEL +#define CONF_GCLK_GEN_4_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_4_oe +#ifndef CONF_GCLK_GEN_4_OE +#define CONF_GCLK_GEN_4_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_4_oov +#ifndef CONF_GCLK_GEN_4_OOV +#define CONF_GCLK_GEN_4_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_4_idc +#ifndef CONF_GCLK_GEN_4_IDC +#define CONF_GCLK_GEN_4_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_4_enable +#ifndef CONF_GCLK_GEN_4_GENEN +#define CONF_GCLK_GEN_4_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 4 division <0x0000-0xFFFF> +// gclk_gen_4_div +#ifndef CONF_GCLK_GEN_4_DIV +#define CONF_GCLK_GEN_4_DIV 1 +#endif +// +// + +// Generic clock generator 5 configuration +// Indicates whether generic clock 5 configuration is enabled or not +// enable_gclk_gen_5 +#ifndef CONF_GCLK_GENERATOR_5_CONFIG +#define CONF_GCLK_GENERATOR_5_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 5 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 16MHz Internal Oscillator (OSC16M) +// Digital Frequency Locked Loop (DFLL48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 5 +// gclk_gen_5_oscillator +#ifndef CONF_GCLK_GEN_5_SOURCE +#define CONF_GCLK_GEN_5_SOURCE GCLK_GENCTRL_SRC_OSC32K +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_5_runstdby +#ifndef CONF_GCLK_GEN_5_RUNSTDBY +#define CONF_GCLK_GEN_5_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_5_div_sel +#ifndef CONF_GCLK_GEN_5_DIVSEL +#define CONF_GCLK_GEN_5_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_5_oe +#ifndef CONF_GCLK_GEN_5_OE +#define CONF_GCLK_GEN_5_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_5_oov +#ifndef CONF_GCLK_GEN_5_OOV +#define CONF_GCLK_GEN_5_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_5_idc +#ifndef CONF_GCLK_GEN_5_IDC +#define CONF_GCLK_GEN_5_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_5_enable +#ifndef CONF_GCLK_GEN_5_GENEN +#define CONF_GCLK_GEN_5_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 5 division <0x0000-0xFFFF> +// gclk_gen_5_div +#ifndef CONF_GCLK_GEN_5_DIV +#define CONF_GCLK_GEN_5_DIV 1 +#endif +// +// + +// Generic clock generator 6 configuration +// Indicates whether generic clock 6 configuration is enabled or not +// enable_gclk_gen_6 +#ifndef CONF_GCLK_GENERATOR_6_CONFIG +#define CONF_GCLK_GENERATOR_6_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 6 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 16MHz Internal Oscillator (OSC16M) +// Digital Frequency Locked Loop (DFLL48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 6 +// gclk_gen_6_oscillator +#ifndef CONF_GCLK_GEN_6_SOURCE +#define CONF_GCLK_GEN_6_SOURCE GCLK_GENCTRL_SRC_OSC32K +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_6_runstdby +#ifndef CONF_GCLK_GEN_6_RUNSTDBY +#define CONF_GCLK_GEN_6_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_6_div_sel +#ifndef CONF_GCLK_GEN_6_DIVSEL +#define CONF_GCLK_GEN_6_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_6_oe +#ifndef CONF_GCLK_GEN_6_OE +#define CONF_GCLK_GEN_6_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_6_oov +#ifndef CONF_GCLK_GEN_6_OOV +#define CONF_GCLK_GEN_6_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_6_idc +#ifndef CONF_GCLK_GEN_6_IDC +#define CONF_GCLK_GEN_6_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_6_enable +#ifndef CONF_GCLK_GEN_6_GENEN +#define CONF_GCLK_GEN_6_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 6 division <0x0000-0xFFFF> +// gclk_gen_6_div +#ifndef CONF_GCLK_GEN_6_DIV +#define CONF_GCLK_GEN_6_DIV 1 +#endif +// +// + +// Generic clock generator 7 configuration +// Indicates whether generic clock 7 configuration is enabled or not +// enable_gclk_gen_7 +#ifndef CONF_GCLK_GENERATOR_7_CONFIG +#define CONF_GCLK_GENERATOR_7_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 7 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 16MHz Internal Oscillator (OSC16M) +// Digital Frequency Locked Loop (DFLL48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 7 +// gclk_gen_7_oscillator +#ifndef CONF_GCLK_GEN_7_SOURCE +#define CONF_GCLK_GEN_7_SOURCE GCLK_GENCTRL_SRC_OSC32K +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_7_runstdby +#ifndef CONF_GCLK_GEN_7_RUNSTDBY +#define CONF_GCLK_GEN_7_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_7_div_sel +#ifndef CONF_GCLK_GEN_7_DIVSEL +#define CONF_GCLK_GEN_7_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_7_oe +#ifndef CONF_GCLK_GEN_7_OE +#define CONF_GCLK_GEN_7_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_7_oov +#ifndef CONF_GCLK_GEN_7_OOV +#define CONF_GCLK_GEN_7_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_7_idc +#ifndef CONF_GCLK_GEN_7_IDC +#define CONF_GCLK_GEN_7_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_7_enable +#ifndef CONF_GCLK_GEN_7_GENEN +#define CONF_GCLK_GEN_7_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 7 division <0x0000-0xFFFF> +// gclk_gen_7_div +#ifndef CONF_GCLK_GEN_7_DIV +#define CONF_GCLK_GEN_7_DIV 1 +#endif +// +// + +// <<< end of configuration section >>> + +#endif // HPL_GCLK_CONFIG_H diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/Config/hpl_mclk_config.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/Config/hpl_mclk_config.h new file mode 100644 index 00000000..94bf182d --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/Config/hpl_mclk_config.h @@ -0,0 +1,98 @@ +/* Auto-generated config file hpl_mclk_config.h */ +#ifndef HPL_MCLK_CONFIG_H +#define HPL_MCLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include + +// System Configuration +// Indicates whether configuration for system is enabled or not +// enable_cpu_clock +#ifndef CONF_SYSTEM_CONFIG +#define CONF_SYSTEM_CONFIG 1 +#endif + +// Basic settings +// CPU Clock source +// Generic clock generator 0 +// This defines the clock source for the CPU +// cpu_clock_source +#ifndef CONF_CPU_SRC +#define CONF_CPU_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// CPU Clock Division Factor +// 1 +// 2 +// 4 +// 8 +// 16 +// 32 +// 64 +// 128 +// Prescalar for CPU clock +// cpu_div +#ifndef CONF_MCLK_CPUDIV +#define CONF_MCLK_CPUDIV MCLK_CPUDIV_CPUDIV_DIV1_Val +#endif +// Low Power Clock Division +// Divide by 1 +// Divide by 2 +// Divide by 4 +// Divide by 8 +// Divide by 16 +// Divide by 32 +// Divide by 64 +// Divide by 128 +// mclk_arch_lpdiv +#ifndef CONF_MCLK_LPDIV +#define CONF_MCLK_LPDIV MCLK_LPDIV_LPDIV_DIV4_Val +#endif + +// Backup Clock Division +// Divide by 1 +// Divide by 2 +// Divide by 4 +// Divide by 8 +// Divide by 16 +// Divide by 32 +// Divide by 64 +// Divide by 128 +// mclk_arch_bupdiv +#ifndef CONF_MCLK_BUPDIV +#define CONF_MCLK_BUPDIV MCLK_BUPDIV_BUPDIV_DIV8_Val +#endif +// + +// NVM Settings +// NVM Wait States +// These bits select the number of wait states for a read operation. +// <0=> 0 +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +// <10=> 10 +// <11=> 11 +// <12=> 12 +// <13=> 13 +// <14=> 14 +// <15=> 15 +// nvm_wait_states +#ifndef CONF_NVM_WAIT_STATE +#define CONF_NVM_WAIT_STATE 0 +#endif + +// + +// + +// <<< end of configuration section >>> + +#endif // HPL_MCLK_CONFIG_H diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/Config/hpl_osc32kctrl_config.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/Config/hpl_osc32kctrl_config.h new file mode 100644 index 00000000..897774b9 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/Config/hpl_osc32kctrl_config.h @@ -0,0 +1,208 @@ +/* Auto-generated config file hpl_osc32kctrl_config.h */ +#ifndef HPL_OSC32KCTRL_CONFIG_H +#define HPL_OSC32KCTRL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// RTC Source configuration +// enable_rtc_source +#ifndef CONF_RTCCTRL_CONFIG +#define CONF_RTCCTRL_CONFIG 0 +#endif + +// RTC source control +// RTC Clock Source Selection +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// This defines the clock source for RTC +// rtc_source_oscillator +#ifndef CONF_RTCCTRL_SRC +#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_OSCULP32K +#endif + +// Use 1 kHz output +// rtc_1khz_selection +#ifndef CONF_RTCCTRL_1KHZ + +#define CONF_RTCCTRL_1KHZ 0 + +#endif + +#if CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSCULP32K +#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val) +#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSC32K +#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K_Val) +#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_XOSC32K +#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val) +#else +#error unexpected CONF_RTCCTRL_SRC +#endif + +// +// +// 32kHz External Crystal Oscillator Configuration +// Indicates whether configuration for External 32K Osc is enabled or not +// enable_xosc32k +#ifndef CONF_XOSC32K_CONFIG +#define CONF_XOSC32K_CONFIG 0 +#endif + +// 32kHz External Crystal Oscillator Control +// Oscillator enable +// Indicates whether 32kHz External Crystal Oscillator is enabled or not +// xosc32k_arch_enable +#ifndef CONF_XOSC32K_ENABLE +#define CONF_XOSC32K_ENABLE 0 +#endif + +// Start-Up Time +// <0x0=>62592us +// <0x1=>125092us +// <0x2=>500092us +// <0x3=>1000092us +// <0x4=>2000092us +// <0x5=>4000092us +// <0x6=>8000092us +// xosc32k_arch_startup +#ifndef CONF_XOSC32K_STARTUP +#define CONF_XOSC32K_STARTUP 0x0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// xosc32k_arch_ondemand +#ifndef CONF_XOSC32K_ONDEMAND +#define CONF_XOSC32K_ONDEMAND 1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// xosc32k_arch_runstdby +#ifndef CONF_XOSC32K_RUNSTDBY +#define CONF_XOSC32K_RUNSTDBY 0 +#endif + +// 1kHz Output Enable +// Indicates whether 1kHz Output is enabled or not +// xosc32k_arch_en1k +#ifndef CONF_XOSC32K_EN1K +#define CONF_XOSC32K_EN1K 0 +#endif + +// 32kHz Output Enable +// Indicates whether 32kHz Output is enabled or not +// xosc32k_arch_en32k +#ifndef CONF_XOSC32K_EN32K +#define CONF_XOSC32K_EN32K 0 +#endif + +// Crystal connected to XIN32/XOUT32 Enable +// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not +// xosc32k_arch_xtalen +#ifndef CONF_XOSC32K_XTALEN +#define CONF_XOSC32K_XTALEN 1 +#endif + +// +// +// 32kHz Internal Oscillator Configuration +// Indicates whether configuration for OSC32K is enabled or not +// enable_osc32k +#ifndef CONF_OSC32K_CONFIG +#define CONF_OSC32K_CONFIG 0 +#endif + +// 32kHz Internal Oscillator Control +// Enable +// Indicates whether 32kHz Internal Oscillator is enabled or not +// osc32k_arch_enable +#ifndef CONF_OSC32K_ENABLE +#define CONF_OSC32K_ENABLE 0 +#endif + +// Oscillator Calibration Control +// Indicates whether Oscillator Calibration is enabled or not +// osc32k_arch_calib_enable +#ifndef CONF_OSC32K_CALIB_ENABLE +#define CONF_OSC32K_CALIB_ENABLE 0 +#endif + +// Oscillator Calibration <0x0-0x7F> +// osc32k_arch_calib +#ifndef CONF_OSC32K_CALIB +#define CONF_OSC32K_CALIB 0x0 +#endif + +// Start-Up Time +// <0x0=>92us +// <0x1=>122us +// <0x2=>183us +// <0x3=>305us +// <0x4=>549us +// <0x5=>1038us +// <0x6=>2014us +// <0x7=>3967us +// osc32k_arch_startup +#ifndef CONF_OSC32K_STARTUP +#define CONF_OSC32K_STARTUP 0x0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// osc32k_arch_ondemand +#ifndef CONF_OSC32K_ONDEMAND +#define CONF_OSC32K_ONDEMAND 0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// osc32k_arch_runstdby +#ifndef CONF_OSC32K_RUNSTDBY +#define CONF_OSC32K_RUNSTDBY 0 +#endif + +// 1kHz Output Enable +// Indicates whether 1kHz Output is enabled or not +// osc32k_arch_en1k +#ifndef CONF_OSC32K_EN1K +#define CONF_OSC32K_EN1K 0 +#endif + +// 32kHz Output Enable +// Indicates whether 32kHz Output is enabled or not +// osc32k_arch_en32k +#ifndef CONF_OSC32K_EN32K +#define CONF_OSC32K_EN32K 0 +#endif +// +// + +// 32kHz Ultra Low Power Internal Oscillator Configuration +// Indicates whether configuration for OSCULP32K is enabled or not +// enable_osculp32k +#ifndef CONF_OSCULP32K_CONFIG +#define CONF_OSCULP32K_CONFIG 1 +#endif + +// 32kHz Ultra Low Power Internal Oscillator Control + +// Oscillator Calibration Control +// Indicates whether Oscillator Calibration is enabled or not +// osculp32k_calib_enable +#ifndef CONF_OSCULP32K_CALIB_ENABLE +#define CONF_OSCULP32K_CALIB_ENABLE 0 +#endif + +// Oscillator Calibration <0x0-0x1F> +// osculp32k_calib +#ifndef CONF_OSCULP32K_CALIB +#define CONF_OSCULP32K_CALIB 0x0 +#endif + +// +// + +// <<< end of configuration section >>> + +#endif // HPL_OSC32KCTRL_CONFIG_H diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/Config/hpl_oscctrl_config.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/Config/hpl_oscctrl_config.h new file mode 100644 index 00000000..7488b5d3 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/Config/hpl_oscctrl_config.h @@ -0,0 +1,462 @@ +/* Auto-generated config file hpl_oscctrl_config.h */ +#ifndef HPL_OSCCTRL_CONFIG_H +#define HPL_OSCCTRL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// External Multipurpose Crystal Oscillator Configuration +// Indicates whether configuration for XOSC is enabled or not +// enable_xosc +#ifndef CONF_XOSC_CONFIG +#define CONF_XOSC_CONFIG 0 +#endif + +// Frequency <400000-32000000> +// Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator. +// xosc_frequency +#ifndef CONF_XOSC_FREQUENCY +#define CONF_XOSC_FREQUENCY 400000 +#endif + +// External Multipurpose Crystal Oscillator Control +// Oscillator enable +// Indicates whether External Multipurpose Crystal Oscillator is enabled or not +// xosc_arch_enable +#ifndef CONF_XOSC_ENABLE +#define CONF_XOSC_ENABLE 0 +#endif + +// Start-Up Time +// <0x0=>31us +// <0x1=>61us +// <0x2=>122us +// <0x3=>244us +// <0x4=>488us +// <0x5=>977us +// <0x6=>1953us +// <0x7=>3906us +// <0x8=>7813us +// <0x9=>15625us +// <0xA=>31250us +// <0xB=>62500us +// <0xC=>125000us +// <0xD=>250000us +// <0xE=>500000us +// <0xF=>1000000us +// xosc_arch_startup +#ifndef CONF_XOSC_STARTUP +#define CONF_XOSC_STARTUP 0x0 +#endif + +// Automatic Amplitude Gain Control +// Indicates whether Automatic Amplitude Gain Control is enabled or not +// xosc_arch_ampgc +#ifndef CONF_XOSC_AMPGC +#define CONF_XOSC_AMPGC 0 +#endif + +// External Multipurpose Crystal Oscillator Gain +// <0x0=>2MHz +// <0x1=>4MHz +// <0x2=>8MHz +// <0x3=>16MHz +// <0x4=>30MHz +// xosc_arch_gain +#ifndef CONF_XOSC_GAIN +#define CONF_XOSC_GAIN 0x0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// xosc_arch_ondemand +#ifndef CONF_XOSC_ONDEMAND +#define CONF_XOSC_ONDEMAND 1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// xosc_arch_runstdby +#ifndef CONF_XOSC_RUNSTDBY +#define CONF_XOSC_RUNSTDBY 0 +#endif + +// Crystal connected to XIN/XOUT Enable +// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not +// xosc_arch_xtalen +#ifndef CONF_XOSC_XTALEN +#define CONF_XOSC_XTALEN 0 +#endif +// +// + +// 16MHz Internal Oscillator Configuration +// Indicates whether configuration for OSC8M is enabled or not +// enable_osc16m +#ifndef CONF_OSC16M_CONFIG +#define CONF_OSC16M_CONFIG 1 +#endif + +// 16MHz Internal Oscillator Control +// Enable +// Indicates whether 16MHz Internal Oscillator is enabled or not +// osc16m_arch_enable +#ifndef CONF_OSC16M_ENABLE +#define CONF_OSC16M_ENABLE 1 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// osc16m_arch_ondemand +#ifndef CONF_OSC16M_ONDEMAND +#define CONF_OSC16M_ONDEMAND 1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// osc16m_arch_runstdby +#ifndef CONF_OSC16M_RUNSTDBY +#define CONF_OSC16M_RUNSTDBY 0 +#endif + +// Oscillator Frequency Selection(Mhz) +// 4 +// 8 +// 12 +// 16 +// This defines the oscillator frequency (Mhz) +// osc16m_freq +#ifndef CONF_OSC16M_FSEL +#define CONF_OSC16M_FSEL OSCCTRL_OSC16MCTRL_FSEL_4_Val +#endif + +// Oscillator Calibration Control +// Indicates whether Oscillator Calibration is enabled or not +// osc16m_arch_calib_enable +#ifndef CONF_OSC16M_CALIB_ENABLE +#define CONF_OSC16M_CALIB_ENABLE 0 +#endif + +// 4MHz Frequency Calibration <0x0-0x3F> +// osc16m_arch_4m_fcal +#ifndef CONF_OSC16M_FCAL +#define CONF_OSC16M_4M_FCAL 0 +#endif + +// 4MHz Temperature Calibration <0x0-0x3F> +// osc16m_arch_4m_tcal +#ifndef CONF_OSC16M_TCAL +#define CONF_OSC16M_4M_TCAL 0 +#endif + +// 8MHz Frequency Calibration <0x0-0x3F> +// osc16m_arch_8m_fcal +#ifndef CONF_OSC16M_FCAL +#define CONF_OSC16M_8M_FCAL 0 +#endif + +// 8MHz Temperature Calibration <0x0-0x3F> +// osc16m_arch_8m_tcal +#ifndef CONF_OSC16M_TCAL +#define CONF_OSC16M_8M_TCAL 0 +#endif + +// 12MHz Frequency Calibration <0x0-0x3F> +// osc16m_arch_12m_fcal +#ifndef CONF_OSC16M_FCAL +#define CONF_OSC16M_12M_FCAL 0 +#endif + +// 12MHz Temperature Calibration <0x0-0x3F> +// osc16m_arch_12m_tcal +#ifndef CONF_OSC16M_TCAL +#define CONF_OSC16M_12M_TCAL 0 +#endif + +// 16MHz Frequency Calibration <0x0-0x3F> +// osc16m_arch_fcal +#ifndef CONF_OSC16M_FCAL +#define CONF_OSC16M_16M_FCAL 0 +#endif + +// 16MHz Temperature Calibration <0x0-0x3F> +// osc16m_arch_16m_tcal +#ifndef CONF_OSC16M_TCAL +#define CONF_OSC16M_16M_TCAL 0 +#endif +// +// + +// DFLL Configuration +// Indicates whether configuration for DFLL is enabled or not +// enable_dfll48m +#ifndef CONF_DFLL_CONFIG +#define CONF_DFLL_CONFIG 0 +#endif + +// Reference Clock Source +// Generic clock generator 0 +// Generic clock generator 1 +// Generic clock generator 2 +// Generic clock generator 3 +// Generic clock generator 4 +// Generic clock generator 5 +// Generic clock generator 6 +// Generic clock generator 7 +// Select the clock source. +// dfll48m_ref_clock +#ifndef CONF_DFLL_GCLK +#define CONF_DFLL_GCLK GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +// Digital Frequency Locked Loop Control +// DFLL Enable +// Indicates whether DFLL is enabled or not +// dfll48m_arch_enable +#ifndef CONF_DFLL_ENABLE +#define CONF_DFLL_ENABLE 0 +#endif + +// Wait Lock +// Indicates whether Wait Lock is enabled or not +// dfll_arch_waitlock +#ifndef CONF_DFLL_WAITLOCK +#define CONF_DFLL_WAITLOCK 0 +#endif + +// Bypass Coarse Lock +// Indicates whether Bypass Coarse Lock is enabled or not +// dfll_arch_bplckc +#ifndef CONF_DFLL_BPLCKC +#define CONF_DFLL_BPLCKC 0 +#endif + +// Quick Lock Disable +// Indicates whether Quick Lock Disable is enabled or not +// dfll_arch_qldis +#ifndef CONF_DFLL_QLDIS +#define CONF_DFLL_QLDIS 0 +#endif + +// Chill Cycle Disable +// Indicates whether Chill Cycle Disable is enabled or not +// dfll_arch_ccdis +#ifndef CONF_DFLL_CCDIS +#define CONF_DFLL_CCDIS 0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// dfll_arch_ondemand +#ifndef CONF_DFLL_ONDEMAND +#define CONF_DFLL_ONDEMAND 1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// dfll_arch_runstdby +#ifndef CONF_DFLL_RUNSTDBY +#define CONF_DFLL_RUNSTDBY 0 +#endif + +// USB Clock Recovery Mode +// Indicates whether USB Clock Recovery Mode is enabled or not +// dfll_arch_usbcrm +#ifndef CONF_DFLL_USBCRM +#define CONF_DFLL_USBCRM 0 +#endif + +// Lose Lock After Wake +// Indicates whether Lose Lock After Wake is enabled or not +// dfll_arch_llaw +#ifndef CONF_DFLL_LLAW +#define CONF_DFLL_LLAW 0 +#endif + +// Stable DFLL Frequency +// Indicates whether Stable DFLL Frequency is enabled or not +// dfll_arch_stable +#ifndef CONF_DFLL_STABLE +#define CONF_DFLL_STABLE 0 +#endif + +// Operating Mode Selection +// <0=>Open Loop Mode +// <1=>Closed Loop Mode +// dfll48m_mode +#ifndef CONF_DFLL_MODE +#define CONF_DFLL_MODE 0 +#endif + +// Coarse Maximum Step <0x0-0x1F> +// dfll_arch_cstep +#ifndef CONF_DFLL_CSTEP +#define CONF_DFLL_CSTEP 1 +#endif + +// Fine Maximum Step <0x0-0x3FF> +// dfll_arch_fstep +#ifndef CONF_DFLL_FSTEP +#define CONF_DFLL_FSTEP 1 +#endif + +// DFLL Multiply Factor <0x0-0xFFFF> +// dfll48m_mul +#ifndef CONF_DFLL_MUL +#define CONF_DFLL_MUL 0 +#endif + +// DFLL Calibration Overwrite +// Indicates whether Overwrite Calibration value of DFLL +// dfll_arch_calibration +#ifndef CONF_DFLL_OVERWRITE_CALIBRATION +#define CONF_DFLL_OVERWRITE_CALIBRATION 0 +#endif + +// Coarse Value <0x0-0x3F> +// dfll_arch_coarse +#ifndef CONF_DFLL_COARSE +#define CONF_DFLL_COARSE (0x1f / 4) +#endif + +// Fine Value <0x0-0x3FF> +// dfll_arch_fine +#ifndef CONF_DFLL_FINE +#define CONF_DFLL_FINE (0x200) +#endif + +// + +// + +// + +// DPLL Configuration +// Indicates whether configuration for DPLL is enabled or not +// enable_fdpll96m +#ifndef CONF_DPLL_CONFIG +#define CONF_DPLL_CONFIG 0 +#endif + +// Reference Clock Source +// 32kHz External Crystal Oscillator (XOSC32K) +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator 0 +// Generic clock generator 1 +// Generic clock generator 2 +// Generic clock generator 3 +// Generic clock generator 4 +// Generic clock generator 5 +// Generic clock generator 6 +// Generic clock generator 7 +// Select the clock source. +// fdpll96m_ref_clock +#ifndef CONF_DPLL_GCLK +#define CONF_DPLL_GCLK GCLK_GENCTRL_SRC_XOSC32K + +#endif + +// Digital Phase Locked Loop Control +// Enable +// Indicates whether Digital Phase Locked Loop is enabled or not +// fdpll96m_arch_enable +#ifndef CONF_DPLL_ENABLE +#define CONF_DPLL_ENABLE 0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// fdpll96m_arch_ondemand +#ifndef CONF_DPLL_ONDEMAND +#define CONF_DPLL_ONDEMAND 1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// fdpll96m_arch_runstdby +#ifndef CONF_DPLL_RUNSTDBY +#define CONF_DPLL_RUNSTDBY 0 +#endif + +// Loop Divider Ratio Fractional Part <0x0-0xF> +// fdpll96m_ldrfrac +#ifndef CONF_DPLL_LDRFRAC +#define CONF_DPLL_LDRFRAC 0xd +#endif + +// Loop Divider Ratio Integer Part <0x0-0xFFF> +// fdpll96m_ldr +#ifndef CONF_DPLL_LDR +#define CONF_DPLL_LDR 0x5b7 +#endif + +// Clock Divider <0x0-0x3FF> +// fdpll96m_clock_div +#ifndef CONF_DPLL_DIV +#define CONF_DPLL_DIV 0 +#endif + +// Lock Bypass +// Indicates whether Lock Bypass is enabled or not +// fdpll96m_arch_lbypass +#ifndef CONF_DPLL_LBYPASS +#define CONF_DPLL_LBYPASS 0 +#endif + +// Lock Time +// <0=>No time-out, automatic lock +// <4=>The Time-out if no lock within 8 ms +// <5=>The Time-out if no lock within 9 ms +// <6=>The Time-out if no lock within 10 ms +// <7=>The Time-out if no lock within 11 ms +// fdpll96m_arch_ltime +#ifndef CONF_DPLL_LTIME +#define CONF_DPLL_LTIME 0 +#endif + +// Reference Clock Selection +// <0=>XOSC32K clock reference +// <1=>XOSC clock reference +// <2=>GCLK clock reference +// fdpll96m_arch_refclk +#ifndef CONF_DPLL_REFCLK +#define CONF_DPLL_REFCLK 0 +#endif + +// Wake Up Fast +// Indicates whether Wake Up Fast is enabled or not +// fdpll96m_arch_wuf +#ifndef CONF_DPLL_WUF +#define CONF_DPLL_WUF 0 +#endif + +// Low-Power Enable +// Indicates whether Low-Power Enable is enabled or not +// fdpll96m_arch_lpen +#ifndef CONF_DPLL_LPEN +#define CONF_DPLL_LPEN 0 +#endif + +// Reference Clock Selection +// <0=>Default filter mode +// <1=>Low bandwidth filter +// <2=>High bandwidth filter +// <3=>High damping filter +// fdpll96m_arch_filter +#ifndef CONF_DPLL_FILTER +#define CONF_DPLL_FILTER 0 +#endif + +// Output Clock Prescaler +// 1 +// 2 +// 4 +// fdpll96m_presc +#ifndef CONF_DPLL_PRESC +#define CONF_DPLL_PRESC OSCCTRL_DPLLPRESC_PRESC_DIV1_Val +#endif +// +// + +// <<< end of configuration section >>> + +#endif // HPL_OSCCTRL_CONFIG_H diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/Config/hpl_port_config.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/Config/hpl_port_config.h new file mode 100644 index 00000000..1efce33e --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/Config/hpl_port_config.h @@ -0,0 +1,284 @@ +/* Auto-generated config file hpl_port_config.h */ +#ifndef HPL_PORT_CONFIG_H +#define HPL_PORT_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// PORT Input Event 0 configuration +// enable_port_input_event_0 +#ifndef CONF_PORT_EVCTRL_PORT_0 +#define CONF_PORT_EVCTRL_PORT_0 0 +#endif + +// PORT Input Event 0 configuration on PORT A + +// PORTA Input Event 0 Enable +// The event action will be triggered on any incoming event if PORT A Input Event 0 configuration is enabled +// porta_input_event_enable_0 +#ifndef CONF_PORTA_EVCTRL_PORTEI_0 +#define CONF_PORTA_EVCTRL_PORTEI_0 0x0 +#endif + +// PORTA Event 0 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port A on which the event action will be performed +// porta_event_pin_identifier_0 +#ifndef CONF_PORTA_EVCTRL_PID_0 +#define CONF_PORTA_EVCTRL_PID_0 0x0 +#endif + +// PORTA Event 0 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT A will perform on event input 0 +// porta_event_action_0 +#ifndef CONF_PORTA_EVCTRL_EVACT_0 +#define CONF_PORTA_EVCTRL_EVACT_0 0 +#endif + +// +// PORT Input Event 0 configuration on PORT B + +// PORTB Input Event 0 Enable +// The event action will be triggered on any incoming event if PORT B Input Event 0 configuration is enabled +// portb_input_event_enable_0 +#ifndef CONF_PORTB_EVCTRL_PORTEI_0 +#define CONF_PORTB_EVCTRL_PORTEI_0 0x0 +#endif + +// PORTB Event 0 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port B on which the event action will be performed +// portb_event_pin_identifier_0 +#ifndef CONF_PORTB_EVCTRL_PID_0 +#define CONF_PORTB_EVCTRL_PID_0 0x0 +#endif + +// PORTB Event 0 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT B will perform on event input 0 +// portb_event_action_0 +#ifndef CONF_PORTB_EVCTRL_EVACT_0 +#define CONF_PORTB_EVCTRL_EVACT_0 0 +#endif + +// + +// + +// PORT Input Event 1 configuration +// enable_port_input_event_1 +#ifndef CONF_PORT_EVCTRL_PORT_1 +#define CONF_PORT_EVCTRL_PORT_1 0 +#endif + +// PORT Input Event 1 configuration on PORT A + +// PORTA Input Event 1 Enable +// The event action will be triggered on any incoming event if PORT A Input Event 1 configuration is enabled +// porta_input_event_enable_1 +#ifndef CONF_PORTA_EVCTRL_PORTEI_1 +#define CONF_PORTA_EVCTRL_PORTEI_1 0x0 +#endif + +// PORTA Event 1 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port A on which the event action will be performed +// porta_event_pin_identifier_1 +#ifndef CONF_PORTA_EVCTRL_PID_1 +#define CONF_PORTA_EVCTRL_PID_1 0x0 +#endif + +// PORTA Event 1 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT A will perform on event input 1 +// porta_event_action_1 +#ifndef CONF_PORTA_EVCTRL_EVACT_1 +#define CONF_PORTA_EVCTRL_EVACT_1 0 +#endif + +// +// PORT Input Event 1 configuration on PORT B + +// PORTB Input Event 1 Enable +// The event action will be triggered on any incoming event if PORT B Input Event 1 configuration is enabled +// portb_input_event_enable_1 +#ifndef CONF_PORTB_EVCTRL_PORTEI_1 +#define CONF_PORTB_EVCTRL_PORTEI_1 0x0 +#endif + +// PORTB Event 1 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port B on which the event action will be performed +// portb_event_pin_identifier_1 +#ifndef CONF_PORTB_EVCTRL_PID_1 +#define CONF_PORTB_EVCTRL_PID_1 0x0 +#endif + +// PORTB Event 1 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT B will perform on event input 1 +// portb_event_action_1 +#ifndef CONF_PORTB_EVCTRL_EVACT_1 +#define CONF_PORTB_EVCTRL_EVACT_1 0 +#endif + +// + +// + +// PORT Input Event 2 configuration +// enable_port_input_event_2 +#ifndef CONF_PORT_EVCTRL_PORT_2 +#define CONF_PORT_EVCTRL_PORT_2 0 +#endif + +// PORT Input Event 2 configuration on PORT A + +// PORTA Input Event 2 Enable +// The event action will be triggered on any incoming event if PORT A Input Event 2 configuration is enabled +// porta_input_event_enable_2 +#ifndef CONF_PORTA_EVCTRL_PORTEI_2 +#define CONF_PORTA_EVCTRL_PORTEI_2 0x0 +#endif + +// PORTA Event 2 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port A on which the event action will be performed +// porta_event_pin_identifier_2 +#ifndef CONF_PORTA_EVCTRL_PID_2 +#define CONF_PORTA_EVCTRL_PID_2 0x0 +#endif + +// PORTA Event 2 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT A will perform on event input 2 +// porta_event_action_2 +#ifndef CONF_PORTA_EVCTRL_EVACT_2 +#define CONF_PORTA_EVCTRL_EVACT_2 0 +#endif + +// +// PORT Input Event 2 configuration on PORT B + +// PORTB Input Event 2 Enable +// The event action will be triggered on any incoming event if PORT B Input Event 2 configuration is enabled +// portb_input_event_enable_2 +#ifndef CONF_PORTB_EVCTRL_PORTEI_2 +#define CONF_PORTB_EVCTRL_PORTEI_2 0x0 +#endif + +// PORTB Event 2 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port B on which the event action will be performed +// portb_event_pin_identifier_2 +#ifndef CONF_PORTB_EVCTRL_PID_2 +#define CONF_PORTB_EVCTRL_PID_2 0x0 +#endif + +// PORTB Event 2 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT B will perform on event input 2 +// portb_event_action_2 +#ifndef CONF_PORTB_EVCTRL_EVACT_2 +#define CONF_PORTB_EVCTRL_EVACT_2 0 +#endif + +// + +// + +// PORT Input Event 3 configuration +// enable_port_input_event_3 +#ifndef CONF_PORT_EVCTRL_PORT_3 +#define CONF_PORT_EVCTRL_PORT_3 0 +#endif + +// PORT Input Event 3 configuration on PORT A + +// PORTA Input Event 3 Enable +// The event action will be triggered on any incoming event if PORT A Input Event 3 configuration is enabled +// porta_input_event_enable_3 +#ifndef CONF_PORTA_EVCTRL_PORTEI_3 +#define CONF_PORTA_EVCTRL_PORTEI_3 0x0 +#endif + +// PORTA Event 3 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port A on which the event action will be performed +// porta_event_pin_identifier_3 +#ifndef CONF_PORTA_EVCTRL_PID_3 +#define CONF_PORTA_EVCTRL_PID_3 0x0 +#endif + +// PORTA Event 3 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT A will perform on event input 3 +// porta_event_action_3 +#ifndef CONF_PORTA_EVCTRL_EVACT_3 +#define CONF_PORTA_EVCTRL_EVACT_3 0 +#endif + +// +// PORT Input Event 3 configuration on PORT B + +// PORTB Input Event 3 Enable +// The event action will be triggered on any incoming event if PORT B Input Event 3 configuration is enabled +// portb_input_event_enable_3 +#ifndef CONF_PORTB_EVCTRL_PORTEI_3 +#define CONF_PORTB_EVCTRL_PORTEI_3 0x0 +#endif + +// PORTB Event 3 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port B on which the event action will be performed +// portb_event_pin_identifier_3 +#ifndef CONF_PORTB_EVCTRL_PID_3 +#define CONF_PORTB_EVCTRL_PID_3 0x0 +#endif + +// PORTB Event 3 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT B will perform on event input 3 +// portb_event_action_3 +#ifndef CONF_PORTB_EVCTRL_EVACT_3 +#define CONF_PORTB_EVCTRL_EVACT_3 0 +#endif + +// + +// + +#define CONF_PORTA_EVCTRL \ + (0 | PORT_EVCTRL_EVACT0(CONF_PORTA_EVCTRL_EVACT_0) | CONF_PORTA_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ + | PORT_EVCTRL_PID0(CONF_PORTA_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTA_EVCTRL_EVACT_1) \ + | CONF_PORTA_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTA_EVCTRL_PID_1) \ + | PORT_EVCTRL_EVACT2(CONF_PORTA_EVCTRL_EVACT_2) | CONF_PORTA_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ + | PORT_EVCTRL_PID2(CONF_PORTA_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTA_EVCTRL_EVACT_3) \ + | CONF_PORTA_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTA_EVCTRL_PID_3)) +#define CONF_PORTB_EVCTRL \ + (0 | PORT_EVCTRL_EVACT0(CONF_PORTB_EVCTRL_EVACT_0) | CONF_PORTB_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ + | PORT_EVCTRL_PID0(CONF_PORTB_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTB_EVCTRL_EVACT_1) \ + | CONF_PORTB_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTB_EVCTRL_PID_1) \ + | PORT_EVCTRL_EVACT2(CONF_PORTB_EVCTRL_EVACT_2) | CONF_PORTB_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ + | PORT_EVCTRL_PID2(CONF_PORTB_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTB_EVCTRL_EVACT_3) \ + | CONF_PORTB_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTB_EVCTRL_PID_3)) + +// <<< end of configuration section >>> + +#endif // HPL_PORT_CONFIG_H diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/Config/hpl_sercom_config.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/Config/hpl_sercom_config.h new file mode 100644 index 00000000..a2c82294 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/Config/hpl_sercom_config.h @@ -0,0 +1,803 @@ +/* Auto-generated config file hpl_sercom_config.h */ +#ifndef HPL_SERCOM_CONFIG_H +#define HPL_SERCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include + +#ifndef CONF_SERCOM_1_USART_ENABLE +#define CONF_SERCOM_1_USART_ENABLE 1 +#endif + +// Basic Configuration + +// Receive buffer enable +// Enable input buffer in SERCOM module +// usart_rx_enable +#ifndef CONF_SERCOM_1_USART_RXEN +#define CONF_SERCOM_1_USART_RXEN 1 +#endif + +// Transmitt buffer enable +// Enable output buffer in SERCOM module +// usart_tx_enable +#ifndef CONF_SERCOM_1_USART_TXEN +#define CONF_SERCOM_1_USART_TXEN 1 +#endif + +// Frame parity +// <0x0=>No parity +// <0x1=>Even parity +// <0x2=>Odd parity +// Parity bit mode for USART frame +// usart_parity +#ifndef CONF_SERCOM_1_USART_PARITY +#define CONF_SERCOM_1_USART_PARITY 0x0 +#endif + +// Character Size +// <0x0=>8 bits +// <0x1=>9 bits +// <0x5=>5 bits +// <0x6=>6 bits +// <0x7=>7 bits +// Data character size in USART frame +// usart_character_size +#ifndef CONF_SERCOM_1_USART_CHSIZE +#define CONF_SERCOM_1_USART_CHSIZE 0x0 +#endif + +// Stop Bit +// <0=>One stop bit +// <1=>Two stop bits +// Number of stop bits in USART frame +// usart_stop_bit +#ifndef CONF_SERCOM_1_USART_SBMODE +#define CONF_SERCOM_1_USART_SBMODE 0 +#endif + +// Baud rate <1-3000000> +// USART baud rate setting +// usart_baud_rate +#ifndef CONF_SERCOM_1_USART_BAUD +#define CONF_SERCOM_1_USART_BAUD 9600 +#endif + +// + +// Advanced configuration +// usart_advanced +#ifndef CONF_SERCOM_1_USART_ADVANCED_CONFIG +#define CONF_SERCOM_1_USART_ADVANCED_CONFIG 0 +#endif + +// Run in stand-by +// Keep the module running in standby sleep mode +// usart_arch_runstdby +#ifndef CONF_SERCOM_1_USART_RUNSTDBY +#define CONF_SERCOM_1_USART_RUNSTDBY 0 +#endif + +// Immediate Buffer Overflow Notification +// Controls when the BUFOVF status bit is asserted +// usart_arch_ibon +#ifndef CONF_SERCOM_1_USART_IBON +#define CONF_SERCOM_1_USART_IBON 0 +#endif + +// Start of Frame Detection Enable +// Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled) +// usart_arch_sfde +#ifndef CONF_SERCOM_1_USART_SFDE +#define CONF_SERCOM_1_USART_SFDE 0 +#endif + +// Collision Detection Enable +// Collision detection enable +// usart_arch_cloden +#ifndef CONF_SERCOM_1_USART_CLODEN +#define CONF_SERCOM_1_USART_CLODEN 0 +#endif + +// Operating Mode +// <0x0=>USART with external clock +// <0x1=>USART with internal clock +// Drive the shift register by an internal clock generated by the baud rate generator or an external clock supplied on the XCK pin. +// usart_arch_clock_mode +#ifndef CONF_SERCOM_1_USART_MODE +#define CONF_SERCOM_1_USART_MODE 0x1 +#endif + +// Sample Rate +// <0x0=>16x arithmetic +// <0x1=>16x fractional +// <0x2=>8x arithmetic +// <0x3=>8x fractional +// <0x4=>3x arithmetic +// How many over-sampling bits used when sampling data state +// usart_arch_sampr +#ifndef CONF_SERCOM_1_USART_SAMPR +#define CONF_SERCOM_1_USART_SAMPR 0x0 +#endif + +// Sample Adjustment +// <0x0=>7-8-9 (3-4-5 8-bit over-sampling) +// <0x1=>9-10-11 (4-5-6 8-bit over-sampling) +// <0x2=>11-12-13 (5-6-7 8-bit over-sampling) +// <0x3=>13-14-15 (6-7-8 8-bit over-sampling) +// Adjust which samples to use for data sampling in asynchronous mode +// usart_arch_sampa +#ifndef CONF_SERCOM_1_USART_SAMPA +#define CONF_SERCOM_1_USART_SAMPA 0x0 +#endif + +// Fractional Part <0-7> +// Fractional part of the baud rate if baud rate generator is in fractional mode +// usart_arch_fractional +#ifndef CONF_SERCOM_1_USART_FRACTIONAL +#define CONF_SERCOM_1_USART_FRACTIONAL 0x0 +#endif + +// Data Order +// <0=>MSB is transmitted first +// <1=>LSB is transmitted first +// Data order of the data bits in the frame +// usart_arch_dord +#ifndef CONF_SERCOM_1_USART_DORD +#define CONF_SERCOM_1_USART_DORD 1 +#endif + +// Does not do anything in UART mode +#define CONF_SERCOM_1_USART_CPOL 0 + +// Encoding Format +// <0=>No encoding +// <1=>IrDA encoded +// usart_arch_enc +#ifndef CONF_SERCOM_1_USART_ENC +#define CONF_SERCOM_1_USART_ENC 0 +#endif + +// LIN Slave Enable +// Break Character Detection and Auto-Baud/LIN Slave Enable. +// Additional setting needed: 16x sample rate using fractional baud rate generation (CTRLA.SAMPR = 1). +// <0=>Disable +// <1=>Enable +// usart_arch_lin_slave_enable +#ifndef CONF_SERCOM_1_USART_LIN_SLAVE_ENABLE +#define CONF_SERCOM_1_USART_LIN_SLAVE_ENABLE 0 +#endif + +// Debug Stop Mode +// Behavior of the baud-rate generator when CPU is halted by external debugger. +// <0=>Keep running +// <1=>Halt +// usart_arch_dbgstop +#ifndef CONF_SERCOM_1_USART_DEBUG_STOP_MODE +#define CONF_SERCOM_1_USART_DEBUG_STOP_MODE 0 +#endif + +// + +#ifndef CONF_SERCOM_1_USART_CMODE +#define CONF_SERCOM_1_USART_CMODE 0 +#endif + +#ifndef CONF_SERCOM_1_USART_RXPO +#define CONF_SERCOM_1_USART_RXPO 3 /* RX is on PIN_PA19 */ +#endif + +#ifndef CONF_SERCOM_1_USART_TXPO +#define CONF_SERCOM_1_USART_TXPO 1 /* TX is on PIN_PA18 */ +#endif + +/* Set correct parity settings in register interface based on PARITY setting */ +#if CONF_SERCOM_1_USART_LIN_SLAVE_ENABLE == 1 +#if CONF_SERCOM_1_USART_PARITY == 0 +#define CONF_SERCOM_1_USART_PMODE 0 +#define CONF_SERCOM_1_USART_FORM 4 +#else +#define CONF_SERCOM_1_USART_PMODE CONF_SERCOM_1_USART_PARITY - 1 +#define CONF_SERCOM_1_USART_FORM 5 +#endif +#else /* #if CONF_SERCOM_1_USART_LIN_SLAVE_ENABLE == 0 */ +#if CONF_SERCOM_1_USART_PARITY == 0 +#define CONF_SERCOM_1_USART_PMODE 0 +#define CONF_SERCOM_1_USART_FORM 0 +#else +#define CONF_SERCOM_1_USART_PMODE CONF_SERCOM_1_USART_PARITY - 1 +#define CONF_SERCOM_1_USART_FORM 1 +#endif +#endif + +// Calculate BAUD register value in UART mode +#if CONF_SERCOM_1_USART_SAMPR == 0 +#ifndef CONF_SERCOM_1_USART_BAUD_RATE +#define CONF_SERCOM_1_USART_BAUD_RATE \ + 65536 - ((65536 * 16.0f * CONF_SERCOM_1_USART_BAUD) / CONF_GCLK_SERCOM1_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_1_USART_SAMPR == 1 +#ifndef CONF_SERCOM_1_USART_BAUD_RATE +#define CONF_SERCOM_1_USART_BAUD_RATE \ + ((CONF_GCLK_SERCOM1_CORE_FREQUENCY) / (CONF_SERCOM_1_USART_BAUD * 16)) - (CONF_SERCOM_1_USART_FRACTIONAL / 8) +#endif +#ifndef CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_1_USART_SAMPR == 2 +#ifndef CONF_SERCOM_1_USART_BAUD_RATE +#define CONF_SERCOM_1_USART_BAUD_RATE \ + 65536 - ((65536 * 8.0f * CONF_SERCOM_1_USART_BAUD) / CONF_GCLK_SERCOM1_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_1_USART_SAMPR == 3 +#ifndef CONF_SERCOM_1_USART_BAUD_RATE +#define CONF_SERCOM_1_USART_BAUD_RATE \ + ((CONF_GCLK_SERCOM1_CORE_FREQUENCY) / (CONF_SERCOM_1_USART_BAUD * 8)) - (CONF_SERCOM_1_USART_FRACTIONAL / 8) +#endif +#ifndef CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_1_USART_SAMPR == 4 +#ifndef CONF_SERCOM_1_USART_BAUD_RATE +#define CONF_SERCOM_1_USART_BAUD_RATE \ + 65536 - ((65536 * 3.0f * CONF_SERCOM_1_USART_BAUD) / CONF_GCLK_SERCOM1_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#endif + +#include + +#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER +#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2) +#endif + +#ifndef CONF_SERCOM_2_I2CM_ENABLE +#define CONF_SERCOM_2_I2CM_ENABLE 1 +#endif + +// Basic + +// I2C Bus clock speed (Hz) <1-400000> +// I2C Bus clock (SCL) speed measured in Hz +// i2c_master_baud_rate +#ifndef CONF_SERCOM_2_I2CM_BAUD +#define CONF_SERCOM_2_I2CM_BAUD 100000 +#endif + +// + +// Advanced +// i2c_master_advanced +#ifndef CONF_SERCOM_2_I2CM_ADVANCED_CONFIG +#define CONF_SERCOM_2_I2CM_ADVANCED_CONFIG 0 +#endif + +// TRise (ns) <0-300> +// Determined by the bus impedance, check electric characteristics in the datasheet +// Standard Fast Mode: typical 215ns, max 300ns +// Fast Mode +: typical 60ns, max 100ns +// High Speed Mode: typical 20ns, max 40ns +// i2c_master_arch_trise + +#ifndef CONF_SERCOM_2_I2CM_TRISE +#define CONF_SERCOM_2_I2CM_TRISE 215 +#endif + +// Master SCL Low Extended Time-Out (MEXTTOEN) +// This enables the master SCL low extend time-out +// i2c_master_arch_mexttoen +#ifndef CONF_SERCOM_2_I2CM_MEXTTOEN +#define CONF_SERCOM_2_I2CM_MEXTTOEN 0 +#endif + +// Slave SCL Low Extend Time-Out (SEXTTOEN) +// Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine +// i2c_master_arch_sexttoen +#ifndef CONF_SERCOM_2_I2CM_SEXTTOEN +#define CONF_SERCOM_2_I2CM_SEXTTOEN 0 +#endif + +// SCL Low Time-Out (LOWTOUT) +// Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold +// i2c_master_arch_lowtout +#ifndef CONF_SERCOM_2_I2CM_LOWTOUT +#define CONF_SERCOM_2_I2CM_LOWTOUT 0 +#endif + +// Inactive Time-Out (INACTOUT) +// <0x0=>Disabled +// <0x1=>5-6 SCL cycle time-out(50-60us) +// <0x2=>10-11 SCL cycle time-out(100-110us) +// <0x3=>20-21 SCL cycle time-out(200-210us) +// Defines if inactivity time-out should be enabled, and how long the time-out should be +// i2c_master_arch_inactout +#ifndef CONF_SERCOM_2_I2CM_INACTOUT +#define CONF_SERCOM_2_I2CM_INACTOUT 0x0 +#endif + +// SDA Hold Time (SDAHOLD) +// <0=>Disabled +// <1=>50-100ns hold time +// <2=>300-600ns hold time +// <3=>400-800ns hold time +// Defines the SDA hold time with respect to the negative edge of SCL +// i2c_master_arch_sdahold +#ifndef CONF_SERCOM_2_I2CM_SDAHOLD +#define CONF_SERCOM_2_I2CM_SDAHOLD 0x2 +#endif + +// Run in stand-by +// Determine if the module shall run in standby sleep mode +// i2c_master_arch_runstdby +#ifndef CONF_SERCOM_2_I2CM_RUNSTDBY +#define CONF_SERCOM_2_I2CM_RUNSTDBY 0 +#endif + +// Debug Stop Mode +// Behavior of the baud-rate generator when CPU is halted by external debugger. +// <0=>Keep running +// <1=>Halt +// i2c_master_arch_dbgstop +#ifndef CONF_SERCOM_2_I2CM_DEBUG_STOP_MODE +#define CONF_SERCOM_2_I2CM_DEBUG_STOP_MODE 0 +#endif + +// + +#ifndef CONF_SERCOM_2_I2CM_SPEED +#define CONF_SERCOM_2_I2CM_SPEED 0x00 // Speed: Standard/Fast mode +#endif +#if CONF_SERCOM_2_I2CM_TRISE < 215 || CONF_SERCOM_2_I2CM_TRISE > 300 +#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns +#undef CONF_SERCOM_2_I2CM_TRISE +#define CONF_SERCOM_2_I2CM_TRISE 215U +#endif + +// gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise) +// BAUD + BAUDLOW = -------------------------------------------------------------------- +// i2c_scl_freq +// BAUD: register value low [7:0] +// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW +#define CONF_SERCOM_2_I2CM_BAUD_BAUDLOW \ + (((CONF_GCLK_SERCOM2_CORE_FREQUENCY - (CONF_SERCOM_2_I2CM_BAUD * 10U) \ + - (CONF_SERCOM_2_I2CM_TRISE * (CONF_SERCOM_2_I2CM_BAUD / 100U) * (CONF_GCLK_SERCOM2_CORE_FREQUENCY / 10000U) \ + / 1000U)) \ + * 10U \ + + 5U) \ + / (CONF_SERCOM_2_I2CM_BAUD * 10U)) +#ifndef CONF_SERCOM_2_I2CM_BAUD_RATE +#if CONF_SERCOM_2_I2CM_BAUD_BAUDLOW > (0xFF * 2) +#warning Requested I2C baudrate too low, please check +#define CONF_SERCOM_2_I2CM_BAUD_RATE 0xFF +#elif CONF_SERCOM_2_I2CM_BAUD_BAUDLOW <= 1 +#warning Requested I2C baudrate too high, please check +#define CONF_SERCOM_2_I2CM_BAUD_RATE 1 +#else +#define CONF_SERCOM_2_I2CM_BAUD_RATE \ + ((CONF_SERCOM_2_I2CM_BAUD_BAUDLOW & 0x1) \ + ? (CONF_SERCOM_2_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_2_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \ + : (CONF_SERCOM_2_I2CM_BAUD_BAUDLOW / 2)) +#endif +#endif + +#include + +#ifndef CONF_SERCOM_3_USART_ENABLE +#define CONF_SERCOM_3_USART_ENABLE 1 +#endif + +// Basic Configuration + +// Receive buffer enable +// Enable input buffer in SERCOM module +// usart_rx_enable +#ifndef CONF_SERCOM_3_USART_RXEN +#define CONF_SERCOM_3_USART_RXEN 1 +#endif + +// Transmitt buffer enable +// Enable output buffer in SERCOM module +// usart_tx_enable +#ifndef CONF_SERCOM_3_USART_TXEN +#define CONF_SERCOM_3_USART_TXEN 1 +#endif + +// Frame parity +// <0x0=>No parity +// <0x1=>Even parity +// <0x2=>Odd parity +// Parity bit mode for USART frame +// usart_parity +#ifndef CONF_SERCOM_3_USART_PARITY +#define CONF_SERCOM_3_USART_PARITY 0x0 +#endif + +// Character Size +// <0x0=>8 bits +// <0x1=>9 bits +// <0x5=>5 bits +// <0x6=>6 bits +// <0x7=>7 bits +// Data character size in USART frame +// usart_character_size +#ifndef CONF_SERCOM_3_USART_CHSIZE +#define CONF_SERCOM_3_USART_CHSIZE 0x0 +#endif + +// Stop Bit +// <0=>One stop bit +// <1=>Two stop bits +// Number of stop bits in USART frame +// usart_stop_bit +#ifndef CONF_SERCOM_3_USART_SBMODE +#define CONF_SERCOM_3_USART_SBMODE 0 +#endif + +// Baud rate <1-3000000> +// USART baud rate setting +// usart_baud_rate +#ifndef CONF_SERCOM_3_USART_BAUD +#define CONF_SERCOM_3_USART_BAUD 9600 +#endif + +// + +// Advanced configuration +// usart_advanced +#ifndef CONF_SERCOM_3_USART_ADVANCED_CONFIG +#define CONF_SERCOM_3_USART_ADVANCED_CONFIG 0 +#endif + +// Run in stand-by +// Keep the module running in standby sleep mode +// usart_arch_runstdby +#ifndef CONF_SERCOM_3_USART_RUNSTDBY +#define CONF_SERCOM_3_USART_RUNSTDBY 0 +#endif + +// Immediate Buffer Overflow Notification +// Controls when the BUFOVF status bit is asserted +// usart_arch_ibon +#ifndef CONF_SERCOM_3_USART_IBON +#define CONF_SERCOM_3_USART_IBON 0 +#endif + +// Start of Frame Detection Enable +// Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled) +// usart_arch_sfde +#ifndef CONF_SERCOM_3_USART_SFDE +#define CONF_SERCOM_3_USART_SFDE 0 +#endif + +// Collision Detection Enable +// Collision detection enable +// usart_arch_cloden +#ifndef CONF_SERCOM_3_USART_CLODEN +#define CONF_SERCOM_3_USART_CLODEN 0 +#endif + +// Operating Mode +// <0x0=>USART with external clock +// <0x1=>USART with internal clock +// Drive the shift register by an internal clock generated by the baud rate generator or an external clock supplied on the XCK pin. +// usart_arch_clock_mode +#ifndef CONF_SERCOM_3_USART_MODE +#define CONF_SERCOM_3_USART_MODE 0x1 +#endif + +// Sample Rate +// <0x0=>16x arithmetic +// <0x1=>16x fractional +// <0x2=>8x arithmetic +// <0x3=>8x fractional +// <0x4=>3x arithmetic +// How many over-sampling bits used when sampling data state +// usart_arch_sampr +#ifndef CONF_SERCOM_3_USART_SAMPR +#define CONF_SERCOM_3_USART_SAMPR 0x0 +#endif + +// Sample Adjustment +// <0x0=>7-8-9 (3-4-5 8-bit over-sampling) +// <0x1=>9-10-11 (4-5-6 8-bit over-sampling) +// <0x2=>11-12-13 (5-6-7 8-bit over-sampling) +// <0x3=>13-14-15 (6-7-8 8-bit over-sampling) +// Adjust which samples to use for data sampling in asynchronous mode +// usart_arch_sampa +#ifndef CONF_SERCOM_3_USART_SAMPA +#define CONF_SERCOM_3_USART_SAMPA 0x0 +#endif + +// Fractional Part <0-7> +// Fractional part of the baud rate if baud rate generator is in fractional mode +// usart_arch_fractional +#ifndef CONF_SERCOM_3_USART_FRACTIONAL +#define CONF_SERCOM_3_USART_FRACTIONAL 0x0 +#endif + +// Data Order +// <0=>MSB is transmitted first +// <1=>LSB is transmitted first +// Data order of the data bits in the frame +// usart_arch_dord +#ifndef CONF_SERCOM_3_USART_DORD +#define CONF_SERCOM_3_USART_DORD 1 +#endif + +// Does not do anything in UART mode +#define CONF_SERCOM_3_USART_CPOL 0 + +// Encoding Format +// <0=>No encoding +// <1=>IrDA encoded +// usart_arch_enc +#ifndef CONF_SERCOM_3_USART_ENC +#define CONF_SERCOM_3_USART_ENC 0 +#endif + +// LIN Slave Enable +// Break Character Detection and Auto-Baud/LIN Slave Enable. +// Additional setting needed: 16x sample rate using fractional baud rate generation (CTRLA.SAMPR = 1). +// <0=>Disable +// <1=>Enable +// usart_arch_lin_slave_enable +#ifndef CONF_SERCOM_3_USART_LIN_SLAVE_ENABLE +#define CONF_SERCOM_3_USART_LIN_SLAVE_ENABLE 0 +#endif + +// Debug Stop Mode +// Behavior of the baud-rate generator when CPU is halted by external debugger. +// <0=>Keep running +// <1=>Halt +// usart_arch_dbgstop +#ifndef CONF_SERCOM_3_USART_DEBUG_STOP_MODE +#define CONF_SERCOM_3_USART_DEBUG_STOP_MODE 0 +#endif + +// + +#ifndef CONF_SERCOM_3_USART_CMODE +#define CONF_SERCOM_3_USART_CMODE 0 +#endif + +#ifndef CONF_SERCOM_3_USART_RXPO +#define CONF_SERCOM_3_USART_RXPO 1 /* RX is on PIN_PA23 */ +#endif + +#ifndef CONF_SERCOM_3_USART_TXPO +#define CONF_SERCOM_3_USART_TXPO 0 /* TX is on PIN_PA22 */ +#endif + +/* Set correct parity settings in register interface based on PARITY setting */ +#if CONF_SERCOM_3_USART_LIN_SLAVE_ENABLE == 1 +#if CONF_SERCOM_3_USART_PARITY == 0 +#define CONF_SERCOM_3_USART_PMODE 0 +#define CONF_SERCOM_3_USART_FORM 4 +#else +#define CONF_SERCOM_3_USART_PMODE CONF_SERCOM_3_USART_PARITY - 1 +#define CONF_SERCOM_3_USART_FORM 5 +#endif +#else /* #if CONF_SERCOM_3_USART_LIN_SLAVE_ENABLE == 0 */ +#if CONF_SERCOM_3_USART_PARITY == 0 +#define CONF_SERCOM_3_USART_PMODE 0 +#define CONF_SERCOM_3_USART_FORM 0 +#else +#define CONF_SERCOM_3_USART_PMODE CONF_SERCOM_3_USART_PARITY - 1 +#define CONF_SERCOM_3_USART_FORM 1 +#endif +#endif + +// Calculate BAUD register value in UART mode +#if CONF_SERCOM_3_USART_SAMPR == 0 +#ifndef CONF_SERCOM_3_USART_BAUD_RATE +#define CONF_SERCOM_3_USART_BAUD_RATE \ + 65536 - ((65536 * 16.0f * CONF_SERCOM_3_USART_BAUD) / CONF_GCLK_SERCOM3_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_3_USART_SAMPR == 1 +#ifndef CONF_SERCOM_3_USART_BAUD_RATE +#define CONF_SERCOM_3_USART_BAUD_RATE \ + ((CONF_GCLK_SERCOM3_CORE_FREQUENCY) / (CONF_SERCOM_3_USART_BAUD * 16)) - (CONF_SERCOM_3_USART_FRACTIONAL / 8) +#endif +#ifndef CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_3_USART_SAMPR == 2 +#ifndef CONF_SERCOM_3_USART_BAUD_RATE +#define CONF_SERCOM_3_USART_BAUD_RATE \ + 65536 - ((65536 * 8.0f * CONF_SERCOM_3_USART_BAUD) / CONF_GCLK_SERCOM3_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_3_USART_SAMPR == 3 +#ifndef CONF_SERCOM_3_USART_BAUD_RATE +#define CONF_SERCOM_3_USART_BAUD_RATE \ + ((CONF_GCLK_SERCOM3_CORE_FREQUENCY) / (CONF_SERCOM_3_USART_BAUD * 8)) - (CONF_SERCOM_3_USART_FRACTIONAL / 8) +#endif +#ifndef CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_3_USART_SAMPR == 4 +#ifndef CONF_SERCOM_3_USART_BAUD_RATE +#define CONF_SERCOM_3_USART_BAUD_RATE \ + 65536 - ((65536 * 3.0f * CONF_SERCOM_3_USART_BAUD) / CONF_GCLK_SERCOM3_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#endif + +#include + +// Enable configuration of module +#ifndef CONF_SERCOM_5_SPI_ENABLE +#define CONF_SERCOM_5_SPI_ENABLE 1 +#endif + +// Set module in SPI Master mode +#ifndef CONF_SERCOM_5_SPI_MODE +#define CONF_SERCOM_5_SPI_MODE 0x03 +#endif + +// Basic Configuration + +// Receive buffer enable +// Enable receive buffer to receive data from slave (RXEN) +// spi_master_rx_enable +#ifndef CONF_SERCOM_5_SPI_RXEN +#define CONF_SERCOM_5_SPI_RXEN 0x1 +#endif + +// Character Size +// Bit size for all characters sent over the SPI bus (CHSIZE) +// <0x0=>8 bits +// <0x1=>9 bits +// spi_master_character_size +#ifndef CONF_SERCOM_5_SPI_CHSIZE +#define CONF_SERCOM_5_SPI_CHSIZE 0x0 +#endif +// Baud rate <1-12000000> +// The SPI data transfer rate +// spi_master_baud_rate +#ifndef CONF_SERCOM_5_SPI_BAUD +#define CONF_SERCOM_5_SPI_BAUD 50000 +#endif + +// + +// Advanced Configuration +// spi_master_advanced +#ifndef CONF_SERCOM_5_SPI_ADVANCED +#define CONF_SERCOM_5_SPI_ADVANCED 0 +#endif + +// Dummy byte <0x00-0x1ff> +// spi_master_dummybyte +// Dummy byte used when reading data from the slave without sending any data +#ifndef CONF_SERCOM_5_SPI_DUMMYBYTE +#define CONF_SERCOM_5_SPI_DUMMYBYTE 0x1ff +#endif + +// Data Order +// <0=>MSB first +// <1=>LSB first +// I least significant or most significant bit is shifted out first (DORD) +// spi_master_arch_dord +#ifndef CONF_SERCOM_5_SPI_DORD +#define CONF_SERCOM_5_SPI_DORD 0x0 +#endif + +// Clock Polarity +// <0=>SCK is low when idle +// <1=>SCK is high when idle +// Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL) +// spi_master_arch_cpol +#ifndef CONF_SERCOM_5_SPI_CPOL +#define CONF_SERCOM_5_SPI_CPOL 0x0 +#endif + +// Clock Phase +// <0x0=>Sample input on leading edge +// <0x1=>Sample input on trailing edge +// Determines if input data is sampled on leading or trailing SCK edge. (CPHA) +// spi_master_arch_cpha +#ifndef CONF_SERCOM_5_SPI_CPHA +#define CONF_SERCOM_5_SPI_CPHA 0x0 +#endif + +// Immediate Buffer Overflow Notification +// Controls when OVF is asserted (IBON) +// <0x0=>In data stream +// <0x1=>On buffer overflow +// spi_master_arch_ibon +#ifndef CONF_SERCOM_5_SPI_IBON +#define CONF_SERCOM_5_SPI_IBON 0x0 +#endif + +// Run in stand-by +// Module stays active in stand-by sleep mode. (RUNSTDBY) +// spi_master_arch_runstdby +#ifndef CONF_SERCOM_5_SPI_RUNSTDBY +#define CONF_SERCOM_5_SPI_RUNSTDBY 0x0 +#endif + +// Debug Stop Mode +// Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP) +// <0=>Keep running +// <1=>Halt +// spi_master_arch_dbgstop +#ifndef CONF_SERCOM_5_SPI_DBGSTOP +#define CONF_SERCOM_5_SPI_DBGSTOP 0 +#endif + +// + +// Address mode disabled in master mode +#ifndef CONF_SERCOM_5_SPI_AMODE_EN +#define CONF_SERCOM_5_SPI_AMODE_EN 0 +#endif + +#ifndef CONF_SERCOM_5_SPI_AMODE +#define CONF_SERCOM_5_SPI_AMODE 0 +#endif + +#ifndef CONF_SERCOM_5_SPI_ADDR +#define CONF_SERCOM_5_SPI_ADDR 0 +#endif + +#ifndef CONF_SERCOM_5_SPI_ADDRMASK +#define CONF_SERCOM_5_SPI_ADDRMASK 0 +#endif + +#ifndef CONF_SERCOM_5_SPI_SSDE +#define CONF_SERCOM_5_SPI_SSDE 0 +#endif + +#ifndef CONF_SERCOM_5_SPI_MSSEN +#define CONF_SERCOM_5_SPI_MSSEN 0x0 +#endif + +#ifndef CONF_SERCOM_5_SPI_PLOADEN +#define CONF_SERCOM_5_SPI_PLOADEN 0 +#endif + +// Receive Data Pinout +// <0x0=>PAD[0] +// <0x1=>PAD[1] +// <0x2=>PAD[2] +// <0x3=>PAD[3] +// spi_master_rxpo +#ifndef CONF_SERCOM_5_SPI_RXPO +#define CONF_SERCOM_5_SPI_RXPO 0 +#endif + +// Transmit Data Pinout +// <0x0=>PAD[0,1]_DO_SCK +// <0x1=>PAD[2,3]_DO_SCK +// <0x2=>PAD[3,1]_DO_SCK +// <0x3=>PAD[0,3]_DO_SCK +// spi_master_txpo +#ifndef CONF_SERCOM_5_SPI_TXPO +#define CONF_SERCOM_5_SPI_TXPO 1 +#endif + +// Calculate baud register value from requested baudrate value +#ifndef CONF_SERCOM_5_SPI_BAUD_RATE +#define CONF_SERCOM_5_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM5_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_5_SPI_BAUD)) - 1 +#endif + +// <<< end of configuration section >>> + +#endif // HPL_SERCOM_CONFIG_H diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/Config/peripheral_clk_config.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/Config/peripheral_clk_config.h new file mode 100644 index 00000000..8a271125 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/Config/peripheral_clk_config.h @@ -0,0 +1,273 @@ +/* Auto-generated config file peripheral_clk_config.h */ +#ifndef PERIPHERAL_CLK_CONFIG_H +#define PERIPHERAL_CLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +/** + * \def CONF_CPU_FREQUENCY + * \brief CPU's Clock frequency + */ +#ifndef CONF_CPU_FREQUENCY +#define CONF_CPU_FREQUENCY 4000000 +#endif + +// Core Clock Source +// core_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM1_CORE_SRC +#define CONF_GCLK_SERCOM1_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// Slow Clock Source +// slow_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the slow clock source. +#ifndef CONF_GCLK_SERCOM1_SLOW_SRC +#define CONF_GCLK_SERCOM1_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM1_CORE_FREQUENCY + * \brief SERCOM1's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY +#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 4000000 +#endif + +/** + * \def CONF_GCLK_SERCOM1_SLOW_FREQUENCY + * \brief SERCOM1's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM1_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 32768 +#endif + +// Core Clock Source +// core_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM2_CORE_SRC +#define CONF_GCLK_SERCOM2_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// Slow Clock Source +// slow_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the slow clock source. +#ifndef CONF_GCLK_SERCOM2_SLOW_SRC +#define CONF_GCLK_SERCOM2_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM2_CORE_FREQUENCY + * \brief SERCOM2's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY +#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 4000000 +#endif + +/** + * \def CONF_GCLK_SERCOM2_SLOW_FREQUENCY + * \brief SERCOM2's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM2_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 32768 +#endif + +// Core Clock Source +// core_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM3_CORE_SRC +#define CONF_GCLK_SERCOM3_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// Slow Clock Source +// slow_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the slow clock source. +#ifndef CONF_GCLK_SERCOM3_SLOW_SRC +#define CONF_GCLK_SERCOM3_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM3_CORE_FREQUENCY + * \brief SERCOM3's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM3_CORE_FREQUENCY +#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 4000000 +#endif + +/** + * \def CONF_GCLK_SERCOM3_SLOW_FREQUENCY + * \brief SERCOM3's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM3_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM3_SLOW_FREQUENCY 32768 +#endif + +// Core Clock Source +// core_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM5_CORE_SRC +#define CONF_GCLK_SERCOM5_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// Slow Clock Source +// slow_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the slow clock source. +#ifndef CONF_GCLK_SERCOM5_SLOW_SRC +#define CONF_GCLK_SERCOM5_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK4_Val +#endif + +/** + * \def CONF_GCLK_SERCOM5_CORE_FREQUENCY + * \brief SERCOM5's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM5_CORE_FREQUENCY +#define CONF_GCLK_SERCOM5_CORE_FREQUENCY 4000000 +#endif + +/** + * \def CONF_GCLK_SERCOM5_SLOW_FREQUENCY + * \brief SERCOM5's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM5_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM5_SLOW_FREQUENCY 32768 +#endif + +// <<< end of configuration section >>> + +#endif // PERIPHERAL_CLK_CONFIG_H diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/Debug.xml b/prototype/firmware/EDBG UART erert/EDBG UART erert/Debug.xml new file mode 100644 index 00000000..44681430 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/Debug.xml @@ -0,0 +1,97 @@ + + True + True + True + True + True + + + DEBUG + + + + + %24(PackRepoDir)\ARM\CMSIS\5.4.0\CMSIS\Core\Include\ + ../Config + ../ + ../examples + ../hal/include + ../hal/utils/include + ../hpl/core + ../hpl/dmac + ../hpl/gclk + ../hpl/mclk + ../hpl/osc32kctrl + ../hpl/oscctrl + ../hpl/pm + ../hpl/port + ../hpl/sercom + ../hri + ../stdio_redirect + %24(PackRepoDir)\Atmel\SAML21_DFP\1.2.125\saml21b\include + + + Optimize (-O1) + True + Maximum (-g3) + True + True + + + libm + + + + + %24(ProjectDir)\Device_Startup + + + True + -Tsaml21j18b_flash.ld + + + %24(PackRepoDir)\ARM\CMSIS\5.4.0\CMSIS\Core\Include\ + ../Config + ../ + ../examples + ../hal/include + ../hal/utils/include + ../hpl/core + ../hpl/dmac + ../hpl/gclk + ../hpl/mclk + ../hpl/osc32kctrl + ../hpl/oscctrl + ../hpl/pm + ../hpl/port + ../hpl/sercom + ../hri + ../stdio_redirect + %24(PackRepoDir)\Atmel\SAML21_DFP\1.2.125\saml21b\include + + + Default (-g) + + + %24(PackRepoDir)\ARM\CMSIS\5.4.0\CMSIS\Core\Include\ + ../Config + ../ + ../examples + ../hal/include + ../hal/utils/include + ../hpl/core + ../hpl/dmac + ../hpl/gclk + ../hpl/mclk + ../hpl/osc32kctrl + ../hpl/oscctrl + ../hpl/pm + ../hpl/port + ../hpl/sercom + ../hri + ../stdio_redirect + %24(PackRepoDir)\Atmel\SAML21_DFP\1.2.125\saml21b\include + + + Default (-Wa,-g) + \ No newline at end of file diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/Default.xml b/prototype/firmware/EDBG UART erert/EDBG UART erert/Default.xml new file mode 100644 index 00000000..c2b7fc10 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/Default.xml @@ -0,0 +1,475 @@ + + + + + + + DebugLevel + None + + + IncludePaths + NDEBUG + + + MiscellaneousSettings + -std=gnu99 + + + OptimizationLevel + Optimize for size (-Os) + + + SymbolDefines + NDEBUG + + + SymbolUndefines + + + + Verbose + False + + + WarningsAsErrors + False + + + armgcc.compiler.general.CLanguageExp + True + + + armgcc.compiler.general.ChangeDefaultCharTypeUnsigned + False + + + armgcc.compiler.general.ChangeDefaultBitFieldUnsigned + False + + + armgcc.compiler.general.processormode + + + + armgcc.compiler.preprocessor.DoNotSearchSystemDirectories + False + + + armgcc.compiler.preprocessor.PreprocessOnly + False + + + armgcc.compiler.symbols.Default + + + + armgcc.compiler.directories.DefaultIncludePath + True + + + armgcc.compiler.optimization.OtherFlags + + + + armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection + True + + + armgcc.compiler.optimization.PrepareDataForGarbageCollection + False + + + armgcc.compiler.optimization.EnableUnsafeMatchOptimizations + False + + + armgcc.compiler.optimization.EnableFastMath + False + + + armgcc.compiler.optimization.GeneratePositionIndependentCode + False + + + armgcc.compiler.optimization.EnableLongCalls + True + + + armgcc.compiler.optimization.OtherDebuggingFlags + + + + armgcc.compiler.optimization.GenerateGprofInformation + False + + + armgcc.compiler.optimization.GenerateProfInformation + False + + + armgcc.compiler.warnings.AllWarnings + True + + + armgcc.compiler.warnings.ExtraWarnings + False + + + armgcc.compiler.warnings.Undefined + False + + + armgcc.compiler.warnings.CheckSyntaxOnly + False + + + armgcc.compiler.warnings.Pedantic + False + + + armgcc.compiler.warnings.PedanticWarningsAsErrors + False + + + armgcc.compiler.warnings.InhibitAllWarnings + False + + + armgcc.compiler.miscellaneous.Device + True + + + armgcc.compiler.miscellaneous.CompileOnly + True + + + armgcc.compiler.miscellaneous.SupportAnsiPrograms + False + + + armgcc.compiler.miscellaneous.MakeFileDependent + True + + + + + Libraries + libm + + + LibrarySearchPath + $(ProjectDir)\Device_Startup + + + MiscellaneousSettings + -Tsaml21j18b_flash.ld + + + armgcc.linker.general.DoNotUseStandardStartFiles + False + + + armgcc.linker.general.DoNotUseDefaultLibraries + False + + + armgcc.linker.general.NoStartupOrDefaultLibs + False + + + armgcc.linker.general.OmitAllSymbolInformation + False + + + armgcc.linker.general.NoSharedLibraries + False + + + armgcc.linker.general.GenerateMAPFile + True + + + armgcc.linker.general.UseNewlibNano + False + + + armgcc.linker.general.AdditionalSpecs + None + + + armgcc.linker.optimization.GarbageCollectUnusedSections + True + + + armgcc.linker.optimization.EnableUnsafeMatchOptimizations + False + + + armgcc.linker.optimization.EnableFastMath + False + + + armgcc.linker.optimization.GeneratePositionIndependentCode + False + + + armgcc.linker.memorysettings.Flash + + + + armgcc.linker.memorysettings.Sram + + + + armgcc.linker.memorysettings.ExternalRAM + + + + armgcc.linker.miscellaneous.OtherOptions + + + + armgcc.linker.miscellaneous.OtherObjects + + + + Release + + + + + DebugLevel + Maximum (-g3) + + + IncludePaths + DEBUG + + + MiscellaneousSettings + -std=gnu99 + + + OptimizationLevel + Optimize (-O1) + + + SymbolDefines + DEBUG + + + SymbolUndefines + + + + Verbose + False + + + WarningsAsErrors + False + + + armgcc.compiler.general.CLanguageExp + True + + + armgcc.compiler.general.ChangeDefaultCharTypeUnsigned + False + + + armgcc.compiler.general.ChangeDefaultBitFieldUnsigned + False + + + armgcc.compiler.general.processormode + + + + armgcc.compiler.preprocessor.DoNotSearchSystemDirectories + False + + + armgcc.compiler.preprocessor.PreprocessOnly + False + + + armgcc.compiler.symbols.Default + + + + armgcc.compiler.directories.DefaultIncludePath + True + + + armgcc.compiler.optimization.OtherFlags + + + + armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection + True + + + armgcc.compiler.optimization.PrepareDataForGarbageCollection + False + + + armgcc.compiler.optimization.EnableUnsafeMatchOptimizations + False + + + armgcc.compiler.optimization.EnableFastMath + False + + + armgcc.compiler.optimization.GeneratePositionIndependentCode + False + + + armgcc.compiler.optimization.EnableLongCalls + True + + + armgcc.compiler.optimization.OtherDebuggingFlags + + + + armgcc.compiler.optimization.GenerateGprofInformation + False + + + armgcc.compiler.optimization.GenerateProfInformation + False + + + armgcc.compiler.warnings.AllWarnings + True + + + armgcc.compiler.warnings.ExtraWarnings + False + + + armgcc.compiler.warnings.Undefined + False + + + armgcc.compiler.warnings.CheckSyntaxOnly + False + + + armgcc.compiler.warnings.Pedantic + False + + + armgcc.compiler.warnings.PedanticWarningsAsErrors + False + + + armgcc.compiler.warnings.InhibitAllWarnings + False + + + armgcc.compiler.miscellaneous.Device + True + + + armgcc.compiler.miscellaneous.CompileOnly + True + + + armgcc.compiler.miscellaneous.SupportAnsiPrograms + False + + + armgcc.compiler.miscellaneous.MakeFileDependent + True + + + + + Libraries + libm + + + LibrarySearchPath + $(ProjectDir)\Device_Startup + + + MiscellaneousSettings + -Tsaml21j18b_flash.ld + + + armgcc.linker.general.DoNotUseStandardStartFiles + False + + + armgcc.linker.general.DoNotUseDefaultLibraries + False + + + armgcc.linker.general.NoStartupOrDefaultLibs + False + + + armgcc.linker.general.OmitAllSymbolInformation + False + + + armgcc.linker.general.NoSharedLibraries + False + + + armgcc.linker.general.GenerateMAPFile + True + + + armgcc.linker.general.UseNewlibNano + False + + + armgcc.linker.general.AdditionalSpecs + None + + + armgcc.linker.optimization.GarbageCollectUnusedSections + True + + + armgcc.linker.optimization.EnableUnsafeMatchOptimizations + False + + + armgcc.linker.optimization.EnableFastMath + False + + + armgcc.linker.optimization.GeneratePositionIndependentCode + False + + + armgcc.linker.memorysettings.Flash + + + + armgcc.linker.memorysettings.Sram + + + + armgcc.linker.memorysettings.ExternalRAM + + + + armgcc.linker.miscellaneous.OtherOptions + + + + armgcc.linker.miscellaneous.OtherObjects + + + + Debug + + + \ No newline at end of file diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/Device_Startup/saml21j18b_flash.ld b/prototype/firmware/EDBG UART erert/EDBG UART erert/Device_Startup/saml21j18b_flash.ld new file mode 100644 index 00000000..d890c8c0 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/Device_Startup/saml21j18b_flash.ld @@ -0,0 +1,153 @@ +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAML21J18B + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 + lpram (rwx) : ORIGIN = 0x30000000, LENGTH = 0x00002000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + .lpram (NOLOAD): + { + . = ALIGN(8); + _slpram = .; + *(.lpram .lpram.*); + . = ALIGN(8); + _elpram = .; + } > lpram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/Device_Startup/saml21j18b_sram.ld b/prototype/firmware/EDBG UART erert/EDBG UART erert/Device_Startup/saml21j18b_sram.ld new file mode 100644 index 00000000..05b56d60 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/Device_Startup/saml21j18b_sram.ld @@ -0,0 +1,152 @@ +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAML21J18B + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 + lpram (rwx) : ORIGIN = 0x30000000, LENGTH = 0x00002000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + .lpram (NOLOAD): + { + . = ALIGN(8); + _slpram = .; + *(.lpram .lpram.*); + . = ALIGN(8); + _elpram = .; + } > lpram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/Device_Startup/startup_saml21.c b/prototype/firmware/EDBG UART erert/EDBG UART erert/Device_Startup/startup_saml21.c new file mode 100644 index 00000000..01fab1cc --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/Device_Startup/startup_saml21.c @@ -0,0 +1,257 @@ +/** + * \file + * + * \brief gcc starttup file for SAML21 + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#include "saml21.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M0+ core handlers */ +void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* MCLK, OSC32KCTRL, OSCCTRL, PAC, PM, SUPC, TAL */ +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void NVMCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef ID_USB +void USB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +void EVSYS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef ID_SERCOM4 +void SERCOM4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_SERCOM5 +void SERCOM5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +void TCC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef ID_TC2 +void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_TC3 +void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef ID_ADC +void ADC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_AC +void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_DAC +void DAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_PTC +void PTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_AES +void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_TRNG +void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pvReservedM12 = (void*) (0UL), /* Reserved */ + .pvReservedM11 = (void*) (0UL), /* Reserved */ + .pvReservedM10 = (void*) (0UL), /* Reserved */ + .pvReservedM9 = (void*) (0UL), /* Reserved */ + .pvReservedM8 = (void*) (0UL), /* Reserved */ + .pvReservedM7 = (void*) (0UL), /* Reserved */ + .pvReservedM6 = (void*) (0UL), /* Reserved */ + .pfnSVCall_Handler = (void*) SVCall_Handler, + .pvReservedM4 = (void*) (0UL), /* Reserved */ + .pvReservedM3 = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnSYSTEM_Handler = (void*) SYSTEM_Handler, /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 1 Watchdog Timer */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 2 Real-Time Counter */ + .pfnEIC_Handler = (void*) EIC_Handler, /* 3 External Interrupt Controller */ + .pfnNVMCTRL_Handler = (void*) NVMCTRL_Handler, /* 4 Non-Volatile Memory Controller */ + .pfnDMAC_Handler = (void*) DMAC_Handler, /* 5 Direct Memory Access Controller */ +#ifdef ID_USB + .pfnUSB_Handler = (void*) USB_Handler, /* 6 Universal Serial Bus */ +#else + .pvReserved6 = (void*) (0UL), /* 6 Reserved */ +#endif + .pfnEVSYS_Handler = (void*) EVSYS_Handler, /* 7 Event System Interface */ + .pfnSERCOM0_Handler = (void*) SERCOM0_Handler, /* 8 Serial Communication Interface 0 */ + .pfnSERCOM1_Handler = (void*) SERCOM1_Handler, /* 9 Serial Communication Interface 1 */ + .pfnSERCOM2_Handler = (void*) SERCOM2_Handler, /* 10 Serial Communication Interface 2 */ + .pfnSERCOM3_Handler = (void*) SERCOM3_Handler, /* 11 Serial Communication Interface 3 */ +#ifdef ID_SERCOM4 + .pfnSERCOM4_Handler = (void*) SERCOM4_Handler, /* 12 Serial Communication Interface 4 */ +#else + .pvReserved12 = (void*) (0UL), /* 12 Reserved */ +#endif +#ifdef ID_SERCOM5 + .pfnSERCOM5_Handler = (void*) SERCOM5_Handler, /* 13 Serial Communication Interface 5 */ +#else + .pvReserved13 = (void*) (0UL), /* 13 Reserved */ +#endif + .pfnTCC0_Handler = (void*) TCC0_Handler, /* 14 Timer Counter Control 0 */ + .pfnTCC1_Handler = (void*) TCC1_Handler, /* 15 Timer Counter Control 1 */ + .pfnTCC2_Handler = (void*) TCC2_Handler, /* 16 Timer Counter Control 2 */ + .pfnTC0_Handler = (void*) TC0_Handler, /* 17 Basic Timer Counter 0 */ + .pfnTC1_Handler = (void*) TC1_Handler, /* 18 Basic Timer Counter 1 */ +#ifdef ID_TC2 + .pfnTC2_Handler = (void*) TC2_Handler, /* 19 Basic Timer Counter 2 */ +#else + .pvReserved19 = (void*) (0UL), /* 19 Reserved */ +#endif +#ifdef ID_TC3 + .pfnTC3_Handler = (void*) TC3_Handler, /* 20 Basic Timer Counter 3 */ +#else + .pvReserved20 = (void*) (0UL), /* 20 Reserved */ +#endif + .pfnTC4_Handler = (void*) TC4_Handler, /* 21 Basic Timer Counter 4 */ +#ifdef ID_ADC + .pfnADC_Handler = (void*) ADC_Handler, /* 22 Analog Digital Converter */ +#else + .pvReserved22 = (void*) (0UL), /* 22 Reserved */ +#endif +#ifdef ID_AC + .pfnAC_Handler = (void*) AC_Handler, /* 23 Analog Comparators */ +#else + .pvReserved23 = (void*) (0UL), /* 23 Reserved */ +#endif +#ifdef ID_DAC + .pfnDAC_Handler = (void*) DAC_Handler, /* 24 Digital-to-Analog Converter */ +#else + .pvReserved24 = (void*) (0UL), /* 24 Reserved */ +#endif +#ifdef ID_PTC + .pfnPTC_Handler = (void*) PTC_Handler, /* 25 Peripheral Touch Controller */ +#else + .pvReserved25 = (void*) (0UL), /* 25 Reserved */ +#endif +#ifdef ID_AES + .pfnAES_Handler = (void*) AES_Handler, /* 26 Advanced Encryption Standard */ +#else + .pvReserved26 = (void*) (0UL), /* 26 Reserved */ +#endif +#ifdef ID_TRNG + .pfnTRNG_Handler = (void*) TRNG_Handler, /* 27 True Random Generator */ +#else + .pvReserved27 = (void*) (0UL), /* 27 Reserved */ +#endif + .pvReserved28 = (void*) (0UL) /* 28 Reserved */ +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Overwriting the default value of the NVMCTRL.CTRLB.MANW bit (errata reference 13134) */ + NVMCTRL->CTRLB.bit.MANW = 1; + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/Device_Startup/system_saml21.c b/prototype/firmware/EDBG UART erert/EDBG UART erert/Device_Startup/system_saml21.c new file mode 100644 index 00000000..5ab3e70d --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/Device_Startup/system_saml21.c @@ -0,0 +1,64 @@ +/** + * \file + * + * \brief Low-level initialization functions called upon chip startup. + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#include "saml21.h" + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (4000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/RFM98W.c b/prototype/firmware/EDBG UART erert/EDBG UART erert/RFM98W.c new file mode 100644 index 00000000..247037e7 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/RFM98W.c @@ -0,0 +1,254 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ +#include +#include "RFM98W.h" + + + +struct io_descriptor *RFM98W_io; + + +/* + * Drivers for RFM98W chip + * + * + */ +#include "RFM98W.h" + +/* set up the SPI Port and associated GPIO */ +void RFM98W_Setup(void) +{ + /* Configure Reset */ + gpio_set_pin_direction(RFM98W_RESET_PIN, GPIO_DIRECTION_OUT); + gpio_set_pin_level(RFM98W_RESET_PIN, true); + + /* Configure Chip Select */ + gpio_set_pin_direction(RFM98W_CS_PIN, GPIO_DIRECTION_OUT); + gpio_set_pin_level(RFM98W_CS_PIN, true); + + /* Configure DIO */ + gpio_set_pin_direction(RFM98W_DIO0_PIN, GPIO_DIRECTION_IN); + gpio_set_pin_pull_mode(RFM98W_DIO0_PIN, GPIO_PULL_UP); + + gpio_set_pin_direction(RFM98W_DIO1_PIN, GPIO_DIRECTION_IN); + gpio_set_pin_pull_mode(RFM98W_DIO1_PIN, GPIO_PULL_UP); + + gpio_set_pin_direction(RFM98W_DIO2_PIN, GPIO_DIRECTION_IN); + gpio_set_pin_pull_mode(RFM98W_DIO2_PIN, GPIO_PULL_UP); + + gpio_set_pin_direction(RFM98W_DIO3_PIN, GPIO_DIRECTION_IN); + gpio_set_pin_pull_mode(RFM98W_DIO3_PIN, GPIO_PULL_UP); + + gpio_set_pin_direction(RFM98W_DIO4_PIN, GPIO_DIRECTION_IN); + gpio_set_pin_pull_mode(RFM98W_DIO4_PIN, GPIO_PULL_UP); + + gpio_set_pin_direction(RFM98W_DIO5_PIN, GPIO_DIRECTION_IN); + gpio_set_pin_pull_mode(RFM98W_DIO5_PIN, GPIO_PULL_UP); + + spi_m_sync_get_io_descriptor(&SPI_0, &RFM98W_io); + spi_m_sync_enable(&SPI_0); +} + + +void Set_RFM98W_CS(void) +{ + gpio_set_pin_level(RFM98W_CS_PIN, false); +} + +void Clear_RFM98W_CS(void) +{ + gpio_set_pin_level(RFM98W_CS_PIN, true); +} + + +/* SPI Chip Reset + * */ +void reset_RFM98W(void) +{ + gpio_set_pin_level(RFM98W_RESET_PIN, false); + delay_ms(1); + gpio_set_pin_level(RFM98W_RESET_PIN, true); + delay_ms(10); +} + +/* Write to an RFM98W register */ + +void write_RFM98W_Register(uint8_t reg, uint8_t val) +{ + unsigned char data[2]; + + data[0]= reg | 0x80; + data[1] = val; + + Set_RFM98W_CS(); + + io_write(RFM98W_io, data, 2); + + Clear_RFM98W_CS(); +} + +/* Read from an RFM98W Register */ + +uint8_t read_RFM98W_Register(uint8_t reg) +{ + + uint8_t data = reg & 0x7F; + uint8_t val; + + Set_RFM98W_CS(); + + io_write(RFM98W_io, &data, 1); + io_read(RFM98W_io, &val, 1); + + Clear_RFM98W_CS(); + + return val; +} + + +/* Write to RFM98W FIFO*/ + +void write_RFM98W_FIFO(uint8_t* data, uint8_t length) +{ + uint8_t reg = REG_FIFO | 0x80; + Set_RFM98W_CS(); + + io_write(RFM98W_io, ®, 1); + io_write(RFM98W_io, data, length); + + Clear_RFM98W_CS(); +} + +/* Read from RFM98W FIFO*/ +void read_RFM98W_FIFO(uint8_t *data, uint8_t length) +{ + uint8_t reg = REG_FIFO; + Set_RFM98W_CS(); + + io_write(RFM98W_io, ®, 1); + io_read(RFM98W_io, data, length); + + Clear_RFM98W_CS(); +} + + + + +/* Set value of DIO Pin */ +void set_RFM98W_DIO(enum dio DIO, uint8_t value) +{ + switch (DIO) + { + case DIO0: + gpio_set_pin_level(RFM98W_DIO0_PIN, value); + break; + + case DIO1: + gpio_set_pin_level(RFM98W_DIO1_PIN, value); + break; + + case DIO2: + gpio_set_pin_level(RFM98W_DIO2_PIN, value); + break; + + case DIO3: + gpio_set_pin_level(RFM98W_DIO3_PIN, value); + break; + + case DIO4: + gpio_set_pin_level(RFM98W_DIO4_PIN, value); + break; + + case DIO5: + gpio_set_pin_level(RFM98W_DIO5_PIN, value); + break; + + + } + + +} + +/* Get value of DIO Pin */ +uint8_t get_RFM98W_DIO(enum dio DIO) +{ + + uint8_t retval = 0; + switch (DIO) + { + case DIO0: + retval = gpio_get_pin_level(RFM98W_DIO0_PIN); + break; + + case DIO1: + retval = gpio_get_pin_level(RFM98W_DIO1_PIN); + break; + + case DIO2: + retval = gpio_get_pin_level(RFM98W_DIO2_PIN); + break; + + case DIO3: + retval = gpio_get_pin_level(RFM98W_DIO3_PIN); + break; + + case DIO4: + retval = gpio_get_pin_level(RFM98W_DIO4_PIN); + break; + + case DIO5: + retval = gpio_get_pin_level(RFM98W_DIO5_PIN); + break; + + + } + + return retval; +} + +/* Configure mode of DIO Pin */ + +void configure_RFM98W_DIO(enum dio DIO, enum gpio_direction direction, enum gpio_pull_mode pullup) +{ + switch (DIO) + { + case DIO0: + gpio_set_pin_direction(RFM98W_DIO0_PIN, direction); + gpio_set_pin_pull_mode(RFM98W_DIO0_PIN, pullup); + break; + + case DIO1: + gpio_set_pin_direction(RFM98W_DIO1_PIN, direction); + gpio_set_pin_pull_mode(RFM98W_DIO1_PIN, pullup); + break; + + case DIO2: + gpio_set_pin_direction(RFM98W_DIO2_PIN, direction); + gpio_set_pin_pull_mode(RFM98W_DIO2_PIN, pullup); + break; + + case DIO3: + gpio_set_pin_direction(RFM98W_DIO3_PIN, direction); + gpio_set_pin_pull_mode(RFM98W_DIO3_PIN, pullup); + break; + + case DIO4: + gpio_set_pin_direction(RFM98W_DIO4_PIN, direction); + gpio_set_pin_pull_mode(RFM98W_DIO4_PIN, pullup); + break; + + case DIO5: + gpio_set_pin_direction(RFM98W_DIO5_PIN, direction); + gpio_set_pin_pull_mode(RFM98W_DIO5_PIN, pullup); + break; + + + } + +} + diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/RFM98W.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/RFM98W.h new file mode 100644 index 00000000..a3adc445 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/RFM98W.h @@ -0,0 +1,141 @@ +/* + * Header File for RFM98W. + * + * + */ +#ifndef RFM98W_INCLUDED +#define RFM98W_INCLUDED + + + +/* Pinouts for prototype board on Atsamdl21 xplained */ + +#define RFM98W_CS_PIN PB17 +#define RFM98W_RESET_PIN PB00 +#define RFM98W_DIO0_PIN PB01 +#define RFM98W_DIO1_PIN PB30 +#define RFM98W_DIO2_PIN PA15 +#define RFM98W_DIO3_PIN PB10 +#define RFM98W_DIO4_PIN PB11 +#define RFM98W_DIO5_PIN PA16 + +enum dio {DIO0, DIO1, DIO2, DIO3, DIO4, DIO5}; + + +/* RFM98W registers */ + +#define REG_FIFO 0x00 +#define REG_BITRATE_MSB 0x02 +#define REG_BITRATE_LSB 0x03 +#define REG_FDEV_MSB 0x04 +#define REG_FDEV_LSB 0x05 +#define REG_FRF_MSB 0x06 +#define REG_FRF_MID 0x07 +#define REG_FRF_LSB 0x08 +#define REG_FIFO_ADDR_PTR 0x0D +#define REG_FIFO_TX_BASE_AD 0x0E +#define REG_FIFO_RX_BASE_AD 0x0F +#define REG_RX_NB_BYTES 0x13 +#define REG_OPMODE 0x01 +#define REG_FIFO_RX_CURRENT_ADDR 0x10 +#define REG_IRQ_FLAGS_MASK 0x11 +#define REG_IRQ_FLAGS 0x12 +#define REG_IRQ_FLAGS1 0x3E +#define REG_IRQ_FLAGS2 0x3F +#define REG_PACKET_SNR 0x19 +#define REG_PACKET_RSSI 0x1A +#define REG_CURRENT_RSSI 0x1B +#define REG_DIO_MAPPING_1 0x40 +#define REG_DIO_MAPPING_2 0x41 +#define REG_MODEM_CONFIG 0x1D +#define REG_MODEM_CONFIG2 0x1E +#define REG_MODEM_CONFIG3 0x26 +#define REG_PAYLOAD_LENGTH 0x22 +#define REG_HOP_PERIOD 0x24 +#define REG_FREQ_ERROR 0x28 +#define REG_DETECT_OPT 0x31 +#define REG_DETECTION_THRESHOLD 0x37 +#define REG_PREAMBLE_MSB_FSK 0x25 +#define REG_PREAMBLE_LSB_FSK 0x26 +#define REG_SYNC_CONFIG 0x27 +#define REG_PACKET_CONFIG1 0x30 +#define REG_PAYLOAD_LENGTH_FSK 0x32 +#define REG_FIFO_THRESH 0x35 +#define REG_VERSION 0x42 + +// MODES +#define RF98_MODE_RX_CONTINUOUS 0x85 +#define RF98_MODE_TX 0x83 +#define RF98_MODE_SLEEP 0x80 +#define RF98_MODE_STANDBY 0x81 + +#define PAYLOAD_LENGTH 255 + +// Modem Config 1 +#define EXPLICIT_MODE 0x00 +#define IMPLICIT_MODE 0x01 + +#define ERROR_CODING_4_5 0x02 +#define ERROR_CODING_4_6 0x04 +#define ERROR_CODING_4_7 0x06 +#define ERROR_CODING_4_8 0x08 + +#define BANDWIDTH_7K8 0x00 +#define BANDWIDTH_10K4 0x10 +#define BANDWIDTH_15K6 0x20 +#define BANDWIDTH_20K8 0x30 +#define BANDWIDTH_31K25 0x40 +#define BANDWIDTH_41K7 0x50 +#define BANDWIDTH_62K5 0x60 +#define BANDWIDTH_125K 0x70 +#define BANDWIDTH_250K 0x80 +#define BANDWIDTH_500K 0x90 + +// Modem Config 2 + +#define SPREADING_6 0x60 +#define SPREADING_7 0x70 +#define SPREADING_8 0x80 +#define SPREADING_9 0x90 +#define SPREADING_10 0xA0 +#define SPREADING_11 0xB0 +#define SPREADING_12 0xC0 + +#define CRC_OFF 0x00 +#define CRC_ON 0x04 + +// POWER AMPLIFIER CONFIG +#define REG_PA_CONFIG 0x09 +#define PA_MAX_BOOST 0x8F +#define PA_LOW_BOOST 0x81 +#define PA_MED_BOOST 0x8A +#define PA_MAX_UK 0x88 +#define PA_OFF_BOOST 0x00 +#define RFO_MIN 0x00 + +// LOW NOISE AMPLIFIER +#define REG_LNA 0x0C +#define LNA_MAX_GAIN 0x23 // 0010 0011 +#define LNA_OFF_GAIN 0x00 +#define LNA_LOW_GAIN 0xC0 // 1100 0000 + + + +/* Function Prototypes */ + +void RFM98W_Setup(void); +void Set_RFM98W_CS(void); +void Clear_RFM98W_CS(void); +void reset_RFM98W(void); +void write_RFM98W_Register(uint8_t, uint8_t); +uint8_t read_RFM98W_Register(uint8_t ); +void write_RFM98W_FIFO(uint8_t*, uint8_t); +void read_RFM98W_FIFO(uint8_t*, uint8_t); +void set_RFM98W_DIO(enum dio, uint8_t); +uint8_t get_RFM98W_DIO(enum dio); +void configure_RFM98W_DIO(enum dio DIO, enum gpio_direction, enum gpio_pull_mode); + + + + +#endif // RFM98W_INCLUDED \ No newline at end of file diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/Release.xml b/prototype/firmware/EDBG UART erert/EDBG UART erert/Release.xml new file mode 100644 index 00000000..c9f4805f --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/Release.xml @@ -0,0 +1,94 @@ + + True + True + True + True + True + + + NDEBUG + + + + + %24(PackRepoDir)\ARM\CMSIS\5.4.0\CMSIS\Core\Include\ + ../Config + ../ + ../examples + ../hal/include + ../hal/utils/include + ../hpl/core + ../hpl/dmac + ../hpl/gclk + ../hpl/mclk + ../hpl/osc32kctrl + ../hpl/oscctrl + ../hpl/pm + ../hpl/port + ../hpl/sercom + ../hri + ../stdio_redirect + %24(PackRepoDir)\Atmel\SAML21_DFP\1.2.125\saml21b\include + + + Optimize for size (-Os) + True + True + True + + + libm + + + + + %24(ProjectDir)\Device_Startup + + + True + -Tsaml21j18b_flash.ld + + + %24(PackRepoDir)\ARM\CMSIS\5.4.0\CMSIS\Core\Include\ + ../Config + ../ + ../examples + ../hal/include + ../hal/utils/include + ../hpl/core + ../hpl/dmac + ../hpl/gclk + ../hpl/mclk + ../hpl/osc32kctrl + ../hpl/oscctrl + ../hpl/pm + ../hpl/port + ../hpl/sercom + ../hri + ../stdio_redirect + %24(PackRepoDir)\Atmel\SAML21_DFP\1.2.125\saml21b\include + + + + + %24(PackRepoDir)\ARM\CMSIS\5.4.0\CMSIS\Core\Include\ + ../Config + ../ + ../examples + ../hal/include + ../hal/utils/include + ../hpl/core + ../hpl/dmac + ../hpl/gclk + ../hpl/mclk + ../hpl/osc32kctrl + ../hpl/oscctrl + ../hpl/pm + ../hpl/port + ../hpl/sercom + ../hri + ../stdio_redirect + %24(PackRepoDir)\Atmel\SAML21_DFP\1.2.125\saml21b\include + + + \ No newline at end of file diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/atmel_start.c b/prototype/firmware/EDBG UART erert/EDBG UART erert/atmel_start.c new file mode 100644 index 00000000..79f252ae --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/atmel_start.c @@ -0,0 +1,9 @@ +#include + +/** + * Initializes MCU, drivers and middleware in the project + **/ +void atmel_start_init(void) +{ + system_init(); +} diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/atmel_start.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/atmel_start.h new file mode 100644 index 00000000..0de62f52 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/atmel_start.h @@ -0,0 +1,18 @@ +#ifndef ATMEL_START_H_INCLUDED +#define ATMEL_START_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include "driver_init.h" + +/** + * Initializes MCU, drivers and middleware in the project + **/ +void atmel_start_init(void); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/atmel_start_pins.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/atmel_start_pins.h new file mode 100644 index 00000000..86a5d447 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/atmel_start_pins.h @@ -0,0 +1,47 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ +#ifndef ATMEL_START_PINS_H_INCLUDED +#define ATMEL_START_PINS_H_INCLUDED + +#include + +// SAML21 has 9 pin functions + +#define GPIO_PIN_FUNCTION_A 0 +#define GPIO_PIN_FUNCTION_B 1 +#define GPIO_PIN_FUNCTION_C 2 +#define GPIO_PIN_FUNCTION_D 3 +#define GPIO_PIN_FUNCTION_E 4 +#define GPIO_PIN_FUNCTION_F 5 +#define GPIO_PIN_FUNCTION_G 6 +#define GPIO_PIN_FUNCTION_H 7 +#define GPIO_PIN_FUNCTION_I 8 + +#define PA08 GPIO(GPIO_PORTA, 8) +#define PA09 GPIO(GPIO_PORTA, 9) +#define PA18 GPIO(GPIO_PORTA, 18) +#define PA19 GPIO(GPIO_PORTA, 19) +#define PA22 GPIO(GPIO_PORTA, 22) +#define PA23 GPIO(GPIO_PORTA, 23) +#define LED0 GPIO(GPIO_PORTB, 10) +#define PB16 GPIO(GPIO_PORTB, 16) +#define PB22 GPIO(GPIO_PORTB, 22) +#define PB23 GPIO(GPIO_PORTB, 23) + + +/* GPIO Pins */ +#define PA15 GPIO(GPIO_PORTA, 15) +#define PA16 GPIO(GPIO_PORTA, 16) +#define PB00 GPIO(GPIO_PORTB, 00) +#define PB01 GPIO(GPIO_PORTB, 01) +#define PB10 GPIO(GPIO_PORTB, 10) +#define PB11 GPIO(GPIO_PORTB, 11) +#define PB17 GPIO(GPIO_PORTB, 17) +#define PB30 GPIO(GPIO_PORTB, 30) + +#endif // ATMEL_START_PINS_H_INCLUDED diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/driver_init.c b/prototype/firmware/EDBG UART erert/EDBG UART erert/driver_init.c new file mode 100644 index 00000000..8be2f1ed --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/driver_init.c @@ -0,0 +1,188 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ + +#include "driver_init.h" +#include +#include +#include + +struct spi_m_sync_descriptor SPI_0; + +struct usart_sync_descriptor USART_0; + +struct i2c_m_sync_desc I2C_0; + +struct usart_sync_descriptor EDBG_COM_1; + +void USART_0_PORT_init(void) +{ + + gpio_set_pin_function(PA18, PINMUX_PA18C_SERCOM1_PAD2); + + gpio_set_pin_function(PA19, PINMUX_PA19C_SERCOM1_PAD3); +} + +void USART_0_CLOCK_init(void) +{ + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM1_GCLK_ID_CORE, CONF_GCLK_SERCOM1_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM1_GCLK_ID_SLOW, CONF_GCLK_SERCOM1_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + + hri_mclk_set_APBCMASK_SERCOM1_bit(MCLK); +} + +void USART_0_init(void) +{ + USART_0_CLOCK_init(); + usart_sync_init(&USART_0, SERCOM1, (void *)NULL); + USART_0_PORT_init(); +} + +void I2C_0_PORT_init(void) +{ + + gpio_set_pin_pull_mode(PA08, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PA08, PINMUX_PA08D_SERCOM2_PAD0); + + gpio_set_pin_pull_mode(PA09, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PA09, PINMUX_PA09D_SERCOM2_PAD1); +} + +void I2C_0_CLOCK_init(void) +{ + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_SLOW, CONF_GCLK_SERCOM2_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + + hri_mclk_set_APBCMASK_SERCOM2_bit(MCLK); +} + +void I2C_0_init(void) +{ + I2C_0_CLOCK_init(); + i2c_m_sync_init(&I2C_0, SERCOM2); + I2C_0_PORT_init(); +} + +void EDBG_COM_1_PORT_init(void) +{ + + gpio_set_pin_function(PA22, PINMUX_PA22C_SERCOM3_PAD0); + + gpio_set_pin_function(PA23, PINMUX_PA23C_SERCOM3_PAD1); +} + +void EDBG_COM_1_CLOCK_init(void) +{ + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM3_GCLK_ID_CORE, CONF_GCLK_SERCOM3_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM3_GCLK_ID_SLOW, CONF_GCLK_SERCOM3_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + + hri_mclk_set_APBCMASK_SERCOM3_bit(MCLK); +} + +void EDBG_COM_1_init(void) +{ + EDBG_COM_1_CLOCK_init(); + usart_sync_init(&EDBG_COM_1, SERCOM3, (void *)NULL); + EDBG_COM_1_PORT_init(); +} + +void SPI_0_PORT_init(void) +{ + + // Set pin direction to input + gpio_set_pin_direction(PB16, GPIO_DIRECTION_IN); + + gpio_set_pin_pull_mode(PB16, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PB16, PINMUX_PB16C_SERCOM5_PAD0); + + gpio_set_pin_level(PB22, + // Initial level + // pad_initial_level + // Low + // High + false); + + // Set pin direction to output + gpio_set_pin_direction(PB22, GPIO_DIRECTION_OUT); + + gpio_set_pin_function(PB22, PINMUX_PB22D_SERCOM5_PAD2); + + gpio_set_pin_level(PB23, + // Initial level + // pad_initial_level + // Low + // High + false); + + // Set pin direction to output + gpio_set_pin_direction(PB23, GPIO_DIRECTION_OUT); + + gpio_set_pin_function(PB23, PINMUX_PB23D_SERCOM5_PAD3); +} + +void SPI_0_CLOCK_init(void) +{ + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM5_GCLK_ID_CORE, CONF_GCLK_SERCOM5_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM5_GCLK_ID_SLOW, CONF_GCLK_SERCOM5_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + + hri_mclk_set_APBDMASK_SERCOM5_bit(MCLK); +} + +void SPI_0_init(void) +{ + SPI_0_CLOCK_init(); + spi_m_sync_init(&SPI_0, SERCOM5); + SPI_0_PORT_init(); +} + +void system_init(void) +{ + init_mcu(); + + // GPIO on PB10 + + gpio_set_pin_level(LED0, + // Initial level + // pad_initial_level + // Low + // High + true); + + // Set pin direction to output + gpio_set_pin_direction(LED0, GPIO_DIRECTION_OUT); + + gpio_set_pin_function(LED0, GPIO_PIN_FUNCTION_OFF); + + USART_0_init(); + + I2C_0_init(); + + EDBG_COM_1_init(); + + SPI_0_init(); +} diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/driver_init.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/driver_init.h new file mode 100644 index 00000000..117670b5 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/driver_init.h @@ -0,0 +1,63 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ +#ifndef DRIVER_INIT_INCLUDED +#define DRIVER_INIT_INCLUDED + +#include "atmel_start_pins.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include +#include + +extern struct usart_sync_descriptor USART_0; + +extern struct i2c_m_sync_desc I2C_0; + +extern struct usart_sync_descriptor EDBG_COM_1; +extern struct spi_m_sync_descriptor SPI_0; + +void USART_0_PORT_init(void); +void USART_0_CLOCK_init(void); +void USART_0_init(void); + +void I2C_0_CLOCK_init(void); +void I2C_0_init(void); +void I2C_0_PORT_init(void); + +void EDBG_COM_1_PORT_init(void); +void EDBG_COM_1_CLOCK_init(void); +void EDBG_COM_1_init(void); + +void SPI_0_PORT_init(void); +void SPI_0_CLOCK_init(void); +void SPI_0_init(void); + +/** + * \brief Perform system initialization, initialize pins and clocks for + * peripherals + */ +void system_init(void); + +#ifdef __cplusplus +} +#endif +#endif // DRIVER_INIT_INCLUDED diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/examples/driver_examples.c b/prototype/firmware/EDBG UART erert/EDBG UART erert/examples/driver_examples.c new file mode 100644 index 00000000..9d5c76b9 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/examples/driver_examples.c @@ -0,0 +1,59 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ + +#include "driver_examples.h" +#include "driver_init.h" +#include "utils.h" + +/** + * Example of using USART_0 to write "Hello World" using the IO abstraction. + */ +void USART_0_example(void) +{ + struct io_descriptor *io; + usart_sync_get_io_descriptor(&USART_0, &io); + usart_sync_enable(&USART_0); + + io_write(io, (uint8_t *)"Hello World!", 12); +} + +void I2C_0_example(void) +{ + struct io_descriptor *I2C_0_io; + + i2c_m_sync_get_io_descriptor(&I2C_0, &I2C_0_io); + i2c_m_sync_enable(&I2C_0); + i2c_m_sync_set_slaveaddr(&I2C_0, 0x12, I2C_M_SEVEN); + io_write(I2C_0_io, (uint8_t *)"Hello World!", 12); +} + +/** + * Example of using EDBG_COM_1 to write "Hello World" using the IO abstraction. + */ +void EDBG_COM_1_example(void) +{ + struct io_descriptor *io; + usart_sync_get_io_descriptor(&EDBG_COM_1, &io); + usart_sync_enable(&EDBG_COM_1); + + io_write(io, (uint8_t *)"Hello World!", 12); +} + +/** + * Example of using SPI_0 to write "Hello World" using the IO abstraction. + */ +static uint8_t example_SPI_0[12] = "Hello World!"; + +void SPI_0_example(void) +{ + struct io_descriptor *io; + spi_m_sync_get_io_descriptor(&SPI_0, &io); + + spi_m_sync_enable(&SPI_0); + io_write(io, example_SPI_0, 12); +} diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/examples/driver_examples.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/examples/driver_examples.h new file mode 100644 index 00000000..1460d961 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/examples/driver_examples.h @@ -0,0 +1,24 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ +#ifndef DRIVER_EXAMPLES_H_INCLUDED +#define DRIVER_EXAMPLES_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +void USART_0_example(void); + +void I2C_0_example(void); + +void EDBG_COM_1_example(void); + +#ifdef __cplusplus +} +#endif +#endif // DRIVER_EXAMPLES_H_INCLUDED diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/fix.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/fix.h new file mode 100644 index 00000000..3b8e75eb --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/fix.h @@ -0,0 +1,26 @@ +#ifndef FIX_H_ +#define FIX_H_ + +#include + +/* convert decimal degrees to degrees in uBlox output format (scaled by 10^7) */ +#define COORD_UBX(x) ((int32_t) (x * 10000000.0f)) + +struct gps_fix { + uint8_t type; /* type of fix (validity) */ + uint8_t num_svs; /* number of satellites used for solution, range 0 .. 19 */ + uint16_t year; /* year, range 0 to 65535 */ + uint8_t month; /* month, range 1 to 12 */ + uint8_t day; /* day, range 1 to 31 */ + uint8_t hour; /* hour, range 0 to 23 */ + uint8_t min; /* minute, range 0 to 59 */ + uint8_t sec; /* second, range 0 to 59 */ + int32_t lat; /* latitude in deg * 10^7, range -90 .. +90 * 10^7 */ + int32_t lon; /* longitude in deg * 10^7, range -180 .. +180 * 10^7 */ + uint16_t alt; /* altitude in m, range 0m, up to ~40000m, clamped */ + uint16_t voltage_radio; /* voltage in mV, range 0 .. 3300mV */ + uint16_t op_status; /* Operation Status Word */ + int16_t temp_BME280; /* tracker interval temperature in °C, range -100 .. 100 */ +}; + +#endif \ No newline at end of file diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/gps.c b/prototype/firmware/EDBG UART erert/EDBG UART erert/gps.c new file mode 100644 index 00000000..841da96e --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/gps.c @@ -0,0 +1,492 @@ +/* + * gps.c + * + * Created: 10 May 2019 21:04:59 + * Author: Medad Newman + */ +/* + * Functions for the UBLOX 8 GPS + * for Pico Balloon Tracker using HC12 radio module and GPS + * HC12 Module with STM8S003F3 processor and silabs Si4463 Radio + * + * Derived Work Copyright (c) 2018 Imperial College Space Society + * From original work Copyright (C) 2014 Richard Meadows + * Also derived from https://github.com/thasti/utrak + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + + +#include "gps.h" +#include +#include "fix.h" +#include "atmel_start.h" + + + + + +const int wakeup_char = 0xFF; +/* + * gps_transmit_string + * + * transmits a command to the GPS + */ +void UART_send_buffer(char *cmd, uint8_t length) { + + io_write(&USART_0.io, cmd, length); +} + + +/* + +*/ +uint8_t SERCOM_USART_read_byte(uint32_t * timeout) +{ + uint8_t data; + uint32_t _timeout = *timeout; + + while(!(SERCOM1->USART.INTFLAG.bit.RXC) && _timeout) _timeout--; // This flag is set when there are unread data in DATA. + + if(!_timeout) // byte reception timed out + { + *timeout = 0; // inform about timing out + return 0; + } + + data = SERCOM1->USART.DATA.reg; // Reading DATA will return the contents of the Receive Data register. + + return data; // return received byte +} + + + +/* + * gps_receive_ack + * + * waits for transmission of an ACK/NAK message from the GPS. + * + * returns 1 if ACK was received, 0 if NAK was received or a timeout occured + * + */ +uint8_t gps_receive_ack(uint8_t class_id, uint8_t msg_id) { + + + int match_count = 0; + int msg_ack = 0; + char rx_byte; + + char ack[] = {0xB5, 0x62, 0x05, 0x01, 0x02, 0x00, 0x00, 0x00}; + char nak[] = {0xB5, 0x62, 0x05, 0x00, 0x02, 0x00, 0x00, 0x00}; + ack[6] = class_id; + nak[6] = class_id; + ack[7] = msg_id; + nak[7] = msg_id; + uint32_t _timeout = 230000; // set individually for every message, ~26 instructions per 1 timeout + + + + //io_write(&EDBG_COM_1, (uint8_t *)"Hello World!", 12); + + /* runs until ACK/NAK packet is received, or a timeout.*/ + while(1) { + // read rx_byte + rx_byte = SERCOM_USART_read_byte(&_timeout); + if(!_timeout) { + return 0; + } // times out if first response byte doesn't show up in time + + + if (rx_byte == ack[match_count] || rx_byte == nak[match_count]) { + + if (match_count == 3) { /* test ACK/NAK byte */ + if (rx_byte == ack[match_count]) { + msg_ack = 1; + } + else { + msg_ack = 0; + } + } + + if (match_count == 7) { + return msg_ack; + } + + match_count++; + } + else { + match_count = 0; + } + } + +} + +/* + * gps_disable_nmea_output + * + * disables all NMEA messages to be output from the GPS. + * even though the parser can cope with NMEA messages and ignores them, it + * may save power to disable them completely. + * + * returns if ACKed by GPS + * + */ +uint8_t gps_disable_nmea_output(void) { + char nonmea[] = { + 0xB5, 0x62, 0x06, 0x00, 20, 0x00, /* UBX-CFG-PRT */ + 0x01, 0x00, 0x00, 0x00, /* UART1, reserved, no TX ready */ + 0xe0, 0x08, 0x00, 0x00, /* UART mode (8N1) */ + 0x80, 0x25, 0x00, 0x00, /* UART baud rate (9600) */ + 0x01, 0x00, /* input protocols (uBx only) */ + 0x01, 0x00, /* output protocols (uBx only) */ + 0x00, 0x00, /* flags */ + 0x00, 0x00, /* reserved */ + 0xaa, 0x79 /* checksum */ + }; + + UART_send_buffer(nonmea, sizeof(nonmea)); + return gps_receive_ack(0x06, 0x00); +} + + +/* + * gps_cfg_reset + * + * Resets the GPS to its default configuration + * + * returns if ACKed by GPS + * + */ +uint8_t gps_cfg_reset(void) { + char gps_cfg_reset_msg[] = { + + 0xB5, 0x62, 0x06, 0x09, 0x0D, 0x00, /* UBX-CFG-CFG */ + 0xFF, 0xFF, 0x00, 0x00, /* clearMask */ + 0x00, 0x00, 0x00, 0x00, /* saveMask */ + 0xFF, 0xFF, 0x00, 0x00, /* loadMask */ + 0x03, /* deviceMask */ + 0x1B, 0x9A /* checksum */ + }; + + UART_send_buffer(gps_cfg_reset_msg, sizeof(gps_cfg_reset_msg)); + return gps_receive_ack(0x06, 0x09); +} + + + +/* + * gps_receive_payload + * + * retrieves the payload of a packet with a given class and message-id with the retrieved length. + * the caller has to ensure suitable buffer length! + * + * returns the length of the payload + * + */ +uint16_t gps_receive_payload(uint8_t class_id, uint8_t msg_id, unsigned char *payload) { + uint8_t rx_byte; + enum {UBX_A, UBX_B, CLASSID, MSGID, LEN_A, LEN_B, PAYLOAD} state = UBX_A; + uint16_t payload_cnt = 0; + uint16_t payload_len = 0; + uint32_t _timeout = 230000; // // 1.5s timeout + + while(1) { + + rx_byte = SERCOM_USART_read_byte(&_timeout); + if(!_timeout) { + return 0; + } // times out if first response byte doesn't show up in time + + switch (state) { + case UBX_A: + if (rx_byte == 0xB5) state = UBX_B; + else state = UBX_A; + break; + case UBX_B: + if (rx_byte == 0x62) state = CLASSID; + else state = UBX_A; + break; + case CLASSID: + if (rx_byte == class_id)state = MSGID; + else state = UBX_A; + break; + case MSGID: + if (rx_byte == msg_id) state = LEN_A; + else state = UBX_A; + break; + case LEN_A: + payload_len = rx_byte; + state = LEN_B; + break; + case LEN_B: + payload_len |= ((uint16_t)rx_byte << 8); + state = PAYLOAD; + break; + case PAYLOAD: + payload[payload_cnt] = rx_byte; + payload_cnt++; + if (payload_cnt == payload_len) + return payload_len; + break; + default: + state = UBX_A; + } + } +} + + +/* + * gps_get_fix + * + * retrieves a GPS fix from the module. if validity flag is not set, date/time and position/altitude are + * assumed not to be reliable! + * + * argument is call by reference to avoid large stack allocations + * + */ +uint8_t gps_get_fix(struct gps_fix *fix) { + static uint8_t response[92]; /* PVT response length is 92 bytes */ + /* UBX-NAV-PVT + * Section 33.17.14 in the Ublox M8Q reference manual + */ + char pvt[] = {0xB5, 0x62, 0x01, 0x07, 0x00, 0x00, 0x08, 0x19}; + int32_t alt_tmp; + + /* wake up from sleep */ + gps_wake_up(); + + + /* request position */ + UART_send_buffer(pvt, sizeof(pvt)); + if(gps_receive_payload(0x01, 0x07, response) == 0) return 0; + + // the mapping is found in the reference manual for M8 series gps modules. Section for UBX-NAV-PVT (0x01 0x07) + fix->num_svs = response[23]; + fix->type = response[20]; + fix->year = response[4] + (response[5] << 8); + fix->month = response[6]; + fix->day = response[7]; + fix->hour = response[8]; + fix->min = response[9]; + fix->sec = response[10]; + fix->lat = (int32_t) ( + (uint32_t)(response[28]) + ((uint32_t)(response[29]) << 8) + ((uint32_t)(response[30]) << 16) + ((uint32_t)(response[31]) << 24) + ); + fix->lon = (int32_t) ( + (uint32_t)(response[24]) + ((uint32_t)(response[25]) << 8) + ((uint32_t)(response[26]) << 16) + ((uint32_t)(response[27]) << 24) + ); + alt_tmp = (((int32_t) + ((uint32_t)(response[36]) + ((uint32_t)(response[37]) << 8) + ((uint32_t)(response[38]) << 16) + ((uint32_t)(response[39]) << 24)) + ) / 1000); + if (alt_tmp <= 0) { + fix->alt = 1; + } else if (alt_tmp > 50000) { + fix->alt = 50000; + } else { + fix->alt = (uint16_t) alt_tmp; + } + return 1; + +} + + + +/* + * gps wake up by sending an 0xFF to uart pin + */ +uint8_t gps_wake_up(void) { + + /* wake up from sleep. Send 0xFF */ + io_write(&USART_0.io, 0xFF, 1); + gps_startup_delay(); + + return 1; + +} + + +/* + * gps_set_gps_only + * + * tells the uBlox to only use the GPS satellites + * + * returns if ACKed by GPS + * + */ +uint8_t gps_set_gps_only(void) { + + char gpsonly[] = { + 0xB5,0x62,0x06,0x3E,0x3C,0x00, /* UBX-CFG-GNSS */ + 0x00,0x00,0x20,0x07, /* use 32 channels, 7 configs following */ + 0x00,0x08,0x10,0x00,0x01,0x00,0x01,0x01, /* GPS enable */ + 0x01,0x01,0x03,0x00,0x00,0x00,0x01,0x01, /* SBAS disable */ + 0x02,0x04,0x08,0x00,0x00,0x00,0x01,0x01, /* Galileo disable */ + 0x03,0x08,0x10,0x00,0x00,0x00,0x01,0x01, /* Beidou disable */ + 0x04,0x00,0x08,0x00,0x00,0x00,0x01,0x01, /* IMES disable */ + 0x05,0x00,0x03,0x00,0x01,0x00,0x01,0x01, /* QZSS enable */ + 0x06,0x08,0x0E,0x00,0x00,0x00,0x01,0x01, /* GLONASS disable */ + 0x2D,0x59 /* checksum */ + }; + +// char gpsonly[] = { +// 0xB5,0x62,0x06,0x3E,0x3C,0x00, /* UBX-CFG-GNSS */ +// 0x00,0x00,0x20,0x07, /* use 32 channels, 7 configs following */ +// 0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x01, /* GPS enable */ +// 0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01, /* SBAS disable */ +// 0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x01, /* Galileo disable */ +// 0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x01, /* Beidou disable */ +// 0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x01, /* IMES disable */ +// 0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x01, /* QZSS disable */ +// 0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x01, /* GLONASS disable */ +// 0xC4,0xBC /* checksum */ +// }; + + UART_send_buffer(gpsonly, sizeof(gpsonly)); + return gps_receive_ack(0x06, 0x3E); +} + +/* + * gps_set_airborne_model + * + * tells the GPS to use the airborne positioning model. Should be used to + * get stable lock up to 50km altitude + * + * working uBlox MAX-M8Q + * + * returns if ACKed by GPS + * + */ +uint8_t gps_set_airborne_model(void) { + char model6[] = { + 0xB5, 0x62, 0x06, 0x24, 0x24, 0x00, /* UBX-CFG-NAV5 */ + 0xFF, 0xFF, /* parameter bitmask */ + 0x06, /* dynamic model */ + 0x03, /* fix mode */ + 0x00, 0x00, 0x00, 0x00, /* 2D fix altitude */ + 0x10, 0x27, 0x00, 0x00, /* 2D fix altitude variance */ + 0x05, /* minimum elevation */ + 0x00, /* reserved */ + 0xFA, 0x00, /* position DOP */ + 0xFA, 0x00, /* time DOP */ + 0x64, 0x00, /* position accuracy */ + 0x2C, 0x01, /* time accuracy */ + 0x00, /* static hold threshold */ + 0x3C, /* DGPS timeout */ + 0x00, /* min. SVs above C/No thresh */ + 0x00, /* C/No threshold */ + 0x00, 0x00, /* reserved */ + 0xc8, 0x00, /* static hold max. distance */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* reserved */ + 0x1a, 0x28 /* checksum */ + }; + + UART_send_buffer(model6, sizeof(model6)); + return gps_receive_ack(0x06, 0x24); +} + +/* + * gps_set_power_save + * + * enables cyclic tracking on the uBlox M8Q + * + * returns if ACKed by GPS + * + */ +uint8_t gps_set_power_save(void) { + /* All the config options are in section 33.10.21.1 Extended Power + * Management configuration of the UBLOX documentation + * This section is perhaps the most important in saveing power + * through software settings + * This config uses the on/off-mode, not the cyclic power save mode */ + + /* put the tracker to sleep forever until I manualy wake it up */ + char powersave[]= { + 0xB5,0x62,0x06,0x3B,0x2C,0x00, /* UBX-CFG-PM2 */ + 0x01,0x06,0x01,0x00, /* v1, reserved 1..3 */ + 0x0E,0x90,0x40,0x01, /* on/off-mode, update ephemeris */ + 0x00,0x00,0x00,0x00, /* update period, ms, 0ms */ + 0x00,0x00,0x00,0x00, /* search period, ms, 0ms */ + 0x00,0x00,0x00,0x00, /* grid offset, ms, 0ms */ + 0x00,0x00, /* on-time after first fix */ + 0x01,0x00, /* minimum acquisition time */ + 0x2C,0x01,0x00,0x00, + 0x4F,0xC1,0x03,0x00, + 0x87,0x02,0x00,0x00, + 0xFF,0x00,0x00,0x00, + 0x64,0x40,0x01,0x00, + 0xC2,0xB0 + }; + + UART_send_buffer(powersave, sizeof(powersave)); + return gps_receive_ack(0x06, 0x3B); +} + +/* + * gps_power_save + * + * enables or disables the power save mode (which was configured before) + */ +uint8_t gps_power_save(int on) { + char recvmgmt[] = { + 0xB5, 0x62, 0x06, 0x11, 2, 0, /* UBX-CFG-RXM */ + 0x08, 0x01, /* reserved, enable power save mode */ + 0x22, 0x92 + }; + if (!on) { + recvmgmt[7] = 0x00; /* continuous mode */ + recvmgmt[8] = 0x21; /* new checksum */ + recvmgmt[9] = 0x91; + } + + UART_send_buffer(recvmgmt, sizeof(recvmgmt)); + return gps_receive_ack(0x06, 0x11); +} + +/* + * gps_save_settings + * + * saves the GPS settings to flash. should be done when power save is disabled and all + * settings are configured. + */ +uint8_t gps_save_settings(void) { + char cfg[] = { + 0xB5, 0x62, 0x06, 0x09, 12, 0, /* UBX-CFG-CFG */ + 0x00, 0x00, 0x00, 0x00, /* clear no sections */ + 0x1f, 0x1e, 0x00, 0x00, /* save all sections */ + 0x00, 0x00, 0x00, 0x00, /* load no sections */ + 0x58, 0x59 + }; + + UART_send_buffer(cfg, sizeof(cfg)); + return gps_receive_ack(0x06, 0x09); +} + +/* + * gps_startup_delay + * + * waits for the GPS to start up. this value is empirical. + * we could also wait for the startup string + */ +void gps_startup_delay(void) { + /* wait for the GPS to startup */ + delay_ms(1000); + +} + diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/gps.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/gps.h new file mode 100644 index 00000000..8651f258 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/gps.h @@ -0,0 +1,75 @@ +/* + * gps.h + * + * Created: 10 May 2019 21:05:36 + * Author: Medad Newman + */ + + +/* + * Functions for the UBLOX 8 GPS + * + * Derived Work Copyright (c) 2018 Imperial College Space Society + * From original work Copyright (C) 2014 Richard Meadows + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef GPS_H +#define GPS_H + +#include +#include "fix.h" + + + +#define UART_RX_BUFFER_LENGTH 120 +#define UBX_CFG_RETRIES 3 +#define UBX_CFG_TIMEOUT 60000 // timeout +#define UBX_POLL_RETRIES 3 +#define UBX_POLL_TIMEOUT 1000000l // timeout + +#define RX_TIMEOUT_MS 1920 +#define UART_BAUDRATE 96 +//#define test_period 1920 + +void UART_send_buffer(char *cmd, uint8_t length); + +uint8_t gps_set_gps_only(void); +uint8_t gps_disable_nmea_output(void); +uint8_t gps_set_airborne_model(void); +uint8_t gps_set_power_save(void); +uint8_t gps_power_save(int on); +uint8_t gps_save_settings(void); +uint8_t gps_get_fix(struct gps_fix *fix); +uint8_t gps_wake_up(void); +uint8_t gps_cfg_reset(void); + +void gps_startup_delay(void); + + +uint8_t SERCOM_USART_read_byte(uint32_t * timeout); + + + + + + +#endif /* GPS_H */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hal_atomic.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hal_atomic.h new file mode 100644 index 00000000..82151fc5 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hal_atomic.h @@ -0,0 +1,120 @@ +/** + * \file + * + * \brief Critical sections related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_ATOMIC_H_INCLUDED +#define _HAL_ATOMIC_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_helper_atomic + * + *@{ + */ + +/** + * \brief Type for the register holding global interrupt enable flag + */ +typedef uint32_t hal_atomic_t; + +/** + * \brief Helper macro for entering critical sections + * + * This macro is recommended to be used instead of a direct call + * hal_enterCritical() function to enter critical + * sections. No semicolon is required after the macro. + * + * \section atomic_usage Usage Example + * \code + * CRITICAL_SECTION_ENTER() + * Critical code + * CRITICAL_SECTION_LEAVE() + * \endcode + */ +#define CRITICAL_SECTION_ENTER() \ + { \ + volatile hal_atomic_t __atomic; \ + atomic_enter_critical(&__atomic); + +/** + * \brief Helper macro for leaving critical sections + * + * This macro is recommended to be used instead of a direct call + * hal_leaveCritical() function to leave critical + * sections. No semicolon is required after the macro. + */ +#define CRITICAL_SECTION_LEAVE() \ + atomic_leave_critical(&__atomic); \ + } + +/** + * \brief Disable interrupts, enter critical section + * + * Disables global interrupts. Supports nested critical sections, + * so that global interrupts are only re-enabled + * upon leaving the outermost nested critical section. + * + * \param[out] atomic The pointer to a variable to store the value of global + * interrupt enable flag + */ +void atomic_enter_critical(hal_atomic_t volatile *atomic); + +/** + * \brief Exit atomic section + * + * Enables global interrupts. Supports nested critical sections, + * so that global interrupts are only re-enabled + * upon leaving the outermost nested critical section. + * + * \param[in] atomic The pointer to a variable, which stores the latest stored + * value of the global interrupt enable flag + */ +void atomic_leave_critical(hal_atomic_t volatile *atomic); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t atomic_get_version(void); +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_ATOMIC_H_INCLUDED */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hal_delay.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hal_delay.h new file mode 100644 index 00000000..9d4aa5c1 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hal_delay.h @@ -0,0 +1,89 @@ +/** + * \file + * + * \brief HAL delay related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +#ifndef _HAL_DELAY_H_INCLUDED +#define _HAL_DELAY_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_delay Delay Driver + * + *@{ + */ + +/** + * \brief Initialize Delay driver + * + * \param[in] hw The pointer to hardware instance + */ +void delay_init(void *const hw); + +/** + * \brief Perform delay in us + * + * This function performs delay for the given amount of microseconds. + * + * \param[in] us The amount delay in us + */ +void delay_us(const uint16_t us); + +/** + * \brief Perform delay in ms + * + * This function performs delay for the given amount of milliseconds. + * + * \param[in] ms The amount delay in ms + */ +void delay_ms(const uint16_t ms); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t delay_get_version(void); + +/**@}*/ +#ifdef __cplusplus +} +#endif +#endif /* _HAL_DELAY_H_INCLUDED */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hal_gpio.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hal_gpio.h new file mode 100644 index 00000000..fbfa2d4a --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hal_gpio.h @@ -0,0 +1,201 @@ +/** + * \file + * + * \brief Port + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ +#ifndef _HAL_GPIO_INCLUDED_ +#define _HAL_GPIO_INCLUDED_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Set gpio pull mode + * + * Set pin pull mode, non existing pull modes throws an fatal assert + * + * \param[in] pin The pin number for device + * \param[in] pull_mode GPIO_PULL_DOWN = Pull pin low with internal resistor + * GPIO_PULL_UP = Pull pin high with internal resistor + * GPIO_PULL_OFF = Disable pin pull mode + */ +static inline void gpio_set_pin_pull_mode(const uint8_t pin, const enum gpio_pull_mode pull_mode) +{ + _gpio_set_pin_pull_mode((enum gpio_port)GPIO_PORT(pin), pin & 0x1F, pull_mode); +} + +/** + * \brief Set pin function + * + * Select which function a pin will be used for + * + * \param[in] pin The pin number for device + * \param[in] function The pin function is given by a 32-bit wide bitfield + * found in the header files for the device + * + */ +static inline void gpio_set_pin_function(const uint32_t pin, uint32_t function) +{ + _gpio_set_pin_function(pin, function); +} + +/** + * \brief Set port data direction + * + * Select if the pin data direction is input, output or disabled. + * If disabled state is not possible, this function throws an assert. + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to the + * corresponding pin + * \param[in] direction GPIO_DIRECTION_IN = Data direction in + * GPIO_DIRECTION_OUT = Data direction out + * GPIO_DIRECTION_OFF = Disables the pin + * (low power state) + */ +static inline void gpio_set_port_direction(const enum gpio_port port, const uint32_t mask, + const enum gpio_direction direction) +{ + _gpio_set_direction(port, mask, direction); +} + +/** + * \brief Set gpio data direction + * + * Select if the pin data direction is input, output or disabled. + * If disabled state is not possible, this function throws an assert. + * + * \param[in] pin The pin number for device + * \param[in] direction GPIO_DIRECTION_IN = Data direction in + * GPIO_DIRECTION_OUT = Data direction out + * GPIO_DIRECTION_OFF = Disables the pin + * (low power state) + */ +static inline void gpio_set_pin_direction(const uint8_t pin, const enum gpio_direction direction) +{ + _gpio_set_direction((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), direction); +} + +/** + * \brief Set port level + * + * Sets output level on the pins defined by the bit mask + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply port level to the corresponding + * pin + * \param[in] level true = Pin levels set to "high" state + * false = Pin levels set to "low" state + */ +static inline void gpio_set_port_level(const enum gpio_port port, const uint32_t mask, const bool level) +{ + _gpio_set_level(port, mask, level); +} + +/** + * \brief Set gpio level + * + * Sets output level on a pin + * + * \param[in] pin The pin number for device + * \param[in] level true = Pin level set to "high" state + * false = Pin level set to "low" state + */ +static inline void gpio_set_pin_level(const uint8_t pin, const bool level) +{ + _gpio_set_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), level); +} + +/** + * \brief Toggle out level on pins + * + * Toggle the pin levels on pins defined by bit mask + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means toggle pin level to the corresponding + * pin + */ +static inline void gpio_toggle_port_level(const enum gpio_port port, const uint32_t mask) +{ + _gpio_toggle_level(port, mask); +} + +/** + * \brief Toggle output level on pin + * + * Toggle the pin levels on pins defined by bit mask + * + * \param[in] pin The pin number for device + */ +static inline void gpio_toggle_pin_level(const uint8_t pin) +{ + _gpio_toggle_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin)); +} + +/** + * \brief Get input level on pins + * + * Read the input level on pins connected to a port + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + */ +static inline uint32_t gpio_get_port_level(const enum gpio_port port) +{ + return _gpio_get_level(port); +} + +/** + * \brief Get level on pin + * + * Reads the level on pins connected to a port + * + * \param[in] pin The pin number for device + */ +static inline bool gpio_get_pin_level(const uint8_t pin) +{ + return (bool)(_gpio_get_level((enum gpio_port)GPIO_PORT(pin)) & (0x01U << GPIO_PIN(pin))); +} +/** + * \brief Get current driver version + */ +uint32_t gpio_get_version(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hal_i2c_m_sync.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hal_i2c_m_sync.h new file mode 100644 index 00000000..24afd639 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hal_i2c_m_sync.h @@ -0,0 +1,244 @@ +/** + * \file + * + * \brief Sync I2C Hardware Abstraction Layer(HAL) declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_I2C_M_SYNC_H_INCLUDED +#define _HAL_I2C_M_SYNC_H_INCLUDED + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_i2c_master_sync + * + * @{ + */ + +#define I2C_M_MAX_RETRY 1 + +/** + * \brief I2C descriptor structure, embed i2c_device & i2c_interface + */ +struct i2c_m_sync_desc { + struct _i2c_m_sync_device device; + struct io_descriptor io; + uint16_t slave_addr; +}; + +/** + * \brief Initialize synchronous I2C interface + * + * This function initializes the given I/O descriptor to be used as a + * synchronous I2C interface descriptor. + * It checks if the given hardware is not initialized and if the given hardware + * is permitted to be initialized. + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status. + * \retval -1 The passed parameters were invalid or the interface is already initialized + * \retval 0 The initialization is completed successfully + */ +int32_t i2c_m_sync_init(struct i2c_m_sync_desc *i2c, void *hw); + +/** + * \brief Deinitialize I2C interface + * + * This function deinitializes the given I/O descriptor. + * It checks if the given hardware is initialized and if the given hardware is permitted to be deinitialized. + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * + * \return Uninitialization status. + * \retval -1 The passed parameters were invalid or the interface is already deinitialized + * \retval 0 The de-initialization is completed successfully + */ +int32_t i2c_m_sync_deinit(struct i2c_m_sync_desc *i2c); + +/** + * \brief Set the slave device address + * + * This function sets the next transfer target slave I2C device address. + * It takes no effect to any already started access. + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * \param[in] addr The slave address to access + * \param[in] addr_len The slave address length, can be I2C_M_TEN or I2C_M_SEVEN + * + * \return Masked slave address. The mask is a maximum 10-bit address, and 10th + * bit is set if a 10-bit address is used + */ +int32_t i2c_m_sync_set_slaveaddr(struct i2c_m_sync_desc *i2c, int16_t addr, int32_t addr_len); + +/** + * \brief Set baudrate + * + * This function sets the I2C device to the specified baudrate. + * It only takes effect when the hardware is disabled. + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * \param[in] clkrate Unused parameter. Should always be 0 + * \param[in] baudrate The baudrate value set to master + * + * \return Whether successfully set the baudrate + * \retval -1 The passed parameters were invalid or the device is already enabled + * \retval 0 The baudrate set is completed successfully + */ +int32_t i2c_m_sync_set_baudrate(struct i2c_m_sync_desc *i2c, uint32_t clkrate, uint32_t baudrate); + +/** + * \brief Sync version of enable hardware + * + * This function enables the I2C device, and then waits for this enabling operation to be done + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * + * \return Whether successfully enable the device + * \retval -1 The passed parameters were invalid or the device enable failed + * \retval 0 The hardware enabling is completed successfully + */ +int32_t i2c_m_sync_enable(struct i2c_m_sync_desc *i2c); + +/** + * \brief Sync version of disable hardware + * + * This function disables the I2C device and then waits for this disabling operation to be done + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * + * \return Whether successfully disable the device + * \retval -1 The passed parameters were invalid or the device disable failed + * \retval 0 The hardware disabling is completed successfully + */ +int32_t i2c_m_sync_disable(struct i2c_m_sync_desc *i2c); + +/** + * \brief Sync version of write command to I2C slave + * + * This function will write the value to a specified register in the I2C slave device and + * then wait for this operation to be done. + * + * The sequence of this routine is + * sta->address(write)->ack->reg address->ack->resta->address(write)->ack->reg value->nack->stt + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * \param[in] reg The internal address/register of the I2C slave device + * \param[in] buffer The buffer holding data to write to the I2C slave device + * \param[in] length The length (in bytes) to write to the I2C slave device + * + * \return Whether successfully write to the device + * \retval <0 The passed parameters were invalid or write fail + * \retval 0 Writing to register is completed successfully + */ +int32_t i2c_m_sync_cmd_write(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length); + +/** + * \brief Sync version of read register value from I2C slave + * + * This function will read a byte value from a specified register in the I2C slave device and + * then wait for this operation to be done. + * + * The sequence of this routine is + * sta->address(write)->ack->reg address->ack->resta->address(read)->ack->reg value->nack->stt + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * \param[in] reg The internal address/register of the I2C slave device + * \param[in] buffer The buffer to hold the read data from the I2C slave device + * \param[in] length The length (in bytes) to read from the I2C slave device + * + * \return Whether successfully read from the device + * \retval <0 The passed parameters were invalid or read fail + * \retval 0 Reading from register is completed successfully + */ +int32_t i2c_m_sync_cmd_read(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length); + +/** + * \brief Sync version of transfer message to/from the I2C slave + * + * This function will transfer a message between the I2C slave and the master. This function will wait for the operation + * to be done. + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * \param[in] msg An i2c_m_msg struct + * + * \return The status of the operation + * \retval 0 Operation completed successfully + * \retval <0 Operation failed + */ +int32_t i2c_m_sync_transfer(struct i2c_m_sync_desc *const i2c, struct _i2c_m_msg *msg); + +/** + * \brief Sync version of send stop condition on the i2c bus + * + * This function will create a stop condition on the i2c bus to release the bus + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * + * \return The status of the operation + * \retval 0 Operation completed successfully + * \retval <0 Operation failed + */ +int32_t i2c_m_sync_send_stop(struct i2c_m_sync_desc *const i2c); + +/** + * \brief Return I/O descriptor for this I2C instance + * + * This function will return a I/O instance for this I2C driver instance + * + * \param[in] i2c_m_sync_desc An I2C descriptor, which is used to communicate through I2C + * \param[in] io_descriptor A pointer to an I/O descriptor pointer type + * + * \return Error code + * \retval 0 No error detected + * \retval <0 Error code + */ +int32_t i2c_m_sync_get_io_descriptor(struct i2c_m_sync_desc *const i2c, struct io_descriptor **io); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t i2c_m_sync_get_version(void); + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hal_init.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hal_init.h new file mode 100644 index 00000000..d7bc6fe2 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hal_init.h @@ -0,0 +1,72 @@ +/** + * \file + * + * \brief HAL initialization related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_INIT_H_INCLUDED +#define _HAL_INIT_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_helper_init Init Driver + * + *@{ + */ + +/** + * \brief Initialize the hardware abstraction layer + * + * This function calls the various initialization functions. + * Currently the following initialization functions are supported: + * - System clock initialization + */ +static inline void init_mcu(void) +{ + _init_chip(); +} + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t init_get_version(void); + +/**@}*/ +#ifdef __cplusplus +} +#endif +#endif /* _HAL_INIT_H_INCLUDED */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hal_io.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hal_io.h new file mode 100644 index 00000000..f50401d7 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hal_io.h @@ -0,0 +1,110 @@ +/** + * \file + * + * \brief I/O related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_IO_INCLUDED +#define _HAL_IO_INCLUDED + +/** + * \addtogroup doc_driver_hal_helper_io I/O Driver + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief I/O descriptor + * + * The I/O descriptor forward declaration. + */ +struct io_descriptor; + +/** + * \brief I/O write function pointer type + */ +typedef int32_t (*io_write_t)(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); + +/** + * \brief I/O read function pointer type + */ +typedef int32_t (*io_read_t)(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); + +/** + * \brief I/O descriptor + */ +struct io_descriptor { + io_write_t write; /*! The write function pointer. */ + io_read_t read; /*! The read function pointer. */ +}; + +/** + * \brief I/O write interface + * + * This function writes up to \p length of bytes to a given I/O descriptor. + * It returns the number of bytes actually write. + * + * \param[in] descr An I/O descriptor to write + * \param[in] buf The buffer pointer to story the write data + * \param[in] length The number of bytes to write + * + * \return The number of bytes written + */ +int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); + +/** + * \brief I/O read interface + * + * This function reads up to \p length bytes from a given I/O descriptor, and + * stores it in the buffer pointed to by \p buf. It returns the number of bytes + * actually read. + * + * \param[in] descr An I/O descriptor to read + * \param[in] buf The buffer pointer to story the read data + * \param[in] length The number of bytes to read + * + * \return The number of bytes actually read. This number can be less than the + * requested length. E.g., in a driver that uses ring buffer for + * reception, it may depend on the availability of data in the + * ring buffer. + */ +int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HAL_IO_INCLUDED */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hal_sleep.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hal_sleep.h new file mode 100644 index 00000000..b90ef6a5 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hal_sleep.h @@ -0,0 +1,74 @@ +/** + * \file + * + * \brief Sleep related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_SLEEP_H_INCLUDED +#define _HAL_SLEEP_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_helper_sleep + * + *@{ + */ + +/** + * \brief Set the sleep mode of the device and put the MCU to sleep + * + * For an overview of which systems are disabled in sleep for the different + * sleep modes, see the data sheet. + * + * \param[in] mode Sleep mode to use + * + * \return The status of a sleep request + * \retval -1 The requested sleep mode was invalid or not available + * \retval 0 The operation completed successfully, returned after leaving the + * sleep + */ +int sleep(const uint8_t mode); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t sleep_get_version(void); +/**@}*/ +#ifdef __cplusplus +} +#endif +#endif /* _HAL_SLEEP_H_INCLUDED */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hal_spi_m_sync.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hal_spi_m_sync.h new file mode 100644 index 00000000..5d040558 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hal_spi_m_sync.h @@ -0,0 +1,221 @@ +/** + * \file + * + * \brief SPI related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_SPI_M_SYNC_H_INCLUDED +#define _HAL_SPI_M_SYNC_H_INCLUDED + +#include +#include + +/** + * \addtogroup doc_driver_hal_spi_master_sync + * + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** \brief SPI HAL driver struct for polling mode + * + */ +struct spi_m_sync_descriptor { + struct _spi_m_sync_hpl_interface *func; + /** SPI device instance */ + struct _spi_sync_dev dev; + /** I/O read/write */ + struct io_descriptor io; + /** Flags for HAL driver */ + uint16_t flags; +}; + +/** \brief Set the SPI HAL instance function pointer for HPL APIs. + * + * Set SPI HAL instance function pointer for HPL APIs. + * + * \param[in] spi Pointer to the HAL SPI instance. + * \param[in] func Pointer to the HPL api structure. + * + */ +void spi_m_sync_set_func_ptr(struct spi_m_sync_descriptor *spi, void *const func); + +/** \brief Initialize SPI HAL instance and hardware for polling mode + * + * Initialize SPI HAL with polling mode. + * + * \param[in] spi Pointer to the HAL SPI instance. + * \param[in] hw Pointer to the hardware base. + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval ERR_INVALID_DATA Error, initialized. + */ +int32_t spi_m_sync_init(struct spi_m_sync_descriptor *spi, void *const hw); + +/** \brief Deinitialize the SPI HAL instance and hardware + * + * Abort transfer, disable and reset SPI, deinit software. + * + * \param[in] spi Pointer to the HAL SPI instance. + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval <0 Error code. + */ +void spi_m_sync_deinit(struct spi_m_sync_descriptor *spi); + +/** \brief Enable SPI + * + * \param[in] spi Pointer to the HAL SPI instance. + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval <0 Error code. + */ +void spi_m_sync_enable(struct spi_m_sync_descriptor *spi); + +/** \brief Disable SPI + * + * \param[in] spi Pointer to the HAL SPI instance. + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval <0 Error code. + */ +void spi_m_sync_disable(struct spi_m_sync_descriptor *spi); + +/** \brief Set SPI baudrate + * + * Works if SPI is initialized as master, it sets the baudrate. + * + * \param[in] spi Pointer to the HAL SPI instance. + * \param[in] baud_val The target baudrate value + * (see "baudrate calculation" for calculating the value). + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval ERR_BUSY Busy + * \retval ERR_INVALID_ARG The baudrate is not supported. + */ +int32_t spi_m_sync_set_baudrate(struct spi_m_sync_descriptor *spi, const uint32_t baud_val); + +/** \brief Set SPI mode + * + * Set the SPI transfer mode (\ref spi_transfer_mode), + * which controls the clock polarity and clock phase: + * - Mode 0: leading edge is rising edge, data sample on leading edge. + * - Mode 1: leading edge is rising edge, data sample on trailing edge. + * - Mode 2: leading edge is falling edge, data sample on leading edge. + * - Mode 3: leading edge is falling edge, data sample on trailing edge. + * + * \param[in] spi Pointer to the HAL SPI instance. + * \param[in] mode The mode (0~3). + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval ERR_BUSY Busy + * \retval ERR_INVALID_ARG The mode is not supported. + */ +int32_t spi_m_sync_set_mode(struct spi_m_sync_descriptor *spi, const enum spi_transfer_mode mode); + +/** \brief Set SPI transfer character size in number of bits + * + * The character size (\ref spi_char_size) influence the way the data is + * sent/received. + * For char size <= 8-bit, data is stored byte by byte. + * For char size between 9-bit ~ 16-bit, data is stored in 2-byte length. + * Note that the default and recommended char size is 8-bit since it's + * supported by all system. + * + * \param[in] spi Pointer to the HAL SPI instance. + * \param[in] char_size The char size (~16, recommended 8). + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval ERR_BUSY Busy + * \retval ERR_INVALID_ARG The char size is not supported. + */ +int32_t spi_m_sync_set_char_size(struct spi_m_sync_descriptor *spi, const enum spi_char_size char_size); + +/** \brief Set SPI transfer data order + * + * \param[in] spi Pointer to the HAL SPI instance. + * \param[in] dord The data order: send LSB/MSB first. + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval ERR_BUSY Busy + * \retval ERR_INVALID_ARG The data order is not supported. + */ +int32_t spi_m_sync_set_data_order(struct spi_m_sync_descriptor *spi, const enum spi_data_order dord); + +/** \brief Perform the SPI data transfer (TX and RX) in polling way + * + * Activate CS, do TX and RX and deactivate CS. It blocks. + * + * \param[in, out] spi Pointer to the HAL SPI instance. + * \param[in] xfer Pointer to the transfer information (\ref spi_xfer). + * + * \retval size Success. + * \retval >=0 Timeout, with number of characters transferred. + * \retval ERR_BUSY SPI is busy + */ +int32_t spi_m_sync_transfer(struct spi_m_sync_descriptor *spi, const struct spi_xfer *xfer); + +/** + * \brief Return the I/O descriptor for this SPI instance + * + * This function will return an I/O instance for this SPI driver instance. + * + * \param[in] spi An SPI master descriptor, which is used to communicate through + * SPI + * \param[in, out] io A pointer to an I/O descriptor pointer type + * + * \retval ERR_NONE + */ +int32_t spi_m_sync_get_io_descriptor(struct spi_m_sync_descriptor *const spi, struct io_descriptor **io); + +/** \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t spi_m_sync_get_version(void); + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _HAL_SPI_M_SYNC_H_INCLUDED */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hal_usart_sync.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hal_usart_sync.h new file mode 100644 index 00000000..1ef22fc6 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hal_usart_sync.h @@ -0,0 +1,247 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_SYNC_USART_H_INCLUDED +#define _HAL_SYNC_USART_H_INCLUDED + +#include "hal_io.h" +#include + +/** + * \addtogroup doc_driver_hal_usart_sync + * + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Synchronous USART descriptor + */ +struct usart_sync_descriptor { + struct io_descriptor io; + struct _usart_sync_device device; +}; + +/** + * \brief Initialize USART interface + * + * This function initializes the given I/O descriptor to be used + * as USART interface descriptor. + * It checks if the given hardware is not initialized and + * if the given hardware is permitted to be initialized. + * + * \param[out] descr A USART descriptor which is used to communicate via USART + * \param[in] hw The pointer to hardware instance + * \param[in] func The pointer to as set of functions pointers + * + * \return Initialization status. + */ +int32_t usart_sync_init(struct usart_sync_descriptor *const descr, void *const hw, void *const func); + +/** + * \brief Deinitialize USART interface + * + * This function deinitializes the given I/O descriptor. + * It checks if the given hardware is initialized and + * if the given hardware is permitted to be deinitialized. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return De-initialization status. + */ +int32_t usart_sync_deinit(struct usart_sync_descriptor *const descr); + +/** + * \brief Enable USART interface + * + * Enables the USART interface + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return Enabling status. + */ +int32_t usart_sync_enable(struct usart_sync_descriptor *const descr); + +/** + * \brief Disable USART interface + * + * Disables the USART interface + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return Disabling status. + */ +int32_t usart_sync_disable(struct usart_sync_descriptor *const descr); + +/** + * \brief Retrieve I/O descriptor + * + * This function retrieves the I/O descriptor of the given USART descriptor. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[out] io An I/O descriptor to retrieve + * + * \return The status of the I/O descriptor retrieving. + */ +int32_t usart_sync_get_io_descriptor(struct usart_sync_descriptor *const descr, struct io_descriptor **io); + +/** + * \brief Specify action for flow control pins + * + * This function sets the action (or state) for the flow control pins + * if the flow control is enabled. + * It sets the state of flow control pins only if the automatic support of + * the flow control is not supported by the hardware. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] state A state to set the flow control pins + * + * \return The status of flow control action setup. + */ +int32_t usart_sync_set_flow_control(struct usart_sync_descriptor *const descr, + const union usart_flow_control_state state); + +/** + * \brief Set USART baud rate + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] baud_rate A baud rate to set + * + * \return The status of baud rate setting. + */ +int32_t usart_sync_set_baud_rate(struct usart_sync_descriptor *const descr, const uint32_t baud_rate); + +/** + * \brief Set USART data order + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] data_order A data order to set + * + * \return The status of data order setting. + */ +int32_t usart_sync_set_data_order(struct usart_sync_descriptor *const descr, const enum usart_data_order data_order); + +/** + * \brief Set USART mode + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] mode A mode to set + * + * \return The status of mode setting. + */ +int32_t usart_sync_set_mode(struct usart_sync_descriptor *const descr, const enum usart_mode mode); + +/** + * \brief Set USART parity + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] parity A parity to set + * + * \return The status of parity setting. + */ +int32_t usart_sync_set_parity(struct usart_sync_descriptor *const descr, const enum usart_parity parity); + +/** + * \brief Set USART stop bits + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] stop_bits Stop bits to set + * + * \return The status of stop bits setting. + */ +int32_t usart_sync_set_stopbits(struct usart_sync_descriptor *const descr, const enum usart_stop_bits stop_bits); + +/** + * \brief Set USART character size + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] size A character size to set + * + * \return The status of character size setting. + */ +int32_t usart_sync_set_character_size(struct usart_sync_descriptor *const descr, const enum usart_character_size size); + +/** + * \brief Retrieve the state of flow control pins + * + * This function retrieves the of flow control pins + * if the flow control is enabled. + * Function can return USART_FLOW_CONTROL_STATE_UNAVAILABLE in case + * if the flow control is done by the hardware + * and the pins state cannot be read out. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[out] state The state of flow control pins + * + * \return The status of flow control state reading. + */ +int32_t usart_sync_flow_control_status(const struct usart_sync_descriptor *const descr, + union usart_flow_control_state *const state); + +/** + * \brief Check if the USART transmitter is empty + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return The status of USART TX empty checking. + * \retval 0 The USART transmitter is not empty + * \retval 1 The USART transmitter is empty + */ +int32_t usart_sync_is_tx_empty(const struct usart_sync_descriptor *const descr); + +/** + * \brief Check if the USART receiver is not empty + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return The status of USART RX empty checking. + * \retval 1 The USART receiver is not empty + * \retval 0 The USART receiver is empty + */ +int32_t usart_sync_is_rx_not_empty(const struct usart_sync_descriptor *const descr); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t usart_sync_get_version(void); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HAL_SYNC_USART_H_INCLUDED */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_core.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_core.h new file mode 100644 index 00000000..9324c43e --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_core.h @@ -0,0 +1,56 @@ +/** + * \file + * + * \brief CPU core related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_CORE_H_INCLUDED +#define _HPL_CORE_H_INCLUDED + +/** + * \addtogroup HPL Core + * + * \section hpl_core_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include "hpl_core_port.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_CORE_H_INCLUDED */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_delay.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_delay.h new file mode 100644 index 00000000..a0f1ac81 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_delay.h @@ -0,0 +1,97 @@ +/** + * \file + * + * \brief Delay related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_DELAY_H_INCLUDED +#define _HPL_DELAY_H_INCLUDED + +/** + * \addtogroup HPL Delay + * + * \section hpl_delay_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifndef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name HPL functions + */ +//@{ + +/** + * \brief Initialize delay functionality + * + * \param[in] hw The pointer to hardware instance + */ +void _delay_init(void *const hw); + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of us + * + * \param[in] us The amount of us to delay for + * + * \return The amount of cycles + */ +uint32_t _get_cycles_for_us(const uint16_t us); + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of ms + * + * \param[in] ms The amount of ms to delay for + * + * \return The amount of cycles + */ +uint32_t _get_cycles_for_ms(const uint16_t ms); + +/** + * \brief Delay loop to delay n number of cycles + * + * \param[in] hw The pointer to hardware instance + * \param[in] cycles The amount of cycles to delay for + */ +void _delay_cycles(void *const hw, uint32_t cycles); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_DELAY_H_INCLUDED */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_dma.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_dma.h new file mode 100644 index 00000000..1e08434a --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_dma.h @@ -0,0 +1,176 @@ +/** + * \file + * + * \brief DMA related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_DMA_H_INCLUDED +#define _HPL_DMA_H_INCLUDED + +/** + * \addtogroup HPL DMA + * + * \section hpl_dma_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct _dma_resource; + +/** + * \brief DMA callback types + */ +enum _dma_callback_type { DMA_TRANSFER_COMPLETE_CB, DMA_TRANSFER_ERROR_CB }; + +/** + * \brief DMA interrupt callbacks + */ +struct _dma_callbacks { + void (*transfer_done)(struct _dma_resource *resource); + void (*error)(struct _dma_resource *resource); +}; + +/** + * \brief DMA resource structure + */ +struct _dma_resource { + struct _dma_callbacks dma_cb; + void * back; +}; + +/** + * \brief Initialize DMA + * + * This function does low level DMA configuration. + * + * \return initialize status + */ +int32_t _dma_init(void); + +/** + * \brief Set destination address + * + * \param[in] channel DMA channel to set destination address for + * \param[in] dst Destination address + * + * \return setting status + */ +int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst); + +/** + * \brief Set source address + * + * \param[in] channel DMA channel to set source address for + * \param[in] src Source address + * + * \return setting status + */ +int32_t _dma_set_source_address(const uint8_t channel, const void *const src); + +/** + * \brief Set next descriptor address + * + * \param[in] current_channel Current DMA channel to set next descriptor address + * \param[in] next_channel Next DMA channel used as next descriptor + * + * \return setting status + */ +int32_t _dma_set_next_descriptor(const uint8_t current_channel, const uint8_t next_channel); + +/** + * \brief Enable/disable source address incrementation during DMA transaction + * + * \param[in] channel DMA channel to set source address for + * \param[in] enable True to enable, false to disable + * + * \return status of operation + */ +int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable); + +/** + * \brief Enable/disable Destination address incrementation during DMA transaction + * + * \param[in] channel DMA channel to set destination address for + * \param[in] enable True to enable, false to disable + * + * \return status of operation + */ +int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable); +/** + * \brief Set the amount of data to be transfered per transaction + * + * \param[in] channel DMA channel to set data amount for + * \param[in] amount Data amount + * + * \return status of operation + */ +int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount); + +/** + * \brief Trigger DMA transaction on the given channel + * + * \param[in] channel DMA channel to trigger transaction on + * + * \return status of operation + */ +int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger); + +/** + * \brief Retrieves DMA resource structure + * + * \param[out] resource The resource to be retrieved + * \param[in] channel DMA channel to retrieve structure for + * + * \return status of operation + */ +int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel); + +/** + * \brief Enable/disable DMA interrupt + * + * \param[in] channel DMA channel to enable/disable interrupt for + * \param[in] type The type of interrupt to disable/enable if applicable + * \param[in] state Enable or disable + */ +void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state); + +#ifdef __cplusplus +} +#endif + +#endif /* HPL_DMA_H_INCLUDED */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_gpio.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_gpio.h new file mode 100644 index 00000000..5cdd387b --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_gpio.h @@ -0,0 +1,185 @@ +/** + * \file + * + * \brief Port related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_GPIO_H_INCLUDED +#define _HPL_GPIO_H_INCLUDED + +/** + * \addtogroup HPL Port + * + * \section hpl_port_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif +/** + * \brief Macros for the pin and port group, lower 5 + * bits stands for pin number in the group, higher 3 + * bits stands for port group + */ +#define GPIO_PIN(n) (((n)&0x1Fu) << 0) +#define GPIO_PORT(n) ((n) >> 5) +#define GPIO(port, pin) ((((port)&0x7u) << 5) + ((pin)&0x1Fu)) +#define GPIO_PIN_FUNCTION_OFF 0xffffffff + +/** + * \brief PORT pull mode settings + */ +enum gpio_pull_mode { GPIO_PULL_OFF, GPIO_PULL_UP, GPIO_PULL_DOWN }; + +/** + * \brief PORT direction settins + */ +enum gpio_direction { GPIO_DIRECTION_OFF, GPIO_DIRECTION_IN, GPIO_DIRECTION_OUT }; + +/** + * \brief PORT group abstraction + */ + +enum gpio_port { GPIO_PORTA, GPIO_PORTB, GPIO_PORTC, GPIO_PORTD, GPIO_PORTE }; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Port initialization function + * + * Port initialization function should setup the port module based + * on a static configuration file, this function should normally + * not be called directly, but is a part of hal_init() + */ +void _gpio_init(void); + +/** + * \brief Set direction on port with mask + * + * Set data direction for each pin, or disable the pin + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to the + * corresponding pin + * \param[in] direction GPIO_DIRECTION_OFF = set pin direction to input + * and disable input buffer to disable the pin + * GPIO_DIRECTION_IN = set pin direction to input + * and enable input buffer to enable the pin + * GPIO_DIRECTION_OUT = set pin direction to output + * and disable input buffer + */ +static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask, + const enum gpio_direction direction); + +/** + * \brief Set output level on port with mask + * + * Sets output state on pin to high or low with pin masking + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to + * the corresponding pin + * \param[in] level true = pin level is set to 1 + * false = pin level is set to 0 + */ +static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level); + +/** + * \brief Change output level to the opposite with mask + * + * Change pin output level to the opposite with pin masking + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to + * the corresponding pin + */ +static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask); + +/** + * \brief Get input levels on all port pins + * + * Get input level on all port pins, will read IN register if configured to + * input and OUT register if configured as output + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + */ +static inline uint32_t _gpio_get_level(const enum gpio_port port); + +/** + * \brief Set pin pull mode + * + * Set pull mode on a single pin + * + * \notice This function will automatically change pin direction to input + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] pin The pin in the group that pull mode should be selected + * for + * \param[in] pull_mode GPIO_PULL_OFF = pull resistor on pin is disabled + * GPIO_PULL_DOWN = pull resistor on pin will pull pin + * level to ground level + * GPIO_PULL_UP = pull resistor on pin will pull pin + * level to VCC + */ +static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin, + const enum gpio_pull_mode pull_mode); + +/** + * \brief Set gpio function + * + * Select which function a gpio is used for + * + * \param[in] gpio The gpio to set function for + * \param[in] function The gpio function is given by a 32-bit wide bitfield + * found in the header files for the device + * + */ +static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function); + +#include +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_GPIO_H_INCLUDED */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_i2c_m_async.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_i2c_m_async.h new file mode 100644 index 00000000..8a9491de --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_i2c_m_async.h @@ -0,0 +1,205 @@ +/** + * \file + * + * \brief I2C Master Hardware Proxy Layer(HPL) declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_M_ASYNC_H_INCLUDED +#define _HPL_I2C_M_ASYNC_H_INCLUDED + +#include "hpl_i2c_m_sync.h" +#include "hpl_irq.h" +#include "utils.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief i2c master callback names + */ +enum _i2c_m_async_callback_type { + I2C_M_ASYNC_DEVICE_ERROR, + I2C_M_ASYNC_DEVICE_TX_COMPLETE, + I2C_M_ASYNC_DEVICE_RX_COMPLETE +}; + +struct _i2c_m_async_device; + +typedef void (*_i2c_complete_cb_t)(struct _i2c_m_async_device *i2c_dev); +typedef void (*_i2c_error_cb_t)(struct _i2c_m_async_device *i2c_dev, int32_t errcode); + +/** + * \brief i2c callback pointers structure + */ +struct _i2c_m_async_callback { + _i2c_error_cb_t error; + _i2c_complete_cb_t tx_complete; + _i2c_complete_cb_t rx_complete; +}; + +/** + * \brief i2c device structure + */ +struct _i2c_m_async_device { + struct _i2c_m_service service; + void * hw; + struct _i2c_m_async_callback cb; + struct _irq_descriptor irq; +}; + +/** + * \name HPL functions + */ + +/** + * \brief Initialize I2C in interrupt mode + * + * This function does low level I2C configuration. + * + * \param[in] i2c_dev The pointer to i2c interrupt device structure + * \param[in] hw The pointer to hardware instance + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw); + +/** + * \brief Deinitialize I2C in interrupt mode + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Transfer data by I2C + * + * This function does low level I2C data transfer. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] msg The pointer to i2c msg structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *const i2c_dev, struct _i2c_m_msg *msg); + +/** + * \brief Set baud rate of I2C + * + * This function does low level I2C set baud rate. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] clkrate The clock rate(KHz) input to i2c module + * \param[in] baudrate The demand baud rate(KHz) of i2c module + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate); + +/** + * \brief Register callback to I2C + * + * This function does low level I2C callback register. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] cb_type The callback type request + * \param[in] func The callback function pointer + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *i2c_dev, enum _i2c_m_async_callback_type cb_type, + FUNC_PTR func); + +/** + * \brief Generate stop condition on the I2C bus + * + * This function will generate a stop condition on the I2C bus + * + * \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C + * + * \return Operation status + * \retval 0 Operation executed successfully + * \retval <0 Operation failed + */ +int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Returns the number of bytes left or not used in the I2C message buffer + * + * This function will return the number of bytes left (not written to the bus) or still free + * (not received from the bus) in the message buffer, depending on direction of transmission. + * + * \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C + * + * \return Number of bytes or error code + * \retval >0 Positive number indicating bytes left + * \retval 0 Buffer is full/empty depending on direction + * \retval <0 Error code + */ +int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Enable/disable I2C master interrupt + * + * param[in] device The pointer to I2C master device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type, + const bool state); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_i2c_m_sync.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_i2c_m_sync.h new file mode 100644 index 00000000..ce173ae2 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_i2c_m_sync.h @@ -0,0 +1,185 @@ +/** + * \file + * + * \brief I2C Master Hardware Proxy Layer(HPL) declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_M_SYNC_H_INCLUDED +#define _HPL_I2C_M_SYNC_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief i2c flags + */ +#define I2C_M_RD 0x0001 /* read data, from slave to master */ +#define I2C_M_BUSY 0x0100 +#define I2C_M_TEN 0x0400 /* this is a ten bit chip address */ +#define I2C_M_SEVEN 0x0800 /* this is a seven bit chip address */ +#define I2C_M_FAIL 0x1000 +#define I2C_M_STOP 0x8000 /* if I2C_FUNC_PROTOCOL_MANGLING */ + +/** + * \brief i2c Return codes + */ +#define I2C_OK 0 /* Operation successful */ +#define I2C_ACK -1 /* Received ACK from device on I2C bus */ +#define I2C_NACK -2 /* Received NACK from device on I2C bus */ +#define I2C_ERR_ARBLOST -3 /* Arbitration lost */ +#define I2C_ERR_BAD_ADDRESS -4 /* Bad address */ +#define I2C_ERR_BUS -5 /* Bus error */ +#define I2C_ERR_BUSY -6 /* Device busy */ +#define I2c_ERR_PACKAGE_COLLISION -7 /* Package collision */ + +/** + * \brief i2c I2C Modes + */ +#define I2C_STANDARD_MODE 0x00 +#define I2C_FASTMODE 0x01 +#define I2C_HIGHSPEED_MODE 0x02 + +/** + * \brief i2c master message structure + */ +struct _i2c_m_msg { + uint16_t addr; + volatile uint16_t flags; + int32_t len; + uint8_t * buffer; +}; + +/** + * \brief i2c master service + */ +struct _i2c_m_service { + struct _i2c_m_msg msg; + uint16_t mode; + uint16_t trise; +}; + +/** + * \brief i2c sync master device structure + */ +struct _i2c_m_sync_device { + struct _i2c_m_service service; + void * hw; +}; + +/** + * \name HPL functions + */ + +/** + * \brief Initialize I2C + * + * This function does low level I2C configuration. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] hw The pointer to hardware instance + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw); + +/** + * \brief Deinitialize I2C + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev); + +/** + * \brief Transfer data by I2C + * + * This function does low level I2C data transfer. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] msg The pointer to i2c msg structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg); + +/** + * \brief Set baud rate of I2C + * + * This function does low level I2C set baud rate. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] clkrate The clock rate(KHz) input to i2c module + * \param[in] baudrate The demand baud rate(KHz) of i2c module + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate); + +/** + * \brief Send send condition on the I2C bus + * + * This function will generate a stop condition on the I2C bus + * + * \param[in] i2c_dev The pointer to i2c device struct + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_i2c_s_async.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_i2c_s_async.h new file mode 100644 index 00000000..92a5765d --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_i2c_s_async.h @@ -0,0 +1,184 @@ +/** + * \file + * + * \brief I2C Slave Hardware Proxy Layer(HPL) declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_S_ASYNC_H_INCLUDED +#define _HPL_I2C_S_ASYNC_H_INCLUDED + +#include "hpl_i2c_s_sync.h" +#include "hpl_irq.h" +#include "utils.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief i2c callback types + */ +enum _i2c_s_async_callback_type { I2C_S_DEVICE_ERROR, I2C_S_DEVICE_TX, I2C_S_DEVICE_RX_COMPLETE }; + +/** + * \brief Forward declaration of I2C Slave device + */ +struct _i2c_s_async_device; + +/** + * \brief i2c slave callback function type + */ +typedef void (*_i2c_s_async_cb_t)(struct _i2c_s_async_device *device); + +/** + * \brief i2c slave callback pointers structure + */ +struct _i2c_s_async_callback { + void (*error)(struct _i2c_s_async_device *const device); + void (*tx)(struct _i2c_s_async_device *const device); + void (*rx_done)(struct _i2c_s_async_device *const device, const uint8_t data); +}; + +/** + * \brief i2c slave device structure + */ +struct _i2c_s_async_device { + void * hw; + struct _i2c_s_async_callback cb; + struct _irq_descriptor irq; +}; + +/** + * \name HPL functions + */ + +/** + * \brief Initialize asynchronous I2C slave + * + * This function does low level I2C configuration. + * + * \param[in] device The pointer to i2c interrupt device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw); + +/** + * \brief Deinitialize asynchronous I2C in interrupt mode + * + * \param[in] device The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device); + +/** + * \brief Check if 10-bit addressing mode is on + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Cheking status + * \retval 1 10-bit addressing mode is on + * \retval 0 10-bit addressing mode is off + */ +int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device); + +/** + * \brief Set I2C slave address + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] address Address to set + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address); + +/** + * \brief Write a byte to the given I2C instance + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] data Data to write + */ +void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data); + +/** + * \brief Retrieve I2C slave status + * + * \param[in] device The pointer to i2c slave device structure + * + *\return I2C slave status + */ +i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device); + +/** + * \brief Abort data transmission + * + * \param[in] device The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device); + +/** + * \brief Enable/disable I2C slave interrupt + * + * param[in] device The pointer to I2C slave device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] disable Enable or disable + */ +int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type, + const bool disable); + +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_I2C_S_ASYNC_H_INCLUDED */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_i2c_s_sync.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_i2c_s_sync.h new file mode 100644 index 00000000..93b59345 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_i2c_s_sync.h @@ -0,0 +1,184 @@ +/** + * \file + * + * \brief I2C Slave Hardware Proxy Layer(HPL) declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_S_SYNC_H_INCLUDED +#define _HPL_I2C_S_SYNC_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief I2C Slave status type + */ +typedef uint32_t i2c_s_status_t; + +/** + * \brief i2c slave device structure + */ +struct _i2c_s_sync_device { + void *hw; +}; + +#include + +/** + * \name HPL functions + */ + +/** + * \brief Initialize synchronous I2C slave + * + * This function does low level I2C configuration. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw); + +/** + * \brief Deinitialize synchronous I2C slave + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device); + +/** + * \brief Check if 10-bit addressing mode is on + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Cheking status + * \retval 1 10-bit addressing mode is on + * \retval 0 10-bit addressing mode is off + */ +int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device); + +/** + * \brief Set I2C slave address + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] address Address to set + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address); + +/** + * \brief Write a byte to the given I2C instance + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] data Data to write + */ +void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data); + +/** + * \brief Retrieve I2C slave status + * + * \param[in] device The pointer to i2c slave device structure + * + *\return I2C slave status + */ +i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device); + +/** + * \brief Clear the Data Ready interrupt flag + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_clear_data_ready_flag(const struct _i2c_s_sync_device *const device); + +/** + * \brief Read a byte from the given I2C instance + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Data received via I2C interface. + */ +uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device); + +/** + * \brief Check if I2C is ready to send next byte + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Status of the ready check. + * \retval true if the I2C is ready to send next byte + * \retval false if the I2C is not ready to send next byte + */ +bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device); + +/** + * \brief Check if there is data received by I2C + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Status of the data received check. + * \retval true if the I2C has received a byte + * \retval false if the I2C has not received a byte + */ +bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device); + +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_I2C_S_SYNC_H_INCLUDED */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_init.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_init.h new file mode 100644 index 00000000..71bf49c9 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_init.h @@ -0,0 +1,124 @@ +/** + * \file + * + * \brief Init related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_INIT_H_INCLUDED +#define _HPL_INIT_H_INCLUDED + +/** + * \addtogroup HPL Init + * + * \section hpl_init_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initializes clock sources + */ +void _sysctrl_init_sources(void); + +/** + * \brief Initializes Power Manager + */ +void _pm_init(void); + +/** + * \brief Initialize generators + */ +void _gclk_init_generators(void); + +/** + * \brief Initialize 32 kHz clock sources + */ +void _osc32kctrl_init_sources(void); + +/** + * \brief Initialize clock sources + */ +void _oscctrl_init_sources(void); + +/** + * \brief Initialize clock sources that need input reference clocks + */ +void _sysctrl_init_referenced_generators(void); + +/** + * \brief Initialize clock sources that need input reference clocks + */ +void _oscctrl_init_referenced_generators(void); + +/** + * \brief Initialize master clock generator + */ +void _mclk_init(void); + +/** + * \brief Initialize clock generator + */ +void _lpmcu_misc_regs_init(void); + +/** + * \brief Initialize clock generator + */ +void _pmc_init(void); + +/** + * \brief Set performance level + * + * \param[in] level The performance level to set + */ +void _set_performance_level(const uint8_t level); + +/** + * \brief Initialize the chip + */ +void _init_chip(void); + +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_INIT_H_INCLUDED */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_irq.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_irq.h new file mode 100644 index 00000000..2894944a --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_irq.h @@ -0,0 +1,116 @@ +/** + * \file + * + * \brief IRQ related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_IRQ_H_INCLUDED +#define _HPL_IRQ_H_INCLUDED + +/** + * \addtogroup HPL IRQ + * + * \section hpl_irq_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief IRQ descriptor + */ +struct _irq_descriptor { + void (*handler)(void *parameter); + void *parameter; +}; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Retrieve current IRQ number + * + * \return The current IRQ number + */ +uint8_t _irq_get_current(void); + +/** + * \brief Disable the given IRQ + * + * \param[in] n The number of IRQ to disable + */ +void _irq_disable(uint8_t n); + +/** + * \brief Set the given IRQ + * + * \param[in] n The number of IRQ to set + */ +void _irq_set(uint8_t n); + +/** + * \brief Clear the given IRQ + * + * \param[in] n The number of IRQ to clear + */ +void _irq_clear(uint8_t n); + +/** + * \brief Enable the given IRQ + * + * \param[in] n The number of IRQ to enable + */ +void _irq_enable(uint8_t n); + +/** + * \brief Register IRQ handler + * + * \param[in] number The number registered IRQ + * \param[in] irq The pointer to irq handler to register + * + * \return The status of IRQ handler registering + * \retval -1 Passed parameters were invalid + * \retval 0 The registering is completed successfully + */ +void _irq_register(const uint8_t number, struct _irq_descriptor *const irq); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_IRQ_H_INCLUDED */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_missing_features.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_missing_features.h new file mode 100644 index 00000000..7071db29 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_missing_features.h @@ -0,0 +1,37 @@ +/** + * \file + * + * \brief Family-dependent missing features expected by HAL + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_MISSING_FEATURES +#define _HPL_MISSING_FEATURES + +#endif /* _HPL_MISSING_FEATURES */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_reset.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_reset.h new file mode 100644 index 00000000..75738b6f --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_reset.h @@ -0,0 +1,92 @@ +/** + * \file + * + * \brief Reset related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_RESET_H_INCLUDED +#define _HPL_RESET_H_INCLUDED + +/** + * \addtogroup HPL Reset + * + * \section hpl_reset_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifndef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Reset reason enumeration + * + * The list of possible reset reasons. + */ +enum reset_reason { + RESET_REASON_POR = 1, + RESET_REASON_BOD12 = 2, + RESET_REASON_BOD33 = 4, + RESET_REASON_EXT = 16, + RESET_REASON_WDT = 32, + RESET_REASON_SYST = 64, + RESET_REASON_BACKUP = 128 +}; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Retrieve the reset reason + * + * Retrieves the reset reason of the last MCU reset. + * + *\return An enum value indicating the reason of the last reset. + */ +enum reset_reason _get_reset_reason(void); + +/** + * \brief Reset MCU + */ +void _reset_mcu(void); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_RESET_H_INCLUDED */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_sleep.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_sleep.h new file mode 100644 index 00000000..6731ec30 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_sleep.h @@ -0,0 +1,88 @@ +/** + * \file + * + * \brief Sleep related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SLEEP_H_INCLUDED +#define _HPL_SLEEP_H_INCLUDED + +/** + * \addtogroup HPL Sleep + * + * \section hpl_sleep_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifndef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Set the sleep mode for the device + * + * This function sets the sleep mode for the device. + * For an overview of which systems are disabled in sleep for the different + * sleep modes see datasheet. + * + * \param[in] mode Sleep mode to use + * + * \return the status of a sleep request + * \retval -1 The requested sleep mode was invalid + * \retval 0 The operation completed successfully, sleep mode is set + */ +int32_t _set_sleep_mode(const uint8_t mode); + +/** + * \brief Reset MCU + */ +void _reset_mcu(void); + +/** + * \brief Put MCU to sleep + */ +void _go_to_sleep(void); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_SLEEP_H_INCLUDED */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_spi.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_spi.h new file mode 100644 index 00000000..a5652e50 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_spi.h @@ -0,0 +1,163 @@ +/** + * \file + * + * \brief SPI related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_H_INCLUDED +#define _HPL_SPI_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief SPI Dummy char is used when reading data from the SPI slave + */ +#define SPI_DUMMY_CHAR 0x1ff + +/** + * \brief SPI message to let driver to process + */ +//@{ +struct spi_msg { + /** Pointer to the output data buffer */ + uint8_t *txbuf; + /** Pointer to the input data buffer */ + uint8_t *rxbuf; + /** Size of the message data in SPI characters */ + uint32_t size; +}; +//@} + +/** + * \brief SPI transfer modes + * SPI transfer mode controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + */ +enum spi_transfer_mode { + /** Leading edge is rising edge, data sample on leading edge. */ + SPI_MODE_0, + /** Leading edge is rising edge, data sample on trailing edge. */ + SPI_MODE_1, + /** Leading edge is falling edge, data sample on leading edge. */ + SPI_MODE_2, + /** Leading edge is falling edge, data sample on trailing edge. */ + SPI_MODE_3 +}; + +/** + * \brief SPI character sizes + * The character size influence the way the data is sent/received. + * For char size <= 8 data is stored byte by byte. + * For char size between 9 ~ 16 data is stored in 2-byte length. + * Note that the default and recommended char size is 8 bit since it's + * supported by all system. + */ +enum spi_char_size { + /** Character size is 8 bit. */ + SPI_CHAR_SIZE_8 = 0, + /** Character size is 9 bit. */ + SPI_CHAR_SIZE_9 = 1, + /** Character size is 10 bit. */ + SPI_CHAR_SIZE_10 = 2, + /** Character size is 11 bit. */ + SPI_CHAR_SIZE_11 = 3, + /** Character size is 12 bit. */ + SPI_CHAR_SIZE_12 = 4, + /** Character size is 13 bit. */ + SPI_CHAR_SIZE_13 = 5, + /** Character size is 14 bit. */ + SPI_CHAR_SIZE_14 = 6, + /** Character size is 15 bit. */ + SPI_CHAR_SIZE_15 = 7, + /** Character size is 16 bit. */ + SPI_CHAR_SIZE_16 = 8 +}; + +/** + * \brief SPI data order + */ +enum spi_data_order { + /** MSB goes first. */ + SPI_DATA_ORDER_MSB_1ST = 0, + /** LSB goes first. */ + SPI_DATA_ORDER_LSB_1ST = 1 +}; + +/** \brief Transfer descriptor for SPI + * Transfer descriptor holds TX and RX buffers + */ +struct spi_xfer { + /** Pointer to data buffer to TX */ + uint8_t *txbuf; + /** Pointer to data buffer to RX */ + uint8_t *rxbuf; + /** Size of data characters to TX & RX */ + uint32_t size; +}; + +/** SPI generic driver. */ +struct spi_dev { + /** Pointer to the hardware base or private data for special device. */ + void *prvt; + /** Reference start of sync/async variables */ + uint32_t sync_async_misc[1]; +}; + +/** + * \brief Calculate the baudrate value for hardware to use to set baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] clk Clock frequency (Hz) for baudrate generation. + * \param[in] baud Target baudrate (bps). + * \return Error or baudrate value. + * \retval >0 Baudrate value. + * \retval ERR_INVALID_ARG Calculation fail. + */ +int32_t _spi_calc_baud_val(struct spi_dev *dev, const uint32_t clk, const uint32_t baud); + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_H_INCLUDED */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_spi_async.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_spi_async.h new file mode 100644 index 00000000..8e5a8485 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_spi_async.h @@ -0,0 +1,131 @@ +/** + * \file + * + * \brief Common SPI related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_ASYNC_H_INCLUDED +#define _HPL_SPI_ASYNC_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Callbacks the SPI driver must offer in async mode + */ +//@{ +/** The callback types */ +enum _spi_async_dev_cb_type { + /** Callback type for transmit, see \ref _spi_async_dev_cb_xfer_t. */ + SPI_DEV_CB_TX, + /** Callback type for receive, see \ref _spi_async_dev_cb_xfer_t. */ + SPI_DEV_CB_RX, + /** Callback type for \ref _spi_async_dev_cb_complete_t. */ + SPI_DEV_CB_COMPLETE, + /** Callback type for error */ + SPI_DEV_CB_ERROR, + /** Number of callbacks. */ + SPI_DEV_CB_N +}; + +struct _spi_async_dev; + +/** \brief The prototype for callback on SPI transfer error. + * If status code is zero, it indicates the normal completion, that is, + * SS deactivation. + * If status code belows zero, it indicates complete. + */ +typedef void (*_spi_async_dev_cb_error_t)(struct _spi_async_dev *dev, int32_t status); + +/** \brief The prototype for callback on SPI transmit/receive event + * For TX, the callback is invoked when transmit is done or ready to start + * transmit. + * For RX, the callback is invoked when receive is done or ready to read data, + * see \ref _spi_async_dev_read_one_t on data reading. + * Without DMA enabled, the callback is invoked on each character event. + * With DMA enabled, the callback is invoked on DMA buffer done. + */ +typedef void (*_spi_async_dev_cb_xfer_t)(struct _spi_async_dev *dev); + +/** + * \brief The callbacks offered by SPI driver + */ +struct _spi_async_dev_callbacks { + /** TX callback, see \ref _spi_async_dev_cb_xfer_t. */ + _spi_async_dev_cb_xfer_t tx; + /** RX callback, see \ref _spi_async_dev_cb_xfer_t. */ + _spi_async_dev_cb_xfer_t rx; + /** Complete or complete callback, see \ref _spi_async_dev_cb_complete_t. */ + _spi_async_dev_cb_xfer_t complete; + /** Error callback, see \ref */ + _spi_async_dev_cb_error_t err; +}; +//@} + +/** + * \brief SPI async driver + */ +//@{ + +/** SPI driver to support async HAL */ +struct _spi_async_dev { + /** Pointer to the hardware base or private data for special device. */ + void *prvt; + /** Data size, number of bytes for each character */ + uint8_t char_size; + /** Dummy byte used in master mode when reading the slave */ + uint16_t dummy_byte; + + /** \brief Pointer to callback functions, ignored for polling mode + * Pointer to the callback functions so that initialize the driver to + * handle interrupts. + */ + struct _spi_async_dev_callbacks callbacks; + /** IRQ instance for SPI device. */ + struct _irq_descriptor irq; +}; +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_ASYNC_H_INCLUDED */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_spi_dma.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_spi_dma.h new file mode 100644 index 00000000..04a30158 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_spi_dma.h @@ -0,0 +1,88 @@ +/** + * \file + * + * \brief Common SPI DMA related functionality declaration. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_DMA_H_INCLUDED +#define _HPL_SPI_DMA_H_INCLUDED + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** The callback types */ +enum _spi_dma_dev_cb_type { + /** Callback type for DMA transmit. */ + SPI_DEV_CB_DMA_TX, + /** Callback type for DMA receive. */ + SPI_DEV_CB_DMA_RX, + /** Callback type for DMA error. */ + SPI_DEV_CB_DMA_ERROR, + /** Number of callbacks. */ + SPI_DEV_CB_DMA_N +}; + +struct _spi_dma_dev; + +/** + * \brief The prototype for callback on SPI DMA. + */ +typedef void (*_spi_dma_cb_t)(struct _dma_resource *resource); + +/** + * \brief The callbacks offered by SPI driver + */ +struct _spi_dma_dev_callbacks { + _spi_dma_cb_t tx; + _spi_dma_cb_t rx; + _spi_dma_cb_t error; +}; + +/** SPI driver to support DMA HAL */ +struct _spi_dma_dev { + /** Pointer to the hardware base or private data for special device. */ + void *prvt; + /** Pointer to callback functions */ + struct _spi_dma_dev_callbacks callbacks; + /** IRQ instance for SPI device. */ + struct _irq_descriptor irq; + /** DMA resource */ + struct _dma_resource *resource; +}; + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _HPL_SPI_DMA_H_INCLUDED */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_spi_m_async.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_spi_m_async.h new file mode 100644 index 00000000..8d3555ed --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_spi_m_async.h @@ -0,0 +1,243 @@ +/** + * \file + * + * \brief SPI Slave Async related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_M_ASYNC_H_INCLUDED +#define _HPL_SPI_M_ASYNC_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI async device driver. */ +#define _spi_m_async_dev _spi_async_dev + +#define _spi_m_async_dev_cb_type _spi_async_dev_cb_type + +/** Uses common SPI async device driver complete callback type. */ +#define _spi_m_async_dev_cb_error_t _spi_async_dev_cb_error_t + +/** Uses common SPI async device driver transfer callback type. */ +#define _spi_m_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access with interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_init(struct _spi_m_async_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_deinit(struct _spi_m_async_dev *dev); + +/** + * \brief Enable SPI for access with interrupts + * Enable the SPI and enable callback generation of receive and error + * interrupts. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_enable(struct _spi_m_async_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI and interrupts. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_disable(struct _spi_m_async_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_mode(struct _spi_m_async_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on + * how it's generated. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_baudrate(struct _spi_m_async_dev *dev, const uint32_t baud_val); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_char_size(struct _spi_m_async_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_data_order(struct _spi_m_async_dev *dev, const enum spi_data_order dord); + +/** + * \brief Enable interrupt on character output + * + * Enable interrupt when a new character can be written + * to the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable output interrupt + * false = disable output interrupt + * + * \return Status code + * \retval 0 Ok status + */ +int32_t _spi_m_async_enable_tx(struct _spi_m_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on character input + * + * Enable interrupt when a new character is ready to be + * read from the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_m_async_enable_rx(struct _spi_m_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on after data transmission complate + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_m_async_enable_tx_complete(struct _spi_m_async_dev *dev, bool state); + +/** + * \brief Read one character to SPI device instance + * \param[in, out] dev Pointer to the SPI device instance. + * + * \return Character read from SPI module + */ +uint16_t _spi_m_async_read_one(struct _spi_m_async_dev *dev); + +/** + * \brief Write one character to assigned buffer + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] data + * + * \return Status code of write operation + * \retval 0 Write operation OK + */ +int32_t _spi_m_async_write_one(struct _spi_m_async_dev *dev, uint16_t data); + +/** + * \brief Register the SPI device callback + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] cb_type The callback type. + * \param[in] func The callback function to register. NULL to disable callback. + * \return Always 0. + */ +int32_t _spi_m_async_register_callback(struct _spi_m_async_dev *dev, const enum _spi_m_async_dev_cb_type cb_type, + const FUNC_PTR func); + +/** + * \brief Enable/disable SPI master interrupt + * + * param[in] device The pointer to SPI master device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _spi_m_async_set_irq_state(struct _spi_m_async_dev *const device, const enum _spi_m_async_dev_cb_type type, + const bool state); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_M_ASYNC_H_INCLUDED */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_spi_m_dma.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_spi_m_dma.h new file mode 100644 index 00000000..2b48300e --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_spi_m_dma.h @@ -0,0 +1,182 @@ +/** + * \file + * + * \brief SPI Master DMA related functionality declaration. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_M_DMA_H_INCLUDED +#define _HPL_SPI_M_DMA_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI dma device driver. */ +#define _spi_m_dma_dev _spi_dma_dev + +#define _spi_m_dma_dev_cb_type _spi_dma_dev_cb_type + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access with interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_init(struct _spi_m_dma_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_deinit(struct _spi_m_dma_dev *dev); + +/** + * \brief Enable SPI for access with interrupts + * Enable the SPI and enable callback generation of receive and error + * interrupts. + * \param[in] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_enable(struct _spi_m_dma_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI and interrupts. Deactivate all CS pins if works as master. + * \param[in] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_disable(struct _spi_m_dma_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_set_mode(struct _spi_m_dma_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in] dev Pointer to the SPI device instance. + * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on + * how it's generated. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_dma_set_baudrate(struct _spi_m_dma_dev *dev, const uint32_t baud_val); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_dma_set_char_size(struct _spi_m_dma_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_dma_set_data_order(struct _spi_m_dma_dev *dev, const enum spi_data_order dord); + +/** + * \brief Register the SPI device callback + * \param[in] dev Pointer to the SPI device instance. + * \param[in] cb_type The callback type. + * \param[in] func The callback function to register. NULL to disable callback. + * \return Always 0. + */ +void _spi_m_dma_register_callback(struct _spi_m_dma_dev *dev, enum _spi_dma_dev_cb_type, _spi_dma_cb_t func); + +/** \brief Do SPI data transfer (TX & RX) with DMA + * Log the TX & RX buffers and transfer them in background. It never blocks. + * + * \param[in] dev Pointer to the SPI device instance. + * \param[in] txbuf Pointer to the transfer information (\ref spi_transfer). + * \param[out] rxbuf Pointer to the receiver information (\ref spi_receive). + * \param[in] length spi transfer data length. + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval ERR_BUSY Busy. + */ +int32_t _spi_m_dma_transfer(struct _spi_m_dma_dev *dev, uint8_t const *txbuf, uint8_t *const rxbuf, + const uint16_t length); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_M_DMA_H_INCLUDED */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_spi_m_sync.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_spi_m_sync.h new file mode 100644 index 00000000..38df15b4 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_spi_m_sync.h @@ -0,0 +1,166 @@ +/** + * \file + * + * \brief SPI related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_M_SYNC_H_INCLUDED +#define _HPL_SPI_M_SYNC_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI sync device driver. */ +#define _spi_m_sync_dev _spi_sync_dev + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access without interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw); + +/** + * \brief Deinitialize SPI + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_deinit(struct _spi_m_sync_dev *dev); + +/** + * \brief Enable SPI for access without interrupts + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_enable(struct _spi_m_sync_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_disable(struct _spi_m_sync_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_mode(struct _spi_m_sync_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on + * how it's generated. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_baudrate(struct _spi_m_sync_dev *dev, const uint32_t baud_val); + +/** + * \brief Set SPI char size + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_char_size(struct _spi_m_sync_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_data_order(struct _spi_m_sync_dev *dev, const enum spi_data_order dord); + +/** + * \brief Transfer the whole message without interrupt + * Transfer the message, it will keep waiting until the message finish or + * error. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] msg Pointer to the message instance to process. + * \return Error or number of characters transferred. + * \retval ERR_BUSY SPI hardware is not ready to start transfer (not + * enabled, busy applying settings, ...). + * \retval SPI_ERR_OVERFLOW Overflow error. + * \retval >=0 Number of characters transferred. + */ +int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_M_SYNC_H_INCLUDED */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_spi_s_async.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_spi_s_async.h new file mode 100644 index 00000000..56472439 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_spi_s_async.h @@ -0,0 +1,232 @@ +/** + * \file + * + * \brief SPI Slave Async related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_S_ASYNC_H_INCLUDED +#define _HPL_SPI_S_ASYNC_H_INCLUDED + +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI async device driver. */ +#define _spi_s_async_dev _spi_async_dev + +#define _spi_s_async_dev_cb_type _spi_async_dev_cb_type + +/** Uses common SPI async device driver complete callback type. */ +#define _spi_m_async_dev_cb_error_t _spi_async_dev_cb_error_t + +/** Uses common SPI async device driver transfer callback type. */ +#define _spi_s_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access with interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev); + +/** + * \brief Enable SPI for access with interrupts + * Enable the SPI and enable callback generation of receive and error + * interrupts. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_enable(struct _spi_s_async_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI and interrupts. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_disable(struct _spi_s_async_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_set_mode(struct _spi_s_async_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_set_char_size(struct _spi_s_async_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_set_data_order(struct _spi_s_async_dev *dev, const enum spi_data_order dord); + +/** + * \brief Enable interrupt on character output + * + * Enable interrupt when a new character can be written + * to the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable output interrupt + * false = disable output interrupt + * + * \return Status code + * \retval 0 Ok status + */ +int32_t _spi_s_async_enable_tx(struct _spi_s_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on character input + * + * Enable interrupt when a new character is ready to be + * read from the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_s_async_enable_rx(struct _spi_s_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on Slave Select (SS) rising + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_s_async_enable_ss_detect(struct _spi_s_async_dev *dev, bool state); + +/** + * \brief Read one character to SPI device instance + * \param[in, out] dev Pointer to the SPI device instance. + * + * \return Character read from SPI module + */ +uint16_t _spi_s_async_read_one(struct _spi_s_async_dev *dev); + +/** + * \brief Write one character to assigned buffer + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] data + * + * \return Status code of write operation + * \retval 0 Write operation OK + */ +int32_t _spi_s_async_write_one(struct _spi_s_async_dev *dev, uint16_t data); + +/** + * \brief Register the SPI device callback + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] cb_type The callback type. + * \param[in] func The callback function to register. NULL to disable callback. + * \return Always 0. + */ +int32_t _spi_s_async_register_callback(struct _spi_s_async_dev *dev, const enum _spi_s_async_dev_cb_type cb_type, + const FUNC_PTR func); + +/** + * \brief Enable/disable SPI slave interrupt + * + * param[in] device The pointer to SPI slave device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _spi_s_async_set_irq_state(struct _spi_s_async_dev *const device, const enum _spi_async_dev_cb_type type, + const bool state); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_S_ASYNC_H_INCLUDED */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_spi_s_sync.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_spi_s_sync.h new file mode 100644 index 00000000..ff4c811a --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_spi_s_sync.h @@ -0,0 +1,232 @@ +/** + * \file + * + * \brief SPI related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_S_SYNC_H_INCLUDED +#define _HPL_SPI_S_SYNC_H_INCLUDED + +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI sync device driver. */ +#define _spi_s_sync_dev _spi_sync_dev + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access without interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev); + +/** + * \brief Enable SPI for access without interrupts + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord); + +/** + * \brief Enable interrupt on character output + * + * Enable interrupt when a new character can be written + * to the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable output interrupt + * false = disable output interrupt + * + * \return Status code + * \retval 0 Ok status + */ +int32_t _spi_s_sync_enable_tx(struct _spi_s_sync_dev *dev, bool state); + +/** + * \brief Enable interrupt on character input + * + * Enable interrupt when a new character is ready to be + * read from the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retval 0 OK Status + */ +int32_t _spi_s_sync_enable_rx(struct _spi_s_sync_dev *dev, bool state); + +/** + * \brief Read one character to SPI device instance + * \param[in, out] dev Pointer to the SPI device instance. + * + * \return Character read from SPI module + */ +uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev); + +/** + * \brief Write one character to assigned buffer + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] data + * + * \return Status code of write operation + * \retval 0 Write operation OK + */ +int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data); + +/** + * \brief Check if TX ready + * + * \param[in] dev Pointer to the SPI device instance + * + * \return TX ready state + * \retval true TX ready + * \retval false TX not ready + */ +bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev); + +/** + * \brief Check if RX character ready + * + * \param[in] dev Pointer to the SPI device instance + * + * \return RX character ready state + * \retval true RX character ready + * \retval false RX character not ready + */ +bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev); + +/** + * \brief Check if SS deactiviation detected + * + * \param[in] dev Pointer to the SPI device instance + * + * \return SS deactiviation state + * \retval true SS deactiviation detected + * \retval false SS deactiviation not detected + */ +bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev); + +/** + * \brief Check if error is detected + * + * \param[in] dev Pointer to the SPI device instance + * + * \return Error detection state + * \retval true Error detected + * \retval false Error not detected + */ +bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_S_SYNC_H_INCLUDED */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_spi_sync.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_spi_sync.h new file mode 100644 index 00000000..dc88648f --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_spi_sync.h @@ -0,0 +1,70 @@ +/** + * \file + * + * \brief Common SPI related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_SYNC_H_INCLUDED +#define _HPL_SPI_SYNC_H_INCLUDED + +#include +#include + +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * \section hpl_spi_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** SPI driver to support sync HAL */ +struct _spi_sync_dev { + /** Pointer to the hardware base or private data for special device. */ + void *prvt; + /** Data size, number of bytes for each character */ + uint8_t char_size; + /** Dummy byte used in master mode when reading the slave */ + uint16_t dummy_byte; +}; + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_SYNC_H_INCLUDED */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_usart.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_usart.h new file mode 100644 index 00000000..0e09501d --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_usart.h @@ -0,0 +1,113 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_USART_H_INCLUDED +#define _HPL_USART_H_INCLUDED + +/** + * \addtogroup HPL USART SYNC + * + * \section hpl_usart_sync_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief USART flow control state + */ +union usart_flow_control_state { + struct { + uint8_t cts : 1; + uint8_t rts : 1; + uint8_t unavailable : 1; + uint8_t reserved : 5; + } bit; + uint8_t value; +}; + +/** + * \brief USART baud rate mode + */ +enum usart_baud_rate_mode { USART_BAUDRATE_ASYNCH_ARITHMETIC, USART_BAUDRATE_ASYNCH_FRACTIONAL, USART_BAUDRATE_SYNCH }; + +/** + * \brief USART data order + */ +enum usart_data_order { USART_DATA_ORDER_MSB = 0, USART_DATA_ORDER_LSB = 1 }; + +/** + * \brief USART mode + */ +enum usart_mode { USART_MODE_ASYNCHRONOUS = 0, USART_MODE_SYNCHRONOUS = 1 }; + +/** + * \brief USART parity + */ +enum usart_parity { + USART_PARITY_EVEN = 0, + USART_PARITY_ODD = 1, + USART_PARITY_NONE = 2, + USART_PARITY_SPACE = 3, + USART_PARITY_MARK = 4 +}; + +/** + * \brief USART stop bits mode + */ +enum usart_stop_bits { USART_STOP_BITS_ONE = 0, USART_STOP_BITS_TWO = 1, USART_STOP_BITS_ONE_P_FIVE = 2 }; + +/** + * \brief USART character size + */ +enum usart_character_size { + USART_CHARACTER_SIZE_8BITS = 0, + USART_CHARACTER_SIZE_9BITS = 1, + USART_CHARACTER_SIZE_5BITS = 5, + USART_CHARACTER_SIZE_6BITS = 6, + USART_CHARACTER_SIZE_7BITS = 7 +}; + +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_USART_H_INCLUDED */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_usart_async.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_usart_async.h new file mode 100644 index 00000000..3f833d1a --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_usart_async.h @@ -0,0 +1,270 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_USART_ASYNC_H_INCLUDED +#define _HPL_USART_ASYNC_H_INCLUDED + +/** + * \addtogroup HPL USART + * + * \section hpl_usart_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include "hpl_usart.h" +#include "hpl_irq.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief USART callback types + */ +enum _usart_async_callback_type { USART_ASYNC_BYTE_SENT, USART_ASYNC_RX_DONE, USART_ASYNC_TX_DONE, USART_ASYNC_ERROR }; + +/** + * \brief USART device structure + * + * The USART device structure forward declaration. + */ +struct _usart_async_device; + +/** + * \brief USART interrupt callbacks + */ +struct _usart_async_callbacks { + void (*tx_byte_sent)(struct _usart_async_device *device); + void (*rx_done_cb)(struct _usart_async_device *device, uint8_t data); + void (*tx_done_cb)(struct _usart_async_device *device); + void (*error_cb)(struct _usart_async_device *device); +}; + +/** + * \brief USART descriptor device structure + */ +struct _usart_async_device { + struct _usart_async_callbacks usart_cb; + struct _irq_descriptor irq; + void * hw; +}; +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize asynchronous USART + * + * This function does low level USART configuration. + * + * \param[in] device The pointer to USART device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status + */ +int32_t _usart_async_init(struct _usart_async_device *const device, void *const hw); + +/** + * \brief Deinitialize USART + * + * This function closes the given USART by disabling its clock. + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_deinit(struct _usart_async_device *const device); + +/** + * \brief Enable usart module + * + * This function will enable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_enable(struct _usart_async_device *const device); + +/** + * \brief Disable usart module + * + * This function will disable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_disable(struct _usart_async_device *const device); + +/** + * \brief Calculate baud rate register value + * + * \param[in] baud Required baud rate + * \param[in] clock_rate clock frequency + * \param[in] samples The number of samples + * \param[in] mode USART mode + * \param[in] fraction A fraction value + * + * \return Calculated baud rate register value + */ +uint16_t _usart_async_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction); + +/** + * \brief Set baud rate + * + * \param[in] device The pointer to USART device instance + * \param[in] baud_rate A baud rate to set + */ +void _usart_async_set_baud_rate(struct _usart_async_device *const device, const uint32_t baud_rate); + +/** + * \brief Set data order + * + * \param[in] device The pointer to USART device instance + * \param[in] order A data order to set + */ +void _usart_async_set_data_order(struct _usart_async_device *const device, const enum usart_data_order order); + +/** + * \brief Set mode + * + * \param[in] device The pointer to USART device instance + * \param[in] mode A mode to set + */ +void _usart_async_set_mode(struct _usart_async_device *const device, const enum usart_mode mode); + +/** + * \brief Set parity + * + * \param[in] device The pointer to USART device instance + * \param[in] parity A parity to set + */ +void _usart_async_set_parity(struct _usart_async_device *const device, const enum usart_parity parity); + +/** + * \brief Set stop bits mode + * + * \param[in] device The pointer to USART device instance + * \param[in] stop_bits A stop bits mode to set + */ +void _usart_async_set_stop_bits(struct _usart_async_device *const device, const enum usart_stop_bits stop_bits); + +/** + * \brief Set character size + * + * \param[in] device The pointer to USART device instance + * \param[in] size A character size to set + */ +void _usart_async_set_character_size(struct _usart_async_device *const device, const enum usart_character_size size); + +/** + * \brief Retrieve usart status + * + * \param[in] device The pointer to USART device instance + */ +uint32_t _usart_async_get_status(const struct _usart_async_device *const device); + +/** + * \brief Write a byte to the given USART instance + * + * \param[in] device The pointer to USART device instance + * \param[in] data Data to write + */ +void _usart_async_write_byte(struct _usart_async_device *const device, uint8_t data); + +/** + * \brief Check if USART is ready to send next byte + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the ready check. + * \retval true if the USART is ready to send next byte + * \retval false if the USART is not ready to send next byte + */ +bool _usart_async_is_byte_sent(const struct _usart_async_device *const device); + +/** + * \brief Set the state of flow control pins + * + * \param[in] device The pointer to USART device instance + * \param[in] state - A state of flow control pins to set + */ +void _usart_async_set_flow_control_state(struct _usart_async_device *const device, + const union usart_flow_control_state state); + +/** + * \brief Retrieve the state of flow control pins + * + * This function retrieves the of flow control pins. + * + * \return USART_FLOW_CONTROL_STATE_UNAVAILABLE. + */ +union usart_flow_control_state _usart_async_get_flow_control_state(const struct _usart_async_device *const device); + +/** + * \brief Enable data register empty interrupt + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_enable_byte_sent_irq(struct _usart_async_device *const device); + +/** + * \brief Enable transmission complete interrupt + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_enable_tx_done_irq(struct _usart_async_device *const device); + +/** + * \brief Retrieve ordinal number of the given USART hardware instance + * + * \param[in] device The pointer to USART device instance + * + * \return The ordinal number of the given USART hardware instance + */ +uint8_t _usart_async_get_hardware_index(const struct _usart_async_device *const device); + +/** + * \brief Enable/disable USART interrupt + * + * param[in] device The pointer to USART device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _usart_async_set_irq_state(struct _usart_async_device *const device, const enum _usart_async_callback_type type, + const bool state); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_USART_ASYNC_H_INCLUDED */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_usart_sync.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_usart_sync.h new file mode 100644 index 00000000..abc7264f --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/include/hpl_usart_sync.h @@ -0,0 +1,254 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SYNC_USART_H_INCLUDED +#define _HPL_SYNC_USART_H_INCLUDED + +/** + * \addtogroup HPL USART SYNC + * + * \section hpl_usart_sync_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief USART descriptor device structure + */ +struct _usart_sync_device { + void *hw; +}; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize synchronous USART + * + * This function does low level USART configuration. + * + * \param[in] device The pointer to USART device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status + */ +int32_t _usart_sync_init(struct _usart_sync_device *const device, void *const hw); + +/** + * \brief Deinitialize USART + * + * This function closes the given USART by disabling its clock. + * + * \param[in] device The pointer to USART device instance + */ +void _usart_sync_deinit(struct _usart_sync_device *const device); + +/** + * \brief Enable usart module + * + * This function will enable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_sync_enable(struct _usart_sync_device *const device); + +/** + * \brief Disable usart module + * + * This function will disable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_sync_disable(struct _usart_sync_device *const device); + +/** + * \brief Calculate baud rate register value + * + * \param[in] baud Required baud rate + * \param[in] clock_rate clock frequency + * \param[in] samples The number of samples + * \param[in] mode USART mode + * \param[in] fraction A fraction value + * + * \return Calculated baud rate register value + */ +uint16_t _usart_sync_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction); + +/** + * \brief Set baud rate + * + * \param[in] device The pointer to USART device instance + * \param[in] baud_rate A baud rate to set + */ +void _usart_sync_set_baud_rate(struct _usart_sync_device *const device, const uint32_t baud_rate); + +/** + * \brief Set data order + * + * \param[in] device The pointer to USART device instance + * \param[in] order A data order to set + */ +void _usart_sync_set_data_order(struct _usart_sync_device *const device, const enum usart_data_order order); + +/** + * \brief Set mode + * + * \param[in] device The pointer to USART device instance + * \param[in] mode A mode to set + */ +void _usart_sync_set_mode(struct _usart_sync_device *const device, const enum usart_mode mode); + +/** + * \brief Set parity + * + * \param[in] device The pointer to USART device instance + * \param[in] parity A parity to set + */ +void _usart_sync_set_parity(struct _usart_sync_device *const device, const enum usart_parity parity); + +/** + * \brief Set stop bits mode + * + * \param[in] device The pointer to USART device instance + * \param[in] stop_bits A stop bits mode to set + */ +void _usart_sync_set_stop_bits(struct _usart_sync_device *const device, const enum usart_stop_bits stop_bits); + +/** + * \brief Set character size + * + * \param[in] device The pointer to USART device instance + * \param[in] size A character size to set + */ +void _usart_sync_set_character_size(struct _usart_sync_device *const device, const enum usart_character_size size); + +/** + * \brief Retrieve usart status + * + * \param[in] device The pointer to USART device instance + */ +uint32_t _usart_sync_get_status(const struct _usart_sync_device *const device); + +/** + * \brief Write a byte to the given USART instance + * + * \param[in] device The pointer to USART device instance + * \param[in] data Data to write + */ +void _usart_sync_write_byte(struct _usart_sync_device *const device, uint8_t data); + +/** + * \brief Read a byte from the given USART instance + * + * \param[in] device The pointer to USART device instance + * \param[in] data Data to write + * + * \return Data received via USART interface. + */ +uint8_t _usart_sync_read_byte(const struct _usart_sync_device *const device); + +/** + * \brief Check if USART is ready to send next byte + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the ready check. + * \retval true if the USART is ready to send next byte + * \retval false if the USART is not ready to send next byte + */ +bool _usart_sync_is_ready_to_send(const struct _usart_sync_device *const device); + +/** + * \brief Check if USART transmitter has sent the byte + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the ready check. + * \retval true if the USART transmitter has sent the byte + * \retval false if the USART transmitter has not send the byte + */ +bool _usart_sync_is_transmit_done(const struct _usart_sync_device *const device); + +/** + * \brief Check if there is data received by USART + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the data received check. + * \retval true if the USART has received a byte + * \retval false if the USART has not received a byte + */ +bool _usart_sync_is_byte_received(const struct _usart_sync_device *const device); + +/** + * \brief Set the state of flow control pins + * + * \param[in] device The pointer to USART device instance + * \param[in] state - A state of flow control pins to set + */ +void _usart_sync_set_flow_control_state(struct _usart_sync_device *const device, + const union usart_flow_control_state state); + +/** + * \brief Retrieve the state of flow control pins + * + * This function retrieves the of flow control pins. + * + * \return USART_FLOW_CONTROL_STATE_UNAVAILABLE. + */ +union usart_flow_control_state _usart_sync_get_flow_control_state(const struct _usart_sync_device *const device); + +/** + * \brief Retrieve ordinal number of the given USART hardware instance + * + * \param[in] device The pointer to USART device instance + * + * \return The ordinal number of the given USART hardware instance + */ +uint8_t _usart_sync_get_hardware_index(const struct _usart_sync_device *const device); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_SYNC_USART_H_INCLUDED */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/src/hal_atomic.c b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/src/hal_atomic.c new file mode 100644 index 00000000..f56418ee --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/src/hal_atomic.c @@ -0,0 +1,66 @@ +/** + * \file + * + * \brief Critical sections related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_atomic.h" + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Disable interrupts, enter critical section + */ +void atomic_enter_critical(hal_atomic_t volatile *atomic) +{ + *atomic = __get_PRIMASK(); + __disable_irq(); + __DMB(); +} + +/** + * \brief Exit atomic section + */ +void atomic_leave_critical(hal_atomic_t volatile *atomic) +{ + __DMB(); + __set_PRIMASK(*atomic); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t atomic_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/src/hal_delay.c b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/src/hal_delay.c new file mode 100644 index 00000000..6f77cc70 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/src/hal_delay.c @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief HAL delay related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include "hal_delay.h" +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief The pointer to a hardware instance used by the driver. + */ +static void *hardware; + +/** + * \brief Initialize Delay driver + */ +void delay_init(void *const hw) +{ + _delay_init(hardware = hw); +} + +/** + * \brief Perform delay in us + */ +void delay_us(const uint16_t us) +{ + _delay_cycles(hardware, _get_cycles_for_us(us)); +} + +/** + * \brief Perform delay in ms + */ +void delay_ms(const uint16_t ms) +{ + _delay_cycles(hardware, _get_cycles_for_ms(ms)); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t delay_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/src/hal_gpio.c b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/src/hal_gpio.c new file mode 100644 index 00000000..00dfea6f --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/src/hal_gpio.c @@ -0,0 +1,44 @@ +/** + * \file + * + * \brief Port + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_gpio.h" + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +uint32_t gpio_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/src/hal_i2c_m_sync.c b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/src/hal_i2c_m_sync.c new file mode 100644 index 00000000..30821a27 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/src/hal_i2c_m_sync.c @@ -0,0 +1,258 @@ +/** + * \file + * + * \brief I/O I2C related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Sync version of I2C I/O read + */ +static int32_t i2c_m_sync_read(struct io_descriptor *io, uint8_t *buf, const uint16_t n) +{ + struct i2c_m_sync_desc *i2c = CONTAINER_OF(io, struct i2c_m_sync_desc, io); + struct _i2c_m_msg msg; + int32_t ret; + + msg.addr = i2c->slave_addr; + msg.len = n; + msg.flags = I2C_M_STOP | I2C_M_RD; + msg.buffer = buf; + + ret = _i2c_m_sync_transfer(&i2c->device, &msg); + + if (ret) { + return ret; + } + + return n; +} + +/** + * \brief Sync version of I2C I/O write + */ +static int32_t i2c_m_sync_write(struct io_descriptor *io, const uint8_t *buf, const uint16_t n) +{ + struct i2c_m_sync_desc *i2c = CONTAINER_OF(io, struct i2c_m_sync_desc, io); + struct _i2c_m_msg msg; + int32_t ret; + + msg.addr = i2c->slave_addr; + msg.len = n; + msg.flags = I2C_M_STOP; + msg.buffer = (uint8_t *)buf; + + ret = _i2c_m_sync_transfer(&i2c->device, &msg); + + if (ret) { + return ret; + } + + return n; +} + +/** + * \brief Sync version of i2c initialize + */ +int32_t i2c_m_sync_init(struct i2c_m_sync_desc *i2c, void *hw) +{ + int32_t init_status; + ASSERT(i2c); + + init_status = _i2c_m_sync_init(&i2c->device, hw); + if (init_status) { + return init_status; + } + + /* Init I/O */ + i2c->io.read = i2c_m_sync_read; + i2c->io.write = i2c_m_sync_write; + + return ERR_NONE; +} + +/** + * \brief deinitialize + */ +int32_t i2c_m_sync_deinit(struct i2c_m_sync_desc *i2c) +{ + int32_t status; + ASSERT(i2c); + + status = _i2c_m_sync_deinit(&i2c->device); + if (status) { + return status; + } + + i2c->io.read = NULL; + i2c->io.write = NULL; + + return ERR_NONE; +} + +/** + * \brief Sync version of i2c enable + */ +int32_t i2c_m_sync_enable(struct i2c_m_sync_desc *i2c) +{ + return _i2c_m_sync_enable(&i2c->device); +} + +/** + * \brief Sync version of i2c disable + */ +int32_t i2c_m_sync_disable(struct i2c_m_sync_desc *i2c) +{ + return _i2c_m_sync_disable(&i2c->device); +} + +/** + * \brief Sync version of i2c set slave address + */ +int32_t i2c_m_sync_set_slaveaddr(struct i2c_m_sync_desc *i2c, int16_t addr, int32_t addr_len) +{ + return i2c->slave_addr = (addr & 0x3ff) | (addr_len & I2C_M_TEN); +} + +/** + * \brief Sync version of i2c set baudrate + */ +int32_t i2c_m_sync_set_baudrate(struct i2c_m_sync_desc *i2c, uint32_t clkrate, uint32_t baudrate) +{ + return _i2c_m_sync_set_baudrate(&i2c->device, clkrate, baudrate); +} + +/** + * \brief Sync version of i2c write command + */ +int32_t i2c_m_sync_cmd_write(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length) +{ + struct _i2c_m_msg msg; + int32_t ret; + + msg.addr = i2c->slave_addr; + msg.len = 1; + msg.flags = 0; + msg.buffer = ® + + ret = _i2c_m_sync_transfer(&i2c->device, &msg); + + if (ret != 0) { + /* error occurred */ + return ret; + } + + msg.flags = I2C_M_STOP; + msg.buffer = buffer; + msg.len = length; + + ret = _i2c_m_sync_transfer(&i2c->device, &msg); + + if (ret != 0) { + /* error occurred */ + return ret; + } + + return ERR_NONE; +} + +/** + * \brief Sync version of i2c read command + */ +int32_t i2c_m_sync_cmd_read(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length) +{ + struct _i2c_m_msg msg; + int32_t ret; + + msg.addr = i2c->slave_addr; + msg.len = 1; + msg.flags = 0; + msg.buffer = ® + + ret = _i2c_m_sync_transfer(&i2c->device, &msg); + + if (ret != 0) { + /* error occurred */ + return ret; + } + + msg.flags = I2C_M_STOP | I2C_M_RD; + msg.buffer = buffer; + msg.len = length; + + ret = _i2c_m_sync_transfer(&i2c->device, &msg); + + if (ret != 0) { + /* error occurred */ + return ret; + } + + return ERR_NONE; +} + +/** + * \brief Sync version of i2c transfer command + */ +int32_t i2c_m_sync_transfer(struct i2c_m_sync_desc *const i2c, struct _i2c_m_msg *msg) +{ + return _i2c_m_sync_transfer(&i2c->device, msg); +} + +/** + * \brief Sync version of i2c send stop condition command + */ +int32_t i2c_m_sync_send_stop(struct i2c_m_sync_desc *const i2c) +{ + return _i2c_m_sync_send_stop(&i2c->device); +} + +/** + * \brief Retrieve I/O descriptor + */ +int32_t i2c_m_sync_get_io_descriptor(struct i2c_m_sync_desc *const i2c, struct io_descriptor **io) +{ + *io = &i2c->io; + return ERR_NONE; +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t i2c_m_sync_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/src/hal_init.c b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/src/hal_init.c new file mode 100644 index 00000000..fb65341f --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/src/hal_init.c @@ -0,0 +1,47 @@ +/** + * \file + * + * \brief HAL initialization related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_init.h" + +/** + * \brief Driver version + */ +#define HAL_INIT_VERSION 0x00000001u + +/** + * \brief Retrieve the current driver version + */ +uint32_t init_get_version(void) +{ + return HAL_INIT_VERSION; +} diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/src/hal_io.c b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/src/hal_io.c new file mode 100644 index 00000000..7e8feb04 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/src/hal_io.c @@ -0,0 +1,63 @@ +/** + * \file + * + * \brief I/O functionality implementation. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +uint32_t io_get_version(void) +{ + return DRIVER_VERSION; +} + +/** + * \brief I/O write interface + */ +int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length) +{ + ASSERT(io_descr && buf); + return io_descr->write(io_descr, buf, length); +} + +/** + * \brief I/O read interface + */ +int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length) +{ + ASSERT(io_descr && buf); + return io_descr->read(io_descr, buf, length); +} diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/src/hal_sleep.c b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/src/hal_sleep.c new file mode 100644 index 00000000..89472f15 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/src/hal_sleep.c @@ -0,0 +1,73 @@ +/** + * \file + * + * \brief Sleep related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_sleep.h" +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Set the sleep mode of the device and put the MCU to sleep + * + * For an overview of which systems are disabled in sleep for the different + * sleep modes, see the data sheet. + * + * \param[in] mode Sleep mode to use + * + * \return The status of a sleep request + * \retval -1 The requested sleep mode was invalid or not available + * \retval 0 The operation completed successfully, returned after leaving the + * sleep + */ +int sleep(const uint8_t mode) +{ + if (ERR_NONE != _set_sleep_mode(mode)) + return ERR_INVALID_ARG; + + _go_to_sleep(); + + return ERR_NONE; +} + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version + */ +uint32_t sleep_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/src/hal_spi_m_sync.c b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/src/hal_spi_m_sync.c new file mode 100644 index 00000000..1a64296a --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/src/hal_spi_m_sync.c @@ -0,0 +1,201 @@ +/** + * \file + * + * \brief I/O SPI related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_spi_m_sync.h" +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Driver version + */ +#define SPI_M_SYNC_DRIVER_VERSION 0x00000001u + +#define SPI_DEACTIVATE_NEXT 0x8000 + +static int32_t _spi_m_sync_io_write(struct io_descriptor *const io, const uint8_t *const buf, const uint16_t length); +static int32_t _spi_m_sync_io_read(struct io_descriptor *const io, uint8_t *const buf, const uint16_t length); + +/** + * \brief Initialize the SPI HAL instance function pointer for HPL APIs. + */ +void spi_m_sync_set_func_ptr(struct spi_m_sync_descriptor *spi, void *const func) +{ + ASSERT(spi); + spi->func = (struct _spi_m_sync_hpl_interface *)func; +} + +int32_t spi_m_sync_init(struct spi_m_sync_descriptor *spi, void *const hw) +{ + int32_t rc = 0; + ASSERT(spi && hw); + spi->dev.prvt = (void *)hw; + rc = _spi_m_sync_init(&spi->dev, hw); + + if (rc < 0) { + return rc; + } + + spi->flags = SPI_DEACTIVATE_NEXT; + spi->io.read = _spi_m_sync_io_read; + spi->io.write = _spi_m_sync_io_write; + + return ERR_NONE; +} + +void spi_m_sync_deinit(struct spi_m_sync_descriptor *spi) +{ + ASSERT(spi); + _spi_m_sync_deinit(&spi->dev); +} + +void spi_m_sync_enable(struct spi_m_sync_descriptor *spi) +{ + ASSERT(spi); + _spi_m_sync_enable(&spi->dev); +} + +void spi_m_sync_disable(struct spi_m_sync_descriptor *spi) +{ + ASSERT(spi); + _spi_m_sync_disable(&spi->dev); +} + +int32_t spi_m_sync_set_baudrate(struct spi_m_sync_descriptor *spi, const uint32_t baud_val) +{ + ASSERT(spi); + return _spi_m_sync_set_baudrate(&spi->dev, baud_val); +} + +int32_t spi_m_sync_set_mode(struct spi_m_sync_descriptor *spi, const enum spi_transfer_mode mode) +{ + ASSERT(spi); + return _spi_m_sync_set_mode(&spi->dev, mode); +} + +int32_t spi_m_sync_set_char_size(struct spi_m_sync_descriptor *spi, const enum spi_char_size char_size) +{ + ASSERT(spi); + return _spi_m_sync_set_char_size(&spi->dev, char_size); +} + +int32_t spi_m_sync_set_data_order(struct spi_m_sync_descriptor *spi, const enum spi_data_order dord) +{ + ASSERT(spi); + return _spi_m_sync_set_data_order(&spi->dev, dord); +} + +/** \brief Do SPI read in polling way + * For SPI master, activate CS, do send 0xFFs and read data, deactivate CS. + * + * It blocks until all data read or error. + * + * \param[in, out] spi Pointer to the HAL SPI instance. + * \param[out] buf Pointer to the buffer to store read data. + * \param[in] size Size of the data in number of characters. + * \return Operation status. + * \retval size Success. + * \retval >=0 Time out, with number of characters read. + */ +static int32_t _spi_m_sync_io_read(struct io_descriptor *io, uint8_t *buf, const uint16_t length) +{ + ASSERT(io); + + struct spi_m_sync_descriptor *spi = CONTAINER_OF(io, struct spi_m_sync_descriptor, io); + struct spi_xfer xfer; + + xfer.rxbuf = buf; + xfer.txbuf = 0; + xfer.size = length; + + return spi_m_sync_transfer(spi, &xfer); +} + +/** \brief Do SPI data write in polling way + * For SPI master, activate CS, do buffer send and deactivate CS. The data back + * is discarded. + * + * The data read back is discarded. + * + * It blocks until all data sent or error. + * + * \param[in, out] spi Pointer to the HAL SPI instance. + * \param[in] p_xfer Pointer to the transfer information (\ref spi_transfer). + * \return Operation status. + * \retval size Success. + * \retval >=0 Timeout, with number of characters transferred. + */ +static int32_t _spi_m_sync_io_write(struct io_descriptor *const io, const uint8_t *const buf, const uint16_t length) +{ + ASSERT(io); + + struct spi_m_sync_descriptor *spi = CONTAINER_OF(io, struct spi_m_sync_descriptor, io); + struct spi_xfer xfer; + + xfer.rxbuf = 0; + xfer.txbuf = (uint8_t *)buf; + xfer.size = length; + + return spi_m_sync_transfer(spi, &xfer); +} + +int32_t spi_m_sync_transfer(struct spi_m_sync_descriptor *spi, const struct spi_xfer *p_xfer) +{ + struct spi_msg msg; + + ASSERT(spi && p_xfer); + + msg.txbuf = p_xfer->txbuf; + msg.rxbuf = p_xfer->rxbuf; + msg.size = p_xfer->size; + return _spi_m_sync_trans(&spi->dev, &msg); +} + +int32_t spi_m_sync_get_io_descriptor(struct spi_m_sync_descriptor *const spi, struct io_descriptor **io) +{ + ASSERT(spi && io); + *io = &spi->io; + return 0; +} + +uint32_t spi_m_sync_get_version(void) +{ + return SPI_M_SYNC_DRIVER_VERSION; +} + +#ifdef __cplusplus +} +#endif diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/src/hal_usart_sync.c b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/src/hal_usart_sync.c new file mode 100644 index 00000000..ab99c1d1 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/src/hal_usart_sync.c @@ -0,0 +1,276 @@ +/** + * \file + * + * \brief I/O USART related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_usart_sync.h" +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +static int32_t usart_sync_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); +static int32_t usart_sync_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); + +/** + * \brief Initialize usart interface + */ +int32_t usart_sync_init(struct usart_sync_descriptor *const descr, void *const hw, void *const func) +{ + int32_t init_status; + ASSERT(descr && hw); + init_status = _usart_sync_init(&descr->device, hw); + if (init_status) { + return init_status; + } + + descr->io.read = usart_sync_read; + descr->io.write = usart_sync_write; + + return ERR_NONE; +} + +/** + * \brief Uninitialize usart interface + */ +int32_t usart_sync_deinit(struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + _usart_sync_deinit(&descr->device); + + descr->io.read = NULL; + descr->io.write = NULL; + + return ERR_NONE; +} + +/** + * \brief Enable usart interface + */ +int32_t usart_sync_enable(struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + _usart_sync_enable(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Disable usart interface + */ +int32_t usart_sync_disable(struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + _usart_sync_disable(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Retrieve I/O descriptor + */ +int32_t usart_sync_get_io_descriptor(struct usart_sync_descriptor *const descr, struct io_descriptor **io) +{ + ASSERT(descr && io); + + *io = &descr->io; + return ERR_NONE; +} + +/** + * \brief Specify action for flow control pins + */ +int32_t usart_sync_set_flow_control(struct usart_sync_descriptor *const descr, + const union usart_flow_control_state state) +{ + ASSERT(descr); + _usart_sync_set_flow_control_state(&descr->device, state); + + return ERR_NONE; +} + +/** + * \brief Set usart baud rate + */ +int32_t usart_sync_set_baud_rate(struct usart_sync_descriptor *const descr, const uint32_t baud_rate) +{ + ASSERT(descr); + _usart_sync_set_baud_rate(&descr->device, baud_rate); + + return ERR_NONE; +} + +/** + * \brief Set usart data order + */ +int32_t usart_sync_set_data_order(struct usart_sync_descriptor *const descr, const enum usart_data_order data_order) +{ + ASSERT(descr); + _usart_sync_set_data_order(&descr->device, data_order); + + return ERR_NONE; +} + +/** + * \brief Set usart mode + */ +int32_t usart_sync_set_mode(struct usart_sync_descriptor *const descr, const enum usart_mode mode) +{ + ASSERT(descr); + _usart_sync_set_mode(&descr->device, mode); + + return ERR_NONE; +} + +/** + * \brief Set usart parity + */ +int32_t usart_sync_set_parity(struct usart_sync_descriptor *const descr, const enum usart_parity parity) +{ + ASSERT(descr); + _usart_sync_set_parity(&descr->device, parity); + + return ERR_NONE; +} + +/** + * \brief Set usart stop bits + */ +int32_t usart_sync_set_stopbits(struct usart_sync_descriptor *const descr, const enum usart_stop_bits stop_bits) +{ + ASSERT(descr); + _usart_sync_set_stop_bits(&descr->device, stop_bits); + + return ERR_NONE; +} + +/** + * \brief Set usart character size + */ +int32_t usart_sync_set_character_size(struct usart_sync_descriptor *const descr, const enum usart_character_size size) +{ + ASSERT(descr); + _usart_sync_set_character_size(&descr->device, size); + + return ERR_NONE; +} + +/** + * \brief Retrieve the state of flow control pins + */ +int32_t usart_sync_flow_control_status(const struct usart_sync_descriptor *const descr, + union usart_flow_control_state *const state) +{ + ASSERT(descr && state); + *state = _usart_sync_get_flow_control_state(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Check if the usart transmitter is empty + */ +int32_t usart_sync_is_tx_empty(const struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + return _usart_sync_is_ready_to_send(&descr->device); +} + +/** + * \brief Check if the usart receiver is not empty + */ +int32_t usart_sync_is_rx_not_empty(const struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + return _usart_sync_is_byte_received(&descr->device); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t usart_sync_get_version(void) +{ + return DRIVER_VERSION; +} + +/* + * \internal Write the given data to usart interface + * + * \param[in] descr The pointer to an io descriptor + * \param[in] buf Data to write to usart + * \param[in] length The number of bytes to write + * + * \return The number of bytes written. + */ +static int32_t usart_sync_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length) +{ + uint32_t offset = 0; + struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io); + + ASSERT(io_descr && buf && length); + while (!_usart_sync_is_ready_to_send(&descr->device)) + ; + do { + _usart_sync_write_byte(&descr->device, buf[offset]); + while (!_usart_sync_is_ready_to_send(&descr->device)) + ; + } while (++offset < length); + while (!_usart_sync_is_transmit_done(&descr->device)) + ; + return (int32_t)offset; +} + +/* + * \internal Read data from usart interface + * + * \param[in] descr The pointer to an io descriptor + * \param[in] buf A buffer to read data to + * \param[in] length The size of a buffer + * + * \return The number of bytes read. + */ +static int32_t usart_sync_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length) +{ + uint32_t offset = 0; + struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io); + + ASSERT(io_descr && buf && length); + do { + while (!_usart_sync_is_byte_received(&descr->device)) + ; + buf[offset] = _usart_sync_read_byte(&descr->device); + } while (++offset < length); + + return (int32_t)offset; +} diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/utils/include/compiler.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/utils/include/compiler.h new file mode 100644 index 00000000..f35db3df --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/utils/include/compiler.h @@ -0,0 +1,64 @@ +/** + * \file + * + * \brief Header + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +/****************************************************************************** + * compiler.h + * + * Created: 05.05.2014 + * Author: N. Fomin + ******************************************************************************/ + +#ifndef _COMPILER_H +#define _COMPILER_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#ifndef _UNIT_TEST_ +#include "parts.h" +#endif +#include "err_codes.h" + +#ifdef __cplusplus +} +#endif + +#endif /* _COMPILER_H */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/utils/include/err_codes.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/utils/include/err_codes.h new file mode 100644 index 00000000..a7aff018 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/utils/include/err_codes.h @@ -0,0 +1,73 @@ +/** + * \file + * + * \brief Error code definitions. + * + * This file defines various status codes returned by functions, + * indicating success or failure as well as what kind of failure. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef ERROR_CODES_H_INCLUDED +#define ERROR_CODES_H_INCLUDED + +#define ERR_NONE 0 +#define ERR_INVALID_DATA -1 +#define ERR_NO_CHANGE -2 +#define ERR_ABORTED -3 +#define ERR_BUSY -4 +#define ERR_SUSPEND -5 +#define ERR_IO -6 +#define ERR_REQ_FLUSHED -7 +#define ERR_TIMEOUT -8 +#define ERR_BAD_DATA -9 +#define ERR_NOT_FOUND -10 +#define ERR_UNSUPPORTED_DEV -11 +#define ERR_NO_MEMORY -12 +#define ERR_INVALID_ARG -13 +#define ERR_BAD_ADDRESS -14 +#define ERR_BAD_FORMAT -15 +#define ERR_BAD_FRQ -16 +#define ERR_DENIED -17 +#define ERR_ALREADY_INITIALIZED -18 +#define ERR_OVERFLOW -19 +#define ERR_NOT_INITIALIZED -20 +#define ERR_SAMPLERATE_UNAVAILABLE -21 +#define ERR_RESOLUTION_UNAVAILABLE -22 +#define ERR_BAUDRATE_UNAVAILABLE -23 +#define ERR_PACKET_COLLISION -24 +#define ERR_PROTOCOL -25 +#define ERR_PIN_MUX_INVALID -26 +#define ERR_UNSUPPORTED_OP -27 +#define ERR_NO_RESOURCE -28 +#define ERR_NOT_READY -29 +#define ERR_FAILURE -30 +#define ERR_WRONG_LENGTH -31 + +#endif diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/utils/include/events.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/utils/include/events.h new file mode 100644 index 00000000..3ee891a7 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/utils/include/events.h @@ -0,0 +1,54 @@ +/** + * \file + * + * \brief Events declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _EVENTS_H_INCLUDED +#define _EVENTS_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * \brief List of events. Must start with 0, be unique and follow numerical order. + */ +#define EVENT_IS_READY_TO_SLEEP_ID 0 +#define EVENT_PREPARE_TO_SLEEP_ID 1 +#define EVENT_WOKEN_UP_ID 2 + +#ifdef __cplusplus +} +#endif + +#endif /* _EVENTS_H_INCLUDED */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/utils/include/parts.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/utils/include/parts.h new file mode 100644 index 00000000..6f45cc99 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/utils/include/parts.h @@ -0,0 +1,41 @@ +/** + * \file + * + * \brief Atmel part identification macros + * + * Copyright (c) 2015-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef ATMEL_PARTS_H +#define ATMEL_PARTS_H + +#include "saml21.h" + +#include "hri_l21b.h" + +#endif /* ATMEL_PARTS_H */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/utils/include/utils.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/utils/include/utils.h new file mode 100644 index 00000000..1cf26996 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/utils/include/utils.h @@ -0,0 +1,368 @@ +/** + * \file + * + * \brief Different macros. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef UTILS_H_INCLUDED +#define UTILS_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_utils_macro + * + * @{ + */ + +/** + * \brief Retrieve pointer to parent structure + */ +#define CONTAINER_OF(ptr, type, field_name) ((type *)(((uint8_t *)ptr) - offsetof(type, field_name))) + +/** + * \brief Retrieve array size + */ +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) + +/** + * \brief Emit the compiler pragma \a arg. + * + * \param[in] arg The pragma directive as it would appear after \e \#pragma + * (i.e. not stringified). + */ +#define COMPILER_PRAGMA(arg) _Pragma(#arg) + +/** + * \def COMPILER_PACK_SET(alignment) + * \brief Set maximum alignment for subsequent struct and union definitions to \a alignment. + */ +#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment)) + +/** + * \def COMPILER_PACK_RESET() + * \brief Set default alignment for subsequent struct and union definitions. + */ +#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack()) + +/** + * \brief Set aligned boundary. + */ +#if defined __GNUC__ +#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) +#elif defined __ICCARM__ +#define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a) +#elif defined __CC_ARM +#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) +#endif + +/** + * \brief Flash located data macros + */ +#if defined __GNUC__ +#define PROGMEM_DECLARE(type, name) const type name +#define PROGMEM_T const +#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) +#define PROGMEM_PTR_T const * +#define PROGMEM_STRING_T const uint8_t * +#elif defined __ICCARM__ +#define PROGMEM_DECLARE(type, name) const type name +#define PROGMEM_T const +#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) +#define PROGMEM_PTR_T const * +#define PROGMEM_STRING_T const uint8_t * +#elif defined __CC_ARM +#define PROGMEM_DECLARE(type, name) const type name +#define PROGMEM_T const +#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) +#define PROGMEM_PTR_T const * +#define PROGMEM_STRING_T const uint8_t * +#endif + +/** + * \brief Optimization + */ +#if defined __GNUC__ +#define OPTIMIZE_HIGH __attribute__((optimize(s))) +#elif defined __CC_ARM +#define OPTIMIZE_HIGH _Pragma("O3") +#elif defined __ICCARM__ +#define OPTIMIZE_HIGH _Pragma("optimize=high") +#endif + +/** + * \brief RAM located function attribute + */ +#if defined(__CC_ARM) /* Keil ?Vision 4 */ +#define RAMFUNC __attribute__((section(".ramfunc"))) +#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */ +#define RAMFUNC __ramfunc +#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */ +#define RAMFUNC __attribute__((section(".ramfunc"))) +#endif + +/** + * \brief No-init section. + * Place a data object or a function in a no-init section. + */ +#if defined(__CC_ARM) +#define NO_INIT(a) __attribute__((zero_init)) +#elif defined(__ICCARM__) +#define NO_INIT(a) __no_init +#elif defined(__GNUC__) +#define NO_INIT(a) __attribute__((section(".no_init"))) +#endif + +/** + * \brief Set user-defined section. + * Place a data object or a function in a user-defined section. + */ +#if defined(__CC_ARM) +#define COMPILER_SECTION(a) __attribute__((__section__(a))) +#elif defined(__ICCARM__) +#define COMPILER_SECTION(a) COMPILER_PRAGMA(location = a) +#elif defined(__GNUC__) +#define COMPILER_SECTION(a) __attribute__((__section__(a))) +#endif + +/** + * \brief Define WEAK attribute. + */ +#if defined(__CC_ARM) /* Keil ?Vision 4 */ +#define WEAK __attribute__((weak)) +#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */ +#define WEAK __weak +#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */ +#define WEAK __attribute__((weak)) +#endif + +/** + * \brief Pointer to function + */ +typedef void (*FUNC_PTR)(void); + +#define LE_BYTE0(a) ((uint8_t)(a)) +#define LE_BYTE1(a) ((uint8_t)((a) >> 8)) +#define LE_BYTE2(a) ((uint8_t)((a) >> 16)) +#define LE_BYTE3(a) ((uint8_t)((a) >> 24)) + +#define LE_2_U16(p) ((p)[0] + ((p)[1] << 8)) +#define LE_2_U32(p) ((p)[0] + ((p)[1] << 8) + ((p)[2] << 16) + ((p)[3] << 24)) + +/** \name Zero-Bit Counting + * + * Under GCC, __builtin_clz and __builtin_ctz behave like macros when + * applied to constant expressions (values known at compile time), so they are + * more optimized than the use of the corresponding assembly instructions and + * they can be used as constant expressions e.g. to initialize objects having + * static storage duration, and like the corresponding assembly instructions + * when applied to non-constant expressions (values unknown at compile time), so + * they are more optimized than an assembly periphrasis. Hence, clz and ctz + * ensure a possible and optimized behavior for both constant and non-constant + * expressions. + * + * @{ */ + +/** \brief Counts the leading zero bits of the given value considered as a 32-bit integer. + * + * \param[in] u Value of which to count the leading zero bits. + * + * \return The count of leading zero bits in \a u. + */ +#if (defined __GNUC__) || (defined __CC_ARM) +#define clz(u) __builtin_clz(u) +#else +#define clz(u) \ + ( \ + ((u) == 0) \ + ? 32 \ + : ((u) & (1ul << 31)) \ + ? 0 \ + : ((u) & (1ul << 30)) \ + ? 1 \ + : ((u) & (1ul << 29)) \ + ? 2 \ + : ((u) & (1ul << 28)) \ + ? 3 \ + : ((u) & (1ul << 27)) \ + ? 4 \ + : ((u) & (1ul << 26)) \ + ? 5 \ + : ((u) & (1ul << 25)) \ + ? 6 \ + : ((u) & (1ul << 24)) \ + ? 7 \ + : ((u) & (1ul << 23)) \ + ? 8 \ + : ((u) & (1ul << 22)) \ + ? 9 \ + : ((u) & (1ul << 21)) \ + ? 10 \ + : ((u) & (1ul << 20)) \ + ? 11 \ + : ((u) & (1ul << 19)) \ + ? 12 \ + : ((u) & (1ul << 18)) \ + ? 13 \ + : ((u) & (1ul << 17)) ? 14 \ + : ((u) & (1ul << 16)) ? 15 \ + : ((u) & (1ul << 15)) ? 16 \ + : ((u) & (1ul << 14)) ? 17 \ + : ((u) & (1ul << 13)) ? 18 \ + : ((u) & (1ul << 12)) ? 19 \ + : ((u) \ + & (1ul \ + << 11)) \ + ? 20 \ + : ((u) \ + & (1ul \ + << 10)) \ + ? 21 \ + : ((u) \ + & (1ul \ + << 9)) \ + ? 22 \ + : ((u) \ + & (1ul \ + << 8)) \ + ? 23 \ + : ((u) & (1ul << 7)) ? 24 \ + : ((u) & (1ul << 6)) ? 25 \ + : ((u) \ + & (1ul \ + << 5)) \ + ? 26 \ + : ((u) & (1ul << 4)) ? 27 \ + : ((u) & (1ul << 3)) ? 28 \ + : ((u) & (1ul << 2)) ? 29 \ + : ( \ + (u) & (1ul << 1)) \ + ? 30 \ + : 31) +#endif + +/** \brief Counts the trailing zero bits of the given value considered as a 32-bit integer. + * + * \param[in] u Value of which to count the trailing zero bits. + * + * \return The count of trailing zero bits in \a u. + */ +#if (defined __GNUC__) || (defined __CC_ARM) +#define ctz(u) __builtin_ctz(u) +#else +#define ctz(u) \ + ( \ + (u) & (1ul << 0) \ + ? 0 \ + : (u) & (1ul << 1) \ + ? 1 \ + : (u) & (1ul << 2) \ + ? 2 \ + : (u) & (1ul << 3) \ + ? 3 \ + : (u) & (1ul << 4) \ + ? 4 \ + : (u) & (1ul << 5) \ + ? 5 \ + : (u) & (1ul << 6) \ + ? 6 \ + : (u) & (1ul << 7) \ + ? 7 \ + : (u) & (1ul << 8) \ + ? 8 \ + : (u) & (1ul << 9) \ + ? 9 \ + : (u) & (1ul << 10) \ + ? 10 \ + : (u) & (1ul << 11) \ + ? 11 \ + : (u) & (1ul << 12) \ + ? 12 \ + : (u) & (1ul << 13) \ + ? 13 \ + : (u) & (1ul << 14) \ + ? 14 \ + : (u) & (1ul << 15) \ + ? 15 \ + : (u) & (1ul << 16) \ + ? 16 \ + : (u) & (1ul << 17) \ + ? 17 \ + : (u) & (1ul << 18) \ + ? 18 \ + : (u) & (1ul << 19) ? 19 \ + : (u) & (1ul << 20) ? 20 \ + : (u) & (1ul << 21) ? 21 \ + : (u) & (1ul << 22) ? 22 \ + : (u) & (1ul << 23) ? 23 \ + : (u) & (1ul << 24) ? 24 \ + : (u) & (1ul << 25) ? 25 \ + : (u) & (1ul << 26) ? 26 \ + : (u) & (1ul << 27) ? 27 \ + : (u) & (1ul << 28) ? 28 : (u) & (1ul << 29) ? 29 : (u) & (1ul << 30) ? 30 : (u) & (1ul << 31) ? 31 : 32) +#endif +/** @} */ + +/** + * \brief Counts the number of bits in a mask (no more than 32 bits) + * \param[in] mask Mask of which to count the bits. + */ +#define size_of_mask(mask) (32 - clz(mask) - ctz(mask)) + +/** + * \brief Retrieve the start position of bits mask (no more than 32 bits) + * \param[in] mask Mask of which to retrieve the start position. + */ +#define pos_of_mask(mask) ctz(mask) + +/** + * \brief Return division result of a/b and round up the result to the closest + * number divisible by "b" + */ +#define round_up(a, b) (((a)-1) / (b) + 1) + +/** + * \brief Get the minimum of x and y + */ +#define min(x, y) ((x) > (y) ? (y) : (x)) + +/** + * \brief Get the maximum of x and y + */ +#define max(x, y) ((x) > (y) ? (x) : (y)) + +/**@}*/ + +#ifdef __cplusplus +} +#endif +#endif /* UTILS_H_INCLUDED */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/utils/include/utils_assert.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/utils/include/utils_assert.h new file mode 100644 index 00000000..c2328d6c --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/utils/include/utils_assert.h @@ -0,0 +1,93 @@ +/** + * \file + * + * \brief Asserts related functionality. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _ASSERT_H_INCLUDED +#define _ASSERT_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#ifndef USE_SIMPLE_ASSERT +//# define USE_SIMPLE_ASSERT +#endif + +/** + * \brief Assert macro + * + * This macro is used to throw asserts. It can be mapped to different function + * based on debug level. + * + * \param[in] condition A condition to be checked; + * assert is thrown if the given condition is false + */ +#define ASSERT(condition) ASSERT_IMPL((condition), __FILE__, __LINE__) + +#ifdef DEBUG + +#ifdef USE_SIMPLE_ASSERT +#define ASSERT_IMPL(condition, file, line) \ + if (!(condition)) \ + __asm("BKPT #0"); +#else +#define ASSERT_IMPL(condition, file, line) assert((condition), file, line) +#endif + +#else /* DEBUG */ + +#ifdef USE_SIMPLE_ASSERT +#define ASSERT_IMPL(condition, file, line) ((void)0) +#else +#define ASSERT_IMPL(condition, file, line) ((void)0) +#endif + +#endif /* DEBUG */ + +/** + * \brief Assert function + * + * This function is used to throw asserts. + * + * \param[in] condition A condition to be checked; assert is thrown if the given + * condition is false + * \param[in] file File name + * \param[in] line Line number + */ +void assert(const bool condition, const char *const file, const int line); + +#ifdef __cplusplus +} +#endif +#endif /* _ASSERT_H_INCLUDED */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/utils/include/utils_event.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/utils/include/utils_event.h new file mode 100644 index 00000000..13067c4f --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/utils/include/utils_event.h @@ -0,0 +1,115 @@ +/** + * \file + * + * \brief Events declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_EVENT_H_INCLUDED +#define _UTILS_EVENT_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +/** + * \brief The maximum amount of events + */ +#define EVENT_MAX_AMOUNT 8 + +/** + * \brief The size of event mask used, it is EVENT_MAX_AMOUNT rounded up to the + * closest number divisible by 8. + */ +#define EVENT_MASK_SIZE (round_up(EVENT_MAX_AMOUNT, 8)) + +/** + * \brief The type of event ID. IDs should start with 0 and be in numerical order. + */ +typedef uint8_t event_id_t; + +/** + * \brief The type of returned parameter. This type is big enough to contain + * pointer to data on any platform. + */ +typedef uintptr_t event_data_t; + +/** + * \brief The type of returned parameter. This type is big enough to contain + * pointer to data on any platform. + */ +typedef void (*event_cb_t)(event_id_t id, event_data_t data); + +/** + * \brief Event structure + */ +struct event { + struct list_element elem; /*! The pointer to next event */ + uint8_t mask[EVENT_MASK_SIZE]; /*! Mask of event IDs callback is called for */ + event_cb_t cb; /*! Callback to be called when an event occurs */ +}; + +/** + * \brief Subscribe to event + * + * \param[in] event The pointer to event structure + * \param[in] id The event ID to subscribe to + * \param[in] cb The callback function to call when the given event occurs + * + * \return The status of subscription + */ +int32_t event_subscribe(struct event *const event, const event_id_t id, event_cb_t cb); + +/** + * \brief Remove event from subscription + * + * \param[in] event The pointer to event structure + * \param[in] id The event ID to remove subscription from + * + * \return The status of subscription removing + */ +int32_t event_unsubscribe(struct event *const event, const event_id_t id); + +/** + * \brief Post event + * + * \param[in] id The event ID to post + * \param[in] data The event data to be passed to event subscribers + */ +void event_post(const event_id_t id, const event_data_t data); + +#ifdef __cplusplus +} +#endif + +#endif /* _UTILS_EVENT_H_INCLUDED */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/utils/include/utils_increment_macro.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/utils/include/utils_increment_macro.h new file mode 100644 index 00000000..464c6cbb --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/utils/include/utils_increment_macro.h @@ -0,0 +1,308 @@ +/** + * \file + * + * \brief Increment macro. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_INCREMENT_MACRO_H +#define _UTILS_INCREMENT_MACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Compile time increment, result value is entire integer literal + * + * \param[in] val - value to be incremented (254 max) + */ +#define INC_VALUE(val) SP_INC_##val + +// Preprocessor increment implementation +#define SP_INC_0 1 +#define SP_INC_1 2 +#define SP_INC_2 3 +#define SP_INC_3 4 +#define SP_INC_4 5 +#define SP_INC_5 6 +#define SP_INC_6 7 +#define SP_INC_7 8 +#define SP_INC_8 9 +#define SP_INC_9 10 +#define SP_INC_10 11 +#define SP_INC_11 12 +#define SP_INC_12 13 +#define SP_INC_13 14 +#define SP_INC_14 15 +#define SP_INC_15 16 +#define SP_INC_16 17 +#define SP_INC_17 18 +#define SP_INC_18 19 +#define SP_INC_19 20 +#define SP_INC_20 21 +#define SP_INC_21 22 +#define SP_INC_22 23 +#define SP_INC_23 24 +#define SP_INC_24 25 +#define SP_INC_25 26 +#define SP_INC_26 27 +#define SP_INC_27 28 +#define SP_INC_28 29 +#define SP_INC_29 30 +#define SP_INC_30 31 +#define SP_INC_31 32 +#define SP_INC_32 33 +#define SP_INC_33 34 +#define SP_INC_34 35 +#define SP_INC_35 36 +#define SP_INC_36 37 +#define SP_INC_37 38 +#define SP_INC_38 39 +#define SP_INC_39 40 +#define SP_INC_40 41 +#define SP_INC_41 42 +#define SP_INC_42 43 +#define SP_INC_43 44 +#define SP_INC_44 45 +#define SP_INC_45 46 +#define SP_INC_46 47 +#define SP_INC_47 48 +#define SP_INC_48 49 +#define SP_INC_49 50 +#define SP_INC_50 51 +#define SP_INC_51 52 +#define SP_INC_52 53 +#define SP_INC_53 54 +#define SP_INC_54 55 +#define SP_INC_55 56 +#define SP_INC_56 57 +#define SP_INC_57 58 +#define SP_INC_58 59 +#define SP_INC_59 60 +#define SP_INC_60 61 +#define SP_INC_61 62 +#define SP_INC_62 63 +#define SP_INC_63 64 +#define SP_INC_64 65 +#define SP_INC_65 66 +#define SP_INC_66 67 +#define SP_INC_67 68 +#define SP_INC_68 69 +#define SP_INC_69 70 +#define SP_INC_70 71 +#define SP_INC_71 72 +#define SP_INC_72 73 +#define SP_INC_73 74 +#define SP_INC_74 75 +#define SP_INC_75 76 +#define SP_INC_76 77 +#define SP_INC_77 78 +#define SP_INC_78 79 +#define SP_INC_79 80 +#define SP_INC_80 81 +#define SP_INC_81 82 +#define SP_INC_82 83 +#define SP_INC_83 84 +#define SP_INC_84 85 +#define SP_INC_85 86 +#define SP_INC_86 87 +#define SP_INC_87 88 +#define SP_INC_88 89 +#define SP_INC_89 90 +#define SP_INC_90 91 +#define SP_INC_91 92 +#define SP_INC_92 93 +#define SP_INC_93 94 +#define SP_INC_94 95 +#define SP_INC_95 96 +#define SP_INC_96 97 +#define SP_INC_97 98 +#define SP_INC_98 99 +#define SP_INC_99 100 +#define SP_INC_100 101 +#define SP_INC_101 102 +#define SP_INC_102 103 +#define SP_INC_103 104 +#define SP_INC_104 105 +#define SP_INC_105 106 +#define SP_INC_106 107 +#define SP_INC_107 108 +#define SP_INC_108 109 +#define SP_INC_109 110 +#define SP_INC_110 111 +#define SP_INC_111 112 +#define SP_INC_112 113 +#define SP_INC_113 114 +#define SP_INC_114 115 +#define SP_INC_115 116 +#define SP_INC_116 117 +#define SP_INC_117 118 +#define SP_INC_118 119 +#define SP_INC_119 120 +#define SP_INC_120 121 +#define SP_INC_121 122 +#define SP_INC_122 123 +#define SP_INC_123 124 +#define SP_INC_124 125 +#define SP_INC_125 126 +#define SP_INC_126 127 +#define SP_INC_127 128 +#define SP_INC_128 129 +#define SP_INC_129 130 +#define SP_INC_130 131 +#define SP_INC_131 132 +#define SP_INC_132 133 +#define SP_INC_133 134 +#define SP_INC_134 135 +#define SP_INC_135 136 +#define SP_INC_136 137 +#define SP_INC_137 138 +#define SP_INC_138 139 +#define SP_INC_139 140 +#define SP_INC_140 141 +#define SP_INC_141 142 +#define SP_INC_142 143 +#define SP_INC_143 144 +#define SP_INC_144 145 +#define SP_INC_145 146 +#define SP_INC_146 147 +#define SP_INC_147 148 +#define SP_INC_148 149 +#define SP_INC_149 150 +#define SP_INC_150 151 +#define SP_INC_151 152 +#define SP_INC_152 153 +#define SP_INC_153 154 +#define SP_INC_154 155 +#define SP_INC_155 156 +#define SP_INC_156 157 +#define SP_INC_157 158 +#define SP_INC_158 159 +#define SP_INC_159 160 +#define SP_INC_160 161 +#define SP_INC_161 162 +#define SP_INC_162 163 +#define SP_INC_163 164 +#define SP_INC_164 165 +#define SP_INC_165 166 +#define SP_INC_166 167 +#define SP_INC_167 168 +#define SP_INC_168 169 +#define SP_INC_169 170 +#define SP_INC_170 171 +#define SP_INC_171 172 +#define SP_INC_172 173 +#define SP_INC_173 174 +#define SP_INC_174 175 +#define SP_INC_175 176 +#define SP_INC_176 177 +#define SP_INC_177 178 +#define SP_INC_178 179 +#define SP_INC_179 180 +#define SP_INC_180 181 +#define SP_INC_181 182 +#define SP_INC_182 183 +#define SP_INC_183 184 +#define SP_INC_184 185 +#define SP_INC_185 186 +#define SP_INC_186 187 +#define SP_INC_187 188 +#define SP_INC_188 189 +#define SP_INC_189 190 +#define SP_INC_190 191 +#define SP_INC_191 192 +#define SP_INC_192 193 +#define SP_INC_193 194 +#define SP_INC_194 195 +#define SP_INC_195 196 +#define SP_INC_196 197 +#define SP_INC_197 198 +#define SP_INC_198 199 +#define SP_INC_199 200 +#define SP_INC_200 201 +#define SP_INC_201 202 +#define SP_INC_202 203 +#define SP_INC_203 204 +#define SP_INC_204 205 +#define SP_INC_205 206 +#define SP_INC_206 207 +#define SP_INC_207 208 +#define SP_INC_208 209 +#define SP_INC_209 210 +#define SP_INC_210 211 +#define SP_INC_211 212 +#define SP_INC_212 213 +#define SP_INC_213 214 +#define SP_INC_214 215 +#define SP_INC_215 216 +#define SP_INC_216 217 +#define SP_INC_217 218 +#define SP_INC_218 219 +#define SP_INC_219 220 +#define SP_INC_220 221 +#define SP_INC_221 222 +#define SP_INC_222 223 +#define SP_INC_223 224 +#define SP_INC_224 225 +#define SP_INC_225 226 +#define SP_INC_226 227 +#define SP_INC_227 228 +#define SP_INC_228 229 +#define SP_INC_229 230 +#define SP_INC_230 231 +#define SP_INC_231 232 +#define SP_INC_232 233 +#define SP_INC_233 234 +#define SP_INC_234 235 +#define SP_INC_235 236 +#define SP_INC_236 237 +#define SP_INC_237 238 +#define SP_INC_238 239 +#define SP_INC_239 240 +#define SP_INC_240 241 +#define SP_INC_241 242 +#define SP_INC_242 243 +#define SP_INC_243 244 +#define SP_INC_244 245 +#define SP_INC_245 246 +#define SP_INC_246 247 +#define SP_INC_247 248 +#define SP_INC_248 249 +#define SP_INC_249 250 +#define SP_INC_250 251 +#define SP_INC_251 252 +#define SP_INC_252 253 +#define SP_INC_253 254 +#define SP_INC_254 255 + +#ifdef __cplusplus +} +#endif +#endif /* _UTILS_INCREMENT_MACRO_H */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/utils/include/utils_list.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/utils/include/utils_list.h new file mode 100644 index 00000000..977e8cca --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/utils/include/utils_list.h @@ -0,0 +1,164 @@ +/** + * \file + * + * \brief List declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_LIST_H_INCLUDED +#define _UTILS_LIST_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_utils_list + * + * @{ + */ + +#include + +/** + * \brief List element type + */ +struct list_element { + struct list_element *next; +}; + +/** + * \brief List head type + */ +struct list_descriptor { + struct list_element *head; +}; + +/** + * \brief Reset list + * + * \param[in] list The pointer to a list descriptor + */ +static inline void list_reset(struct list_descriptor *const list) +{ + list->head = NULL; +} + +/** + * \brief Retrieve list head + * + * \param[in] list The pointer to a list descriptor + * + * \return A pointer to the head of the given list or NULL if the list is + * empty + */ +static inline void *list_get_head(const struct list_descriptor *const list) +{ + return (void *)list->head; +} + +/** + * \brief Retrieve next list head + * + * \param[in] list The pointer to a list element + * + * \return A pointer to the next list element or NULL if there is not next + * element + */ +static inline void *list_get_next_element(const void *const element) +{ + return element ? ((struct list_element *)element)->next : NULL; +} + +/** + * \brief Insert an element as list head + * + * \param[in] list The pointer to a list element + * \param[in] element An element to insert to the given list + */ +void list_insert_as_head(struct list_descriptor *const list, void *const element); + +/** + * \brief Insert an element after the given list element + * + * \param[in] after An element to insert after + * \param[in] element Element to insert to the given list + */ +void list_insert_after(void *const after, void *const element); + +/** + * \brief Insert an element at list end + * + * \param[in] after An element to insert after + * \param[in] element Element to insert to the given list + */ +void list_insert_at_end(struct list_descriptor *const list, void *const element); + +/** + * \brief Check whether an element belongs to a list + * + * \param[in] list The pointer to a list + * \param[in] element An element to check + * + * \return The result of checking + * \retval true If the given element is an element of the given list + * \retval false Otherwise + */ +bool is_list_element(const struct list_descriptor *const list, const void *const element); + +/** + * \brief Removes list head + * + * This function removes the list head and sets the next element after the list + * head as a new list head. + * + * \param[in] list The pointer to a list + * + * \return The pointer to the new list head of NULL if the list head is NULL + */ +void *list_remove_head(struct list_descriptor *const list); + +/** + * \brief Removes the list element + * + * \param[in] list The pointer to a list + * \param[in] element An element to remove + * + * \return The result of element removing + * \retval true The given element is removed from the given list + * \retval false The given element is not an element of the given list + */ +bool list_delete_element(struct list_descriptor *const list, const void *const element); + +/**@}*/ + +#ifdef __cplusplus +} +#endif +#endif /* _UTILS_LIST_H_INCLUDED */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/utils/include/utils_repeat_macro.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/utils/include/utils_repeat_macro.h new file mode 100644 index 00000000..89e6f52d --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/utils/include/utils_repeat_macro.h @@ -0,0 +1,322 @@ +/** + * \file + * + * \brief Repeat macro. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_REPEAT_MACRO_H +#define _UTILS_REPEAT_MACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * \brief Sequently repeates specified macro for n times (255 max). + * + * Specified macro shall have two arguments: macro(arg, i) + * arg - user defined argument, which have the same value for all iterations. + * i - iteration number; numbering begins from zero and increments on each + * iteration. + * + * \param[in] macro - macro to be repeated + * \param[in] arg - user defined argument for repeated macro + * \param[in] n - total number of iterations (255 max) + */ +#define REPEAT_MACRO(macro, arg, n) REPEAT_MACRO_I(macro, arg, n) + +/* + * \brief Second level is needed to get integer literal from "n" if it is + * defined as macro + */ +#define REPEAT_MACRO_I(macro, arg, n) REPEAT##n(macro, arg, 0) + +#define REPEAT1(macro, arg, n) macro(arg, n) +#define REPEAT2(macro, arg, n) macro(arg, n) REPEAT1(macro, arg, INC_VALUE(n)) +#define REPEAT3(macro, arg, n) macro(arg, n) REPEAT2(macro, arg, INC_VALUE(n)) +#define REPEAT4(macro, arg, n) macro(arg, n) REPEAT3(macro, arg, INC_VALUE(n)) +#define REPEAT5(macro, arg, n) macro(arg, n) REPEAT4(macro, arg, INC_VALUE(n)) +#define REPEAT6(macro, arg, n) macro(arg, n) REPEAT5(macro, arg, INC_VALUE(n)) +#define REPEAT7(macro, arg, n) macro(arg, n) REPEAT6(macro, arg, INC_VALUE(n)) +#define REPEAT8(macro, arg, n) macro(arg, n) REPEAT7(macro, arg, INC_VALUE(n)) +#define REPEAT9(macro, arg, n) macro(arg, n) REPEAT8(macro, arg, INC_VALUE(n)) +#define REPEAT10(macro, arg, n) macro(arg, n) REPEAT9(macro, arg, INC_VALUE(n)) +#define REPEAT11(macro, arg, n) macro(arg, n) REPEAT10(macro, arg, INC_VALUE(n)) +#define REPEAT12(macro, arg, n) macro(arg, n) REPEAT11(macro, arg, INC_VALUE(n)) +#define REPEAT13(macro, arg, n) macro(arg, n) REPEAT12(macro, arg, INC_VALUE(n)) +#define REPEAT14(macro, arg, n) macro(arg, n) REPEAT13(macro, arg, INC_VALUE(n)) +#define REPEAT15(macro, arg, n) macro(arg, n) REPEAT14(macro, arg, INC_VALUE(n)) +#define REPEAT16(macro, arg, n) macro(arg, n) REPEAT15(macro, arg, INC_VALUE(n)) +#define REPEAT17(macro, arg, n) macro(arg, n) REPEAT16(macro, arg, INC_VALUE(n)) +#define REPEAT18(macro, arg, n) macro(arg, n) REPEAT17(macro, arg, INC_VALUE(n)) +#define REPEAT19(macro, arg, n) macro(arg, n) REPEAT18(macro, arg, INC_VALUE(n)) +#define REPEAT20(macro, arg, n) macro(arg, n) REPEAT19(macro, arg, INC_VALUE(n)) +#define REPEAT21(macro, arg, n) macro(arg, n) REPEAT20(macro, arg, INC_VALUE(n)) +#define REPEAT22(macro, arg, n) macro(arg, n) REPEAT21(macro, arg, INC_VALUE(n)) +#define REPEAT23(macro, arg, n) macro(arg, n) REPEAT22(macro, arg, INC_VALUE(n)) +#define REPEAT24(macro, arg, n) macro(arg, n) REPEAT23(macro, arg, INC_VALUE(n)) +#define REPEAT25(macro, arg, n) macro(arg, n) REPEAT24(macro, arg, INC_VALUE(n)) +#define REPEAT26(macro, arg, n) macro(arg, n) REPEAT25(macro, arg, INC_VALUE(n)) +#define REPEAT27(macro, arg, n) macro(arg, n) REPEAT26(macro, arg, INC_VALUE(n)) +#define REPEAT28(macro, arg, n) macro(arg, n) REPEAT27(macro, arg, INC_VALUE(n)) +#define REPEAT29(macro, arg, n) macro(arg, n) REPEAT28(macro, arg, INC_VALUE(n)) +#define REPEAT30(macro, arg, n) macro(arg, n) REPEAT29(macro, arg, INC_VALUE(n)) +#define REPEAT31(macro, arg, n) macro(arg, n) REPEAT30(macro, arg, INC_VALUE(n)) +#define REPEAT32(macro, arg, n) macro(arg, n) REPEAT31(macro, arg, INC_VALUE(n)) +#define REPEAT33(macro, arg, n) macro(arg, n) REPEAT32(macro, arg, INC_VALUE(n)) +#define REPEAT34(macro, arg, n) macro(arg, n) REPEAT33(macro, arg, INC_VALUE(n)) +#define REPEAT35(macro, arg, n) macro(arg, n) REPEAT34(macro, arg, INC_VALUE(n)) +#define REPEAT36(macro, arg, n) macro(arg, n) REPEAT35(macro, arg, INC_VALUE(n)) +#define REPEAT37(macro, arg, n) macro(arg, n) REPEAT36(macro, arg, INC_VALUE(n)) +#define REPEAT38(macro, arg, n) macro(arg, n) REPEAT37(macro, arg, INC_VALUE(n)) +#define REPEAT39(macro, arg, n) macro(arg, n) REPEAT38(macro, arg, INC_VALUE(n)) +#define REPEAT40(macro, arg, n) macro(arg, n) REPEAT39(macro, arg, INC_VALUE(n)) +#define REPEAT41(macro, arg, n) macro(arg, n) REPEAT40(macro, arg, INC_VALUE(n)) +#define REPEAT42(macro, arg, n) macro(arg, n) REPEAT41(macro, arg, INC_VALUE(n)) +#define REPEAT43(macro, arg, n) macro(arg, n) REPEAT42(macro, arg, INC_VALUE(n)) +#define REPEAT44(macro, arg, n) macro(arg, n) REPEAT43(macro, arg, INC_VALUE(n)) +#define REPEAT45(macro, arg, n) macro(arg, n) REPEAT44(macro, arg, INC_VALUE(n)) +#define REPEAT46(macro, arg, n) macro(arg, n) REPEAT45(macro, arg, INC_VALUE(n)) +#define REPEAT47(macro, arg, n) macro(arg, n) REPEAT46(macro, arg, INC_VALUE(n)) +#define REPEAT48(macro, arg, n) macro(arg, n) REPEAT47(macro, arg, INC_VALUE(n)) +#define REPEAT49(macro, arg, n) macro(arg, n) REPEAT48(macro, arg, INC_VALUE(n)) +#define REPEAT50(macro, arg, n) macro(arg, n) REPEAT49(macro, arg, INC_VALUE(n)) +#define REPEAT51(macro, arg, n) macro(arg, n) REPEAT50(macro, arg, INC_VALUE(n)) +#define REPEAT52(macro, arg, n) macro(arg, n) REPEAT51(macro, arg, INC_VALUE(n)) +#define REPEAT53(macro, arg, n) macro(arg, n) REPEAT52(macro, arg, INC_VALUE(n)) +#define REPEAT54(macro, arg, n) macro(arg, n) REPEAT53(macro, arg, INC_VALUE(n)) +#define REPEAT55(macro, arg, n) macro(arg, n) REPEAT54(macro, arg, INC_VALUE(n)) +#define REPEAT56(macro, arg, n) macro(arg, n) REPEAT55(macro, arg, INC_VALUE(n)) +#define REPEAT57(macro, arg, n) macro(arg, n) REPEAT56(macro, arg, INC_VALUE(n)) +#define REPEAT58(macro, arg, n) macro(arg, n) REPEAT57(macro, arg, INC_VALUE(n)) +#define REPEAT59(macro, arg, n) macro(arg, n) REPEAT58(macro, arg, INC_VALUE(n)) +#define REPEAT60(macro, arg, n) macro(arg, n) REPEAT59(macro, arg, INC_VALUE(n)) +#define REPEAT61(macro, arg, n) macro(arg, n) REPEAT60(macro, arg, INC_VALUE(n)) +#define REPEAT62(macro, arg, n) macro(arg, n) REPEAT61(macro, arg, INC_VALUE(n)) +#define REPEAT63(macro, arg, n) macro(arg, n) REPEAT62(macro, arg, INC_VALUE(n)) +#define REPEAT64(macro, arg, n) macro(arg, n) REPEAT63(macro, arg, INC_VALUE(n)) +#define REPEAT65(macro, arg, n) macro(arg, n) REPEAT64(macro, arg, INC_VALUE(n)) +#define REPEAT66(macro, arg, n) macro(arg, n) REPEAT65(macro, arg, INC_VALUE(n)) +#define REPEAT67(macro, arg, n) macro(arg, n) REPEAT66(macro, arg, INC_VALUE(n)) +#define REPEAT68(macro, arg, n) macro(arg, n) REPEAT67(macro, arg, INC_VALUE(n)) +#define REPEAT69(macro, arg, n) macro(arg, n) REPEAT68(macro, arg, INC_VALUE(n)) +#define REPEAT70(macro, arg, n) macro(arg, n) REPEAT69(macro, arg, INC_VALUE(n)) +#define REPEAT71(macro, arg, n) macro(arg, n) REPEAT70(macro, arg, INC_VALUE(n)) +#define REPEAT72(macro, arg, n) macro(arg, n) REPEAT71(macro, arg, INC_VALUE(n)) +#define REPEAT73(macro, arg, n) macro(arg, n) REPEAT72(macro, arg, INC_VALUE(n)) +#define REPEAT74(macro, arg, n) macro(arg, n) REPEAT73(macro, arg, INC_VALUE(n)) +#define REPEAT75(macro, arg, n) macro(arg, n) REPEAT74(macro, arg, INC_VALUE(n)) +#define REPEAT76(macro, arg, n) macro(arg, n) REPEAT75(macro, arg, INC_VALUE(n)) +#define REPEAT77(macro, arg, n) macro(arg, n) REPEAT76(macro, arg, INC_VALUE(n)) +#define REPEAT78(macro, arg, n) macro(arg, n) REPEAT77(macro, arg, INC_VALUE(n)) +#define REPEAT79(macro, arg, n) macro(arg, n) REPEAT78(macro, arg, INC_VALUE(n)) +#define REPEAT80(macro, arg, n) macro(arg, n) REPEAT79(macro, arg, INC_VALUE(n)) +#define REPEAT81(macro, arg, n) macro(arg, n) REPEAT80(macro, arg, INC_VALUE(n)) +#define REPEAT82(macro, arg, n) macro(arg, n) REPEAT81(macro, arg, INC_VALUE(n)) +#define REPEAT83(macro, arg, n) macro(arg, n) REPEAT82(macro, arg, INC_VALUE(n)) +#define REPEAT84(macro, arg, n) macro(arg, n) REPEAT83(macro, arg, INC_VALUE(n)) +#define REPEAT85(macro, arg, n) macro(arg, n) REPEAT84(macro, arg, INC_VALUE(n)) +#define REPEAT86(macro, arg, n) macro(arg, n) REPEAT85(macro, arg, INC_VALUE(n)) +#define REPEAT87(macro, arg, n) macro(arg, n) REPEAT86(macro, arg, INC_VALUE(n)) +#define REPEAT88(macro, arg, n) macro(arg, n) REPEAT87(macro, arg, INC_VALUE(n)) +#define REPEAT89(macro, arg, n) macro(arg, n) REPEAT88(macro, arg, INC_VALUE(n)) +#define REPEAT90(macro, arg, n) macro(arg, n) REPEAT89(macro, arg, INC_VALUE(n)) +#define REPEAT91(macro, arg, n) macro(arg, n) REPEAT90(macro, arg, INC_VALUE(n)) +#define REPEAT92(macro, arg, n) macro(arg, n) REPEAT91(macro, arg, INC_VALUE(n)) +#define REPEAT93(macro, arg, n) macro(arg, n) REPEAT92(macro, arg, INC_VALUE(n)) +#define REPEAT94(macro, arg, n) macro(arg, n) REPEAT93(macro, arg, INC_VALUE(n)) +#define REPEAT95(macro, arg, n) macro(arg, n) REPEAT94(macro, arg, INC_VALUE(n)) +#define REPEAT96(macro, arg, n) macro(arg, n) REPEAT95(macro, arg, INC_VALUE(n)) +#define REPEAT97(macro, arg, n) macro(arg, n) REPEAT96(macro, arg, INC_VALUE(n)) +#define REPEAT98(macro, arg, n) macro(arg, n) REPEAT97(macro, arg, INC_VALUE(n)) +#define REPEAT99(macro, arg, n) macro(arg, n) REPEAT98(macro, arg, INC_VALUE(n)) +#define REPEAT100(macro, arg, n) macro(arg, n) REPEAT99(macro, arg, INC_VALUE(n)) +#define REPEAT101(macro, arg, n) macro(arg, n) REPEAT100(macro, arg, INC_VALUE(n)) +#define REPEAT102(macro, arg, n) macro(arg, n) REPEAT101(macro, arg, INC_VALUE(n)) +#define REPEAT103(macro, arg, n) macro(arg, n) REPEAT102(macro, arg, INC_VALUE(n)) +#define REPEAT104(macro, arg, n) macro(arg, n) REPEAT103(macro, arg, INC_VALUE(n)) +#define REPEAT105(macro, arg, n) macro(arg, n) REPEAT104(macro, arg, INC_VALUE(n)) +#define REPEAT106(macro, arg, n) macro(arg, n) REPEAT105(macro, arg, INC_VALUE(n)) +#define REPEAT107(macro, arg, n) macro(arg, n) REPEAT106(macro, arg, INC_VALUE(n)) +#define REPEAT108(macro, arg, n) macro(arg, n) REPEAT107(macro, arg, INC_VALUE(n)) +#define REPEAT109(macro, arg, n) macro(arg, n) REPEAT108(macro, arg, INC_VALUE(n)) +#define REPEAT110(macro, arg, n) macro(arg, n) REPEAT109(macro, arg, INC_VALUE(n)) +#define REPEAT111(macro, arg, n) macro(arg, n) REPEAT110(macro, arg, INC_VALUE(n)) +#define REPEAT112(macro, arg, n) macro(arg, n) REPEAT111(macro, arg, INC_VALUE(n)) +#define REPEAT113(macro, arg, n) macro(arg, n) REPEAT112(macro, arg, INC_VALUE(n)) +#define REPEAT114(macro, arg, n) macro(arg, n) REPEAT113(macro, arg, INC_VALUE(n)) +#define REPEAT115(macro, arg, n) macro(arg, n) REPEAT114(macro, arg, INC_VALUE(n)) +#define REPEAT116(macro, arg, n) macro(arg, n) REPEAT115(macro, arg, INC_VALUE(n)) +#define REPEAT117(macro, arg, n) macro(arg, n) REPEAT116(macro, arg, INC_VALUE(n)) +#define REPEAT118(macro, arg, n) macro(arg, n) REPEAT117(macro, arg, INC_VALUE(n)) +#define REPEAT119(macro, arg, n) macro(arg, n) REPEAT118(macro, arg, INC_VALUE(n)) +#define REPEAT120(macro, arg, n) macro(arg, n) REPEAT119(macro, arg, INC_VALUE(n)) +#define REPEAT121(macro, arg, n) macro(arg, n) REPEAT120(macro, arg, INC_VALUE(n)) +#define REPEAT122(macro, arg, n) macro(arg, n) REPEAT121(macro, arg, INC_VALUE(n)) +#define REPEAT123(macro, arg, n) macro(arg, n) REPEAT122(macro, arg, INC_VALUE(n)) +#define REPEAT124(macro, arg, n) macro(arg, n) REPEAT123(macro, arg, INC_VALUE(n)) +#define REPEAT125(macro, arg, n) macro(arg, n) REPEAT124(macro, arg, INC_VALUE(n)) +#define REPEAT126(macro, arg, n) macro(arg, n) REPEAT125(macro, arg, INC_VALUE(n)) +#define REPEAT127(macro, arg, n) macro(arg, n) REPEAT126(macro, arg, INC_VALUE(n)) +#define REPEAT128(macro, arg, n) macro(arg, n) REPEAT127(macro, arg, INC_VALUE(n)) +#define REPEAT129(macro, arg, n) macro(arg, n) REPEAT128(macro, arg, INC_VALUE(n)) +#define REPEAT130(macro, arg, n) macro(arg, n) REPEAT129(macro, arg, INC_VALUE(n)) +#define REPEAT131(macro, arg, n) macro(arg, n) REPEAT130(macro, arg, INC_VALUE(n)) +#define REPEAT132(macro, arg, n) macro(arg, n) REPEAT131(macro, arg, INC_VALUE(n)) +#define REPEAT133(macro, arg, n) macro(arg, n) REPEAT132(macro, arg, INC_VALUE(n)) +#define REPEAT134(macro, arg, n) macro(arg, n) REPEAT133(macro, arg, INC_VALUE(n)) +#define REPEAT135(macro, arg, n) macro(arg, n) REPEAT134(macro, arg, INC_VALUE(n)) +#define REPEAT136(macro, arg, n) macro(arg, n) REPEAT135(macro, arg, INC_VALUE(n)) +#define REPEAT137(macro, arg, n) macro(arg, n) REPEAT136(macro, arg, INC_VALUE(n)) +#define REPEAT138(macro, arg, n) macro(arg, n) REPEAT137(macro, arg, INC_VALUE(n)) +#define REPEAT139(macro, arg, n) macro(arg, n) REPEAT138(macro, arg, INC_VALUE(n)) +#define REPEAT140(macro, arg, n) macro(arg, n) REPEAT139(macro, arg, INC_VALUE(n)) +#define REPEAT141(macro, arg, n) macro(arg, n) REPEAT140(macro, arg, INC_VALUE(n)) +#define REPEAT142(macro, arg, n) macro(arg, n) REPEAT141(macro, arg, INC_VALUE(n)) +#define REPEAT143(macro, arg, n) macro(arg, n) REPEAT142(macro, arg, INC_VALUE(n)) +#define REPEAT144(macro, arg, n) macro(arg, n) REPEAT143(macro, arg, INC_VALUE(n)) +#define REPEAT145(macro, arg, n) macro(arg, n) REPEAT144(macro, arg, INC_VALUE(n)) +#define REPEAT146(macro, arg, n) macro(arg, n) REPEAT145(macro, arg, INC_VALUE(n)) +#define REPEAT147(macro, arg, n) macro(arg, n) REPEAT146(macro, arg, INC_VALUE(n)) +#define REPEAT148(macro, arg, n) macro(arg, n) REPEAT147(macro, arg, INC_VALUE(n)) +#define REPEAT149(macro, arg, n) macro(arg, n) REPEAT148(macro, arg, INC_VALUE(n)) +#define REPEAT150(macro, arg, n) macro(arg, n) REPEAT149(macro, arg, INC_VALUE(n)) +#define REPEAT151(macro, arg, n) macro(arg, n) REPEAT150(macro, arg, INC_VALUE(n)) +#define REPEAT152(macro, arg, n) macro(arg, n) REPEAT151(macro, arg, INC_VALUE(n)) +#define REPEAT153(macro, arg, n) macro(arg, n) REPEAT152(macro, arg, INC_VALUE(n)) +#define REPEAT154(macro, arg, n) macro(arg, n) REPEAT153(macro, arg, INC_VALUE(n)) +#define REPEAT155(macro, arg, n) macro(arg, n) REPEAT154(macro, arg, INC_VALUE(n)) +#define REPEAT156(macro, arg, n) macro(arg, n) REPEAT155(macro, arg, INC_VALUE(n)) +#define REPEAT157(macro, arg, n) macro(arg, n) REPEAT156(macro, arg, INC_VALUE(n)) +#define REPEAT158(macro, arg, n) macro(arg, n) REPEAT157(macro, arg, INC_VALUE(n)) +#define REPEAT159(macro, arg, n) macro(arg, n) REPEAT158(macro, arg, INC_VALUE(n)) +#define REPEAT160(macro, arg, n) macro(arg, n) REPEAT159(macro, arg, INC_VALUE(n)) +#define REPEAT161(macro, arg, n) macro(arg, n) REPEAT160(macro, arg, INC_VALUE(n)) +#define REPEAT162(macro, arg, n) macro(arg, n) REPEAT161(macro, arg, INC_VALUE(n)) +#define REPEAT163(macro, arg, n) macro(arg, n) REPEAT162(macro, arg, INC_VALUE(n)) +#define REPEAT164(macro, arg, n) macro(arg, n) REPEAT163(macro, arg, INC_VALUE(n)) +#define REPEAT165(macro, arg, n) macro(arg, n) REPEAT164(macro, arg, INC_VALUE(n)) +#define REPEAT166(macro, arg, n) macro(arg, n) REPEAT165(macro, arg, INC_VALUE(n)) +#define REPEAT167(macro, arg, n) macro(arg, n) REPEAT166(macro, arg, INC_VALUE(n)) +#define REPEAT168(macro, arg, n) macro(arg, n) REPEAT167(macro, arg, INC_VALUE(n)) +#define REPEAT169(macro, arg, n) macro(arg, n) REPEAT168(macro, arg, INC_VALUE(n)) +#define REPEAT170(macro, arg, n) macro(arg, n) REPEAT169(macro, arg, INC_VALUE(n)) +#define REPEAT171(macro, arg, n) macro(arg, n) REPEAT170(macro, arg, INC_VALUE(n)) +#define REPEAT172(macro, arg, n) macro(arg, n) REPEAT171(macro, arg, INC_VALUE(n)) +#define REPEAT173(macro, arg, n) macro(arg, n) REPEAT172(macro, arg, INC_VALUE(n)) +#define REPEAT174(macro, arg, n) macro(arg, n) REPEAT173(macro, arg, INC_VALUE(n)) +#define REPEAT175(macro, arg, n) macro(arg, n) REPEAT174(macro, arg, INC_VALUE(n)) +#define REPEAT176(macro, arg, n) macro(arg, n) REPEAT175(macro, arg, INC_VALUE(n)) +#define REPEAT177(macro, arg, n) macro(arg, n) REPEAT176(macro, arg, INC_VALUE(n)) +#define REPEAT178(macro, arg, n) macro(arg, n) REPEAT177(macro, arg, INC_VALUE(n)) +#define REPEAT179(macro, arg, n) macro(arg, n) REPEAT178(macro, arg, INC_VALUE(n)) +#define REPEAT180(macro, arg, n) macro(arg, n) REPEAT179(macro, arg, INC_VALUE(n)) +#define REPEAT181(macro, arg, n) macro(arg, n) REPEAT180(macro, arg, INC_VALUE(n)) +#define REPEAT182(macro, arg, n) macro(arg, n) REPEAT181(macro, arg, INC_VALUE(n)) +#define REPEAT183(macro, arg, n) macro(arg, n) REPEAT182(macro, arg, INC_VALUE(n)) +#define REPEAT184(macro, arg, n) macro(arg, n) REPEAT183(macro, arg, INC_VALUE(n)) +#define REPEAT185(macro, arg, n) macro(arg, n) REPEAT184(macro, arg, INC_VALUE(n)) +#define REPEAT186(macro, arg, n) macro(arg, n) REPEAT185(macro, arg, INC_VALUE(n)) +#define REPEAT187(macro, arg, n) macro(arg, n) REPEAT186(macro, arg, INC_VALUE(n)) +#define REPEAT188(macro, arg, n) macro(arg, n) REPEAT187(macro, arg, INC_VALUE(n)) +#define REPEAT189(macro, arg, n) macro(arg, n) REPEAT188(macro, arg, INC_VALUE(n)) +#define REPEAT190(macro, arg, n) macro(arg, n) REPEAT189(macro, arg, INC_VALUE(n)) +#define REPEAT191(macro, arg, n) macro(arg, n) REPEAT190(macro, arg, INC_VALUE(n)) +#define REPEAT192(macro, arg, n) macro(arg, n) REPEAT191(macro, arg, INC_VALUE(n)) +#define REPEAT193(macro, arg, n) macro(arg, n) REPEAT192(macro, arg, INC_VALUE(n)) +#define REPEAT194(macro, arg, n) macro(arg, n) REPEAT193(macro, arg, INC_VALUE(n)) +#define REPEAT195(macro, arg, n) macro(arg, n) REPEAT194(macro, arg, INC_VALUE(n)) +#define REPEAT196(macro, arg, n) macro(arg, n) REPEAT195(macro, arg, INC_VALUE(n)) +#define REPEAT197(macro, arg, n) macro(arg, n) REPEAT196(macro, arg, INC_VALUE(n)) +#define REPEAT198(macro, arg, n) macro(arg, n) REPEAT197(macro, arg, INC_VALUE(n)) +#define REPEAT199(macro, arg, n) macro(arg, n) REPEAT198(macro, arg, INC_VALUE(n)) +#define REPEAT200(macro, arg, n) macro(arg, n) REPEAT199(macro, arg, INC_VALUE(n)) +#define REPEAT201(macro, arg, n) macro(arg, n) REPEAT200(macro, arg, INC_VALUE(n)) +#define REPEAT202(macro, arg, n) macro(arg, n) REPEAT201(macro, arg, INC_VALUE(n)) +#define REPEAT203(macro, arg, n) macro(arg, n) REPEAT202(macro, arg, INC_VALUE(n)) +#define REPEAT204(macro, arg, n) macro(arg, n) REPEAT203(macro, arg, INC_VALUE(n)) +#define REPEAT205(macro, arg, n) macro(arg, n) REPEAT204(macro, arg, INC_VALUE(n)) +#define REPEAT206(macro, arg, n) macro(arg, n) REPEAT205(macro, arg, INC_VALUE(n)) +#define REPEAT207(macro, arg, n) macro(arg, n) REPEAT206(macro, arg, INC_VALUE(n)) +#define REPEAT208(macro, arg, n) macro(arg, n) REPEAT207(macro, arg, INC_VALUE(n)) +#define REPEAT209(macro, arg, n) macro(arg, n) REPEAT208(macro, arg, INC_VALUE(n)) +#define REPEAT210(macro, arg, n) macro(arg, n) REPEAT209(macro, arg, INC_VALUE(n)) +#define REPEAT211(macro, arg, n) macro(arg, n) REPEAT210(macro, arg, INC_VALUE(n)) +#define REPEAT212(macro, arg, n) macro(arg, n) REPEAT211(macro, arg, INC_VALUE(n)) +#define REPEAT213(macro, arg, n) macro(arg, n) REPEAT212(macro, arg, INC_VALUE(n)) +#define REPEAT214(macro, arg, n) macro(arg, n) REPEAT213(macro, arg, INC_VALUE(n)) +#define REPEAT215(macro, arg, n) macro(arg, n) REPEAT214(macro, arg, INC_VALUE(n)) +#define REPEAT216(macro, arg, n) macro(arg, n) REPEAT215(macro, arg, INC_VALUE(n)) +#define REPEAT217(macro, arg, n) macro(arg, n) REPEAT216(macro, arg, INC_VALUE(n)) +#define REPEAT218(macro, arg, n) macro(arg, n) REPEAT217(macro, arg, INC_VALUE(n)) +#define REPEAT219(macro, arg, n) macro(arg, n) REPEAT218(macro, arg, INC_VALUE(n)) +#define REPEAT220(macro, arg, n) macro(arg, n) REPEAT219(macro, arg, INC_VALUE(n)) +#define REPEAT221(macro, arg, n) macro(arg, n) REPEAT220(macro, arg, INC_VALUE(n)) +#define REPEAT222(macro, arg, n) macro(arg, n) REPEAT221(macro, arg, INC_VALUE(n)) +#define REPEAT223(macro, arg, n) macro(arg, n) REPEAT222(macro, arg, INC_VALUE(n)) +#define REPEAT224(macro, arg, n) macro(arg, n) REPEAT223(macro, arg, INC_VALUE(n)) +#define REPEAT225(macro, arg, n) macro(arg, n) REPEAT224(macro, arg, INC_VALUE(n)) +#define REPEAT226(macro, arg, n) macro(arg, n) REPEAT225(macro, arg, INC_VALUE(n)) +#define REPEAT227(macro, arg, n) macro(arg, n) REPEAT226(macro, arg, INC_VALUE(n)) +#define REPEAT228(macro, arg, n) macro(arg, n) REPEAT227(macro, arg, INC_VALUE(n)) +#define REPEAT229(macro, arg, n) macro(arg, n) REPEAT228(macro, arg, INC_VALUE(n)) +#define REPEAT230(macro, arg, n) macro(arg, n) REPEAT229(macro, arg, INC_VALUE(n)) +#define REPEAT231(macro, arg, n) macro(arg, n) REPEAT230(macro, arg, INC_VALUE(n)) +#define REPEAT232(macro, arg, n) macro(arg, n) REPEAT231(macro, arg, INC_VALUE(n)) +#define REPEAT233(macro, arg, n) macro(arg, n) REPEAT232(macro, arg, INC_VALUE(n)) +#define REPEAT234(macro, arg, n) macro(arg, n) REPEAT233(macro, arg, INC_VALUE(n)) +#define REPEAT235(macro, arg, n) macro(arg, n) REPEAT234(macro, arg, INC_VALUE(n)) +#define REPEAT236(macro, arg, n) macro(arg, n) REPEAT235(macro, arg, INC_VALUE(n)) +#define REPEAT237(macro, arg, n) macro(arg, n) REPEAT236(macro, arg, INC_VALUE(n)) +#define REPEAT238(macro, arg, n) macro(arg, n) REPEAT237(macro, arg, INC_VALUE(n)) +#define REPEAT239(macro, arg, n) macro(arg, n) REPEAT238(macro, arg, INC_VALUE(n)) +#define REPEAT240(macro, arg, n) macro(arg, n) REPEAT239(macro, arg, INC_VALUE(n)) +#define REPEAT241(macro, arg, n) macro(arg, n) REPEAT240(macro, arg, INC_VALUE(n)) +#define REPEAT242(macro, arg, n) macro(arg, n) REPEAT241(macro, arg, INC_VALUE(n)) +#define REPEAT243(macro, arg, n) macro(arg, n) REPEAT242(macro, arg, INC_VALUE(n)) +#define REPEAT244(macro, arg, n) macro(arg, n) REPEAT243(macro, arg, INC_VALUE(n)) +#define REPEAT245(macro, arg, n) macro(arg, n) REPEAT244(macro, arg, INC_VALUE(n)) +#define REPEAT246(macro, arg, n) macro(arg, n) REPEAT245(macro, arg, INC_VALUE(n)) +#define REPEAT247(macro, arg, n) macro(arg, n) REPEAT246(macro, arg, INC_VALUE(n)) +#define REPEAT248(macro, arg, n) macro(arg, n) REPEAT247(macro, arg, INC_VALUE(n)) +#define REPEAT249(macro, arg, n) macro(arg, n) REPEAT248(macro, arg, INC_VALUE(n)) +#define REPEAT250(macro, arg, n) macro(arg, n) REPEAT249(macro, arg, INC_VALUE(n)) +#define REPEAT251(macro, arg, n) macro(arg, n) REPEAT250(macro, arg, INC_VALUE(n)) +#define REPEAT252(macro, arg, n) macro(arg, n) REPEAT251(macro, arg, INC_VALUE(n)) +#define REPEAT253(macro, arg, n) macro(arg, n) REPEAT252(macro, arg, INC_VALUE(n)) +#define REPEAT254(macro, arg, n) macro(arg, n) REPEAT253(macro, arg, INC_VALUE(n)) +#define REPEAT255(macro, arg, n) macro(arg, n) REPEAT254(macro, arg, INC_VALUE(n)) + +#ifdef __cplusplus +} +#endif + +#include +#endif /* _UTILS_REPEAT_MACRO_H */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/utils/src/utils_assert.c b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/utils/src/utils_assert.c new file mode 100644 index 00000000..b376c970 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/utils/src/utils_assert.c @@ -0,0 +1,46 @@ +/** + * \file + * + * \brief Asserts related functionality. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include + +/** + * \brief Assert function + */ +void assert(const bool condition, const char *const file, const int line) +{ + if (!(condition)) { + __asm("BKPT #0"); + } + (void)file; + (void)line; +} diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/utils/src/utils_event.c b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/utils/src/utils_event.c new file mode 100644 index 00000000..d1af9d0c --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/utils/src/utils_event.c @@ -0,0 +1,125 @@ +/** + * \file + * + * \brief Events implementation. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +#define EVENT_WORD_BITS (sizeof(event_word_t) * 8) + +static struct list_descriptor events; +static uint8_t subscribed[EVENT_MASK_SIZE]; + +int32_t event_subscribe(struct event *const event, const event_id_t id, event_cb_t cb) +{ + /* get byte and bit number of the given event in the event mask */ + const uint8_t position = id >> 3; + const uint8_t mask = 1 << (id & 0x7); + + ASSERT(event && cb && (id < EVENT_MAX_AMOUNT)); + + if (event->mask[position] & mask) { + return ERR_NO_CHANGE; /* Already subscribed */ + } + + if (!is_list_element(&events, event)) { + memset(event->mask, 0, EVENT_MASK_SIZE); + list_insert_as_head(&events, event); + } + event->cb = cb; + event->mask[position] |= mask; + + subscribed[position] |= mask; + + return ERR_NONE; +} + +int32_t event_unsubscribe(struct event *const event, const event_id_t id) +{ + /* get byte and bit number of the given event in the event mask */ + const uint8_t position = id >> 3; + const uint8_t mask = 1 << (id & 0x7); + const struct event *current; + uint8_t i; + + ASSERT(event && (id < EVENT_MAX_AMOUNT)); + + if (!(event->mask[position] & mask)) { + return ERR_NO_CHANGE; /* Already unsubscribed */ + } + + event->mask[position] &= ~mask; + + /* Check if there are more subscribers */ + for ((current = (const struct event *)list_get_head(&events)); current; + current = (const struct event *)list_get_next_element(current)) { + if (current->mask[position] & mask) { + break; + } + } + if (!current) { + subscribed[position] &= ~mask; + } + + /* Remove event from the list. Can be unsave, document it! */ + for (i = 0; i < ARRAY_SIZE(event->mask); i++) { + if (event->mask[i]) { + return ERR_NONE; + } + } + list_delete_element(&events, event); + + return ERR_NONE; +} + +void event_post(const event_id_t id, const event_data_t data) +{ + /* get byte and bit number of the given event in the event mask */ + const uint8_t position = id >> 3; + const uint8_t mask = 1 << (id & 0x7); + const struct event *current; + + ASSERT((id < EVENT_MAX_AMOUNT)); + + if (!(subscribed[position] & mask)) { + return; /* No subscribers */ + } + + /* Find all subscribers */ + for ((current = (const struct event *)list_get_head(&events)); current; + current = (const struct event *)list_get_next_element(current)) { + if (current->mask[position] & mask) { + current->cb(id, data); + } + } +} diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/utils/src/utils_list.c b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/utils/src/utils_list.c new file mode 100644 index 00000000..4006a019 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/utils/src/utils_list.c @@ -0,0 +1,136 @@ +/** + * \file + * + * \brief List functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** + * \brief Check whether element belongs to list + */ +bool is_list_element(const struct list_descriptor *const list, const void *const element) +{ + struct list_element *it; + for (it = list->head; it; it = it->next) { + if (it == element) { + return true; + } + } + + return false; +} + +/** + * \brief Insert an element as list head + */ +void list_insert_as_head(struct list_descriptor *const list, void *const element) +{ + ASSERT(!is_list_element(list, element)); + + ((struct list_element *)element)->next = list->head; + list->head = (struct list_element *)element; +} + +/** + * \brief Insert an element after the given list element + */ +void list_insert_after(void *const after, void *const element) +{ + ((struct list_element *)element)->next = ((struct list_element *)after)->next; + ((struct list_element *)after)->next = (struct list_element *)element; +} + +/** + * \brief Insert an element at list end + */ +void list_insert_at_end(struct list_descriptor *const list, void *const element) +{ + struct list_element *it = list->head; + + ASSERT(!is_list_element(list, element)); + + if (!list->head) { + list->head = (struct list_element *)element; + ((struct list_element *)element)->next = NULL; + return; + } + + while (it->next) { + it = it->next; + } + it->next = (struct list_element *)element; + ((struct list_element *)element)->next = NULL; +} + +/** + * \brief Removes list head + */ +void *list_remove_head(struct list_descriptor *const list) +{ + if (list->head) { + struct list_element *tmp = list->head; + + list->head = list->head->next; + return (void *)tmp; + } + + return NULL; +} + +/** + * \brief Removes list element + */ +bool list_delete_element(struct list_descriptor *const list, const void *const element) +{ + if (!element) { + return false; + } + + if (list->head == element) { + list->head = list->head->next; + return true; + } else { + struct list_element *it = list->head; + + while (it && it->next != element) { + it = it->next; + } + if (it) { + it->next = ((struct list_element *)element)->next; + return true; + } + } + + return false; +} + +//@} diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/utils/src/utils_syscalls.c b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/utils/src/utils_syscalls.c new file mode 100644 index 00000000..79e2f1fe --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hal/utils/src/utils_syscalls.c @@ -0,0 +1,152 @@ +/** + * \file + * + * \brief Syscalls for SAM0 (GCC). + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#undef errno +extern int errno; +extern int _end; + +extern caddr_t _sbrk(int incr); +extern int link(char *old, char *_new); +extern int _close(int file); +extern int _fstat(int file, struct stat *st); +extern int _isatty(int file); +extern int _lseek(int file, int ptr, int dir); +extern void _exit(int status); +extern void _kill(int pid, int sig); +extern int _getpid(void); + +/** + * \brief Replacement of C library of _sbrk + */ +extern caddr_t _sbrk(int incr) +{ + static unsigned char *heap = NULL; + unsigned char * prev_heap; + + if (heap == NULL) { + heap = (unsigned char *)&_end; + } + prev_heap = heap; + + heap += incr; + + return (caddr_t)prev_heap; +} + +/** + * \brief Replacement of C library of link + */ +extern int link(char *old, char *_new) +{ + (void)old, (void)_new; + return -1; +} + +/** + * \brief Replacement of C library of _close + */ +extern int _close(int file) +{ + (void)file; + return -1; +} + +/** + * \brief Replacement of C library of _fstat + */ +extern int _fstat(int file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + + return 0; +} + +/** + * \brief Replacement of C library of _isatty + */ +extern int _isatty(int file) +{ + (void)file; + return 1; +} + +/** + * \brief Replacement of C library of _lseek + */ +extern int _lseek(int file, int ptr, int dir) +{ + (void)file, (void)ptr, (void)dir; + return 0; +} + +/** + * \brief Replacement of C library of _exit + */ +extern void _exit(int status) +{ + printf("Exiting with status %d.\n", status); + + for (;;) + ; +} + +/** + * \brief Replacement of C library of _kill + */ +extern void _kill(int pid, int sig) +{ + (void)pid, (void)sig; + return; +} + +/** + * \brief Replacement of C library of _getpid + */ +extern int _getpid(void) +{ + return -1; +} + +#ifdef __cplusplus +} +#endif diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hpl/core/hpl_core_m0plus_base.c b/prototype/firmware/EDBG UART erert/EDBG UART erert/hpl/core/hpl_core_m0plus_base.c new file mode 100644 index 00000000..28d799ec --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hpl/core/hpl_core_m0plus_base.c @@ -0,0 +1,232 @@ +/** + * \file + * + * \brief Core related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include +#include +#ifndef _UNIT_TEST_ +#include +#endif +#include +#include + +#ifndef CONF_CPU_FREQUENCY +#define CONF_CPU_FREQUENCY 1000000 +#endif + +#if CONF_CPU_FREQUENCY < 1000 +#define CPU_FREQ_POWER 3 +#elif CONF_CPU_FREQUENCY < 10000 +#define CPU_FREQ_POWER 4 +#elif CONF_CPU_FREQUENCY < 100000 +#define CPU_FREQ_POWER 5 +#elif CONF_CPU_FREQUENCY < 1000000 +#define CPU_FREQ_POWER 6 +#elif CONF_CPU_FREQUENCY < 10000000 +#define CPU_FREQ_POWER 7 +#elif CONF_CPU_FREQUENCY < 100000000 +#define CPU_FREQ_POWER 8 +#endif + +/** + * \brief The array of interrupt handlers + */ +struct _irq_descriptor *_irq_table[PERIPH_COUNT_IRQn]; + +/** + * \brief Reset MCU + */ +void _reset_mcu(void) +{ + NVIC_SystemReset(); +} + +/** + * \brief Put MCU to sleep + */ +void _go_to_sleep(void) +{ + __DSB(); + __WFI(); +} + +/** + * \brief Retrieve current IRQ number + */ +uint8_t _irq_get_current(void) +{ + return (uint8_t)__get_IPSR() - 16; +} + +/** + * \brief Disable the given IRQ + */ +void _irq_disable(uint8_t n) +{ + NVIC_DisableIRQ((IRQn_Type)n); +} + +/** + * \brief Set the given IRQ + */ +void _irq_set(uint8_t n) +{ + NVIC_SetPendingIRQ((IRQn_Type)n); +} + +/** + * \brief Clear the given IRQ + */ +void _irq_clear(uint8_t n) +{ + NVIC_ClearPendingIRQ((IRQn_Type)n); +} + +/** + * \brief Enable the given IRQ + */ +void _irq_enable(uint8_t n) +{ + NVIC_EnableIRQ((IRQn_Type)n); +} + +/** + * \brief Register IRQ handler + */ +void _irq_register(const uint8_t n, struct _irq_descriptor *const irq) +{ + ASSERT(n < PERIPH_COUNT_IRQn); + + _irq_table[n] = irq; +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Default_Handler(void) +{ + while (1) { + } +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of us + */ +static inline uint32_t _get_cycles_for_us_internal(const uint16_t us, const uint32_t freq, const uint8_t power) +{ + switch (power) { + case 8: + return (us * (freq / 100000) + 29) / 30; + case 7: + return (us * (freq / 10000) + 299) / 300; + case 6: + return (us * (freq / 1000) + 2999) / 3000; + case 5: + return (us * (freq / 100) + 29999) / 30000; + case 4: + return (us * (freq / 10) + 299999) / 300000; + default: + return (us * freq + 2999999) / 3000000; + } +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of us + */ +uint32_t _get_cycles_for_us(const uint16_t us) +{ + return _get_cycles_for_us_internal(us, CONF_CPU_FREQUENCY, CPU_FREQ_POWER); +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of ms + */ +static inline uint32_t _get_cycles_for_ms_internal(const uint16_t ms, const uint32_t freq, const uint8_t power) +{ + switch (power) { + case 8: + return (ms * (freq / 100000) + 2) / 3 * 100; + case 7: + return (ms * (freq / 10000) + 2) / 3 * 10; + case 6: + return (ms * (freq / 1000) + 2) / 3; + case 5: + return (ms * (freq / 100) + 29) / 30; + case 4: + return (ms * (freq / 10) + 299) / 300; + default: + return (ms * (freq / 1) + 2999) / 3000; + } +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of ms + */ +uint32_t _get_cycles_for_ms(const uint16_t ms) +{ + return _get_cycles_for_ms_internal(ms, CONF_CPU_FREQUENCY, CPU_FREQ_POWER); +} +/** + * \brief Initialize delay functionality + */ +void _delay_init(void *const hw) +{ + (void)hw; +} +/** + * \brief Delay loop to delay n number of cycles + */ +void _delay_cycles(void *const hw, uint32_t cycles) +{ +#ifndef _UNIT_TEST_ + (void)hw; + (void)cycles; +#if defined __GNUC__ + __asm(".syntax unified\n" + "__delay:\n" + "subs r1, r1, #1\n" + "bhi __delay\n" + ".syntax divided"); +#elif defined __CC_ARM + __asm("__delay:\n" + "subs cycles, cycles, #1\n" + "bhi __delay\n"); +#elif defined __ICCARM__ + __asm("__delay:\n" + "subs r1, r1, #1\n" + "bhi __delay\n"); +#endif +#endif +} diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hpl/core/hpl_core_port.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hpl/core/hpl_core_port.h new file mode 100644 index 00000000..3f3e8f28 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hpl/core/hpl_core_port.h @@ -0,0 +1,61 @@ +/** + * \file + * + * \brief Core related functionality implementation. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_CORE_PORT_H_INCLUDED +#define _HPL_CORE_PORT_H_INCLUDED + +#include + +/* It's possible to include this file in ARM ASM files (e.g., in FreeRTOS IAR + * portable implement, portasm.s -> FreeRTOSConfig.h -> hpl_core_port.h), + * there will be assembling errors. + * So the following things are not included for assembling. + */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + +#ifndef _UNIT_TEST_ +#include +#endif + +/** + * \brief Check if it's in ISR handling + * \return \c true if it's in ISR + */ +static inline bool _is_in_isr(void) +{ + return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk); +} + +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _HPL_CORE_PORT_H_INCLUDED */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hpl/core/hpl_init.c b/prototype/firmware/EDBG UART erert/EDBG UART erert/hpl/core/hpl_init.c new file mode 100644 index 00000000..b77b840c --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hpl/core/hpl_init.c @@ -0,0 +1,74 @@ +/** + * \file + * + * \brief HPL initialization related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include + +#include +#include + +/* Referenced GCLKs (out of 0~7), should be initialized firstly + */ +#define _GCLK_INIT_1ST 0x00000000 +/* Not referenced GCLKs, initialized last */ +#define _GCLK_INIT_LAST 0x000000FF + +/** + * \brief Initialize the hardware abstraction layer + */ +void _init_chip(void) +{ + hri_nvmctrl_set_CTRLB_RWS_bf(NVMCTRL, CONF_NVM_WAIT_STATE); + + _set_performance_level(2); + + _osc32kctrl_init_sources(); + _oscctrl_init_sources(); + _mclk_init(); +#if _GCLK_INIT_1ST + _gclk_init_generators_by_fref(_GCLK_INIT_1ST); +#endif + _oscctrl_init_referenced_generators(); + _gclk_init_generators_by_fref(_GCLK_INIT_LAST); + +#if CONF_DMAC_ENABLE + hri_mclk_set_AHBMASK_DMAC_bit(MCLK); + _dma_init(); +#endif + +#if (CONF_PORT_EVCTRL_PORT_0 | CONF_PORT_EVCTRL_PORT_1 | CONF_PORT_EVCTRL_PORT_2 | CONF_PORT_EVCTRL_PORT_3) + _port_event_init(); +#endif +} diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hpl/dmac/hpl_dmac.c b/prototype/firmware/EDBG UART erert/EDBG UART erert/hpl/dmac/hpl_dmac.c new file mode 100644 index 00000000..460393c1 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hpl/dmac/hpl_dmac.c @@ -0,0 +1,249 @@ + +/** + * \file + * + * \brief Generic DMAC related functionality. + * + * Copyright (c) 2016-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include +#include +#include +#include + +#if CONF_DMAC_ENABLE + +#ifndef SECTION_DMAC_DESCRIPTOR +#define SECTION_DMAC_DESCRIPTOR +#warning Please double confirm if your DMA descriptor needs specific RAM +#endif + +/* Section containing first descriptors for all DMAC channels */ +COMPILER_ALIGNED(16) +DmacDescriptor _descriptor_section[DMAC_CH_NUM] SECTION_DMAC_DESCRIPTOR; + +/* Section containing current descriptors for all DMAC channels */ +COMPILER_ALIGNED(16) +DmacDescriptor _write_back_section[DMAC_CH_NUM] SECTION_DMAC_DESCRIPTOR; + +/* Array containing callbacks for DMAC channels */ +static struct _dma_resource _resources[DMAC_CH_NUM]; + +/* This macro DMAC configuration */ +#define DMAC_CHANNEL_CFG(i, n) \ + {(CONF_DMAC_RUNSTDBY_##n << DMAC_CHCTRLA_RUNSTDBY_Pos) | (CONF_DMAC_ENABLE_##n << DMAC_CHCTRLA_ENABLE_Pos), \ + DMAC_CHCTRLB_TRIGACT(CONF_DMAC_TRIGACT_##n) | DMAC_CHCTRLB_TRIGSRC(CONF_DMAC_TRIGSRC_##n) \ + | DMAC_CHCTRLB_LVL(CONF_DMAC_LVL_##n) | (CONF_DMAC_EVOE_##n << DMAC_CHCTRLB_EVOE_Pos) \ + | (CONF_DMAC_EVIE_##n << DMAC_CHCTRLB_EVIE_Pos) | DMAC_CHCTRLB_EVACT(CONF_DMAC_EVACT_##n), \ + DMAC_BTCTRL_STEPSIZE(CONF_DMAC_STEPSIZE_##n) | (CONF_DMAC_STEPSEL_##n << DMAC_BTCTRL_STEPSEL_Pos) \ + | (CONF_DMAC_DSTINC_##n << DMAC_BTCTRL_DSTINC_Pos) | (CONF_DMAC_SRCINC_##n << DMAC_BTCTRL_SRCINC_Pos) \ + | DMAC_BTCTRL_BEATSIZE(CONF_DMAC_BEATSIZE_##n) | DMAC_BTCTRL_BLOCKACT(CONF_DMAC_BLOCKACT_##n) \ + | DMAC_BTCTRL_EVOSEL(CONF_DMAC_EVOSEL_##n)}, + +/* DMAC channel configuration */ +struct dmac_channel_cfg { + uint8_t ctrla; + uint32_t ctrlb; + uint16_t btctrl; +}; + +/* DMAC channel configurations */ +const static struct dmac_channel_cfg _cfgs[] = {REPEAT_MACRO(DMAC_CHANNEL_CFG, i, DMAC_CH_NUM)}; + +/** + * \brief Initialize DMAC + */ +int32_t _dma_init(void) +{ + uint8_t i = 0; + + hri_dmac_clear_CTRL_DMAENABLE_bit(DMAC); + hri_dmac_clear_CTRL_CRCENABLE_bit(DMAC); + hri_dmac_set_CHCTRLA_SWRST_bit(DMAC); + + hri_dmac_write_CTRL_reg(DMAC, + (CONF_DMAC_LVLEN0 << DMAC_CTRL_LVLEN0_Pos) | (CONF_DMAC_LVLEN1 << DMAC_CTRL_LVLEN1_Pos) + | (CONF_DMAC_LVLEN2 << DMAC_CTRL_LVLEN2_Pos) + | (CONF_DMAC_LVLEN3 << DMAC_CTRL_LVLEN3_Pos)); + hri_dmac_write_DBGCTRL_DBGRUN_bit(DMAC, CONF_DMAC_DBGRUN); + + hri_dmac_write_QOSCTRL_reg(DMAC, + DMAC_QOSCTRL_WRBQOS(CONF_DMAC_WRBQOS) | DMAC_QOSCTRL_FQOS(CONF_DMAC_FQOS) + | DMAC_QOSCTRL_DQOS(CONF_DMAC_DQOS)); + + hri_dmac_write_PRICTRL0_reg( + DMAC, + DMAC_PRICTRL0_LVLPRI0(CONF_DMAC_LVLPRI0) | DMAC_PRICTRL0_LVLPRI1(CONF_DMAC_LVLPRI1) + | DMAC_PRICTRL0_LVLPRI2(CONF_DMAC_LVLPRI2) | DMAC_PRICTRL0_LVLPRI3(CONF_DMAC_LVLPRI3) + | (CONF_DMAC_RRLVLEN0 << DMAC_PRICTRL0_RRLVLEN0_Pos) | (CONF_DMAC_RRLVLEN1 << DMAC_PRICTRL0_RRLVLEN1_Pos) + | (CONF_DMAC_RRLVLEN2 << DMAC_PRICTRL0_RRLVLEN2_Pos) | (CONF_DMAC_RRLVLEN3 << DMAC_PRICTRL0_RRLVLEN3_Pos)); + hri_dmac_write_BASEADDR_reg(DMAC, (uint32_t)_descriptor_section); + hri_dmac_write_WRBADDR_reg(DMAC, (uint32_t)_write_back_section); + + for (; i < DMAC_CH_NUM; i++) { + hri_dmac_write_CHID_reg(DMAC, i); + + hri_dmac_write_CHCTRLA_RUNSTDBY_bit(DMAC, _cfgs[i].ctrla & DMAC_CHCTRLA_RUNSTDBY); + + hri_dmac_write_CHCTRLB_reg(DMAC, _cfgs[i].ctrlb); + hri_dmacdescriptor_write_BTCTRL_reg(&_descriptor_section[i], _cfgs[i].btctrl); + hri_dmacdescriptor_write_DESCADDR_reg(&_descriptor_section[i], 0x0); + } + + NVIC_DisableIRQ(DMAC_IRQn); + NVIC_ClearPendingIRQ(DMAC_IRQn); + NVIC_EnableIRQ(DMAC_IRQn); + + hri_dmac_set_CTRL_DMAENABLE_bit(DMAC); + + return ERR_NONE; +} + +/** + * \brief Enable/disable DMA interrupt + */ +void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state) +{ + hri_dmac_write_CHID_reg(DMAC, channel); + + if (DMA_TRANSFER_COMPLETE_CB == type) { + hri_dmac_write_CHINTEN_TCMPL_bit(DMAC, state); + } else if (DMA_TRANSFER_ERROR_CB == type) { + hri_dmac_write_CHINTEN_TERR_bit(DMAC, state); + } +} + +int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst) +{ + hri_dmacdescriptor_write_DSTADDR_reg(&_descriptor_section[channel], (uint32_t)dst); + + return ERR_NONE; +} + +int32_t _dma_set_source_address(const uint8_t channel, const void *const src) +{ + hri_dmacdescriptor_write_SRCADDR_reg(&_descriptor_section[channel], (uint32_t)src); + + return ERR_NONE; +} + +int32_t _dma_set_next_descriptor(const uint8_t current_channel, const uint8_t next_channel) +{ + hri_dmacdescriptor_write_DESCADDR_reg(&_descriptor_section[current_channel], + (uint32_t)&_descriptor_section[next_channel]); + + return ERR_NONE; +} + +int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable) +{ + hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(&_descriptor_section[channel], enable); + + return ERR_NONE; +} + +int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount) +{ + uint32_t address = hri_dmacdescriptor_read_DSTADDR_reg(&_descriptor_section[channel]); + uint8_t beat_size = hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(&_descriptor_section[channel]); + + if (hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(&_descriptor_section[channel])) { + hri_dmacdescriptor_write_DSTADDR_reg(&_descriptor_section[channel], address + amount * (1 << beat_size)); + } + + address = hri_dmacdescriptor_read_SRCADDR_reg(&_descriptor_section[channel]); + + if (hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(&_descriptor_section[channel])) { + hri_dmacdescriptor_write_SRCADDR_reg(&_descriptor_section[channel], address + amount * (1 << beat_size)); + } + + hri_dmacdescriptor_write_BTCNT_reg(&_descriptor_section[channel], amount); + + return ERR_NONE; +} + +int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger) +{ + hri_dmac_write_CHID_reg(DMAC, channel); + hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[channel]); + hri_dmac_set_CHCTRLA_ENABLE_bit(DMAC); + if (software_trigger) { + hri_dmac_set_SWTRIGCTRL_reg(DMAC, 1 << channel); + } + + return ERR_NONE; +} + +int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel) +{ + *resource = &_resources[channel]; + + return ERR_NONE; +} + +int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable) +{ + hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(&_descriptor_section[channel], enable); + + return ERR_NONE; +} + +/** + * \internal DMAC interrupt handler + */ +static inline void _dmac_handler(void) +{ + uint8_t channel = hri_dmac_read_INTPEND_ID_bf(DMAC); + uint8_t current_channel = hri_dmac_read_CHID_reg(DMAC); + uint8_t flag_status; + struct _dma_resource *tmp_resource = &_resources[channel]; + + hri_dmac_write_CHID_reg(DMAC, channel); + flag_status = hri_dmac_get_CHINTFLAG_reg(DMAC, DMAC_CHINTFLAG_MASK); + hri_dmac_write_CHID_reg(DMAC, current_channel); + + if (flag_status & DMAC_CHINTFLAG_TERR) { + hri_dmac_clear_CHINTFLAG_TERR_bit(DMAC); + tmp_resource->dma_cb.error(tmp_resource); + } else if (flag_status & DMAC_CHINTFLAG_TCMPL) { + hri_dmac_clear_CHINTFLAG_TCMPL_bit(DMAC); + tmp_resource->dma_cb.transfer_done(tmp_resource); + } +} + +/** + * \brief DMAC interrupt handler + */ +void DMAC_Handler(void) +{ + _dmac_handler(); +} + +#endif /* CONF_DMAC_ENABLE */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hpl/gclk/hpl_gclk.c b/prototype/firmware/EDBG UART erert/EDBG UART erert/hpl/gclk/hpl_gclk.c new file mode 100644 index 00000000..f93ec0c9 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hpl/gclk/hpl_gclk.c @@ -0,0 +1,246 @@ + +/** + * \file + * + * \brief Generic Clock Controller related functionality. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +/** + * \brief Initializes generators + */ +void _gclk_init_generators(void) +{ + +#if CONF_GCLK_GENERATOR_0_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 0, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_0_DIV) | (CONF_GCLK_GEN_0_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_0_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_0_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_0_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_0_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_0_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_0_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_1_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 1, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_1_DIV) | (CONF_GCLK_GEN_1_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_1_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_1_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_1_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_1_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_1_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_1_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_2_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 2, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_2_DIV) | (CONF_GCLK_GEN_2_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_2_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_2_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_2_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_2_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_2_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_2_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_3_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 3, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_3_DIV) | (CONF_GCLK_GEN_3_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_3_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_3_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_3_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_3_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_3_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_3_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_4_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 4, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_4_DIV) | (CONF_GCLK_GEN_4_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_4_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_4_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_4_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_4_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_4_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_5_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 5, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_5_DIV) | (CONF_GCLK_GEN_5_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_5_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_5_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_5_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_5_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_5_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_5_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_6_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 6, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_6_DIV) | (CONF_GCLK_GEN_6_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_6_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_6_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_6_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_6_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_6_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_6_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_7_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 7, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_7_DIV) | (CONF_GCLK_GEN_7_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_7_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_7_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_7_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_7_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_7_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_7_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_8_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 8, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_8_DIV) | (CONF_GCLK_GEN_8_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_8_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_8_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_8_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_8_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_8_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_8_SOURCE); +#endif +} + +void _gclk_init_generators_by_fref(uint32_t bm) +{ + +#if CONF_GCLK_GENERATOR_0_CONFIG == 1 + if (bm & (1ul << 0)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 0, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_0_DIV) | (CONF_GCLK_GEN_0_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_0_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_0_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_0_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_0_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_0_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_0_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_1_CONFIG == 1 + if (bm & (1ul << 1)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 1, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_1_DIV) | (CONF_GCLK_GEN_1_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_1_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_1_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_1_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_1_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_1_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_1_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_2_CONFIG == 1 + if (bm & (1ul << 2)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 2, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_2_DIV) | (CONF_GCLK_GEN_2_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_2_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_2_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_2_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_2_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_2_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_2_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_3_CONFIG == 1 + if (bm & (1ul << 3)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 3, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_3_DIV) | (CONF_GCLK_GEN_3_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_3_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_3_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_3_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_3_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_3_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_3_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_4_CONFIG == 1 + if (bm & (1ul << 4)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 4, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_4_DIV) | (CONF_GCLK_GEN_4_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_4_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_4_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_4_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_4_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_4_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_5_CONFIG == 1 + if (bm & (1ul << 5)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 5, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_5_DIV) | (CONF_GCLK_GEN_5_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_5_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_5_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_5_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_5_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_5_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_5_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_6_CONFIG == 1 + if (bm & (1ul << 6)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 6, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_6_DIV) | (CONF_GCLK_GEN_6_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_6_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_6_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_6_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_6_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_6_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_6_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_7_CONFIG == 1 + if (bm & (1ul << 7)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 7, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_7_DIV) | (CONF_GCLK_GEN_7_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_7_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_7_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_7_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_7_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_7_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_7_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_8_CONFIG == 1 + if (bm & (1ul << 8)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 8, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_8_DIV) | (CONF_GCLK_GEN_8_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_8_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_8_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_8_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_8_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_8_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_8_SOURCE); + } +#endif +} diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hpl/gclk/hpl_gclk_base.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hpl/gclk/hpl_gclk_base.h new file mode 100644 index 00000000..3e7d2825 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hpl/gclk/hpl_gclk_base.h @@ -0,0 +1,87 @@ +/** + * \file + * + * \brief Generic Clock Controller. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_GCLK_H_INCLUDED +#define _HPL_GCLK_H_INCLUDED + +#include +#ifdef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup gclk_group GCLK Hardware Proxy Layer + * + * \section gclk_hpl_rev Revision History + * - v0.0.0.1 Initial Commit + * + *@{ + */ + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Enable clock on the given channel with the given clock source + * + * This function maps the given clock source to the given clock channel + * and enables channel. + * + * \param[in] channel The channel to enable clock for + * \param[in] source The clock source for the given channel + */ +static inline void _gclk_enable_channel(const uint8_t channel, const uint8_t source) +{ + + hri_gclk_write_PCHCTRL_reg(GCLK, channel, source | GCLK_PCHCTRL_CHEN); +} + +/** + * \brief Initialize GCLK generators by function references + * \param[in] bm Bit mapping for referenced generators, + * a bit 1 in position triggers generator initialization. + */ +void _gclk_init_generators_by_fref(uint32_t bm); + +//@} +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_GCLK_H_INCLUDED */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hpl/mclk/hpl_mclk.c b/prototype/firmware/EDBG UART erert/EDBG UART erert/hpl/mclk/hpl_mclk.c new file mode 100644 index 00000000..cd27f094 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hpl/mclk/hpl_mclk.c @@ -0,0 +1,46 @@ +/** + * \file + * + * \brief SAM Main Clock. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** + * \brief Initialize master clock generator + */ +void _mclk_init(void) +{ + void *hw = (void *)MCLK; + hri_mclk_write_BUPDIV_reg(hw, MCLK_BUPDIV_BUPDIV(CONF_MCLK_BUPDIV)); + hri_mclk_write_LPDIV_reg(hw, MCLK_LPDIV_LPDIV(CONF_MCLK_LPDIV)); + hri_mclk_write_CPUDIV_reg(hw, MCLK_CPUDIV_CPUDIV(CONF_MCLK_CPUDIV)); +} diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hpl/osc32kctrl/hpl_osc32kctrl.c b/prototype/firmware/EDBG UART erert/EDBG UART erert/hpl/osc32kctrl/hpl_osc32kctrl.c new file mode 100644 index 00000000..0d543ad0 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hpl/osc32kctrl/hpl_osc32kctrl.c @@ -0,0 +1,102 @@ +/** + * \file + * + * \brief SAM 32k Oscillators Controller. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include + +/** + * \brief Initialize 32 kHz clock sources + */ +void _osc32kctrl_init_sources(void) +{ + void * hw = (void *)OSC32KCTRL; + uint16_t calib = 0; + +#if CONF_XOSC32K_CONFIG == 1 + hri_osc32kctrl_write_XOSC32K_reg( + hw, + OSC32KCTRL_XOSC32K_STARTUP(CONF_XOSC32K_STARTUP) | (CONF_XOSC32K_ONDEMAND << OSC32KCTRL_XOSC32K_ONDEMAND_Pos) + | (CONF_XOSC32K_RUNSTDBY << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos) + | (CONF_XOSC32K_EN1K << OSC32KCTRL_XOSC32K_EN1K_Pos) | (CONF_XOSC32K_EN32K << OSC32KCTRL_XOSC32K_EN32K_Pos) + | (CONF_XOSC32K_XTALEN << OSC32KCTRL_XOSC32K_XTALEN_Pos) + | (CONF_XOSC32K_ENABLE << OSC32KCTRL_XOSC32K_ENABLE_Pos)); + +#endif + +#if CONF_OSC32K_CONFIG == 1 + /* OSC32K calibration value at bit 12:6 of memory 0x00806020 */ + calib = (*((uint32_t *)0x00806020) & 0x0001FC0) >> 6; + hri_osc32kctrl_write_OSC32K_reg( + hw, +#if CONF_OSC32K_CALIB_ENABLE == 1 + OSC32KCTRL_OSC32K_CALIB(CONF_OSC32K_CALIB) | +#else + OSC32KCTRL_OSC32K_CALIB(calib) | +#endif + OSC32KCTRL_OSC32K_STARTUP(CONF_OSC32K_STARTUP) | (CONF_OSC32K_ONDEMAND << OSC32KCTRL_OSC32K_ONDEMAND_Pos) + | (CONF_OSC32K_RUNSTDBY << OSC32KCTRL_OSC32K_RUNSTDBY_Pos) + | (CONF_OSC32K_EN1K << OSC32KCTRL_OSC32K_EN1K_Pos) | (CONF_OSC32K_EN32K << OSC32KCTRL_OSC32K_EN32K_Pos) + | (CONF_OSC32K_ENABLE << OSC32KCTRL_OSC32K_ENABLE_Pos)); +#endif +#if CONF_OSCULP32K_CONFIG == 1 + calib = hri_osc32kctrl_read_OSCULP32K_CALIB_bf(hw); + hri_osc32kctrl_write_OSCULP32K_reg(hw, +#if CONF_OSC32K_CALIB_ENABLE == 1 + OSC32KCTRL_OSCULP32K_CALIB(CONF_OSC32K_CALIB) +#else + OSC32KCTRL_OSCULP32K_CALIB(calib) +#endif + ); +#endif + +#if CONF_XOSC32K_CONFIG +#if CONF_XOSC32K_ENABLE == 1 && CONF_XOSC32K_ONDEMAND == 0 + while (!hri_osc32kctrl_get_STATUS_XOSC32KRDY_bit(hw)) + ; +#endif +#if CONF_OSCULP32K_ULP32KSW == 1 + hri_osc32kctrl_set_OSCULP32K_reg(hw, OSC32KCTRL_OSCULP32K_ULP32KSW); + while (!hri_osc32kctrl_get_STATUS_ULP32KSW_bit(hw)) + ; +#endif +#endif + +#if CONF_OSC32K_CONFIG == 1 +#if CONF_OSC32K_ENABLE == 1 && CONF_OSC32K_ONDEMAND == 0 + while (!hri_osc32kctrl_get_STATUS_OSC32KRDY_bit(hw)) + ; +#endif +#endif + hri_osc32kctrl_write_RTCCTRL_reg(hw, OSC32KCTRL_RTCCTRL_RTCSEL(CONF_RTCCTRL)); + (void)calib; +} diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hpl/oscctrl/hpl_oscctrl.c b/prototype/firmware/EDBG UART erert/EDBG UART erert/hpl/oscctrl/hpl_oscctrl.c new file mode 100644 index 00000000..5b38cb77 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hpl/oscctrl/hpl_oscctrl.c @@ -0,0 +1,177 @@ + +/** + * \file + * + * \brief SAM Oscillators Controller. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include + +/** + * \brief Initialize clock sources + */ +void _oscctrl_init_sources(void) +{ + void *hw = (void *)OSCCTRL; + +#if CONF_XOSC_CONFIG == 1 + hri_oscctrl_write_XOSCCTRL_reg(hw, + OSCCTRL_XOSCCTRL_STARTUP(CONF_XOSC_STARTUP) | (0 << OSCCTRL_XOSCCTRL_AMPGC_Pos) + | OSCCTRL_XOSCCTRL_GAIN(CONF_XOSC_GAIN) | (0 << OSCCTRL_XOSCCTRL_ONDEMAND_Pos) + | (CONF_XOSC_RUNSTDBY << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos) + | (CONF_XOSC_XTALEN << OSCCTRL_XOSCCTRL_XTALEN_Pos) + | (CONF_XOSC_ENABLE << OSCCTRL_XOSCCTRL_ENABLE_Pos)); + +#endif + +#if CONF_OSC16M_CONFIG == 1 + hri_oscctrl_write_OSC16MCTRL_reg(hw, + (CONF_OSC16M_ONDEMAND << OSCCTRL_OSC16MCTRL_ONDEMAND_Pos) + | (CONF_OSC16M_RUNSTDBY << OSCCTRL_OSC16MCTRL_RUNSTDBY_Pos) + | (CONF_OSC16M_ENABLE << OSCCTRL_OSC16MCTRL_ENABLE_Pos) + | OSCCTRL_OSC16MCTRL_FSEL(CONF_OSC16M_FSEL)); +#endif + +#if CONF_XOSC_CONFIG == 1 +#if CONF_XOSC_ENABLE == 1 + while (!hri_oscctrl_get_STATUS_XOSCRDY_bit(hw)) + ; +#endif +#if CONF_XOSC_AMPGC == 1 + hri_oscctrl_set_XOSCCTRL_AMPGC_bit(hw); +#endif +#if CONF_XOSC_ONDEMAND == 1 + hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(hw); +#endif +#endif + +#if CONF_OSC16M_CONFIG == 1 +#if CONF_OSC16M_ENABLE == 1 + while (!hri_oscctrl_get_STATUS_OSC16MRDY_bit(hw)) + ; +#endif +#if CONF_OSC16M_ONDEMAND == 1 + hri_oscctrl_set_OSC16MCTRL_ONDEMAND_bit(hw); +#endif +#endif + (void)hw; +} + +void _oscctrl_init_referenced_generators(void) +{ + void * hw = (void *)OSCCTRL; + hri_oscctrl_dfllctrl_reg_t tmp = 0; + +#if CONF_DFLL_CONFIG == 1 +#if CONF_DFLL_OVERWRITE_CALIBRATION == 0 +#define NVM_DFLL_COARSE_POS 26 +#define NVM_DFLL_COARSE_SIZE 6 + uint32_t coarse; + coarse = *((uint32_t *)(NVMCTRL_OTP5)) >> NVM_DFLL_COARSE_POS; +#endif +#if CONF_DFLL_USBCRM != 1 && CONF_DFLL_MODE != 0 + hri_gclk_write_PCHCTRL_reg(GCLK, 0, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_DFLL_GCLK)); +#endif + hri_oscctrl_write_DFLLCTRL_reg(hw, OSCCTRL_DFLLCTRL_ENABLE); + while (!hri_oscctrl_get_STATUS_DFLLRDY_bit(hw)) + ; + hri_oscctrl_write_DFLLMUL_reg(hw, + OSCCTRL_DFLLMUL_CSTEP(CONF_DFLL_CSTEP) | OSCCTRL_DFLLMUL_FSTEP(CONF_DFLL_FSTEP) + | OSCCTRL_DFLLMUL_MUL(CONF_DFLL_MUL)); + while (!hri_oscctrl_get_STATUS_DFLLRDY_bit(hw)) + ; + +#if CONF_DFLL_OVERWRITE_CALIBRATION == 0 + /* FINE is set to fixed value, which defined by DFLL48M Characteristics */ + hri_oscctrl_write_DFLLVAL_reg(hw, OSCCTRL_DFLLVAL_COARSE(coarse) | OSCCTRL_DFLLVAL_FINE(512)); +#else + hri_oscctrl_write_DFLLVAL_reg(hw, OSCCTRL_DFLLVAL_COARSE(CONF_DFLL_COARSE) | OSCCTRL_DFLLVAL_FINE(CONF_DFLL_FINE)); +#endif + + tmp = (CONF_DFLL_WAITLOCK << OSCCTRL_DFLLCTRL_WAITLOCK_Pos) | (CONF_DFLL_BPLCKC << OSCCTRL_DFLLCTRL_BPLCKC_Pos) + | (CONF_DFLL_QLDIS << OSCCTRL_DFLLCTRL_QLDIS_Pos) | (CONF_DFLL_CCDIS << OSCCTRL_DFLLCTRL_CCDIS_Pos) + | (CONF_DFLL_RUNSTDBY << OSCCTRL_DFLLCTRL_RUNSTDBY_Pos) | (CONF_DFLL_USBCRM << OSCCTRL_DFLLCTRL_USBCRM_Pos) + | (CONF_DFLL_LLAW << OSCCTRL_DFLLCTRL_LLAW_Pos) | (CONF_DFLL_STABLE << OSCCTRL_DFLLCTRL_STABLE_Pos) + | (CONF_DFLL_MODE << OSCCTRL_DFLLCTRL_MODE_Pos) | (CONF_DFLL_ENABLE << OSCCTRL_DFLLCTRL_ENABLE_Pos); + hri_oscctrl_write_DFLLCTRL_reg(hw, tmp); + +#endif + +#if CONF_DPLL_CONFIG == 1 +#if CONF_DPLL_REFCLK == 2 + hri_gclk_write_PCHCTRL_reg(GCLK, 1, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_DPLL_GCLK)); +#endif + hri_oscctrl_write_DPLLRATIO_reg( + hw, OSCCTRL_DPLLRATIO_LDRFRAC(CONF_DPLL_LDRFRAC) | OSCCTRL_DPLLRATIO_LDR(CONF_DPLL_LDR)); + hri_oscctrl_write_DPLLCTRLB_reg( + hw, + OSCCTRL_DPLLCTRLB_DIV(CONF_DPLL_DIV) | (CONF_DPLL_LBYPASS << OSCCTRL_DPLLCTRLB_LBYPASS_Pos) + | OSCCTRL_DPLLCTRLB_LTIME(CONF_DPLL_LTIME) | OSCCTRL_DPLLCTRLB_REFCLK(CONF_DPLL_REFCLK) + | (CONF_DPLL_WUF << OSCCTRL_DPLLCTRLB_WUF_Pos) | (CONF_DPLL_LPEN << OSCCTRL_DPLLCTRLB_LPEN_Pos) + | OSCCTRL_DPLLCTRLB_FILTER(CONF_DPLL_FILTER)); + hri_oscctrl_write_DPLLPRESC_reg(hw, OSCCTRL_DPLLPRESC_PRESC(CONF_DPLL_PRESC)); + hri_oscctrl_write_DPLLCTRLA_reg(hw, + (0 << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos) + | (CONF_DPLL_RUNSTDBY << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos) + | (CONF_DPLL_ENABLE << OSCCTRL_DPLLCTRLA_ENABLE_Pos)); +#endif + +#if CONF_DFLL_CONFIG == 1 + if (hri_oscctrl_get_DFLLCTRL_MODE_bit(hw)) { + hri_oscctrl_status_reg_t status_mask = OSCCTRL_STATUS_DFLLRDY | OSCCTRL_STATUS_DFLLLCKC; + + while (hri_oscctrl_get_STATUS_reg(hw, status_mask) != status_mask) + ; + } else { + while (!hri_oscctrl_get_STATUS_DFLLRDY_bit(hw)) + ; + } +#if CONF_DFLL_ONDEMAND == 1 + hri_oscctrl_set_DFLLCTRL_ONDEMAND_bit(hw); +#endif +#endif + +#if CONF_DPLL_CONFIG == 1 +#if CONF_DPLL_ENABLE == 1 + while (!(hri_oscctrl_get_DPLLSTATUS_LOCK_bit(hw) || hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(hw))) + ; +#endif +#if CONF_DPLL_ONDEMAND == 1 + hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(hw); +#endif +#endif + +#if CONF_DFLL_CONFIG == 1 + while (hri_gclk_read_SYNCBUSY_reg(GCLK)) + ; +#endif + (void)hw, (void)tmp; +} diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hpl/pm/hpl_pm.c b/prototype/firmware/EDBG UART erert/EDBG UART erert/hpl/pm/hpl_pm.c new file mode 100644 index 00000000..d6439f1d --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hpl/pm/hpl_pm.c @@ -0,0 +1,77 @@ + +/** + * \file + * + * \brief SAM Power manager + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +/** + * \brief Retrieve the reset reason + */ +enum reset_reason _get_reset_reason(void) +{ + return (enum reset_reason)hri_rstc_read_RCAUSE_reg(RSTC); +} + +/** + * \brief Set the sleep mode for the device + */ +int32_t _set_sleep_mode(const uint8_t mode) +{ + switch (mode) { + case 2: /* IDLE */ + case 4: /* STANDBY */ + case 5: /* BACKUP */ + case 6: /* OFF */ + hri_pm_write_SLEEPCFG_SLEEPMODE_bf(PM, mode); + break; + default: + return ERR_INVALID_ARG; + } + + return ERR_NONE; +} + +/** + * \brief Set performance level + */ +void _set_performance_level(const uint8_t level) +{ + if (hri_pm_get_PLCFG_PLSEL_bf(PM, PM_PLCFG_PLSEL_Msk) != level) { + hri_pm_clear_INTFLAG_reg(PM, 0xFF); + hri_pm_write_PLCFG_PLSEL_bf(PM, level); + while (!hri_pm_read_INTFLAG_reg(PM)) + ; + } +} diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hpl/pm/hpl_pm_base.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hpl/pm/hpl_pm_base.h new file mode 100644 index 00000000..5a50a914 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hpl/pm/hpl_pm_base.h @@ -0,0 +1,45 @@ +/** + * \file + * + * \brief SAM Power manager + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifndef _HPL_PM_BASE_H_INCLUDED +#define _HPL_PM_BASE_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#ifdef __cplusplus +} +#endif +#endif /* _HPL_PM_BASE_H_INCLUDED */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hpl/port/hpl_gpio_base.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hpl/port/hpl_gpio_base.h new file mode 100644 index 00000000..3cc1981f --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hpl/port/hpl_gpio_base.h @@ -0,0 +1,170 @@ + +/** + * \file + * + * \brief SAM PORT. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include +#include + +/** + * \brief Set direction on port with mask + */ +static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask, + const enum gpio_direction direction) +{ + switch (direction) { + case GPIO_DIRECTION_OFF: + hri_port_clear_DIR_reg(PORT_IOBUS, port, mask); + hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff)); + hri_port_write_WRCONFIG_reg( + PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16)); + break; + + case GPIO_DIRECTION_IN: + hri_port_clear_DIR_reg(PORT_IOBUS, port, mask); + hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN | (mask & 0xffff)); + hri_port_write_WRCONFIG_reg(PORT, + port, + PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN + | ((mask & 0xffff0000) >> 16)); + break; + + case GPIO_DIRECTION_OUT: + hri_port_set_DIR_reg(PORT_IOBUS, port, mask); + hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff)); + hri_port_write_WRCONFIG_reg( + PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16)); + break; + + default: + ASSERT(false); + } +} + +/** + * \brief Set output level on port with mask + */ +static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level) +{ + if (level) { + hri_port_set_OUT_reg(PORT_IOBUS, port, mask); + } else { + hri_port_clear_OUT_reg(PORT_IOBUS, port, mask); + } +} + +/** + * \brief Change output level to the opposite with mask + */ +static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask) +{ + hri_port_toggle_OUT_reg(PORT_IOBUS, port, mask); +} + +/** + * \brief Get input levels on all port pins + */ +static inline uint32_t _gpio_get_level(const enum gpio_port port) +{ + uint32_t tmp; + + CRITICAL_SECTION_ENTER(); + + uint32_t dir_tmp = hri_port_read_DIR_reg(PORT_IOBUS, port); + + tmp = hri_port_read_IN_reg(PORT, port) & ~dir_tmp; + tmp |= hri_port_read_OUT_reg(PORT_IOBUS, port) & dir_tmp; + + CRITICAL_SECTION_LEAVE(); + + return tmp; +} + +/** + * \brief Set pin pull mode + */ +static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin, + const enum gpio_pull_mode pull_mode) +{ + switch (pull_mode) { + case GPIO_PULL_OFF: + hri_port_clear_PINCFG_PULLEN_bit(PORT, port, pin); + break; + + case GPIO_PULL_UP: + hri_port_clear_DIR_reg(PORT_IOBUS, port, 1U << pin); + hri_port_set_PINCFG_PULLEN_bit(PORT, port, pin); + hri_port_set_OUT_reg(PORT_IOBUS, port, 1U << pin); + break; + + case GPIO_PULL_DOWN: + hri_port_clear_DIR_reg(PORT_IOBUS, port, 1U << pin); + hri_port_set_PINCFG_PULLEN_bit(PORT, port, pin); + hri_port_clear_OUT_reg(PORT_IOBUS, port, 1U << pin); + break; + + default: + ASSERT(false); + break; + } +} + +/** + * \brief Set gpio pin function + */ +static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function) +{ + uint8_t port = GPIO_PORT(gpio); + uint8_t pin = GPIO_PIN(gpio); + + if (function == GPIO_PIN_FUNCTION_OFF) { + hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, false); + + } else { + hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, true); + + if (pin & 1) { + // Odd numbered pin + hri_port_write_PMUX_PMUXO_bf(PORT, port, pin >> 1, function & 0xffff); + } else { + // Even numbered pin + hri_port_write_PMUX_PMUXE_bf(PORT, port, pin >> 1, function & 0xffff); + } + } +} + +static inline void _port_event_init() +{ + hri_port_set_EVCTRL_reg(PORT, 0, CONF_PORTA_EVCTRL); + hri_port_set_EVCTRL_reg(PORT, 1, CONF_PORTB_EVCTRL); +} diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hpl/sercom/hpl_sercom.c b/prototype/firmware/EDBG UART erert/EDBG UART erert/hpl/sercom/hpl_sercom.c new file mode 100644 index 00000000..7a448e61 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hpl/sercom/hpl_sercom.c @@ -0,0 +1,2920 @@ + +/** + * \file + * + * \brief SAM Serial Communication Interface + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef CONF_SERCOM_0_USART_ENABLE +#define CONF_SERCOM_0_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_USART_ENABLE +#define CONF_SERCOM_1_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_USART_ENABLE +#define CONF_SERCOM_2_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_USART_ENABLE +#define CONF_SERCOM_3_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_USART_ENABLE +#define CONF_SERCOM_4_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_USART_ENABLE +#define CONF_SERCOM_5_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_USART_ENABLE +#define CONF_SERCOM_6_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_USART_ENABLE +#define CONF_SERCOM_7_USART_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as USART. */ +#define SERCOM_USART_AMOUNT \ + (CONF_SERCOM_0_USART_ENABLE + CONF_SERCOM_1_USART_ENABLE + CONF_SERCOM_2_USART_ENABLE + CONF_SERCOM_3_USART_ENABLE \ + + CONF_SERCOM_4_USART_ENABLE + CONF_SERCOM_5_USART_ENABLE + CONF_SERCOM_6_USART_ENABLE \ + + CONF_SERCOM_7_USART_ENABLE) + +/** + * \brief Macro is used to fill usart configuration structure based on + * its number + * + * \param[in] n The number of structures + */ +#define SERCOM_CONFIGURATION(n) \ + { \ + n, \ + SERCOM_USART_CTRLA_MODE(CONF_SERCOM_##n##_USART_MODE) \ + | (CONF_SERCOM_##n##_USART_RUNSTDBY << SERCOM_USART_CTRLA_RUNSTDBY_Pos) \ + | (CONF_SERCOM_##n##_USART_IBON << SERCOM_USART_CTRLA_IBON_Pos) \ + | SERCOM_USART_CTRLA_SAMPR(CONF_SERCOM_##n##_USART_SAMPR) \ + | SERCOM_USART_CTRLA_TXPO(CONF_SERCOM_##n##_USART_TXPO) \ + | SERCOM_USART_CTRLA_RXPO(CONF_SERCOM_##n##_USART_RXPO) \ + | SERCOM_USART_CTRLA_SAMPA(CONF_SERCOM_##n##_USART_SAMPA) \ + | SERCOM_USART_CTRLA_FORM(CONF_SERCOM_##n##_USART_FORM) \ + | (CONF_SERCOM_##n##_USART_CMODE << SERCOM_USART_CTRLA_CMODE_Pos) \ + | (CONF_SERCOM_##n##_USART_CPOL << SERCOM_USART_CTRLA_CPOL_Pos) \ + | (CONF_SERCOM_##n##_USART_DORD << SERCOM_USART_CTRLA_DORD_Pos), \ + SERCOM_USART_CTRLB_CHSIZE(CONF_SERCOM_##n##_USART_CHSIZE) \ + | (CONF_SERCOM_##n##_USART_SBMODE << SERCOM_USART_CTRLB_SBMODE_Pos) \ + | (CONF_SERCOM_##n##_USART_CLODEN << SERCOM_USART_CTRLB_COLDEN_Pos) \ + | (CONF_SERCOM_##n##_USART_SFDE << SERCOM_USART_CTRLB_SFDE_Pos) \ + | (CONF_SERCOM_##n##_USART_ENC << SERCOM_USART_CTRLB_ENC_Pos) \ + | (CONF_SERCOM_##n##_USART_PMODE << SERCOM_USART_CTRLB_PMODE_Pos) \ + | (CONF_SERCOM_##n##_USART_TXEN << SERCOM_USART_CTRLB_TXEN_Pos) \ + | (CONF_SERCOM_##n##_USART_RXEN << SERCOM_USART_CTRLB_RXEN_Pos), \ + (uint16_t)(CONF_SERCOM_##n##_USART_BAUD_RATE), CONF_SERCOM_##n##_USART_FRACTIONAL, \ + CONF_SERCOM_##n##_USART_RECEIVE_PULSE_LENGTH, CONF_SERCOM_##n##_USART_DEBUG_STOP_MODE, \ + } + +/** + * \brief SERCOM USART configuration type + */ +struct usart_configuration { + uint8_t number; + hri_sercomusart_ctrla_reg_t ctrl_a; + hri_sercomusart_ctrlb_reg_t ctrl_b; + hri_sercomusart_baud_reg_t baud; + uint8_t fractional; + hri_sercomusart_rxpl_reg_t rxpl; + hri_sercomusart_dbgctrl_reg_t debug_ctrl; +}; + +#if SERCOM_USART_AMOUNT < 1 +/** Dummy array to pass compiling. */ +static struct usart_configuration _usarts[1] = {{0}}; +#else +/** + * \brief Array of SERCOM USART configurations + */ +static struct usart_configuration _usarts[] = { +#if CONF_SERCOM_0_USART_ENABLE == 1 + SERCOM_CONFIGURATION(0), +#endif +#if CONF_SERCOM_1_USART_ENABLE == 1 + SERCOM_CONFIGURATION(1), +#endif +#if CONF_SERCOM_2_USART_ENABLE == 1 + SERCOM_CONFIGURATION(2), +#endif +#if CONF_SERCOM_3_USART_ENABLE == 1 + SERCOM_CONFIGURATION(3), +#endif +#if CONF_SERCOM_4_USART_ENABLE == 1 + SERCOM_CONFIGURATION(4), +#endif +#if CONF_SERCOM_5_USART_ENABLE == 1 + SERCOM_CONFIGURATION(5), +#endif +#if CONF_SERCOM_6_USART_ENABLE == 1 + SERCOM_CONFIGURATION(6), +#endif +#if CONF_SERCOM_7_USART_ENABLE == 1 + SERCOM_CONFIGURATION(7), +#endif +}; +#endif + +static uint8_t _get_sercom_index(const void *const hw); +static uint8_t _sercom_get_irq_num(const void *const hw); +static void _sercom_init_irq_param(const void *const hw, void *dev); +static uint8_t _sercom_get_hardware_index(const void *const hw); + +static int32_t _usart_init(void *const hw); +static inline void _usart_deinit(void *const hw); +static uint16_t _usart_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction); +static void _usart_set_baud_rate(void *const hw, const uint32_t baud_rate); +static void _usart_set_data_order(void *const hw, const enum usart_data_order order); +static void _usart_set_mode(void *const hw, const enum usart_mode mode); +static void _usart_set_parity(void *const hw, const enum usart_parity parity); +static void _usart_set_stop_bits(void *const hw, const enum usart_stop_bits stop_bits); +static void _usart_set_character_size(void *const hw, const enum usart_character_size size); + +/** + * \brief Initialize synchronous SERCOM USART + */ +int32_t _usart_sync_init(struct _usart_sync_device *const device, void *const hw) +{ + ASSERT(device); + + device->hw = hw; + + return _usart_init(hw); +} + +/** + * \brief Initialize asynchronous SERCOM USART + */ +int32_t _usart_async_init(struct _usart_async_device *const device, void *const hw) +{ + int32_t init_status; + + ASSERT(device); + + init_status = _usart_init(hw); + if (init_status) { + return init_status; + } + device->hw = hw; + _sercom_init_irq_param(hw, (void *)device); + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + + return ERR_NONE; +} + +/** + * \brief De-initialize SERCOM USART + */ +void _usart_sync_deinit(struct _usart_sync_device *const device) +{ + _usart_deinit(device->hw); +} + +/** + * \brief De-initialize SERCOM USART + */ +void _usart_async_deinit(struct _usart_async_device *const device) +{ + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(device->hw)); + _usart_deinit(device->hw); +} + +/** + * \brief Calculate baud rate register value + */ +uint16_t _usart_sync_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction) +{ + return _usart_calculate_baud_rate(baud, clock_rate, samples, mode, fraction); +} + +/** + * \brief Calculate baud rate register value + */ +uint16_t _usart_async_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction) +{ + return _usart_calculate_baud_rate(baud, clock_rate, samples, mode, fraction); +} + +/** + * \brief Enable SERCOM module + */ +void _usart_sync_enable(struct _usart_sync_device *const device) +{ + hri_sercomusart_set_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Enable SERCOM module + */ +void _usart_async_enable(struct _usart_async_device *const device) +{ + hri_sercomusart_set_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Disable SERCOM module + */ +void _usart_sync_disable(struct _usart_sync_device *const device) +{ + hri_sercomusart_clear_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Disable SERCOM module + */ +void _usart_async_disable(struct _usart_async_device *const device) +{ + hri_sercomusart_clear_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Set baud rate + */ +void _usart_sync_set_baud_rate(struct _usart_sync_device *const device, const uint32_t baud_rate) +{ + _usart_set_baud_rate(device->hw, baud_rate); +} + +/** + * \brief Set baud rate + */ +void _usart_async_set_baud_rate(struct _usart_async_device *const device, const uint32_t baud_rate) +{ + _usart_set_baud_rate(device->hw, baud_rate); +} + +/** + * \brief Set data order + */ +void _usart_sync_set_data_order(struct _usart_sync_device *const device, const enum usart_data_order order) +{ + _usart_set_data_order(device->hw, order); +} + +/** + * \brief Set data order + */ +void _usart_async_set_data_order(struct _usart_async_device *const device, const enum usart_data_order order) +{ + _usart_set_data_order(device->hw, order); +} + +/** + * \brief Set mode + */ +void _usart_sync_set_mode(struct _usart_sync_device *const device, const enum usart_mode mode) +{ + _usart_set_mode(device->hw, mode); +} + +/** + * \brief Set mode + */ +void _usart_async_set_mode(struct _usart_async_device *const device, const enum usart_mode mode) +{ + _usart_set_mode(device->hw, mode); +} + +/** + * \brief Set parity + */ +void _usart_sync_set_parity(struct _usart_sync_device *const device, const enum usart_parity parity) +{ + _usart_set_parity(device->hw, parity); +} + +/** + * \brief Set parity + */ +void _usart_async_set_parity(struct _usart_async_device *const device, const enum usart_parity parity) +{ + _usart_set_parity(device->hw, parity); +} + +/** + * \brief Set stop bits mode + */ +void _usart_sync_set_stop_bits(struct _usart_sync_device *const device, const enum usart_stop_bits stop_bits) +{ + _usart_set_stop_bits(device->hw, stop_bits); +} + +/** + * \brief Set stop bits mode + */ +void _usart_async_set_stop_bits(struct _usart_async_device *const device, const enum usart_stop_bits stop_bits) +{ + _usart_set_stop_bits(device->hw, stop_bits); +} + +/** + * \brief Set character size + */ +void _usart_sync_set_character_size(struct _usart_sync_device *const device, const enum usart_character_size size) +{ + _usart_set_character_size(device->hw, size); +} + +/** + * \brief Set character size + */ +void _usart_async_set_character_size(struct _usart_async_device *const device, const enum usart_character_size size) +{ + _usart_set_character_size(device->hw, size); +} + +/** + * \brief Retrieve SERCOM usart status + */ +uint32_t _usart_sync_get_status(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_read_STATUS_reg(device->hw); +} + +/** + * \brief Retrieve SERCOM usart status + */ +uint32_t _usart_async_get_status(const struct _usart_async_device *const device) +{ + return hri_sercomusart_read_STATUS_reg(device->hw); +} + +/** + * \brief Write a byte to the given SERCOM USART instance + */ +void _usart_sync_write_byte(struct _usart_sync_device *const device, uint8_t data) +{ + hri_sercomusart_write_DATA_reg(device->hw, data); +} + +/** + * \brief Write a byte to the given SERCOM USART instance + */ +void _usart_async_write_byte(struct _usart_async_device *const device, uint8_t data) +{ + hri_sercomusart_write_DATA_reg(device->hw, data); +} + +/** + * \brief Read a byte from the given SERCOM USART instance + */ +uint8_t _usart_sync_read_byte(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_read_DATA_reg(device->hw); +} + +/** + * \brief Check if USART is ready to send next byte + */ +bool _usart_sync_is_ready_to_send(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_get_interrupt_DRE_bit(device->hw); +} + +/** + * \brief Check if USART transmission complete + */ +bool _usart_sync_is_transmit_done(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_get_interrupt_TXC_bit(device->hw); +} + +/** + * \brief Check if USART is ready to send next byte + */ +bool _usart_async_is_byte_sent(const struct _usart_async_device *const device) +{ + return hri_sercomusart_get_interrupt_DRE_bit(device->hw); +} + +/** + * \brief Check if there is data received by USART + */ +bool _usart_sync_is_byte_received(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_get_interrupt_RXC_bit(device->hw); +} + +/** + * \brief Set the state of flow control pins + */ +void _usart_sync_set_flow_control_state(struct _usart_sync_device *const device, + const union usart_flow_control_state state) +{ + (void)device; + (void)state; +} + +/** + * \brief Set the state of flow control pins + */ +void _usart_async_set_flow_control_state(struct _usart_async_device *const device, + const union usart_flow_control_state state) +{ + (void)device; + (void)state; +} + +/** + * \brief Retrieve the state of flow control pins + */ +union usart_flow_control_state _usart_sync_get_flow_control_state(const struct _usart_sync_device *const device) +{ + (void)device; + union usart_flow_control_state state; + + state.value = 0; + state.bit.unavailable = 1; + return state; +} + +/** + * \brief Retrieve the state of flow control pins + */ +union usart_flow_control_state _usart_async_get_flow_control_state(const struct _usart_async_device *const device) +{ + (void)device; + union usart_flow_control_state state; + + state.value = 0; + state.bit.unavailable = 1; + return state; +} + +/** + * \brief Enable data register empty interrupt + */ +void _usart_async_enable_byte_sent_irq(struct _usart_async_device *const device) +{ + hri_sercomusart_set_INTEN_DRE_bit(device->hw); +} + +/** + * \brief Enable transmission complete interrupt + */ +void _usart_async_enable_tx_done_irq(struct _usart_async_device *const device) +{ + hri_sercomusart_set_INTEN_TXC_bit(device->hw); +} + +/** + * \brief Retrieve ordinal number of the given sercom hardware instance + */ +static uint8_t _sercom_get_hardware_index(const void *const hw) +{ +#ifdef _UNIT_TEST_ + return ((uint32_t)hw - (uint32_t)SERCOM0) / sizeof(Sercom); +#endif + if ((uint32_t)SERCOM5 == (uint32_t)hw) { + return 5; + } + + return ((uint32_t)hw - (uint32_t)SERCOM0) >> 10; +} + +/** + * \brief Retrieve ordinal number of the given SERCOM USART hardware instance + */ +uint8_t _usart_sync_get_hardware_index(const struct _usart_sync_device *const device) +{ + return _sercom_get_hardware_index(device->hw); +} + +/** + * \brief Retrieve ordinal number of the given SERCOM USART hardware instance + */ +uint8_t _usart_async_get_hardware_index(const struct _usart_async_device *const device) +{ + return _sercom_get_hardware_index(device->hw); +} + +/** + * \brief Enable/disable USART interrupt + */ +void _usart_async_set_irq_state(struct _usart_async_device *const device, const enum _usart_async_callback_type type, + const bool state) +{ + ASSERT(device); + + if (USART_ASYNC_BYTE_SENT == type || USART_ASYNC_TX_DONE == type) { + hri_sercomusart_write_INTEN_DRE_bit(device->hw, state); + hri_sercomusart_write_INTEN_TXC_bit(device->hw, state); + } else if (USART_ASYNC_RX_DONE == type) { + hri_sercomusart_write_INTEN_RXC_bit(device->hw, state); + } else if (USART_ASYNC_ERROR == type) { + hri_sercomusart_write_INTEN_ERROR_bit(device->hw, state); + } +} + +/** + * \internal Retrieve ordinal number of the given sercom hardware instance + * + * \param[in] hw The pointer to hardware instance + + * \return The ordinal number of the given sercom hardware instance + */ +static uint8_t _get_sercom_index(const void *const hw) +{ + uint8_t sercom_offset = _sercom_get_hardware_index(hw); + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(_usarts); i++) { + if (_usarts[i].number == sercom_offset) { + return i; + } + } + + ASSERT(false); + return 0; +} + +/** + * \brief Init irq param with the given sercom hardware instance + */ +static void _sercom_init_irq_param(const void *const hw, void *dev) +{ +} + +/** + * \internal Initialize SERCOM USART + * + * \param[in] hw The pointer to hardware instance + * + * \return The status of initialization + */ +static int32_t _usart_init(void *const hw) +{ + uint8_t i = _get_sercom_index(hw); + + if (!hri_sercomusart_is_syncing(hw, SERCOM_USART_SYNCBUSY_SWRST)) { + uint32_t mode = _usarts[i].ctrl_a & SERCOM_USART_CTRLA_MODE_Msk; + if (hri_sercomusart_get_CTRLA_reg(hw, SERCOM_USART_CTRLA_ENABLE)) { + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + } + hri_sercomusart_write_CTRLA_reg(hw, SERCOM_USART_CTRLA_SWRST | mode); + } + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); + + hri_sercomusart_write_CTRLA_reg(hw, _usarts[i].ctrl_a); + hri_sercomusart_write_CTRLB_reg(hw, _usarts[i].ctrl_b); + if ((_usarts[i].ctrl_a & SERCOM_USART_CTRLA_SAMPR(0x1)) || (_usarts[i].ctrl_a & SERCOM_USART_CTRLA_SAMPR(0x3))) { + ((Sercom *)hw)->USART.BAUD.FRAC.BAUD = _usarts[i].baud; + ((Sercom *)hw)->USART.BAUD.FRAC.FP = _usarts[i].fractional; + } else { + hri_sercomusart_write_BAUD_reg(hw, _usarts[i].baud); + } + + hri_sercomusart_write_RXPL_reg(hw, _usarts[i].rxpl); + hri_sercomusart_write_DBGCTRL_reg(hw, _usarts[i].debug_ctrl); + + return ERR_NONE; +} + +/** + * \internal De-initialize SERCOM USART + * + * \param[in] hw The pointer to hardware instance + */ +static inline void _usart_deinit(void *const hw) +{ + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + hri_sercomusart_set_CTRLA_SWRST_bit(hw); +} + +/** + * \internal Calculate baud rate register value + * + * \param[in] baud Required baud rate + * \param[in] clock_rate SERCOM clock frequency + * \param[in] samples The number of samples + * \param[in] mode USART mode + * \param[in] fraction A fraction value + * + * \return Calculated baud rate register value + */ +static uint16_t _usart_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction) +{ + if (USART_BAUDRATE_ASYNCH_ARITHMETIC == mode) { + return 65536 - ((uint64_t)65536 * samples * baud) / clock_rate; + } + + if (USART_BAUDRATE_ASYNCH_FRACTIONAL == mode) { + return clock_rate / baud / samples + SERCOM_USART_BAUD_FRACFP_FP(fraction); + } + + if (USART_BAUDRATE_SYNCH == mode) { + return clock_rate / baud / 2 - 1; + } + + return 0; +} + +/** + * \internal Set baud rate + * + * \param[in] device The pointer to USART device instance + * \param[in] baud_rate A baud rate to set + */ +static void _usart_set_baud_rate(void *const hw, const uint32_t baud_rate) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_BAUD_reg(hw, baud_rate); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set data order + * + * \param[in] device The pointer to USART device instance + * \param[in] order A data order to set + */ +static void _usart_set_data_order(void *const hw, const enum usart_data_order order) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLA_DORD_bit(hw, order); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set mode + * + * \param[in] device The pointer to USART device instance + * \param[in] mode A mode to set + */ +static void _usart_set_mode(void *const hw, const enum usart_mode mode) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLA_CMODE_bit(hw, mode); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set parity + * + * \param[in] device The pointer to USART device instance + * \param[in] parity A parity to set + */ +static void _usart_set_parity(void *const hw, const enum usart_parity parity) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + + if (USART_PARITY_NONE != parity) { + hri_sercomusart_set_CTRLA_FORM_bf(hw, 1); + } else { + hri_sercomusart_clear_CTRLA_FORM_bf(hw, 1); + } + + hri_sercomusart_write_CTRLB_PMODE_bit(hw, parity); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set stop bits mode + * + * \param[in] device The pointer to USART device instance + * \param[in] stop_bits A stop bits mode to set + */ +static void _usart_set_stop_bits(void *const hw, const enum usart_stop_bits stop_bits) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLB_SBMODE_bit(hw, stop_bits); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set character size + * + * \param[in] device The pointer to USART device instance + * \param[in] size A character size to set + */ +static void _usart_set_character_size(void *const hw, const enum usart_character_size size) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLB_CHSIZE_bf(hw, size); + CRITICAL_SECTION_LEAVE() + + if (enabled) { + hri_sercomusart_set_CTRLA_ENABLE_bit(hw); + } +} + + /* Sercom I2C implementation */ + +#ifndef CONF_SERCOM_0_I2CM_ENABLE +#define CONF_SERCOM_0_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_I2CM_ENABLE +#define CONF_SERCOM_1_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_I2CM_ENABLE +#define CONF_SERCOM_2_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_I2CM_ENABLE +#define CONF_SERCOM_3_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_I2CM_ENABLE +#define CONF_SERCOM_4_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_I2CM_ENABLE +#define CONF_SERCOM_5_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_I2CM_ENABLE +#define CONF_SERCOM_6_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_I2CM_ENABLE +#define CONF_SERCOM_7_I2CM_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as I2C Master. */ +#define SERCOM_I2CM_AMOUNT \ + (CONF_SERCOM_0_I2CM_ENABLE + CONF_SERCOM_1_I2CM_ENABLE + CONF_SERCOM_2_I2CM_ENABLE + CONF_SERCOM_3_I2CM_ENABLE \ + + CONF_SERCOM_4_I2CM_ENABLE + CONF_SERCOM_5_I2CM_ENABLE + CONF_SERCOM_6_I2CM_ENABLE + CONF_SERCOM_7_I2CM_ENABLE) + +/** + * \brief Macro is used to fill i2cm configuration structure based on + * its number + * + * \param[in] n The number of structures + */ +#define I2CM_CONFIGURATION(n) \ + { \ + (n), \ + (SERCOM_I2CM_CTRLA_MODE_I2C_MASTER) | (CONF_SERCOM_##n##_I2CM_RUNSTDBY << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos) \ + | (CONF_SERCOM_##n##_I2CM_SPEED << SERCOM_I2CM_CTRLA_SPEED_Pos) \ + | (CONF_SERCOM_##n##_I2CM_MEXTTOEN << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos) \ + | (CONF_SERCOM_##n##_I2CM_SEXTTOEN << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos) \ + | (CONF_SERCOM_##n##_I2CM_INACTOUT << SERCOM_I2CM_CTRLA_INACTOUT_Pos) \ + | (CONF_SERCOM_##n##_I2CM_LOWTOUT << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos) \ + | (CONF_SERCOM_##n##_I2CM_SDAHOLD << SERCOM_I2CM_CTRLA_SDAHOLD_Pos), \ + SERCOM_I2CM_CTRLB_SMEN, (uint32_t)(CONF_SERCOM_##n##_I2CM_BAUD_RATE), \ + CONF_SERCOM_##n##_I2CM_DEBUG_STOP_MODE, CONF_SERCOM_##n##_I2CM_TRISE, CONF_GCLK_SERCOM##n##_CORE_FREQUENCY \ + } + +#define ERROR_FLAG (1 << 7) +#define SB_FLAG (1 << 1) +#define MB_FLAG (1 << 0) + +#define CMD_STOP 0x3 +#define I2C_IDLE 0x1 +#define I2C_SM 0x0 +#define I2C_FM 0x1 +#define I2C_HS 0x2 +#define TEN_ADDR_FRAME 0x78 +#define TEN_ADDR_MASK 0x3ff +#define SEVEN_ADDR_MASK 0x7f + +/** + * \brief SERCOM I2CM configuration type + */ +struct i2cm_configuration { + uint8_t number; + hri_sercomi2cm_ctrla_reg_t ctrl_a; + hri_sercomi2cm_ctrlb_reg_t ctrl_b; + hri_sercomi2cm_baud_reg_t baud; + hri_sercomi2cm_dbgctrl_reg_t dbgctrl; + uint16_t trise; + uint32_t clk; /* SERCOM peripheral clock frequency */ +}; + +static inline void _i2c_m_enable_implementation(void *hw); +static int32_t _i2c_m_sync_init_impl(struct _i2c_m_service *const service, void *const hw); + +#if SERCOM_I2CM_AMOUNT < 1 +/** Dummy array to pass compiling. */ +static struct i2cm_configuration _i2cms[1] = {{0}}; +#else +/** + * \brief Array of SERCOM I2CM configurations + */ +static struct i2cm_configuration _i2cms[] = { +#if CONF_SERCOM_0_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(0), +#endif +#if CONF_SERCOM_1_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(1), +#endif +#if CONF_SERCOM_2_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(2), +#endif +#if CONF_SERCOM_3_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(3), +#endif +#if CONF_SERCOM_4_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(4), +#endif +#if CONF_SERCOM_5_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(5), +#endif +#if CONF_SERCOM_6_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(6), +#endif +#if CONF_SERCOM_7_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(7), +#endif +}; +#endif + +/** + * \internal Retrieve ordinal number of the given sercom hardware instance + * + * \param[in] hw The pointer to hardware instance + + * \return The ordinal number of the given sercom hardware instance + */ +static int8_t _get_i2cm_index(const void *const hw) +{ + uint8_t sercom_offset = _sercom_get_hardware_index(hw); + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(_i2cms); i++) { + if (_i2cms[i].number == sercom_offset) { + return i; + } + } + + ASSERT(false); + return -1; +} + +static inline void _sercom_i2c_send_stop(void *const hw) +{ + hri_sercomi2cm_set_CTRLB_CMD_bf(hw, CMD_STOP); +} + +/** + * \brief SERCOM I2CM analyze hardware status and transfer next byte + */ +static inline int32_t _sercom_i2c_sync_analyse_flags(void *const hw, uint32_t flags, struct _i2c_m_msg *const msg) +{ + int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); + uint16_t status = hri_sercomi2cm_read_STATUS_reg(hw); + + if (flags & MB_FLAG) { + /* tx error */ + if (status & SERCOM_I2CM_STATUS_ARBLOST) { + hri_sercomi2cm_clear_interrupt_MB_bit(hw); + msg->flags |= I2C_M_FAIL; + msg->flags &= ~I2C_M_BUSY; + + if (status & SERCOM_I2CM_STATUS_BUSERR) { + return I2C_ERR_BUS; + } + + return I2C_ERR_BAD_ADDRESS; + } else { + if (status & SERCOM_I2CM_STATUS_RXNACK) { + + /* Slave rejects to receive more data */ + if (msg->len > 0) { + msg->flags |= I2C_M_FAIL; + } + + if (msg->flags & I2C_M_STOP) { + _sercom_i2c_send_stop(hw); + } + + msg->flags &= ~I2C_M_BUSY; + + return I2C_NACK; + } + + if (msg->flags & I2C_M_TEN) { + hri_sercomi2cm_write_ADDR_reg(hw, + ((((msg->addr & TEN_ADDR_MASK) >> 8) | TEN_ADDR_FRAME) << 1) | I2C_M_RD + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + msg->flags &= ~I2C_M_TEN; + + return I2C_OK; + } + + if (msg->len == 0) { + if (msg->flags & I2C_M_STOP) { + _sercom_i2c_send_stop(hw); + } + + msg->flags &= ~I2C_M_BUSY; + } else { + hri_sercomi2cm_write_DATA_reg(hw, *msg->buffer); + msg->buffer++; + msg->len--; + } + + return I2C_OK; + } + } else if (flags & SB_FLAG) { + if ((msg->len) && !(status & SERCOM_I2CM_STATUS_RXNACK)) { + msg->len--; + + /* last byte, send nack */ + if ((msg->len == 0 && !sclsm) || (msg->len == 1 && sclsm)) { + hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); + } + + if (msg->len == 0) { + if (msg->flags & I2C_M_STOP) { + hri_sercomi2cm_clear_CTRLB_SMEN_bit(hw); + _sercom_i2c_send_stop(hw); + } + + msg->flags &= ~I2C_M_BUSY; + } + + /* Accessing DATA.DATA auto-triggers I2C bus operations. + * The operation performed depends on the state of + * CTRLB.ACKACT, CTRLB.SMEN + **/ + *msg->buffer++ = hri_sercomi2cm_read_DATA_reg(hw); + } else { + hri_sercomi2cm_clear_interrupt_SB_bit(hw); + return I2C_NACK; + } + + hri_sercomi2cm_clear_interrupt_SB_bit(hw); + } + + return I2C_OK; +} + +/** + * \brief Enable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + _i2c_m_enable_implementation(i2c_dev->hw); + + return ERR_NONE; +} + +/** + * \brief Disable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** + * \brief Set baudrate of master + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] clkrate The clock rate of i2c master, in KHz + * \param[in] baudrate The baud rate desired for i2c master, in KHz + */ +int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate) +{ + uint32_t tmp; + void * hw = i2c_dev->hw; + + if (hri_sercomi2cm_get_CTRLA_ENABLE_bit(hw)) { + return ERR_DENIED; + } + + tmp = _get_i2cm_index(hw); + clkrate = _i2cms[tmp].clk / 1000; + + if (i2c_dev->service.mode == I2C_STANDARD_MODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_FASTMODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_HIGHSPEED_MODE) { + tmp = (clkrate - 2 * baudrate) / (2 * baudrate); + hri_sercomi2cm_write_BAUD_HSBAUD_bf(hw, tmp); + } else { + /* error baudrate */ + return ERR_INVALID_ARG; + } + + return ERR_NONE; +} + +/** + * \brief Retrieve IRQ number for the given hardware instance + */ +static uint8_t _sercom_get_irq_num(const void *const hw) +{ + return SERCOM0_IRQn + _sercom_get_hardware_index(hw); +} + +/** + * \brief Initialize sercom i2c module to use in async mode + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw) +{ + int32_t init_status; + + ASSERT(i2c_dev); + + i2c_dev->hw = hw; + + init_status = _i2c_m_sync_init_impl(&i2c_dev->service, hw); + if (init_status) { + return init_status; + } + + _sercom_init_irq_param(hw, (void *)i2c_dev); + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + + return ERR_NONE; +} + +/** + * \brief Deinitialize sercom i2c module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(i2c_dev->hw); + hri_sercomi2cm_set_CTRLA_SWRST_bit(i2c_dev->hw); + + return ERR_NONE; +} + +/** + * \brief Transfer the slave address to bus, which will start the transfer + * + * \param[in] i2c_dev The pointer to i2c device + */ +static int32_t _sercom_i2c_send_address(struct _i2c_m_async_device *const i2c_dev) +{ + void * hw = i2c_dev->hw; + struct _i2c_m_msg *msg = &i2c_dev->service.msg; + int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); + + ASSERT(i2c_dev); + + if (msg->len == 1 && sclsm) { + hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); + } else { + hri_sercomi2cm_clear_CTRLB_ACKACT_bit(hw); + } + + /* ten bit address */ + if (msg->addr & I2C_M_TEN) { + if (msg->flags & I2C_M_RD) { + msg->flags |= I2C_M_TEN; + } + + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & TEN_ADDR_MASK) << 1) | SERCOM_I2CM_ADDR_TENBITEN + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } else { + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & SEVEN_ADDR_MASK) << 1) | (msg->flags & I2C_M_RD ? I2C_M_RD : 0x0) + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } + + return ERR_NONE; +} + +/** + * \brief Transfer data specified by msg + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] msg The pointer to i2c message + * + * \return Transfer status. + * \retval 0 Transfer success + * \retval <0 Transfer fail, return the error code + */ +int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *i2c_dev, struct _i2c_m_msg *msg) +{ + int ret; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + ASSERT(msg); + + if (msg->len == 0) { + return ERR_NONE; + } + + if (i2c_dev->service.msg.flags & I2C_M_BUSY) { + return ERR_BUSY; + } + + msg->flags |= I2C_M_BUSY; + i2c_dev->service.msg = *msg; + hri_sercomi2cm_set_CTRLB_SMEN_bit(i2c_dev->hw); + + ret = _sercom_i2c_send_address(i2c_dev); + + if (ret) { + i2c_dev->service.msg.flags &= ~I2C_M_BUSY; + + return ret; + } + + return ERR_NONE; +} + +/** + * \brief Set callback to be called in interrupt handler + * + * \param[in] i2c_dev The pointer to master i2c device + * \param[in] type The callback type + * \param[in] func The callback function pointer + */ +int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *const i2c_dev, enum _i2c_m_async_callback_type type, + FUNC_PTR func) +{ + switch (type) { + case I2C_M_ASYNC_DEVICE_ERROR: + i2c_dev->cb.error = (_i2c_error_cb_t)func; + break; + case I2C_M_ASYNC_DEVICE_TX_COMPLETE: + i2c_dev->cb.tx_complete = (_i2c_complete_cb_t)func; + break; + case I2C_M_ASYNC_DEVICE_RX_COMPLETE: + i2c_dev->cb.rx_complete = (_i2c_complete_cb_t)func; + break; + default: + /* error */ + break; + } + + return ERR_NONE; +} + +/** + * \brief Set stop condition on I2C + * + * \param i2c_dev Pointer to master i2c device + * + * \return Operation status + * \retval I2C_OK Operation was successfull + */ +int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + _sercom_i2c_send_stop(hw); + + return I2C_OK; +} + +/** + * \brief Get number of bytes left in transfer buffer + * + * \param i2c_dev Pointer to i2c master device + * + * \return Bytes left in buffer + * \retval =>0 Bytes left in buffer + */ +int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev) +{ + if (i2c_dev->service.msg.flags & I2C_M_BUSY) { + return i2c_dev->service.msg.len; + } + + return 0; +} + +/** + * \brief Initialize sercom i2c module to use in sync mode + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw) +{ + ASSERT(i2c_dev); + + i2c_dev->hw = hw; + + return _i2c_m_sync_init_impl(&i2c_dev->service, hw); +} + +/** + * \brief Deinitialize sercom i2c module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(i2c_dev->hw); + hri_sercomi2cm_set_CTRLA_SWRST_bit(i2c_dev->hw); + + return ERR_NONE; +} + +/** + * \brief Enable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + _i2c_m_enable_implementation(i2c_dev->hw); + + return ERR_NONE; +} + +/** + * \brief Disable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** + * \brief Set baudrate of master + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] clkrate The clock rate of i2c master, in KHz + * \param[in] baudrate The baud rate desired for i2c master, in KHz + */ +int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate) +{ + uint32_t tmp; + void * hw = i2c_dev->hw; + + if (hri_sercomi2cm_get_CTRLA_ENABLE_bit(hw)) { + return ERR_DENIED; + } + + tmp = _get_i2cm_index(hw); + clkrate = _i2cms[tmp].clk / 1000; + + if (i2c_dev->service.mode == I2C_STANDARD_MODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_FASTMODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_HIGHSPEED_MODE) { + tmp = (clkrate - 2 * baudrate) / (2 * baudrate); + hri_sercomi2cm_write_BAUD_HSBAUD_bf(hw, tmp); + } else { + /* error baudrate */ + return ERR_INVALID_ARG; + } + + return ERR_NONE; +} + +/** + * \brief Enable/disable I2C master interrupt + */ +void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type, + const bool state) +{ + if (I2C_M_ASYNC_DEVICE_TX_COMPLETE == type || I2C_M_ASYNC_DEVICE_RX_COMPLETE == type) { + hri_sercomi2cm_write_INTEN_SB_bit(device->hw, state); + hri_sercomi2cm_write_INTEN_MB_bit(device->hw, state); + } else if (I2C_M_ASYNC_DEVICE_ERROR == type) { + hri_sercomi2cm_write_INTEN_ERROR_bit(device->hw, state); + } +} + +/** + * \brief Wait for bus response + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] flags Store the hardware response + * + * \return Bus response status. + * \retval 0 Bus response status OK + * \retval <0 Bus response fail + */ +inline static int32_t _sercom_i2c_sync_wait_bus(struct _i2c_m_sync_device *const i2c_dev, uint32_t *flags) +{ + uint32_t timeout = 65535; + void * hw = i2c_dev->hw; + + do { + *flags = hri_sercomi2cm_read_INTFLAG_reg(hw); + + if (timeout-- == 0) { + return I2C_ERR_BUS; + } + } while (!(*flags & MB_FLAG) && !(*flags & SB_FLAG)); + + return I2C_OK; +} + +/** + * \brief Send the slave address to bus, which will start the transfer + * + * \param[in] i2c_dev The pointer to i2c device + */ +static int32_t _sercom_i2c_sync_send_address(struct _i2c_m_sync_device *const i2c_dev) +{ + void * hw = i2c_dev->hw; + struct _i2c_m_msg *msg = &i2c_dev->service.msg; + int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); + uint32_t flags; + + ASSERT(i2c_dev); + + if (msg->len == 1 && sclsm) { + hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); + } else { + hri_sercomi2cm_clear_CTRLB_ACKACT_bit(hw); + } + + /* ten bit address */ + if (msg->addr & I2C_M_TEN) { + if (msg->flags & I2C_M_RD) { + msg->flags |= I2C_M_TEN; + } + + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & TEN_ADDR_MASK) << 1) | SERCOM_I2CM_ADDR_TENBITEN + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } else { + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & SEVEN_ADDR_MASK) << 1) | (msg->flags & I2C_M_RD ? I2C_M_RD : 0x0) + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } + + _sercom_i2c_sync_wait_bus(i2c_dev, &flags); + return _sercom_i2c_sync_analyse_flags(hw, flags, msg); +} + +/** + * \brief Transfer data specified by msg + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] msg The pointer to i2c message + * + * \return Transfer status. + * \retval 0 Transfer success + * \retval <0 Transfer fail or partial fail, return the error code + */ +int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg) +{ + uint32_t flags; + int ret; + void * hw = i2c_dev->hw; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + ASSERT(msg); + + if (i2c_dev->service.msg.flags & I2C_M_BUSY) { + return I2C_ERR_BUSY; + } + + msg->flags |= I2C_M_BUSY; + i2c_dev->service.msg = *msg; + hri_sercomi2cm_set_CTRLB_SMEN_bit(hw); + + ret = _sercom_i2c_sync_send_address(i2c_dev); + + if (ret) { + i2c_dev->service.msg.flags &= ~I2C_M_BUSY; + + return ret; + } + + while (i2c_dev->service.msg.flags & I2C_M_BUSY) { + ret = _sercom_i2c_sync_wait_bus(i2c_dev, &flags); + + if (ret) { + if (msg->flags & I2C_M_STOP) { + _sercom_i2c_send_stop(hw); + } + + i2c_dev->service.msg.flags &= ~I2C_M_BUSY; + + return ret; + } + + ret = _sercom_i2c_sync_analyse_flags(hw, flags, &i2c_dev->service.msg); + } + + return ret; +} + +int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + _sercom_i2c_send_stop(hw); + + return I2C_OK; +} + +static inline void _i2c_m_enable_implementation(void *const hw) +{ + int timeout = 65535; + + ASSERT(hw); + + /* Enable interrupts */ + hri_sercomi2cm_set_CTRLA_ENABLE_bit(hw); + + while (hri_sercomi2cm_read_STATUS_BUSSTATE_bf(hw) != I2C_IDLE) { + timeout--; + + if (timeout <= 0) { + hri_sercomi2cm_clear_STATUS_reg(hw, SERCOM_I2CM_STATUS_BUSSTATE(I2C_IDLE)); + } + } +} + +static int32_t _i2c_m_sync_init_impl(struct _i2c_m_service *const service, void *const hw) +{ + uint8_t i = _get_i2cm_index(hw); + + if (!hri_sercomi2cm_is_syncing(hw, SERCOM_I2CM_SYNCBUSY_SWRST)) { + uint32_t mode = _i2cms[i].ctrl_a & SERCOM_I2CM_CTRLA_MODE_Msk; + if (hri_sercomi2cm_get_CTRLA_reg(hw, SERCOM_I2CM_CTRLA_ENABLE)) { + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_ENABLE); + } + hri_sercomi2cm_write_CTRLA_reg(hw, SERCOM_I2CM_CTRLA_SWRST | mode); + } + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); + + hri_sercomi2cm_write_CTRLA_reg(hw, _i2cms[i].ctrl_a); + hri_sercomi2cm_write_CTRLB_reg(hw, _i2cms[i].ctrl_b); + hri_sercomi2cm_write_BAUD_reg(hw, _i2cms[i].baud); + + service->mode = (_i2cms[i].ctrl_a & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos; + hri_sercomi2cm_write_ADDR_HS_bit(hw, service->mode < I2C_HS ? 0 : 1); + + service->trise = _i2cms[i].trise; + + return ERR_NONE; +} + + /* SERCOM I2C slave */ + +#ifndef CONF_SERCOM_0_I2CS_ENABLE +#define CONF_SERCOM_0_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_I2CS_ENABLE +#define CONF_SERCOM_1_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_I2CS_ENABLE +#define CONF_SERCOM_2_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_I2CS_ENABLE +#define CONF_SERCOM_3_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_I2CS_ENABLE +#define CONF_SERCOM_4_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_I2CS_ENABLE +#define CONF_SERCOM_5_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_I2CS_ENABLE +#define CONF_SERCOM_6_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_I2CS_ENABLE +#define CONF_SERCOM_7_I2CS_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as I2C Slave. */ +#define SERCOM_I2CS_AMOUNT \ + (CONF_SERCOM_0_I2CS_ENABLE + CONF_SERCOM_1_I2CS_ENABLE + CONF_SERCOM_2_I2CS_ENABLE + CONF_SERCOM_3_I2CS_ENABLE \ + + CONF_SERCOM_4_I2CS_ENABLE + CONF_SERCOM_5_I2CS_ENABLE + CONF_SERCOM_6_I2CS_ENABLE + CONF_SERCOM_7_I2CS_ENABLE) + +/** + * \brief Macro is used to fill I2C slave configuration structure based on + * its number + * + * \param[in] n The number of structures + */ +#define I2CS_CONFIGURATION(n) \ + { \ + n, \ + SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE | (CONF_SERCOM_##n##_I2CS_RUNSTDBY << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos) \ + | SERCOM_I2CS_CTRLA_SDAHOLD(CONF_SERCOM_##n##_I2CS_SDAHOLD) \ + | (CONF_SERCOM_##n##_I2CS_SEXTTOEN << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos) \ + | (CONF_SERCOM_##n##_I2CS_SPEED << SERCOM_I2CS_CTRLA_SPEED_Pos) \ + | (CONF_SERCOM_##n##_I2CS_SCLSM << SERCOM_I2CS_CTRLA_SCLSM_Pos) \ + | (CONF_SERCOM_##n##_I2CS_LOWTOUT << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos), \ + SERCOM_I2CS_CTRLB_SMEN | SERCOM_I2CS_CTRLB_AACKEN | SERCOM_I2CS_CTRLB_AMODE(CONF_SERCOM_##n##_I2CS_AMODE), \ + (CONF_SERCOM_##n##_I2CS_GENCEN << SERCOM_I2CS_ADDR_GENCEN_Pos) \ + | SERCOM_I2CS_ADDR_ADDR(CONF_SERCOM_##n##_I2CS_ADDRESS) \ + | (CONF_SERCOM_##n##_I2CS_TENBITEN << SERCOM_I2CS_ADDR_TENBITEN_Pos) \ + | SERCOM_I2CS_ADDR_ADDRMASK(CONF_SERCOM_##n##_I2CS_ADDRESS_MASK) \ + } + +/** + * \brief Macro to check 10-bit addressing + */ +#define I2CS_7BIT_ADDRESSING_MASK 0x7F + +static int32_t _i2c_s_init(void *const hw); +static int8_t _get_i2c_s_index(const void *const hw); +static inline void _i2c_s_deinit(void *const hw); +static int32_t _i2c_s_set_address(void *const hw, const uint16_t address); + +/** + * \brief SERCOM I2C slave configuration type + */ +struct i2cs_configuration { + uint8_t number; + hri_sercomi2cs_ctrla_reg_t ctrl_a; + hri_sercomi2cs_ctrlb_reg_t ctrl_b; + hri_sercomi2cs_addr_reg_t address; +}; + +#if SERCOM_I2CS_AMOUNT < 1 +/** Dummy array for compiling. */ +static struct i2cs_configuration _i2css[1] = {{0}}; +#else +/** + * \brief Array of SERCOM I2C slave configurations + */ +static struct i2cs_configuration _i2css[] = { +#if CONF_SERCOM_0_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(0), +#endif +#if CONF_SERCOM_1_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(1), +#endif +#if CONF_SERCOM_2_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(2), +#endif +#if CONF_SERCOM_3_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(3), +#endif +#if CONF_SERCOM_4_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(4), +#endif +#if CONF_SERCOM_5_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(5), +#endif +}; +#endif + +/** + * \brief Initialize synchronous I2C slave + */ +int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw) +{ + int32_t status; + + ASSERT(device); + + status = _i2c_s_init(hw); + if (status) { + return status; + } + device->hw = hw; + + return ERR_NONE; +} + +/** + * \brief Initialize asynchronous I2C slave + */ +int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw) +{ + int32_t init_status; + + ASSERT(device); + + init_status = _i2c_s_init(hw); + if (init_status) { + return init_status; + } + + device->hw = hw; + _sercom_init_irq_param(hw, (void *)device); + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + + return ERR_NONE; +} + +/** + * \brief Deinitialize synchronous I2C + */ +int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device) +{ + _i2c_s_deinit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Deinitialize asynchronous I2C + */ +int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device) +{ + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(device->hw)); + _i2c_s_deinit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Enable I2C module + */ +int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device) +{ + hri_sercomi2cs_set_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Enable I2C module + */ +int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device) +{ + hri_sercomi2cs_set_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Disable I2C module + */ +int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device) +{ + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Disable I2C module + */ +int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device) +{ + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Check if 10-bit addressing mode is on + */ +int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_get_ADDR_TENBITEN_bit(device->hw); +} + +/** + * \brief Check if 10-bit addressing mode is on + */ +int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device) +{ + return hri_sercomi2cs_get_ADDR_TENBITEN_bit(device->hw); +} + +/** + * \brief Set I2C slave address + */ +int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address) +{ + return _i2c_s_set_address(device->hw, address); +} + +/** + * \brief Set I2C slave address + */ +int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address) +{ + return _i2c_s_set_address(device->hw, address); +} + +/** + * \brief Write a byte to the given I2C instance + */ +void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data) +{ + hri_sercomi2cs_write_DATA_reg(device->hw, data); +} + +/** + * \brief Write a byte to the given I2C instance + */ +void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data) +{ + hri_sercomi2cs_write_DATA_reg(device->hw, data); +} + +/** + * \brief Read a byte from the given I2C instance + */ +uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_read_DATA_reg(device->hw); +} + +/** + * \brief Check if I2C is ready to send next byt + */ +bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_get_interrupt_DRDY_bit(device->hw); +} + +/** + * \brief Check if there is data received by I2C + */ +bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_get_interrupt_DRDY_bit(device->hw); +} + +/** + * \brief Retrieve I2C slave status + */ +i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_read_STATUS_reg(device->hw); +} + +/** + * \brief Clear the Data Ready interrupt flag + */ +int32_t _i2c_s_sync_clear_data_ready_flag(const struct _i2c_s_sync_device *const device) +{ + hri_sercomi2cs_clear_INTFLAG_DRDY_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Retrieve I2C slave status + */ +i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device) +{ + return hri_sercomi2cs_read_STATUS_reg(device->hw); +} + +/** + * \brief Abort data transmission + */ +int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device) +{ + hri_sercomi2cs_clear_INTEN_DRDY_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Enable/disable I2C slave interrupt + */ +int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type, + const bool state) +{ + ASSERT(device); + + if (I2C_S_DEVICE_TX == type || I2C_S_DEVICE_RX_COMPLETE == type) { + hri_sercomi2cs_write_INTEN_DRDY_bit(device->hw, state); + } else if (I2C_S_DEVICE_ERROR == type) { + hri_sercomi2cs_write_INTEN_ERROR_bit(device->hw, state); + } + + return ERR_NONE; +} + +/** + * \internal Initalize i2c slave hardware + * + * \param[in] p The pointer to hardware instance + * + *\ return status of initialization + */ +static int32_t _i2c_s_init(void *const hw) +{ + int8_t i = _get_i2c_s_index(hw); + if (i == -1) { + return ERR_INVALID_ARG; + } + + if (!hri_sercomi2cs_is_syncing(hw, SERCOM_I2CS_CTRLA_SWRST)) { + uint32_t mode = _i2css[i].ctrl_a & SERCOM_I2CS_CTRLA_MODE_Msk; + if (hri_sercomi2cs_get_CTRLA_reg(hw, SERCOM_I2CS_CTRLA_ENABLE)) { + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_ENABLE); + } + hri_sercomi2cs_write_CTRLA_reg(hw, SERCOM_I2CS_CTRLA_SWRST | mode); + } + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); + + hri_sercomi2cs_write_CTRLA_reg(hw, _i2css[i].ctrl_a); + hri_sercomi2cs_write_CTRLB_reg(hw, _i2css[i].ctrl_b); + hri_sercomi2cs_write_ADDR_reg(hw, _i2css[i].address); + + return ERR_NONE; +} + +/** + * \internal Retrieve ordinal number of the given sercom hardware instance + * + * \param[in] hw The pointer to hardware instance + * + * \return The ordinal number of the given sercom hardware instance + */ +static int8_t _get_i2c_s_index(const void *const hw) +{ + uint8_t sercom_offset = _sercom_get_hardware_index(hw); + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(_i2css); i++) { + if (_i2css[i].number == sercom_offset) { + return i; + } + } + + ASSERT(false); + return -1; +} + +/** + * \internal De-initialize i2c slave + * + * \param[in] hw The pointer to hardware instance + */ +static inline void _i2c_s_deinit(void *const hw) +{ + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); + hri_sercomi2cs_set_CTRLA_SWRST_bit(hw); +} + +/** + * \internal De-initialize i2c slave + * + * \param[in] hw The pointer to hardware instance + * \param[in] address Address to set + */ +static int32_t _i2c_s_set_address(void *const hw, const uint16_t address) +{ + bool enabled; + + enabled = hri_sercomi2cs_get_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); + hri_sercomi2cs_write_ADDR_ADDR_bf(hw, address); + CRITICAL_SECTION_LEAVE() + + if (enabled) { + hri_sercomi2cs_set_CTRLA_ENABLE_bit(hw); + } + + return ERR_NONE; +} + + /* Sercom SPI implementation */ + +#ifndef SERCOM_USART_CTRLA_MODE_SPI_SLAVE +#define SERCOM_USART_CTRLA_MODE_SPI_SLAVE (2 << 2) +#endif + +#define SPI_DEV_IRQ_MODE 0x8000 + +#define _SPI_CS_PORT_EXTRACT(cs) (((cs) >> 0) & 0xFF) +#define _SPI_CS_PIN_EXTRACT(cs) (((cs) >> 8) & 0xFF) + +COMPILER_PACK_SET(1) +/** Initialization configuration of registers. */ +struct sercomspi_regs_cfg { + uint32_t ctrla; + uint32_t ctrlb; + uint32_t addr; + uint8_t baud; + uint8_t dbgctrl; + uint16_t dummy_byte; + uint8_t n; +}; +COMPILER_PACK_RESET() + +/** Build configuration from header macros. */ +#define SERCOMSPI_REGS(n) \ + { \ + (((CONF_SERCOM_##n##_SPI_DORD) << SERCOM_SPI_CTRLA_DORD_Pos) \ + | (CONF_SERCOM_##n##_SPI_CPOL << SERCOM_SPI_CTRLA_CPOL_Pos) \ + | (CONF_SERCOM_##n##_SPI_CPHA << SERCOM_SPI_CTRLA_CPHA_Pos) \ + | (CONF_SERCOM_##n##_SPI_AMODE_EN ? SERCOM_SPI_CTRLA_FORM(2) : SERCOM_SPI_CTRLA_FORM(0)) \ + | SERCOM_SPI_CTRLA_DOPO(CONF_SERCOM_##n##_SPI_TXPO) | SERCOM_SPI_CTRLA_DIPO(CONF_SERCOM_##n##_SPI_RXPO) \ + | (CONF_SERCOM_##n##_SPI_IBON << SERCOM_SPI_CTRLA_IBON_Pos) \ + | (CONF_SERCOM_##n##_SPI_RUNSTDBY << SERCOM_SPI_CTRLA_RUNSTDBY_Pos) \ + | SERCOM_SPI_CTRLA_MODE(CONF_SERCOM_##n##_SPI_MODE)), /* ctrla */ \ + ((CONF_SERCOM_##n##_SPI_RXEN << SERCOM_SPI_CTRLB_RXEN_Pos) \ + | (CONF_SERCOM_##n##_SPI_MSSEN << SERCOM_SPI_CTRLB_MSSEN_Pos) \ + | (CONF_SERCOM_##n##_SPI_SSDE << SERCOM_SPI_CTRLB_SSDE_Pos) \ + | (CONF_SERCOM_##n##_SPI_PLOADEN << SERCOM_SPI_CTRLB_PLOADEN_Pos) \ + | SERCOM_SPI_CTRLB_AMODE(CONF_SERCOM_##n##_SPI_AMODE) \ + | SERCOM_SPI_CTRLB_CHSIZE(CONF_SERCOM_##n##_SPI_CHSIZE)), /* ctrlb */ \ + (SERCOM_SPI_ADDR_ADDR(CONF_SERCOM_##n##_SPI_ADDR) \ + | SERCOM_SPI_ADDR_ADDRMASK(CONF_SERCOM_##n##_SPI_ADDRMASK)), /* addr */ \ + ((uint8_t)CONF_SERCOM_##n##_SPI_BAUD_RATE), /* baud */ \ + (CONF_SERCOM_##n##_SPI_DBGSTOP << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos), /* dbgctrl */ \ + CONF_SERCOM_##n##_SPI_DUMMYBYTE, /* Dummy byte for SPI master mode */ \ + n /* sercom number */ \ + } + +#ifndef CONF_SERCOM_0_SPI_ENABLE +#define CONF_SERCOM_0_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_SPI_ENABLE +#define CONF_SERCOM_1_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_SPI_ENABLE +#define CONF_SERCOM_2_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_SPI_ENABLE +#define CONF_SERCOM_3_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_SPI_ENABLE +#define CONF_SERCOM_4_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_SPI_ENABLE +#define CONF_SERCOM_5_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_SPI_ENABLE +#define CONF_SERCOM_6_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_SPI_ENABLE +#define CONF_SERCOM_7_SPI_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as SPI */ +#define SERCOM_SPI_AMOUNT \ + (CONF_SERCOM_0_SPI_ENABLE + CONF_SERCOM_1_SPI_ENABLE + CONF_SERCOM_2_SPI_ENABLE + CONF_SERCOM_3_SPI_ENABLE \ + + CONF_SERCOM_4_SPI_ENABLE + CONF_SERCOM_5_SPI_ENABLE + CONF_SERCOM_6_SPI_ENABLE + CONF_SERCOM_7_SPI_ENABLE) + +#if SERCOM_SPI_AMOUNT < 1 +/** Dummy array for compiling. */ +static const struct sercomspi_regs_cfg sercomspi_regs[1] = {{0}}; +#else +/** The SERCOM SPI configurations of SERCOM that is used as SPI. */ +static const struct sercomspi_regs_cfg sercomspi_regs[] = { +#if CONF_SERCOM_0_SPI_ENABLE + SERCOMSPI_REGS(0), +#endif +#if CONF_SERCOM_1_SPI_ENABLE + SERCOMSPI_REGS(1), +#endif +#if CONF_SERCOM_2_SPI_ENABLE + SERCOMSPI_REGS(2), +#endif +#if CONF_SERCOM_3_SPI_ENABLE + SERCOMSPI_REGS(3), +#endif +#if CONF_SERCOM_4_SPI_ENABLE + SERCOMSPI_REGS(4), +#endif +#if CONF_SERCOM_5_SPI_ENABLE + SERCOMSPI_REGS(5), +#endif +#if CONF_SERCOM_6_SPI_ENABLE + SERCOMSPI_REGS(6), +#endif +#if CONF_SERCOM_7_SPI_ENABLE + SERCOMSPI_REGS(7), +#endif +}; +#endif + +/** \internal De-initialize SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return De-initialization status + */ +static int32_t _spi_deinit(void *const hw) +{ + hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); + hri_sercomspi_set_CTRLA_SWRST_bit(hw); + + return ERR_NONE; +} + +/** \internal Enable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Enabling status + */ +static int32_t _spi_sync_enable(void *const hw) +{ + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + + hri_sercomspi_set_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** \internal Enable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Enabling status + */ +static int32_t _spi_async_enable(void *const hw) +{ + _spi_sync_enable(hw); + NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + + return ERR_NONE; +} + +/** \internal Disable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Disabling status + */ +static int32_t _spi_sync_disable(void *const hw) +{ + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** \internal Disable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Disabling status + */ +static int32_t _spi_async_disable(void *const hw) +{ + _spi_sync_disable(hw); + hri_sercomspi_clear_INTEN_reg( + hw, SERCOM_SPI_INTFLAG_ERROR | SERCOM_SPI_INTFLAG_RXC | SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE); + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI mode + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] mode The mode to set + * + * \return Setting mode status + */ +static int32_t _spi_set_mode(void *const hw, const enum spi_transfer_mode mode) +{ + uint32_t ctrla; + + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE)) { + return ERR_BUSY; + } + + ctrla = hri_sercomspi_read_CTRLA_reg(hw); + ctrla &= ~(SERCOM_SPI_CTRLA_CPOL | SERCOM_SPI_CTRLA_CPHA); + ctrla |= (mode & 0x3u) << SERCOM_SPI_CTRLA_CPHA_Pos; + hri_sercomspi_write_CTRLA_reg(hw, ctrla); + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI baudrate + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] baud_val The baudrate to set + * + * \return Setting baudrate status + */ +static int32_t _spi_set_baudrate(void *const hw, const uint32_t baud_val) +{ + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + + hri_sercomspi_write_BAUD_reg(hw, baud_val); + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI char size + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] baud_val The baudrate to set + * \param[out] size Stored char size + * + * \return Setting char size status + */ +static int32_t _spi_set_char_size(void *const hw, const enum spi_char_size char_size, uint8_t *const size) +{ + /* Only 8-bit or 9-bit accepted */ + if (!(char_size == SPI_CHAR_SIZE_8 || char_size == SPI_CHAR_SIZE_9)) { + return ERR_INVALID_ARG; + } + + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_CTRLB)) { + return ERR_BUSY; + } + + hri_sercomspi_write_CTRLB_CHSIZE_bf(hw, char_size); + *size = (char_size == SPI_CHAR_SIZE_8) ? 1 : 2; + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI data order + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] baud_val The baudrate to set + * + * \return Setting data order status + */ +static int32_t _spi_set_data_order(void *const hw, const enum spi_data_order dord) +{ + uint32_t ctrla; + + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + + ctrla = hri_sercomspi_read_CTRLA_reg(hw); + + if (dord == SPI_DATA_ORDER_LSB_1ST) { + ctrla |= SERCOM_SPI_CTRLA_DORD; + } else { + ctrla &= ~SERCOM_SPI_CTRLA_DORD; + } + hri_sercomspi_write_CTRLA_reg(hw, ctrla); + + return ERR_NONE; +} + +/** \brief Load SERCOM registers to init for SPI master mode + * The settings will be applied with default master mode, unsupported things + * are ignored. + * \param[in, out] hw Pointer to the hardware register base. + * \param[in] regs Pointer to register configuration values. + */ +static inline void _spi_load_regs_master(void *const hw, const struct sercomspi_regs_cfg *regs) +{ + ASSERT(hw && regs); + hri_sercomspi_write_CTRLA_reg( + hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST)); + hri_sercomspi_write_CTRLB_reg( + hw, + (regs->ctrlb + & ~(SERCOM_SPI_CTRLB_MSSEN | SERCOM_SPI_CTRLB_AMODE_Msk | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN)) + | (SERCOM_SPI_CTRLB_RXEN)); + hri_sercomspi_write_BAUD_reg(hw, regs->baud); + hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl); +} + +/** \brief Load SERCOM registers to init for SPI slave mode + * The settings will be applied with default slave mode, unsupported things + * are ignored. + * \param[in, out] hw Pointer to the hardware register base. + * \param[in] regs Pointer to register configuration values. + */ +static inline void _spi_load_regs_slave(void *const hw, const struct sercomspi_regs_cfg *regs) +{ + ASSERT(hw && regs); + hri_sercomspi_write_CTRLA_reg( + hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST)); + hri_sercomspi_write_CTRLB_reg(hw, + (regs->ctrlb & ~(SERCOM_SPI_CTRLB_MSSEN)) + | (SERCOM_SPI_CTRLB_RXEN | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN)); + hri_sercomspi_write_ADDR_reg(hw, regs->addr); + hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl); + while (hri_sercomspi_is_syncing(hw, 0xFFFFFFFF)) + ; +} + +/** \brief Return the pointer to register settings of specific SERCOM + * \param[in] hw_addr The hardware register base address. + * \return Pointer to register settings of specific SERCOM. + */ +static inline const struct sercomspi_regs_cfg *_spi_get_regs(const uint32_t hw_addr) +{ + uint8_t n = _sercom_get_hardware_index((const void *)hw_addr); + uint8_t i; + + for (i = 0; i < sizeof(sercomspi_regs) / sizeof(struct sercomspi_regs_cfg); i++) { + if (sercomspi_regs[i].n == n) { + return &sercomspi_regs[i]; + } + } + + return NULL; +} + +int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw) +{ + const struct sercomspi_regs_cfg *regs = _spi_get_regs((uint32_t)hw); + + ASSERT(dev && hw); + + if (regs == NULL) { + return ERR_INVALID_ARG; + } + + if (!hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + uint32_t mode = regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk; + if (hri_sercomspi_get_CTRLA_reg(hw, SERCOM_SPI_CTRLA_ENABLE)) { + hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_ENABLE); + } + hri_sercomspi_write_CTRLA_reg(hw, SERCOM_SPI_CTRLA_SWRST | mode); + } + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); + + dev->prvt = hw; + + if ((regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk) == SERCOM_USART_CTRLA_MODE_SPI_SLAVE) { + _spi_load_regs_slave(hw, regs); + } else { + _spi_load_regs_master(hw, regs); + } + + /* Load character size from default hardware configuration */ + dev->char_size = ((regs->ctrlb & SERCOM_SPI_CTRLB_CHSIZE_Msk) == 0) ? 1 : 2; + + dev->dummy_byte = regs->dummy_byte; + + return ERR_NONE; +} + +int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw) +{ + return _spi_m_sync_init(dev, hw); +} + +int32_t _spi_m_async_init(struct _spi_async_dev *dev, void *const hw) +{ + struct _spi_async_dev *spid = dev; + /* Do hardware initialize. */ + int32_t rc = _spi_m_sync_init((struct _spi_m_sync_dev *)dev, hw); + + if (rc < 0) { + return rc; + } + + _sercom_init_irq_param(hw, (void *)dev); + /* Initialize callbacks: must use them */ + spid->callbacks.complete = NULL; + spid->callbacks.rx = NULL; + spid->callbacks.tx = NULL; + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + + return ERR_NONE; +} + +int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw) +{ + return _spi_m_async_init(dev, hw); +} + +int32_t _spi_m_async_deinit(struct _spi_async_dev *dev) +{ + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); + + return _spi_deinit(dev->prvt); +} + +int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev) +{ + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); + + return _spi_deinit(dev->prvt); +} + +int32_t _spi_m_sync_deinit(struct _spi_m_sync_dev *dev) +{ + return _spi_deinit(dev->prvt); +} + +int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev) +{ + return _spi_deinit(dev->prvt); +} + +int32_t _spi_m_sync_enable(struct _spi_m_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_enable(dev->prvt); +} + +int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_enable(dev->prvt); +} + +int32_t _spi_m_async_enable(struct _spi_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_enable(dev->prvt); +} + +int32_t _spi_s_async_enable(struct _spi_s_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_enable(dev->prvt); +} + +int32_t _spi_m_sync_disable(struct _spi_m_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_disable(dev->prvt); +} + +int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_disable(dev->prvt); +} + +int32_t _spi_m_async_disable(struct _spi_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_disable(dev->prvt); +} + +int32_t _spi_s_async_disable(struct _spi_s_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_disable(dev->prvt); +} + +int32_t _spi_m_sync_set_mode(struct _spi_m_sync_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_m_async_set_mode(struct _spi_async_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_s_async_set_mode(struct _spi_s_async_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_calc_baud_val(struct spi_dev *dev, const uint32_t clk, const uint32_t baud) +{ + int32_t rc; + ASSERT(dev); + + /* Not accept 0es */ + if (clk == 0 || baud == 0) { + return ERR_INVALID_ARG; + } + + /* Check baudrate range of current assigned clock */ + if (!(baud <= (clk >> 1) && baud >= (clk >> 8))) { + return ERR_INVALID_ARG; + } + + rc = ((clk >> 1) / baud) - 1; + return rc; +} + +int32_t _spi_m_sync_set_baudrate(struct _spi_m_sync_dev *dev, const uint32_t baud_val) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_baudrate(dev->prvt, baud_val); +} + +int32_t _spi_m_async_set_baudrate(struct _spi_async_dev *dev, const uint32_t baud_val) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_baudrate(dev->prvt, baud_val); +} + +int32_t _spi_m_sync_set_char_size(struct _spi_m_sync_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_m_async_set_char_size(struct _spi_async_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_s_async_set_char_size(struct _spi_s_async_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_m_sync_set_data_order(struct _spi_m_sync_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +int32_t _spi_m_async_set_data_order(struct _spi_async_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +int32_t _spi_s_async_set_data_order(struct _spi_s_async_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +/** Wait until SPI bus idle. */ +static inline void _spi_wait_bus_idle(void *const hw) +{ + while (!(hri_sercomspi_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE))) { + ; + } + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE); +} + +/** Holds run time information for message sync transaction. */ +struct _spi_trans_ctrl { + /** Pointer to transmitting data buffer. */ + uint8_t *txbuf; + /** Pointer to receiving data buffer. */ + uint8_t *rxbuf; + /** Count number of data transmitted. */ + uint32_t txcnt; + /** Count number of data received. */ + uint32_t rxcnt; + /** Data character size. */ + uint8_t char_size; +}; + +/** Check interrupt flag of RXC and update transaction runtime information. */ +static inline bool _spi_rx_check_and_receive(void *const hw, const uint32_t iflag, struct _spi_trans_ctrl *ctrl) +{ + uint32_t data; + + if (!(iflag & SERCOM_SPI_INTFLAG_RXC)) { + return false; + } + + data = hri_sercomspi_read_DATA_reg(hw); + + if (ctrl->rxbuf) { + *ctrl->rxbuf++ = (uint8_t)data; + + if (ctrl->char_size > 1) { + *ctrl->rxbuf++ = (uint8_t)(data >> 8); + } + } + + ctrl->rxcnt++; + + return true; +} + +/** Check interrupt flag of DRE and update transaction runtime information. */ +static inline void _spi_tx_check_and_send(void *const hw, const uint32_t iflag, struct _spi_trans_ctrl *ctrl, + uint16_t dummy) +{ + uint32_t data; + + if (!(SERCOM_SPI_INTFLAG_DRE & iflag)) { + return; + } + + if (ctrl->txbuf) { + data = *ctrl->txbuf++; + + if (ctrl->char_size > 1) { + data |= (*ctrl->txbuf) << 8; + ctrl->txbuf++; + } + } else { + data = dummy; + } + + ctrl->txcnt++; + hri_sercomspi_write_DATA_reg(hw, data); +} + +/** Check interrupt flag of ERROR and update transaction runtime information. */ +static inline int32_t _spi_err_check(const uint32_t iflag, void *const hw) +{ + if (SERCOM_SPI_INTFLAG_ERROR & iflag) { + hri_sercomspi_clear_STATUS_reg(hw, ~0); + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR); + return ERR_OVERFLOW; + } + + return ERR_NONE; +} + +int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg) +{ + void * hw = dev->prvt; + int32_t rc = 0; + struct _spi_trans_ctrl ctrl = {msg->txbuf, msg->rxbuf, 0, 0, dev->char_size}; + + ASSERT(dev && hw); + + /* If settings are not applied (pending), we can not go on */ + if (hri_sercomspi_is_syncing( + hw, (SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE | SERCOM_SPI_SYNCBUSY_CTRLB))) { + return ERR_BUSY; + } + + /* SPI must be enabled to start synchronous transfer */ + if (!hri_sercomspi_get_CTRLA_ENABLE_bit(hw)) { + return ERR_NOT_INITIALIZED; + } + + for (;;) { + uint32_t iflag = hri_sercomspi_read_INTFLAG_reg(hw); + + if (!_spi_rx_check_and_receive(hw, iflag, &ctrl)) { + /* In master mode, do not start next byte before previous byte received + * to make better output waveform */ + if (ctrl.rxcnt >= ctrl.txcnt) { + _spi_tx_check_and_send(hw, iflag, &ctrl, dev->dummy_byte); + } + } + + rc = _spi_err_check(iflag, hw); + + if (rc < 0) { + break; + } + if (ctrl.txcnt >= msg->size && ctrl.rxcnt >= msg->size) { + rc = ctrl.txcnt; + break; + } + } + /* Wait until SPI bus idle */ + _spi_wait_bus_idle(hw); + + return rc; +} + +int32_t _spi_m_async_enable_tx(struct _spi_async_dev *dev, bool state) +{ + void *hw = dev->prvt; + + ASSERT(dev && hw); + + if (state) { + hri_sercomspi_set_INTEN_DRE_bit(hw); + } else { + hri_sercomspi_clear_INTEN_DRE_bit(hw); + } + + return ERR_NONE; +} + +int32_t _spi_s_async_enable_tx(struct _spi_s_async_dev *dev, bool state) +{ + return _spi_m_async_enable_tx(dev, state); +} + +int32_t _spi_m_async_enable_rx(struct _spi_async_dev *dev, bool state) +{ + void *hw = dev->prvt; + + ASSERT(dev); + ASSERT(hw); + + if (state) { + hri_sercomspi_set_INTEN_RXC_bit(hw); + } else { + hri_sercomspi_clear_INTEN_RXC_bit(hw); + } + + return ERR_NONE; +} + +int32_t _spi_s_async_enable_rx(struct _spi_s_async_dev *dev, bool state) +{ + return _spi_m_async_enable_rx(dev, state); +} + +int32_t _spi_m_async_enable_tx_complete(struct _spi_async_dev *dev, bool state) +{ + ASSERT(dev && dev->prvt); + + if (state) { + hri_sercomspi_set_INTEN_TXC_bit(dev->prvt); + } else { + hri_sercomspi_clear_INTEN_TXC_bit(dev->prvt); + } + + return ERR_NONE; +} + +int32_t _spi_s_async_enable_ss_detect(struct _spi_s_async_dev *dev, bool state) +{ + return _spi_m_async_enable_tx_complete(dev, state); +} + +int32_t _spi_m_async_write_one(struct _spi_async_dev *dev, uint16_t data) +{ + ASSERT(dev && dev->prvt); + + hri_sercomspi_write_DATA_reg(dev->prvt, data); + + return ERR_NONE; +} + +int32_t _spi_s_async_write_one(struct _spi_s_async_dev *dev, uint16_t data) +{ + ASSERT(dev && dev->prvt); + + hri_sercomspi_write_DATA_reg(dev->prvt, data); + + return ERR_NONE; +} + +int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data) +{ + ASSERT(dev && dev->prvt); + + hri_sercomspi_write_DATA_reg(dev->prvt, data); + + return ERR_NONE; +} + +uint16_t _spi_m_async_read_one(struct _spi_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomspi_read_DATA_reg(dev->prvt); +} + +uint16_t _spi_s_async_read_one(struct _spi_s_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomspi_read_DATA_reg(dev->prvt); +} + +uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomspi_read_DATA_reg(dev->prvt); +} + +int32_t _spi_m_async_register_callback(struct _spi_async_dev *dev, const enum _spi_async_dev_cb_type cb_type, + const FUNC_PTR func) +{ + typedef void (*func_t)(void); + struct _spi_async_dev *spid = dev; + + ASSERT(dev && (cb_type < SPI_DEV_CB_N)); + + func_t *p_ls = (func_t *)&spid->callbacks; + p_ls[cb_type] = (func_t)func; + + return ERR_NONE; +} + +int32_t _spi_s_async_register_callback(struct _spi_s_async_dev *dev, const enum _spi_s_async_dev_cb_type cb_type, + const FUNC_PTR func) +{ + return _spi_m_async_register_callback(dev, cb_type, func); +} + +bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomi2cm_get_INTFLAG_reg(dev->prvt, SERCOM_SPI_INTFLAG_DRE); +} + +bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomi2cm_get_INTFLAG_reg(dev->prvt, SERCOM_SPI_INTFLAG_RXC); +} + +bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev) +{ + void *hw = dev->prvt; + + ASSERT(dev && hw); + + if (hri_sercomi2cm_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC)) { + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC); + return true; + } + return false; +} + +bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev) +{ + void *hw = dev->prvt; + + ASSERT(dev && hw); + + if (hri_sercomi2cm_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR)) { + hri_sercomspi_clear_STATUS_reg(hw, SERCOM_SPI_STATUS_BUFOVF); + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR); + return true; + } + return false; +} + +/** + * \brief Enable/disable SPI master interrupt + * + * param[in] device The pointer to SPI master device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _spi_m_async_set_irq_state(struct _spi_async_dev *const device, const enum _spi_async_dev_cb_type type, + const bool state) +{ + ASSERT(device); + + if (SPI_DEV_CB_ERROR == type) { + hri_sercomspi_write_INTEN_ERROR_bit(device->prvt, state); + } +} + +/** + * \brief Enable/disable SPI slave interrupt + * + * param[in] device The pointer to SPI slave device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _spi_s_async_set_irq_state(struct _spi_async_dev *const device, const enum _spi_async_dev_cb_type type, + const bool state) +{ + _spi_m_async_set_irq_state(device, type, state); +} diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_ac_l21.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_ac_l21.h new file mode 100644 index 00000000..e7c6018b --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_ac_l21.h @@ -0,0 +1,1746 @@ +/** + * \file + * + * \brief SAM AC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_AC_COMPONENT_ +#ifndef _HRI_AC_L21_H_INCLUDED_ +#define _HRI_AC_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_AC_CRITICAL_SECTIONS) +#define AC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define AC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define AC_CRITICAL_SECTION_ENTER() +#define AC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_ac_evctrl_reg_t; +typedef uint32_t hri_ac_compctrl_reg_t; +typedef uint32_t hri_ac_syncbusy_reg_t; +typedef uint8_t hri_ac_ctrla_reg_t; +typedef uint8_t hri_ac_ctrlb_reg_t; +typedef uint8_t hri_ac_dbgctrl_reg_t; +typedef uint8_t hri_ac_intenset_reg_t; +typedef uint8_t hri_ac_intflag_reg_t; +typedef uint8_t hri_ac_scaler_reg_t; +typedef uint8_t hri_ac_statusa_reg_t; +typedef uint8_t hri_ac_statusb_reg_t; +typedef uint8_t hri_ac_winctrl_reg_t; + +static inline void hri_ac_wait_for_sync(const void *const hw, hri_ac_syncbusy_reg_t reg) +{ + while (((Ac *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_ac_is_syncing(const void *const hw, hri_ac_syncbusy_reg_t reg) +{ + return ((Ac *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_ac_get_INTFLAG_COMP0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos; +} + +static inline void hri_ac_clear_INTFLAG_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0; +} + +static inline bool hri_ac_get_INTFLAG_COMP1_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos; +} + +static inline void hri_ac_clear_INTFLAG_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1; +} + +static inline bool hri_ac_get_INTFLAG_WIN0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos; +} + +static inline void hri_ac_clear_INTFLAG_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0; +} + +static inline bool hri_ac_get_interrupt_COMP0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos; +} + +static inline void hri_ac_clear_interrupt_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0; +} + +static inline bool hri_ac_get_interrupt_COMP1_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos; +} + +static inline void hri_ac_clear_interrupt_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1; +} + +static inline bool hri_ac_get_interrupt_WIN0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos; +} + +static inline void hri_ac_clear_interrupt_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0; +} + +static inline hri_ac_intflag_reg_t hri_ac_get_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_intflag_reg_t hri_ac_read_INTFLAG_reg(const void *const hw) +{ + return ((Ac *)hw)->INTFLAG.reg; +} + +static inline void hri_ac_clear_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask) +{ + ((Ac *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_ac_set_INTEN_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0; +} + +static inline bool hri_ac_get_INTEN_COMP0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP0) >> AC_INTENSET_COMP0_Pos; +} + +static inline void hri_ac_write_INTEN_COMP0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0; + } else { + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0; + } +} + +static inline void hri_ac_clear_INTEN_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0; +} + +static inline void hri_ac_set_INTEN_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1; +} + +static inline bool hri_ac_get_INTEN_COMP1_bit(const void *const hw) +{ + return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP1) >> AC_INTENSET_COMP1_Pos; +} + +static inline void hri_ac_write_INTEN_COMP1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1; + } else { + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1; + } +} + +static inline void hri_ac_clear_INTEN_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1; +} + +static inline void hri_ac_set_INTEN_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0; +} + +static inline bool hri_ac_get_INTEN_WIN0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_WIN0) >> AC_INTENSET_WIN0_Pos; +} + +static inline void hri_ac_write_INTEN_WIN0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0; + } else { + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0; + } +} + +static inline void hri_ac_clear_INTEN_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0; +} + +static inline void hri_ac_set_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) +{ + ((Ac *)hw)->INTENSET.reg = mask; +} + +static inline hri_ac_intenset_reg_t hri_ac_get_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_intenset_reg_t hri_ac_read_INTEN_reg(const void *const hw) +{ + return ((Ac *)hw)->INTENSET.reg; +} + +static inline void hri_ac_write_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t data) +{ + ((Ac *)hw)->INTENSET.reg = data; + ((Ac *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_ac_clear_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) +{ + ((Ac *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_ac_get_STATUSA_STATE0_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE0) >> AC_STATUSA_STATE0_Pos; +} + +static inline bool hri_ac_get_STATUSA_STATE1_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE1) >> AC_STATUSA_STATE1_Pos; +} + +static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_WSTATE0_bf(const void *const hw, hri_ac_statusa_reg_t mask) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0(mask)) >> AC_STATUSA_WSTATE0_Pos; +} + +static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_WSTATE0_bf(const void *const hw) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0_Msk) >> AC_STATUSA_WSTATE0_Pos; +} + +static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_reg(const void *const hw, hri_ac_statusa_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->STATUSA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_reg(const void *const hw) +{ + return ((Ac *)hw)->STATUSA.reg; +} + +static inline bool hri_ac_get_STATUSB_READY0_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY0) >> AC_STATUSB_READY0_Pos; +} + +static inline bool hri_ac_get_STATUSB_READY1_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY1) >> AC_STATUSB_READY1_Pos; +} + +static inline hri_ac_statusb_reg_t hri_ac_get_STATUSB_reg(const void *const hw, hri_ac_statusb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->STATUSB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_statusb_reg_t hri_ac_read_STATUSB_reg(const void *const hw) +{ + return ((Ac *)hw)->STATUSB.reg; +} + +static inline bool hri_ac_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_SWRST) >> AC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_ENABLE) >> AC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_WINCTRL_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_WINCTRL) >> AC_SYNCBUSY_WINCTRL_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_COMPCTRL0_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL0) >> AC_SYNCBUSY_COMPCTRL0_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_COMPCTRL1_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL1) >> AC_SYNCBUSY_COMPCTRL1_Pos; +} + +static inline hri_ac_syncbusy_reg_t hri_ac_get_SYNCBUSY_reg(const void *const hw, hri_ac_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_syncbusy_reg_t hri_ac_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Ac *)hw)->SYNCBUSY.reg; +} + +static inline void hri_ac_set_CTRLA_SWRST_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg |= AC_CTRLA_SWRST; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp = (tmp & AC_CTRLA_SWRST) >> AC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_ac_set_CTRLA_ENABLE_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg |= AC_CTRLA_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp = (tmp & AC_CTRLA_ENABLE) >> AC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp &= ~AC_CTRLA_ENABLE; + tmp |= value << AC_CTRLA_ENABLE_Pos; + ((Ac *)hw)->CTRLA.reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg &= ~AC_CTRLA_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg ^= AC_CTRLA_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg |= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_ctrla_reg_t hri_ac_get_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg = data; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg &= ~mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg ^= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_ctrla_reg_t hri_ac_read_CTRLA_reg(const void *const hw) +{ + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + return ((Ac *)hw)->CTRLA.reg; +} + +static inline void hri_ac_set_EVCTRL_COMPEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEO0) >> AC_EVCTRL_COMPEO0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEO0; + tmp |= value << AC_EVCTRL_COMPEO0_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_COMPEO1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEO1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEO1) >> AC_EVCTRL_COMPEO1_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEO1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEO1; + tmp |= value << AC_EVCTRL_COMPEO1_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEO1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEO1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_WINEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_WINEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_WINEO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_WINEO0) >> AC_EVCTRL_WINEO0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_WINEO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_WINEO0; + tmp |= value << AC_EVCTRL_WINEO0_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_WINEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_WINEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_WINEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_WINEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_COMPEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEI0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEI0) >> AC_EVCTRL_COMPEI0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEI0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEI0; + tmp |= value << AC_EVCTRL_COMPEI0_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_COMPEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEI1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEI1) >> AC_EVCTRL_COMPEI1_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEI1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEI1; + tmp |= value << AC_EVCTRL_COMPEI1_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_INVEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_INVEI0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_INVEI0) >> AC_EVCTRL_INVEI0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_INVEI0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_INVEI0; + tmp |= value << AC_EVCTRL_INVEI0_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_INVEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_INVEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_INVEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_INVEI1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_INVEI1) >> AC_EVCTRL_INVEI1_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_INVEI1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_INVEI1; + tmp |= value << AC_EVCTRL_INVEI1_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_INVEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_INVEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_evctrl_reg_t hri_ac_get_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_evctrl_reg_t hri_ac_read_EVCTRL_reg(const void *const hw) +{ + return ((Ac *)hw)->EVCTRL.reg; +} + +static inline void hri_ac_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg |= AC_DBGCTRL_DBGRUN; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->DBGCTRL.reg; + tmp = (tmp & AC_DBGCTRL_DBGRUN) >> AC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->DBGCTRL.reg; + tmp &= ~AC_DBGCTRL_DBGRUN; + tmp |= value << AC_DBGCTRL_DBGRUN_Pos; + ((Ac *)hw)->DBGCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg &= ~AC_DBGCTRL_DBGRUN; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg ^= AC_DBGCTRL_DBGRUN; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg |= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_dbgctrl_reg_t hri_ac_get_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg &= ~mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg ^= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_dbgctrl_reg_t hri_ac_read_DBGCTRL_reg(const void *const hw) +{ + return ((Ac *)hw)->DBGCTRL.reg; +} + +static inline void hri_ac_set_WINCTRL_WEN0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WEN0; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_WINCTRL_WEN0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp = (tmp & AC_WINCTRL_WEN0) >> AC_WINCTRL_WEN0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_WINCTRL_WEN0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp &= ~AC_WINCTRL_WEN0; + tmp |= value << AC_WINCTRL_WEN0_Pos; + ((Ac *)hw)->WINCTRL.reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_WINCTRL_WEN0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WEN0; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_WINCTRL_WEN0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WEN0; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WINTSEL0(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp = (tmp & AC_WINCTRL_WINTSEL0(mask)) >> AC_WINCTRL_WINTSEL0_Pos; + return tmp; +} + +static inline void hri_ac_write_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t data) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp &= ~AC_WINCTRL_WINTSEL0_Msk; + tmp |= AC_WINCTRL_WINTSEL0(data); + ((Ac *)hw)->WINCTRL.reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WINTSEL0(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WINTSEL0(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_WINTSEL0_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp = (tmp & AC_WINCTRL_WINTSEL0_Msk) >> AC_WINCTRL_WINTSEL0_Pos; + return tmp; +} + +static inline void hri_ac_set_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg |= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg = data; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg &= ~mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg ^= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_reg(const void *const hw) +{ + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + return ((Ac *)hw)->WINCTRL.reg; +} + +static inline void hri_ac_set_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg |= AC_SCALER_VALUE(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_VALUE_bf(const void *const hw, uint8_t index, + hri_ac_scaler_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp = (tmp & AC_SCALER_VALUE(mask)) >> AC_SCALER_VALUE_Pos; + return tmp; +} + +static inline void hri_ac_write_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp &= ~AC_SCALER_VALUE_Msk; + tmp |= AC_SCALER_VALUE(data); + ((Ac *)hw)->SCALER[index].reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg &= ~AC_SCALER_VALUE(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg ^= AC_SCALER_VALUE(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_VALUE_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp = (tmp & AC_SCALER_VALUE_Msk) >> AC_SCALER_VALUE_Pos; + return tmp; +} + +static inline void hri_ac_set_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg |= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg &= ~mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg ^= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_reg(const void *const hw, uint8_t index) +{ + return ((Ac *)hw)->SCALER[index].reg; +} + +static inline void hri_ac_set_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_ENABLE) >> AC_COMPCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_ENABLE; + tmp |= value << AC_COMPCTRL_ENABLE_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SINGLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SINGLE) >> AC_COMPCTRL_SINGLE_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_SINGLE; + tmp |= value << AC_COMPCTRL_SINGLE_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SINGLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SINGLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_RUNSTDBY; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_RUNSTDBY) >> AC_COMPCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_RUNSTDBY; + tmp |= value << AC_COMPCTRL_RUNSTDBY_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_RUNSTDBY; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_RUNSTDBY; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SWAP; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SWAP) >> AC_COMPCTRL_SWAP_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_SWAP; + tmp |= value << AC_COMPCTRL_SWAP_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SWAP; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SWAP; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_HYSTEN; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_HYSTEN) >> AC_COMPCTRL_HYSTEN_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_HYSTEN; + tmp |= value << AC_COMPCTRL_HYSTEN_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_HYSTEN; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_HYSTEN; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_INTSEL(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_INTSEL(mask)) >> AC_COMPCTRL_INTSEL_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_INTSEL_Msk; + tmp |= AC_COMPCTRL_INTSEL(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_INTSEL(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_INTSEL(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_INTSEL_Msk) >> AC_COMPCTRL_INTSEL_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXNEG(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXNEG(mask)) >> AC_COMPCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_MUXNEG_Msk; + tmp |= AC_COMPCTRL_MUXNEG(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXNEG(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXNEG(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXNEG_Msk) >> AC_COMPCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXPOS(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXPOS(mask)) >> AC_COMPCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_MUXPOS_Msk; + tmp |= AC_COMPCTRL_MUXPOS(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXPOS(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXPOS(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXPOS_Msk) >> AC_COMPCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SPEED(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SPEED(mask)) >> AC_COMPCTRL_SPEED_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_SPEED_Msk; + tmp |= AC_COMPCTRL_SPEED(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SPEED(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SPEED(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SPEED_Msk) >> AC_COMPCTRL_SPEED_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_HYST(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_HYST(mask)) >> AC_COMPCTRL_HYST_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_HYST_Msk; + tmp |= AC_COMPCTRL_HYST(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_HYST(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_HYST(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_HYST_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_HYST_Msk) >> AC_COMPCTRL_HYST_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_FLEN(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_FLEN(mask)) >> AC_COMPCTRL_FLEN_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_FLEN_Msk; + tmp |= AC_COMPCTRL_FLEN(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_FLEN(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_FLEN(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_FLEN_Msk) >> AC_COMPCTRL_FLEN_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_OUT(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_OUT(mask)) >> AC_COMPCTRL_OUT_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_OUT_Msk; + tmp |= AC_COMPCTRL_OUT(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_OUT(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_OUT(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_OUT_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_OUT_Msk) >> AC_COMPCTRL_OUT_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_reg(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg = data; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_reg(const void *const hw, uint8_t index) +{ + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + return ((Ac *)hw)->COMPCTRL[index].reg; +} + +static inline void hri_ac_write_CTRLB_reg(const void *const hw, hri_ac_ctrlb_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLB.reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_AC_L21_H_INCLUDED */ +#endif /* _SAML21_AC_COMPONENT_ */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_adc_l21.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_adc_l21.h new file mode 100644 index 00000000..296e2cec --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_adc_l21.h @@ -0,0 +1,2707 @@ +/** + * \file + * + * \brief SAM ADC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_ADC_COMPONENT_ +#ifndef _HRI_ADC_L21_H_INCLUDED_ +#define _HRI_ADC_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_ADC_CRITICAL_SECTIONS) +#define ADC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define ADC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define ADC_CRITICAL_SECTION_ENTER() +#define ADC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_adc_calib_reg_t; +typedef uint16_t hri_adc_ctrlc_reg_t; +typedef uint16_t hri_adc_gaincorr_reg_t; +typedef uint16_t hri_adc_inputctrl_reg_t; +typedef uint16_t hri_adc_offsetcorr_reg_t; +typedef uint16_t hri_adc_result_reg_t; +typedef uint16_t hri_adc_syncbusy_reg_t; +typedef uint16_t hri_adc_winlt_reg_t; +typedef uint16_t hri_adc_winut_reg_t; +typedef uint32_t hri_adc_seqctrl_reg_t; +typedef uint8_t hri_adc_avgctrl_reg_t; +typedef uint8_t hri_adc_ctrla_reg_t; +typedef uint8_t hri_adc_ctrlb_reg_t; +typedef uint8_t hri_adc_dbgctrl_reg_t; +typedef uint8_t hri_adc_evctrl_reg_t; +typedef uint8_t hri_adc_intenset_reg_t; +typedef uint8_t hri_adc_intflag_reg_t; +typedef uint8_t hri_adc_refctrl_reg_t; +typedef uint8_t hri_adc_sampctrl_reg_t; +typedef uint8_t hri_adc_seqstatus_reg_t; +typedef uint8_t hri_adc_swtrig_reg_t; + +static inline void hri_adc_wait_for_sync(const void *const hw, hri_adc_syncbusy_reg_t reg) +{ + while (((Adc *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_adc_is_syncing(const void *const hw, hri_adc_syncbusy_reg_t reg) +{ + return ((Adc *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_adc_get_INTFLAG_RESRDY_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos; +} + +static inline void hri_adc_clear_INTFLAG_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY; +} + +static inline bool hri_adc_get_INTFLAG_OVERRUN_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos; +} + +static inline void hri_adc_clear_INTFLAG_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN; +} + +static inline bool hri_adc_get_INTFLAG_WINMON_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos; +} + +static inline void hri_adc_clear_INTFLAG_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON; +} + +static inline bool hri_adc_get_interrupt_RESRDY_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos; +} + +static inline void hri_adc_clear_interrupt_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY; +} + +static inline bool hri_adc_get_interrupt_OVERRUN_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos; +} + +static inline void hri_adc_clear_interrupt_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN; +} + +static inline bool hri_adc_get_interrupt_WINMON_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos; +} + +static inline void hri_adc_clear_interrupt_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON; +} + +static inline hri_adc_intflag_reg_t hri_adc_get_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_intflag_reg_t hri_adc_read_INTFLAG_reg(const void *const hw) +{ + return ((Adc *)hw)->INTFLAG.reg; +} + +static inline void hri_adc_clear_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask) +{ + ((Adc *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_adc_set_INTEN_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY; +} + +static inline bool hri_adc_get_INTEN_RESRDY_bit(const void *const hw) +{ + return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_RESRDY) >> ADC_INTENSET_RESRDY_Pos; +} + +static inline void hri_adc_write_INTEN_RESRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY; + } else { + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY; + } +} + +static inline void hri_adc_clear_INTEN_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY; +} + +static inline void hri_adc_set_INTEN_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN; +} + +static inline bool hri_adc_get_INTEN_OVERRUN_bit(const void *const hw) +{ + return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_OVERRUN) >> ADC_INTENSET_OVERRUN_Pos; +} + +static inline void hri_adc_write_INTEN_OVERRUN_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN; + } else { + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN; + } +} + +static inline void hri_adc_clear_INTEN_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN; +} + +static inline void hri_adc_set_INTEN_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON; +} + +static inline bool hri_adc_get_INTEN_WINMON_bit(const void *const hw) +{ + return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_WINMON) >> ADC_INTENSET_WINMON_Pos; +} + +static inline void hri_adc_write_INTEN_WINMON_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON; + } else { + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON; + } +} + +static inline void hri_adc_clear_INTEN_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON; +} + +static inline void hri_adc_set_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) +{ + ((Adc *)hw)->INTENSET.reg = mask; +} + +static inline hri_adc_intenset_reg_t hri_adc_get_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_intenset_reg_t hri_adc_read_INTEN_reg(const void *const hw) +{ + return ((Adc *)hw)->INTENSET.reg; +} + +static inline void hri_adc_write_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t data) +{ + ((Adc *)hw)->INTENSET.reg = data; + ((Adc *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_adc_clear_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) +{ + ((Adc *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_adc_get_SEQSTATUS_SEQBUSY_bit(const void *const hw) +{ + return (((Adc *)hw)->SEQSTATUS.reg & ADC_SEQSTATUS_SEQBUSY) >> ADC_SEQSTATUS_SEQBUSY_Pos; +} + +static inline hri_adc_seqstatus_reg_t hri_adc_get_SEQSTATUS_SEQSTATE_bf(const void *const hw, + hri_adc_seqstatus_reg_t mask) +{ + return (((Adc *)hw)->SEQSTATUS.reg & ADC_SEQSTATUS_SEQSTATE(mask)) >> ADC_SEQSTATUS_SEQSTATE_Pos; +} + +static inline hri_adc_seqstatus_reg_t hri_adc_read_SEQSTATUS_SEQSTATE_bf(const void *const hw) +{ + return (((Adc *)hw)->SEQSTATUS.reg & ADC_SEQSTATUS_SEQSTATE_Msk) >> ADC_SEQSTATUS_SEQSTATE_Pos; +} + +static inline hri_adc_seqstatus_reg_t hri_adc_get_SEQSTATUS_reg(const void *const hw, hri_adc_seqstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SEQSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_seqstatus_reg_t hri_adc_read_SEQSTATUS_reg(const void *const hw) +{ + return ((Adc *)hw)->SEQSTATUS.reg; +} + +static inline bool hri_adc_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SWRST) >> ADC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_ENABLE) >> ADC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_INPUTCTRL_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_INPUTCTRL) >> ADC_SYNCBUSY_INPUTCTRL_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_CTRLC_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_CTRLC) >> ADC_SYNCBUSY_CTRLC_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_AVGCTRL_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_AVGCTRL) >> ADC_SYNCBUSY_AVGCTRL_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_SAMPCTRL_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SAMPCTRL) >> ADC_SYNCBUSY_SAMPCTRL_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_WINLT_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_WINLT) >> ADC_SYNCBUSY_WINLT_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_WINUT_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_WINUT) >> ADC_SYNCBUSY_WINUT_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_GAINCORR_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_GAINCORR) >> ADC_SYNCBUSY_GAINCORR_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_OFFSETCORR_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_OFFSETCORR) >> ADC_SYNCBUSY_OFFSETCORR_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_SWTRIG_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SWTRIG) >> ADC_SYNCBUSY_SWTRIG_Pos; +} + +static inline hri_adc_syncbusy_reg_t hri_adc_get_SYNCBUSY_reg(const void *const hw, hri_adc_syncbusy_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_syncbusy_reg_t hri_adc_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Adc *)hw)->SYNCBUSY.reg; +} + +static inline hri_adc_result_reg_t hri_adc_get_RESULT_RESULT_bf(const void *const hw, hri_adc_result_reg_t mask) +{ + return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT(mask)) >> ADC_RESULT_RESULT_Pos; +} + +static inline hri_adc_result_reg_t hri_adc_read_RESULT_RESULT_bf(const void *const hw) +{ + return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT_Msk) >> ADC_RESULT_RESULT_Pos; +} + +static inline hri_adc_result_reg_t hri_adc_get_RESULT_reg(const void *const hw, hri_adc_result_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->RESULT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_result_reg_t hri_adc_read_RESULT_reg(const void *const hw) +{ + return ((Adc *)hw)->RESULT.reg; +} + +static inline void hri_adc_set_CTRLA_SWRST_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_SWRST; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_SWRST) >> ADC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_adc_set_CTRLA_ENABLE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ENABLE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_ENABLE) >> ADC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_ENABLE; + tmp |= value << ADC_CTRLA_ENABLE_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ENABLE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ENABLE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_RUNSTDBY; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_RUNSTDBY) >> ADC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_RUNSTDBY; + tmp |= value << ADC_CTRLA_RUNSTDBY_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_RUNSTDBY; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_RUNSTDBY; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_ONDEMAND_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ONDEMAND; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_ONDEMAND_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_ONDEMAND) >> ADC_CTRLA_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_ONDEMAND_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_ONDEMAND; + tmp |= value << ADC_CTRLA_ONDEMAND_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_ONDEMAND_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ONDEMAND; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_ONDEMAND_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ONDEMAND; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + return ((Adc *)hw)->CTRLA.reg; +} + +static inline void hri_adc_set_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_PRESCALER(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_PRESCALER(mask)) >> ADC_CTRLB_PRESCALER_Pos; + return tmp; +} + +static inline void hri_adc_write_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= ~ADC_CTRLB_PRESCALER_Msk; + tmp |= ADC_CTRLB_PRESCALER(data); + ((Adc *)hw)->CTRLB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_PRESCALER(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_PRESCALER(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_PRESCALER_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_PRESCALER_Msk) >> ADC_CTRLB_PRESCALER_Pos; + return tmp; +} + +static inline void hri_adc_set_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_reg(const void *const hw) +{ + return ((Adc *)hw)->CTRLB.reg; +} + +static inline void hri_adc_set_REFCTRL_REFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFCOMP; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_REFCTRL_REFCOMP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp = (tmp & ADC_REFCTRL_REFCOMP) >> ADC_REFCTRL_REFCOMP_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_REFCTRL_REFCOMP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp &= ~ADC_REFCTRL_REFCOMP; + tmp |= value << ADC_REFCTRL_REFCOMP_Pos; + ((Adc *)hw)->REFCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_REFCTRL_REFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFCOMP; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_REFCTRL_REFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFCOMP; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFSEL(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp = (tmp & ADC_REFCTRL_REFSEL(mask)) >> ADC_REFCTRL_REFSEL_Pos; + return tmp; +} + +static inline void hri_adc_write_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp &= ~ADC_REFCTRL_REFSEL_Msk; + tmp |= ADC_REFCTRL_REFSEL(data); + ((Adc *)hw)->REFCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFSEL(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFSEL(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_REFSEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp = (tmp & ADC_REFCTRL_REFSEL_Msk) >> ADC_REFCTRL_REFSEL_Pos; + return tmp; +} + +static inline void hri_adc_set_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_reg(const void *const hw) +{ + return ((Adc *)hw)->REFCTRL.reg; +} + +static inline void hri_adc_set_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_FLUSHEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_FLUSHEI) >> ADC_EVCTRL_FLUSHEI_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_FLUSHEI_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_FLUSHEI; + tmp |= value << ADC_EVCTRL_FLUSHEI_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_FLUSHEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_FLUSHEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_STARTEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_STARTEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_STARTEI_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_STARTEI) >> ADC_EVCTRL_STARTEI_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_STARTEI_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_STARTEI; + tmp |= value << ADC_EVCTRL_STARTEI_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_STARTEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_STARTEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_STARTEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_STARTEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_FLUSHINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_FLUSHINV) >> ADC_EVCTRL_FLUSHINV_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_FLUSHINV_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_FLUSHINV; + tmp |= value << ADC_EVCTRL_FLUSHINV_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_FLUSHINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_FLUSHINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_STARTINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_STARTINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_STARTINV_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_STARTINV) >> ADC_EVCTRL_STARTINV_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_STARTINV_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_STARTINV; + tmp |= value << ADC_EVCTRL_STARTINV_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_STARTINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_STARTINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_STARTINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_STARTINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_RESRDYEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_RESRDYEO) >> ADC_EVCTRL_RESRDYEO_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_RESRDYEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_RESRDYEO; + tmp |= value << ADC_EVCTRL_RESRDYEO_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_RESRDYEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_RESRDYEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_WINMONEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_WINMONEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_WINMONEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_WINMONEO) >> ADC_EVCTRL_WINMONEO_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_WINMONEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_WINMONEO; + tmp |= value << ADC_EVCTRL_WINMONEO_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_WINMONEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_WINMONEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_WINMONEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_WINMONEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_evctrl_reg_t hri_adc_get_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_evctrl_reg_t hri_adc_read_EVCTRL_reg(const void *const hw) +{ + return ((Adc *)hw)->EVCTRL.reg; +} + +static inline void hri_adc_set_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXPOS(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXPOS_bf(const void *const hw, + hri_adc_inputctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXPOS(mask)) >> ADC_INPUTCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_adc_write_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= ~ADC_INPUTCTRL_MUXPOS_Msk; + tmp |= ADC_INPUTCTRL_MUXPOS(data); + ((Adc *)hw)->INPUTCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXPOS(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXPOS(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXPOS_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXPOS_Msk) >> ADC_INPUTCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_adc_set_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXNEG(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXNEG_bf(const void *const hw, + hri_adc_inputctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXNEG(mask)) >> ADC_INPUTCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_adc_write_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= ~ADC_INPUTCTRL_MUXNEG_Msk; + tmp |= ADC_INPUTCTRL_MUXNEG(data); + ((Adc *)hw)->INPUTCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXNEG(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXNEG(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXNEG_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXNEG_Msk) >> ADC_INPUTCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_adc_set_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->INPUTCTRL.reg; +} + +static inline void hri_adc_set_CTRLC_DIFFMODE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_DIFFMODE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLC_DIFFMODE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_DIFFMODE) >> ADC_CTRLC_DIFFMODE_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLC_DIFFMODE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLC.reg; + tmp &= ~ADC_CTRLC_DIFFMODE; + tmp |= value << ADC_CTRLC_DIFFMODE_Pos; + ((Adc *)hw)->CTRLC.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLC_DIFFMODE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_DIFFMODE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLC_DIFFMODE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_DIFFMODE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLC_LEFTADJ_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_LEFTADJ; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLC_LEFTADJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_LEFTADJ) >> ADC_CTRLC_LEFTADJ_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLC_LEFTADJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLC.reg; + tmp &= ~ADC_CTRLC_LEFTADJ; + tmp |= value << ADC_CTRLC_LEFTADJ_Pos; + ((Adc *)hw)->CTRLC.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLC_LEFTADJ_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_LEFTADJ; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLC_LEFTADJ_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_LEFTADJ; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLC_FREERUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_FREERUN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLC_FREERUN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_FREERUN) >> ADC_CTRLC_FREERUN_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLC_FREERUN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLC.reg; + tmp &= ~ADC_CTRLC_FREERUN; + tmp |= value << ADC_CTRLC_FREERUN_Pos; + ((Adc *)hw)->CTRLC.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLC_FREERUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_FREERUN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLC_FREERUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_FREERUN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLC_CORREN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_CORREN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLC_CORREN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_CORREN) >> ADC_CTRLC_CORREN_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLC_CORREN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLC.reg; + tmp &= ~ADC_CTRLC_CORREN; + tmp |= value << ADC_CTRLC_CORREN_Pos; + ((Adc *)hw)->CTRLC.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLC_CORREN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_CORREN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLC_CORREN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_CORREN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLC_RESSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_RESSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlc_reg_t hri_adc_get_CTRLC_RESSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_RESSEL(mask)) >> ADC_CTRLC_RESSEL_Pos; + return tmp; +} + +static inline void hri_adc_write_CTRLC_RESSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLC.reg; + tmp &= ~ADC_CTRLC_RESSEL_Msk; + tmp |= ADC_CTRLC_RESSEL(data); + ((Adc *)hw)->CTRLC.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLC_RESSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_RESSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLC_RESSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_RESSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlc_reg_t hri_adc_read_CTRLC_RESSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_RESSEL_Msk) >> ADC_CTRLC_RESSEL_Pos; + return tmp; +} + +static inline void hri_adc_set_CTRLC_WINMODE_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_WINMODE(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlc_reg_t hri_adc_get_CTRLC_WINMODE_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_WINMODE(mask)) >> ADC_CTRLC_WINMODE_Pos; + return tmp; +} + +static inline void hri_adc_write_CTRLC_WINMODE_bf(const void *const hw, hri_adc_ctrlc_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLC.reg; + tmp &= ~ADC_CTRLC_WINMODE_Msk; + tmp |= ADC_CTRLC_WINMODE(data); + ((Adc *)hw)->CTRLC.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLC_WINMODE_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_WINMODE(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLC_WINMODE_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_WINMODE(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlc_reg_t hri_adc_read_CTRLC_WINMODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_WINMODE_Msk) >> ADC_CTRLC_WINMODE_Pos; + return tmp; +} + +static inline void hri_adc_set_CTRLC_reg(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlc_reg_t hri_adc_get_CTRLC_reg(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->CTRLC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_CTRLC_reg(const void *const hw, hri_adc_ctrlc_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLC_reg(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLC_reg(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlc_reg_t hri_adc_read_CTRLC_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->CTRLC.reg; +} + +static inline void hri_adc_set_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_SAMPLENUM(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_SAMPLENUM(mask)) >> ADC_AVGCTRL_SAMPLENUM_Pos; + return tmp; +} + +static inline void hri_adc_write_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp &= ~ADC_AVGCTRL_SAMPLENUM_Msk; + tmp |= ADC_AVGCTRL_SAMPLENUM(data); + ((Adc *)hw)->AVGCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_SAMPLENUM(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_SAMPLENUM(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_SAMPLENUM_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_SAMPLENUM_Msk) >> ADC_AVGCTRL_SAMPLENUM_Pos; + return tmp; +} + +static inline void hri_adc_set_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_ADJRES(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_ADJRES(mask)) >> ADC_AVGCTRL_ADJRES_Pos; + return tmp; +} + +static inline void hri_adc_write_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp &= ~ADC_AVGCTRL_ADJRES_Msk; + tmp |= ADC_AVGCTRL_ADJRES(data); + ((Adc *)hw)->AVGCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_ADJRES(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_ADJRES(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_ADJRES_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_ADJRES_Msk) >> ADC_AVGCTRL_ADJRES_Pos; + return tmp; +} + +static inline void hri_adc_set_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->AVGCTRL.reg; +} + +static inline void hri_adc_set_SAMPCTRL_OFFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg |= ADC_SAMPCTRL_OFFCOMP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_SAMPCTRL_OFFCOMP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp = (tmp & ADC_SAMPCTRL_OFFCOMP) >> ADC_SAMPCTRL_OFFCOMP_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_SAMPCTRL_OFFCOMP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp &= ~ADC_SAMPCTRL_OFFCOMP; + tmp |= value << ADC_SAMPCTRL_OFFCOMP_Pos; + ((Adc *)hw)->SAMPCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SAMPCTRL_OFFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg &= ~ADC_SAMPCTRL_OFFCOMP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SAMPCTRL_OFFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg ^= ADC_SAMPCTRL_OFFCOMP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg |= ADC_SAMPCTRL_SAMPLEN(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp = (tmp & ADC_SAMPCTRL_SAMPLEN(mask)) >> ADC_SAMPCTRL_SAMPLEN_Pos; + return tmp; +} + +static inline void hri_adc_write_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp &= ~ADC_SAMPCTRL_SAMPLEN_Msk; + tmp |= ADC_SAMPCTRL_SAMPLEN(data); + ((Adc *)hw)->SAMPCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg &= ~ADC_SAMPCTRL_SAMPLEN(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg ^= ADC_SAMPCTRL_SAMPLEN(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_SAMPLEN_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp = (tmp & ADC_SAMPCTRL_SAMPLEN_Msk) >> ADC_SAMPCTRL_SAMPLEN_Pos; + return tmp; +} + +static inline void hri_adc_set_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->SAMPCTRL.reg; +} + +static inline void hri_adc_set_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg |= ADC_WINLT_WINLT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + tmp = ((Adc *)hw)->WINLT.reg; + tmp = (tmp & ADC_WINLT_WINLT(mask)) >> ADC_WINLT_WINLT_Pos; + return tmp; +} + +static inline void hri_adc_write_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->WINLT.reg; + tmp &= ~ADC_WINLT_WINLT_Msk; + tmp |= ADC_WINLT_WINLT(data); + ((Adc *)hw)->WINLT.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg &= ~ADC_WINLT_WINLT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg ^= ADC_WINLT_WINLT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_WINLT_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + tmp = ((Adc *)hw)->WINLT.reg; + tmp = (tmp & ADC_WINLT_WINLT_Msk) >> ADC_WINLT_WINLT_Pos; + return tmp; +} + +static inline void hri_adc_set_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + tmp = ((Adc *)hw)->WINLT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + return ((Adc *)hw)->WINLT.reg; +} + +static inline void hri_adc_set_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg |= ADC_WINUT_WINUT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_get_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + tmp = ((Adc *)hw)->WINUT.reg; + tmp = (tmp & ADC_WINUT_WINUT(mask)) >> ADC_WINUT_WINUT_Pos; + return tmp; +} + +static inline void hri_adc_write_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->WINUT.reg; + tmp &= ~ADC_WINUT_WINUT_Msk; + tmp |= ADC_WINUT_WINUT(data); + ((Adc *)hw)->WINUT.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg &= ~ADC_WINUT_WINUT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg ^= ADC_WINUT_WINUT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_read_WINUT_WINUT_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + tmp = ((Adc *)hw)->WINUT.reg; + tmp = (tmp & ADC_WINUT_WINUT_Msk) >> ADC_WINUT_WINUT_Pos; + return tmp; +} + +static inline void hri_adc_set_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_get_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + tmp = ((Adc *)hw)->WINUT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_WINUT_reg(const void *const hw, hri_adc_winut_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_read_WINUT_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + return ((Adc *)hw)->WINUT.reg; +} + +static inline void hri_adc_set_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg |= ADC_GAINCORR_GAINCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp = (tmp & ADC_GAINCORR_GAINCORR(mask)) >> ADC_GAINCORR_GAINCORR_Pos; + return tmp; +} + +static inline void hri_adc_write_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp &= ~ADC_GAINCORR_GAINCORR_Msk; + tmp |= ADC_GAINCORR_GAINCORR(data); + ((Adc *)hw)->GAINCORR.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg &= ~ADC_GAINCORR_GAINCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg ^= ADC_GAINCORR_GAINCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_GAINCORR_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp = (tmp & ADC_GAINCORR_GAINCORR_Msk) >> ADC_GAINCORR_GAINCORR_Pos; + return tmp; +} + +static inline void hri_adc_set_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + return ((Adc *)hw)->GAINCORR.reg; +} + +static inline void hri_adc_set_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg |= ADC_OFFSETCORR_OFFSETCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_OFFSETCORR_bf(const void *const hw, + hri_adc_offsetcorr_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR(mask)) >> ADC_OFFSETCORR_OFFSETCORR_Pos; + return tmp; +} + +static inline void hri_adc_write_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp &= ~ADC_OFFSETCORR_OFFSETCORR_Msk; + tmp |= ADC_OFFSETCORR_OFFSETCORR(data); + ((Adc *)hw)->OFFSETCORR.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg &= ~ADC_OFFSETCORR_OFFSETCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg ^= ADC_OFFSETCORR_OFFSETCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_OFFSETCORR_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR_Msk) >> ADC_OFFSETCORR_OFFSETCORR_Pos; + return tmp; +} + +static inline void hri_adc_set_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + return ((Adc *)hw)->OFFSETCORR.reg; +} + +static inline void hri_adc_set_SWTRIG_FLUSH_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_FLUSH; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_SWTRIG_FLUSH_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp = (tmp & ADC_SWTRIG_FLUSH) >> ADC_SWTRIG_FLUSH_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_SWTRIG_FLUSH_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp &= ~ADC_SWTRIG_FLUSH; + tmp |= value << ADC_SWTRIG_FLUSH_Pos; + ((Adc *)hw)->SWTRIG.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SWTRIG_FLUSH_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_FLUSH; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SWTRIG_FLUSH_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_FLUSH; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_SWTRIG_START_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_START; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_SWTRIG_START_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp = (tmp & ADC_SWTRIG_START) >> ADC_SWTRIG_START_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_SWTRIG_START_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp &= ~ADC_SWTRIG_START; + tmp |= value << ADC_SWTRIG_START_Pos; + ((Adc *)hw)->SWTRIG.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SWTRIG_START_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_START; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SWTRIG_START_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_START; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_swtrig_reg_t hri_adc_get_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_swtrig_reg_t hri_adc_read_SWTRIG_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->SWTRIG.reg; +} + +static inline void hri_adc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg |= ADC_DBGCTRL_DBGRUN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->DBGCTRL.reg; + tmp = (tmp & ADC_DBGCTRL_DBGRUN) >> ADC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DBGCTRL.reg; + tmp &= ~ADC_DBGCTRL_DBGRUN; + tmp |= value << ADC_DBGCTRL_DBGRUN_Pos; + ((Adc *)hw)->DBGCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg &= ~ADC_DBGCTRL_DBGRUN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg ^= ADC_DBGCTRL_DBGRUN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_dbgctrl_reg_t hri_adc_get_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_dbgctrl_reg_t hri_adc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Adc *)hw)->DBGCTRL.reg; +} + +static inline void hri_adc_set_SEQCTRL_SEQEN_bf(const void *const hw, hri_adc_seqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SEQCTRL.reg |= ADC_SEQCTRL_SEQEN(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_seqctrl_reg_t hri_adc_get_SEQCTRL_SEQEN_bf(const void *const hw, hri_adc_seqctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Adc *)hw)->SEQCTRL.reg; + tmp = (tmp & ADC_SEQCTRL_SEQEN(mask)) >> ADC_SEQCTRL_SEQEN_Pos; + return tmp; +} + +static inline void hri_adc_write_SEQCTRL_SEQEN_bf(const void *const hw, hri_adc_seqctrl_reg_t data) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->SEQCTRL.reg; + tmp &= ~ADC_SEQCTRL_SEQEN_Msk; + tmp |= ADC_SEQCTRL_SEQEN(data); + ((Adc *)hw)->SEQCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SEQCTRL_SEQEN_bf(const void *const hw, hri_adc_seqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SEQCTRL.reg &= ~ADC_SEQCTRL_SEQEN(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SEQCTRL_SEQEN_bf(const void *const hw, hri_adc_seqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SEQCTRL.reg ^= ADC_SEQCTRL_SEQEN(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_seqctrl_reg_t hri_adc_read_SEQCTRL_SEQEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Adc *)hw)->SEQCTRL.reg; + tmp = (tmp & ADC_SEQCTRL_SEQEN_Msk) >> ADC_SEQCTRL_SEQEN_Pos; + return tmp; +} + +static inline void hri_adc_set_SEQCTRL_reg(const void *const hw, hri_adc_seqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SEQCTRL.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_seqctrl_reg_t hri_adc_get_SEQCTRL_reg(const void *const hw, hri_adc_seqctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Adc *)hw)->SEQCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_SEQCTRL_reg(const void *const hw, hri_adc_seqctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SEQCTRL.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SEQCTRL_reg(const void *const hw, hri_adc_seqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SEQCTRL.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SEQCTRL_reg(const void *const hw, hri_adc_seqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SEQCTRL.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_seqctrl_reg_t hri_adc_read_SEQCTRL_reg(const void *const hw) +{ + return ((Adc *)hw)->SEQCTRL.reg; +} + +static inline void hri_adc_set_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASCOMP(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASCOMP(mask)) >> ADC_CALIB_BIASCOMP_Pos; + return tmp; +} + +static inline void hri_adc_write_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CALIB.reg; + tmp &= ~ADC_CALIB_BIASCOMP_Msk; + tmp |= ADC_CALIB_BIASCOMP(data); + ((Adc *)hw)->CALIB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASCOMP(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASCOMP(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASCOMP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASCOMP_Msk) >> ADC_CALIB_BIASCOMP_Pos; + return tmp; +} + +static inline void hri_adc_set_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASREFBUF(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASREFBUF(mask)) >> ADC_CALIB_BIASREFBUF_Pos; + return tmp; +} + +static inline void hri_adc_write_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CALIB.reg; + tmp &= ~ADC_CALIB_BIASREFBUF_Msk; + tmp |= ADC_CALIB_BIASREFBUF(data); + ((Adc *)hw)->CALIB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASREFBUF(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASREFBUF(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASREFBUF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASREFBUF_Msk) >> ADC_CALIB_BIASREFBUF_Pos; + return tmp; +} + +static inline void hri_adc_set_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_get_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_CALIB_reg(const void *const hw, hri_adc_calib_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_read_CALIB_reg(const void *const hw) +{ + return ((Adc *)hw)->CALIB.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_ADC_L21_H_INCLUDED */ +#endif /* _SAML21_ADC_COMPONENT_ */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_aes_l21.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_aes_l21.h new file mode 100644 index 00000000..abb9e333 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_aes_l21.h @@ -0,0 +1,1213 @@ +/** + * \file + * + * \brief SAM AES + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_AES_COMPONENT_ +#ifndef _HRI_AES_L21_H_INCLUDED_ +#define _HRI_AES_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_AES_CRITICAL_SECTIONS) +#define AES_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define AES_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define AES_CRITICAL_SECTION_ENTER() +#define AES_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_aes_ciplen_reg_t; +typedef uint32_t hri_aes_ctrla_reg_t; +typedef uint32_t hri_aes_ghash_reg_t; +typedef uint32_t hri_aes_hashkey_reg_t; +typedef uint32_t hri_aes_indata_reg_t; +typedef uint32_t hri_aes_intvectv_reg_t; +typedef uint32_t hri_aes_keyword_reg_t; +typedef uint32_t hri_aes_randseed_reg_t; +typedef uint8_t hri_aes_ctrlb_reg_t; +typedef uint8_t hri_aes_databufptr_reg_t; +typedef uint8_t hri_aes_dbgctrl_reg_t; +typedef uint8_t hri_aes_intenset_reg_t; +typedef uint8_t hri_aes_intflag_reg_t; + +static inline bool hri_aes_get_INTFLAG_ENCCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_ENCCMP) >> AES_INTFLAG_ENCCMP_Pos; +} + +static inline void hri_aes_clear_INTFLAG_ENCCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_ENCCMP; +} + +static inline bool hri_aes_get_INTFLAG_GFMCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_GFMCMP) >> AES_INTFLAG_GFMCMP_Pos; +} + +static inline void hri_aes_clear_INTFLAG_GFMCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_GFMCMP; +} + +static inline bool hri_aes_get_interrupt_ENCCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_ENCCMP) >> AES_INTFLAG_ENCCMP_Pos; +} + +static inline void hri_aes_clear_interrupt_ENCCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_ENCCMP; +} + +static inline bool hri_aes_get_interrupt_GFMCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_GFMCMP) >> AES_INTFLAG_GFMCMP_Pos; +} + +static inline void hri_aes_clear_interrupt_GFMCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_GFMCMP; +} + +static inline hri_aes_intflag_reg_t hri_aes_get_INTFLAG_reg(const void *const hw, hri_aes_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_aes_intflag_reg_t hri_aes_read_INTFLAG_reg(const void *const hw) +{ + return ((Aes *)hw)->INTFLAG.reg; +} + +static inline void hri_aes_clear_INTFLAG_reg(const void *const hw, hri_aes_intflag_reg_t mask) +{ + ((Aes *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_aes_set_INTEN_ENCCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTENSET.reg = AES_INTENSET_ENCCMP; +} + +static inline bool hri_aes_get_INTEN_ENCCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTENSET.reg & AES_INTENSET_ENCCMP) >> AES_INTENSET_ENCCMP_Pos; +} + +static inline void hri_aes_write_INTEN_ENCCMP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_ENCCMP; + } else { + ((Aes *)hw)->INTENSET.reg = AES_INTENSET_ENCCMP; + } +} + +static inline void hri_aes_clear_INTEN_ENCCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_ENCCMP; +} + +static inline void hri_aes_set_INTEN_GFMCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTENSET.reg = AES_INTENSET_GFMCMP; +} + +static inline bool hri_aes_get_INTEN_GFMCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTENSET.reg & AES_INTENSET_GFMCMP) >> AES_INTENSET_GFMCMP_Pos; +} + +static inline void hri_aes_write_INTEN_GFMCMP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_GFMCMP; + } else { + ((Aes *)hw)->INTENSET.reg = AES_INTENSET_GFMCMP; + } +} + +static inline void hri_aes_clear_INTEN_GFMCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_GFMCMP; +} + +static inline void hri_aes_set_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask) +{ + ((Aes *)hw)->INTENSET.reg = mask; +} + +static inline hri_aes_intenset_reg_t hri_aes_get_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_aes_intenset_reg_t hri_aes_read_INTEN_reg(const void *const hw) +{ + return ((Aes *)hw)->INTENSET.reg; +} + +static inline void hri_aes_write_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t data) +{ + ((Aes *)hw)->INTENSET.reg = data; + ((Aes *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_aes_clear_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask) +{ + ((Aes *)hw)->INTENCLR.reg = mask; +} + +static inline void hri_aes_set_CTRLA_SWRST_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_SWRST; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_SWRST) >> AES_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_aes_set_CTRLA_ENABLE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_ENABLE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_ENABLE) >> AES_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_ENABLE; + tmp |= value << AES_CTRLA_ENABLE_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_ENABLE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_ENABLE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_CIPHER_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CIPHER; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_CIPHER_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_CIPHER) >> AES_CTRLA_CIPHER_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_CIPHER_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_CIPHER; + tmp |= value << AES_CTRLA_CIPHER_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_CIPHER_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CIPHER; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_CIPHER_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CIPHER; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_STARTMODE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_STARTMODE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_STARTMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_STARTMODE) >> AES_CTRLA_STARTMODE_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_STARTMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_STARTMODE; + tmp |= value << AES_CTRLA_STARTMODE_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_STARTMODE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_STARTMODE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_STARTMODE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_STARTMODE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_LOD_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_LOD; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_LOD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_LOD) >> AES_CTRLA_LOD_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_LOD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_LOD; + tmp |= value << AES_CTRLA_LOD_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_LOD_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_LOD; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_LOD_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_LOD; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_KEYGEN_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_KEYGEN; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_KEYGEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_KEYGEN) >> AES_CTRLA_KEYGEN_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_KEYGEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_KEYGEN; + tmp |= value << AES_CTRLA_KEYGEN_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_KEYGEN_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_KEYGEN; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_KEYGEN_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_KEYGEN; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_XORKEY_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_XORKEY; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_XORKEY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_XORKEY) >> AES_CTRLA_XORKEY_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_XORKEY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_XORKEY; + tmp |= value << AES_CTRLA_XORKEY_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_XORKEY_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_XORKEY; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_XORKEY_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_XORKEY; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_AESMODE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_AESMODE(mask)) >> AES_CTRLA_AESMODE_Pos; + return tmp; +} + +static inline void hri_aes_write_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t data) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_AESMODE_Msk; + tmp |= AES_CTRLA_AESMODE(data); + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_AESMODE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_AESMODE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_AESMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_AESMODE_Msk) >> AES_CTRLA_AESMODE_Pos; + return tmp; +} + +static inline void hri_aes_set_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CFBS(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_CFBS(mask)) >> AES_CTRLA_CFBS_Pos; + return tmp; +} + +static inline void hri_aes_write_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t data) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_CFBS_Msk; + tmp |= AES_CTRLA_CFBS(data); + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CFBS(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CFBS(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_CFBS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_CFBS_Msk) >> AES_CTRLA_CFBS_Pos; + return tmp; +} + +static inline void hri_aes_set_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_KEYSIZE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_KEYSIZE(mask)) >> AES_CTRLA_KEYSIZE_Pos; + return tmp; +} + +static inline void hri_aes_write_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t data) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_KEYSIZE_Msk; + tmp |= AES_CTRLA_KEYSIZE(data); + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_KEYSIZE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_KEYSIZE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_KEYSIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_KEYSIZE_Msk) >> AES_CTRLA_KEYSIZE_Pos; + return tmp; +} + +static inline void hri_aes_set_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CTYPE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_CTYPE(mask)) >> AES_CTRLA_CTYPE_Pos; + return tmp; +} + +static inline void hri_aes_write_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t data) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_CTYPE_Msk; + tmp |= AES_CTRLA_CTYPE(data); + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CTYPE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CTYPE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_CTYPE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_CTYPE_Msk) >> AES_CTRLA_CTYPE_Pos; + return tmp; +} + +static inline void hri_aes_set_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_reg(const void *const hw) +{ + return ((Aes *)hw)->CTRLA.reg; +} + +static inline void hri_aes_set_CTRLB_START_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_START; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLB_START_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->CTRLB.reg; + tmp = (tmp & AES_CTRLB_START) >> AES_CTRLB_START_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLB_START_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLB.reg; + tmp &= ~AES_CTRLB_START; + tmp |= value << AES_CTRLB_START_Pos; + ((Aes *)hw)->CTRLB.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLB_START_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_START; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLB_START_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_START; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLB_NEWMSG_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_NEWMSG; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLB_NEWMSG_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->CTRLB.reg; + tmp = (tmp & AES_CTRLB_NEWMSG) >> AES_CTRLB_NEWMSG_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLB_NEWMSG_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLB.reg; + tmp &= ~AES_CTRLB_NEWMSG; + tmp |= value << AES_CTRLB_NEWMSG_Pos; + ((Aes *)hw)->CTRLB.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLB_NEWMSG_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_NEWMSG; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLB_NEWMSG_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_NEWMSG; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLB_EOM_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_EOM; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLB_EOM_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->CTRLB.reg; + tmp = (tmp & AES_CTRLB_EOM) >> AES_CTRLB_EOM_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLB_EOM_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLB.reg; + tmp &= ~AES_CTRLB_EOM; + tmp |= value << AES_CTRLB_EOM_Pos; + ((Aes *)hw)->CTRLB.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLB_EOM_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_EOM; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLB_EOM_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_EOM; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLB_GFMUL_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_GFMUL; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLB_GFMUL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->CTRLB.reg; + tmp = (tmp & AES_CTRLB_GFMUL) >> AES_CTRLB_GFMUL_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLB_GFMUL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLB.reg; + tmp &= ~AES_CTRLB_GFMUL; + tmp |= value << AES_CTRLB_GFMUL_Pos; + ((Aes *)hw)->CTRLB.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLB_GFMUL_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_GFMUL; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLB_GFMUL_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_GFMUL; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrlb_reg_t hri_aes_get_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrlb_reg_t hri_aes_read_CTRLB_reg(const void *const hw) +{ + return ((Aes *)hw)->CTRLB.reg; +} + +static inline void hri_aes_set_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg |= AES_DATABUFPTR_INDATAPTR(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_databufptr_reg_t hri_aes_get_DATABUFPTR_INDATAPTR_bf(const void *const hw, + hri_aes_databufptr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->DATABUFPTR.reg; + tmp = (tmp & AES_DATABUFPTR_INDATAPTR(mask)) >> AES_DATABUFPTR_INDATAPTR_Pos; + return tmp; +} + +static inline void hri_aes_write_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t data) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->DATABUFPTR.reg; + tmp &= ~AES_DATABUFPTR_INDATAPTR_Msk; + tmp |= AES_DATABUFPTR_INDATAPTR(data); + ((Aes *)hw)->DATABUFPTR.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg &= ~AES_DATABUFPTR_INDATAPTR(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg ^= AES_DATABUFPTR_INDATAPTR(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_databufptr_reg_t hri_aes_read_DATABUFPTR_INDATAPTR_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->DATABUFPTR.reg; + tmp = (tmp & AES_DATABUFPTR_INDATAPTR_Msk) >> AES_DATABUFPTR_INDATAPTR_Pos; + return tmp; +} + +static inline void hri_aes_set_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_databufptr_reg_t hri_aes_get_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->DATABUFPTR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_databufptr_reg_t hri_aes_read_DATABUFPTR_reg(const void *const hw) +{ + return ((Aes *)hw)->DATABUFPTR.reg; +} + +static inline void hri_aes_set_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->INDATA.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_indata_reg_t hri_aes_get_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->INDATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_INDATA_reg(const void *const hw, hri_aes_indata_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->INDATA.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->INDATA.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->INDATA.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_indata_reg_t hri_aes_read_INDATA_reg(const void *const hw) +{ + return ((Aes *)hw)->INDATA.reg; +} + +static inline void hri_aes_set_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->HASHKEY[index].reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_hashkey_reg_t hri_aes_get_HASHKEY_reg(const void *const hw, uint8_t index, + hri_aes_hashkey_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->HASHKEY[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->HASHKEY[index].reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->HASHKEY[index].reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->HASHKEY[index].reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_hashkey_reg_t hri_aes_read_HASHKEY_reg(const void *const hw, uint8_t index) +{ + return ((Aes *)hw)->HASHKEY[index].reg; +} + +static inline void hri_aes_set_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->GHASH[index].reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ghash_reg_t hri_aes_get_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->GHASH[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->GHASH[index].reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->GHASH[index].reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->GHASH[index].reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ghash_reg_t hri_aes_read_GHASH_reg(const void *const hw, uint8_t index) +{ + return ((Aes *)hw)->GHASH[index].reg; +} + +static inline void hri_aes_set_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CIPLEN.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ciplen_reg_t hri_aes_get_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CIPLEN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CIPLEN.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CIPLEN.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CIPLEN.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ciplen_reg_t hri_aes_read_CIPLEN_reg(const void *const hw) +{ + return ((Aes *)hw)->CIPLEN.reg; +} + +static inline void hri_aes_set_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->RANDSEED.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_randseed_reg_t hri_aes_get_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->RANDSEED.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->RANDSEED.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->RANDSEED.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->RANDSEED.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_randseed_reg_t hri_aes_read_RANDSEED_reg(const void *const hw) +{ + return ((Aes *)hw)->RANDSEED.reg; +} + +static inline void hri_aes_write_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DBGCTRL.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_write_KEYWORD_reg(const void *const hw, uint8_t index, hri_aes_keyword_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->KEYWORD[index].reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_write_INTVECTV_reg(const void *const hw, uint8_t index, hri_aes_intvectv_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->INTVECTV[index].reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_AES_L21_H_INCLUDED */ +#endif /* _SAML21_AES_COMPONENT_ */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_ccl_l21.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_ccl_l21.h new file mode 100644 index 00000000..e88acd39 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_ccl_l21.h @@ -0,0 +1,776 @@ +/** + * \file + * + * \brief SAM CCL + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_CCL_COMPONENT_ +#ifndef _HRI_CCL_L21_H_INCLUDED_ +#define _HRI_CCL_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_CCL_CRITICAL_SECTIONS) +#define CCL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define CCL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define CCL_CRITICAL_SECTION_ENTER() +#define CCL_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_ccl_lutctrl_reg_t; +typedef uint8_t hri_ccl_ctrl_reg_t; +typedef uint8_t hri_ccl_seqctrl_reg_t; + +static inline void hri_ccl_set_CTRL_SWRST_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_SWRST; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_CTRL_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->CTRL.reg; + tmp = (tmp & CCL_CTRL_SWRST) >> CCL_CTRL_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_set_CTRL_ENABLE_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_CTRL_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->CTRL.reg; + tmp = (tmp & CCL_CTRL_ENABLE) >> CCL_CTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_CTRL_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->CTRL.reg; + tmp &= ~CCL_CTRL_ENABLE; + tmp |= value << CCL_CTRL_ENABLE_Pos; + ((Ccl *)hw)->CTRL.reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_CTRL_ENABLE_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg &= ~CCL_CTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_CTRL_ENABLE_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg ^= CCL_CTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_CTRL_RUNSTDBY_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_RUNSTDBY; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_CTRL_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->CTRL.reg; + tmp = (tmp & CCL_CTRL_RUNSTDBY) >> CCL_CTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_CTRL_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->CTRL.reg; + tmp &= ~CCL_CTRL_RUNSTDBY; + tmp |= value << CCL_CTRL_RUNSTDBY_Pos; + ((Ccl *)hw)->CTRL.reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_CTRL_RUNSTDBY_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg &= ~CCL_CTRL_RUNSTDBY; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_CTRL_RUNSTDBY_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg ^= CCL_CTRL_RUNSTDBY; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg |= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_ctrl_reg_t hri_ccl_get_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ccl_write_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t data) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg = data; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg &= ~mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg ^= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_ctrl_reg_t hri_ccl_read_CTRL_reg(const void *const hw) +{ + return ((Ccl *)hw)->CTRL.reg; +} + +static inline void hri_ccl_set_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg |= CCL_SEQCTRL_SEQSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_seqctrl_reg_t hri_ccl_get_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, + hri_ccl_seqctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->SEQCTRL[index].reg; + tmp = (tmp & CCL_SEQCTRL_SEQSEL(mask)) >> CCL_SEQCTRL_SEQSEL_Pos; + return tmp; +} + +static inline void hri_ccl_write_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t data) +{ + uint8_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->SEQCTRL[index].reg; + tmp &= ~CCL_SEQCTRL_SEQSEL_Msk; + tmp |= CCL_SEQCTRL_SEQSEL(data); + ((Ccl *)hw)->SEQCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg &= ~CCL_SEQCTRL_SEQSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg ^= CCL_SEQCTRL_SEQSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_seqctrl_reg_t hri_ccl_read_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->SEQCTRL[index].reg; + tmp = (tmp & CCL_SEQCTRL_SEQSEL_Msk) >> CCL_SEQCTRL_SEQSEL_Pos; + return tmp; +} + +static inline void hri_ccl_set_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg |= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_seqctrl_reg_t hri_ccl_get_SEQCTRL_reg(const void *const hw, uint8_t index, + hri_ccl_seqctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->SEQCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ccl_write_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t data) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg = data; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg &= ~mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg ^= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_seqctrl_reg_t hri_ccl_read_SEQCTRL_reg(const void *const hw, uint8_t index) +{ + return ((Ccl *)hw)->SEQCTRL[index].reg; +} + +static inline void hri_ccl_set_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_ENABLE) >> CCL_LUTCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_ENABLE; + tmp |= value << CCL_LUTCTRL_ENABLE_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_EDGESEL; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_EDGESEL) >> CCL_LUTCTRL_EDGESEL_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_EDGESEL; + tmp |= value << CCL_LUTCTRL_EDGESEL_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_EDGESEL; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_EDGESEL; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INVEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INVEI) >> CCL_LUTCTRL_INVEI_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_INVEI; + tmp |= value << CCL_LUTCTRL_INVEI_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INVEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INVEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_LUTEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_LUTEI) >> CCL_LUTCTRL_LUTEI_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_LUTEI; + tmp |= value << CCL_LUTCTRL_LUTEI_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_LUTEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_LUTEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_LUTEO; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_LUTEO) >> CCL_LUTCTRL_LUTEO_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_LUTEO; + tmp |= value << CCL_LUTCTRL_LUTEO_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_LUTEO; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_LUTEO; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_FILTSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_FILTSEL(mask)) >> CCL_LUTCTRL_FILTSEL_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_FILTSEL_Msk; + tmp |= CCL_LUTCTRL_FILTSEL(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_FILTSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_FILTSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_FILTSEL_Msk) >> CCL_LUTCTRL_FILTSEL_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL0(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL0(mask)) >> CCL_LUTCTRL_INSEL0_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_INSEL0_Msk; + tmp |= CCL_LUTCTRL_INSEL0(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL0(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL0(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL0_Msk) >> CCL_LUTCTRL_INSEL0_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL1(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL1(mask)) >> CCL_LUTCTRL_INSEL1_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_INSEL1_Msk; + tmp |= CCL_LUTCTRL_INSEL1(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL1(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL1(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL1_Msk) >> CCL_LUTCTRL_INSEL1_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL2(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL2(mask)) >> CCL_LUTCTRL_INSEL2_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_INSEL2_Msk; + tmp |= CCL_LUTCTRL_INSEL2(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL2(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL2(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL2_Msk) >> CCL_LUTCTRL_INSEL2_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_TRUTH(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_TRUTH(mask)) >> CCL_LUTCTRL_TRUTH_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_TRUTH_Msk; + tmp |= CCL_LUTCTRL_TRUTH(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_TRUTH(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_TRUTH(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_TRUTH_Msk) >> CCL_LUTCTRL_TRUTH_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_reg(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg = data; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_reg(const void *const hw, uint8_t index) +{ + return ((Ccl *)hw)->LUTCTRL[index].reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_CCL_L21_H_INCLUDED */ +#endif /* _SAML21_CCL_COMPONENT_ */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_dac_l21.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_dac_l21.h new file mode 100644 index 00000000..328973df --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_dac_l21.h @@ -0,0 +1,1327 @@ +/** + * \file + * + * \brief SAM DAC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_DAC_COMPONENT_ +#ifndef _HRI_DAC_L21_H_INCLUDED_ +#define _HRI_DAC_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_DAC_CRITICAL_SECTIONS) +#define DAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define DAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define DAC_CRITICAL_SECTION_ENTER() +#define DAC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_dac_dacctrl_reg_t; +typedef uint16_t hri_dac_data_reg_t; +typedef uint16_t hri_dac_databuf_reg_t; +typedef uint32_t hri_dac_syncbusy_reg_t; +typedef uint8_t hri_dac_ctrla_reg_t; +typedef uint8_t hri_dac_ctrlb_reg_t; +typedef uint8_t hri_dac_dbgctrl_reg_t; +typedef uint8_t hri_dac_evctrl_reg_t; +typedef uint8_t hri_dac_intenset_reg_t; +typedef uint8_t hri_dac_intflag_reg_t; +typedef uint8_t hri_dac_status_reg_t; + +static inline void hri_dac_wait_for_sync(const void *const hw, hri_dac_syncbusy_reg_t reg) +{ + while (((Dac *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_dac_is_syncing(const void *const hw, hri_dac_syncbusy_reg_t reg) +{ + return ((Dac *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_dac_get_INTFLAG_UNDERRUN0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN0) >> DAC_INTFLAG_UNDERRUN0_Pos; +} + +static inline void hri_dac_clear_INTFLAG_UNDERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN0; +} + +static inline bool hri_dac_get_INTFLAG_UNDERRUN1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN1) >> DAC_INTFLAG_UNDERRUN1_Pos; +} + +static inline void hri_dac_clear_INTFLAG_UNDERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN1; +} + +static inline bool hri_dac_get_INTFLAG_EMPTY0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY0) >> DAC_INTFLAG_EMPTY0_Pos; +} + +static inline void hri_dac_clear_INTFLAG_EMPTY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY0; +} + +static inline bool hri_dac_get_INTFLAG_EMPTY1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY1) >> DAC_INTFLAG_EMPTY1_Pos; +} + +static inline void hri_dac_clear_INTFLAG_EMPTY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY1; +} + +static inline bool hri_dac_get_interrupt_UNDERRUN0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN0) >> DAC_INTFLAG_UNDERRUN0_Pos; +} + +static inline void hri_dac_clear_interrupt_UNDERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN0; +} + +static inline bool hri_dac_get_interrupt_UNDERRUN1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN1) >> DAC_INTFLAG_UNDERRUN1_Pos; +} + +static inline void hri_dac_clear_interrupt_UNDERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN1; +} + +static inline bool hri_dac_get_interrupt_EMPTY0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY0) >> DAC_INTFLAG_EMPTY0_Pos; +} + +static inline void hri_dac_clear_interrupt_EMPTY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY0; +} + +static inline bool hri_dac_get_interrupt_EMPTY1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY1) >> DAC_INTFLAG_EMPTY1_Pos; +} + +static inline void hri_dac_clear_interrupt_EMPTY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY1; +} + +static inline hri_dac_intflag_reg_t hri_dac_get_INTFLAG_reg(const void *const hw, hri_dac_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_intflag_reg_t hri_dac_read_INTFLAG_reg(const void *const hw) +{ + return ((Dac *)hw)->INTFLAG.reg; +} + +static inline void hri_dac_clear_INTFLAG_reg(const void *const hw, hri_dac_intflag_reg_t mask) +{ + ((Dac *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_dac_set_INTEN_UNDERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN0; +} + +static inline bool hri_dac_get_INTEN_UNDERRUN0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_UNDERRUN0) >> DAC_INTENSET_UNDERRUN0_Pos; +} + +static inline void hri_dac_write_INTEN_UNDERRUN0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN0; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN0; + } +} + +static inline void hri_dac_clear_INTEN_UNDERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN0; +} + +static inline void hri_dac_set_INTEN_UNDERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN1; +} + +static inline bool hri_dac_get_INTEN_UNDERRUN1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_UNDERRUN1) >> DAC_INTENSET_UNDERRUN1_Pos; +} + +static inline void hri_dac_write_INTEN_UNDERRUN1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN1; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN1; + } +} + +static inline void hri_dac_clear_INTEN_UNDERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN1; +} + +static inline void hri_dac_set_INTEN_EMPTY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY0; +} + +static inline bool hri_dac_get_INTEN_EMPTY0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_EMPTY0) >> DAC_INTENSET_EMPTY0_Pos; +} + +static inline void hri_dac_write_INTEN_EMPTY0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY0; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY0; + } +} + +static inline void hri_dac_clear_INTEN_EMPTY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY0; +} + +static inline void hri_dac_set_INTEN_EMPTY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY1; +} + +static inline bool hri_dac_get_INTEN_EMPTY1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_EMPTY1) >> DAC_INTENSET_EMPTY1_Pos; +} + +static inline void hri_dac_write_INTEN_EMPTY1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY1; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY1; + } +} + +static inline void hri_dac_clear_INTEN_EMPTY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY1; +} + +static inline void hri_dac_set_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) +{ + ((Dac *)hw)->INTENSET.reg = mask; +} + +static inline hri_dac_intenset_reg_t hri_dac_get_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_intenset_reg_t hri_dac_read_INTEN_reg(const void *const hw) +{ + return ((Dac *)hw)->INTENSET.reg; +} + +static inline void hri_dac_write_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t data) +{ + ((Dac *)hw)->INTENSET.reg = data; + ((Dac *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_dac_clear_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) +{ + ((Dac *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_dac_get_STATUS_READY0_bit(const void *const hw) +{ + return (((Dac *)hw)->STATUS.reg & DAC_STATUS_READY0) >> DAC_STATUS_READY0_Pos; +} + +static inline bool hri_dac_get_STATUS_READY1_bit(const void *const hw) +{ + return (((Dac *)hw)->STATUS.reg & DAC_STATUS_READY1) >> DAC_STATUS_READY1_Pos; +} + +static inline bool hri_dac_get_STATUS_EOC0_bit(const void *const hw) +{ + return (((Dac *)hw)->STATUS.reg & DAC_STATUS_EOC0) >> DAC_STATUS_EOC0_Pos; +} + +static inline bool hri_dac_get_STATUS_EOC1_bit(const void *const hw) +{ + return (((Dac *)hw)->STATUS.reg & DAC_STATUS_EOC1) >> DAC_STATUS_EOC1_Pos; +} + +static inline hri_dac_status_reg_t hri_dac_get_STATUS_reg(const void *const hw, hri_dac_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_status_reg_t hri_dac_read_STATUS_reg(const void *const hw) +{ + return ((Dac *)hw)->STATUS.reg; +} + +static inline bool hri_dac_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_SWRST) >> DAC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_dac_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_ENABLE) >> DAC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_dac_get_SYNCBUSY_DATA0_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATA0) >> DAC_SYNCBUSY_DATA0_Pos; +} + +static inline bool hri_dac_get_SYNCBUSY_DATA1_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATA1) >> DAC_SYNCBUSY_DATA1_Pos; +} + +static inline bool hri_dac_get_SYNCBUSY_DATABUF0_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATABUF0) >> DAC_SYNCBUSY_DATABUF0_Pos; +} + +static inline bool hri_dac_get_SYNCBUSY_DATABUF1_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATABUF1) >> DAC_SYNCBUSY_DATABUF1_Pos; +} + +static inline hri_dac_syncbusy_reg_t hri_dac_get_SYNCBUSY_reg(const void *const hw, hri_dac_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dac *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_syncbusy_reg_t hri_dac_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Dac *)hw)->SYNCBUSY.reg; +} + +static inline void hri_dac_set_CTRLA_SWRST_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_SWRST; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST); + tmp = ((Dac *)hw)->CTRLA.reg; + tmp = (tmp & DAC_CTRLA_SWRST) >> DAC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_dac_set_CTRLA_ENABLE_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_ENABLE; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + tmp = ((Dac *)hw)->CTRLA.reg; + tmp = (tmp & DAC_CTRLA_ENABLE) >> DAC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->CTRLA.reg; + tmp &= ~DAC_CTRLA_ENABLE; + tmp |= value << DAC_CTRLA_ENABLE_Pos; + ((Dac *)hw)->CTRLA.reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg &= ~DAC_CTRLA_ENABLE; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg ^= DAC_CTRLA_ENABLE; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg |= mask; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrla_reg_t hri_dac_get_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + tmp = ((Dac *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg = data; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg &= ~mask; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg ^= mask; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrla_reg_t hri_dac_read_CTRLA_reg(const void *const hw) +{ + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + return ((Dac *)hw)->CTRLA.reg; +} + +static inline void hri_dac_set_CTRLB_DIFF_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_DIFF; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLB_DIFF_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp = (tmp & DAC_CTRLB_DIFF) >> DAC_CTRLB_DIFF_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_CTRLB_DIFF_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->CTRLB.reg; + tmp &= ~DAC_CTRLB_DIFF; + tmp |= value << DAC_CTRLB_DIFF_Pos; + ((Dac *)hw)->CTRLB.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLB_DIFF_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_DIFF; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLB_DIFF_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_DIFF; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_REFSEL(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrlb_reg_t hri_dac_get_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp = (tmp & DAC_CTRLB_REFSEL(mask)) >> DAC_CTRLB_REFSEL_Pos; + return tmp; +} + +static inline void hri_dac_write_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t data) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->CTRLB.reg; + tmp &= ~DAC_CTRLB_REFSEL_Msk; + tmp |= DAC_CTRLB_REFSEL(data); + ((Dac *)hw)->CTRLB.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_REFSEL(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_REFSEL(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrlb_reg_t hri_dac_read_CTRLB_REFSEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp = (tmp & DAC_CTRLB_REFSEL_Msk) >> DAC_CTRLB_REFSEL_Pos; + return tmp; +} + +static inline void hri_dac_set_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg |= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrlb_reg_t hri_dac_get_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg = data; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg &= ~mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg ^= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrlb_reg_t hri_dac_read_CTRLB_reg(const void *const hw) +{ + return ((Dac *)hw)->CTRLB.reg; +} + +static inline void hri_dac_set_EVCTRL_STARTEI0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_STARTEI0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_STARTEI0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_STARTEI0) >> DAC_EVCTRL_STARTEI0_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_STARTEI0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_STARTEI0; + tmp |= value << DAC_EVCTRL_STARTEI0_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_STARTEI0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_STARTEI0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_STARTEI0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_STARTEI0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_STARTEI1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_STARTEI1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_STARTEI1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_STARTEI1) >> DAC_EVCTRL_STARTEI1_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_STARTEI1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_STARTEI1; + tmp |= value << DAC_EVCTRL_STARTEI1_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_STARTEI1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_STARTEI1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_STARTEI1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_STARTEI1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_EMPTYEO0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_EMPTYEO0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_EMPTYEO0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_EMPTYEO0) >> DAC_EVCTRL_EMPTYEO0_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_EMPTYEO0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_EMPTYEO0; + tmp |= value << DAC_EVCTRL_EMPTYEO0_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_EMPTYEO0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_EMPTYEO0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_EMPTYEO0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_EMPTYEO0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_EMPTYEO1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_EMPTYEO1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_EMPTYEO1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_EMPTYEO1) >> DAC_EVCTRL_EMPTYEO1_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_EMPTYEO1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_EMPTYEO1; + tmp |= value << DAC_EVCTRL_EMPTYEO1_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_EMPTYEO1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_EMPTYEO1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_EMPTYEO1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_EMPTYEO1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_INVEI0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_INVEI0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_INVEI0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_INVEI0) >> DAC_EVCTRL_INVEI0_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_INVEI0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_INVEI0; + tmp |= value << DAC_EVCTRL_INVEI0_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_INVEI0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_INVEI0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_INVEI0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_INVEI0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_INVEI1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_INVEI1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_INVEI1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_INVEI1) >> DAC_EVCTRL_INVEI1_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_INVEI1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_INVEI1; + tmp |= value << DAC_EVCTRL_INVEI1_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_INVEI1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_INVEI1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_INVEI1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_INVEI1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_evctrl_reg_t hri_dac_get_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg = data; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_evctrl_reg_t hri_dac_read_EVCTRL_reg(const void *const hw) +{ + return ((Dac *)hw)->EVCTRL.reg; +} + +static inline void hri_dac_set_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_LEFTADJ; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_LEFTADJ) >> DAC_DACCTRL_LEFTADJ_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index, bool value) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_LEFTADJ; + tmp |= value << DAC_DACCTRL_LEFTADJ_Pos; + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_LEFTADJ; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_LEFTADJ; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_ENABLE; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + uint16_t tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_ENABLE) >> DAC_DACCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_ENABLE; + tmp |= value << DAC_DACCTRL_ENABLE_Pos; + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_ENABLE; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_ENABLE; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_RUNSTDBY; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_RUNSTDBY) >> DAC_DACCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_RUNSTDBY; + tmp |= value << DAC_DACCTRL_RUNSTDBY_Pos; + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_RUNSTDBY; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_RUNSTDBY; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_DITHER; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_DITHER) >> DAC_DACCTRL_DITHER_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_DACCTRL_DITHER_bit(const void *const hw, uint8_t index, bool value) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_DITHER; + tmp |= value << DAC_DACCTRL_DITHER_Pos; + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_DITHER; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_DITHER; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_CCTRL(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, + hri_dac_dacctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_CCTRL(mask)) >> DAC_DACCTRL_CCTRL_Pos; + return tmp; +} + +static inline void hri_dac_write_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_CCTRL_Msk; + tmp |= DAC_DACCTRL_CCTRL(data); + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_CCTRL(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_CCTRL(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_CCTRL_Msk) >> DAC_DACCTRL_CCTRL_Pos; + return tmp; +} + +static inline void hri_dac_set_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_REFRESH(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, + hri_dac_dacctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_REFRESH(mask)) >> DAC_DACCTRL_REFRESH_Pos; + return tmp; +} + +static inline void hri_dac_write_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_REFRESH_Msk; + tmp |= DAC_DACCTRL_REFRESH(data); + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_REFRESH(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_REFRESH(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_REFRESH_Msk) >> DAC_DACCTRL_REFRESH_Pos; + return tmp; +} + +static inline void hri_dac_set_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= mask; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_reg(const void *const hw, uint8_t index, + hri_dac_dacctrl_reg_t mask) +{ + uint16_t tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg = data; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~mask; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= mask; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_reg(const void *const hw, uint8_t index) +{ + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + return ((Dac *)hw)->DACCTRL[index].reg; +} + +static inline void hri_dac_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg |= DAC_DBGCTRL_DBGRUN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->DBGCTRL.reg; + tmp = (tmp & DAC_DBGCTRL_DBGRUN) >> DAC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DBGCTRL.reg; + tmp &= ~DAC_DBGCTRL_DBGRUN; + tmp |= value << DAC_DBGCTRL_DBGRUN_Pos; + ((Dac *)hw)->DBGCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg &= ~DAC_DBGCTRL_DBGRUN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg ^= DAC_DBGCTRL_DBGRUN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg |= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dbgctrl_reg_t hri_dac_get_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg = data; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg &= ~mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg ^= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dbgctrl_reg_t hri_dac_read_DBGCTRL_reg(const void *const hw) +{ + return ((Dac *)hw)->DBGCTRL.reg; +} + +static inline void hri_dac_write_DATA_reg(const void *const hw, uint8_t index, hri_dac_data_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DATA[index].reg = data; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_DATA0 | DAC_SYNCBUSY_DATA1); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_write_DATABUF_reg(const void *const hw, uint8_t index, hri_dac_databuf_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DATABUF[index].reg = data; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_DATABUF0 | DAC_SYNCBUSY_DATABUF1); + DAC_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_DAC_L21_H_INCLUDED */ +#endif /* _SAML21_DAC_COMPONENT_ */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_dmac_l21.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_dmac_l21.h new file mode 100644 index 00000000..f3e1a5a9 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_dmac_l21.h @@ -0,0 +1,4559 @@ +/** + * \file + * + * \brief SAM DMAC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_DMAC_COMPONENT_ +#ifndef _HRI_DMAC_L21_H_INCLUDED_ +#define _HRI_DMAC_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_DMAC_CRITICAL_SECTIONS) +#define DMAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define DMAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define DMAC_CRITICAL_SECTION_ENTER() +#define DMAC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_dmac_crcctrl_reg_t; +typedef uint16_t hri_dmac_ctrl_reg_t; +typedef uint16_t hri_dmac_intpend_reg_t; +typedef uint16_t hri_dmacdescriptor_btcnt_reg_t; +typedef uint16_t hri_dmacdescriptor_btctrl_reg_t; +typedef uint32_t hri_dmac_active_reg_t; +typedef uint32_t hri_dmac_baseaddr_reg_t; +typedef uint32_t hri_dmac_busych_reg_t; +typedef uint32_t hri_dmac_chctrlb_reg_t; +typedef uint32_t hri_dmac_crcchksum_reg_t; +typedef uint32_t hri_dmac_crcdatain_reg_t; +typedef uint32_t hri_dmac_intstatus_reg_t; +typedef uint32_t hri_dmac_pendch_reg_t; +typedef uint32_t hri_dmac_prictrl0_reg_t; +typedef uint32_t hri_dmac_swtrigctrl_reg_t; +typedef uint32_t hri_dmac_wrbaddr_reg_t; +typedef uint32_t hri_dmacdescriptor_descaddr_reg_t; +typedef uint32_t hri_dmacdescriptor_dstaddr_reg_t; +typedef uint32_t hri_dmacdescriptor_srcaddr_reg_t; +typedef uint8_t hri_dmac_chctrla_reg_t; +typedef uint8_t hri_dmac_chid_reg_t; +typedef uint8_t hri_dmac_chintenset_reg_t; +typedef uint8_t hri_dmac_chintflag_reg_t; +typedef uint8_t hri_dmac_chstatus_reg_t; +typedef uint8_t hri_dmac_crcstatus_reg_t; +typedef uint8_t hri_dmac_dbgctrl_reg_t; +typedef uint8_t hri_dmac_qosctrl_reg_t; + +static inline bool hri_dmac_get_CHINTFLAG_TERR_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; +} + +static inline void hri_dmac_clear_CHINTFLAG_TERR_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; +} + +static inline bool hri_dmac_get_CHINTFLAG_TCMPL_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; +} + +static inline void hri_dmac_clear_CHINTFLAG_TCMPL_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; +} + +static inline bool hri_dmac_get_CHINTFLAG_SUSP_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; +} + +static inline void hri_dmac_clear_CHINTFLAG_SUSP_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; +} + +static inline bool hri_dmac_get_interrupt_TERR_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; +} + +static inline void hri_dmac_clear_interrupt_TERR_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; +} + +static inline bool hri_dmac_get_interrupt_TCMPL_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; +} + +static inline void hri_dmac_clear_interrupt_TCMPL_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; +} + +static inline bool hri_dmac_get_interrupt_SUSP_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; +} + +static inline void hri_dmac_clear_interrupt_SUSP_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; +} + +static inline hri_dmac_chintflag_reg_t hri_dmac_get_CHINTFLAG_reg(const void *const hw, hri_dmac_chintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_chintflag_reg_t hri_dmac_read_CHINTFLAG_reg(const void *const hw) +{ + return ((Dmac *)hw)->CHINTFLAG.reg; +} + +static inline void hri_dmac_clear_CHINTFLAG_reg(const void *const hw, hri_dmac_chintflag_reg_t mask) +{ + ((Dmac *)hw)->CHINTFLAG.reg = mask; +} + +static inline void hri_dmac_set_CHINTEN_TERR_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR; +} + +static inline bool hri_dmac_get_CHINTEN_TERR_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TERR) >> DMAC_CHINTENSET_TERR_Pos; +} + +static inline void hri_dmac_write_CHINTEN_TERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR; + } else { + ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR; + } +} + +static inline void hri_dmac_clear_CHINTEN_TERR_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR; +} + +static inline void hri_dmac_set_CHINTEN_TCMPL_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; +} + +static inline bool hri_dmac_get_CHINTEN_TCMPL_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TCMPL) >> DMAC_CHINTENSET_TCMPL_Pos; +} + +static inline void hri_dmac_write_CHINTEN_TCMPL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; + } else { + ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; + } +} + +static inline void hri_dmac_clear_CHINTEN_TCMPL_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; +} + +static inline void hri_dmac_set_CHINTEN_SUSP_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP; +} + +static inline bool hri_dmac_get_CHINTEN_SUSP_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_SUSP) >> DMAC_CHINTENSET_SUSP_Pos; +} + +static inline void hri_dmac_write_CHINTEN_SUSP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; + } else { + ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP; + } +} + +static inline void hri_dmac_clear_CHINTEN_SUSP_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; +} + +static inline void hri_dmac_set_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask) +{ + ((Dmac *)hw)->CHINTENSET.reg = mask; +} + +static inline hri_dmac_chintenset_reg_t hri_dmac_get_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_chintenset_reg_t hri_dmac_read_CHINTEN_reg(const void *const hw) +{ + return ((Dmac *)hw)->CHINTENSET.reg; +} + +static inline void hri_dmac_write_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t data) +{ + ((Dmac *)hw)->CHINTENSET.reg = data; + ((Dmac *)hw)->CHINTENCLR.reg = ~data; +} + +static inline void hri_dmac_clear_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask) +{ + ((Dmac *)hw)->CHINTENCLR.reg = mask; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT0_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT0) >> DMAC_INTSTATUS_CHINT0_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT1_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT1) >> DMAC_INTSTATUS_CHINT1_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT2_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT2) >> DMAC_INTSTATUS_CHINT2_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT3_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT3) >> DMAC_INTSTATUS_CHINT3_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT4_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT4) >> DMAC_INTSTATUS_CHINT4_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT5_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT5) >> DMAC_INTSTATUS_CHINT5_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT6_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT6) >> DMAC_INTSTATUS_CHINT6_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT7_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT7) >> DMAC_INTSTATUS_CHINT7_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT8_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT8) >> DMAC_INTSTATUS_CHINT8_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT9_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT9) >> DMAC_INTSTATUS_CHINT9_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT10_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT10) >> DMAC_INTSTATUS_CHINT10_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT11_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT11) >> DMAC_INTSTATUS_CHINT11_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT12_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT12) >> DMAC_INTSTATUS_CHINT12_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT13_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT13) >> DMAC_INTSTATUS_CHINT13_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT14_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT14) >> DMAC_INTSTATUS_CHINT14_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT15_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT15) >> DMAC_INTSTATUS_CHINT15_Pos; +} + +static inline hri_dmac_intstatus_reg_t hri_dmac_get_INTSTATUS_reg(const void *const hw, hri_dmac_intstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->INTSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_intstatus_reg_t hri_dmac_read_INTSTATUS_reg(const void *const hw) +{ + return ((Dmac *)hw)->INTSTATUS.reg; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH0_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH0) >> DMAC_BUSYCH_BUSYCH0_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH1_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH1) >> DMAC_BUSYCH_BUSYCH1_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH2_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH2) >> DMAC_BUSYCH_BUSYCH2_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH3_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH3) >> DMAC_BUSYCH_BUSYCH3_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH4_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH4) >> DMAC_BUSYCH_BUSYCH4_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH5_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH5) >> DMAC_BUSYCH_BUSYCH5_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH6_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH6) >> DMAC_BUSYCH_BUSYCH6_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH7_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH7) >> DMAC_BUSYCH_BUSYCH7_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH8_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH8) >> DMAC_BUSYCH_BUSYCH8_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH9_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH9) >> DMAC_BUSYCH_BUSYCH9_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH10_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH10) >> DMAC_BUSYCH_BUSYCH10_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH11_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH11) >> DMAC_BUSYCH_BUSYCH11_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH12_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH12) >> DMAC_BUSYCH_BUSYCH12_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH13_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH13) >> DMAC_BUSYCH_BUSYCH13_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH14_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH14) >> DMAC_BUSYCH_BUSYCH14_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH15_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH15) >> DMAC_BUSYCH_BUSYCH15_Pos; +} + +static inline hri_dmac_busych_reg_t hri_dmac_get_BUSYCH_reg(const void *const hw, hri_dmac_busych_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BUSYCH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_busych_reg_t hri_dmac_read_BUSYCH_reg(const void *const hw) +{ + return ((Dmac *)hw)->BUSYCH.reg; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH0_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH0) >> DMAC_PENDCH_PENDCH0_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH1_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH1) >> DMAC_PENDCH_PENDCH1_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH2_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH2) >> DMAC_PENDCH_PENDCH2_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH3_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH3) >> DMAC_PENDCH_PENDCH3_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH4_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH4) >> DMAC_PENDCH_PENDCH4_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH5_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH5) >> DMAC_PENDCH_PENDCH5_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH6_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH6) >> DMAC_PENDCH_PENDCH6_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH7_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH7) >> DMAC_PENDCH_PENDCH7_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH8_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH8) >> DMAC_PENDCH_PENDCH8_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH9_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH9) >> DMAC_PENDCH_PENDCH9_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH10_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH10) >> DMAC_PENDCH_PENDCH10_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH11_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH11) >> DMAC_PENDCH_PENDCH11_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH12_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH12) >> DMAC_PENDCH_PENDCH12_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH13_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH13) >> DMAC_PENDCH_PENDCH13_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH14_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH14) >> DMAC_PENDCH_PENDCH14_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH15_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH15) >> DMAC_PENDCH_PENDCH15_Pos; +} + +static inline hri_dmac_pendch_reg_t hri_dmac_get_PENDCH_reg(const void *const hw, hri_dmac_pendch_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PENDCH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_pendch_reg_t hri_dmac_read_PENDCH_reg(const void *const hw) +{ + return ((Dmac *)hw)->PENDCH.reg; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX0_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX0) >> DMAC_ACTIVE_LVLEX0_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX1_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX1) >> DMAC_ACTIVE_LVLEX1_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX2_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX2) >> DMAC_ACTIVE_LVLEX2_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX3_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX3) >> DMAC_ACTIVE_LVLEX3_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_ABUSY_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ABUSY) >> DMAC_ACTIVE_ABUSY_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_ID_bf(const void *const hw, hri_dmac_active_reg_t mask) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID(mask)) >> DMAC_ACTIVE_ID_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_ID_bf(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID_Msk) >> DMAC_ACTIVE_ID_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_BTCNT_bf(const void *const hw, hri_dmac_active_reg_t mask) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT(mask)) >> DMAC_ACTIVE_BTCNT_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_BTCNT_bf(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT_Msk) >> DMAC_ACTIVE_BTCNT_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_reg(const void *const hw, hri_dmac_active_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->ACTIVE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_reg(const void *const hw) +{ + return ((Dmac *)hw)->ACTIVE.reg; +} + +static inline bool hri_dmac_get_CHSTATUS_PEND_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_PEND) >> DMAC_CHSTATUS_PEND_Pos; +} + +static inline bool hri_dmac_get_CHSTATUS_BUSY_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_BUSY) >> DMAC_CHSTATUS_BUSY_Pos; +} + +static inline bool hri_dmac_get_CHSTATUS_FERR_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_FERR) >> DMAC_CHSTATUS_FERR_Pos; +} + +static inline hri_dmac_chstatus_reg_t hri_dmac_get_CHSTATUS_reg(const void *const hw, hri_dmac_chstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_chstatus_reg_t hri_dmac_read_CHSTATUS_reg(const void *const hw) +{ + return ((Dmac *)hw)->CHSTATUS.reg; +} + +static inline void hri_dmac_set_CTRL_SWRST_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_SWRST; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_SWRST) >> DMAC_CTRL_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_set_CTRL_DMAENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_DMAENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_DMAENABLE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_DMAENABLE) >> DMAC_CTRL_DMAENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_DMAENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_DMAENABLE; + tmp |= value << DMAC_CTRL_DMAENABLE_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_DMAENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_DMAENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_DMAENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_DMAENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_CRCENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_CRCENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_CRCENABLE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_CRCENABLE) >> DMAC_CTRL_CRCENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_CRCENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_CRCENABLE; + tmp |= value << DMAC_CTRL_CRCENABLE_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_CRCENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_CRCENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_CRCENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_CRCENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN0) >> DMAC_CTRL_LVLEN0_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN0; + tmp |= value << DMAC_CTRL_LVLEN0_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN1) >> DMAC_CTRL_LVLEN1_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN1; + tmp |= value << DMAC_CTRL_LVLEN1_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN2) >> DMAC_CTRL_LVLEN2_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN2; + tmp |= value << DMAC_CTRL_LVLEN2_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN3) >> DMAC_CTRL_LVLEN3_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN3; + tmp |= value << DMAC_CTRL_LVLEN3_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_ctrl_reg_t hri_dmac_get_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_ctrl_reg_t hri_dmac_read_CTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->CTRL.reg; +} + +static inline void hri_dmac_set_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCBEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, + hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE(mask)) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= ~DMAC_CRCCTRL_CRCBEATSIZE_Msk; + tmp |= DMAC_CRCCTRL_CRCBEATSIZE(data); + ((Dmac *)hw)->CRCCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCBEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCBEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCBEATSIZE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE_Msk) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCPOLY(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCPOLY(mask)) >> DMAC_CRCCTRL_CRCPOLY_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= ~DMAC_CRCCTRL_CRCPOLY_Msk; + tmp |= DMAC_CRCCTRL_CRCPOLY(data); + ((Dmac *)hw)->CRCCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCPOLY(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCPOLY(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCPOLY_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCPOLY_Msk) >> DMAC_CRCCTRL_CRCPOLY_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCSRC(mask)) >> DMAC_CRCCTRL_CRCSRC_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= ~DMAC_CRCCTRL_CRCSRC_Msk; + tmp |= DMAC_CRCCTRL_CRCSRC(data); + ((Dmac *)hw)->CRCCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCSRC_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCSRC_Msk) >> DMAC_CRCCTRL_CRCSRC_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCCTRL.reg; +} + +static inline void hri_dmac_set_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg |= DMAC_CRCDATAIN_CRCDATAIN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_CRCDATAIN_bf(const void *const hw, + hri_dmac_crcdatain_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN(mask)) >> DMAC_CRCDATAIN_CRCDATAIN_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp &= ~DMAC_CRCDATAIN_CRCDATAIN_Msk; + tmp |= DMAC_CRCDATAIN_CRCDATAIN(data); + ((Dmac *)hw)->CRCDATAIN.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg &= ~DMAC_CRCDATAIN_CRCDATAIN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg ^= DMAC_CRCDATAIN_CRCDATAIN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_CRCDATAIN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN_Msk) >> DMAC_CRCDATAIN_CRCDATAIN_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCDATAIN.reg; +} + +static inline void hri_dmac_set_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg |= DMAC_CRCCHKSUM_CRCCHKSUM(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, + hri_dmac_crcchksum_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM(mask)) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp &= ~DMAC_CRCCHKSUM_CRCCHKSUM_Msk; + tmp |= DMAC_CRCCHKSUM_CRCCHKSUM(data); + ((Dmac *)hw)->CRCCHKSUM.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg &= ~DMAC_CRCCHKSUM_CRCCHKSUM(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg ^= DMAC_CRCCHKSUM_CRCCHKSUM(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM_Msk) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCCHKSUM.reg; +} + +static inline void hri_dmac_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg |= DMAC_DBGCTRL_DBGRUN; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->DBGCTRL.reg; + tmp = (tmp & DMAC_DBGCTRL_DBGRUN) >> DMAC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->DBGCTRL.reg; + tmp &= ~DMAC_DBGCTRL_DBGRUN; + tmp |= value << DMAC_DBGCTRL_DBGRUN_Pos; + ((Dmac *)hw)->DBGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg &= ~DMAC_DBGCTRL_DBGRUN; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg ^= DMAC_DBGCTRL_DBGRUN; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_dbgctrl_reg_t hri_dmac_get_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_dbgctrl_reg_t hri_dmac_read_DBGCTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->DBGCTRL.reg; +} + +static inline void hri_dmac_set_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg |= DMAC_QOSCTRL_WRBQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp = (tmp & DMAC_QOSCTRL_WRBQOS(mask)) >> DMAC_QOSCTRL_WRBQOS_Pos; + return tmp; +} + +static inline void hri_dmac_write_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp &= ~DMAC_QOSCTRL_WRBQOS_Msk; + tmp |= DMAC_QOSCTRL_WRBQOS(data); + ((Dmac *)hw)->QOSCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg &= ~DMAC_QOSCTRL_WRBQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg ^= DMAC_QOSCTRL_WRBQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_WRBQOS_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp = (tmp & DMAC_QOSCTRL_WRBQOS_Msk) >> DMAC_QOSCTRL_WRBQOS_Pos; + return tmp; +} + +static inline void hri_dmac_set_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg |= DMAC_QOSCTRL_FQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp = (tmp & DMAC_QOSCTRL_FQOS(mask)) >> DMAC_QOSCTRL_FQOS_Pos; + return tmp; +} + +static inline void hri_dmac_write_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp &= ~DMAC_QOSCTRL_FQOS_Msk; + tmp |= DMAC_QOSCTRL_FQOS(data); + ((Dmac *)hw)->QOSCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg &= ~DMAC_QOSCTRL_FQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg ^= DMAC_QOSCTRL_FQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_FQOS_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp = (tmp & DMAC_QOSCTRL_FQOS_Msk) >> DMAC_QOSCTRL_FQOS_Pos; + return tmp; +} + +static inline void hri_dmac_set_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg |= DMAC_QOSCTRL_DQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp = (tmp & DMAC_QOSCTRL_DQOS(mask)) >> DMAC_QOSCTRL_DQOS_Pos; + return tmp; +} + +static inline void hri_dmac_write_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp &= ~DMAC_QOSCTRL_DQOS_Msk; + tmp |= DMAC_QOSCTRL_DQOS(data); + ((Dmac *)hw)->QOSCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg &= ~DMAC_QOSCTRL_DQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg ^= DMAC_QOSCTRL_DQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_DQOS_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp = (tmp & DMAC_QOSCTRL_DQOS_Msk) >> DMAC_QOSCTRL_DQOS_Pos; + return tmp; +} + +static inline void hri_dmac_set_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->QOSCTRL.reg; +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG0) >> DMAC_SWTRIGCTRL_SWTRIG0_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG0; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG0_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG1) >> DMAC_SWTRIGCTRL_SWTRIG1_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG1; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG1_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG2) >> DMAC_SWTRIGCTRL_SWTRIG2_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG2; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG2_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG3) >> DMAC_SWTRIGCTRL_SWTRIG3_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG3; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG3_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG4; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG4) >> DMAC_SWTRIGCTRL_SWTRIG4_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG4; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG4_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG4; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG4; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG5; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG5) >> DMAC_SWTRIGCTRL_SWTRIG5_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG5; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG5_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG5; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG5; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG6; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG6) >> DMAC_SWTRIGCTRL_SWTRIG6_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG6; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG6_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG6; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG6; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG7; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG7) >> DMAC_SWTRIGCTRL_SWTRIG7_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG7; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG7_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG7; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG7; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG8; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG8) >> DMAC_SWTRIGCTRL_SWTRIG8_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG8; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG8_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG8; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG8; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG9; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG9) >> DMAC_SWTRIGCTRL_SWTRIG9_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG9; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG9_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG9; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG9; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG10; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG10) >> DMAC_SWTRIGCTRL_SWTRIG10_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG10; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG10_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG10; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG10; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG11; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG11) >> DMAC_SWTRIGCTRL_SWTRIG11_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG11; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG11_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG11; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG11; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG12; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG12) >> DMAC_SWTRIGCTRL_SWTRIG12_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG12; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG12_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG12; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG12; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG13; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG13) >> DMAC_SWTRIGCTRL_SWTRIG13_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG13; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG13_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG13; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG13; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG14; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG14) >> DMAC_SWTRIGCTRL_SWTRIG14_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG14; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG14_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG14; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG14; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG15; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG15) >> DMAC_SWTRIGCTRL_SWTRIG15_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG15; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG15_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG15; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG15; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_swtrigctrl_reg_t hri_dmac_get_SWTRIGCTRL_reg(const void *const hw, + hri_dmac_swtrigctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_swtrigctrl_reg_t hri_dmac_read_SWTRIGCTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->SWTRIGCTRL.reg; +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN0) >> DMAC_PRICTRL0_RRLVLEN0_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN0; + tmp |= value << DMAC_PRICTRL0_RRLVLEN0_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN1) >> DMAC_PRICTRL0_RRLVLEN1_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN1; + tmp |= value << DMAC_PRICTRL0_RRLVLEN1_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN2) >> DMAC_PRICTRL0_RRLVLEN2_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN2; + tmp |= value << DMAC_PRICTRL0_RRLVLEN2_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN3) >> DMAC_PRICTRL0_RRLVLEN3_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN3; + tmp |= value << DMAC_PRICTRL0_RRLVLEN3_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI0_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI0(mask)) >> DMAC_PRICTRL0_LVLPRI0_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI0_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI0(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI0_Msk) >> DMAC_PRICTRL0_LVLPRI0_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI1_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI1(mask)) >> DMAC_PRICTRL0_LVLPRI1_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI1_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI1(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI1_Msk) >> DMAC_PRICTRL0_LVLPRI1_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI2_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI2(mask)) >> DMAC_PRICTRL0_LVLPRI2_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI2_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI2(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI2_Msk) >> DMAC_PRICTRL0_LVLPRI2_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI3_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI3(mask)) >> DMAC_PRICTRL0_LVLPRI3_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI3_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI3(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI3_Msk) >> DMAC_PRICTRL0_LVLPRI3_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_reg(const void *const hw) +{ + return ((Dmac *)hw)->PRICTRL0.reg; +} + +static inline void hri_dmac_set_INTPEND_TERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_TERR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_TERR) >> DMAC_INTPEND_TERR_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_TERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_TERR; + tmp |= value << DMAC_INTPEND_TERR_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_TERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_TERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_TCMPL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TCMPL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_TCMPL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_TCMPL) >> DMAC_INTPEND_TCMPL_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_TCMPL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_TCMPL; + tmp |= value << DMAC_INTPEND_TCMPL_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_TCMPL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TCMPL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_TCMPL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TCMPL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_SUSP_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_SUSP; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_SUSP_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_SUSP) >> DMAC_INTPEND_SUSP_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_SUSP_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_SUSP; + tmp |= value << DMAC_INTPEND_SUSP_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_SUSP_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_SUSP; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_SUSP_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_SUSP; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_FERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_FERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_FERR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_FERR) >> DMAC_INTPEND_FERR_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_FERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_FERR; + tmp |= value << DMAC_INTPEND_FERR_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_FERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_FERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_FERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_FERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_BUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_BUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_BUSY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_BUSY) >> DMAC_INTPEND_BUSY_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_BUSY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_BUSY; + tmp |= value << DMAC_INTPEND_BUSY_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_BUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_BUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_BUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_BUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_PEND_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_PEND; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_PEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_PEND) >> DMAC_INTPEND_PEND_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_PEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_PEND; + tmp |= value << DMAC_INTPEND_PEND_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_PEND_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_PEND; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_PEND_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_PEND; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_ID(mask)) >> DMAC_INTPEND_ID_Pos; + return tmp; +} + +static inline void hri_dmac_write_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_ID_Msk; + tmp |= DMAC_INTPEND_ID(data); + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_ID_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_ID_Msk) >> DMAC_INTPEND_ID_Pos; + return tmp; +} + +static inline void hri_dmac_set_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_reg(const void *const hw) +{ + return ((Dmac *)hw)->INTPEND.reg; +} + +static inline void hri_dmac_set_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg |= DMAC_BASEADDR_BASEADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_BASEADDR_bf(const void *const hw, + hri_dmac_baseaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp = (tmp & DMAC_BASEADDR_BASEADDR(mask)) >> DMAC_BASEADDR_BASEADDR_Pos; + return tmp; +} + +static inline void hri_dmac_write_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp &= ~DMAC_BASEADDR_BASEADDR_Msk; + tmp |= DMAC_BASEADDR_BASEADDR(data); + ((Dmac *)hw)->BASEADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg &= ~DMAC_BASEADDR_BASEADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg ^= DMAC_BASEADDR_BASEADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_BASEADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp = (tmp & DMAC_BASEADDR_BASEADDR_Msk) >> DMAC_BASEADDR_BASEADDR_Pos; + return tmp; +} + +static inline void hri_dmac_set_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_reg(const void *const hw) +{ + return ((Dmac *)hw)->BASEADDR.reg; +} + +static inline void hri_dmac_set_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg |= DMAC_WRBADDR_WRBADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp = (tmp & DMAC_WRBADDR_WRBADDR(mask)) >> DMAC_WRBADDR_WRBADDR_Pos; + return tmp; +} + +static inline void hri_dmac_write_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp &= ~DMAC_WRBADDR_WRBADDR_Msk; + tmp |= DMAC_WRBADDR_WRBADDR(data); + ((Dmac *)hw)->WRBADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg &= ~DMAC_WRBADDR_WRBADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg ^= DMAC_WRBADDR_WRBADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_WRBADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp = (tmp & DMAC_WRBADDR_WRBADDR_Msk) >> DMAC_WRBADDR_WRBADDR_Pos; + return tmp; +} + +static inline void hri_dmac_set_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_reg(const void *const hw) +{ + return ((Dmac *)hw)->WRBADDR.reg; +} + +static inline void hri_dmac_set_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHID.reg |= DMAC_CHID_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chid_reg_t hri_dmac_get_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHID.reg; + tmp = (tmp & DMAC_CHID_ID(mask)) >> DMAC_CHID_ID_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHID.reg; + tmp &= ~DMAC_CHID_ID_Msk; + tmp |= DMAC_CHID_ID(data); + ((Dmac *)hw)->CHID.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHID.reg &= ~DMAC_CHID_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHID.reg ^= DMAC_CHID_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chid_reg_t hri_dmac_read_CHID_ID_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHID.reg; + tmp = (tmp & DMAC_CHID_ID_Msk) >> DMAC_CHID_ID_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHID.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chid_reg_t hri_dmac_get_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHID.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CHID_reg(const void *const hw, hri_dmac_chid_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHID.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHID.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHID.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chid_reg_t hri_dmac_read_CHID_reg(const void *const hw) +{ + return ((Dmac *)hw)->CHID.reg; +} + +static inline void hri_dmac_set_CHCTRLA_SWRST_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_SWRST; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_SWRST) >> DMAC_CHCTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_set_CHCTRLA_ENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_ENABLE) >> DMAC_CHCTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CHCTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_ENABLE; + tmp |= value << DMAC_CHCTRLA_ENABLE_Pos; + ((Dmac *)hw)->CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_ENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_ENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CHCTRLA_RUNSTDBY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_RUNSTDBY) >> DMAC_CHCTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CHCTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_RUNSTDBY; + tmp |= value << DMAC_CHCTRLA_RUNSTDBY_Pos; + ((Dmac *)hw)->CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_RUNSTDBY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_RUNSTDBY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_reg(const void *const hw) +{ + return ((Dmac *)hw)->CHCTRLA.reg; +} + +static inline void hri_dmac_set_CHCTRLB_EVIE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLB_EVIE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_EVIE) >> DMAC_CHCTRLB_EVIE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CHCTRLB_EVIE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_EVIE; + tmp |= value << DMAC_CHCTRLB_EVIE_Pos; + ((Dmac *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_EVIE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_EVIE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CHCTRLB_EVOE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLB_EVOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_EVOE) >> DMAC_CHCTRLB_EVOE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CHCTRLB_EVOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_EVOE; + tmp |= value << DMAC_CHCTRLB_EVOE_Pos; + ((Dmac *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_EVOE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_EVOE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_EVACT(mask)) >> DMAC_CHCTRLB_EVACT_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_EVACT_Msk; + tmp |= DMAC_CHCTRLB_EVACT(data); + ((Dmac *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_EVACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_EVACT_Msk) >> DMAC_CHCTRLB_EVACT_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_LVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_LVL(mask)) >> DMAC_CHCTRLB_LVL_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_LVL_Msk; + tmp |= DMAC_CHCTRLB_LVL(data); + ((Dmac *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_LVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_LVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_LVL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_LVL_Msk) >> DMAC_CHCTRLB_LVL_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_TRIGSRC(mask)) >> DMAC_CHCTRLB_TRIGSRC_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_TRIGSRC_Msk; + tmp |= DMAC_CHCTRLB_TRIGSRC(data); + ((Dmac *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_TRIGSRC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_TRIGSRC_Msk) >> DMAC_CHCTRLB_TRIGSRC_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_TRIGACT(mask)) >> DMAC_CHCTRLB_TRIGACT_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_TRIGACT_Msk; + tmp |= DMAC_CHCTRLB_TRIGACT(data); + ((Dmac *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_TRIGACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_TRIGACT_Msk) >> DMAC_CHCTRLB_TRIGACT_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_CMD(mask)) >> DMAC_CHCTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_CMD_Msk; + tmp |= DMAC_CHCTRLB_CMD(data); + ((Dmac *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_CMD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_CMD_Msk) >> DMAC_CHCTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_reg(const void *const hw) +{ + return ((Dmac *)hw)->CHCTRLB.reg; +} + +static inline bool hri_dmac_get_CRCSTATUS_CRCBUSY_bit(const void *const hw) +{ + return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) >> DMAC_CRCSTATUS_CRCBUSY_Pos; +} + +static inline void hri_dmac_clear_CRCSTATUS_CRCBUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCBUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CRCSTATUS_CRCZERO_bit(const void *const hw) +{ + return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCZERO) >> DMAC_CRCSTATUS_CRCZERO_Pos; +} + +static inline void hri_dmac_clear_CRCSTATUS_CRCZERO_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCZERO; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcstatus_reg_t hri_dmac_get_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CRCSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_clear_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCSTATUS.reg = mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcstatus_reg_t hri_dmac_read_CRCSTATUS_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCSTATUS.reg; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_VALID_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_VALID; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_VALID_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_VALID) >> DMAC_BTCTRL_VALID_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_VALID_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_VALID; + tmp |= value << DMAC_BTCTRL_VALID_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_VALID_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_VALID; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_VALID_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_VALID; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_SRCINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_SRCINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_SRCINC) >> DMAC_BTCTRL_SRCINC_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_SRCINC; + tmp |= value << DMAC_BTCTRL_SRCINC_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_SRCINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_SRCINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_SRCINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_SRCINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_DSTINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_DSTINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_DSTINC) >> DMAC_BTCTRL_DSTINC_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_DSTINC; + tmp |= value << DMAC_BTCTRL_DSTINC_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_DSTINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_DSTINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_DSTINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_DSTINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_STEPSEL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSEL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_STEPSEL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_STEPSEL) >> DMAC_BTCTRL_STEPSEL_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_STEPSEL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_STEPSEL; + tmp |= value << DMAC_BTCTRL_STEPSEL_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSEL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSEL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSEL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSEL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_EVOSEL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_EVOSEL(mask)) >> DMAC_BTCTRL_EVOSEL_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_EVOSEL_Msk; + tmp |= DMAC_BTCTRL_EVOSEL(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_EVOSEL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_EVOSEL_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_EVOSEL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_EVOSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_EVOSEL_Msk) >> DMAC_BTCTRL_EVOSEL_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BLOCKACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BLOCKACT(mask)) >> DMAC_BTCTRL_BLOCKACT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_BLOCKACT_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_BLOCKACT_Msk; + tmp |= DMAC_BTCTRL_BLOCKACT(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_BLOCKACT_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BLOCKACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_BLOCKACT_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BLOCKACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BLOCKACT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BLOCKACT_Msk) >> DMAC_BTCTRL_BLOCKACT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BEATSIZE(mask)) >> DMAC_BTCTRL_BEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_BEATSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_BEATSIZE_Msk; + tmp |= DMAC_BTCTRL_BEATSIZE(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_BEATSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_BEATSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BEATSIZE_Msk) >> DMAC_BTCTRL_BEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_STEPSIZE(mask)) >> DMAC_BTCTRL_STEPSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_STEPSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_STEPSIZE_Msk; + tmp |= DMAC_BTCTRL_STEPSIZE(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_STEPSIZE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_STEPSIZE_Msk) >> DMAC_BTCTRL_STEPSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_get_BTCTRL_reg(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->BTCTRL.reg; +} + +static inline void hri_dmacdescriptor_set_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg |= DMAC_BTCNT_BTCNT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_BTCNT_bf(const void *const hw, + hri_dmacdescriptor_btcnt_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp = (tmp & DMAC_BTCNT_BTCNT(mask)) >> DMAC_BTCNT_BTCNT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp &= ~DMAC_BTCNT_BTCNT_Msk; + tmp |= DMAC_BTCNT_BTCNT(data); + ((DmacDescriptor *)hw)->BTCNT.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg &= ~DMAC_BTCNT_BTCNT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg ^= DMAC_BTCNT_BTCNT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_BTCNT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp = (tmp & DMAC_BTCNT_BTCNT_Msk) >> DMAC_BTCNT_BTCNT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_reg(const void *const hw, + hri_dmacdescriptor_btcnt_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->BTCNT.reg; +} + +static inline void hri_dmacdescriptor_set_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg |= DMAC_SRCADDR_SRCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t +hri_dmacdescriptor_get_SRCADDR_SRCADDR_bf(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp = (tmp & DMAC_SRCADDR_SRCADDR(mask)) >> DMAC_SRCADDR_SRCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp &= ~DMAC_SRCADDR_SRCADDR_Msk; + tmp |= DMAC_SRCADDR_SRCADDR(data); + ((DmacDescriptor *)hw)->SRCADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg &= ~DMAC_SRCADDR_SRCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg ^= DMAC_SRCADDR_SRCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_SRCADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp = (tmp & DMAC_SRCADDR_SRCADDR_Msk) >> DMAC_SRCADDR_SRCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_get_SRCADDR_reg(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->SRCADDR.reg; +} + +static inline void hri_dmacdescriptor_set_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg |= DMAC_DSTADDR_DSTADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t +hri_dmacdescriptor_get_DSTADDR_DSTADDR_bf(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp = (tmp & DMAC_DSTADDR_DSTADDR(mask)) >> DMAC_DSTADDR_DSTADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp &= ~DMAC_DSTADDR_DSTADDR_Msk; + tmp |= DMAC_DSTADDR_DSTADDR(data); + ((DmacDescriptor *)hw)->DSTADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg &= ~DMAC_DSTADDR_DSTADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg ^= DMAC_DSTADDR_DSTADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_DSTADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp = (tmp & DMAC_DSTADDR_DSTADDR_Msk) >> DMAC_DSTADDR_DSTADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_get_DSTADDR_reg(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->DSTADDR.reg; +} + +static inline void hri_dmacdescriptor_set_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg |= DMAC_DESCADDR_DESCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t +hri_dmacdescriptor_get_DESCADDR_DESCADDR_bf(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp = (tmp & DMAC_DESCADDR_DESCADDR(mask)) >> DMAC_DESCADDR_DESCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp &= ~DMAC_DESCADDR_DESCADDR_Msk; + tmp |= DMAC_DESCADDR_DESCADDR(data); + ((DmacDescriptor *)hw)->DESCADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg &= ~DMAC_DESCADDR_DESCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg ^= DMAC_DESCADDR_DESCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_DESCADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp = (tmp & DMAC_DESCADDR_DESCADDR_Msk) >> DMAC_DESCADDR_DESCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t +hri_dmacdescriptor_get_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->DESCADDR.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_DMAC_L21_H_INCLUDED */ +#endif /* _SAML21_DMAC_COMPONENT_ */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_dsu_l21.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_dsu_l21.h new file mode 100644 index 00000000..d9c66b1c --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_dsu_l21.h @@ -0,0 +1,1163 @@ +/** + * \file + * + * \brief SAM DSU + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_DSU_COMPONENT_ +#ifndef _HRI_DSU_L21_H_INCLUDED_ +#define _HRI_DSU_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_DSU_CRITICAL_SECTIONS) +#define DSU_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define DSU_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define DSU_CRITICAL_SECTION_ENTER() +#define DSU_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_dsu_addr_reg_t; +typedef uint32_t hri_dsu_cid0_reg_t; +typedef uint32_t hri_dsu_cid1_reg_t; +typedef uint32_t hri_dsu_cid2_reg_t; +typedef uint32_t hri_dsu_cid3_reg_t; +typedef uint32_t hri_dsu_data_reg_t; +typedef uint32_t hri_dsu_dcc_reg_t; +typedef uint32_t hri_dsu_dcfg_reg_t; +typedef uint32_t hri_dsu_did_reg_t; +typedef uint32_t hri_dsu_end_reg_t; +typedef uint32_t hri_dsu_entry0_reg_t; +typedef uint32_t hri_dsu_entry1_reg_t; +typedef uint32_t hri_dsu_length_reg_t; +typedef uint32_t hri_dsu_memtype_reg_t; +typedef uint32_t hri_dsu_pid0_reg_t; +typedef uint32_t hri_dsu_pid1_reg_t; +typedef uint32_t hri_dsu_pid2_reg_t; +typedef uint32_t hri_dsu_pid3_reg_t; +typedef uint32_t hri_dsu_pid4_reg_t; +typedef uint32_t hri_dsu_pid5_reg_t; +typedef uint32_t hri_dsu_pid6_reg_t; +typedef uint32_t hri_dsu_pid7_reg_t; +typedef uint8_t hri_dsu_ctrl_reg_t; +typedef uint8_t hri_dsu_statusa_reg_t; +typedef uint8_t hri_dsu_statusb_reg_t; + +static inline bool hri_dsu_get_STATUSB_PROT_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_PROT) >> DSU_STATUSB_PROT_Pos; +} + +static inline bool hri_dsu_get_STATUSB_DBGPRES_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DBGPRES) >> DSU_STATUSB_DBGPRES_Pos; +} + +static inline bool hri_dsu_get_STATUSB_DCCD0_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD0) >> DSU_STATUSB_DCCD0_Pos; +} + +static inline bool hri_dsu_get_STATUSB_DCCD1_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD1) >> DSU_STATUSB_DCCD1_Pos; +} + +static inline bool hri_dsu_get_STATUSB_HPE_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_HPE) >> DSU_STATUSB_HPE_Pos; +} + +static inline hri_dsu_statusb_reg_t hri_dsu_get_STATUSB_reg(const void *const hw, hri_dsu_statusb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dsu *)hw)->STATUSB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_statusb_reg_t hri_dsu_read_STATUSB_reg(const void *const hw) +{ + return ((Dsu *)hw)->STATUSB.reg; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_DEVSEL_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL(mask)) >> DSU_DID_DEVSEL_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_DEVSEL_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL_Msk) >> DSU_DID_DEVSEL_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_REVISION_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION(mask)) >> DSU_DID_REVISION_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_REVISION_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION_Msk) >> DSU_DID_REVISION_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_DIE_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DIE(mask)) >> DSU_DID_DIE_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_DIE_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DIE_Msk) >> DSU_DID_DIE_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_SERIES_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES(mask)) >> DSU_DID_SERIES_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_SERIES_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES_Msk) >> DSU_DID_SERIES_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_FAMILY_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY(mask)) >> DSU_DID_FAMILY_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_FAMILY_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY_Msk) >> DSU_DID_FAMILY_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_PROCESSOR_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR(mask)) >> DSU_DID_PROCESSOR_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_PROCESSOR_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR_Msk) >> DSU_DID_PROCESSOR_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_reg(const void *const hw, hri_dsu_did_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DID.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_reg(const void *const hw) +{ + return ((Dsu *)hw)->DID.reg; +} + +static inline bool hri_dsu_get_ENTRY0_EPRES_bit(const void *const hw) +{ + return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_EPRES) >> DSU_ENTRY0_EPRES_Pos; +} + +static inline bool hri_dsu_get_ENTRY0_FMT_bit(const void *const hw) +{ + return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_FMT) >> DSU_ENTRY0_FMT_Pos; +} + +static inline hri_dsu_entry0_reg_t hri_dsu_get_ENTRY0_ADDOFF_bf(const void *const hw, hri_dsu_entry0_reg_t mask) +{ + return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_ADDOFF(mask)) >> DSU_ENTRY0_ADDOFF_Pos; +} + +static inline hri_dsu_entry0_reg_t hri_dsu_read_ENTRY0_ADDOFF_bf(const void *const hw) +{ + return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_ADDOFF_Msk) >> DSU_ENTRY0_ADDOFF_Pos; +} + +static inline hri_dsu_entry0_reg_t hri_dsu_get_ENTRY0_reg(const void *const hw, hri_dsu_entry0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ENTRY0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_entry0_reg_t hri_dsu_read_ENTRY0_reg(const void *const hw) +{ + return ((Dsu *)hw)->ENTRY0.reg; +} + +static inline hri_dsu_entry1_reg_t hri_dsu_get_ENTRY1_reg(const void *const hw, hri_dsu_entry1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ENTRY1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_entry1_reg_t hri_dsu_read_ENTRY1_reg(const void *const hw) +{ + return ((Dsu *)hw)->ENTRY1.reg; +} + +static inline hri_dsu_end_reg_t hri_dsu_get_END_END_bf(const void *const hw, hri_dsu_end_reg_t mask) +{ + return (((Dsu *)hw)->END.reg & DSU_END_END(mask)) >> DSU_END_END_Pos; +} + +static inline hri_dsu_end_reg_t hri_dsu_read_END_END_bf(const void *const hw) +{ + return (((Dsu *)hw)->END.reg & DSU_END_END_Msk) >> DSU_END_END_Pos; +} + +static inline hri_dsu_end_reg_t hri_dsu_get_END_reg(const void *const hw, hri_dsu_end_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->END.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_end_reg_t hri_dsu_read_END_reg(const void *const hw) +{ + return ((Dsu *)hw)->END.reg; +} + +static inline bool hri_dsu_get_MEMTYPE_SMEMP_bit(const void *const hw) +{ + return (((Dsu *)hw)->MEMTYPE.reg & DSU_MEMTYPE_SMEMP) >> DSU_MEMTYPE_SMEMP_Pos; +} + +static inline hri_dsu_memtype_reg_t hri_dsu_get_MEMTYPE_reg(const void *const hw, hri_dsu_memtype_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MEMTYPE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_memtype_reg_t hri_dsu_read_MEMTYPE_reg(const void *const hw) +{ + return ((Dsu *)hw)->MEMTYPE.reg; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_JEPCC_bf(const void *const hw, hri_dsu_pid4_reg_t mask) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC(mask)) >> DSU_PID4_JEPCC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_JEPCC_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC_Msk) >> DSU_PID4_JEPCC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_FKBC_bf(const void *const hw, hri_dsu_pid4_reg_t mask) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC(mask)) >> DSU_PID4_FKBC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_FKBC_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC_Msk) >> DSU_PID4_FKBC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_reg(const void *const hw, hri_dsu_pid4_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID4.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID4.reg; +} + +static inline hri_dsu_pid5_reg_t hri_dsu_get_PID5_reg(const void *const hw, hri_dsu_pid5_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID5.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid5_reg_t hri_dsu_read_PID5_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID5.reg; +} + +static inline hri_dsu_pid6_reg_t hri_dsu_get_PID6_reg(const void *const hw, hri_dsu_pid6_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID6.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid6_reg_t hri_dsu_read_PID6_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID6.reg; +} + +static inline hri_dsu_pid7_reg_t hri_dsu_get_PID7_reg(const void *const hw, hri_dsu_pid7_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID7.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid7_reg_t hri_dsu_read_PID7_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID7.reg; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_PARTNBL_bf(const void *const hw, hri_dsu_pid0_reg_t mask) +{ + return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL(mask)) >> DSU_PID0_PARTNBL_Pos; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_PARTNBL_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL_Msk) >> DSU_PID0_PARTNBL_Pos; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_reg(const void *const hw, hri_dsu_pid0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID0.reg; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_PARTNBH_bf(const void *const hw, hri_dsu_pid1_reg_t mask) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH(mask)) >> DSU_PID1_PARTNBH_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_PARTNBH_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH_Msk) >> DSU_PID1_PARTNBH_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_JEPIDCL_bf(const void *const hw, hri_dsu_pid1_reg_t mask) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL(mask)) >> DSU_PID1_JEPIDCL_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_JEPIDCL_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL_Msk) >> DSU_PID1_JEPIDCL_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_reg(const void *const hw, hri_dsu_pid1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID1.reg; +} + +static inline bool hri_dsu_get_PID2_JEPU_bit(const void *const hw) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPU) >> DSU_PID2_JEPU_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_JEPIDCH_bf(const void *const hw, hri_dsu_pid2_reg_t mask) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH(mask)) >> DSU_PID2_JEPIDCH_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_JEPIDCH_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH_Msk) >> DSU_PID2_JEPIDCH_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_REVISION_bf(const void *const hw, hri_dsu_pid2_reg_t mask) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION(mask)) >> DSU_PID2_REVISION_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_REVISION_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION_Msk) >> DSU_PID2_REVISION_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_reg(const void *const hw, hri_dsu_pid2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID2.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID2.reg; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_CUSMOD_bf(const void *const hw, hri_dsu_pid3_reg_t mask) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD(mask)) >> DSU_PID3_CUSMOD_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_CUSMOD_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD_Msk) >> DSU_PID3_CUSMOD_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_REVAND_bf(const void *const hw, hri_dsu_pid3_reg_t mask) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND(mask)) >> DSU_PID3_REVAND_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_REVAND_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND_Msk) >> DSU_PID3_REVAND_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_reg(const void *const hw, hri_dsu_pid3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID3.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID3.reg; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_PREAMBLEB0_bf(const void *const hw, hri_dsu_cid0_reg_t mask) +{ + return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0(mask)) >> DSU_CID0_PREAMBLEB0_Pos; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_PREAMBLEB0_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0_Msk) >> DSU_CID0_PREAMBLEB0_Pos; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_reg(const void *const hw, hri_dsu_cid0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID0.reg; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_PREAMBLE_bf(const void *const hw, hri_dsu_cid1_reg_t mask) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE(mask)) >> DSU_CID1_PREAMBLE_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_PREAMBLE_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE_Msk) >> DSU_CID1_PREAMBLE_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_CCLASS_bf(const void *const hw, hri_dsu_cid1_reg_t mask) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS(mask)) >> DSU_CID1_CCLASS_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_CCLASS_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS_Msk) >> DSU_CID1_CCLASS_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_reg(const void *const hw, hri_dsu_cid1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID1.reg; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_PREAMBLEB2_bf(const void *const hw, hri_dsu_cid2_reg_t mask) +{ + return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2(mask)) >> DSU_CID2_PREAMBLEB2_Pos; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_PREAMBLEB2_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2_Msk) >> DSU_CID2_PREAMBLEB2_Pos; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_reg(const void *const hw, hri_dsu_cid2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID2.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID2.reg; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_PREAMBLEB3_bf(const void *const hw, hri_dsu_cid3_reg_t mask) +{ + return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3(mask)) >> DSU_CID3_PREAMBLEB3_Pos; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_PREAMBLEB3_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3_Msk) >> DSU_CID3_PREAMBLEB3_Pos; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_reg(const void *const hw, hri_dsu_cid3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID3.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID3.reg; +} + +static inline void hri_dsu_set_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg |= DSU_ADDR_AMOD(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp = (tmp & DSU_ADDR_AMOD(mask)) >> DSU_ADDR_AMOD_Pos; + return tmp; +} + +static inline void hri_dsu_write_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->ADDR.reg; + tmp &= ~DSU_ADDR_AMOD_Msk; + tmp |= DSU_ADDR_AMOD(data); + ((Dsu *)hw)->ADDR.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_AMOD(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_AMOD(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_AMOD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp = (tmp & DSU_ADDR_AMOD_Msk) >> DSU_ADDR_AMOD_Pos; + return tmp; +} + +static inline void hri_dsu_set_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg |= DSU_ADDR_ADDR(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp = (tmp & DSU_ADDR_ADDR(mask)) >> DSU_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_dsu_write_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->ADDR.reg; + tmp &= ~DSU_ADDR_ADDR_Msk; + tmp |= DSU_ADDR_ADDR(data); + ((Dsu *)hw)->ADDR.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_ADDR(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_ADDR(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp = (tmp & DSU_ADDR_ADDR_Msk) >> DSU_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_dsu_set_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_reg(const void *const hw) +{ + return ((Dsu *)hw)->ADDR.reg; +} + +static inline void hri_dsu_set_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg |= DSU_LENGTH_LENGTH(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp = (tmp & DSU_LENGTH_LENGTH(mask)) >> DSU_LENGTH_LENGTH_Pos; + return tmp; +} + +static inline void hri_dsu_write_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp &= ~DSU_LENGTH_LENGTH_Msk; + tmp |= DSU_LENGTH_LENGTH(data); + ((Dsu *)hw)->LENGTH.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg &= ~DSU_LENGTH_LENGTH(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg ^= DSU_LENGTH_LENGTH(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_LENGTH_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp = (tmp & DSU_LENGTH_LENGTH_Msk) >> DSU_LENGTH_LENGTH_Pos; + return tmp; +} + +static inline void hri_dsu_set_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_reg(const void *const hw) +{ + return ((Dsu *)hw)->LENGTH.reg; +} + +static inline void hri_dsu_set_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg |= DSU_DATA_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_get_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DATA.reg; + tmp = (tmp & DSU_DATA_DATA(mask)) >> DSU_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_write_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->DATA.reg; + tmp &= ~DSU_DATA_DATA_Msk; + tmp |= DSU_DATA_DATA(data); + ((Dsu *)hw)->DATA.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg &= ~DSU_DATA_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg ^= DSU_DATA_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_read_DATA_DATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DATA.reg; + tmp = (tmp & DSU_DATA_DATA_Msk) >> DSU_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_set_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_get_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_DATA_reg(const void *const hw, hri_dsu_data_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_read_DATA_reg(const void *const hw) +{ + return ((Dsu *)hw)->DATA.reg; +} + +static inline void hri_dsu_set_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg |= DSU_DCC_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp = (tmp & DSU_DCC_DATA(mask)) >> DSU_DCC_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_write_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp &= ~DSU_DCC_DATA_Msk; + tmp |= DSU_DCC_DATA(data); + ((Dsu *)hw)->DCC[index].reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg &= ~DSU_DCC_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg ^= DSU_DCC_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_DATA_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp = (tmp & DSU_DCC_DATA_Msk) >> DSU_DCC_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_set_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_reg(const void *const hw, uint8_t index) +{ + return ((Dsu *)hw)->DCC[index].reg; +} + +static inline void hri_dsu_set_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCFG[index].reg |= DSU_DCFG_DCFG(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcfg_reg_t hri_dsu_get_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCFG[index].reg; + tmp = (tmp & DSU_DCFG_DCFG(mask)) >> DSU_DCFG_DCFG_Pos; + return tmp; +} + +static inline void hri_dsu_write_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->DCFG[index].reg; + tmp &= ~DSU_DCFG_DCFG_Msk; + tmp |= DSU_DCFG_DCFG(data); + ((Dsu *)hw)->DCFG[index].reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCFG[index].reg &= ~DSU_DCFG_DCFG(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCFG[index].reg ^= DSU_DCFG_DCFG(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcfg_reg_t hri_dsu_read_DCFG_DCFG_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCFG[index].reg; + tmp = (tmp & DSU_DCFG_DCFG_Msk) >> DSU_DCFG_DCFG_Pos; + return tmp; +} + +static inline void hri_dsu_set_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCFG[index].reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcfg_reg_t hri_dsu_get_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCFG[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCFG[index].reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCFG[index].reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCFG[index].reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcfg_reg_t hri_dsu_read_DCFG_reg(const void *const hw, uint8_t index) +{ + return ((Dsu *)hw)->DCFG[index].reg; +} + +static inline bool hri_dsu_get_STATUSA_DONE_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_DONE) >> DSU_STATUSA_DONE_Pos; +} + +static inline void hri_dsu_clear_STATUSA_DONE_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_DONE; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_CRSTEXT_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_CRSTEXT) >> DSU_STATUSA_CRSTEXT_Pos; +} + +static inline void hri_dsu_clear_STATUSA_CRSTEXT_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_CRSTEXT; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_BERR_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_BERR) >> DSU_STATUSA_BERR_Pos; +} + +static inline void hri_dsu_clear_STATUSA_BERR_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_BERR; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_FAIL_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_FAIL) >> DSU_STATUSA_FAIL_Pos; +} + +static inline void hri_dsu_clear_STATUSA_FAIL_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_FAIL; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_PERR_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_PERR) >> DSU_STATUSA_PERR_Pos; +} + +static inline void hri_dsu_clear_STATUSA_PERR_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_PERR; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_statusa_reg_t hri_dsu_get_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dsu *)hw)->STATUSA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_clear_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_statusa_reg_t hri_dsu_read_STATUSA_reg(const void *const hw) +{ + return ((Dsu *)hw)->STATUSA.reg; +} + +static inline void hri_dsu_write_CTRL_reg(const void *const hw, hri_dsu_ctrl_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CTRL.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_DSU_L21_H_INCLUDED */ +#endif /* _SAML21_DSU_COMPONENT_ */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_eic_l21.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_eic_l21.h new file mode 100644 index 00000000..9d2ddeaf --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_eic_l21.h @@ -0,0 +1,1463 @@ +/** + * \file + * + * \brief SAM EIC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_EIC_COMPONENT_ +#ifndef _HRI_EIC_L21_H_INCLUDED_ +#define _HRI_EIC_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_EIC_CRITICAL_SECTIONS) +#define EIC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define EIC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define EIC_CRITICAL_SECTION_ENTER() +#define EIC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_eic_nmiflag_reg_t; +typedef uint32_t hri_eic_asynch_reg_t; +typedef uint32_t hri_eic_config_reg_t; +typedef uint32_t hri_eic_evctrl_reg_t; +typedef uint32_t hri_eic_intenset_reg_t; +typedef uint32_t hri_eic_intflag_reg_t; +typedef uint32_t hri_eic_syncbusy_reg_t; +typedef uint8_t hri_eic_ctrla_reg_t; +typedef uint8_t hri_eic_nmictrl_reg_t; + +static inline void hri_eic_wait_for_sync(const void *const hw, hri_eic_syncbusy_reg_t reg) +{ + while (((Eic *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_eic_is_syncing(const void *const hw, hri_eic_syncbusy_reg_t reg) +{ + return ((Eic *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_eic_get_NMIFLAG_NMI_bit(const void *const hw) +{ + return (((Eic *)hw)->NMIFLAG.reg & EIC_NMIFLAG_NMI) >> EIC_NMIFLAG_NMI_Pos; +} + +static inline void hri_eic_clear_NMIFLAG_NMI_bit(const void *const hw) +{ + ((Eic *)hw)->NMIFLAG.reg = EIC_NMIFLAG_NMI; +} + +static inline hri_eic_nmiflag_reg_t hri_eic_get_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Eic *)hw)->NMIFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_nmiflag_reg_t hri_eic_read_NMIFLAG_reg(const void *const hw) +{ + return ((Eic *)hw)->NMIFLAG.reg; +} + +static inline void hri_eic_clear_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask) +{ + ((Eic *)hw)->NMIFLAG.reg = mask; +} + +static inline hri_eic_intflag_reg_t hri_eic_get_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_intflag_reg_t hri_eic_read_INTFLAG_reg(const void *const hw) +{ + return ((Eic *)hw)->INTFLAG.reg; +} + +static inline void hri_eic_clear_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask) +{ + ((Eic *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_eic_set_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) +{ + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(mask); +} + +static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->INTENSET.reg; + tmp = (tmp & EIC_INTENSET_EXTINT(mask)) >> EIC_INTENSET_EXTINT_Pos; + return tmp; +} + +static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_EXTINT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->INTENSET.reg; + tmp = (tmp & EIC_INTENSET_EXTINT_Msk) >> EIC_INTENSET_EXTINT_Pos; + return tmp; +} + +static inline void hri_eic_write_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t data) +{ + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(data); + ((Eic *)hw)->INTENCLR.reg = ~EIC_INTENSET_EXTINT(data); +} + +static inline void hri_eic_clear_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) +{ + ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT(mask); +} + +static inline void hri_eic_set_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) +{ + ((Eic *)hw)->INTENSET.reg = mask; +} + +static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_reg(const void *const hw) +{ + return ((Eic *)hw)->INTENSET.reg; +} + +static inline void hri_eic_write_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t data) +{ + ((Eic *)hw)->INTENSET.reg = data; + ((Eic *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_eic_clear_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) +{ + ((Eic *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_eic_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_SWRST) >> EIC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_eic_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_ENABLE) >> EIC_SYNCBUSY_ENABLE_Pos; +} + +static inline hri_eic_syncbusy_reg_t hri_eic_get_SYNCBUSY_reg(const void *const hw, hri_eic_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_syncbusy_reg_t hri_eic_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Eic *)hw)->SYNCBUSY.reg; +} + +static inline void hri_eic_set_CTRLA_SWRST_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_SWRST; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp = (tmp & EIC_CTRLA_SWRST) >> EIC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_eic_set_CTRLA_ENABLE_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_ENABLE; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp = (tmp & EIC_CTRLA_ENABLE) >> EIC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp &= ~EIC_CTRLA_ENABLE; + tmp |= value << EIC_CTRLA_ENABLE_Pos; + ((Eic *)hw)->CTRLA.reg = tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_ENABLE; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_ENABLE; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CTRLA_CKSEL_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_CKSEL; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CTRLA_CKSEL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->CTRLA.reg; + tmp = (tmp & EIC_CTRLA_CKSEL) >> EIC_CTRLA_CKSEL_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CTRLA_CKSEL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp &= ~EIC_CTRLA_CKSEL; + tmp |= value << EIC_CTRLA_CKSEL_Pos; + ((Eic *)hw)->CTRLA.reg = tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CTRLA_CKSEL_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_CKSEL; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CTRLA_CKSEL_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_CKSEL; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg |= mask; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_ctrla_reg_t hri_eic_get_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg = data; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg &= ~mask; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg ^= mask; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_ctrla_reg_t hri_eic_read_CTRLA_reg(const void *const hw) +{ + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + return ((Eic *)hw)->CTRLA.reg; +} + +static inline void hri_eic_set_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIFILTEN; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp = (tmp & EIC_NMICTRL_NMIFILTEN) >> EIC_NMICTRL_NMIFILTEN_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_NMICTRL_NMIFILTEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp &= ~EIC_NMICTRL_NMIFILTEN; + tmp |= value << EIC_NMICTRL_NMIFILTEN_Pos; + ((Eic *)hw)->NMICTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIFILTEN; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIFILTEN; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_NMICTRL_NMIASYNCH_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIASYNCH; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_NMICTRL_NMIASYNCH_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp = (tmp & EIC_NMICTRL_NMIASYNCH) >> EIC_NMICTRL_NMIASYNCH_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_NMICTRL_NMIASYNCH_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp &= ~EIC_NMICTRL_NMIASYNCH; + tmp |= value << EIC_NMICTRL_NMIASYNCH_Pos; + ((Eic *)hw)->NMICTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_NMICTRL_NMIASYNCH_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIASYNCH; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_NMICTRL_NMIASYNCH_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIASYNCH; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMISENSE(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp = (tmp & EIC_NMICTRL_NMISENSE(mask)) >> EIC_NMICTRL_NMISENSE_Pos; + return tmp; +} + +static inline void hri_eic_write_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t data) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp &= ~EIC_NMICTRL_NMISENSE_Msk; + tmp |= EIC_NMICTRL_NMISENSE(data); + ((Eic *)hw)->NMICTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMISENSE(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMISENSE(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_NMISENSE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp = (tmp & EIC_NMICTRL_NMISENSE_Msk) >> EIC_NMICTRL_NMISENSE_Pos; + return tmp; +} + +static inline void hri_eic_set_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_reg(const void *const hw) +{ + return ((Eic *)hw)->NMICTRL.reg; +} + +static inline void hri_eic_set_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp = (tmp & EIC_EVCTRL_EXTINTEO(mask)) >> EIC_EVCTRL_EXTINTEO_Pos; + return tmp; +} + +static inline void hri_eic_write_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp &= ~EIC_EVCTRL_EXTINTEO_Msk; + tmp |= EIC_EVCTRL_EXTINTEO(data); + ((Eic *)hw)->EVCTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_EXTINTEO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp = (tmp & EIC_EVCTRL_EXTINTEO_Msk) >> EIC_EVCTRL_EXTINTEO_Pos; + return tmp; +} + +static inline void hri_eic_set_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_reg(const void *const hw) +{ + return ((Eic *)hw)->EVCTRL.reg; +} + +static inline void hri_eic_set_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg |= EIC_ASYNCH_ASYNCH(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->ASYNCH.reg; + tmp = (tmp & EIC_ASYNCH_ASYNCH(mask)) >> EIC_ASYNCH_ASYNCH_Pos; + return tmp; +} + +static inline void hri_eic_write_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->ASYNCH.reg; + tmp &= ~EIC_ASYNCH_ASYNCH_Msk; + tmp |= EIC_ASYNCH_ASYNCH(data); + ((Eic *)hw)->ASYNCH.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg &= ~EIC_ASYNCH_ASYNCH(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg ^= EIC_ASYNCH_ASYNCH(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_ASYNCH_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->ASYNCH.reg; + tmp = (tmp & EIC_ASYNCH_ASYNCH_Msk) >> EIC_ASYNCH_ASYNCH_Pos; + return tmp; +} + +static inline void hri_eic_set_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->ASYNCH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_reg(const void *const hw) +{ + return ((Eic *)hw)->ASYNCH.reg; +} + +static inline void hri_eic_set_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN0) >> EIC_CONFIG_FILTEN0_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN0; + tmp |= value << EIC_CONFIG_FILTEN0_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN1) >> EIC_CONFIG_FILTEN1_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN1; + tmp |= value << EIC_CONFIG_FILTEN1_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN2; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN2) >> EIC_CONFIG_FILTEN2_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN2; + tmp |= value << EIC_CONFIG_FILTEN2_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN2; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN2; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN3; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN3) >> EIC_CONFIG_FILTEN3_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN3; + tmp |= value << EIC_CONFIG_FILTEN3_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN3; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN3; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN4; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN4) >> EIC_CONFIG_FILTEN4_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN4; + tmp |= value << EIC_CONFIG_FILTEN4_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN4; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN4; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN5; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN5) >> EIC_CONFIG_FILTEN5_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN5; + tmp |= value << EIC_CONFIG_FILTEN5_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN5; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN5; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN6; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN6) >> EIC_CONFIG_FILTEN6_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN6; + tmp |= value << EIC_CONFIG_FILTEN6_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN6; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN6; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN7; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN7) >> EIC_CONFIG_FILTEN7_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN7; + tmp |= value << EIC_CONFIG_FILTEN7_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN7; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN7; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE0(mask)) >> EIC_CONFIG_SENSE0_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE0_Msk; + tmp |= EIC_CONFIG_SENSE0(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE0_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE0_Msk) >> EIC_CONFIG_SENSE0_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE1(mask)) >> EIC_CONFIG_SENSE1_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE1_Msk; + tmp |= EIC_CONFIG_SENSE1(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE1_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE1_Msk) >> EIC_CONFIG_SENSE1_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE2(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE2(mask)) >> EIC_CONFIG_SENSE2_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE2_Msk; + tmp |= EIC_CONFIG_SENSE2(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE2(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE2(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE2_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE2_Msk) >> EIC_CONFIG_SENSE2_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE3(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE3(mask)) >> EIC_CONFIG_SENSE3_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE3_Msk; + tmp |= EIC_CONFIG_SENSE3(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE3(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE3(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE3_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE3_Msk) >> EIC_CONFIG_SENSE3_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE4(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE4(mask)) >> EIC_CONFIG_SENSE4_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE4_Msk; + tmp |= EIC_CONFIG_SENSE4(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE4(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE4(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE4_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE4_Msk) >> EIC_CONFIG_SENSE4_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE5(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE5(mask)) >> EIC_CONFIG_SENSE5_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE5_Msk; + tmp |= EIC_CONFIG_SENSE5(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE5(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE5(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE5_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE5_Msk) >> EIC_CONFIG_SENSE5_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE6(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE6(mask)) >> EIC_CONFIG_SENSE6_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE6_Msk; + tmp |= EIC_CONFIG_SENSE6(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE6(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE6(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE6_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE6_Msk) >> EIC_CONFIG_SENSE6_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE7(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE7(mask)) >> EIC_CONFIG_SENSE7_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE7_Msk; + tmp |= EIC_CONFIG_SENSE7(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE7(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE7(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE7_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE7_Msk) >> EIC_CONFIG_SENSE7_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_reg(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_reg(const void *const hw, uint8_t index) +{ + return ((Eic *)hw)->CONFIG[index].reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_EIC_L21_H_INCLUDED */ +#endif /* _SAML21_EIC_COMPONENT_ */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_evsys_l21.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_evsys_l21.h new file mode 100644 index 00000000..e05d1e32 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_evsys_l21.h @@ -0,0 +1,1725 @@ +/** + * \file + * + * \brief SAM EVSYS + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_EVSYS_COMPONENT_ +#ifndef _HRI_EVSYS_L21_H_INCLUDED_ +#define _HRI_EVSYS_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_EVSYS_CRITICAL_SECTIONS) +#define EVSYS_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define EVSYS_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define EVSYS_CRITICAL_SECTION_ENTER() +#define EVSYS_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_evsys_channel_reg_t; +typedef uint32_t hri_evsys_chstatus_reg_t; +typedef uint32_t hri_evsys_intenset_reg_t; +typedef uint32_t hri_evsys_intflag_reg_t; +typedef uint32_t hri_evsys_swevt_reg_t; +typedef uint32_t hri_evsys_user_reg_t; +typedef uint8_t hri_evsys_ctrla_reg_t; + +static inline bool hri_evsys_get_INTFLAG_OVR0_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR0) >> EVSYS_INTFLAG_OVR0_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR0; +} + +static inline bool hri_evsys_get_INTFLAG_OVR1_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR1) >> EVSYS_INTFLAG_OVR1_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR1; +} + +static inline bool hri_evsys_get_INTFLAG_OVR2_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR2) >> EVSYS_INTFLAG_OVR2_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR2; +} + +static inline bool hri_evsys_get_INTFLAG_OVR3_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR3) >> EVSYS_INTFLAG_OVR3_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR3; +} + +static inline bool hri_evsys_get_INTFLAG_OVR4_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR4) >> EVSYS_INTFLAG_OVR4_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR4; +} + +static inline bool hri_evsys_get_INTFLAG_OVR5_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR5) >> EVSYS_INTFLAG_OVR5_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR5; +} + +static inline bool hri_evsys_get_INTFLAG_OVR6_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR6) >> EVSYS_INTFLAG_OVR6_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR6; +} + +static inline bool hri_evsys_get_INTFLAG_OVR7_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR7) >> EVSYS_INTFLAG_OVR7_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR7; +} + +static inline bool hri_evsys_get_INTFLAG_OVR8_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR8) >> EVSYS_INTFLAG_OVR8_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR8_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR8; +} + +static inline bool hri_evsys_get_INTFLAG_OVR9_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR9) >> EVSYS_INTFLAG_OVR9_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR9_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR9; +} + +static inline bool hri_evsys_get_INTFLAG_OVR10_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR10) >> EVSYS_INTFLAG_OVR10_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR10_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR10; +} + +static inline bool hri_evsys_get_INTFLAG_OVR11_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR11) >> EVSYS_INTFLAG_OVR11_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR11_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR11; +} + +static inline bool hri_evsys_get_INTFLAG_EVD0_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD0) >> EVSYS_INTFLAG_EVD0_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD0; +} + +static inline bool hri_evsys_get_INTFLAG_EVD1_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD1) >> EVSYS_INTFLAG_EVD1_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD1; +} + +static inline bool hri_evsys_get_INTFLAG_EVD2_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD2) >> EVSYS_INTFLAG_EVD2_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD2; +} + +static inline bool hri_evsys_get_INTFLAG_EVD3_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD3) >> EVSYS_INTFLAG_EVD3_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD3; +} + +static inline bool hri_evsys_get_INTFLAG_EVD4_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD4) >> EVSYS_INTFLAG_EVD4_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD4; +} + +static inline bool hri_evsys_get_INTFLAG_EVD5_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD5) >> EVSYS_INTFLAG_EVD5_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD5; +} + +static inline bool hri_evsys_get_INTFLAG_EVD6_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD6) >> EVSYS_INTFLAG_EVD6_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD6; +} + +static inline bool hri_evsys_get_INTFLAG_EVD7_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD7) >> EVSYS_INTFLAG_EVD7_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD7; +} + +static inline bool hri_evsys_get_INTFLAG_EVD8_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD8) >> EVSYS_INTFLAG_EVD8_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD8_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD8; +} + +static inline bool hri_evsys_get_INTFLAG_EVD9_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD9) >> EVSYS_INTFLAG_EVD9_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD9_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD9; +} + +static inline bool hri_evsys_get_INTFLAG_EVD10_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD10) >> EVSYS_INTFLAG_EVD10_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD10_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD10; +} + +static inline bool hri_evsys_get_INTFLAG_EVD11_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD11) >> EVSYS_INTFLAG_EVD11_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD11_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD11; +} + +static inline bool hri_evsys_get_interrupt_OVR0_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR0) >> EVSYS_INTFLAG_OVR0_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR0; +} + +static inline bool hri_evsys_get_interrupt_OVR1_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR1) >> EVSYS_INTFLAG_OVR1_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR1; +} + +static inline bool hri_evsys_get_interrupt_OVR2_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR2) >> EVSYS_INTFLAG_OVR2_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR2; +} + +static inline bool hri_evsys_get_interrupt_OVR3_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR3) >> EVSYS_INTFLAG_OVR3_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR3; +} + +static inline bool hri_evsys_get_interrupt_OVR4_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR4) >> EVSYS_INTFLAG_OVR4_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR4; +} + +static inline bool hri_evsys_get_interrupt_OVR5_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR5) >> EVSYS_INTFLAG_OVR5_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR5; +} + +static inline bool hri_evsys_get_interrupt_OVR6_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR6) >> EVSYS_INTFLAG_OVR6_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR6; +} + +static inline bool hri_evsys_get_interrupt_OVR7_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR7) >> EVSYS_INTFLAG_OVR7_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR7; +} + +static inline bool hri_evsys_get_interrupt_OVR8_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR8) >> EVSYS_INTFLAG_OVR8_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR8_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR8; +} + +static inline bool hri_evsys_get_interrupt_OVR9_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR9) >> EVSYS_INTFLAG_OVR9_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR9_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR9; +} + +static inline bool hri_evsys_get_interrupt_OVR10_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR10) >> EVSYS_INTFLAG_OVR10_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR10_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR10; +} + +static inline bool hri_evsys_get_interrupt_OVR11_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR11) >> EVSYS_INTFLAG_OVR11_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR11_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR11; +} + +static inline bool hri_evsys_get_interrupt_EVD0_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD0) >> EVSYS_INTFLAG_EVD0_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD0; +} + +static inline bool hri_evsys_get_interrupt_EVD1_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD1) >> EVSYS_INTFLAG_EVD1_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD1; +} + +static inline bool hri_evsys_get_interrupt_EVD2_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD2) >> EVSYS_INTFLAG_EVD2_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD2; +} + +static inline bool hri_evsys_get_interrupt_EVD3_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD3) >> EVSYS_INTFLAG_EVD3_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD3; +} + +static inline bool hri_evsys_get_interrupt_EVD4_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD4) >> EVSYS_INTFLAG_EVD4_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD4; +} + +static inline bool hri_evsys_get_interrupt_EVD5_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD5) >> EVSYS_INTFLAG_EVD5_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD5; +} + +static inline bool hri_evsys_get_interrupt_EVD6_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD6) >> EVSYS_INTFLAG_EVD6_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD6; +} + +static inline bool hri_evsys_get_interrupt_EVD7_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD7) >> EVSYS_INTFLAG_EVD7_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD7; +} + +static inline bool hri_evsys_get_interrupt_EVD8_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD8) >> EVSYS_INTFLAG_EVD8_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD8_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD8; +} + +static inline bool hri_evsys_get_interrupt_EVD9_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD9) >> EVSYS_INTFLAG_EVD9_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD9_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD9; +} + +static inline bool hri_evsys_get_interrupt_EVD10_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD10) >> EVSYS_INTFLAG_EVD10_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD10_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD10; +} + +static inline bool hri_evsys_get_interrupt_EVD11_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD11) >> EVSYS_INTFLAG_EVD11_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD11_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD11; +} + +static inline hri_evsys_intflag_reg_t hri_evsys_get_INTFLAG_reg(const void *const hw, hri_evsys_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_intflag_reg_t hri_evsys_read_INTFLAG_reg(const void *const hw) +{ + return ((Evsys *)hw)->INTFLAG.reg; +} + +static inline void hri_evsys_clear_INTFLAG_reg(const void *const hw, hri_evsys_intflag_reg_t mask) +{ + ((Evsys *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_evsys_set_INTEN_OVR0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR0; +} + +static inline bool hri_evsys_get_INTEN_OVR0_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR0) >> EVSYS_INTENSET_OVR0_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR0; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR0; + } +} + +static inline void hri_evsys_clear_INTEN_OVR0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR0; +} + +static inline void hri_evsys_set_INTEN_OVR1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR1; +} + +static inline bool hri_evsys_get_INTEN_OVR1_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR1) >> EVSYS_INTENSET_OVR1_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR1; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR1; + } +} + +static inline void hri_evsys_clear_INTEN_OVR1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR1; +} + +static inline void hri_evsys_set_INTEN_OVR2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR2; +} + +static inline bool hri_evsys_get_INTEN_OVR2_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR2) >> EVSYS_INTENSET_OVR2_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR2; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR2; + } +} + +static inline void hri_evsys_clear_INTEN_OVR2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR2; +} + +static inline void hri_evsys_set_INTEN_OVR3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR3; +} + +static inline bool hri_evsys_get_INTEN_OVR3_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR3) >> EVSYS_INTENSET_OVR3_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR3; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR3; + } +} + +static inline void hri_evsys_clear_INTEN_OVR3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR3; +} + +static inline void hri_evsys_set_INTEN_OVR4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR4; +} + +static inline bool hri_evsys_get_INTEN_OVR4_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR4) >> EVSYS_INTENSET_OVR4_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR4; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR4; + } +} + +static inline void hri_evsys_clear_INTEN_OVR4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR4; +} + +static inline void hri_evsys_set_INTEN_OVR5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR5; +} + +static inline bool hri_evsys_get_INTEN_OVR5_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR5) >> EVSYS_INTENSET_OVR5_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR5; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR5; + } +} + +static inline void hri_evsys_clear_INTEN_OVR5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR5; +} + +static inline void hri_evsys_set_INTEN_OVR6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR6; +} + +static inline bool hri_evsys_get_INTEN_OVR6_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR6) >> EVSYS_INTENSET_OVR6_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR6; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR6; + } +} + +static inline void hri_evsys_clear_INTEN_OVR6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR6; +} + +static inline void hri_evsys_set_INTEN_OVR7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR7; +} + +static inline bool hri_evsys_get_INTEN_OVR7_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR7) >> EVSYS_INTENSET_OVR7_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR7; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR7; + } +} + +static inline void hri_evsys_clear_INTEN_OVR7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR7; +} + +static inline void hri_evsys_set_INTEN_OVR8_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR8; +} + +static inline bool hri_evsys_get_INTEN_OVR8_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR8) >> EVSYS_INTENSET_OVR8_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR8_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR8; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR8; + } +} + +static inline void hri_evsys_clear_INTEN_OVR8_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR8; +} + +static inline void hri_evsys_set_INTEN_OVR9_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR9; +} + +static inline bool hri_evsys_get_INTEN_OVR9_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR9) >> EVSYS_INTENSET_OVR9_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR9_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR9; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR9; + } +} + +static inline void hri_evsys_clear_INTEN_OVR9_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR9; +} + +static inline void hri_evsys_set_INTEN_OVR10_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR10; +} + +static inline bool hri_evsys_get_INTEN_OVR10_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR10) >> EVSYS_INTENSET_OVR10_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR10_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR10; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR10; + } +} + +static inline void hri_evsys_clear_INTEN_OVR10_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR10; +} + +static inline void hri_evsys_set_INTEN_OVR11_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR11; +} + +static inline bool hri_evsys_get_INTEN_OVR11_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR11) >> EVSYS_INTENSET_OVR11_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR11_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR11; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR11; + } +} + +static inline void hri_evsys_clear_INTEN_OVR11_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR11; +} + +static inline void hri_evsys_set_INTEN_EVD0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD0; +} + +static inline bool hri_evsys_get_INTEN_EVD0_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD0) >> EVSYS_INTENSET_EVD0_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD0; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD0; + } +} + +static inline void hri_evsys_clear_INTEN_EVD0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD0; +} + +static inline void hri_evsys_set_INTEN_EVD1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD1; +} + +static inline bool hri_evsys_get_INTEN_EVD1_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD1) >> EVSYS_INTENSET_EVD1_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD1; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD1; + } +} + +static inline void hri_evsys_clear_INTEN_EVD1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD1; +} + +static inline void hri_evsys_set_INTEN_EVD2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD2; +} + +static inline bool hri_evsys_get_INTEN_EVD2_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD2) >> EVSYS_INTENSET_EVD2_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD2; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD2; + } +} + +static inline void hri_evsys_clear_INTEN_EVD2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD2; +} + +static inline void hri_evsys_set_INTEN_EVD3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD3; +} + +static inline bool hri_evsys_get_INTEN_EVD3_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD3) >> EVSYS_INTENSET_EVD3_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD3; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD3; + } +} + +static inline void hri_evsys_clear_INTEN_EVD3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD3; +} + +static inline void hri_evsys_set_INTEN_EVD4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD4; +} + +static inline bool hri_evsys_get_INTEN_EVD4_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD4) >> EVSYS_INTENSET_EVD4_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD4; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD4; + } +} + +static inline void hri_evsys_clear_INTEN_EVD4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD4; +} + +static inline void hri_evsys_set_INTEN_EVD5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD5; +} + +static inline bool hri_evsys_get_INTEN_EVD5_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD5) >> EVSYS_INTENSET_EVD5_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD5; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD5; + } +} + +static inline void hri_evsys_clear_INTEN_EVD5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD5; +} + +static inline void hri_evsys_set_INTEN_EVD6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD6; +} + +static inline bool hri_evsys_get_INTEN_EVD6_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD6) >> EVSYS_INTENSET_EVD6_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD6; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD6; + } +} + +static inline void hri_evsys_clear_INTEN_EVD6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD6; +} + +static inline void hri_evsys_set_INTEN_EVD7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD7; +} + +static inline bool hri_evsys_get_INTEN_EVD7_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD7) >> EVSYS_INTENSET_EVD7_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD7; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD7; + } +} + +static inline void hri_evsys_clear_INTEN_EVD7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD7; +} + +static inline void hri_evsys_set_INTEN_EVD8_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD8; +} + +static inline bool hri_evsys_get_INTEN_EVD8_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD8) >> EVSYS_INTENSET_EVD8_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD8_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD8; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD8; + } +} + +static inline void hri_evsys_clear_INTEN_EVD8_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD8; +} + +static inline void hri_evsys_set_INTEN_EVD9_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD9; +} + +static inline bool hri_evsys_get_INTEN_EVD9_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD9) >> EVSYS_INTENSET_EVD9_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD9_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD9; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD9; + } +} + +static inline void hri_evsys_clear_INTEN_EVD9_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD9; +} + +static inline void hri_evsys_set_INTEN_EVD10_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD10; +} + +static inline bool hri_evsys_get_INTEN_EVD10_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD10) >> EVSYS_INTENSET_EVD10_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD10_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD10; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD10; + } +} + +static inline void hri_evsys_clear_INTEN_EVD10_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD10; +} + +static inline void hri_evsys_set_INTEN_EVD11_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD11; +} + +static inline bool hri_evsys_get_INTEN_EVD11_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD11) >> EVSYS_INTENSET_EVD11_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD11_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD11; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD11; + } +} + +static inline void hri_evsys_clear_INTEN_EVD11_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD11; +} + +static inline void hri_evsys_set_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t mask) +{ + ((Evsys *)hw)->INTENSET.reg = mask; +} + +static inline hri_evsys_intenset_reg_t hri_evsys_get_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_intenset_reg_t hri_evsys_read_INTEN_reg(const void *const hw) +{ + return ((Evsys *)hw)->INTENSET.reg; +} + +static inline void hri_evsys_write_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t data) +{ + ((Evsys *)hw)->INTENSET.reg = data; + ((Evsys *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_evsys_clear_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t mask) +{ + ((Evsys *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY0_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY0) >> EVSYS_CHSTATUS_USRRDY0_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY1_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY1) >> EVSYS_CHSTATUS_USRRDY1_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY2_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY2) >> EVSYS_CHSTATUS_USRRDY2_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY3_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY3) >> EVSYS_CHSTATUS_USRRDY3_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY4_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY4) >> EVSYS_CHSTATUS_USRRDY4_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY5_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY5) >> EVSYS_CHSTATUS_USRRDY5_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY6_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY6) >> EVSYS_CHSTATUS_USRRDY6_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY7_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY7) >> EVSYS_CHSTATUS_USRRDY7_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY8_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY8) >> EVSYS_CHSTATUS_USRRDY8_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY9_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY9) >> EVSYS_CHSTATUS_USRRDY9_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY10_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY10) >> EVSYS_CHSTATUS_USRRDY10_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY11_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY11) >> EVSYS_CHSTATUS_USRRDY11_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY0_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY0) >> EVSYS_CHSTATUS_CHBUSY0_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY1_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY1) >> EVSYS_CHSTATUS_CHBUSY1_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY2_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY2) >> EVSYS_CHSTATUS_CHBUSY2_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY3_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY3) >> EVSYS_CHSTATUS_CHBUSY3_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY4_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY4) >> EVSYS_CHSTATUS_CHBUSY4_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY5_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY5) >> EVSYS_CHSTATUS_CHBUSY5_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY6_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY6) >> EVSYS_CHSTATUS_CHBUSY6_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY7_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY7) >> EVSYS_CHSTATUS_CHBUSY7_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY8_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY8) >> EVSYS_CHSTATUS_CHBUSY8_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY9_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY9) >> EVSYS_CHSTATUS_CHBUSY9_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY10_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY10) >> EVSYS_CHSTATUS_CHBUSY10_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY11_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY11) >> EVSYS_CHSTATUS_CHBUSY11_Pos; +} + +static inline hri_evsys_chstatus_reg_t hri_evsys_get_CHSTATUS_reg(const void *const hw, hri_evsys_chstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_chstatus_reg_t hri_evsys_read_CHSTATUS_reg(const void *const hw) +{ + return ((Evsys *)hw)->CHSTATUS.reg; +} + +static inline void hri_evsys_set_CTRLA_SWRST_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg |= EVSYS_CTRLA_SWRST; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->CTRLA.reg; + tmp = (tmp & EVSYS_CTRLA_SWRST) >> EVSYS_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_set_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_ctrla_reg_t hri_evsys_get_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsys_write_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_ctrla_reg_t hri_evsys_read_CTRLA_reg(const void *const hw) +{ + return ((Evsys *)hw)->CTRLA.reg; +} + +static inline void hri_evsys_set_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg |= EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp = (tmp & EVSYS_CHANNEL_RUNSTDBY) >> EVSYS_CHANNEL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp &= ~EVSYS_CHANNEL_RUNSTDBY; + tmp |= value << EVSYS_CHANNEL_RUNSTDBY_Pos; + ((Evsys *)hw)->CHANNEL[index].reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg &= ~EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg ^= EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg |= EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp = (tmp & EVSYS_CHANNEL_ONDEMAND) >> EVSYS_CHANNEL_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp &= ~EVSYS_CHANNEL_ONDEMAND; + tmp |= value << EVSYS_CHANNEL_ONDEMAND_Pos; + ((Evsys *)hw)->CHANNEL[index].reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg &= ~EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg ^= EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg |= EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp = (tmp & EVSYS_CHANNEL_EVGEN(mask)) >> EVSYS_CHANNEL_EVGEN_Pos; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp &= ~EVSYS_CHANNEL_EVGEN_Msk; + tmp |= EVSYS_CHANNEL_EVGEN(data); + ((Evsys *)hw)->CHANNEL[index].reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg &= ~EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg ^= EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp = (tmp & EVSYS_CHANNEL_EVGEN_Msk) >> EVSYS_CHANNEL_EVGEN_Pos; + return tmp; +} + +static inline void hri_evsys_set_CHANNEL_PATH_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg |= EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_PATH_bf(const void *const hw, uint8_t index, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp = (tmp & EVSYS_CHANNEL_PATH(mask)) >> EVSYS_CHANNEL_PATH_Pos; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_PATH_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp &= ~EVSYS_CHANNEL_PATH_Msk; + tmp |= EVSYS_CHANNEL_PATH(data); + ((Evsys *)hw)->CHANNEL[index].reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_PATH_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg &= ~EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_PATH_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg ^= EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_PATH_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp = (tmp & EVSYS_CHANNEL_PATH_Msk) >> EVSYS_CHANNEL_PATH_Pos; + return tmp; +} + +static inline void hri_evsys_set_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg |= EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp = (tmp & EVSYS_CHANNEL_EDGSEL(mask)) >> EVSYS_CHANNEL_EDGSEL_Pos; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp &= ~EVSYS_CHANNEL_EDGSEL_Msk; + tmp |= EVSYS_CHANNEL_EDGSEL(data); + ((Evsys *)hw)->CHANNEL[index].reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg &= ~EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg ^= EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp = (tmp & EVSYS_CHANNEL_EDGSEL_Msk) >> EVSYS_CHANNEL_EDGSEL_Pos; + return tmp; +} + +static inline void hri_evsys_set_CHANNEL_reg(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_reg(const void *const hw, uint8_t index, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_reg(const void *const hw, uint8_t index, hri_evsys_channel_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_reg(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_reg(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_reg(const void *const hw, uint8_t index) +{ + return ((Evsys *)hw)->CHANNEL[index].reg; +} + +static inline void hri_evsys_set_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg |= EVSYS_USER_CHANNEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_get_USER_CHANNEL_bf(const void *const hw, uint8_t index, + hri_evsys_user_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->USER[index].reg; + tmp = (tmp & EVSYS_USER_CHANNEL(mask)) >> EVSYS_USER_CHANNEL_Pos; + return tmp; +} + +static inline void hri_evsys_write_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->USER[index].reg; + tmp &= ~EVSYS_USER_CHANNEL_Msk; + tmp |= EVSYS_USER_CHANNEL(data); + ((Evsys *)hw)->USER[index].reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg &= ~EVSYS_USER_CHANNEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg ^= EVSYS_USER_CHANNEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_read_USER_CHANNEL_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->USER[index].reg; + tmp = (tmp & EVSYS_USER_CHANNEL_Msk) >> EVSYS_USER_CHANNEL_Pos; + return tmp; +} + +static inline void hri_evsys_set_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_get_USER_reg(const void *const hw, uint8_t index, + hri_evsys_user_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->USER[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsys_write_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_read_USER_reg(const void *const hw, uint8_t index) +{ + return ((Evsys *)hw)->USER[index].reg; +} + +static inline void hri_evsys_write_SWEVT_reg(const void *const hw, hri_evsys_swevt_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->SWEVT.reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_EVSYS_L21_H_INCLUDED */ +#endif /* _SAML21_EVSYS_COMPONENT_ */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_gclk_l21.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_gclk_l21.h new file mode 100644 index 00000000..3b5b1e4b --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_gclk_l21.h @@ -0,0 +1,790 @@ +/** + * \file + * + * \brief SAM GCLK + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_GCLK_COMPONENT_ +#ifndef _HRI_GCLK_L21_H_INCLUDED_ +#define _HRI_GCLK_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_GCLK_CRITICAL_SECTIONS) +#define GCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define GCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define GCLK_CRITICAL_SECTION_ENTER() +#define GCLK_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_gclk_genctrl_reg_t; +typedef uint32_t hri_gclk_pchctrl_reg_t; +typedef uint32_t hri_gclk_syncbusy_reg_t; +typedef uint8_t hri_gclk_ctrla_reg_t; + +static inline void hri_gclk_wait_for_sync(const void *const hw, hri_gclk_syncbusy_reg_t reg) +{ + while (((Gclk *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_gclk_is_syncing(const void *const hw, hri_gclk_syncbusy_reg_t reg) +{ + return ((Gclk *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_gclk_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_SWRST) >> GCLK_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL0_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL0) >> GCLK_SYNCBUSY_GENCTRL0_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL1_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL1) >> GCLK_SYNCBUSY_GENCTRL1_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL2_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL2) >> GCLK_SYNCBUSY_GENCTRL2_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL3_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL3) >> GCLK_SYNCBUSY_GENCTRL3_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL4_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL4) >> GCLK_SYNCBUSY_GENCTRL4_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL5_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL5) >> GCLK_SYNCBUSY_GENCTRL5_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL6_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL6) >> GCLK_SYNCBUSY_GENCTRL6_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL7_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL7) >> GCLK_SYNCBUSY_GENCTRL7_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL8_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL8) >> GCLK_SYNCBUSY_GENCTRL8_Pos; +} + +static inline hri_gclk_syncbusy_reg_t hri_gclk_get_SYNCBUSY_reg(const void *const hw, hri_gclk_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gclk_syncbusy_reg_t hri_gclk_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Gclk *)hw)->SYNCBUSY.reg; +} + +static inline void hri_gclk_set_CTRLA_SWRST_bit(const void *const hw) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg |= GCLK_CTRLA_SWRST; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + tmp = ((Gclk *)hw)->CTRLA.reg; + tmp = (tmp & GCLK_CTRLA_SWRST) >> GCLK_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_set_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg |= mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_ctrla_reg_t hri_gclk_get_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + tmp = ((Gclk *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gclk_write_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t data) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg = data; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg &= ~mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg ^= mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_ctrla_reg_t hri_gclk_read_CTRLA_reg(const void *const hw) +{ + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + return ((Gclk *)hw)->CTRLA.reg; +} + +static inline void hri_gclk_set_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_GENEN; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_GENEN) >> GCLK_GENCTRL_GENEN_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_GENEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_GENEN; + tmp |= value << GCLK_GENCTRL_GENEN_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_GENEN; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_GENEN; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_IDC_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_IDC; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_IDC_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_IDC) >> GCLK_GENCTRL_IDC_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_IDC_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_IDC; + tmp |= value << GCLK_GENCTRL_IDC_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_IDC_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_IDC; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_IDC_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_IDC; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_OOV_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OOV; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_OOV_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_OOV) >> GCLK_GENCTRL_OOV_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_OOV_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_OOV; + tmp |= value << GCLK_GENCTRL_OOV_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_OOV_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OOV; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_OOV_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OOV; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_OE_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OE; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_OE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_OE) >> GCLK_GENCTRL_OE_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_OE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_OE; + tmp |= value << GCLK_GENCTRL_OE_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_OE_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OE; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_OE_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OE; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIVSEL; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_DIVSEL) >> GCLK_GENCTRL_DIVSEL_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_DIVSEL; + tmp |= value << GCLK_GENCTRL_DIVSEL_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIVSEL; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIVSEL; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_RUNSTDBY; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_RUNSTDBY) >> GCLK_GENCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_RUNSTDBY; + tmp |= value << GCLK_GENCTRL_RUNSTDBY_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_RUNSTDBY; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_RUNSTDBY; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_SRC(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_SRC_bf(const void *const hw, uint8_t index, + hri_gclk_genctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_SRC(mask)) >> GCLK_GENCTRL_SRC_Pos; + return tmp; +} + +static inline void hri_gclk_write_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_SRC_Msk; + tmp |= GCLK_GENCTRL_SRC(data); + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_SRC(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_SRC(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_SRC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_SRC_Msk) >> GCLK_GENCTRL_SRC_Pos; + return tmp; +} + +static inline void hri_gclk_set_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIV(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_DIV_bf(const void *const hw, uint8_t index, + hri_gclk_genctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_DIV(mask)) >> GCLK_GENCTRL_DIV_Pos; + return tmp; +} + +static inline void hri_gclk_write_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_DIV_Msk; + tmp |= GCLK_GENCTRL_DIV(data); + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIV(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIV(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_DIV_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_DIV_Msk) >> GCLK_GENCTRL_DIV_Pos; + return tmp; +} + +static inline void hri_gclk_set_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_reg(const void *const hw, uint8_t index, + hri_gclk_genctrl_reg_t mask) +{ + uint32_t tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gclk_write_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg = data; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_reg(const void *const hw, uint8_t index) +{ + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + return ((Gclk *)hw)->GENCTRL[index].reg; +} + +static inline void hri_gclk_set_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_CHEN; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp = (tmp & GCLK_PCHCTRL_CHEN) >> GCLK_PCHCTRL_CHEN_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp &= ~GCLK_PCHCTRL_CHEN; + tmp |= value << GCLK_PCHCTRL_CHEN_Pos; + ((Gclk *)hw)->PCHCTRL[index].reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_CHEN; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_CHEN; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_WRTLOCK; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp = (tmp & GCLK_PCHCTRL_WRTLOCK) >> GCLK_PCHCTRL_WRTLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp &= ~GCLK_PCHCTRL_WRTLOCK; + tmp |= value << GCLK_PCHCTRL_WRTLOCK_Pos; + ((Gclk *)hw)->PCHCTRL[index].reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_WRTLOCK; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_WRTLOCK; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_GEN(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, + hri_gclk_pchctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp = (tmp & GCLK_PCHCTRL_GEN(mask)) >> GCLK_PCHCTRL_GEN_Pos; + return tmp; +} + +static inline void hri_gclk_write_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp &= ~GCLK_PCHCTRL_GEN_Msk; + tmp |= GCLK_PCHCTRL_GEN(data); + ((Gclk *)hw)->PCHCTRL[index].reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_GEN(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_GEN(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_GEN_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp = (tmp & GCLK_PCHCTRL_GEN_Msk) >> GCLK_PCHCTRL_GEN_Pos; + return tmp; +} + +static inline void hri_gclk_set_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg |= mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_reg(const void *const hw, uint8_t index, + hri_gclk_pchctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gclk_write_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg = data; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg &= ~mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg ^= mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_reg(const void *const hw, uint8_t index) +{ + return ((Gclk *)hw)->PCHCTRL[index].reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_GCLK_L21_H_INCLUDED */ +#endif /* _SAML21_GCLK_COMPONENT_ */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_l21b.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_l21b.h new file mode 100644 index 00000000..35772521 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_l21b.h @@ -0,0 +1,70 @@ +/** + * \file + * + * \brief SAM L21 HRI top-level header file + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HRI_L21_H_INCLUDED_ +#define _HRI_L21_H_INCLUDED_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#endif /* _HRI_L21_H_INCLUDED_ */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_mclk_l21.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_mclk_l21.h new file mode 100644 index 00000000..a503db1b --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_mclk_l21.h @@ -0,0 +1,2916 @@ +/** + * \file + * + * \brief SAM MCLK + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_MCLK_COMPONENT_ +#ifndef _HRI_MCLK_L21_H_INCLUDED_ +#define _HRI_MCLK_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_MCLK_CRITICAL_SECTIONS) +#define MCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define MCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define MCLK_CRITICAL_SECTION_ENTER() +#define MCLK_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_mclk_ahbmask_reg_t; +typedef uint32_t hri_mclk_apbamask_reg_t; +typedef uint32_t hri_mclk_apbbmask_reg_t; +typedef uint32_t hri_mclk_apbcmask_reg_t; +typedef uint32_t hri_mclk_apbdmask_reg_t; +typedef uint32_t hri_mclk_apbemask_reg_t; +typedef uint8_t hri_mclk_bupdiv_reg_t; +typedef uint8_t hri_mclk_cpudiv_reg_t; +typedef uint8_t hri_mclk_ctrla_reg_t; +typedef uint8_t hri_mclk_intenset_reg_t; +typedef uint8_t hri_mclk_intflag_reg_t; +typedef uint8_t hri_mclk_lpdiv_reg_t; + +static inline bool hri_mclk_get_INTFLAG_CKRDY_bit(const void *const hw) +{ + return (((Mclk *)hw)->INTFLAG.reg & MCLK_INTFLAG_CKRDY) >> MCLK_INTFLAG_CKRDY_Pos; +} + +static inline void hri_mclk_clear_INTFLAG_CKRDY_bit(const void *const hw) +{ + ((Mclk *)hw)->INTFLAG.reg = MCLK_INTFLAG_CKRDY; +} + +static inline bool hri_mclk_get_interrupt_CKRDY_bit(const void *const hw) +{ + return (((Mclk *)hw)->INTFLAG.reg & MCLK_INTFLAG_CKRDY) >> MCLK_INTFLAG_CKRDY_Pos; +} + +static inline void hri_mclk_clear_interrupt_CKRDY_bit(const void *const hw) +{ + ((Mclk *)hw)->INTFLAG.reg = MCLK_INTFLAG_CKRDY; +} + +static inline hri_mclk_intflag_reg_t hri_mclk_get_INTFLAG_reg(const void *const hw, hri_mclk_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mclk_intflag_reg_t hri_mclk_read_INTFLAG_reg(const void *const hw) +{ + return ((Mclk *)hw)->INTFLAG.reg; +} + +static inline void hri_mclk_clear_INTFLAG_reg(const void *const hw, hri_mclk_intflag_reg_t mask) +{ + ((Mclk *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_mclk_set_INTEN_CKRDY_bit(const void *const hw) +{ + ((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY; +} + +static inline bool hri_mclk_get_INTEN_CKRDY_bit(const void *const hw) +{ + return (((Mclk *)hw)->INTENSET.reg & MCLK_INTENSET_CKRDY) >> MCLK_INTENSET_CKRDY_Pos; +} + +static inline void hri_mclk_write_INTEN_CKRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY; + } else { + ((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY; + } +} + +static inline void hri_mclk_clear_INTEN_CKRDY_bit(const void *const hw) +{ + ((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY; +} + +static inline void hri_mclk_set_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask) +{ + ((Mclk *)hw)->INTENSET.reg = mask; +} + +static inline hri_mclk_intenset_reg_t hri_mclk_get_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mclk_intenset_reg_t hri_mclk_read_INTEN_reg(const void *const hw) +{ + return ((Mclk *)hw)->INTENSET.reg; +} + +static inline void hri_mclk_write_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t data) +{ + ((Mclk *)hw)->INTENSET.reg = data; + ((Mclk *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_mclk_clear_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask) +{ + ((Mclk *)hw)->INTENCLR.reg = mask; +} + +static inline void hri_mclk_set_CTRLA_reg(const void *const hw, hri_mclk_ctrla_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CTRLA.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_ctrla_reg_t hri_mclk_get_CTRLA_reg(const void *const hw, hri_mclk_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_CTRLA_reg(const void *const hw, hri_mclk_ctrla_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CTRLA.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_CTRLA_reg(const void *const hw, hri_mclk_ctrla_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CTRLA.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_CTRLA_reg(const void *const hw, hri_mclk_ctrla_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CTRLA.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_ctrla_reg_t hri_mclk_read_CTRLA_reg(const void *const hw) +{ + return ((Mclk *)hw)->CTRLA.reg; +} + +static inline void hri_mclk_set_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg |= MCLK_CPUDIV_CPUDIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_cpudiv_reg_t hri_mclk_get_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->CPUDIV.reg; + tmp = (tmp & MCLK_CPUDIV_CPUDIV(mask)) >> MCLK_CPUDIV_CPUDIV_Pos; + return tmp; +} + +static inline void hri_mclk_write_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t data) +{ + uint8_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->CPUDIV.reg; + tmp &= ~MCLK_CPUDIV_CPUDIV_Msk; + tmp |= MCLK_CPUDIV_CPUDIV(data); + ((Mclk *)hw)->CPUDIV.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg &= ~MCLK_CPUDIV_CPUDIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg ^= MCLK_CPUDIV_CPUDIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_cpudiv_reg_t hri_mclk_read_CPUDIV_CPUDIV_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->CPUDIV.reg; + tmp = (tmp & MCLK_CPUDIV_CPUDIV_Msk) >> MCLK_CPUDIV_CPUDIV_Pos; + return tmp; +} + +static inline void hri_mclk_set_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_cpudiv_reg_t hri_mclk_get_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->CPUDIV.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_cpudiv_reg_t hri_mclk_read_CPUDIV_reg(const void *const hw) +{ + return ((Mclk *)hw)->CPUDIV.reg; +} + +static inline void hri_mclk_set_LPDIV_LPDIV_bf(const void *const hw, hri_mclk_lpdiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->LPDIV.reg |= MCLK_LPDIV_LPDIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_lpdiv_reg_t hri_mclk_get_LPDIV_LPDIV_bf(const void *const hw, hri_mclk_lpdiv_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->LPDIV.reg; + tmp = (tmp & MCLK_LPDIV_LPDIV(mask)) >> MCLK_LPDIV_LPDIV_Pos; + return tmp; +} + +static inline void hri_mclk_write_LPDIV_LPDIV_bf(const void *const hw, hri_mclk_lpdiv_reg_t data) +{ + uint8_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->LPDIV.reg; + tmp &= ~MCLK_LPDIV_LPDIV_Msk; + tmp |= MCLK_LPDIV_LPDIV(data); + ((Mclk *)hw)->LPDIV.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_LPDIV_LPDIV_bf(const void *const hw, hri_mclk_lpdiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->LPDIV.reg &= ~MCLK_LPDIV_LPDIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_LPDIV_LPDIV_bf(const void *const hw, hri_mclk_lpdiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->LPDIV.reg ^= MCLK_LPDIV_LPDIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_lpdiv_reg_t hri_mclk_read_LPDIV_LPDIV_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->LPDIV.reg; + tmp = (tmp & MCLK_LPDIV_LPDIV_Msk) >> MCLK_LPDIV_LPDIV_Pos; + return tmp; +} + +static inline void hri_mclk_set_LPDIV_reg(const void *const hw, hri_mclk_lpdiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->LPDIV.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_lpdiv_reg_t hri_mclk_get_LPDIV_reg(const void *const hw, hri_mclk_lpdiv_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->LPDIV.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_LPDIV_reg(const void *const hw, hri_mclk_lpdiv_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->LPDIV.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_LPDIV_reg(const void *const hw, hri_mclk_lpdiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->LPDIV.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_LPDIV_reg(const void *const hw, hri_mclk_lpdiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->LPDIV.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_lpdiv_reg_t hri_mclk_read_LPDIV_reg(const void *const hw) +{ + return ((Mclk *)hw)->LPDIV.reg; +} + +static inline void hri_mclk_set_BUPDIV_BUPDIV_bf(const void *const hw, hri_mclk_bupdiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->BUPDIV.reg |= MCLK_BUPDIV_BUPDIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_bupdiv_reg_t hri_mclk_get_BUPDIV_BUPDIV_bf(const void *const hw, hri_mclk_bupdiv_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->BUPDIV.reg; + tmp = (tmp & MCLK_BUPDIV_BUPDIV(mask)) >> MCLK_BUPDIV_BUPDIV_Pos; + return tmp; +} + +static inline void hri_mclk_write_BUPDIV_BUPDIV_bf(const void *const hw, hri_mclk_bupdiv_reg_t data) +{ + uint8_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->BUPDIV.reg; + tmp &= ~MCLK_BUPDIV_BUPDIV_Msk; + tmp |= MCLK_BUPDIV_BUPDIV(data); + ((Mclk *)hw)->BUPDIV.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_BUPDIV_BUPDIV_bf(const void *const hw, hri_mclk_bupdiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->BUPDIV.reg &= ~MCLK_BUPDIV_BUPDIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_BUPDIV_BUPDIV_bf(const void *const hw, hri_mclk_bupdiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->BUPDIV.reg ^= MCLK_BUPDIV_BUPDIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_bupdiv_reg_t hri_mclk_read_BUPDIV_BUPDIV_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->BUPDIV.reg; + tmp = (tmp & MCLK_BUPDIV_BUPDIV_Msk) >> MCLK_BUPDIV_BUPDIV_Pos; + return tmp; +} + +static inline void hri_mclk_set_BUPDIV_reg(const void *const hw, hri_mclk_bupdiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->BUPDIV.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_bupdiv_reg_t hri_mclk_get_BUPDIV_reg(const void *const hw, hri_mclk_bupdiv_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->BUPDIV.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_BUPDIV_reg(const void *const hw, hri_mclk_bupdiv_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->BUPDIV.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_BUPDIV_reg(const void *const hw, hri_mclk_bupdiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->BUPDIV.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_BUPDIV_reg(const void *const hw, hri_mclk_bupdiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->BUPDIV.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_bupdiv_reg_t hri_mclk_read_BUPDIV_reg(const void *const hw) +{ + return ((Mclk *)hw)->BUPDIV.reg; +} + +static inline void hri_mclk_set_AHBMASK_HPB0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HPB0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HPB0) >> MCLK_AHBMASK_HPB0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HPB0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HPB0; + tmp |= value << MCLK_AHBMASK_HPB0_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HPB0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HPB0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HPB1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HPB1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HPB1) >> MCLK_AHBMASK_HPB1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HPB1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HPB1; + tmp |= value << MCLK_AHBMASK_HPB1_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HPB1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HPB1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HPB2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HPB2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HPB2) >> MCLK_AHBMASK_HPB2_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HPB2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HPB2; + tmp |= value << MCLK_AHBMASK_HPB2_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HPB2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HPB2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HPB3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HPB3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HPB3) >> MCLK_AHBMASK_HPB3_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HPB3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HPB3; + tmp |= value << MCLK_AHBMASK_HPB3_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HPB3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HPB3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HPB4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HPB4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HPB4) >> MCLK_AHBMASK_HPB4_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HPB4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HPB4; + tmp |= value << MCLK_AHBMASK_HPB4_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HPB4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HPB4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_DSU_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_DSU) >> MCLK_AHBMASK_DSU_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_DSU_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_DSU; + tmp |= value << MCLK_AHBMASK_DSU_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_NVMCTRL) >> MCLK_AHBMASK_NVMCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_NVMCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_NVMCTRL; + tmp |= value << MCLK_AHBMASK_NVMCTRL_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HSRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HSRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HSRAM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HSRAM) >> MCLK_AHBMASK_HSRAM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HSRAM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HSRAM; + tmp |= value << MCLK_AHBMASK_HSRAM_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HSRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HSRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HSRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HSRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_LPRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_LPRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_LPRAM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_LPRAM) >> MCLK_AHBMASK_LPRAM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_LPRAM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_LPRAM; + tmp |= value << MCLK_AHBMASK_LPRAM_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_LPRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_LPRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_LPRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_LPRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_DMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_DMAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_DMAC) >> MCLK_AHBMASK_DMAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_DMAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_DMAC; + tmp |= value << MCLK_AHBMASK_DMAC_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_DMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_DMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_USB_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_USB) >> MCLK_AHBMASK_USB_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_USB_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_USB; + tmp |= value << MCLK_AHBMASK_USB_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_PAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_PAC) >> MCLK_AHBMASK_PAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_PAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_PAC; + tmp |= value << MCLK_AHBMASK_PAC_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL_PICACHU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_NVMCTRL_PICACHU) >> MCLK_AHBMASK_NVMCTRL_PICACHU_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_NVMCTRL_PICACHU; + tmp |= value << MCLK_AHBMASK_NVMCTRL_PICACHU_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL_PICACHU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL_PICACHU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_L2HBRIDGES_H_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_L2HBRIDGES_H; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_L2HBRIDGES_H_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_L2HBRIDGES_H) >> MCLK_AHBMASK_L2HBRIDGES_H_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_L2HBRIDGES_H_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_L2HBRIDGES_H; + tmp |= value << MCLK_AHBMASK_L2HBRIDGES_H_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_L2HBRIDGES_H_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_L2HBRIDGES_H; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_L2HBRIDGES_H_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_L2HBRIDGES_H; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_H2LBRIDGES_H_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_H2LBRIDGES_H; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_H2LBRIDGES_H_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_H2LBRIDGES_H) >> MCLK_AHBMASK_H2LBRIDGES_H_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_H2LBRIDGES_H_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_H2LBRIDGES_H; + tmp |= value << MCLK_AHBMASK_H2LBRIDGES_H_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_H2LBRIDGES_H_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_H2LBRIDGES_H; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_H2LBRIDGES_H_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_H2LBRIDGES_H; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HSRAM_AHBSETUPKEEPER_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HSRAM_AHBSETUPKEEPER; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HSRAM_AHBSETUPKEEPER_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HSRAM_AHBSETUPKEEPER) >> MCLK_AHBMASK_HSRAM_AHBSETUPKEEPER_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HSRAM_AHBSETUPKEEPER_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HSRAM_AHBSETUPKEEPER; + tmp |= value << MCLK_AHBMASK_HSRAM_AHBSETUPKEEPER_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HSRAM_AHBSETUPKEEPER_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HSRAM_AHBSETUPKEEPER; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HSRAM_AHBSETUPKEEPER_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HSRAM_AHBSETUPKEEPER; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HSRAM_HMATRIXLP2HMCRAMCHSBRIDGE_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HSRAM_HMATRIXLP2HMCRAMCHSBRIDGE; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HSRAM_HMATRIXLP2HMCRAMCHSBRIDGE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HSRAM_HMATRIXLP2HMCRAMCHSBRIDGE) >> MCLK_AHBMASK_HSRAM_HMATRIXLP2HMCRAMCHSBRIDGE_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HSRAM_HMATRIXLP2HMCRAMCHSBRIDGE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HSRAM_HMATRIXLP2HMCRAMCHSBRIDGE; + tmp |= value << MCLK_AHBMASK_HSRAM_HMATRIXLP2HMCRAMCHSBRIDGE_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HSRAM_HMATRIXLP2HMCRAMCHSBRIDGE_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HSRAM_HMATRIXLP2HMCRAMCHSBRIDGE; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HSRAM_HMATRIXLP2HMCRAMCHSBRIDGE_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HSRAM_HMATRIXLP2HMCRAMCHSBRIDGE; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_ahbmask_reg_t hri_mclk_get_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_ahbmask_reg_t hri_mclk_read_AHBMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->AHBMASK.reg; +} + +static inline void hri_mclk_set_APBAMASK_PM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_PM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_PM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_PM) >> MCLK_APBAMASK_PM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_PM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_PM; + tmp |= value << MCLK_APBAMASK_PM_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_PM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_PM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_PM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_PM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_MCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_MCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_MCLK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_MCLK) >> MCLK_APBAMASK_MCLK_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_MCLK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_MCLK; + tmp |= value << MCLK_APBAMASK_MCLK_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_MCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_MCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_MCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_MCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_RSTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RSTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_RSTC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_RSTC) >> MCLK_APBAMASK_RSTC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_RSTC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_RSTC; + tmp |= value << MCLK_APBAMASK_RSTC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_RSTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_RSTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_RSTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_RSTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_OSCCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_OSCCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_OSCCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_OSCCTRL) >> MCLK_APBAMASK_OSCCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_OSCCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_OSCCTRL; + tmp |= value << MCLK_APBAMASK_OSCCTRL_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_OSCCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_OSCCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_OSCCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_OSCCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_OSC32KCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_OSC32KCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_OSC32KCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_OSC32KCTRL) >> MCLK_APBAMASK_OSC32KCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_OSC32KCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_OSC32KCTRL; + tmp |= value << MCLK_APBAMASK_OSC32KCTRL_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_OSC32KCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_OSC32KCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_OSC32KCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_OSC32KCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_SUPC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SUPC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_SUPC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_SUPC) >> MCLK_APBAMASK_SUPC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_SUPC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_SUPC; + tmp |= value << MCLK_APBAMASK_SUPC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_SUPC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SUPC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_SUPC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SUPC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_GCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_GCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_GCLK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_GCLK) >> MCLK_APBAMASK_GCLK_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_GCLK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_GCLK; + tmp |= value << MCLK_APBAMASK_GCLK_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_GCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_GCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_GCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_GCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_WDT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_WDT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_WDT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_WDT) >> MCLK_APBAMASK_WDT_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_WDT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_WDT; + tmp |= value << MCLK_APBAMASK_WDT_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_WDT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_WDT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_WDT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_WDT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_RTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_RTC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_RTC) >> MCLK_APBAMASK_RTC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_RTC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_RTC; + tmp |= value << MCLK_APBAMASK_RTC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_RTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_RTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_RTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_RTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_EIC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_EIC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_EIC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_EIC) >> MCLK_APBAMASK_EIC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_EIC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_EIC; + tmp |= value << MCLK_APBAMASK_EIC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_EIC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_EIC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_EIC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_EIC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_PORT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_PORT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_PORT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_PORT) >> MCLK_APBAMASK_PORT_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_PORT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_PORT; + tmp |= value << MCLK_APBAMASK_PORT_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_PORT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_PORT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_PORT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_PORT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbamask_reg_t hri_mclk_get_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbamask_reg_t hri_mclk_read_APBAMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->APBAMASK.reg; +} + +static inline void hri_mclk_set_APBBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_USB_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_USB) >> MCLK_APBBMASK_USB_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_USB_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_USB; + tmp |= value << MCLK_APBBMASK_USB_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_DSU_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_DSU) >> MCLK_APBBMASK_DSU_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_DSU_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_DSU; + tmp |= value << MCLK_APBBMASK_DSU_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_NVMCTRL) >> MCLK_APBBMASK_NVMCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_NVMCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_NVMCTRL; + tmp |= value << MCLK_APBBMASK_NVMCTRL_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbbmask_reg_t hri_mclk_get_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbbmask_reg_t hri_mclk_read_APBBMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->APBBMASK.reg; +} + +static inline void hri_mclk_set_APBCMASK_SERCOM0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_SERCOM0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_SERCOM0) >> MCLK_APBCMASK_SERCOM0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_SERCOM0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_SERCOM0; + tmp |= value << MCLK_APBCMASK_SERCOM0_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_SERCOM0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_SERCOM0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_SERCOM1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_SERCOM1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_SERCOM1) >> MCLK_APBCMASK_SERCOM1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_SERCOM1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_SERCOM1; + tmp |= value << MCLK_APBCMASK_SERCOM1_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_SERCOM1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_SERCOM1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_SERCOM2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_SERCOM2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_SERCOM2) >> MCLK_APBCMASK_SERCOM2_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_SERCOM2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_SERCOM2; + tmp |= value << MCLK_APBCMASK_SERCOM2_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_SERCOM2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_SERCOM2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_SERCOM3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_SERCOM3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_SERCOM3) >> MCLK_APBCMASK_SERCOM3_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_SERCOM3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_SERCOM3; + tmp |= value << MCLK_APBCMASK_SERCOM3_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_SERCOM3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_SERCOM3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_SERCOM4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_SERCOM4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_SERCOM4) >> MCLK_APBCMASK_SERCOM4_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_SERCOM4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_SERCOM4; + tmp |= value << MCLK_APBCMASK_SERCOM4_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_SERCOM4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_SERCOM4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TCC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TCC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TCC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TCC0) >> MCLK_APBCMASK_TCC0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TCC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TCC0; + tmp |= value << MCLK_APBCMASK_TCC0_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TCC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TCC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TCC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TCC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TCC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TCC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TCC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TCC1) >> MCLK_APBCMASK_TCC1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TCC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TCC1; + tmp |= value << MCLK_APBCMASK_TCC1_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TCC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TCC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TCC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TCC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TCC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TCC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TCC2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TCC2) >> MCLK_APBCMASK_TCC2_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TCC2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TCC2; + tmp |= value << MCLK_APBCMASK_TCC2_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TCC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TCC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TCC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TCC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TC0) >> MCLK_APBCMASK_TC0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TC0; + tmp |= value << MCLK_APBCMASK_TC0_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TC1) >> MCLK_APBCMASK_TC1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TC1; + tmp |= value << MCLK_APBCMASK_TC1_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TC2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TC2) >> MCLK_APBCMASK_TC2_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TC2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TC2; + tmp |= value << MCLK_APBCMASK_TC2_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TC3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TC3) >> MCLK_APBCMASK_TC3_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TC3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TC3; + tmp |= value << MCLK_APBCMASK_TC3_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_DAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_DAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_DAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_DAC) >> MCLK_APBCMASK_DAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_DAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_DAC; + tmp |= value << MCLK_APBCMASK_DAC_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_DAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_DAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_DAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_DAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_AES_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_AES; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_AES_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_AES) >> MCLK_APBCMASK_AES_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_AES_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_AES; + tmp |= value << MCLK_APBCMASK_AES_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_AES_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_AES; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_AES_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_AES; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TRNG_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TRNG; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TRNG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TRNG) >> MCLK_APBCMASK_TRNG_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TRNG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TRNG; + tmp |= value << MCLK_APBCMASK_TRNG_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TRNG_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TRNG; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TRNG_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TRNG; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbcmask_reg_t hri_mclk_get_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbcmask_reg_t hri_mclk_read_APBCMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->APBCMASK.reg; +} + +static inline void hri_mclk_set_APBDMASK_EVSYS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_EVSYS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_EVSYS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_EVSYS) >> MCLK_APBDMASK_EVSYS_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_EVSYS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_EVSYS; + tmp |= value << MCLK_APBDMASK_EVSYS_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_EVSYS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_EVSYS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_EVSYS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_EVSYS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_SERCOM5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_SERCOM5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_SERCOM5) >> MCLK_APBDMASK_SERCOM5_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_SERCOM5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_SERCOM5; + tmp |= value << MCLK_APBDMASK_SERCOM5_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_SERCOM5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_SERCOM5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_TC4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_TC4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_TC4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_TC4) >> MCLK_APBDMASK_TC4_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_TC4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_TC4; + tmp |= value << MCLK_APBDMASK_TC4_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_TC4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_TC4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_TC4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_TC4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_ADC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_ADC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_ADC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_ADC) >> MCLK_APBDMASK_ADC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_ADC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_ADC; + tmp |= value << MCLK_APBDMASK_ADC_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_ADC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_ADC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_ADC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_ADC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_AC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_AC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_AC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_AC) >> MCLK_APBDMASK_AC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_AC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_AC; + tmp |= value << MCLK_APBDMASK_AC_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_AC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_AC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_AC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_AC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_PTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_PTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_PTC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_PTC) >> MCLK_APBDMASK_PTC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_PTC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_PTC; + tmp |= value << MCLK_APBDMASK_PTC_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_PTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_PTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_PTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_PTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_OPAMP_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_OPAMP; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_OPAMP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_OPAMP) >> MCLK_APBDMASK_OPAMP_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_OPAMP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_OPAMP; + tmp |= value << MCLK_APBDMASK_OPAMP_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_OPAMP_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_OPAMP; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_OPAMP_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_OPAMP; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_CCL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_CCL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_CCL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_CCL) >> MCLK_APBDMASK_CCL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_CCL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_CCL; + tmp |= value << MCLK_APBDMASK_CCL_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_CCL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_CCL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_CCL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_CCL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbdmask_reg_t hri_mclk_get_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbdmask_reg_t hri_mclk_read_APBDMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->APBDMASK.reg; +} + +static inline void hri_mclk_set_APBEMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBEMASK.reg |= MCLK_APBEMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBEMASK_PAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBEMASK.reg; + tmp = (tmp & MCLK_APBEMASK_PAC) >> MCLK_APBEMASK_PAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBEMASK_PAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBEMASK.reg; + tmp &= ~MCLK_APBEMASK_PAC; + tmp |= value << MCLK_APBEMASK_PAC_Pos; + ((Mclk *)hw)->APBEMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBEMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBEMASK.reg &= ~MCLK_APBEMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBEMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBEMASK.reg ^= MCLK_APBEMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBEMASK_reg(const void *const hw, hri_mclk_apbemask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBEMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbemask_reg_t hri_mclk_get_APBEMASK_reg(const void *const hw, hri_mclk_apbemask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBEMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_APBEMASK_reg(const void *const hw, hri_mclk_apbemask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBEMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBEMASK_reg(const void *const hw, hri_mclk_apbemask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBEMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBEMASK_reg(const void *const hw, hri_mclk_apbemask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBEMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbemask_reg_t hri_mclk_read_APBEMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->APBEMASK.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_MCLK_L21_H_INCLUDED */ +#endif /* _SAML21_MCLK_COMPONENT_ */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_mtb_l21.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_mtb_l21.h new file mode 100644 index 00000000..7d04b825 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_mtb_l21.h @@ -0,0 +1,551 @@ +/** + * \file + * + * \brief SAM MTB + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_MTB_COMPONENT_ +#ifndef _HRI_MTB_L21_H_INCLUDED_ +#define _HRI_MTB_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_MTB_CRITICAL_SECTIONS) +#define MTB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define MTB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define MTB_CRITICAL_SECTION_ENTER() +#define MTB_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_mtb_authstatus_reg_t; +typedef uint32_t hri_mtb_base_reg_t; +typedef uint32_t hri_mtb_cid0_reg_t; +typedef uint32_t hri_mtb_cid1_reg_t; +typedef uint32_t hri_mtb_cid2_reg_t; +typedef uint32_t hri_mtb_cid3_reg_t; +typedef uint32_t hri_mtb_claimset_reg_t; +typedef uint32_t hri_mtb_devarch_reg_t; +typedef uint32_t hri_mtb_devid_reg_t; +typedef uint32_t hri_mtb_devtype_reg_t; +typedef uint32_t hri_mtb_flow_reg_t; +typedef uint32_t hri_mtb_itctrl_reg_t; +typedef uint32_t hri_mtb_lockaccess_reg_t; +typedef uint32_t hri_mtb_lockstatus_reg_t; +typedef uint32_t hri_mtb_master_reg_t; +typedef uint32_t hri_mtb_pid0_reg_t; +typedef uint32_t hri_mtb_pid1_reg_t; +typedef uint32_t hri_mtb_pid2_reg_t; +typedef uint32_t hri_mtb_pid3_reg_t; +typedef uint32_t hri_mtb_pid4_reg_t; +typedef uint32_t hri_mtb_pid5_reg_t; +typedef uint32_t hri_mtb_pid6_reg_t; +typedef uint32_t hri_mtb_pid7_reg_t; +typedef uint32_t hri_mtb_position_reg_t; + +static inline void hri_mtb_set_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t mask) +{ + ((Mtb *)hw)->CLAIMSET.reg = mask; +} + +static inline hri_mtb_claimset_reg_t hri_mtb_get_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->CLAIMSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_claimset_reg_t hri_mtb_read_CLAIM_reg(const void *const hw) +{ + return ((Mtb *)hw)->CLAIMSET.reg; +} + +static inline void hri_mtb_write_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t data) +{ + ((Mtb *)hw)->CLAIMSET.reg = data; + ((Mtb *)hw)->CLAIMCLR.reg = ~data; +} + +static inline void hri_mtb_clear_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t mask) +{ + ((Mtb *)hw)->CLAIMCLR.reg = mask; +} + +static inline hri_mtb_base_reg_t hri_mtb_get_BASE_reg(const void *const hw, hri_mtb_base_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->BASE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_base_reg_t hri_mtb_read_BASE_reg(const void *const hw) +{ + return ((Mtb *)hw)->BASE.reg; +} + +static inline hri_mtb_lockstatus_reg_t hri_mtb_get_LOCKSTATUS_reg(const void *const hw, hri_mtb_lockstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->LOCKSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_lockstatus_reg_t hri_mtb_read_LOCKSTATUS_reg(const void *const hw) +{ + return ((Mtb *)hw)->LOCKSTATUS.reg; +} + +static inline hri_mtb_authstatus_reg_t hri_mtb_get_AUTHSTATUS_reg(const void *const hw, hri_mtb_authstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->AUTHSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_authstatus_reg_t hri_mtb_read_AUTHSTATUS_reg(const void *const hw) +{ + return ((Mtb *)hw)->AUTHSTATUS.reg; +} + +static inline hri_mtb_devarch_reg_t hri_mtb_get_DEVARCH_reg(const void *const hw, hri_mtb_devarch_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->DEVARCH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_devarch_reg_t hri_mtb_read_DEVARCH_reg(const void *const hw) +{ + return ((Mtb *)hw)->DEVARCH.reg; +} + +static inline hri_mtb_devid_reg_t hri_mtb_get_DEVID_reg(const void *const hw, hri_mtb_devid_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->DEVID.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_devid_reg_t hri_mtb_read_DEVID_reg(const void *const hw) +{ + return ((Mtb *)hw)->DEVID.reg; +} + +static inline hri_mtb_devtype_reg_t hri_mtb_get_DEVTYPE_reg(const void *const hw, hri_mtb_devtype_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->DEVTYPE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_devtype_reg_t hri_mtb_read_DEVTYPE_reg(const void *const hw) +{ + return ((Mtb *)hw)->DEVTYPE.reg; +} + +static inline hri_mtb_pid4_reg_t hri_mtb_get_PID4_reg(const void *const hw, hri_mtb_pid4_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID4.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid4_reg_t hri_mtb_read_PID4_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID4.reg; +} + +static inline hri_mtb_pid5_reg_t hri_mtb_get_PID5_reg(const void *const hw, hri_mtb_pid5_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID5.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid5_reg_t hri_mtb_read_PID5_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID5.reg; +} + +static inline hri_mtb_pid6_reg_t hri_mtb_get_PID6_reg(const void *const hw, hri_mtb_pid6_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID6.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid6_reg_t hri_mtb_read_PID6_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID6.reg; +} + +static inline hri_mtb_pid7_reg_t hri_mtb_get_PID7_reg(const void *const hw, hri_mtb_pid7_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID7.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid7_reg_t hri_mtb_read_PID7_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID7.reg; +} + +static inline hri_mtb_pid0_reg_t hri_mtb_get_PID0_reg(const void *const hw, hri_mtb_pid0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid0_reg_t hri_mtb_read_PID0_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID0.reg; +} + +static inline hri_mtb_pid1_reg_t hri_mtb_get_PID1_reg(const void *const hw, hri_mtb_pid1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid1_reg_t hri_mtb_read_PID1_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID1.reg; +} + +static inline hri_mtb_pid2_reg_t hri_mtb_get_PID2_reg(const void *const hw, hri_mtb_pid2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID2.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid2_reg_t hri_mtb_read_PID2_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID2.reg; +} + +static inline hri_mtb_pid3_reg_t hri_mtb_get_PID3_reg(const void *const hw, hri_mtb_pid3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID3.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid3_reg_t hri_mtb_read_PID3_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID3.reg; +} + +static inline hri_mtb_cid0_reg_t hri_mtb_get_CID0_reg(const void *const hw, hri_mtb_cid0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->CID0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_cid0_reg_t hri_mtb_read_CID0_reg(const void *const hw) +{ + return ((Mtb *)hw)->CID0.reg; +} + +static inline hri_mtb_cid1_reg_t hri_mtb_get_CID1_reg(const void *const hw, hri_mtb_cid1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->CID1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_cid1_reg_t hri_mtb_read_CID1_reg(const void *const hw) +{ + return ((Mtb *)hw)->CID1.reg; +} + +static inline hri_mtb_cid2_reg_t hri_mtb_get_CID2_reg(const void *const hw, hri_mtb_cid2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->CID2.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_cid2_reg_t hri_mtb_read_CID2_reg(const void *const hw) +{ + return ((Mtb *)hw)->CID2.reg; +} + +static inline hri_mtb_cid3_reg_t hri_mtb_get_CID3_reg(const void *const hw, hri_mtb_cid3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->CID3.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_cid3_reg_t hri_mtb_read_CID3_reg(const void *const hw) +{ + return ((Mtb *)hw)->CID3.reg; +} + +static inline void hri_mtb_set_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->POSITION.reg |= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_position_reg_t hri_mtb_get_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->POSITION.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mtb_write_POSITION_reg(const void *const hw, hri_mtb_position_reg_t data) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->POSITION.reg = data; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_clear_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->POSITION.reg &= ~mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_toggle_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->POSITION.reg ^= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_position_reg_t hri_mtb_read_POSITION_reg(const void *const hw) +{ + return ((Mtb *)hw)->POSITION.reg; +} + +static inline void hri_mtb_set_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->MASTER.reg |= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_master_reg_t hri_mtb_get_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->MASTER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mtb_write_MASTER_reg(const void *const hw, hri_mtb_master_reg_t data) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->MASTER.reg = data; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_clear_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->MASTER.reg &= ~mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_toggle_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->MASTER.reg ^= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_master_reg_t hri_mtb_read_MASTER_reg(const void *const hw) +{ + return ((Mtb *)hw)->MASTER.reg; +} + +static inline void hri_mtb_set_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->FLOW.reg |= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_flow_reg_t hri_mtb_get_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->FLOW.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mtb_write_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t data) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->FLOW.reg = data; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_clear_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->FLOW.reg &= ~mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_toggle_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->FLOW.reg ^= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_flow_reg_t hri_mtb_read_FLOW_reg(const void *const hw) +{ + return ((Mtb *)hw)->FLOW.reg; +} + +static inline void hri_mtb_set_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->ITCTRL.reg |= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_itctrl_reg_t hri_mtb_get_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->ITCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mtb_write_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t data) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->ITCTRL.reg = data; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_clear_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->ITCTRL.reg &= ~mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_toggle_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->ITCTRL.reg ^= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_itctrl_reg_t hri_mtb_read_ITCTRL_reg(const void *const hw) +{ + return ((Mtb *)hw)->ITCTRL.reg; +} + +static inline void hri_mtb_set_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->LOCKACCESS.reg |= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_lockaccess_reg_t hri_mtb_get_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->LOCKACCESS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mtb_write_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t data) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->LOCKACCESS.reg = data; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_clear_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->LOCKACCESS.reg &= ~mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_toggle_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->LOCKACCESS.reg ^= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_lockaccess_reg_t hri_mtb_read_LOCKACCESS_reg(const void *const hw) +{ + return ((Mtb *)hw)->LOCKACCESS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_MTB_L21_H_INCLUDED */ +#endif /* _SAML21_MTB_COMPONENT_ */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_nvic_l21.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_nvic_l21.h new file mode 100644 index 00000000..0cb5e2cd --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_nvic_l21.h @@ -0,0 +1,269 @@ +/** + * \file + * + * \brief SAM NVIC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_NVIC_COMPONENT_ +#ifndef _HRI_NVIC_L21_H_INCLUDED_ +#define _HRI_NVIC_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_NVIC_CRITICAL_SECTIONS) +#define NVIC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define NVIC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define NVIC_CRITICAL_SECTION_ENTER() +#define NVIC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_nvic_icer_reg_t; +typedef uint32_t hri_nvic_icpr_reg_t; +typedef uint32_t hri_nvic_ipr_reg_t; +typedef uint32_t hri_nvic_iser_reg_t; +typedef uint32_t hri_nvic_ispr_reg_t; + +static inline void hri_nvic_set_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ISER.reg |= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_iser_reg_t hri_nvic_get_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->ISER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvic_write_ISER_reg(const void *const hw, hri_nvic_iser_reg_t data) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ISER.reg = data; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ISER.reg &= ~mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ISER.reg ^= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_iser_reg_t hri_nvic_read_ISER_reg(const void *const hw) +{ + return ((Nvic *)hw)->ISER.reg; +} + +static inline void hri_nvic_set_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ICER.reg |= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_icer_reg_t hri_nvic_get_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->ICER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvic_write_ICER_reg(const void *const hw, hri_nvic_icer_reg_t data) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ICER.reg = data; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ICER.reg &= ~mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ICER.reg ^= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_icer_reg_t hri_nvic_read_ICER_reg(const void *const hw) +{ + return ((Nvic *)hw)->ICER.reg; +} + +static inline void hri_nvic_set_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ISPR.reg |= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_ispr_reg_t hri_nvic_get_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->ISPR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvic_write_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t data) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ISPR.reg = data; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ISPR.reg &= ~mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ISPR.reg ^= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_ispr_reg_t hri_nvic_read_ISPR_reg(const void *const hw) +{ + return ((Nvic *)hw)->ISPR.reg; +} + +static inline void hri_nvic_set_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ICPR.reg |= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_icpr_reg_t hri_nvic_get_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->ICPR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvic_write_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t data) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ICPR.reg = data; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ICPR.reg &= ~mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ICPR.reg ^= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_icpr_reg_t hri_nvic_read_ICPR_reg(const void *const hw) +{ + return ((Nvic *)hw)->ICPR.reg; +} + +static inline void hri_nvic_set_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->IPR[index].reg |= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_ipr_reg_t hri_nvic_get_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->IPR[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvic_write_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t data) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->IPR[index].reg = data; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->IPR[index].reg &= ~mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->IPR[index].reg ^= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_ipr_reg_t hri_nvic_read_IPR_reg(const void *const hw, uint8_t index) +{ + return ((Nvic *)hw)->IPR[index].reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_NVIC_L21_H_INCLUDED */ +#endif /* _SAML21_NVIC_COMPONENT_ */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_nvmctrl_l21.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_nvmctrl_l21.h new file mode 100644 index 00000000..08e70193 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_nvmctrl_l21.h @@ -0,0 +1,1104 @@ +/** + * \file + * + * \brief SAM NVMCTRL + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_NVMCTRL_COMPONENT_ +#ifndef _HRI_NVMCTRL_L21_H_INCLUDED_ +#define _HRI_NVMCTRL_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_NVMCTRL_CRITICAL_SECTIONS) +#define NVMCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define NVMCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define NVMCTRL_CRITICAL_SECTION_ENTER() +#define NVMCTRL_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_nvmctrl_ctrla_reg_t; +typedef uint16_t hri_nvmctrl_lock_reg_t; +typedef uint16_t hri_nvmctrl_status_reg_t; +typedef uint32_t hri_nvmctrl_addr_reg_t; +typedef uint32_t hri_nvmctrl_ctrlb_reg_t; +typedef uint32_t hri_nvmctrl_param_reg_t; +typedef uint8_t hri_nvmctrl_intenset_reg_t; +typedef uint8_t hri_nvmctrl_intflag_reg_t; + +static inline bool hri_nvmctrl_get_INTFLAG_READY_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_READY) >> NVMCTRL_INTFLAG_READY_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_READY_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_READY; +} + +static inline bool hri_nvmctrl_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ERROR) >> NVMCTRL_INTFLAG_ERROR_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ERROR; +} + +static inline bool hri_nvmctrl_get_interrupt_READY_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_READY) >> NVMCTRL_INTFLAG_READY_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_READY_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_READY; +} + +static inline bool hri_nvmctrl_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ERROR) >> NVMCTRL_INTFLAG_ERROR_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ERROR; +} + +static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_get_INTFLAG_reg(const void *const hw, + hri_nvmctrl_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Nvmctrl *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_read_INTFLAG_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->INTFLAG.reg; +} + +static inline void hri_nvmctrl_clear_INTFLAG_reg(const void *const hw, hri_nvmctrl_intflag_reg_t mask) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_nvmctrl_set_INTEN_READY_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_READY; +} + +static inline bool hri_nvmctrl_get_INTEN_READY_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_READY) >> NVMCTRL_INTENSET_READY_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_READY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_READY; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_READY; + } +} + +static inline void hri_nvmctrl_clear_INTEN_READY_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_READY; +} + +static inline void hri_nvmctrl_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ERROR; +} + +static inline bool hri_nvmctrl_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ERROR) >> NVMCTRL_INTENSET_ERROR_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ERROR; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ERROR; + } +} + +static inline void hri_nvmctrl_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ERROR; +} + +static inline void hri_nvmctrl_set_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask) +{ + ((Nvmctrl *)hw)->INTENSET.reg = mask; +} + +static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_get_INTEN_reg(const void *const hw, + hri_nvmctrl_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Nvmctrl *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_read_INTEN_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->INTENSET.reg; +} + +static inline void hri_nvmctrl_write_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t data) +{ + ((Nvmctrl *)hw)->INTENSET.reg = data; + ((Nvmctrl *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_nvmctrl_clear_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = mask; +} + +static inline void hri_nvmctrl_set_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CMD(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_CMD(mask)) >> NVMCTRL_CTRLA_CMD_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_CMD_Msk; + tmp |= NVMCTRL_CTRLA_CMD(data); + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CMD(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CMD(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_CMD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_CMD_Msk) >> NVMCTRL_CTRLA_CMD_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CMDEX(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_CMDEX(mask)) >> NVMCTRL_CTRLA_CMDEX_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_CMDEX_Msk; + tmp |= NVMCTRL_CTRLA_CMDEX(data); + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CMDEX(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CMDEX(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_CMDEX_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_CMDEX_Msk) >> NVMCTRL_CTRLA_CMDEX_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->CTRLA.reg; +} + +static inline void hri_nvmctrl_set_CTRLB_MANW_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_MANW; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_CTRLB_MANW_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_MANW) >> NVMCTRL_CTRLB_MANW_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_CTRLB_MANW_bit(const void *const hw, bool value) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp &= ~NVMCTRL_CTRLB_MANW; + tmp |= value << NVMCTRL_CTRLB_MANW_Pos; + ((Nvmctrl *)hw)->CTRLB.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLB_MANW_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_MANW; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLB_MANW_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_MANW; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLB_FWUP_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_FWUP; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_CTRLB_FWUP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_FWUP) >> NVMCTRL_CTRLB_FWUP_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_CTRLB_FWUP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp &= ~NVMCTRL_CTRLB_FWUP; + tmp |= value << NVMCTRL_CTRLB_FWUP_Pos; + ((Nvmctrl *)hw)->CTRLB.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLB_FWUP_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_FWUP; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLB_FWUP_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_FWUP; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLB_CACHEDIS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_CACHEDIS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_CTRLB_CACHEDIS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_CACHEDIS) >> NVMCTRL_CTRLB_CACHEDIS_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_CTRLB_CACHEDIS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp &= ~NVMCTRL_CTRLB_CACHEDIS; + tmp |= value << NVMCTRL_CTRLB_CACHEDIS_Pos; + ((Nvmctrl *)hw)->CTRLB.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLB_CACHEDIS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_CACHEDIS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLB_CACHEDIS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_CACHEDIS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_RWS(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_RWS(mask)) >> NVMCTRL_CTRLB_RWS_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp &= ~NVMCTRL_CTRLB_RWS_Msk; + tmp |= NVMCTRL_CTRLB_RWS(data); + ((Nvmctrl *)hw)->CTRLB.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_RWS(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_RWS(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_RWS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_RWS_Msk) >> NVMCTRL_CTRLB_RWS_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_SLEEPPRM(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_SLEEPPRM_bf(const void *const hw, + hri_nvmctrl_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_SLEEPPRM(mask)) >> NVMCTRL_CTRLB_SLEEPPRM_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp &= ~NVMCTRL_CTRLB_SLEEPPRM_Msk; + tmp |= NVMCTRL_CTRLB_SLEEPPRM(data); + ((Nvmctrl *)hw)->CTRLB.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_SLEEPPRM(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_SLEEPPRM(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_SLEEPPRM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_SLEEPPRM_Msk) >> NVMCTRL_CTRLB_SLEEPPRM_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_READMODE(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_READMODE_bf(const void *const hw, + hri_nvmctrl_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_READMODE(mask)) >> NVMCTRL_CTRLB_READMODE_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp &= ~NVMCTRL_CTRLB_READMODE_Msk; + tmp |= NVMCTRL_CTRLB_READMODE(data); + ((Nvmctrl *)hw)->CTRLB.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_READMODE(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_READMODE(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_READMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_READMODE_Msk) >> NVMCTRL_CTRLB_READMODE_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->CTRLB.reg; +} + +static inline void hri_nvmctrl_set_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg |= NVMCTRL_PARAM_NVMP(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp = (tmp & NVMCTRL_PARAM_NVMP(mask)) >> NVMCTRL_PARAM_NVMP_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp &= ~NVMCTRL_PARAM_NVMP_Msk; + tmp |= NVMCTRL_PARAM_NVMP(data); + ((Nvmctrl *)hw)->PARAM.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg &= ~NVMCTRL_PARAM_NVMP(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg ^= NVMCTRL_PARAM_NVMP(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_NVMP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp = (tmp & NVMCTRL_PARAM_NVMP_Msk) >> NVMCTRL_PARAM_NVMP_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg |= NVMCTRL_PARAM_PSZ(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp = (tmp & NVMCTRL_PARAM_PSZ(mask)) >> NVMCTRL_PARAM_PSZ_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp &= ~NVMCTRL_PARAM_PSZ_Msk; + tmp |= NVMCTRL_PARAM_PSZ(data); + ((Nvmctrl *)hw)->PARAM.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg &= ~NVMCTRL_PARAM_PSZ(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg ^= NVMCTRL_PARAM_PSZ(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_PSZ_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp = (tmp & NVMCTRL_PARAM_PSZ_Msk) >> NVMCTRL_PARAM_PSZ_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_PARAM_RWWEEP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg |= NVMCTRL_PARAM_RWWEEP(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_RWWEEP_bf(const void *const hw, + hri_nvmctrl_param_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp = (tmp & NVMCTRL_PARAM_RWWEEP(mask)) >> NVMCTRL_PARAM_RWWEEP_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_PARAM_RWWEEP_bf(const void *const hw, hri_nvmctrl_param_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp &= ~NVMCTRL_PARAM_RWWEEP_Msk; + tmp |= NVMCTRL_PARAM_RWWEEP(data); + ((Nvmctrl *)hw)->PARAM.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_PARAM_RWWEEP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg &= ~NVMCTRL_PARAM_RWWEEP(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_PARAM_RWWEEP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg ^= NVMCTRL_PARAM_RWWEEP(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_RWWEEP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp = (tmp & NVMCTRL_PARAM_RWWEEP_Msk) >> NVMCTRL_PARAM_RWWEEP_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->PARAM.reg; +} + +static inline void hri_nvmctrl_set_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg |= NVMCTRL_ADDR_ADDR(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp = (tmp & NVMCTRL_ADDR_ADDR(mask)) >> NVMCTRL_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp &= ~NVMCTRL_ADDR_ADDR_Msk; + tmp |= NVMCTRL_ADDR_ADDR(data); + ((Nvmctrl *)hw)->ADDR.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg &= ~NVMCTRL_ADDR_ADDR(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg ^= NVMCTRL_ADDR_ADDR(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp = (tmp & NVMCTRL_ADDR_ADDR_Msk) >> NVMCTRL_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->ADDR.reg; +} + +static inline void hri_nvmctrl_set_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->LOCK.reg |= NVMCTRL_LOCK_LOCK(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_get_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->LOCK.reg; + tmp = (tmp & NVMCTRL_LOCK_LOCK(mask)) >> NVMCTRL_LOCK_LOCK_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t data) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->LOCK.reg; + tmp &= ~NVMCTRL_LOCK_LOCK_Msk; + tmp |= NVMCTRL_LOCK_LOCK(data); + ((Nvmctrl *)hw)->LOCK.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->LOCK.reg &= ~NVMCTRL_LOCK_LOCK(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->LOCK.reg ^= NVMCTRL_LOCK_LOCK(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_read_LOCK_LOCK_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->LOCK.reg; + tmp = (tmp & NVMCTRL_LOCK_LOCK_Msk) >> NVMCTRL_LOCK_LOCK_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->LOCK.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_get_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->LOCK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->LOCK.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->LOCK.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->LOCK.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_read_LOCK_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->LOCK.reg; +} + +static inline bool hri_nvmctrl_get_STATUS_PRM_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_PRM) >> NVMCTRL_STATUS_PRM_Pos; +} + +static inline void hri_nvmctrl_clear_STATUS_PRM_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_PRM; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_STATUS_LOAD_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_LOAD) >> NVMCTRL_STATUS_LOAD_Pos; +} + +static inline void hri_nvmctrl_clear_STATUS_LOAD_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_LOAD; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_STATUS_PROGE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_PROGE) >> NVMCTRL_STATUS_PROGE_Pos; +} + +static inline void hri_nvmctrl_clear_STATUS_PROGE_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_PROGE; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_STATUS_LOCKE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_LOCKE) >> NVMCTRL_STATUS_LOCKE_Pos; +} + +static inline void hri_nvmctrl_clear_STATUS_LOCKE_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_LOCKE; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_STATUS_NVME_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_NVME) >> NVMCTRL_STATUS_NVME_Pos; +} + +static inline void hri_nvmctrl_clear_STATUS_NVME_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_NVME; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_STATUS_SB_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_SB) >> NVMCTRL_STATUS_SB_Pos; +} + +static inline void hri_nvmctrl_clear_STATUS_SB_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_SB; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_status_reg_t hri_nvmctrl_get_STATUS_reg(const void *const hw, hri_nvmctrl_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_clear_STATUS_reg(const void *const hw, hri_nvmctrl_status_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->STATUS.reg = mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_status_reg_t hri_nvmctrl_read_STATUS_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->STATUS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_NVMCTRL_L21_H_INCLUDED */ +#endif /* _SAML21_NVMCTRL_COMPONENT_ */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_opamp_l21.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_opamp_l21.h new file mode 100644 index 00000000..bb45b322 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_opamp_l21.h @@ -0,0 +1,812 @@ +/** + * \file + * + * \brief SAM OPAMP + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_OPAMP_COMPONENT_ +#ifndef _HRI_OPAMP_L21_H_INCLUDED_ +#define _HRI_OPAMP_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_OPAMP_CRITICAL_SECTIONS) +#define OPAMP_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define OPAMP_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define OPAMP_CRITICAL_SECTION_ENTER() +#define OPAMP_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_opamp_opampctrl_reg_t; +typedef uint8_t hri_opamp_ctrla_reg_t; +typedef uint8_t hri_opamp_status_reg_t; + +static inline bool hri_opamp_get_STATUS_READY0_bit(const void *const hw) +{ + return (((Opamp *)hw)->STATUS.reg & OPAMP_STATUS_READY0) >> OPAMP_STATUS_READY0_Pos; +} + +static inline bool hri_opamp_get_STATUS_READY1_bit(const void *const hw) +{ + return (((Opamp *)hw)->STATUS.reg & OPAMP_STATUS_READY1) >> OPAMP_STATUS_READY1_Pos; +} + +static inline bool hri_opamp_get_STATUS_READY2_bit(const void *const hw) +{ + return (((Opamp *)hw)->STATUS.reg & OPAMP_STATUS_READY2) >> OPAMP_STATUS_READY2_Pos; +} + +static inline hri_opamp_status_reg_t hri_opamp_get_STATUS_reg(const void *const hw, hri_opamp_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Opamp *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_opamp_status_reg_t hri_opamp_read_STATUS_reg(const void *const hw) +{ + return ((Opamp *)hw)->STATUS.reg; +} + +static inline void hri_opamp_set_CTRLA_SWRST_bit(const void *const hw) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->CTRLA.reg |= OPAMP_CTRLA_SWRST; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_opamp_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Opamp *)hw)->CTRLA.reg; + tmp = (tmp & OPAMP_CTRLA_SWRST) >> OPAMP_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_opamp_set_CTRLA_ENABLE_bit(const void *const hw) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->CTRLA.reg |= OPAMP_CTRLA_ENABLE; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_opamp_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Opamp *)hw)->CTRLA.reg; + tmp = (tmp & OPAMP_CTRLA_ENABLE) >> OPAMP_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_opamp_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OPAMP_CRITICAL_SECTION_ENTER(); + tmp = ((Opamp *)hw)->CTRLA.reg; + tmp &= ~OPAMP_CTRLA_ENABLE; + tmp |= value << OPAMP_CTRLA_ENABLE_Pos; + ((Opamp *)hw)->CTRLA.reg = tmp; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->CTRLA.reg &= ~OPAMP_CTRLA_ENABLE; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->CTRLA.reg ^= OPAMP_CTRLA_ENABLE; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_set_CTRLA_LPMUX_bit(const void *const hw) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->CTRLA.reg |= OPAMP_CTRLA_LPMUX; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_opamp_get_CTRLA_LPMUX_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Opamp *)hw)->CTRLA.reg; + tmp = (tmp & OPAMP_CTRLA_LPMUX) >> OPAMP_CTRLA_LPMUX_Pos; + return (bool)tmp; +} + +static inline void hri_opamp_write_CTRLA_LPMUX_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OPAMP_CRITICAL_SECTION_ENTER(); + tmp = ((Opamp *)hw)->CTRLA.reg; + tmp &= ~OPAMP_CTRLA_LPMUX; + tmp |= value << OPAMP_CTRLA_LPMUX_Pos; + ((Opamp *)hw)->CTRLA.reg = tmp; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_clear_CTRLA_LPMUX_bit(const void *const hw) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->CTRLA.reg &= ~OPAMP_CTRLA_LPMUX; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_toggle_CTRLA_LPMUX_bit(const void *const hw) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->CTRLA.reg ^= OPAMP_CTRLA_LPMUX; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_set_CTRLA_reg(const void *const hw, hri_opamp_ctrla_reg_t mask) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->CTRLA.reg |= mask; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_opamp_ctrla_reg_t hri_opamp_get_CTRLA_reg(const void *const hw, hri_opamp_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Opamp *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_opamp_write_CTRLA_reg(const void *const hw, hri_opamp_ctrla_reg_t data) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->CTRLA.reg = data; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_clear_CTRLA_reg(const void *const hw, hri_opamp_ctrla_reg_t mask) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->CTRLA.reg &= ~mask; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_toggle_CTRLA_reg(const void *const hw, hri_opamp_ctrla_reg_t mask) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->CTRLA.reg ^= mask; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_opamp_ctrla_reg_t hri_opamp_read_CTRLA_reg(const void *const hw) +{ + return ((Opamp *)hw)->CTRLA.reg; +} + +static inline void hri_opamp_set_OPAMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg |= OPAMP_OPAMPCTRL_ENABLE; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_opamp_get_OPAMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp = (tmp & OPAMP_OPAMPCTRL_ENABLE) >> OPAMP_OPAMPCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_opamp_write_OPAMPCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OPAMP_CRITICAL_SECTION_ENTER(); + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp &= ~OPAMP_OPAMPCTRL_ENABLE; + tmp |= value << OPAMP_OPAMPCTRL_ENABLE_Pos; + ((Opamp *)hw)->OPAMPCTRL[index].reg = tmp; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_clear_OPAMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg &= ~OPAMP_OPAMPCTRL_ENABLE; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_toggle_OPAMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg ^= OPAMP_OPAMPCTRL_ENABLE; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_set_OPAMPCTRL_ANAOUT_bit(const void *const hw, uint8_t index) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg |= OPAMP_OPAMPCTRL_ANAOUT; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_opamp_get_OPAMPCTRL_ANAOUT_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp = (tmp & OPAMP_OPAMPCTRL_ANAOUT) >> OPAMP_OPAMPCTRL_ANAOUT_Pos; + return (bool)tmp; +} + +static inline void hri_opamp_write_OPAMPCTRL_ANAOUT_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OPAMP_CRITICAL_SECTION_ENTER(); + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp &= ~OPAMP_OPAMPCTRL_ANAOUT; + tmp |= value << OPAMP_OPAMPCTRL_ANAOUT_Pos; + ((Opamp *)hw)->OPAMPCTRL[index].reg = tmp; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_clear_OPAMPCTRL_ANAOUT_bit(const void *const hw, uint8_t index) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg &= ~OPAMP_OPAMPCTRL_ANAOUT; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_toggle_OPAMPCTRL_ANAOUT_bit(const void *const hw, uint8_t index) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg ^= OPAMP_OPAMPCTRL_ANAOUT; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_set_OPAMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg |= OPAMP_OPAMPCTRL_RUNSTDBY; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_opamp_get_OPAMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp = (tmp & OPAMP_OPAMPCTRL_RUNSTDBY) >> OPAMP_OPAMPCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_opamp_write_OPAMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OPAMP_CRITICAL_SECTION_ENTER(); + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp &= ~OPAMP_OPAMPCTRL_RUNSTDBY; + tmp |= value << OPAMP_OPAMPCTRL_RUNSTDBY_Pos; + ((Opamp *)hw)->OPAMPCTRL[index].reg = tmp; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_clear_OPAMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg &= ~OPAMP_OPAMPCTRL_RUNSTDBY; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_toggle_OPAMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg ^= OPAMP_OPAMPCTRL_RUNSTDBY; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_set_OPAMPCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg |= OPAMP_OPAMPCTRL_ONDEMAND; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_opamp_get_OPAMPCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp = (tmp & OPAMP_OPAMPCTRL_ONDEMAND) >> OPAMP_OPAMPCTRL_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_opamp_write_OPAMPCTRL_ONDEMAND_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OPAMP_CRITICAL_SECTION_ENTER(); + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp &= ~OPAMP_OPAMPCTRL_ONDEMAND; + tmp |= value << OPAMP_OPAMPCTRL_ONDEMAND_Pos; + ((Opamp *)hw)->OPAMPCTRL[index].reg = tmp; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_clear_OPAMPCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg &= ~OPAMP_OPAMPCTRL_ONDEMAND; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_toggle_OPAMPCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg ^= OPAMP_OPAMPCTRL_ONDEMAND; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_set_OPAMPCTRL_RES2OUT_bit(const void *const hw, uint8_t index) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg |= OPAMP_OPAMPCTRL_RES2OUT; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_opamp_get_OPAMPCTRL_RES2OUT_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp = (tmp & OPAMP_OPAMPCTRL_RES2OUT) >> OPAMP_OPAMPCTRL_RES2OUT_Pos; + return (bool)tmp; +} + +static inline void hri_opamp_write_OPAMPCTRL_RES2OUT_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OPAMP_CRITICAL_SECTION_ENTER(); + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp &= ~OPAMP_OPAMPCTRL_RES2OUT; + tmp |= value << OPAMP_OPAMPCTRL_RES2OUT_Pos; + ((Opamp *)hw)->OPAMPCTRL[index].reg = tmp; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_clear_OPAMPCTRL_RES2OUT_bit(const void *const hw, uint8_t index) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg &= ~OPAMP_OPAMPCTRL_RES2OUT; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_toggle_OPAMPCTRL_RES2OUT_bit(const void *const hw, uint8_t index) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg ^= OPAMP_OPAMPCTRL_RES2OUT; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_set_OPAMPCTRL_RES2VCC_bit(const void *const hw, uint8_t index) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg |= OPAMP_OPAMPCTRL_RES2VCC; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_opamp_get_OPAMPCTRL_RES2VCC_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp = (tmp & OPAMP_OPAMPCTRL_RES2VCC) >> OPAMP_OPAMPCTRL_RES2VCC_Pos; + return (bool)tmp; +} + +static inline void hri_opamp_write_OPAMPCTRL_RES2VCC_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OPAMP_CRITICAL_SECTION_ENTER(); + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp &= ~OPAMP_OPAMPCTRL_RES2VCC; + tmp |= value << OPAMP_OPAMPCTRL_RES2VCC_Pos; + ((Opamp *)hw)->OPAMPCTRL[index].reg = tmp; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_clear_OPAMPCTRL_RES2VCC_bit(const void *const hw, uint8_t index) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg &= ~OPAMP_OPAMPCTRL_RES2VCC; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_toggle_OPAMPCTRL_RES2VCC_bit(const void *const hw, uint8_t index) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg ^= OPAMP_OPAMPCTRL_RES2VCC; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_set_OPAMPCTRL_RES1EN_bit(const void *const hw, uint8_t index) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg |= OPAMP_OPAMPCTRL_RES1EN; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_opamp_get_OPAMPCTRL_RES1EN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp = (tmp & OPAMP_OPAMPCTRL_RES1EN) >> OPAMP_OPAMPCTRL_RES1EN_Pos; + return (bool)tmp; +} + +static inline void hri_opamp_write_OPAMPCTRL_RES1EN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OPAMP_CRITICAL_SECTION_ENTER(); + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp &= ~OPAMP_OPAMPCTRL_RES1EN; + tmp |= value << OPAMP_OPAMPCTRL_RES1EN_Pos; + ((Opamp *)hw)->OPAMPCTRL[index].reg = tmp; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_clear_OPAMPCTRL_RES1EN_bit(const void *const hw, uint8_t index) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg &= ~OPAMP_OPAMPCTRL_RES1EN; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_toggle_OPAMPCTRL_RES1EN_bit(const void *const hw, uint8_t index) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg ^= OPAMP_OPAMPCTRL_RES1EN; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_set_OPAMPCTRL_BIAS_bf(const void *const hw, uint8_t index, hri_opamp_opampctrl_reg_t mask) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg |= OPAMP_OPAMPCTRL_BIAS(mask); + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_opamp_opampctrl_reg_t hri_opamp_get_OPAMPCTRL_BIAS_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp = (tmp & OPAMP_OPAMPCTRL_BIAS(mask)) >> OPAMP_OPAMPCTRL_BIAS_Pos; + return tmp; +} + +static inline void hri_opamp_write_OPAMPCTRL_BIAS_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t data) +{ + uint32_t tmp; + OPAMP_CRITICAL_SECTION_ENTER(); + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp &= ~OPAMP_OPAMPCTRL_BIAS_Msk; + tmp |= OPAMP_OPAMPCTRL_BIAS(data); + ((Opamp *)hw)->OPAMPCTRL[index].reg = tmp; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_clear_OPAMPCTRL_BIAS_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t mask) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg &= ~OPAMP_OPAMPCTRL_BIAS(mask); + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_toggle_OPAMPCTRL_BIAS_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t mask) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg ^= OPAMP_OPAMPCTRL_BIAS(mask); + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_opamp_opampctrl_reg_t hri_opamp_read_OPAMPCTRL_BIAS_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp = (tmp & OPAMP_OPAMPCTRL_BIAS_Msk) >> OPAMP_OPAMPCTRL_BIAS_Pos; + return tmp; +} + +static inline void hri_opamp_set_OPAMPCTRL_RES1MUX_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t mask) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg |= OPAMP_OPAMPCTRL_RES1MUX(mask); + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_opamp_opampctrl_reg_t hri_opamp_get_OPAMPCTRL_RES1MUX_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp = (tmp & OPAMP_OPAMPCTRL_RES1MUX(mask)) >> OPAMP_OPAMPCTRL_RES1MUX_Pos; + return tmp; +} + +static inline void hri_opamp_write_OPAMPCTRL_RES1MUX_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t data) +{ + uint32_t tmp; + OPAMP_CRITICAL_SECTION_ENTER(); + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp &= ~OPAMP_OPAMPCTRL_RES1MUX_Msk; + tmp |= OPAMP_OPAMPCTRL_RES1MUX(data); + ((Opamp *)hw)->OPAMPCTRL[index].reg = tmp; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_clear_OPAMPCTRL_RES1MUX_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t mask) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg &= ~OPAMP_OPAMPCTRL_RES1MUX(mask); + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_toggle_OPAMPCTRL_RES1MUX_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t mask) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg ^= OPAMP_OPAMPCTRL_RES1MUX(mask); + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_opamp_opampctrl_reg_t hri_opamp_read_OPAMPCTRL_RES1MUX_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp = (tmp & OPAMP_OPAMPCTRL_RES1MUX_Msk) >> OPAMP_OPAMPCTRL_RES1MUX_Pos; + return tmp; +} + +static inline void hri_opamp_set_OPAMPCTRL_POTMUX_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t mask) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg |= OPAMP_OPAMPCTRL_POTMUX(mask); + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_opamp_opampctrl_reg_t hri_opamp_get_OPAMPCTRL_POTMUX_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp = (tmp & OPAMP_OPAMPCTRL_POTMUX(mask)) >> OPAMP_OPAMPCTRL_POTMUX_Pos; + return tmp; +} + +static inline void hri_opamp_write_OPAMPCTRL_POTMUX_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t data) +{ + uint32_t tmp; + OPAMP_CRITICAL_SECTION_ENTER(); + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp &= ~OPAMP_OPAMPCTRL_POTMUX_Msk; + tmp |= OPAMP_OPAMPCTRL_POTMUX(data); + ((Opamp *)hw)->OPAMPCTRL[index].reg = tmp; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_clear_OPAMPCTRL_POTMUX_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t mask) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg &= ~OPAMP_OPAMPCTRL_POTMUX(mask); + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_toggle_OPAMPCTRL_POTMUX_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t mask) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg ^= OPAMP_OPAMPCTRL_POTMUX(mask); + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_opamp_opampctrl_reg_t hri_opamp_read_OPAMPCTRL_POTMUX_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp = (tmp & OPAMP_OPAMPCTRL_POTMUX_Msk) >> OPAMP_OPAMPCTRL_POTMUX_Pos; + return tmp; +} + +static inline void hri_opamp_set_OPAMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t mask) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg |= OPAMP_OPAMPCTRL_MUXPOS(mask); + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_opamp_opampctrl_reg_t hri_opamp_get_OPAMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp = (tmp & OPAMP_OPAMPCTRL_MUXPOS(mask)) >> OPAMP_OPAMPCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_opamp_write_OPAMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t data) +{ + uint32_t tmp; + OPAMP_CRITICAL_SECTION_ENTER(); + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp &= ~OPAMP_OPAMPCTRL_MUXPOS_Msk; + tmp |= OPAMP_OPAMPCTRL_MUXPOS(data); + ((Opamp *)hw)->OPAMPCTRL[index].reg = tmp; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_clear_OPAMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t mask) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg &= ~OPAMP_OPAMPCTRL_MUXPOS(mask); + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_toggle_OPAMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t mask) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg ^= OPAMP_OPAMPCTRL_MUXPOS(mask); + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_opamp_opampctrl_reg_t hri_opamp_read_OPAMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp = (tmp & OPAMP_OPAMPCTRL_MUXPOS_Msk) >> OPAMP_OPAMPCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_opamp_set_OPAMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t mask) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg |= OPAMP_OPAMPCTRL_MUXNEG(mask); + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_opamp_opampctrl_reg_t hri_opamp_get_OPAMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp = (tmp & OPAMP_OPAMPCTRL_MUXNEG(mask)) >> OPAMP_OPAMPCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_opamp_write_OPAMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t data) +{ + uint32_t tmp; + OPAMP_CRITICAL_SECTION_ENTER(); + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp &= ~OPAMP_OPAMPCTRL_MUXNEG_Msk; + tmp |= OPAMP_OPAMPCTRL_MUXNEG(data); + ((Opamp *)hw)->OPAMPCTRL[index].reg = tmp; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_clear_OPAMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t mask) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg &= ~OPAMP_OPAMPCTRL_MUXNEG(mask); + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_toggle_OPAMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t mask) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg ^= OPAMP_OPAMPCTRL_MUXNEG(mask); + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_opamp_opampctrl_reg_t hri_opamp_read_OPAMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp = (tmp & OPAMP_OPAMPCTRL_MUXNEG_Msk) >> OPAMP_OPAMPCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_opamp_set_OPAMPCTRL_reg(const void *const hw, uint8_t index, hri_opamp_opampctrl_reg_t mask) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg |= mask; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_opamp_opampctrl_reg_t hri_opamp_get_OPAMPCTRL_reg(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_opamp_write_OPAMPCTRL_reg(const void *const hw, uint8_t index, hri_opamp_opampctrl_reg_t data) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg = data; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_clear_OPAMPCTRL_reg(const void *const hw, uint8_t index, hri_opamp_opampctrl_reg_t mask) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg &= ~mask; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_toggle_OPAMPCTRL_reg(const void *const hw, uint8_t index, hri_opamp_opampctrl_reg_t mask) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg ^= mask; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_opamp_opampctrl_reg_t hri_opamp_read_OPAMPCTRL_reg(const void *const hw, uint8_t index) +{ + return ((Opamp *)hw)->OPAMPCTRL[index].reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_OPAMP_L21_H_INCLUDED */ +#endif /* _SAML21_OPAMP_COMPONENT_ */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_osc32kctrl_l21.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_osc32kctrl_l21.h new file mode 100644 index 00000000..9aa600af --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_osc32kctrl_l21.h @@ -0,0 +1,1200 @@ +/** + * \file + * + * \brief SAM OSC32KCTRL + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_OSC32KCTRL_COMPONENT_ +#ifndef _HRI_OSC32KCTRL_L21_H_INCLUDED_ +#define _HRI_OSC32KCTRL_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_OSC32KCTRL_CRITICAL_SECTIONS) +#define OSC32KCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define OSC32KCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define OSC32KCTRL_CRITICAL_SECTION_ENTER() +#define OSC32KCTRL_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_osc32kctrl_intenset_reg_t; +typedef uint32_t hri_osc32kctrl_intflag_reg_t; +typedef uint32_t hri_osc32kctrl_osc32k_reg_t; +typedef uint32_t hri_osc32kctrl_osculp32k_reg_t; +typedef uint32_t hri_osc32kctrl_rtcctrl_reg_t; +typedef uint32_t hri_osc32kctrl_status_reg_t; +typedef uint32_t hri_osc32kctrl_xosc32k_reg_t; + +static inline bool hri_osc32kctrl_get_INTFLAG_XOSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KRDY) >> OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos; +} + +static inline void hri_osc32kctrl_clear_INTFLAG_XOSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY; +} + +static inline bool hri_osc32kctrl_get_INTFLAG_OSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_OSC32KRDY) >> OSC32KCTRL_INTFLAG_OSC32KRDY_Pos; +} + +static inline void hri_osc32kctrl_clear_INTFLAG_OSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_OSC32KRDY; +} + +static inline bool hri_osc32kctrl_get_interrupt_XOSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KRDY) >> OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos; +} + +static inline void hri_osc32kctrl_clear_interrupt_XOSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY; +} + +static inline bool hri_osc32kctrl_get_interrupt_OSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_OSC32KRDY) >> OSC32KCTRL_INTFLAG_OSC32KRDY_Pos; +} + +static inline void hri_osc32kctrl_clear_interrupt_OSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_OSC32KRDY; +} + +static inline hri_osc32kctrl_intflag_reg_t hri_osc32kctrl_get_INTFLAG_reg(const void *const hw, + hri_osc32kctrl_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_osc32kctrl_intflag_reg_t hri_osc32kctrl_read_INTFLAG_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->INTFLAG.reg; +} + +static inline void hri_osc32kctrl_clear_INTFLAG_reg(const void *const hw, hri_osc32kctrl_intflag_reg_t mask) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_osc32kctrl_set_INTEN_XOSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; +} + +static inline bool hri_osc32kctrl_get_INTEN_XOSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_XOSC32KRDY) >> OSC32KCTRL_INTENSET_XOSC32KRDY_Pos; +} + +static inline void hri_osc32kctrl_write_INTEN_XOSC32KRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; + } else { + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; + } +} + +static inline void hri_osc32kctrl_clear_INTEN_XOSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; +} + +static inline void hri_osc32kctrl_set_INTEN_OSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_OSC32KRDY; +} + +static inline bool hri_osc32kctrl_get_INTEN_OSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_OSC32KRDY) >> OSC32KCTRL_INTENSET_OSC32KRDY_Pos; +} + +static inline void hri_osc32kctrl_write_INTEN_OSC32KRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_OSC32KRDY; + } else { + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_OSC32KRDY; + } +} + +static inline void hri_osc32kctrl_clear_INTEN_OSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_OSC32KRDY; +} + +static inline void hri_osc32kctrl_set_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t mask) +{ + ((Osc32kctrl *)hw)->INTENSET.reg = mask; +} + +static inline hri_osc32kctrl_intenset_reg_t hri_osc32kctrl_get_INTEN_reg(const void *const hw, + hri_osc32kctrl_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_osc32kctrl_intenset_reg_t hri_osc32kctrl_read_INTEN_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->INTENSET.reg; +} + +static inline void hri_osc32kctrl_write_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t data) +{ + ((Osc32kctrl *)hw)->INTENSET.reg = data; + ((Osc32kctrl *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_osc32kctrl_clear_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t mask) +{ + ((Osc32kctrl *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_osc32kctrl_get_STATUS_XOSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KRDY) >> OSC32KCTRL_STATUS_XOSC32KRDY_Pos; +} + +static inline bool hri_osc32kctrl_get_STATUS_OSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_OSC32KRDY) >> OSC32KCTRL_STATUS_OSC32KRDY_Pos; +} + +static inline hri_osc32kctrl_status_reg_t hri_osc32kctrl_get_STATUS_reg(const void *const hw, + hri_osc32kctrl_status_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_osc32kctrl_status_reg_t hri_osc32kctrl_read_STATUS_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->STATUS.reg; +} + +static inline void hri_osc32kctrl_set_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg |= OSC32KCTRL_RTCCTRL_RTCSEL(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_get_RTCCTRL_RTCSEL_bf(const void *const hw, + hri_osc32kctrl_rtcctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; + tmp = (tmp & OSC32KCTRL_RTCCTRL_RTCSEL(mask)) >> OSC32KCTRL_RTCCTRL_RTCSEL_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_write_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t data) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; + tmp &= ~OSC32KCTRL_RTCCTRL_RTCSEL_Msk; + tmp |= OSC32KCTRL_RTCCTRL_RTCSEL(data); + ((Osc32kctrl *)hw)->RTCCTRL.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg &= ~OSC32KCTRL_RTCCTRL_RTCSEL(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg ^= OSC32KCTRL_RTCCTRL_RTCSEL(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_read_RTCCTRL_RTCSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; + tmp = (tmp & OSC32KCTRL_RTCCTRL_RTCSEL_Msk) >> OSC32KCTRL_RTCCTRL_RTCSEL_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_set_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_get_RTCCTRL_reg(const void *const hw, + hri_osc32kctrl_rtcctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_read_RTCCTRL_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->RTCCTRL.reg; +} + +static inline void hri_osc32kctrl_set_XOSC32K_ENABLE_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ENABLE; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_ENABLE) >> OSC32KCTRL_XOSC32K_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_ENABLE; + tmp |= value << OSC32KCTRL_XOSC32K_ENABLE_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_ENABLE_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ENABLE; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_ENABLE_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_ENABLE; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_XTALEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_XTALEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_XTALEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_XTALEN) >> OSC32KCTRL_XOSC32K_XTALEN_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_XTALEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_XTALEN; + tmp |= value << OSC32KCTRL_XOSC32K_XTALEN_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_XTALEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_XTALEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_XTALEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_XTALEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_EN32K_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_EN32K) >> OSC32KCTRL_XOSC32K_EN32K_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_EN32K_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_EN32K; + tmp |= value << OSC32KCTRL_XOSC32K_EN32K_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_EN1K_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_EN1K) >> OSC32KCTRL_XOSC32K_EN1K_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_EN1K_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_EN1K; + tmp |= value << OSC32KCTRL_XOSC32K_EN1K_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_RUNSTDBY; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_RUNSTDBY) >> OSC32KCTRL_XOSC32K_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_RUNSTDBY; + tmp |= value << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_RUNSTDBY; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_RUNSTDBY; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ONDEMAND; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_ONDEMAND) >> OSC32KCTRL_XOSC32K_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_ONDEMAND_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_ONDEMAND; + tmp |= value << OSC32KCTRL_XOSC32K_ONDEMAND_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ONDEMAND; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_ONDEMAND; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_WRTLOCK) >> OSC32KCTRL_XOSC32K_WRTLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_WRTLOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_WRTLOCK; + tmp |= value << OSC32KCTRL_XOSC32K_WRTLOCK_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_STARTUP(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_STARTUP_bf(const void *const hw, + hri_osc32kctrl_xosc32k_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_STARTUP(mask)) >> OSC32KCTRL_XOSC32K_STARTUP_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_STARTUP_Msk; + tmp |= OSC32KCTRL_XOSC32K_STARTUP(data); + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_STARTUP(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_STARTUP(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_STARTUP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_STARTUP_Msk) >> OSC32KCTRL_XOSC32K_STARTUP_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_set_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_reg(const void *const hw, + hri_osc32kctrl_xosc32k_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->XOSC32K.reg; +} + +static inline void hri_osc32kctrl_set_OSC32K_ENABLE_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg |= OSC32KCTRL_OSC32K_ENABLE; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSC32K_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp = (tmp & OSC32KCTRL_OSC32K_ENABLE) >> OSC32KCTRL_OSC32K_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSC32K_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp &= ~OSC32KCTRL_OSC32K_ENABLE; + tmp |= value << OSC32KCTRL_OSC32K_ENABLE_Pos; + ((Osc32kctrl *)hw)->OSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSC32K_ENABLE_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg &= ~OSC32KCTRL_OSC32K_ENABLE; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSC32K_ENABLE_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg ^= OSC32KCTRL_OSC32K_ENABLE; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSC32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg |= OSC32KCTRL_OSC32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSC32K_EN32K_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp = (tmp & OSC32KCTRL_OSC32K_EN32K) >> OSC32KCTRL_OSC32K_EN32K_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSC32K_EN32K_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp &= ~OSC32KCTRL_OSC32K_EN32K; + tmp |= value << OSC32KCTRL_OSC32K_EN32K_Pos; + ((Osc32kctrl *)hw)->OSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSC32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg &= ~OSC32KCTRL_OSC32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSC32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg ^= OSC32KCTRL_OSC32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSC32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg |= OSC32KCTRL_OSC32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSC32K_EN1K_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp = (tmp & OSC32KCTRL_OSC32K_EN1K) >> OSC32KCTRL_OSC32K_EN1K_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSC32K_EN1K_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp &= ~OSC32KCTRL_OSC32K_EN1K; + tmp |= value << OSC32KCTRL_OSC32K_EN1K_Pos; + ((Osc32kctrl *)hw)->OSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSC32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg &= ~OSC32KCTRL_OSC32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSC32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg ^= OSC32KCTRL_OSC32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSC32K_RUNSTDBY_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg |= OSC32KCTRL_OSC32K_RUNSTDBY; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSC32K_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp = (tmp & OSC32KCTRL_OSC32K_RUNSTDBY) >> OSC32KCTRL_OSC32K_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSC32K_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp &= ~OSC32KCTRL_OSC32K_RUNSTDBY; + tmp |= value << OSC32KCTRL_OSC32K_RUNSTDBY_Pos; + ((Osc32kctrl *)hw)->OSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSC32K_RUNSTDBY_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg &= ~OSC32KCTRL_OSC32K_RUNSTDBY; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSC32K_RUNSTDBY_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg ^= OSC32KCTRL_OSC32K_RUNSTDBY; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSC32K_ONDEMAND_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg |= OSC32KCTRL_OSC32K_ONDEMAND; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSC32K_ONDEMAND_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp = (tmp & OSC32KCTRL_OSC32K_ONDEMAND) >> OSC32KCTRL_OSC32K_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSC32K_ONDEMAND_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp &= ~OSC32KCTRL_OSC32K_ONDEMAND; + tmp |= value << OSC32KCTRL_OSC32K_ONDEMAND_Pos; + ((Osc32kctrl *)hw)->OSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSC32K_ONDEMAND_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg &= ~OSC32KCTRL_OSC32K_ONDEMAND; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSC32K_ONDEMAND_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg ^= OSC32KCTRL_OSC32K_ONDEMAND; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSC32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg |= OSC32KCTRL_OSC32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSC32K_WRTLOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp = (tmp & OSC32KCTRL_OSC32K_WRTLOCK) >> OSC32KCTRL_OSC32K_WRTLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSC32K_WRTLOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp &= ~OSC32KCTRL_OSC32K_WRTLOCK; + tmp |= value << OSC32KCTRL_OSC32K_WRTLOCK_Pos; + ((Osc32kctrl *)hw)->OSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSC32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg &= ~OSC32KCTRL_OSC32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSC32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg ^= OSC32KCTRL_OSC32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_osc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg |= OSC32KCTRL_OSC32K_STARTUP(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osc32k_reg_t hri_osc32kctrl_get_OSC32K_STARTUP_bf(const void *const hw, + hri_osc32kctrl_osc32k_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp = (tmp & OSC32KCTRL_OSC32K_STARTUP(mask)) >> OSC32KCTRL_OSC32K_STARTUP_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_write_OSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_osc32k_reg_t data) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp &= ~OSC32KCTRL_OSC32K_STARTUP_Msk; + tmp |= OSC32KCTRL_OSC32K_STARTUP(data); + ((Osc32kctrl *)hw)->OSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_osc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg &= ~OSC32KCTRL_OSC32K_STARTUP(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_osc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg ^= OSC32KCTRL_OSC32K_STARTUP(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osc32k_reg_t hri_osc32kctrl_read_OSC32K_STARTUP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp = (tmp & OSC32KCTRL_OSC32K_STARTUP_Msk) >> OSC32KCTRL_OSC32K_STARTUP_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_set_OSC32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg |= OSC32KCTRL_OSC32K_CALIB(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osc32k_reg_t hri_osc32kctrl_get_OSC32K_CALIB_bf(const void *const hw, + hri_osc32kctrl_osc32k_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp = (tmp & OSC32KCTRL_OSC32K_CALIB(mask)) >> OSC32KCTRL_OSC32K_CALIB_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_write_OSC32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osc32k_reg_t data) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp &= ~OSC32KCTRL_OSC32K_CALIB_Msk; + tmp |= OSC32KCTRL_OSC32K_CALIB(data); + ((Osc32kctrl *)hw)->OSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSC32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg &= ~OSC32KCTRL_OSC32K_CALIB(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSC32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg ^= OSC32KCTRL_OSC32K_CALIB(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osc32k_reg_t hri_osc32kctrl_read_OSC32K_CALIB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp = (tmp & OSC32KCTRL_OSC32K_CALIB_Msk) >> OSC32KCTRL_OSC32K_CALIB_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_set_OSC32K_reg(const void *const hw, hri_osc32kctrl_osc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osc32k_reg_t hri_osc32kctrl_get_OSC32K_reg(const void *const hw, + hri_osc32kctrl_osc32k_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_OSC32K_reg(const void *const hw, hri_osc32kctrl_osc32k_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSC32K_reg(const void *const hw, hri_osc32kctrl_osc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSC32K_reg(const void *const hw, hri_osc32kctrl_osc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osc32k_reg_t hri_osc32kctrl_read_OSC32K_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->OSC32K.reg; +} + +static inline void hri_osc32kctrl_set_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & OSC32KCTRL_OSCULP32K_WRTLOCK) >> OSC32KCTRL_OSCULP32K_WRTLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSCULP32K_WRTLOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp &= ~OSC32KCTRL_OSCULP32K_WRTLOCK; + tmp |= value << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos; + ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_CALIB(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_get_OSCULP32K_CALIB_bf(const void *const hw, + hri_osc32kctrl_osculp32k_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB(mask)) >> OSC32KCTRL_OSCULP32K_CALIB_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_write_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp &= ~OSC32KCTRL_OSCULP32K_CALIB_Msk; + tmp |= OSC32KCTRL_OSCULP32K_CALIB(data); + ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_CALIB(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_CALIB(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_CALIB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB_Msk) >> OSC32KCTRL_OSCULP32K_CALIB_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_set_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_get_OSCULP32K_reg(const void *const hw, + hri_osc32kctrl_osculp32k_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->OSCULP32K.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_OSC32KCTRL_L21_H_INCLUDED */ +#endif /* _SAML21_OSC32KCTRL_COMPONENT_ */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_oscctrl_l21.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_oscctrl_l21.h new file mode 100644 index 00000000..e83e1d92 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_oscctrl_l21.h @@ -0,0 +1,3135 @@ +/** + * \file + * + * \brief SAM OSCCTRL + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_OSCCTRL_COMPONENT_ +#ifndef _HRI_OSCCTRL_L21_H_INCLUDED_ +#define _HRI_OSCCTRL_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_OSCCTRL_CRITICAL_SECTIONS) +#define OSCCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define OSCCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define OSCCTRL_CRITICAL_SECTION_ENTER() +#define OSCCTRL_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_oscctrl_dfllctrl_reg_t; +typedef uint16_t hri_oscctrl_xoscctrl_reg_t; +typedef uint32_t hri_oscctrl_dfllmul_reg_t; +typedef uint32_t hri_oscctrl_dfllval_reg_t; +typedef uint32_t hri_oscctrl_dpllctrlb_reg_t; +typedef uint32_t hri_oscctrl_dpllratio_reg_t; +typedef uint32_t hri_oscctrl_intenset_reg_t; +typedef uint32_t hri_oscctrl_intflag_reg_t; +typedef uint32_t hri_oscctrl_status_reg_t; +typedef uint8_t hri_oscctrl_dfllsync_reg_t; +typedef uint8_t hri_oscctrl_dpllctrla_reg_t; +typedef uint8_t hri_oscctrl_dpllpresc_reg_t; +typedef uint8_t hri_oscctrl_dpllstatus_reg_t; +typedef uint8_t hri_oscctrl_dpllsyncbusy_reg_t; +typedef uint8_t hri_oscctrl_osc16mctrl_reg_t; + +static inline void hri_oscctrl_wait_for_sync(const void *const hw, hri_oscctrl_dpllsyncbusy_reg_t reg) +{ + while (((Oscctrl *)hw)->DPLLSYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_oscctrl_is_syncing(const void *const hw, hri_oscctrl_dpllsyncbusy_reg_t reg) +{ + return ((Oscctrl *)hw)->DPLLSYNCBUSY.reg & reg; +} + +static inline bool hri_oscctrl_get_INTFLAG_XOSCRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY) >> OSCCTRL_INTFLAG_XOSCRDY_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_XOSCRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY; +} + +static inline bool hri_oscctrl_get_INTFLAG_OSC16MRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_OSC16MRDY) >> OSCCTRL_INTFLAG_OSC16MRDY_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_OSC16MRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_OSC16MRDY; +} + +static inline bool hri_oscctrl_get_INTFLAG_DFLLRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRDY) >> OSCCTRL_INTFLAG_DFLLRDY_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DFLLRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY; +} + +static inline bool hri_oscctrl_get_INTFLAG_DFLLOOB_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLOOB) >> OSCCTRL_INTFLAG_DFLLOOB_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DFLLOOB_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLOOB; +} + +static inline bool hri_oscctrl_get_INTFLAG_DFLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKF) >> OSCCTRL_INTFLAG_DFLLLCKF_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DFLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKF; +} + +static inline bool hri_oscctrl_get_INTFLAG_DFLLLCKC_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKC) >> OSCCTRL_INTFLAG_DFLLLCKC_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DFLLLCKC_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKC; +} + +static inline bool hri_oscctrl_get_INTFLAG_DFLLRCS_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRCS) >> OSCCTRL_INTFLAG_DFLLRCS_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DFLLRCS_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRCS; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLLLCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLCKR) >> OSCCTRL_INTFLAG_DPLLLCKR_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLLLCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLCKR; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLCKF) >> OSCCTRL_INTFLAG_DPLLLCKF_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLCKF; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLLLTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLTO) >> OSCCTRL_INTFLAG_DPLLLTO_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLLLTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLTO; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLLLDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLDRTO) >> OSCCTRL_INTFLAG_DPLLLDRTO_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLLLDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLDRTO; +} + +static inline bool hri_oscctrl_get_interrupt_XOSCRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY) >> OSCCTRL_INTFLAG_XOSCRDY_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_XOSCRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY; +} + +static inline bool hri_oscctrl_get_interrupt_OSC16MRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_OSC16MRDY) >> OSCCTRL_INTFLAG_OSC16MRDY_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_OSC16MRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_OSC16MRDY; +} + +static inline bool hri_oscctrl_get_interrupt_DFLLRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRDY) >> OSCCTRL_INTFLAG_DFLLRDY_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DFLLRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY; +} + +static inline bool hri_oscctrl_get_interrupt_DFLLOOB_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLOOB) >> OSCCTRL_INTFLAG_DFLLOOB_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DFLLOOB_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLOOB; +} + +static inline bool hri_oscctrl_get_interrupt_DFLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKF) >> OSCCTRL_INTFLAG_DFLLLCKF_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DFLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKF; +} + +static inline bool hri_oscctrl_get_interrupt_DFLLLCKC_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKC) >> OSCCTRL_INTFLAG_DFLLLCKC_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DFLLLCKC_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKC; +} + +static inline bool hri_oscctrl_get_interrupt_DFLLRCS_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRCS) >> OSCCTRL_INTFLAG_DFLLRCS_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DFLLRCS_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRCS; +} + +static inline bool hri_oscctrl_get_interrupt_DPLLLCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLCKR) >> OSCCTRL_INTFLAG_DPLLLCKR_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLLLCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLCKR; +} + +static inline bool hri_oscctrl_get_interrupt_DPLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLCKF) >> OSCCTRL_INTFLAG_DPLLLCKF_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLCKF; +} + +static inline bool hri_oscctrl_get_interrupt_DPLLLTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLTO) >> OSCCTRL_INTFLAG_DPLLLTO_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLLLTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLTO; +} + +static inline bool hri_oscctrl_get_interrupt_DPLLLDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLDRTO) >> OSCCTRL_INTFLAG_DPLLLDRTO_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLLLDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLDRTO; +} + +static inline hri_oscctrl_intflag_reg_t hri_oscctrl_get_INTFLAG_reg(const void *const hw, + hri_oscctrl_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_intflag_reg_t hri_oscctrl_read_INTFLAG_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->INTFLAG.reg; +} + +static inline void hri_oscctrl_clear_INTFLAG_reg(const void *const hw, hri_oscctrl_intflag_reg_t mask) +{ + ((Oscctrl *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_oscctrl_set_INTEN_XOSCRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY; +} + +static inline bool hri_oscctrl_get_INTEN_XOSCRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCRDY) >> OSCCTRL_INTENSET_XOSCRDY_Pos; +} + +static inline void hri_oscctrl_write_INTEN_XOSCRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY; + } +} + +static inline void hri_oscctrl_clear_INTEN_XOSCRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY; +} + +static inline void hri_oscctrl_set_INTEN_OSC16MRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_OSC16MRDY; +} + +static inline bool hri_oscctrl_get_INTEN_OSC16MRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_OSC16MRDY) >> OSCCTRL_INTENSET_OSC16MRDY_Pos; +} + +static inline void hri_oscctrl_write_INTEN_OSC16MRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_OSC16MRDY; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_OSC16MRDY; + } +} + +static inline void hri_oscctrl_clear_INTEN_OSC16MRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_OSC16MRDY; +} + +static inline void hri_oscctrl_set_INTEN_DFLLRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRDY; +} + +static inline bool hri_oscctrl_get_INTEN_DFLLRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLRDY) >> OSCCTRL_INTENSET_DFLLRDY_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DFLLRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRDY; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRDY; + } +} + +static inline void hri_oscctrl_clear_INTEN_DFLLRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRDY; +} + +static inline void hri_oscctrl_set_INTEN_DFLLOOB_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLOOB; +} + +static inline bool hri_oscctrl_get_INTEN_DFLLOOB_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLOOB) >> OSCCTRL_INTENSET_DFLLOOB_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DFLLOOB_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLOOB; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLOOB; + } +} + +static inline void hri_oscctrl_clear_INTEN_DFLLOOB_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLOOB; +} + +static inline void hri_oscctrl_set_INTEN_DFLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKF; +} + +static inline bool hri_oscctrl_get_INTEN_DFLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLLCKF) >> OSCCTRL_INTENSET_DFLLLCKF_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DFLLLCKF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKF; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKF; + } +} + +static inline void hri_oscctrl_clear_INTEN_DFLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKF; +} + +static inline void hri_oscctrl_set_INTEN_DFLLLCKC_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKC; +} + +static inline bool hri_oscctrl_get_INTEN_DFLLLCKC_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLLCKC) >> OSCCTRL_INTENSET_DFLLLCKC_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DFLLLCKC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKC; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKC; + } +} + +static inline void hri_oscctrl_clear_INTEN_DFLLLCKC_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKC; +} + +static inline void hri_oscctrl_set_INTEN_DFLLRCS_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRCS; +} + +static inline bool hri_oscctrl_get_INTEN_DFLLRCS_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLRCS) >> OSCCTRL_INTENSET_DFLLRCS_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DFLLRCS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRCS; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRCS; + } +} + +static inline void hri_oscctrl_clear_INTEN_DFLLRCS_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRCS; +} + +static inline void hri_oscctrl_set_INTEN_DPLLLCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLCKR; +} + +static inline bool hri_oscctrl_get_INTEN_DPLLLCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLLLCKR) >> OSCCTRL_INTENSET_DPLLLCKR_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLLLCKR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLCKR; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLCKR; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLLLCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLCKR; +} + +static inline void hri_oscctrl_set_INTEN_DPLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLCKF; +} + +static inline bool hri_oscctrl_get_INTEN_DPLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLLLCKF) >> OSCCTRL_INTENSET_DPLLLCKF_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLLLCKF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLCKF; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLCKF; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLCKF; +} + +static inline void hri_oscctrl_set_INTEN_DPLLLTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLTO; +} + +static inline bool hri_oscctrl_get_INTEN_DPLLLTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLLLTO) >> OSCCTRL_INTENSET_DPLLLTO_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLLLTO_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLTO; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLTO; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLLLTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLTO; +} + +static inline void hri_oscctrl_set_INTEN_DPLLLDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLDRTO; +} + +static inline bool hri_oscctrl_get_INTEN_DPLLLDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLLLDRTO) >> OSCCTRL_INTENSET_DPLLLDRTO_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLLLDRTO_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLDRTO; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLDRTO; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLLLDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLDRTO; +} + +static inline void hri_oscctrl_set_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t mask) +{ + ((Oscctrl *)hw)->INTENSET.reg = mask; +} + +static inline hri_oscctrl_intenset_reg_t hri_oscctrl_get_INTEN_reg(const void *const hw, + hri_oscctrl_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_intenset_reg_t hri_oscctrl_read_INTEN_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->INTENSET.reg; +} + +static inline void hri_oscctrl_write_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t data) +{ + ((Oscctrl *)hw)->INTENSET.reg = data; + ((Oscctrl *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_oscctrl_clear_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t mask) +{ + ((Oscctrl *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_oscctrl_get_STATUS_XOSCRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCRDY) >> OSCCTRL_STATUS_XOSCRDY_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_OSC16MRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_OSC16MRDY) >> OSCCTRL_STATUS_OSC16MRDY_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DFLLRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLRDY) >> OSCCTRL_STATUS_DFLLRDY_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DFLLOOB_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLOOB) >> OSCCTRL_STATUS_DFLLOOB_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DFLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLLCKF) >> OSCCTRL_STATUS_DFLLLCKF_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DFLLLCKC_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLLCKC) >> OSCCTRL_STATUS_DFLLLCKC_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DFLLRCS_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLRCS) >> OSCCTRL_STATUS_DFLLRCS_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLLLCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLLLCKR) >> OSCCTRL_STATUS_DPLLLCKR_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLLLCKF) >> OSCCTRL_STATUS_DPLLLCKF_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLLTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLLTO) >> OSCCTRL_STATUS_DPLLTO_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLLLDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLLLDRTO) >> OSCCTRL_STATUS_DPLLLDRTO_Pos; +} + +static inline hri_oscctrl_status_reg_t hri_oscctrl_get_STATUS_reg(const void *const hw, hri_oscctrl_status_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_status_reg_t hri_oscctrl_read_STATUS_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->STATUS.reg; +} + +static inline bool hri_oscctrl_get_DPLLSYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_ENABLE) >> OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_oscctrl_get_DPLLSYNCBUSY_DPLLRATIO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLRATIO) >> OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos; +} + +static inline bool hri_oscctrl_get_DPLLSYNCBUSY_DPLLPRESC_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLPRESC) >> OSCCTRL_DPLLSYNCBUSY_DPLLPRESC_Pos; +} + +static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrl_get_DPLLSYNCBUSY_reg(const void *const hw, + hri_oscctrl_dpllsyncbusy_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DPLLSYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrl_read_DPLLSYNCBUSY_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DPLLSYNCBUSY.reg; +} + +static inline bool hri_oscctrl_get_DPLLSTATUS_LOCK_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_LOCK) >> OSCCTRL_DPLLSTATUS_LOCK_Pos; +} + +static inline bool hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY) >> OSCCTRL_DPLLSTATUS_CLKRDY_Pos; +} + +static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrl_get_DPLLSTATUS_reg(const void *const hw, + hri_oscctrl_dpllstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DPLLSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrl_read_DPLLSTATUS_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DPLLSTATUS.reg; +} + +static inline void hri_oscctrl_set_XOSCCTRL_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_ENABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_ENABLE) >> OSCCTRL_XOSCCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= ~OSCCTRL_XOSCCTRL_ENABLE; + tmp |= value << OSCCTRL_XOSCCTRL_ENABLE_Pos; + ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_ENABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_ENABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_XTALEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_XTALEN; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_XTALEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_XTALEN) >> OSCCTRL_XOSCCTRL_XTALEN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_XTALEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= ~OSCCTRL_XOSCCTRL_XTALEN; + tmp |= value << OSCCTRL_XOSCCTRL_XTALEN_Pos; + ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_XTALEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_XTALEN; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_XTALEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_XTALEN; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_RUNSTDBY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_RUNSTDBY) >> OSCCTRL_XOSCCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= ~OSCCTRL_XOSCCTRL_RUNSTDBY; + tmp |= value << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos; + ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_ONDEMAND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_ONDEMAND) >> OSCCTRL_XOSCCTRL_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_ONDEMAND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= ~OSCCTRL_XOSCCTRL_ONDEMAND; + tmp |= value << OSCCTRL_XOSCCTRL_ONDEMAND_Pos; + ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_AMPGC_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_AMPGC; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_AMPGC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_AMPGC) >> OSCCTRL_XOSCCTRL_AMPGC_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_AMPGC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= ~OSCCTRL_XOSCCTRL_AMPGC; + tmp |= value << OSCCTRL_XOSCCTRL_AMPGC_Pos; + ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_AMPGC_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_AMPGC; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_AMPGC_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_AMPGC; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_GAIN_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_GAIN(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_GAIN_bf(const void *const hw, + hri_oscctrl_xoscctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_GAIN(mask)) >> OSCCTRL_XOSCCTRL_GAIN_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_GAIN_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t data) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= ~OSCCTRL_XOSCCTRL_GAIN_Msk; + tmp |= OSCCTRL_XOSCCTRL_GAIN(data); + ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_GAIN_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_GAIN(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_GAIN_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_GAIN(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_GAIN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_GAIN_Msk) >> OSCCTRL_XOSCCTRL_GAIN_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_XOSCCTRL_STARTUP_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_STARTUP(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_STARTUP_bf(const void *const hw, + hri_oscctrl_xoscctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_STARTUP(mask)) >> OSCCTRL_XOSCCTRL_STARTUP_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_STARTUP_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t data) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= ~OSCCTRL_XOSCCTRL_STARTUP_Msk; + tmp |= OSCCTRL_XOSCCTRL_STARTUP(data); + ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_STARTUP_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_STARTUP(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_STARTUP_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_STARTUP(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_STARTUP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_STARTUP_Msk) >> OSCCTRL_XOSCCTRL_STARTUP_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_XOSCCTRL_reg(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_reg(const void *const hw, + hri_oscctrl_xoscctrl_reg_t mask) +{ + uint16_t tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_reg(const void *const hw, hri_oscctrl_xoscctrl_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg = data; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_reg(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_reg(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_reg(const void *const hw) +{ + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + return ((Oscctrl *)hw)->XOSCCTRL.reg; +} + +static inline void hri_oscctrl_set_OSC16MCTRL_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg |= OSCCTRL_OSC16MCTRL_ENABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_OSC16MCTRL_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg; + tmp = (tmp & OSCCTRL_OSC16MCTRL_ENABLE) >> OSCCTRL_OSC16MCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_OSC16MCTRL_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg; + tmp &= ~OSCCTRL_OSC16MCTRL_ENABLE; + tmp |= value << OSCCTRL_OSC16MCTRL_ENABLE_Pos; + ((Oscctrl *)hw)->OSC16MCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_OSC16MCTRL_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg &= ~OSCCTRL_OSC16MCTRL_ENABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_OSC16MCTRL_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg ^= OSCCTRL_OSC16MCTRL_ENABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_OSC16MCTRL_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg |= OSCCTRL_OSC16MCTRL_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_OSC16MCTRL_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg; + tmp = (tmp & OSCCTRL_OSC16MCTRL_RUNSTDBY) >> OSCCTRL_OSC16MCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_OSC16MCTRL_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg; + tmp &= ~OSCCTRL_OSC16MCTRL_RUNSTDBY; + tmp |= value << OSCCTRL_OSC16MCTRL_RUNSTDBY_Pos; + ((Oscctrl *)hw)->OSC16MCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_OSC16MCTRL_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg &= ~OSCCTRL_OSC16MCTRL_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_OSC16MCTRL_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg ^= OSCCTRL_OSC16MCTRL_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_OSC16MCTRL_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg |= OSCCTRL_OSC16MCTRL_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_OSC16MCTRL_ONDEMAND_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg; + tmp = (tmp & OSCCTRL_OSC16MCTRL_ONDEMAND) >> OSCCTRL_OSC16MCTRL_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_OSC16MCTRL_ONDEMAND_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg; + tmp &= ~OSCCTRL_OSC16MCTRL_ONDEMAND; + tmp |= value << OSCCTRL_OSC16MCTRL_ONDEMAND_Pos; + ((Oscctrl *)hw)->OSC16MCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_OSC16MCTRL_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg &= ~OSCCTRL_OSC16MCTRL_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_OSC16MCTRL_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg ^= OSCCTRL_OSC16MCTRL_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_OSC16MCTRL_FSEL_bf(const void *const hw, hri_oscctrl_osc16mctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg |= OSCCTRL_OSC16MCTRL_FSEL(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_osc16mctrl_reg_t hri_oscctrl_get_OSC16MCTRL_FSEL_bf(const void *const hw, + hri_oscctrl_osc16mctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg; + tmp = (tmp & OSCCTRL_OSC16MCTRL_FSEL(mask)) >> OSCCTRL_OSC16MCTRL_FSEL_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_OSC16MCTRL_FSEL_bf(const void *const hw, hri_oscctrl_osc16mctrl_reg_t data) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg; + tmp &= ~OSCCTRL_OSC16MCTRL_FSEL_Msk; + tmp |= OSCCTRL_OSC16MCTRL_FSEL(data); + ((Oscctrl *)hw)->OSC16MCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_OSC16MCTRL_FSEL_bf(const void *const hw, hri_oscctrl_osc16mctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg &= ~OSCCTRL_OSC16MCTRL_FSEL(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_OSC16MCTRL_FSEL_bf(const void *const hw, hri_oscctrl_osc16mctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg ^= OSCCTRL_OSC16MCTRL_FSEL(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_osc16mctrl_reg_t hri_oscctrl_read_OSC16MCTRL_FSEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg; + tmp = (tmp & OSCCTRL_OSC16MCTRL_FSEL_Msk) >> OSCCTRL_OSC16MCTRL_FSEL_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_OSC16MCTRL_reg(const void *const hw, hri_oscctrl_osc16mctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg |= mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_osc16mctrl_reg_t hri_oscctrl_get_OSC16MCTRL_reg(const void *const hw, + hri_oscctrl_osc16mctrl_reg_t mask) +{ + uint8_t tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_OSC16MCTRL_reg(const void *const hw, hri_oscctrl_osc16mctrl_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg = data; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_OSC16MCTRL_reg(const void *const hw, hri_oscctrl_osc16mctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg &= ~mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_OSC16MCTRL_reg(const void *const hw, hri_oscctrl_osc16mctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg ^= mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_osc16mctrl_reg_t hri_oscctrl_read_OSC16MCTRL_reg(const void *const hw) +{ + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + return ((Oscctrl *)hw)->OSC16MCTRL.reg; +} + +static inline void hri_oscctrl_set_DFLLCTRL_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_ENABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRL_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & OSCCTRL_DFLLCTRL_ENABLE) >> OSCCTRL_DFLLCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRL_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp &= ~OSCCTRL_DFLLCTRL_ENABLE; + tmp |= value << OSCCTRL_DFLLCTRL_ENABLE_Pos; + ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRL_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_ENABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRL_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_ENABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRL_MODE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_MODE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRL_MODE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & OSCCTRL_DFLLCTRL_MODE) >> OSCCTRL_DFLLCTRL_MODE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRL_MODE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp &= ~OSCCTRL_DFLLCTRL_MODE; + tmp |= value << OSCCTRL_DFLLCTRL_MODE_Pos; + ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRL_MODE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_MODE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRL_MODE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_MODE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRL_STABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_STABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRL_STABLE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & OSCCTRL_DFLLCTRL_STABLE) >> OSCCTRL_DFLLCTRL_STABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRL_STABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp &= ~OSCCTRL_DFLLCTRL_STABLE; + tmp |= value << OSCCTRL_DFLLCTRL_STABLE_Pos; + ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRL_STABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_STABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRL_STABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_STABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRL_LLAW_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_LLAW; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRL_LLAW_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & OSCCTRL_DFLLCTRL_LLAW) >> OSCCTRL_DFLLCTRL_LLAW_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRL_LLAW_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp &= ~OSCCTRL_DFLLCTRL_LLAW; + tmp |= value << OSCCTRL_DFLLCTRL_LLAW_Pos; + ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRL_LLAW_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_LLAW; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRL_LLAW_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_LLAW; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRL_USBCRM_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_USBCRM; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRL_USBCRM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & OSCCTRL_DFLLCTRL_USBCRM) >> OSCCTRL_DFLLCTRL_USBCRM_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRL_USBCRM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp &= ~OSCCTRL_DFLLCTRL_USBCRM; + tmp |= value << OSCCTRL_DFLLCTRL_USBCRM_Pos; + ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRL_USBCRM_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_USBCRM; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRL_USBCRM_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_USBCRM; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRL_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRL_RUNSTDBY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & OSCCTRL_DFLLCTRL_RUNSTDBY) >> OSCCTRL_DFLLCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRL_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp &= ~OSCCTRL_DFLLCTRL_RUNSTDBY; + tmp |= value << OSCCTRL_DFLLCTRL_RUNSTDBY_Pos; + ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRL_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRL_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRL_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRL_ONDEMAND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & OSCCTRL_DFLLCTRL_ONDEMAND) >> OSCCTRL_DFLLCTRL_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRL_ONDEMAND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp &= ~OSCCTRL_DFLLCTRL_ONDEMAND; + tmp |= value << OSCCTRL_DFLLCTRL_ONDEMAND_Pos; + ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRL_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRL_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRL_CCDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_CCDIS; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRL_CCDIS_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & OSCCTRL_DFLLCTRL_CCDIS) >> OSCCTRL_DFLLCTRL_CCDIS_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRL_CCDIS_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp &= ~OSCCTRL_DFLLCTRL_CCDIS; + tmp |= value << OSCCTRL_DFLLCTRL_CCDIS_Pos; + ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRL_CCDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_CCDIS; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRL_CCDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_CCDIS; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRL_QLDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_QLDIS; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRL_QLDIS_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & OSCCTRL_DFLLCTRL_QLDIS) >> OSCCTRL_DFLLCTRL_QLDIS_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRL_QLDIS_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp &= ~OSCCTRL_DFLLCTRL_QLDIS; + tmp |= value << OSCCTRL_DFLLCTRL_QLDIS_Pos; + ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRL_QLDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_QLDIS; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRL_QLDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_QLDIS; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRL_BPLCKC_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_BPLCKC; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRL_BPLCKC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & OSCCTRL_DFLLCTRL_BPLCKC) >> OSCCTRL_DFLLCTRL_BPLCKC_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRL_BPLCKC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp &= ~OSCCTRL_DFLLCTRL_BPLCKC; + tmp |= value << OSCCTRL_DFLLCTRL_BPLCKC_Pos; + ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRL_BPLCKC_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_BPLCKC; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRL_BPLCKC_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_BPLCKC; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRL_WAITLOCK_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_WAITLOCK; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRL_WAITLOCK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & OSCCTRL_DFLLCTRL_WAITLOCK) >> OSCCTRL_DFLLCTRL_WAITLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRL_WAITLOCK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp &= ~OSCCTRL_DFLLCTRL_WAITLOCK; + tmp |= value << OSCCTRL_DFLLCTRL_WAITLOCK_Pos; + ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRL_WAITLOCK_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_WAITLOCK; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRL_WAITLOCK_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_WAITLOCK; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRL_reg(const void *const hw, hri_oscctrl_dfllctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg |= mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllctrl_reg_t hri_oscctrl_get_DFLLCTRL_reg(const void *const hw, + hri_oscctrl_dfllctrl_reg_t mask) +{ + uint16_t tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRL_reg(const void *const hw, hri_oscctrl_dfllctrl_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg = data; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRL_reg(const void *const hw, hri_oscctrl_dfllctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg &= ~mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRL_reg(const void *const hw, hri_oscctrl_dfllctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg ^= mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllctrl_reg_t hri_oscctrl_read_DFLLCTRL_reg(const void *const hw) +{ + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + return ((Oscctrl *)hw)->DFLLCTRL.reg; +} + +static inline void hri_oscctrl_set_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_FINE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_FINE_bf(const void *const hw, + hri_oscctrl_dfllval_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_FINE(mask)) >> OSCCTRL_DFLLVAL_FINE_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp &= ~OSCCTRL_DFLLVAL_FINE_Msk; + tmp |= OSCCTRL_DFLLVAL_FINE(data); + ((Oscctrl *)hw)->DFLLVAL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_FINE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_FINE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_FINE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_FINE_Msk) >> OSCCTRL_DFLLVAL_FINE_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_COARSE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_COARSE_bf(const void *const hw, + hri_oscctrl_dfllval_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_COARSE(mask)) >> OSCCTRL_DFLLVAL_COARSE_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp &= ~OSCCTRL_DFLLVAL_COARSE_Msk; + tmp |= OSCCTRL_DFLLVAL_COARSE(data); + ((Oscctrl *)hw)->DFLLVAL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_COARSE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_COARSE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_COARSE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_COARSE_Msk) >> OSCCTRL_DFLLVAL_COARSE_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_DIFF(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_DIFF_bf(const void *const hw, + hri_oscctrl_dfllval_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_DIFF(mask)) >> OSCCTRL_DFLLVAL_DIFF_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp &= ~OSCCTRL_DFLLVAL_DIFF_Msk; + tmp |= OSCCTRL_DFLLVAL_DIFF(data); + ((Oscctrl *)hw)->DFLLVAL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_DIFF(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_DIFF(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_DIFF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_DIFF_Msk) >> OSCCTRL_DFLLVAL_DIFF_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_reg(const void *const hw, + hri_oscctrl_dfllval_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DFLLVAL.reg; +} + +static inline void hri_oscctrl_set_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_MUL(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_MUL_bf(const void *const hw, + hri_oscctrl_dfllmul_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_MUL(mask)) >> OSCCTRL_DFLLMUL_MUL_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp &= ~OSCCTRL_DFLLMUL_MUL_Msk; + tmp |= OSCCTRL_DFLLMUL_MUL(data); + ((Oscctrl *)hw)->DFLLMUL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_MUL(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_MUL(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_MUL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_MUL_Msk) >> OSCCTRL_DFLLMUL_MUL_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_FSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_FSTEP_bf(const void *const hw, + hri_oscctrl_dfllmul_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_FSTEP(mask)) >> OSCCTRL_DFLLMUL_FSTEP_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp &= ~OSCCTRL_DFLLMUL_FSTEP_Msk; + tmp |= OSCCTRL_DFLLMUL_FSTEP(data); + ((Oscctrl *)hw)->DFLLMUL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_FSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_FSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_FSTEP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_FSTEP_Msk) >> OSCCTRL_DFLLMUL_FSTEP_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_CSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_CSTEP_bf(const void *const hw, + hri_oscctrl_dfllmul_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_CSTEP(mask)) >> OSCCTRL_DFLLMUL_CSTEP_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp &= ~OSCCTRL_DFLLMUL_CSTEP_Msk; + tmp |= OSCCTRL_DFLLMUL_CSTEP(data); + ((Oscctrl *)hw)->DFLLMUL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_CSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_CSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_CSTEP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_CSTEP_Msk) >> OSCCTRL_DFLLMUL_CSTEP_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_reg(const void *const hw, + hri_oscctrl_dfllmul_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DFLLMUL.reg; +} + +static inline void hri_oscctrl_set_DFLLSYNC_READREQ_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_READREQ; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLSYNC_READREQ_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp = (tmp & OSCCTRL_DFLLSYNC_READREQ) >> OSCCTRL_DFLLSYNC_READREQ_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLSYNC_READREQ_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp &= ~OSCCTRL_DFLLSYNC_READREQ; + tmp |= value << OSCCTRL_DFLLSYNC_READREQ_Pos; + ((Oscctrl *)hw)->DFLLSYNC.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLSYNC_READREQ_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_READREQ; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLSYNC_READREQ_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_READREQ; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllsync_reg_t hri_oscctrl_get_DFLLSYNC_reg(const void *const hw, + hri_oscctrl_dfllsync_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllsync_reg_t hri_oscctrl_read_DFLLSYNC_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DFLLSYNC.reg; +} + +static inline void hri_oscctrl_set_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ENABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_ENABLE) >> OSCCTRL_DPLLCTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_ENABLE; + tmp |= value << OSCCTRL_DPLLCTRLA_ENABLE_Pos; + ((Oscctrl *)hw)->DPLLCTRLA.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ENABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ENABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_RUNSTDBY) >> OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; + tmp |= value << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; + ((Oscctrl *)hw)->DPLLCTRLA.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_ONDEMAND) >> OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLA_ONDEMAND_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; + tmp |= value << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; + ((Oscctrl *)hw)->DPLLCTRLA.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg |= mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrl_get_DPLLCTRLA_reg(const void *const hw, + hri_oscctrl_dpllctrla_reg_t mask) +{ + uint8_t tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg = data; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg &= ~mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg ^= mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrl_read_DPLLCTRLA_reg(const void *const hw) +{ + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + return ((Oscctrl *)hw)->DPLLCTRLA.reg; +} + +static inline void hri_oscctrl_set_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDR(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_get_DPLLRATIO_LDR_bf(const void *const hw, + hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDR(mask)) >> OSCCTRL_DPLLRATIO_LDR_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLRATIO.reg; + tmp &= ~OSCCTRL_DPLLRATIO_LDR_Msk; + tmp |= OSCCTRL_DPLLRATIO_LDR(data); + ((Oscctrl *)hw)->DPLLRATIO.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDR(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDR(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_LDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDR_Msk) >> OSCCTRL_DPLLRATIO_LDR_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDRFRAC(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_get_DPLLRATIO_LDRFRAC_bf(const void *const hw, + hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC(mask)) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLRATIO.reg; + tmp &= ~OSCCTRL_DPLLRATIO_LDRFRAC_Msk; + tmp |= OSCCTRL_DPLLRATIO_LDRFRAC(data); + ((Oscctrl *)hw)->DPLLRATIO.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDRFRAC(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDRFRAC(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_LDRFRAC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC_Msk) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg |= mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_get_DPLLRATIO_reg(const void *const hw, + hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + tmp = ((Oscctrl *)hw)->DPLLRATIO.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg = data; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg &= ~mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg ^= mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_reg(const void *const hw) +{ + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + return ((Oscctrl *)hw)->DPLLRATIO.reg; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_LPEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LPEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLB_LPEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LPEN) >> OSCCTRL_DPLLCTRLB_LPEN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_LPEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_LPEN; + tmp |= value << OSCCTRL_DPLLCTRLB_LPEN_Pos; + ((Oscctrl *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_LPEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LPEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_LPEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LPEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLB_WUF_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLB_WUF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_WUF) >> OSCCTRL_DPLLCTRLB_WUF_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_WUF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_WUF; + tmp |= value << OSCCTRL_DPLLCTRLB_WUF_Pos; + ((Oscctrl *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_WUF_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_WUF_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LBYPASS) >> OSCCTRL_DPLLCTRLB_LBYPASS_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_LBYPASS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_LBYPASS; + tmp |= value << OSCCTRL_DPLLCTRLB_LBYPASS_Pos; + ((Oscctrl *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_FILTER_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER(mask)) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_FILTER_Msk; + tmp |= OSCCTRL_DPLLCTRLB_FILTER(data); + ((Oscctrl *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_FILTER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER_Msk) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_REFCLK_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK(mask)) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_REFCLK_Msk; + tmp |= OSCCTRL_DPLLCTRLB_REFCLK(data); + ((Oscctrl *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_REFCLK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK_Msk) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_LTIME_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME(mask)) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_LTIME_Msk; + tmp |= OSCCTRL_DPLLCTRLB_LTIME(data); + ((Oscctrl *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_LTIME_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME_Msk) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_DIV_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV(mask)) >> OSCCTRL_DPLLCTRLB_DIV_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_DIV_Msk; + tmp |= OSCCTRL_DPLLCTRLB_DIV(data); + ((Oscctrl *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_DIV_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV_Msk) >> OSCCTRL_DPLLCTRLB_DIV_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_reg(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DPLLCTRLB.reg; +} + +static inline void hri_oscctrl_set_DPLLPRESC_PRESC_bf(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLPRESC.reg |= OSCCTRL_DPLLPRESC_PRESC(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllpresc_reg_t hri_oscctrl_get_DPLLPRESC_PRESC_bf(const void *const hw, + hri_oscctrl_dpllpresc_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DPLLPRESC.reg; + tmp = (tmp & OSCCTRL_DPLLPRESC_PRESC(mask)) >> OSCCTRL_DPLLPRESC_PRESC_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLPRESC_PRESC_bf(const void *const hw, hri_oscctrl_dpllpresc_reg_t data) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLPRESC.reg; + tmp &= ~OSCCTRL_DPLLPRESC_PRESC_Msk; + tmp |= OSCCTRL_DPLLPRESC_PRESC(data); + ((Oscctrl *)hw)->DPLLPRESC.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLPRESC_PRESC_bf(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLPRESC.reg &= ~OSCCTRL_DPLLPRESC_PRESC(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLPRESC_PRESC_bf(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLPRESC.reg ^= OSCCTRL_DPLLPRESC_PRESC(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllpresc_reg_t hri_oscctrl_read_DPLLPRESC_PRESC_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DPLLPRESC.reg; + tmp = (tmp & OSCCTRL_DPLLPRESC_PRESC_Msk) >> OSCCTRL_DPLLPRESC_PRESC_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLPRESC_reg(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLPRESC.reg |= mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllpresc_reg_t hri_oscctrl_get_DPLLPRESC_reg(const void *const hw, + hri_oscctrl_dpllpresc_reg_t mask) +{ + uint8_t tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + tmp = ((Oscctrl *)hw)->DPLLPRESC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLPRESC_reg(const void *const hw, hri_oscctrl_dpllpresc_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLPRESC.reg = data; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLPRESC_reg(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLPRESC.reg &= ~mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLPRESC_reg(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLPRESC.reg ^= mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllpresc_reg_t hri_oscctrl_read_DPLLPRESC_reg(const void *const hw) +{ + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + return ((Oscctrl *)hw)->DPLLPRESC.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_OSCCTRL_L21_H_INCLUDED */ +#endif /* _SAML21_OSCCTRL_COMPONENT_ */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_pac_l21.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_pac_l21.h new file mode 100644 index 00000000..07997ea6 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_pac_l21.h @@ -0,0 +1,1257 @@ +/** + * \file + * + * \brief SAM PAC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_PAC_COMPONENT_ +#ifndef _HRI_PAC_L21_H_INCLUDED_ +#define _HRI_PAC_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PAC_CRITICAL_SECTIONS) +#define PAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PAC_CRITICAL_SECTION_ENTER() +#define PAC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_pac_intflaga_reg_t; +typedef uint32_t hri_pac_intflagahb_reg_t; +typedef uint32_t hri_pac_intflagb_reg_t; +typedef uint32_t hri_pac_intflagc_reg_t; +typedef uint32_t hri_pac_intflagd_reg_t; +typedef uint32_t hri_pac_intflage_reg_t; +typedef uint32_t hri_pac_statusa_reg_t; +typedef uint32_t hri_pac_statusb_reg_t; +typedef uint32_t hri_pac_statusc_reg_t; +typedef uint32_t hri_pac_statusd_reg_t; +typedef uint32_t hri_pac_statuse_reg_t; +typedef uint32_t hri_pac_wrctrl_reg_t; +typedef uint8_t hri_pac_evctrl_reg_t; +typedef uint8_t hri_pac_intenset_reg_t; + +static inline bool hri_pac_get_INTFLAGAHB_FLASH_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_FLASH) >> PAC_INTFLAGAHB_FLASH_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_FLASH_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_FLASH; +} + +static inline bool hri_pac_get_INTFLAGAHB_HSRAMCM0P_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HSRAMCM0P) >> PAC_INTFLAGAHB_HSRAMCM0P_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HSRAMCM0P_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HSRAMCM0P; +} + +static inline bool hri_pac_get_INTFLAGAHB_HSRAMDSU_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HSRAMDSU) >> PAC_INTFLAGAHB_HSRAMDSU_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HSRAMDSU_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HSRAMDSU; +} + +static inline bool hri_pac_get_INTFLAGAHB_HPB1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB1) >> PAC_INTFLAGAHB_HPB1_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HPB1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB1; +} + +static inline bool hri_pac_get_INTFLAGAHB_H2LBRIDGES_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_H2LBRIDGES) >> PAC_INTFLAGAHB_H2LBRIDGES_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_H2LBRIDGES_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_H2LBRIDGES; +} + +static inline bool hri_pac_get_INTFLAGAHB_HPB0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB0) >> PAC_INTFLAGAHB_HPB0_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HPB0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB0; +} + +static inline bool hri_pac_get_INTFLAGAHB_HPB2_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB2) >> PAC_INTFLAGAHB_HPB2_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HPB2_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB2; +} + +static inline bool hri_pac_get_INTFLAGAHB_HPB3_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB3) >> PAC_INTFLAGAHB_HPB3_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HPB3_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB3; +} + +static inline bool hri_pac_get_INTFLAGAHB_HPB4_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB4) >> PAC_INTFLAGAHB_HPB4_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HPB4_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB4; +} + +static inline bool hri_pac_get_INTFLAGAHB_LPRAMHS_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_LPRAMHS) >> PAC_INTFLAGAHB_LPRAMHS_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_LPRAMHS_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_LPRAMHS; +} + +static inline bool hri_pac_get_INTFLAGAHB_LPRAMPICOP_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_LPRAMPICOP) >> PAC_INTFLAGAHB_LPRAMPICOP_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_LPRAMPICOP_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_LPRAMPICOP; +} + +static inline bool hri_pac_get_INTFLAGAHB_LPRAMDMAC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_LPRAMDMAC) >> PAC_INTFLAGAHB_LPRAMDMAC_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_LPRAMDMAC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_LPRAMDMAC; +} + +static inline bool hri_pac_get_INTFLAGAHB_L2HBRIDGES_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_L2HBRIDGES) >> PAC_INTFLAGAHB_L2HBRIDGES_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_L2HBRIDGES_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_L2HBRIDGES; +} + +static inline bool hri_pac_get_INTFLAGAHB_HSRAMLP_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HSRAMLP) >> PAC_INTFLAGAHB_HSRAMLP_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HSRAMLP_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HSRAMLP; +} + +static inline hri_pac_intflagahb_reg_t hri_pac_get_INTFLAGAHB_reg(const void *const hw, hri_pac_intflagahb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGAHB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflagahb_reg_t hri_pac_read_INTFLAGAHB_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGAHB.reg; +} + +static inline void hri_pac_clear_INTFLAGAHB_reg(const void *const hw, hri_pac_intflagahb_reg_t mask) +{ + ((Pac *)hw)->INTFLAGAHB.reg = mask; +} + +static inline bool hri_pac_get_INTFLAGA_PM_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_PM) >> PAC_INTFLAGA_PM_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_PM_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_PM; +} + +static inline bool hri_pac_get_INTFLAGA_MCLK_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_MCLK) >> PAC_INTFLAGA_MCLK_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_MCLK_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_MCLK; +} + +static inline bool hri_pac_get_INTFLAGA_RSTC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_RSTC) >> PAC_INTFLAGA_RSTC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_RSTC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_RSTC; +} + +static inline bool hri_pac_get_INTFLAGA_OSCCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_OSCCTRL) >> PAC_INTFLAGA_OSCCTRL_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_OSCCTRL_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_OSCCTRL; +} + +static inline bool hri_pac_get_INTFLAGA_OSC32KCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_OSC32KCTRL) >> PAC_INTFLAGA_OSC32KCTRL_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_OSC32KCTRL_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_OSC32KCTRL; +} + +static inline bool hri_pac_get_INTFLAGA_SUPC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SUPC) >> PAC_INTFLAGA_SUPC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_SUPC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SUPC; +} + +static inline bool hri_pac_get_INTFLAGA_GCLK_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_GCLK) >> PAC_INTFLAGA_GCLK_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_GCLK_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_GCLK; +} + +static inline bool hri_pac_get_INTFLAGA_WDT_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_WDT) >> PAC_INTFLAGA_WDT_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_WDT_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_WDT; +} + +static inline bool hri_pac_get_INTFLAGA_RTC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_RTC) >> PAC_INTFLAGA_RTC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_RTC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_RTC; +} + +static inline bool hri_pac_get_INTFLAGA_EIC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_EIC) >> PAC_INTFLAGA_EIC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_EIC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_EIC; +} + +static inline bool hri_pac_get_INTFLAGA_PORT_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_PORT) >> PAC_INTFLAGA_PORT_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_PORT_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_PORT; +} + +static inline hri_pac_intflaga_reg_t hri_pac_get_INTFLAGA_reg(const void *const hw, hri_pac_intflaga_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflaga_reg_t hri_pac_read_INTFLAGA_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGA.reg; +} + +static inline void hri_pac_clear_INTFLAGA_reg(const void *const hw, hri_pac_intflaga_reg_t mask) +{ + ((Pac *)hw)->INTFLAGA.reg = mask; +} + +static inline bool hri_pac_get_INTFLAGB_USB_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_USB) >> PAC_INTFLAGB_USB_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_USB_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_USB; +} + +static inline bool hri_pac_get_INTFLAGB_DSU_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_DSU) >> PAC_INTFLAGB_DSU_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_DSU_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_DSU; +} + +static inline bool hri_pac_get_INTFLAGB_NVMCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_NVMCTRL) >> PAC_INTFLAGB_NVMCTRL_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_NVMCTRL_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_NVMCTRL; +} + +static inline bool hri_pac_get_INTFLAGB_MTB_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_MTB) >> PAC_INTFLAGB_MTB_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_MTB_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_MTB; +} + +static inline hri_pac_intflagb_reg_t hri_pac_get_INTFLAGB_reg(const void *const hw, hri_pac_intflagb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflagb_reg_t hri_pac_read_INTFLAGB_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGB.reg; +} + +static inline void hri_pac_clear_INTFLAGB_reg(const void *const hw, hri_pac_intflagb_reg_t mask) +{ + ((Pac *)hw)->INTFLAGB.reg = mask; +} + +static inline bool hri_pac_get_INTFLAGC_SERCOM0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM0) >> PAC_INTFLAGC_SERCOM0_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_SERCOM0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM0; +} + +static inline bool hri_pac_get_INTFLAGC_SERCOM1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM1) >> PAC_INTFLAGC_SERCOM1_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_SERCOM1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM1; +} + +static inline bool hri_pac_get_INTFLAGC_SERCOM2_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM2) >> PAC_INTFLAGC_SERCOM2_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_SERCOM2_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM2; +} + +static inline bool hri_pac_get_INTFLAGC_SERCOM3_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM3) >> PAC_INTFLAGC_SERCOM3_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_SERCOM3_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM3; +} + +static inline bool hri_pac_get_INTFLAGC_SERCOM4_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM4) >> PAC_INTFLAGC_SERCOM4_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_SERCOM4_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM4; +} + +static inline bool hri_pac_get_INTFLAGC_TCC0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TCC0) >> PAC_INTFLAGC_TCC0_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TCC0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TCC0; +} + +static inline bool hri_pac_get_INTFLAGC_TCC1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TCC1) >> PAC_INTFLAGC_TCC1_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TCC1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TCC1; +} + +static inline bool hri_pac_get_INTFLAGC_TCC2_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TCC2) >> PAC_INTFLAGC_TCC2_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TCC2_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TCC2; +} + +static inline bool hri_pac_get_INTFLAGC_TC0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC0) >> PAC_INTFLAGC_TC0_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TC0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC0; +} + +static inline bool hri_pac_get_INTFLAGC_TC1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC1) >> PAC_INTFLAGC_TC1_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TC1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC1; +} + +static inline bool hri_pac_get_INTFLAGC_TC2_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC2) >> PAC_INTFLAGC_TC2_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TC2_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC2; +} + +static inline bool hri_pac_get_INTFLAGC_TC3_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC3) >> PAC_INTFLAGC_TC3_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TC3_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC3; +} + +static inline bool hri_pac_get_INTFLAGC_DAC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_DAC) >> PAC_INTFLAGC_DAC_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_DAC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_DAC; +} + +static inline bool hri_pac_get_INTFLAGC_AES_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_AES) >> PAC_INTFLAGC_AES_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_AES_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_AES; +} + +static inline bool hri_pac_get_INTFLAGC_TRNG_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TRNG) >> PAC_INTFLAGC_TRNG_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TRNG_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TRNG; +} + +static inline hri_pac_intflagc_reg_t hri_pac_get_INTFLAGC_reg(const void *const hw, hri_pac_intflagc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGC.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflagc_reg_t hri_pac_read_INTFLAGC_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGC.reg; +} + +static inline void hri_pac_clear_INTFLAGC_reg(const void *const hw, hri_pac_intflagc_reg_t mask) +{ + ((Pac *)hw)->INTFLAGC.reg = mask; +} + +static inline bool hri_pac_get_INTFLAGD_EVSYS_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_EVSYS) >> PAC_INTFLAGD_EVSYS_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_EVSYS_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_EVSYS; +} + +static inline bool hri_pac_get_INTFLAGD_SERCOM5_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM5) >> PAC_INTFLAGD_SERCOM5_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_SERCOM5_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM5; +} + +static inline bool hri_pac_get_INTFLAGD_TC4_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_TC4) >> PAC_INTFLAGD_TC4_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_TC4_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_TC4; +} + +static inline bool hri_pac_get_INTFLAGD_ADC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_ADC) >> PAC_INTFLAGD_ADC_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_ADC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_ADC; +} + +static inline bool hri_pac_get_INTFLAGD_AC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_AC) >> PAC_INTFLAGD_AC_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_AC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_AC; +} + +static inline bool hri_pac_get_INTFLAGD_PTC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_PTC) >> PAC_INTFLAGD_PTC_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_PTC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_PTC; +} + +static inline bool hri_pac_get_INTFLAGD_OPAMP_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_OPAMP) >> PAC_INTFLAGD_OPAMP_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_OPAMP_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_OPAMP; +} + +static inline bool hri_pac_get_INTFLAGD_CCL_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_CCL) >> PAC_INTFLAGD_CCL_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_CCL_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_CCL; +} + +static inline hri_pac_intflagd_reg_t hri_pac_get_INTFLAGD_reg(const void *const hw, hri_pac_intflagd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGD.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflagd_reg_t hri_pac_read_INTFLAGD_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGD.reg; +} + +static inline void hri_pac_clear_INTFLAGD_reg(const void *const hw, hri_pac_intflagd_reg_t mask) +{ + ((Pac *)hw)->INTFLAGD.reg = mask; +} + +static inline bool hri_pac_get_INTFLAGE_PAC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGE.reg & PAC_INTFLAGE_PAC) >> PAC_INTFLAGE_PAC_Pos; +} + +static inline void hri_pac_clear_INTFLAGE_PAC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGE.reg = PAC_INTFLAGE_PAC; +} + +static inline bool hri_pac_get_INTFLAGE_DMAC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGE.reg & PAC_INTFLAGE_DMAC) >> PAC_INTFLAGE_DMAC_Pos; +} + +static inline void hri_pac_clear_INTFLAGE_DMAC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGE.reg = PAC_INTFLAGE_DMAC; +} + +static inline hri_pac_intflage_reg_t hri_pac_get_INTFLAGE_reg(const void *const hw, hri_pac_intflage_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflage_reg_t hri_pac_read_INTFLAGE_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGE.reg; +} + +static inline void hri_pac_clear_INTFLAGE_reg(const void *const hw, hri_pac_intflage_reg_t mask) +{ + ((Pac *)hw)->INTFLAGE.reg = mask; +} + +static inline void hri_pac_set_INTEN_ERR_bit(const void *const hw) +{ + ((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR; +} + +static inline bool hri_pac_get_INTEN_ERR_bit(const void *const hw) +{ + return (((Pac *)hw)->INTENSET.reg & PAC_INTENSET_ERR) >> PAC_INTENSET_ERR_Pos; +} + +static inline void hri_pac_write_INTEN_ERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR; + } else { + ((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR; + } +} + +static inline void hri_pac_clear_INTEN_ERR_bit(const void *const hw) +{ + ((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR; +} + +static inline void hri_pac_set_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) +{ + ((Pac *)hw)->INTENSET.reg = mask; +} + +static inline hri_pac_intenset_reg_t hri_pac_get_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pac *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intenset_reg_t hri_pac_read_INTEN_reg(const void *const hw) +{ + return ((Pac *)hw)->INTENSET.reg; +} + +static inline void hri_pac_write_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t data) +{ + ((Pac *)hw)->INTENSET.reg = data; + ((Pac *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_pac_clear_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) +{ + ((Pac *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_pac_get_STATUSA_PM_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_PM) >> PAC_STATUSA_PM_Pos; +} + +static inline bool hri_pac_get_STATUSA_MCLK_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_MCLK) >> PAC_STATUSA_MCLK_Pos; +} + +static inline bool hri_pac_get_STATUSA_RSTC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_RSTC) >> PAC_STATUSA_RSTC_Pos; +} + +static inline bool hri_pac_get_STATUSA_OSCCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_OSCCTRL) >> PAC_STATUSA_OSCCTRL_Pos; +} + +static inline bool hri_pac_get_STATUSA_OSC32KCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_OSC32KCTRL) >> PAC_STATUSA_OSC32KCTRL_Pos; +} + +static inline bool hri_pac_get_STATUSA_SUPC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SUPC) >> PAC_STATUSA_SUPC_Pos; +} + +static inline bool hri_pac_get_STATUSA_GCLK_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_GCLK) >> PAC_STATUSA_GCLK_Pos; +} + +static inline bool hri_pac_get_STATUSA_WDT_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_WDT) >> PAC_STATUSA_WDT_Pos; +} + +static inline bool hri_pac_get_STATUSA_RTC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_RTC) >> PAC_STATUSA_RTC_Pos; +} + +static inline bool hri_pac_get_STATUSA_EIC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_EIC) >> PAC_STATUSA_EIC_Pos; +} + +static inline bool hri_pac_get_STATUSA_PORT_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_PORT) >> PAC_STATUSA_PORT_Pos; +} + +static inline hri_pac_statusa_reg_t hri_pac_get_STATUSA_reg(const void *const hw, hri_pac_statusa_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->STATUSA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_statusa_reg_t hri_pac_read_STATUSA_reg(const void *const hw) +{ + return ((Pac *)hw)->STATUSA.reg; +} + +static inline bool hri_pac_get_STATUSB_USB_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_USB) >> PAC_STATUSB_USB_Pos; +} + +static inline bool hri_pac_get_STATUSB_DSU_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_DSU) >> PAC_STATUSB_DSU_Pos; +} + +static inline bool hri_pac_get_STATUSB_NVMCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_NVMCTRL) >> PAC_STATUSB_NVMCTRL_Pos; +} + +static inline bool hri_pac_get_STATUSB_MTB_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_MTB) >> PAC_STATUSB_MTB_Pos; +} + +static inline hri_pac_statusb_reg_t hri_pac_get_STATUSB_reg(const void *const hw, hri_pac_statusb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->STATUSB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_statusb_reg_t hri_pac_read_STATUSB_reg(const void *const hw) +{ + return ((Pac *)hw)->STATUSB.reg; +} + +static inline bool hri_pac_get_STATUSC_SERCOM0_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM0) >> PAC_STATUSC_SERCOM0_Pos; +} + +static inline bool hri_pac_get_STATUSC_SERCOM1_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM1) >> PAC_STATUSC_SERCOM1_Pos; +} + +static inline bool hri_pac_get_STATUSC_SERCOM2_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM2) >> PAC_STATUSC_SERCOM2_Pos; +} + +static inline bool hri_pac_get_STATUSC_SERCOM3_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM3) >> PAC_STATUSC_SERCOM3_Pos; +} + +static inline bool hri_pac_get_STATUSC_SERCOM4_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM4) >> PAC_STATUSC_SERCOM4_Pos; +} + +static inline bool hri_pac_get_STATUSC_TCC0_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TCC0) >> PAC_STATUSC_TCC0_Pos; +} + +static inline bool hri_pac_get_STATUSC_TCC1_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TCC1) >> PAC_STATUSC_TCC1_Pos; +} + +static inline bool hri_pac_get_STATUSC_TCC2_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TCC2) >> PAC_STATUSC_TCC2_Pos; +} + +static inline bool hri_pac_get_STATUSC_TC0_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC0) >> PAC_STATUSC_TC0_Pos; +} + +static inline bool hri_pac_get_STATUSC_TC1_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC1) >> PAC_STATUSC_TC1_Pos; +} + +static inline bool hri_pac_get_STATUSC_TC2_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC2) >> PAC_STATUSC_TC2_Pos; +} + +static inline bool hri_pac_get_STATUSC_TC3_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC3) >> PAC_STATUSC_TC3_Pos; +} + +static inline bool hri_pac_get_STATUSC_DAC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_DAC) >> PAC_STATUSC_DAC_Pos; +} + +static inline bool hri_pac_get_STATUSC_AES_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_AES) >> PAC_STATUSC_AES_Pos; +} + +static inline bool hri_pac_get_STATUSC_TRNG_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TRNG) >> PAC_STATUSC_TRNG_Pos; +} + +static inline hri_pac_statusc_reg_t hri_pac_get_STATUSC_reg(const void *const hw, hri_pac_statusc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->STATUSC.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_statusc_reg_t hri_pac_read_STATUSC_reg(const void *const hw) +{ + return ((Pac *)hw)->STATUSC.reg; +} + +static inline bool hri_pac_get_STATUSD_EVSYS_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_EVSYS) >> PAC_STATUSD_EVSYS_Pos; +} + +static inline bool hri_pac_get_STATUSD_SERCOM5_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM5) >> PAC_STATUSD_SERCOM5_Pos; +} + +static inline bool hri_pac_get_STATUSD_TC4_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_TC4) >> PAC_STATUSD_TC4_Pos; +} + +static inline bool hri_pac_get_STATUSD_ADC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_ADC) >> PAC_STATUSD_ADC_Pos; +} + +static inline bool hri_pac_get_STATUSD_AC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_AC) >> PAC_STATUSD_AC_Pos; +} + +static inline bool hri_pac_get_STATUSD_PTC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_PTC) >> PAC_STATUSD_PTC_Pos; +} + +static inline bool hri_pac_get_STATUSD_OPAMP_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_OPAMP) >> PAC_STATUSD_OPAMP_Pos; +} + +static inline bool hri_pac_get_STATUSD_CCL_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_CCL) >> PAC_STATUSD_CCL_Pos; +} + +static inline hri_pac_statusd_reg_t hri_pac_get_STATUSD_reg(const void *const hw, hri_pac_statusd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->STATUSD.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_statusd_reg_t hri_pac_read_STATUSD_reg(const void *const hw) +{ + return ((Pac *)hw)->STATUSD.reg; +} + +static inline bool hri_pac_get_STATUSE_PAC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSE.reg & PAC_STATUSE_PAC) >> PAC_STATUSE_PAC_Pos; +} + +static inline bool hri_pac_get_STATUSE_DMAC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSE.reg & PAC_STATUSE_DMAC) >> PAC_STATUSE_DMAC_Pos; +} + +static inline hri_pac_statuse_reg_t hri_pac_get_STATUSE_reg(const void *const hw, hri_pac_statuse_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->STATUSE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_statuse_reg_t hri_pac_read_STATUSE_reg(const void *const hw) +{ + return ((Pac *)hw)->STATUSE.reg; +} + +static inline void hri_pac_set_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg |= PAC_WRCTRL_PERID(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp = (tmp & PAC_WRCTRL_PERID(mask)) >> PAC_WRCTRL_PERID_Pos; + return tmp; +} + +static inline void hri_pac_write_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t data) +{ + uint32_t tmp; + PAC_CRITICAL_SECTION_ENTER(); + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp &= ~PAC_WRCTRL_PERID_Msk; + tmp |= PAC_WRCTRL_PERID(data); + ((Pac *)hw)->WRCTRL.reg = tmp; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg &= ~PAC_WRCTRL_PERID(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg ^= PAC_WRCTRL_PERID(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_PERID_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp = (tmp & PAC_WRCTRL_PERID_Msk) >> PAC_WRCTRL_PERID_Pos; + return tmp; +} + +static inline void hri_pac_set_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg |= PAC_WRCTRL_KEY(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp = (tmp & PAC_WRCTRL_KEY(mask)) >> PAC_WRCTRL_KEY_Pos; + return tmp; +} + +static inline void hri_pac_write_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t data) +{ + uint32_t tmp; + PAC_CRITICAL_SECTION_ENTER(); + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp &= ~PAC_WRCTRL_KEY_Msk; + tmp |= PAC_WRCTRL_KEY(data); + ((Pac *)hw)->WRCTRL.reg = tmp; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg &= ~PAC_WRCTRL_KEY(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg ^= PAC_WRCTRL_KEY(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_KEY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp = (tmp & PAC_WRCTRL_KEY_Msk) >> PAC_WRCTRL_KEY_Pos; + return tmp; +} + +static inline void hri_pac_set_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg |= mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pac_write_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t data) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg = data; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg &= ~mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg ^= mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_reg(const void *const hw) +{ + return ((Pac *)hw)->WRCTRL.reg; +} + +static inline void hri_pac_set_EVCTRL_ERREO_bit(const void *const hw) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg |= PAC_EVCTRL_ERREO; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pac_get_EVCTRL_ERREO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pac *)hw)->EVCTRL.reg; + tmp = (tmp & PAC_EVCTRL_ERREO) >> PAC_EVCTRL_ERREO_Pos; + return (bool)tmp; +} + +static inline void hri_pac_write_EVCTRL_ERREO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + PAC_CRITICAL_SECTION_ENTER(); + tmp = ((Pac *)hw)->EVCTRL.reg; + tmp &= ~PAC_EVCTRL_ERREO; + tmp |= value << PAC_EVCTRL_ERREO_Pos; + ((Pac *)hw)->EVCTRL.reg = tmp; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_EVCTRL_ERREO_bit(const void *const hw) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg &= ~PAC_EVCTRL_ERREO; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_EVCTRL_ERREO_bit(const void *const hw) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg ^= PAC_EVCTRL_ERREO; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_set_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg |= mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_evctrl_reg_t hri_pac_get_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pac *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pac_write_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t data) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg = data; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg &= ~mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg ^= mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_evctrl_reg_t hri_pac_read_EVCTRL_reg(const void *const hw) +{ + return ((Pac *)hw)->EVCTRL.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PAC_L21_H_INCLUDED */ +#endif /* _SAML21_PAC_COMPONENT_ */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_pm_l21.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_pm_l21.h new file mode 100644 index 00000000..c36d148a --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_pm_l21.h @@ -0,0 +1,994 @@ +/** + * \file + * + * \brief SAM PM + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_PM_COMPONENT_ +#ifndef _HRI_PM_L21_H_INCLUDED_ +#define _HRI_PM_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PM_CRITICAL_SECTIONS) +#define PM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PM_CRITICAL_SECTION_ENTER() +#define PM_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_pm_stdbycfg_reg_t; +typedef uint8_t hri_pm_ctrla_reg_t; +typedef uint8_t hri_pm_intenset_reg_t; +typedef uint8_t hri_pm_intflag_reg_t; +typedef uint8_t hri_pm_plcfg_reg_t; +typedef uint8_t hri_pm_pwsakdly_reg_t; +typedef uint8_t hri_pm_sleepcfg_reg_t; + +static inline bool hri_pm_get_INTFLAG_PLRDY_bit(const void *const hw) +{ + return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_PLRDY) >> PM_INTFLAG_PLRDY_Pos; +} + +static inline void hri_pm_clear_INTFLAG_PLRDY_bit(const void *const hw) +{ + ((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_PLRDY; +} + +static inline bool hri_pm_get_interrupt_PLRDY_bit(const void *const hw) +{ + return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_PLRDY) >> PM_INTFLAG_PLRDY_Pos; +} + +static inline void hri_pm_clear_interrupt_PLRDY_bit(const void *const hw) +{ + ((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_PLRDY; +} + +static inline hri_pm_intflag_reg_t hri_pm_get_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pm_intflag_reg_t hri_pm_read_INTFLAG_reg(const void *const hw) +{ + return ((Pm *)hw)->INTFLAG.reg; +} + +static inline void hri_pm_clear_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask) +{ + ((Pm *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_pm_set_INTEN_PLRDY_bit(const void *const hw) +{ + ((Pm *)hw)->INTENSET.reg = PM_INTENSET_PLRDY; +} + +static inline bool hri_pm_get_INTEN_PLRDY_bit(const void *const hw) +{ + return (((Pm *)hw)->INTENSET.reg & PM_INTENSET_PLRDY) >> PM_INTENSET_PLRDY_Pos; +} + +static inline void hri_pm_write_INTEN_PLRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pm *)hw)->INTENCLR.reg = PM_INTENSET_PLRDY; + } else { + ((Pm *)hw)->INTENSET.reg = PM_INTENSET_PLRDY; + } +} + +static inline void hri_pm_clear_INTEN_PLRDY_bit(const void *const hw) +{ + ((Pm *)hw)->INTENCLR.reg = PM_INTENSET_PLRDY; +} + +static inline void hri_pm_set_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) +{ + ((Pm *)hw)->INTENSET.reg = mask; +} + +static inline hri_pm_intenset_reg_t hri_pm_get_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pm_intenset_reg_t hri_pm_read_INTEN_reg(const void *const hw) +{ + return ((Pm *)hw)->INTENSET.reg; +} + +static inline void hri_pm_write_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t data) +{ + ((Pm *)hw)->INTENSET.reg = data; + ((Pm *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_pm_clear_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) +{ + ((Pm *)hw)->INTENCLR.reg = mask; +} + +static inline void hri_pm_set_CTRLA_IORET_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg |= PM_CTRLA_IORET; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_CTRLA_IORET_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->CTRLA.reg; + tmp = (tmp & PM_CTRLA_IORET) >> PM_CTRLA_IORET_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_CTRLA_IORET_bit(const void *const hw, bool value) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->CTRLA.reg; + tmp &= ~PM_CTRLA_IORET; + tmp |= value << PM_CTRLA_IORET_Pos; + ((Pm *)hw)->CTRLA.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_CTRLA_IORET_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg &= ~PM_CTRLA_IORET; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_CTRLA_IORET_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg ^= PM_CTRLA_IORET; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_ctrla_reg_t hri_pm_get_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_ctrla_reg_t hri_pm_read_CTRLA_reg(const void *const hw) +{ + return ((Pm *)hw)->CTRLA.reg; +} + +static inline void hri_pm_set_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg |= PM_SLEEPCFG_SLEEPMODE(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->SLEEPCFG.reg; + tmp = (tmp & PM_SLEEPCFG_SLEEPMODE(mask)) >> PM_SLEEPCFG_SLEEPMODE_Pos; + return tmp; +} + +static inline void hri_pm_write_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->SLEEPCFG.reg; + tmp &= ~PM_SLEEPCFG_SLEEPMODE_Msk; + tmp |= PM_SLEEPCFG_SLEEPMODE(data); + ((Pm *)hw)->SLEEPCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg &= ~PM_SLEEPCFG_SLEEPMODE(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg ^= PM_SLEEPCFG_SLEEPMODE(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_SLEEPMODE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->SLEEPCFG.reg; + tmp = (tmp & PM_SLEEPCFG_SLEEPMODE_Msk) >> PM_SLEEPCFG_SLEEPMODE_Pos; + return tmp; +} + +static inline void hri_pm_set_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->SLEEPCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_reg(const void *const hw) +{ + return ((Pm *)hw)->SLEEPCFG.reg; +} + +static inline void hri_pm_set_PLCFG_PLDIS_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PLCFG.reg |= PM_PLCFG_PLDIS; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_PLCFG_PLDIS_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->PLCFG.reg; + tmp = (tmp & PM_PLCFG_PLDIS) >> PM_PLCFG_PLDIS_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_PLCFG_PLDIS_bit(const void *const hw, bool value) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->PLCFG.reg; + tmp &= ~PM_PLCFG_PLDIS; + tmp |= value << PM_PLCFG_PLDIS_Pos; + ((Pm *)hw)->PLCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_PLCFG_PLDIS_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PLCFG.reg &= ~PM_PLCFG_PLDIS; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_PLCFG_PLDIS_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PLCFG.reg ^= PM_PLCFG_PLDIS; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PLCFG.reg |= PM_PLCFG_PLSEL(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_plcfg_reg_t hri_pm_get_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->PLCFG.reg; + tmp = (tmp & PM_PLCFG_PLSEL(mask)) >> PM_PLCFG_PLSEL_Pos; + return tmp; +} + +static inline void hri_pm_write_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->PLCFG.reg; + tmp &= ~PM_PLCFG_PLSEL_Msk; + tmp |= PM_PLCFG_PLSEL(data); + ((Pm *)hw)->PLCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PLCFG.reg &= ~PM_PLCFG_PLSEL(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PLCFG.reg ^= PM_PLCFG_PLSEL(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_plcfg_reg_t hri_pm_read_PLCFG_PLSEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->PLCFG.reg; + tmp = (tmp & PM_PLCFG_PLSEL_Msk) >> PM_PLCFG_PLSEL_Pos; + return tmp; +} + +static inline void hri_pm_set_PLCFG_reg(const void *const hw, hri_pm_plcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PLCFG.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_plcfg_reg_t hri_pm_get_PLCFG_reg(const void *const hw, hri_pm_plcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->PLCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_PLCFG_reg(const void *const hw, hri_pm_plcfg_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PLCFG.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_PLCFG_reg(const void *const hw, hri_pm_plcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PLCFG.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_PLCFG_reg(const void *const hw, hri_pm_plcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PLCFG.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_plcfg_reg_t hri_pm_read_PLCFG_reg(const void *const hw) +{ + return ((Pm *)hw)->PLCFG.reg; +} + +static inline void hri_pm_set_STDBYCFG_DPGPD0_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_DPGPD0; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_STDBYCFG_DPGPD0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_DPGPD0) >> PM_STDBYCFG_DPGPD0_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_STDBYCFG_DPGPD0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp &= ~PM_STDBYCFG_DPGPD0; + tmp |= value << PM_STDBYCFG_DPGPD0_Pos; + ((Pm *)hw)->STDBYCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_STDBYCFG_DPGPD0_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_DPGPD0; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_STDBYCFG_DPGPD0_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_DPGPD0; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_STDBYCFG_DPGPD1_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_DPGPD1; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_STDBYCFG_DPGPD1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_DPGPD1) >> PM_STDBYCFG_DPGPD1_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_STDBYCFG_DPGPD1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp &= ~PM_STDBYCFG_DPGPD1; + tmp |= value << PM_STDBYCFG_DPGPD1_Pos; + ((Pm *)hw)->STDBYCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_STDBYCFG_DPGPD1_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_DPGPD1; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_STDBYCFG_DPGPD1_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_DPGPD1; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_STDBYCFG_PDCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_PDCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_PDCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + uint16_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_PDCFG(mask)) >> PM_STDBYCFG_PDCFG_Pos; + return tmp; +} + +static inline void hri_pm_write_STDBYCFG_PDCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t data) +{ + uint16_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp &= ~PM_STDBYCFG_PDCFG_Msk; + tmp |= PM_STDBYCFG_PDCFG(data); + ((Pm *)hw)->STDBYCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_STDBYCFG_PDCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_PDCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_STDBYCFG_PDCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_PDCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_PDCFG_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_PDCFG_Msk) >> PM_STDBYCFG_PDCFG_Pos; + return tmp; +} + +static inline void hri_pm_set_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_VREGSMOD(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + uint16_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_VREGSMOD(mask)) >> PM_STDBYCFG_VREGSMOD_Pos; + return tmp; +} + +static inline void hri_pm_write_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t data) +{ + uint16_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp &= ~PM_STDBYCFG_VREGSMOD_Msk; + tmp |= PM_STDBYCFG_VREGSMOD(data); + ((Pm *)hw)->STDBYCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_VREGSMOD(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_VREGSMOD(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_VREGSMOD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_VREGSMOD_Msk) >> PM_STDBYCFG_VREGSMOD_Pos; + return tmp; +} + +static inline void hri_pm_set_STDBYCFG_LINKPD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_LINKPD(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_LINKPD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + uint16_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_LINKPD(mask)) >> PM_STDBYCFG_LINKPD_Pos; + return tmp; +} + +static inline void hri_pm_write_STDBYCFG_LINKPD_bf(const void *const hw, hri_pm_stdbycfg_reg_t data) +{ + uint16_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp &= ~PM_STDBYCFG_LINKPD_Msk; + tmp |= PM_STDBYCFG_LINKPD(data); + ((Pm *)hw)->STDBYCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_STDBYCFG_LINKPD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_LINKPD(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_STDBYCFG_LINKPD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_LINKPD(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_LINKPD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_LINKPD_Msk) >> PM_STDBYCFG_LINKPD_Pos; + return tmp; +} + +static inline void hri_pm_set_STDBYCFG_BBIASHS_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_BBIASHS(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_BBIASHS_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + uint16_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_BBIASHS(mask)) >> PM_STDBYCFG_BBIASHS_Pos; + return tmp; +} + +static inline void hri_pm_write_STDBYCFG_BBIASHS_bf(const void *const hw, hri_pm_stdbycfg_reg_t data) +{ + uint16_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp &= ~PM_STDBYCFG_BBIASHS_Msk; + tmp |= PM_STDBYCFG_BBIASHS(data); + ((Pm *)hw)->STDBYCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_STDBYCFG_BBIASHS_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_BBIASHS(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_STDBYCFG_BBIASHS_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_BBIASHS(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_BBIASHS_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_BBIASHS_Msk) >> PM_STDBYCFG_BBIASHS_Pos; + return tmp; +} + +static inline void hri_pm_set_STDBYCFG_BBIASLP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_BBIASLP(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_BBIASLP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + uint16_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_BBIASLP(mask)) >> PM_STDBYCFG_BBIASLP_Pos; + return tmp; +} + +static inline void hri_pm_write_STDBYCFG_BBIASLP_bf(const void *const hw, hri_pm_stdbycfg_reg_t data) +{ + uint16_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp &= ~PM_STDBYCFG_BBIASLP_Msk; + tmp |= PM_STDBYCFG_BBIASLP(data); + ((Pm *)hw)->STDBYCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_STDBYCFG_BBIASLP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_BBIASLP(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_STDBYCFG_BBIASLP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_BBIASLP(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_BBIASLP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_BBIASLP_Msk) >> PM_STDBYCFG_BBIASLP_Pos; + return tmp; +} + +static inline void hri_pm_set_STDBYCFG_BBIASPP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_BBIASPP(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_BBIASPP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + uint16_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_BBIASPP(mask)) >> PM_STDBYCFG_BBIASPP_Pos; + return tmp; +} + +static inline void hri_pm_write_STDBYCFG_BBIASPP_bf(const void *const hw, hri_pm_stdbycfg_reg_t data) +{ + uint16_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp &= ~PM_STDBYCFG_BBIASPP_Msk; + tmp |= PM_STDBYCFG_BBIASPP(data); + ((Pm *)hw)->STDBYCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_STDBYCFG_BBIASPP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_BBIASPP(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_STDBYCFG_BBIASPP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_BBIASPP(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_BBIASPP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_BBIASPP_Msk) >> PM_STDBYCFG_BBIASPP_Pos; + return tmp; +} + +static inline void hri_pm_set_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + uint16_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_reg(const void *const hw) +{ + return ((Pm *)hw)->STDBYCFG.reg; +} + +static inline void hri_pm_set_PWSAKDLY_IGNACK_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg |= PM_PWSAKDLY_IGNACK; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_PWSAKDLY_IGNACK_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->PWSAKDLY.reg; + tmp = (tmp & PM_PWSAKDLY_IGNACK) >> PM_PWSAKDLY_IGNACK_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_PWSAKDLY_IGNACK_bit(const void *const hw, bool value) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->PWSAKDLY.reg; + tmp &= ~PM_PWSAKDLY_IGNACK; + tmp |= value << PM_PWSAKDLY_IGNACK_Pos; + ((Pm *)hw)->PWSAKDLY.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_PWSAKDLY_IGNACK_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg &= ~PM_PWSAKDLY_IGNACK; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_PWSAKDLY_IGNACK_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg ^= PM_PWSAKDLY_IGNACK; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg |= PM_PWSAKDLY_DLYVAL(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_pwsakdly_reg_t hri_pm_get_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->PWSAKDLY.reg; + tmp = (tmp & PM_PWSAKDLY_DLYVAL(mask)) >> PM_PWSAKDLY_DLYVAL_Pos; + return tmp; +} + +static inline void hri_pm_write_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->PWSAKDLY.reg; + tmp &= ~PM_PWSAKDLY_DLYVAL_Msk; + tmp |= PM_PWSAKDLY_DLYVAL(data); + ((Pm *)hw)->PWSAKDLY.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg &= ~PM_PWSAKDLY_DLYVAL(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg ^= PM_PWSAKDLY_DLYVAL(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_pwsakdly_reg_t hri_pm_read_PWSAKDLY_DLYVAL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->PWSAKDLY.reg; + tmp = (tmp & PM_PWSAKDLY_DLYVAL_Msk) >> PM_PWSAKDLY_DLYVAL_Pos; + return tmp; +} + +static inline void hri_pm_set_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_pwsakdly_reg_t hri_pm_get_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->PWSAKDLY.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_pwsakdly_reg_t hri_pm_read_PWSAKDLY_reg(const void *const hw) +{ + return ((Pm *)hw)->PWSAKDLY.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PM_L21_H_INCLUDED */ +#endif /* _SAML21_PM_COMPONENT_ */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_port_l21.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_port_l21.h new file mode 100644 index 00000000..374ca612 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_port_l21.h @@ -0,0 +1,2528 @@ +/** + * \file + * + * \brief SAM PORT + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_PORT_COMPONENT_ +#ifndef _HRI_PORT_L21_H_INCLUDED_ +#define _HRI_PORT_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PORT_CRITICAL_SECTIONS) +#define PORT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PORT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PORT_CRITICAL_SECTION_ENTER() +#define PORT_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_port_ctrl_reg_t; +typedef uint32_t hri_port_dir_reg_t; +typedef uint32_t hri_port_evctrl_reg_t; +typedef uint32_t hri_port_in_reg_t; +typedef uint32_t hri_port_out_reg_t; +typedef uint32_t hri_port_wrconfig_reg_t; +typedef uint32_t hri_portgroup_ctrl_reg_t; +typedef uint32_t hri_portgroup_dir_reg_t; +typedef uint32_t hri_portgroup_evctrl_reg_t; +typedef uint32_t hri_portgroup_in_reg_t; +typedef uint32_t hri_portgroup_out_reg_t; +typedef uint32_t hri_portgroup_wrconfig_reg_t; +typedef uint8_t hri_port_pincfg_reg_t; +typedef uint8_t hri_port_pmux_reg_t; +typedef uint8_t hri_portgroup_pincfg_reg_t; +typedef uint8_t hri_portgroup_pmux_reg_t; + +static inline void hri_portgroup_set_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRSET.reg = PORT_DIR_DIR(mask); +} + +static inline hri_port_dir_reg_t hri_portgroup_get_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->DIR.reg; + tmp = (tmp & PORT_DIR_DIR(mask)) >> PORT_DIR_DIR_Pos; + return tmp; +} + +static inline hri_port_dir_reg_t hri_portgroup_read_DIR_DIR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->DIR.reg; + tmp = (tmp & PORT_DIR_DIR_Msk) >> PORT_DIR_DIR_Pos; + return tmp; +} + +static inline void hri_portgroup_write_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t data) +{ + ((PortGroup *)hw)->DIRSET.reg = PORT_DIR_DIR(data); + ((PortGroup *)hw)->DIRCLR.reg = ~PORT_DIR_DIR(data); +} + +static inline void hri_portgroup_clear_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRCLR.reg = PORT_DIR_DIR(mask); +} + +static inline void hri_portgroup_toggle_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRTGL.reg = PORT_DIR_DIR(mask); +} + +static inline void hri_portgroup_set_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRSET.reg = mask; +} + +static inline hri_port_dir_reg_t hri_portgroup_get_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->DIR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_dir_reg_t hri_portgroup_read_DIR_reg(const void *const hw) +{ + return ((PortGroup *)hw)->DIR.reg; +} + +static inline void hri_portgroup_write_DIR_reg(const void *const hw, hri_port_dir_reg_t data) +{ + ((PortGroup *)hw)->DIRSET.reg = data; + ((PortGroup *)hw)->DIRCLR.reg = ~data; +} + +static inline void hri_portgroup_clear_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRCLR.reg = mask; +} + +static inline void hri_portgroup_toggle_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRTGL.reg = mask; +} + +static inline void hri_portgroup_set_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTSET.reg = PORT_OUT_OUT(mask); +} + +static inline hri_port_out_reg_t hri_portgroup_get_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->OUT.reg; + tmp = (tmp & PORT_OUT_OUT(mask)) >> PORT_OUT_OUT_Pos; + return tmp; +} + +static inline hri_port_out_reg_t hri_portgroup_read_OUT_OUT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->OUT.reg; + tmp = (tmp & PORT_OUT_OUT_Msk) >> PORT_OUT_OUT_Pos; + return tmp; +} + +static inline void hri_portgroup_write_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t data) +{ + ((PortGroup *)hw)->OUTSET.reg = PORT_OUT_OUT(data); + ((PortGroup *)hw)->OUTCLR.reg = ~PORT_OUT_OUT(data); +} + +static inline void hri_portgroup_clear_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTCLR.reg = PORT_OUT_OUT(mask); +} + +static inline void hri_portgroup_toggle_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTTGL.reg = PORT_OUT_OUT(mask); +} + +static inline void hri_portgroup_set_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTSET.reg = mask; +} + +static inline hri_port_out_reg_t hri_portgroup_get_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->OUT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_out_reg_t hri_portgroup_read_OUT_reg(const void *const hw) +{ + return ((PortGroup *)hw)->OUT.reg; +} + +static inline void hri_portgroup_write_OUT_reg(const void *const hw, hri_port_out_reg_t data) +{ + ((PortGroup *)hw)->OUTSET.reg = data; + ((PortGroup *)hw)->OUTCLR.reg = ~data; +} + +static inline void hri_portgroup_clear_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTCLR.reg = mask; +} + +static inline void hri_portgroup_toggle_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTTGL.reg = mask; +} + +static inline hri_port_in_reg_t hri_portgroup_get_IN_IN_bf(const void *const hw, hri_port_in_reg_t mask) +{ + return (((PortGroup *)hw)->IN.reg & PORT_IN_IN(mask)) >> PORT_IN_IN_Pos; +} + +static inline hri_port_in_reg_t hri_portgroup_read_IN_IN_bf(const void *const hw) +{ + return (((PortGroup *)hw)->IN.reg & PORT_IN_IN_Msk) >> PORT_IN_IN_Pos; +} + +static inline hri_port_in_reg_t hri_portgroup_get_IN_reg(const void *const hw, hri_port_in_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->IN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_in_reg_t hri_portgroup_read_IN_reg(const void *const hw) +{ + return ((PortGroup *)hw)->IN.reg; +} + +static inline void hri_portgroup_set_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg |= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_portgroup_write_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp &= ~PORT_CTRL_SAMPLING_Msk; + tmp |= PORT_CTRL_SAMPLING(data); + ((PortGroup *)hw)->CTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg &= ~PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg ^= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_SAMPLING_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_portgroup_set_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_portgroup_write_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_reg(const void *const hw) +{ + return ((PortGroup *)hw)->CTRL.reg; +} + +static inline void hri_portgroup_set_EVCTRL_PORTEI0_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_EVCTRL_PORTEI0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI0) >> PORT_EVCTRL_PORTEI0_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PORTEI0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI0; + tmp |= value << PORT_EVCTRL_PORTEI0_Pos; + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PORTEI0_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PORTEI0_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_EVCTRL_PORTEI1_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_EVCTRL_PORTEI1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI1) >> PORT_EVCTRL_PORTEI1_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PORTEI1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI1; + tmp |= value << PORT_EVCTRL_PORTEI1_Pos; + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PORTEI1_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PORTEI1_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_EVCTRL_PORTEI2_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_EVCTRL_PORTEI2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI2) >> PORT_EVCTRL_PORTEI2_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PORTEI2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI2; + tmp |= value << PORT_EVCTRL_PORTEI2_Pos; + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PORTEI2_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PORTEI2_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_EVCTRL_PORTEI3_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_EVCTRL_PORTEI3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI3) >> PORT_EVCTRL_PORTEI3_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PORTEI3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI3; + tmp |= value << PORT_EVCTRL_PORTEI3_Pos; + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PORTEI3_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PORTEI3_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID0(mask)) >> PORT_EVCTRL_PID0_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID0_Msk; + tmp |= PORT_EVCTRL_PID0(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID0_Msk) >> PORT_EVCTRL_PID0_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT0(mask)) >> PORT_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT0_Msk; + tmp |= PORT_EVCTRL_EVACT0(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT0_Msk) >> PORT_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID1(mask)) >> PORT_EVCTRL_PID1_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID1_Msk; + tmp |= PORT_EVCTRL_PID1(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID1_Msk) >> PORT_EVCTRL_PID1_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT1(mask)) >> PORT_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT1_Msk; + tmp |= PORT_EVCTRL_EVACT1(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT1_Msk) >> PORT_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID2(mask)) >> PORT_EVCTRL_PID2_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID2_Msk; + tmp |= PORT_EVCTRL_PID2(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID2_Msk) >> PORT_EVCTRL_PID2_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT2(mask)) >> PORT_EVCTRL_EVACT2_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT2_Msk; + tmp |= PORT_EVCTRL_EVACT2(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT2_Msk) >> PORT_EVCTRL_EVACT2_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID3(mask)) >> PORT_EVCTRL_PID3_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID3_Msk; + tmp |= PORT_EVCTRL_PID3(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID3_Msk) >> PORT_EVCTRL_PID3_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT3(mask)) >> PORT_EVCTRL_EVACT3_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT3_Msk; + tmp |= PORT_EVCTRL_EVACT3(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT3_Msk) >> PORT_EVCTRL_EVACT3_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_reg(const void *const hw) +{ + return ((PortGroup *)hw)->EVCTRL.reg; +} + +static inline void hri_portgroup_set_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXE_bf(const void *const hw, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_portgroup_write_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXE_Msk; + tmp |= PORT_PMUX_PMUXE(data); + ((PortGroup *)hw)->PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXE_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_portgroup_set_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXO_bf(const void *const hw, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_portgroup_write_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXO_Msk; + tmp |= PORT_PMUX_PMUXO(data); + ((PortGroup *)hw)->PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXO_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_portgroup_set_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_reg(const void *const hw, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_portgroup_write_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_reg(const void *const hw, uint8_t index) +{ + return ((PortGroup *)hw)->PMUX[index].reg; +} + +static inline void hri_portgroup_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PMUXEN; + tmp |= value << PORT_PINCFG_PMUXEN_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_INEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_INEN; + tmp |= value << PORT_PINCFG_INEN_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PULLEN; + tmp |= value << PORT_PINCFG_PULLEN_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_DRVSTR; + tmp |= value << PORT_PINCFG_DRVSTR_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_portgroup_get_PINCFG_reg(const void *const hw, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_portgroup_write_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_portgroup_read_PINCFG_reg(const void *const hw, uint8_t index) +{ + return ((PortGroup *)hw)->PINCFG[index].reg; +} + +static inline void hri_portgroup_write_WRCONFIG_reg(const void *const hw, hri_port_wrconfig_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->WRCONFIG.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRSET.reg = PORT_DIR_DIR(mask); +} + +static inline hri_port_dir_reg_t hri_port_get_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, + hri_port_dir_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].DIR.reg; + tmp = (tmp & PORT_DIR_DIR(mask)) >> PORT_DIR_DIR_Pos; + return tmp; +} + +static inline hri_port_dir_reg_t hri_port_read_DIR_DIR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].DIR.reg; + tmp = (tmp & PORT_DIR_DIR_Msk) >> PORT_DIR_DIR_Pos; + return tmp; +} + +static inline void hri_port_write_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t data) +{ + ((Port *)hw)->Group[submodule_index].DIRSET.reg = PORT_DIR_DIR(data); + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~PORT_DIR_DIR(data); +} + +static inline void hri_port_clear_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = PORT_DIR_DIR(mask); +} + +static inline void hri_port_toggle_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRTGL.reg = PORT_DIR_DIR(mask); +} + +static inline void hri_port_set_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRSET.reg = mask; +} + +static inline hri_port_dir_reg_t hri_port_get_DIR_reg(const void *const hw, uint8_t submodule_index, + hri_port_dir_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].DIR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_dir_reg_t hri_port_read_DIR_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].DIR.reg; +} + +static inline void hri_port_write_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t data) +{ + ((Port *)hw)->Group[submodule_index].DIRSET.reg = data; + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~data; +} + +static inline void hri_port_clear_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask; +} + +static inline void hri_port_toggle_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRTGL.reg = mask; +} + +static inline void hri_port_set_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTSET.reg = PORT_OUT_OUT(mask); +} + +static inline hri_port_out_reg_t hri_port_get_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, + hri_port_out_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].OUT.reg; + tmp = (tmp & PORT_OUT_OUT(mask)) >> PORT_OUT_OUT_Pos; + return tmp; +} + +static inline hri_port_out_reg_t hri_port_read_OUT_OUT_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].OUT.reg; + tmp = (tmp & PORT_OUT_OUT_Msk) >> PORT_OUT_OUT_Pos; + return tmp; +} + +static inline void hri_port_write_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t data) +{ + ((Port *)hw)->Group[submodule_index].OUTSET.reg = PORT_OUT_OUT(data); + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = ~PORT_OUT_OUT(data); +} + +static inline void hri_port_clear_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = PORT_OUT_OUT(mask); +} + +static inline void hri_port_toggle_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTTGL.reg = PORT_OUT_OUT(mask); +} + +static inline void hri_port_set_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTSET.reg = mask; +} + +static inline hri_port_out_reg_t hri_port_get_OUT_reg(const void *const hw, uint8_t submodule_index, + hri_port_out_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].OUT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_out_reg_t hri_port_read_OUT_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].OUT.reg; +} + +static inline void hri_port_write_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t data) +{ + ((Port *)hw)->Group[submodule_index].OUTSET.reg = data; + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = ~data; +} + +static inline void hri_port_clear_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask; +} + +static inline void hri_port_toggle_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTTGL.reg = mask; +} + +static inline hri_port_in_reg_t hri_port_get_IN_IN_bf(const void *const hw, uint8_t submodule_index, + hri_port_in_reg_t mask) +{ + return (((Port *)hw)->Group[submodule_index].IN.reg & PORT_IN_IN(mask)) >> PORT_IN_IN_Pos; +} + +static inline hri_port_in_reg_t hri_port_read_IN_IN_bf(const void *const hw, uint8_t submodule_index) +{ + return (((Port *)hw)->Group[submodule_index].IN.reg & PORT_IN_IN_Msk) >> PORT_IN_IN_Pos; +} + +static inline hri_port_in_reg_t hri_port_get_IN_reg(const void *const hw, uint8_t submodule_index, + hri_port_in_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].IN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_in_reg_t hri_port_read_IN_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].IN.reg; +} + +static inline void hri_port_set_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg |= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_get_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_port_write_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp &= ~PORT_CTRL_SAMPLING_Msk; + tmp |= PORT_CTRL_SAMPLING(data); + ((Port *)hw)->Group[submodule_index].CTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg &= ~PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg ^= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_read_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_port_set_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_get_CTRL_reg(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_port_write_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_read_CTRL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].CTRL.reg; +} + +static inline void hri_port_set_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI0) >> PORT_EVCTRL_PORTEI0_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI0; + tmp |= value << PORT_EVCTRL_PORTEI0_Pos; + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI1) >> PORT_EVCTRL_PORTEI1_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI1; + tmp |= value << PORT_EVCTRL_PORTEI1_Pos; + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI2) >> PORT_EVCTRL_PORTEI2_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI2; + tmp |= value << PORT_EVCTRL_PORTEI2_Pos; + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI3) >> PORT_EVCTRL_PORTEI3_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI3; + tmp |= value << PORT_EVCTRL_PORTEI3_Pos; + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID0(mask)) >> PORT_EVCTRL_PID0_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID0_Msk; + tmp |= PORT_EVCTRL_PID0(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID0_Msk) >> PORT_EVCTRL_PID0_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT0(mask)) >> PORT_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT0_Msk; + tmp |= PORT_EVCTRL_EVACT0(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT0_Msk) >> PORT_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID1(mask)) >> PORT_EVCTRL_PID1_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID1_Msk; + tmp |= PORT_EVCTRL_PID1(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID1_Msk) >> PORT_EVCTRL_PID1_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT1(mask)) >> PORT_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT1_Msk; + tmp |= PORT_EVCTRL_EVACT1(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT1_Msk) >> PORT_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID2(mask)) >> PORT_EVCTRL_PID2_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID2_Msk; + tmp |= PORT_EVCTRL_PID2(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID2_Msk) >> PORT_EVCTRL_PID2_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT2(mask)) >> PORT_EVCTRL_EVACT2_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT2_Msk; + tmp |= PORT_EVCTRL_EVACT2(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT2_Msk) >> PORT_EVCTRL_EVACT2_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID3(mask)) >> PORT_EVCTRL_PID3_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID3_Msk; + tmp |= PORT_EVCTRL_PID3(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID3_Msk) >> PORT_EVCTRL_PID3_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT3(mask)) >> PORT_EVCTRL_EVACT3_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT3_Msk; + tmp |= PORT_EVCTRL_EVACT3(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT3_Msk) >> PORT_EVCTRL_EVACT3_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_reg(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_port_write_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].EVCTRL.reg; +} + +static inline void hri_port_set_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, + uint8_t index, hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_port_write_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXE_Msk; + tmp |= PORT_PMUX_PMUXE(data); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, + uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_port_set_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, + uint8_t index, hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_port_write_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXO_Msk; + tmp |= PORT_PMUX_PMUXO(data); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, + uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_port_set_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_get_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_port_write_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_read_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + return ((Port *)hw)->Group[submodule_index].PMUX[index].reg; +} + +static inline void hri_port_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PMUXEN; + tmp |= value << PORT_PINCFG_PMUXEN_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_INEN; + tmp |= value << PORT_PINCFG_INEN_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PULLEN; + tmp |= value << PORT_PINCFG_PULLEN_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_DRVSTR; + tmp |= value << PORT_PINCFG_DRVSTR_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_port_get_PINCFG_reg(const void *const hw, uint8_t submodule_index, + uint8_t index, hri_port_pincfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_port_write_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_port_read_PINCFG_reg(const void *const hw, uint8_t submodule_index, + uint8_t index) +{ + return ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; +} + +static inline void hri_port_write_WRCONFIG_reg(const void *const hw, uint8_t submodule_index, + hri_port_wrconfig_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PORT_L21_H_INCLUDED */ +#endif /* _SAML21_PORT_COMPONENT_ */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_rstc_l21.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_rstc_l21.h new file mode 100644 index 00000000..b62222ad --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_rstc_l21.h @@ -0,0 +1,498 @@ +/** + * \file + * + * \brief SAM RSTC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_RSTC_COMPONENT_ +#ifndef _HRI_RSTC_L21_H_INCLUDED_ +#define _HRI_RSTC_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_RSTC_CRITICAL_SECTIONS) +#define RSTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define RSTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define RSTC_CRITICAL_SECTION_ENTER() +#define RSTC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_rstc_wkcause_reg_t; +typedef uint16_t hri_rstc_wken_reg_t; +typedef uint16_t hri_rstc_wkpol_reg_t; +typedef uint8_t hri_rstc_bkupexit_reg_t; +typedef uint8_t hri_rstc_rcause_reg_t; +typedef uint8_t hri_rstc_wkdbconf_reg_t; + +static inline bool hri_rstc_get_RCAUSE_POR_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_POR) >> RSTC_RCAUSE_POR_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_BOD12_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BOD12) >> RSTC_RCAUSE_BOD12_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_BOD33_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BOD33) >> RSTC_RCAUSE_BOD33_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_EXT_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_EXT) >> RSTC_RCAUSE_EXT_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_WDT_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_WDT) >> RSTC_RCAUSE_WDT_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_SYST_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_SYST) >> RSTC_RCAUSE_SYST_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_BACKUP_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BACKUP) >> RSTC_RCAUSE_BACKUP_Pos; +} + +static inline hri_rstc_rcause_reg_t hri_rstc_get_RCAUSE_reg(const void *const hw, hri_rstc_rcause_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rstc *)hw)->RCAUSE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rstc_rcause_reg_t hri_rstc_read_RCAUSE_reg(const void *const hw) +{ + return ((Rstc *)hw)->RCAUSE.reg; +} + +static inline bool hri_rstc_get_BKUPEXIT_EXTWAKE_bit(const void *const hw) +{ + return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_EXTWAKE) >> RSTC_BKUPEXIT_EXTWAKE_Pos; +} + +static inline bool hri_rstc_get_BKUPEXIT_RTC_bit(const void *const hw) +{ + return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_RTC) >> RSTC_BKUPEXIT_RTC_Pos; +} + +static inline bool hri_rstc_get_BKUPEXIT_BBPS_bit(const void *const hw) +{ + return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_BBPS) >> RSTC_BKUPEXIT_BBPS_Pos; +} + +static inline hri_rstc_bkupexit_reg_t hri_rstc_get_BKUPEXIT_reg(const void *const hw, hri_rstc_bkupexit_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rstc *)hw)->BKUPEXIT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rstc_bkupexit_reg_t hri_rstc_read_BKUPEXIT_reg(const void *const hw) +{ + return ((Rstc *)hw)->BKUPEXIT.reg; +} + +static inline void hri_rstc_set_WKDBCONF_WKDBCNT_bf(const void *const hw, hri_rstc_wkdbconf_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKDBCONF.reg |= RSTC_WKDBCONF_WKDBCNT(mask); + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rstc_wkdbconf_reg_t hri_rstc_get_WKDBCONF_WKDBCNT_bf(const void *const hw, + hri_rstc_wkdbconf_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rstc *)hw)->WKDBCONF.reg; + tmp = (tmp & RSTC_WKDBCONF_WKDBCNT(mask)) >> RSTC_WKDBCONF_WKDBCNT_Pos; + return tmp; +} + +static inline void hri_rstc_write_WKDBCONF_WKDBCNT_bf(const void *const hw, hri_rstc_wkdbconf_reg_t data) +{ + uint8_t tmp; + RSTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rstc *)hw)->WKDBCONF.reg; + tmp &= ~RSTC_WKDBCONF_WKDBCNT_Msk; + tmp |= RSTC_WKDBCONF_WKDBCNT(data); + ((Rstc *)hw)->WKDBCONF.reg = tmp; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_clear_WKDBCONF_WKDBCNT_bf(const void *const hw, hri_rstc_wkdbconf_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKDBCONF.reg &= ~RSTC_WKDBCONF_WKDBCNT(mask); + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_toggle_WKDBCONF_WKDBCNT_bf(const void *const hw, hri_rstc_wkdbconf_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKDBCONF.reg ^= RSTC_WKDBCONF_WKDBCNT(mask); + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rstc_wkdbconf_reg_t hri_rstc_read_WKDBCONF_WKDBCNT_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Rstc *)hw)->WKDBCONF.reg; + tmp = (tmp & RSTC_WKDBCONF_WKDBCNT_Msk) >> RSTC_WKDBCONF_WKDBCNT_Pos; + return tmp; +} + +static inline void hri_rstc_set_WKDBCONF_reg(const void *const hw, hri_rstc_wkdbconf_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKDBCONF.reg |= mask; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rstc_wkdbconf_reg_t hri_rstc_get_WKDBCONF_reg(const void *const hw, hri_rstc_wkdbconf_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rstc *)hw)->WKDBCONF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rstc_write_WKDBCONF_reg(const void *const hw, hri_rstc_wkdbconf_reg_t data) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKDBCONF.reg = data; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_clear_WKDBCONF_reg(const void *const hw, hri_rstc_wkdbconf_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKDBCONF.reg &= ~mask; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_toggle_WKDBCONF_reg(const void *const hw, hri_rstc_wkdbconf_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKDBCONF.reg ^= mask; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rstc_wkdbconf_reg_t hri_rstc_read_WKDBCONF_reg(const void *const hw) +{ + return ((Rstc *)hw)->WKDBCONF.reg; +} + +static inline void hri_rstc_set_WKPOL_WKPOL_bf(const void *const hw, hri_rstc_wkpol_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKPOL.reg |= RSTC_WKPOL_WKPOL(mask); + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rstc_wkpol_reg_t hri_rstc_get_WKPOL_WKPOL_bf(const void *const hw, hri_rstc_wkpol_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rstc *)hw)->WKPOL.reg; + tmp = (tmp & RSTC_WKPOL_WKPOL(mask)) >> RSTC_WKPOL_WKPOL_Pos; + return tmp; +} + +static inline void hri_rstc_write_WKPOL_WKPOL_bf(const void *const hw, hri_rstc_wkpol_reg_t data) +{ + uint16_t tmp; + RSTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rstc *)hw)->WKPOL.reg; + tmp &= ~RSTC_WKPOL_WKPOL_Msk; + tmp |= RSTC_WKPOL_WKPOL(data); + ((Rstc *)hw)->WKPOL.reg = tmp; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_clear_WKPOL_WKPOL_bf(const void *const hw, hri_rstc_wkpol_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKPOL.reg &= ~RSTC_WKPOL_WKPOL(mask); + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_toggle_WKPOL_WKPOL_bf(const void *const hw, hri_rstc_wkpol_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKPOL.reg ^= RSTC_WKPOL_WKPOL(mask); + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rstc_wkpol_reg_t hri_rstc_read_WKPOL_WKPOL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rstc *)hw)->WKPOL.reg; + tmp = (tmp & RSTC_WKPOL_WKPOL_Msk) >> RSTC_WKPOL_WKPOL_Pos; + return tmp; +} + +static inline void hri_rstc_set_WKPOL_reg(const void *const hw, hri_rstc_wkpol_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKPOL.reg |= mask; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rstc_wkpol_reg_t hri_rstc_get_WKPOL_reg(const void *const hw, hri_rstc_wkpol_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rstc *)hw)->WKPOL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rstc_write_WKPOL_reg(const void *const hw, hri_rstc_wkpol_reg_t data) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKPOL.reg = data; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_clear_WKPOL_reg(const void *const hw, hri_rstc_wkpol_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKPOL.reg &= ~mask; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_toggle_WKPOL_reg(const void *const hw, hri_rstc_wkpol_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKPOL.reg ^= mask; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rstc_wkpol_reg_t hri_rstc_read_WKPOL_reg(const void *const hw) +{ + return ((Rstc *)hw)->WKPOL.reg; +} + +static inline void hri_rstc_set_WKEN_WKEN_bf(const void *const hw, hri_rstc_wken_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKEN.reg |= RSTC_WKEN_WKEN(mask); + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rstc_wken_reg_t hri_rstc_get_WKEN_WKEN_bf(const void *const hw, hri_rstc_wken_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rstc *)hw)->WKEN.reg; + tmp = (tmp & RSTC_WKEN_WKEN(mask)) >> RSTC_WKEN_WKEN_Pos; + return tmp; +} + +static inline void hri_rstc_write_WKEN_WKEN_bf(const void *const hw, hri_rstc_wken_reg_t data) +{ + uint16_t tmp; + RSTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rstc *)hw)->WKEN.reg; + tmp &= ~RSTC_WKEN_WKEN_Msk; + tmp |= RSTC_WKEN_WKEN(data); + ((Rstc *)hw)->WKEN.reg = tmp; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_clear_WKEN_WKEN_bf(const void *const hw, hri_rstc_wken_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKEN.reg &= ~RSTC_WKEN_WKEN(mask); + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_toggle_WKEN_WKEN_bf(const void *const hw, hri_rstc_wken_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKEN.reg ^= RSTC_WKEN_WKEN(mask); + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rstc_wken_reg_t hri_rstc_read_WKEN_WKEN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rstc *)hw)->WKEN.reg; + tmp = (tmp & RSTC_WKEN_WKEN_Msk) >> RSTC_WKEN_WKEN_Pos; + return tmp; +} + +static inline void hri_rstc_set_WKEN_reg(const void *const hw, hri_rstc_wken_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKEN.reg |= mask; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rstc_wken_reg_t hri_rstc_get_WKEN_reg(const void *const hw, hri_rstc_wken_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rstc *)hw)->WKEN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rstc_write_WKEN_reg(const void *const hw, hri_rstc_wken_reg_t data) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKEN.reg = data; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_clear_WKEN_reg(const void *const hw, hri_rstc_wken_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKEN.reg &= ~mask; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_toggle_WKEN_reg(const void *const hw, hri_rstc_wken_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKEN.reg ^= mask; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rstc_wken_reg_t hri_rstc_read_WKEN_reg(const void *const hw) +{ + return ((Rstc *)hw)->WKEN.reg; +} + +static inline void hri_rstc_set_WKCAUSE_WKCAUSE_bf(const void *const hw, hri_rstc_wkcause_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKCAUSE.reg |= RSTC_WKCAUSE_WKCAUSE(mask); + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rstc_wkcause_reg_t hri_rstc_get_WKCAUSE_WKCAUSE_bf(const void *const hw, hri_rstc_wkcause_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rstc *)hw)->WKCAUSE.reg; + tmp = (tmp & RSTC_WKCAUSE_WKCAUSE(mask)) >> RSTC_WKCAUSE_WKCAUSE_Pos; + return tmp; +} + +static inline void hri_rstc_write_WKCAUSE_WKCAUSE_bf(const void *const hw, hri_rstc_wkcause_reg_t data) +{ + uint16_t tmp; + RSTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rstc *)hw)->WKCAUSE.reg; + tmp &= ~RSTC_WKCAUSE_WKCAUSE_Msk; + tmp |= RSTC_WKCAUSE_WKCAUSE(data); + ((Rstc *)hw)->WKCAUSE.reg = tmp; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_clear_WKCAUSE_WKCAUSE_bf(const void *const hw, hri_rstc_wkcause_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKCAUSE.reg &= ~RSTC_WKCAUSE_WKCAUSE(mask); + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_toggle_WKCAUSE_WKCAUSE_bf(const void *const hw, hri_rstc_wkcause_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKCAUSE.reg ^= RSTC_WKCAUSE_WKCAUSE(mask); + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rstc_wkcause_reg_t hri_rstc_read_WKCAUSE_WKCAUSE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rstc *)hw)->WKCAUSE.reg; + tmp = (tmp & RSTC_WKCAUSE_WKCAUSE_Msk) >> RSTC_WKCAUSE_WKCAUSE_Pos; + return tmp; +} + +static inline void hri_rstc_set_WKCAUSE_reg(const void *const hw, hri_rstc_wkcause_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKCAUSE.reg |= mask; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rstc_wkcause_reg_t hri_rstc_get_WKCAUSE_reg(const void *const hw, hri_rstc_wkcause_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rstc *)hw)->WKCAUSE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rstc_write_WKCAUSE_reg(const void *const hw, hri_rstc_wkcause_reg_t data) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKCAUSE.reg = data; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_clear_WKCAUSE_reg(const void *const hw, hri_rstc_wkcause_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKCAUSE.reg &= ~mask; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_toggle_WKCAUSE_reg(const void *const hw, hri_rstc_wkcause_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKCAUSE.reg ^= mask; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rstc_wkcause_reg_t hri_rstc_read_WKCAUSE_reg(const void *const hw) +{ + return ((Rstc *)hw)->WKCAUSE.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_RSTC_L21_H_INCLUDED */ +#endif /* _SAML21_RSTC_COMPONENT_ */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_rtc_l21.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_rtc_l21.h new file mode 100644 index 00000000..85384f7c --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_rtc_l21.h @@ -0,0 +1,6235 @@ +/** + * \file + * + * \brief SAM RTC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_RTC_COMPONENT_ +#ifndef _HRI_RTC_L21_H_INCLUDED_ +#define _HRI_RTC_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_RTC_CRITICAL_SECTIONS) +#define RTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define RTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define RTC_CRITICAL_SECTION_ENTER() +#define RTC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_rtcmode0_ctrla_reg_t; +typedef uint16_t hri_rtcmode0_intenset_reg_t; +typedef uint16_t hri_rtcmode0_intflag_reg_t; +typedef uint16_t hri_rtcmode1_comp_reg_t; +typedef uint16_t hri_rtcmode1_count_reg_t; +typedef uint16_t hri_rtcmode1_ctrla_reg_t; +typedef uint16_t hri_rtcmode1_intenset_reg_t; +typedef uint16_t hri_rtcmode1_intflag_reg_t; +typedef uint16_t hri_rtcmode1_per_reg_t; +typedef uint16_t hri_rtcmode2_ctrla_reg_t; +typedef uint16_t hri_rtcmode2_intenset_reg_t; +typedef uint16_t hri_rtcmode2_intflag_reg_t; +typedef uint32_t hri_rtc_gp_reg_t; +typedef uint32_t hri_rtcalarm_alarm_reg_t; +typedef uint32_t hri_rtcmode0_comp_reg_t; +typedef uint32_t hri_rtcmode0_count_reg_t; +typedef uint32_t hri_rtcmode0_evctrl_reg_t; +typedef uint32_t hri_rtcmode0_syncbusy_reg_t; +typedef uint32_t hri_rtcmode1_evctrl_reg_t; +typedef uint32_t hri_rtcmode1_syncbusy_reg_t; +typedef uint32_t hri_rtcmode2_alarm_reg_t; +typedef uint32_t hri_rtcmode2_clock_reg_t; +typedef uint32_t hri_rtcmode2_evctrl_reg_t; +typedef uint32_t hri_rtcmode2_syncbusy_reg_t; +typedef uint8_t hri_rtc_dbgctrl_reg_t; +typedef uint8_t hri_rtc_freqcorr_reg_t; +typedef uint8_t hri_rtcalarm_mask_reg_t; +typedef uint8_t hri_rtcmode2_mask_reg_t; + +static inline void hri_rtcmode0_wait_for_sync(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg) +{ + while (((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_rtcmode0_is_syncing(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg) +{ + return ((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg; +} + +static inline void hri_rtcmode1_wait_for_sync(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg) +{ + while (((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_rtcmode1_is_syncing(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg) +{ + return ((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg; +} + +static inline void hri_rtcmode2_wait_for_sync(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg) +{ + while (((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_rtcmode2_is_syncing(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg) +{ + return ((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg; +} + +static inline void hri_rtcalarm_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_SECOND_Msk; + tmp |= RTC_MODE2_ALARM_SECOND(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk; + tmp |= RTC_MODE2_ALARM_MINUTE(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_HOUR_Msk; + tmp |= RTC_MODE2_ALARM_HOUR(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_DAY_Msk; + tmp |= RTC_MODE2_ALARM_DAY(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MONTH_Msk; + tmp |= RTC_MODE2_ALARM_MONTH(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_YEAR_Msk; + tmp |= RTC_MODE2_ALARM_YEAR(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_reg(const void *const hw, uint8_t submodule_index) +{ + return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; +} + +static inline void hri_rtcalarm_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t data) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp &= ~RTC_MODE2_MASK_SEL_Msk; + tmp |= RTC_MODE2_MASK_SEL(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_get_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcalarm_write_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_read_MASK_reg(const void *const hw, uint8_t submodule_index) +{ + return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; +} + +static inline void hri_rtcmode2_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_SECOND_Msk; + tmp |= RTC_MODE2_ALARM_SECOND(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk; + tmp |= RTC_MODE2_ALARM_MINUTE(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_HOUR_Msk; + tmp |= RTC_MODE2_ALARM_HOUR(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_DAY_Msk; + tmp |= RTC_MODE2_ALARM_DAY(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MONTH_Msk; + tmp |= RTC_MODE2_ALARM_MONTH(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_YEAR_Msk; + tmp |= RTC_MODE2_ALARM_YEAR(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; +} + +static inline void hri_rtcmode2_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t data) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp &= ~RTC_MODE2_MASK_SEL_Msk; + tmp |= RTC_MODE2_MASK_SEL(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER0) >> RTC_MODE0_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER0; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER1) >> RTC_MODE0_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER1; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER2) >> RTC_MODE0_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER3) >> RTC_MODE0_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER3; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER4) >> RTC_MODE0_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER4; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER5) >> RTC_MODE0_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER5; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER6) >> RTC_MODE0_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER6; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER7) >> RTC_MODE0_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER7; +} + +static inline bool hri_rtcmode0_get_INTFLAG_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode0_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF; +} + +static inline bool hri_rtcmode0_get_interrupt_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER0) >> RTC_MODE0_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER0; +} + +static inline bool hri_rtcmode0_get_interrupt_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER1) >> RTC_MODE0_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER1; +} + +static inline bool hri_rtcmode0_get_interrupt_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER2) >> RTC_MODE0_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2; +} + +static inline bool hri_rtcmode0_get_interrupt_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER3) >> RTC_MODE0_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER3; +} + +static inline bool hri_rtcmode0_get_interrupt_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER4) >> RTC_MODE0_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER4; +} + +static inline bool hri_rtcmode0_get_interrupt_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER5) >> RTC_MODE0_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER5; +} + +static inline bool hri_rtcmode0_get_interrupt_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER6) >> RTC_MODE0_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER6; +} + +static inline bool hri_rtcmode0_get_interrupt_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER7) >> RTC_MODE0_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER7; +} + +static inline bool hri_rtcmode0_get_interrupt_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode0_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF; +} + +static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_get_INTFLAG_reg(const void *const hw, + hri_rtcmode0_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_read_INTFLAG_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.INTFLAG.reg; +} + +static inline void hri_rtcmode0_clear_INTFLAG_reg(const void *const hw, hri_rtcmode0_intflag_reg_t mask) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = mask; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER0) >> RTC_MODE1_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER0; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER1) >> RTC_MODE1_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER1; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER2) >> RTC_MODE1_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER2; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER3) >> RTC_MODE1_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER3; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER4) >> RTC_MODE1_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER4; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER5) >> RTC_MODE1_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER5; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER6) >> RTC_MODE1_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER6; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER7) >> RTC_MODE1_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER7; +} + +static inline bool hri_rtcmode1_get_INTFLAG_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode1_get_INTFLAG_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1; +} + +static inline bool hri_rtcmode1_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF; +} + +static inline bool hri_rtcmode1_get_interrupt_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER0) >> RTC_MODE1_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER0; +} + +static inline bool hri_rtcmode1_get_interrupt_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER1) >> RTC_MODE1_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER1; +} + +static inline bool hri_rtcmode1_get_interrupt_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER2) >> RTC_MODE1_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER2; +} + +static inline bool hri_rtcmode1_get_interrupt_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER3) >> RTC_MODE1_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER3; +} + +static inline bool hri_rtcmode1_get_interrupt_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER4) >> RTC_MODE1_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER4; +} + +static inline bool hri_rtcmode1_get_interrupt_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER5) >> RTC_MODE1_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER5; +} + +static inline bool hri_rtcmode1_get_interrupt_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER6) >> RTC_MODE1_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER6; +} + +static inline bool hri_rtcmode1_get_interrupt_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER7) >> RTC_MODE1_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER7; +} + +static inline bool hri_rtcmode1_get_interrupt_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode1_get_interrupt_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1; +} + +static inline bool hri_rtcmode1_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF; +} + +static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_get_INTFLAG_reg(const void *const hw, + hri_rtcmode1_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_read_INTFLAG_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.INTFLAG.reg; +} + +static inline void hri_rtcmode1_clear_INTFLAG_reg(const void *const hw, hri_rtcmode1_intflag_reg_t mask) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = mask; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER0) >> RTC_MODE2_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER0; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER1) >> RTC_MODE2_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER1; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER2) >> RTC_MODE2_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER2; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER3) >> RTC_MODE2_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER3; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER4) >> RTC_MODE2_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER4; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER5) >> RTC_MODE2_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER5; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER6) >> RTC_MODE2_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER6; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER7) >> RTC_MODE2_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER7; +} + +static inline bool hri_rtcmode2_get_INTFLAG_ALARM0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0; +} + +static inline bool hri_rtcmode2_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF; +} + +static inline bool hri_rtcmode2_get_interrupt_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER0) >> RTC_MODE2_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER0; +} + +static inline bool hri_rtcmode2_get_interrupt_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER1) >> RTC_MODE2_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER1; +} + +static inline bool hri_rtcmode2_get_interrupt_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER2) >> RTC_MODE2_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER2; +} + +static inline bool hri_rtcmode2_get_interrupt_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER3) >> RTC_MODE2_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER3; +} + +static inline bool hri_rtcmode2_get_interrupt_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER4) >> RTC_MODE2_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER4; +} + +static inline bool hri_rtcmode2_get_interrupt_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER5) >> RTC_MODE2_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER5; +} + +static inline bool hri_rtcmode2_get_interrupt_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER6) >> RTC_MODE2_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER6; +} + +static inline bool hri_rtcmode2_get_interrupt_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER7) >> RTC_MODE2_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER7; +} + +static inline bool hri_rtcmode2_get_interrupt_ALARM0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0; +} + +static inline bool hri_rtcmode2_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF; +} + +static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_get_INTFLAG_reg(const void *const hw, + hri_rtcmode2_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_read_INTFLAG_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.INTFLAG.reg; +} + +static inline void hri_rtcmode2_clear_INTFLAG_reg(const void *const hw, hri_rtcmode2_intflag_reg_t mask) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = mask; +} + +static inline void hri_rtcmode0_set_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0; +} + +static inline bool hri_rtcmode0_get_INTEN_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER0) >> RTC_MODE0_INTENSET_PER0_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0; +} + +static inline void hri_rtcmode0_set_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER1; +} + +static inline bool hri_rtcmode0_get_INTEN_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER1) >> RTC_MODE0_INTENSET_PER1_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER1; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER1; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER1; +} + +static inline void hri_rtcmode0_set_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2; +} + +static inline bool hri_rtcmode0_get_INTEN_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER2) >> RTC_MODE0_INTENSET_PER2_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER2; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER2; +} + +static inline void hri_rtcmode0_set_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER3; +} + +static inline bool hri_rtcmode0_get_INTEN_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER3) >> RTC_MODE0_INTENSET_PER3_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER3; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER3; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER3; +} + +static inline void hri_rtcmode0_set_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER4; +} + +static inline bool hri_rtcmode0_get_INTEN_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER4) >> RTC_MODE0_INTENSET_PER4_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER4; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER4; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER4; +} + +static inline void hri_rtcmode0_set_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER5; +} + +static inline bool hri_rtcmode0_get_INTEN_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER5) >> RTC_MODE0_INTENSET_PER5_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER5; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER5; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER5; +} + +static inline void hri_rtcmode0_set_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER6; +} + +static inline bool hri_rtcmode0_get_INTEN_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER6) >> RTC_MODE0_INTENSET_PER6_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER6; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER6; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER6; +} + +static inline void hri_rtcmode0_set_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER7; +} + +static inline bool hri_rtcmode0_get_INTEN_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER7) >> RTC_MODE0_INTENSET_PER7_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER7; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER7; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER7; +} + +static inline void hri_rtcmode0_set_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0; +} + +static inline bool hri_rtcmode0_get_INTEN_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_CMP0) >> RTC_MODE0_INTENSET_CMP0_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_CMP0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0; + } +} + +static inline void hri_rtcmode0_clear_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0; +} + +static inline void hri_rtcmode0_set_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF; +} + +static inline bool hri_rtcmode0_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_OVF) >> RTC_MODE0_INTENSET_OVF_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF; + } +} + +static inline void hri_rtcmode0_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF; +} + +static inline void hri_rtcmode0_set_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = mask; +} + +static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_get_INTEN_reg(const void *const hw, + hri_rtcmode0_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_read_INTEN_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.INTENSET.reg; +} + +static inline void hri_rtcmode0_write_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t data) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = data; + ((Rtc *)hw)->MODE0.INTENCLR.reg = ~data; +} + +static inline void hri_rtcmode0_clear_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = mask; +} + +static inline void hri_rtcmode1_set_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0; +} + +static inline bool hri_rtcmode1_get_INTEN_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER0) >> RTC_MODE1_INTENSET_PER0_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0; +} + +static inline void hri_rtcmode1_set_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER1; +} + +static inline bool hri_rtcmode1_get_INTEN_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER1) >> RTC_MODE1_INTENSET_PER1_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER1; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER1; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER1; +} + +static inline void hri_rtcmode1_set_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER2; +} + +static inline bool hri_rtcmode1_get_INTEN_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER2) >> RTC_MODE1_INTENSET_PER2_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER2; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER2; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER2; +} + +static inline void hri_rtcmode1_set_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER3; +} + +static inline bool hri_rtcmode1_get_INTEN_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER3) >> RTC_MODE1_INTENSET_PER3_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER3; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER3; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER3; +} + +static inline void hri_rtcmode1_set_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER4; +} + +static inline bool hri_rtcmode1_get_INTEN_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER4) >> RTC_MODE1_INTENSET_PER4_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER4; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER4; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER4; +} + +static inline void hri_rtcmode1_set_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER5; +} + +static inline bool hri_rtcmode1_get_INTEN_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER5) >> RTC_MODE1_INTENSET_PER5_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER5; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER5; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER5; +} + +static inline void hri_rtcmode1_set_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER6; +} + +static inline bool hri_rtcmode1_get_INTEN_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER6) >> RTC_MODE1_INTENSET_PER6_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER6; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER6; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER6; +} + +static inline void hri_rtcmode1_set_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER7; +} + +static inline bool hri_rtcmode1_get_INTEN_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER7) >> RTC_MODE1_INTENSET_PER7_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER7; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER7; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER7; +} + +static inline void hri_rtcmode1_set_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0; +} + +static inline bool hri_rtcmode1_get_INTEN_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP0) >> RTC_MODE1_INTENSET_CMP0_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_CMP0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0; + } +} + +static inline void hri_rtcmode1_clear_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0; +} + +static inline void hri_rtcmode1_set_INTEN_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1; +} + +static inline bool hri_rtcmode1_get_INTEN_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP1) >> RTC_MODE1_INTENSET_CMP1_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_CMP1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1; + } +} + +static inline void hri_rtcmode1_clear_INTEN_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1; +} + +static inline void hri_rtcmode1_set_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF; +} + +static inline bool hri_rtcmode1_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_OVF) >> RTC_MODE1_INTENSET_OVF_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF; + } +} + +static inline void hri_rtcmode1_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF; +} + +static inline void hri_rtcmode1_set_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = mask; +} + +static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_get_INTEN_reg(const void *const hw, + hri_rtcmode1_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_read_INTEN_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.INTENSET.reg; +} + +static inline void hri_rtcmode1_write_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t data) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = data; + ((Rtc *)hw)->MODE1.INTENCLR.reg = ~data; +} + +static inline void hri_rtcmode1_clear_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = mask; +} + +static inline void hri_rtcmode2_set_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0; +} + +static inline bool hri_rtcmode2_get_INTEN_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER0) >> RTC_MODE2_INTENSET_PER0_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0; +} + +static inline void hri_rtcmode2_set_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1; +} + +static inline bool hri_rtcmode2_get_INTEN_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER1) >> RTC_MODE2_INTENSET_PER1_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1; +} + +static inline void hri_rtcmode2_set_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2; +} + +static inline bool hri_rtcmode2_get_INTEN_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER2) >> RTC_MODE2_INTENSET_PER2_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2; +} + +static inline void hri_rtcmode2_set_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER3; +} + +static inline bool hri_rtcmode2_get_INTEN_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER3) >> RTC_MODE2_INTENSET_PER3_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER3; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3; +} + +static inline void hri_rtcmode2_set_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER4; +} + +static inline bool hri_rtcmode2_get_INTEN_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER4) >> RTC_MODE2_INTENSET_PER4_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER4; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4; +} + +static inline void hri_rtcmode2_set_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER5; +} + +static inline bool hri_rtcmode2_get_INTEN_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER5) >> RTC_MODE2_INTENSET_PER5_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER5; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER5; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER5; +} + +static inline void hri_rtcmode2_set_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER6; +} + +static inline bool hri_rtcmode2_get_INTEN_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER6) >> RTC_MODE2_INTENSET_PER6_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER6; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER6; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER6; +} + +static inline void hri_rtcmode2_set_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7; +} + +static inline bool hri_rtcmode2_get_INTEN_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER7) >> RTC_MODE2_INTENSET_PER7_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER7; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER7; +} + +static inline void hri_rtcmode2_set_INTEN_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0; +} + +static inline bool hri_rtcmode2_get_INTEN_ALARM0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_ALARM0) >> RTC_MODE2_INTENSET_ALARM0_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_ALARM0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0; + } +} + +static inline void hri_rtcmode2_clear_INTEN_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0; +} + +static inline void hri_rtcmode2_set_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF; +} + +static inline bool hri_rtcmode2_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_OVF) >> RTC_MODE2_INTENSET_OVF_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF; + } +} + +static inline void hri_rtcmode2_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF; +} + +static inline void hri_rtcmode2_set_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = mask; +} + +static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_get_INTEN_reg(const void *const hw, + hri_rtcmode2_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_read_INTEN_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.INTENSET.reg; +} + +static inline void hri_rtcmode2_write_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t data) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = data; + ((Rtc *)hw)->MODE2.INTENCLR.reg = ~data; +} + +static inline void hri_rtcmode2_clear_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = mask; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_SWRST) >> RTC_MODE0_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_ENABLE) >> RTC_MODE0_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_FREQCORR_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_FREQCORR) >> RTC_MODE0_SYNCBUSY_FREQCORR_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COUNT) >> RTC_MODE0_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_COMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COMP0) >> RTC_MODE0_SYNCBUSY_COMP0_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_COUNTSYNC_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COUNTSYNC) >> RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos; +} + +static inline hri_rtcmode0_syncbusy_reg_t hri_rtcmode0_get_SYNCBUSY_reg(const void *const hw, + hri_rtcmode0_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode0_syncbusy_reg_t hri_rtcmode0_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.SYNCBUSY.reg; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_SWRST) >> RTC_MODE1_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_ENABLE) >> RTC_MODE1_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_FREQCORR_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_FREQCORR) >> RTC_MODE1_SYNCBUSY_FREQCORR_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COUNT) >> RTC_MODE1_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_PER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_PER) >> RTC_MODE1_SYNCBUSY_PER_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP0) >> RTC_MODE1_SYNCBUSY_COMP0_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP1) >> RTC_MODE1_SYNCBUSY_COMP1_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COUNTSYNC_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COUNTSYNC) >> RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos; +} + +static inline hri_rtcmode1_syncbusy_reg_t hri_rtcmode1_get_SYNCBUSY_reg(const void *const hw, + hri_rtcmode1_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode1_syncbusy_reg_t hri_rtcmode1_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.SYNCBUSY.reg; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_SWRST) >> RTC_MODE2_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ENABLE) >> RTC_MODE2_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_FREQCORR_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_FREQCORR) >> RTC_MODE2_SYNCBUSY_FREQCORR_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_CLOCK_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_CLOCK) >> RTC_MODE2_SYNCBUSY_CLOCK_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_ALARM0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ALARM0) >> RTC_MODE2_SYNCBUSY_ALARM0_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_MASK0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_MASK0) >> RTC_MODE2_SYNCBUSY_MASK0_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_CLOCKSYNC_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_CLOCKSYNC) >> RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos; +} + +static inline hri_rtcmode2_syncbusy_reg_t hri_rtcmode2_get_SYNCBUSY_reg(const void *const hw, + hri_rtcmode2_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode2_syncbusy_reg_t hri_rtcmode2_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.SYNCBUSY.reg; +} + +static inline void hri_rtcmode0_set_CTRLA_SWRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_SWRST; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_SWRST) >> RTC_MODE0_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_set_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_ENABLE; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_ENABLE) >> RTC_MODE0_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_ENABLE; + tmp |= value << RTC_MODE0_CTRLA_ENABLE_Pos; + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_ENABLE; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_ENABLE; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MATCHCLR; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_MATCHCLR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_MATCHCLR) >> RTC_MODE0_CTRLA_MATCHCLR_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_MATCHCLR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_MATCHCLR; + tmp |= value << RTC_MODE0_CTRLA_MATCHCLR_Pos; + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_MATCHCLR; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_MATCHCLR; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_COUNTSYNC; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_COUNTSYNC) >> RTC_MODE0_CTRLA_COUNTSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_COUNTSYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_COUNTSYNC; + tmp |= value << RTC_MODE0_CTRLA_COUNTSYNC_Pos; + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_COUNTSYNC; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_COUNTSYNC; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MODE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_MODE_bf(const void *const hw, + hri_rtcmode0_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_MODE(mask)) >> RTC_MODE0_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_MODE_Msk; + tmp |= RTC_MODE0_CTRLA_MODE(data); + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_MODE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_MODE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_MODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_MODE_Msk) >> RTC_MODE0_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_PRESCALER(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_PRESCALER_bf(const void *const hw, + hri_rtcmode0_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_PRESCALER(mask)) >> RTC_MODE0_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_PRESCALER_Msk; + tmp |= RTC_MODE0_CTRLA_PRESCALER(data); + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_PRESCALER(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_PRESCALER(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_PRESCALER_Msk) >> RTC_MODE0_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg = data; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_reg(const void *const hw) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + return ((Rtc *)hw)->MODE0.CTRLA.reg; +} + +static inline void hri_rtcmode1_set_CTRLA_SWRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_SWRST; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_SWRST) >> RTC_MODE1_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_set_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_ENABLE; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_ENABLE) >> RTC_MODE1_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_ENABLE; + tmp |= value << RTC_MODE1_CTRLA_ENABLE_Pos; + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_ENABLE; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_ENABLE; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_COUNTSYNC; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_COUNTSYNC) >> RTC_MODE1_CTRLA_COUNTSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_COUNTSYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_COUNTSYNC; + tmp |= value << RTC_MODE1_CTRLA_COUNTSYNC_Pos; + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_COUNTSYNC; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_COUNTSYNC; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_MODE(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_MODE_bf(const void *const hw, + hri_rtcmode1_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_MODE(mask)) >> RTC_MODE1_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_MODE_Msk; + tmp |= RTC_MODE1_CTRLA_MODE(data); + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_MODE(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_MODE(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_MODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_MODE_Msk) >> RTC_MODE1_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_PRESCALER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_PRESCALER_bf(const void *const hw, + hri_rtcmode1_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_PRESCALER(mask)) >> RTC_MODE1_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_PRESCALER_Msk; + tmp |= RTC_MODE1_CTRLA_PRESCALER(data); + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_PRESCALER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_PRESCALER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_PRESCALER_Msk) >> RTC_MODE1_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg = data; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_reg(const void *const hw) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + return ((Rtc *)hw)->MODE1.CTRLA.reg; +} + +static inline void hri_rtcmode2_set_CTRLA_SWRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_SWRST; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_SWRST) >> RTC_MODE2_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_set_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_ENABLE; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_ENABLE) >> RTC_MODE2_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_ENABLE; + tmp |= value << RTC_MODE2_CTRLA_ENABLE_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_ENABLE; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_ENABLE; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_CLKREP_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_CLKREP; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_CLKREP_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_CLKREP) >> RTC_MODE2_CTRLA_CLKREP_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_CLKREP_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_CLKREP; + tmp |= value << RTC_MODE2_CTRLA_CLKREP_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_CLKREP_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_CLKREP; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_CLKREP_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLKREP; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_MATCHCLR; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_MATCHCLR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_MATCHCLR) >> RTC_MODE2_CTRLA_MATCHCLR_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_MATCHCLR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_MATCHCLR; + tmp |= value << RTC_MODE2_CTRLA_MATCHCLR_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_MATCHCLR; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_MATCHCLR; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_CLOCKSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_CLOCKSYNC; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_CLOCKSYNC_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_CLOCKSYNC) >> RTC_MODE2_CTRLA_CLOCKSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_CLOCKSYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_CLOCKSYNC; + tmp |= value << RTC_MODE2_CTRLA_CLOCKSYNC_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_CLOCKSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_CLOCKSYNC; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_CLOCKSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLOCKSYNC; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_MODE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_MODE_bf(const void *const hw, + hri_rtcmode2_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_MODE(mask)) >> RTC_MODE2_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_MODE_Msk; + tmp |= RTC_MODE2_CTRLA_MODE(data); + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_MODE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_MODE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_MODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_MODE_Msk) >> RTC_MODE2_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_PRESCALER(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_PRESCALER_bf(const void *const hw, + hri_rtcmode2_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_PRESCALER(mask)) >> RTC_MODE2_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_PRESCALER_Msk; + tmp |= RTC_MODE2_CTRLA_PRESCALER(data); + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_PRESCALER(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_PRESCALER(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_PRESCALER_Msk) >> RTC_MODE2_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg = data; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_reg(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + return ((Rtc *)hw)->MODE2.CTRLA.reg; +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO0) >> RTC_MODE0_EVCTRL_PEREO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO0; + tmp |= value << RTC_MODE0_EVCTRL_PEREO0_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO1) >> RTC_MODE0_EVCTRL_PEREO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO1; + tmp |= value << RTC_MODE0_EVCTRL_PEREO1_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO2) >> RTC_MODE0_EVCTRL_PEREO2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO2; + tmp |= value << RTC_MODE0_EVCTRL_PEREO2_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO3) >> RTC_MODE0_EVCTRL_PEREO3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO3; + tmp |= value << RTC_MODE0_EVCTRL_PEREO3_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO4) >> RTC_MODE0_EVCTRL_PEREO4_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO4; + tmp |= value << RTC_MODE0_EVCTRL_PEREO4_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO5) >> RTC_MODE0_EVCTRL_PEREO5_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO5; + tmp |= value << RTC_MODE0_EVCTRL_PEREO5_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO6) >> RTC_MODE0_EVCTRL_PEREO6_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO6; + tmp |= value << RTC_MODE0_EVCTRL_PEREO6_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO7) >> RTC_MODE0_EVCTRL_PEREO7_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO7; + tmp |= value << RTC_MODE0_EVCTRL_PEREO7_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_CMPEO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_CMPEO0) >> RTC_MODE0_EVCTRL_CMPEO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_CMPEO0; + tmp |= value << RTC_MODE0_EVCTRL_CMPEO0_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_OVFEO) >> RTC_MODE0_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_OVFEO; + tmp |= value << RTC_MODE0_EVCTRL_OVFEO_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_get_EVCTRL_reg(const void *const hw, + hri_rtcmode0_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_read_EVCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.EVCTRL.reg; +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO0) >> RTC_MODE1_EVCTRL_PEREO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO0; + tmp |= value << RTC_MODE1_EVCTRL_PEREO0_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO1) >> RTC_MODE1_EVCTRL_PEREO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO1; + tmp |= value << RTC_MODE1_EVCTRL_PEREO1_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO2) >> RTC_MODE1_EVCTRL_PEREO2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO2; + tmp |= value << RTC_MODE1_EVCTRL_PEREO2_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO3) >> RTC_MODE1_EVCTRL_PEREO3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO3; + tmp |= value << RTC_MODE1_EVCTRL_PEREO3_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO4) >> RTC_MODE1_EVCTRL_PEREO4_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO4; + tmp |= value << RTC_MODE1_EVCTRL_PEREO4_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO5) >> RTC_MODE1_EVCTRL_PEREO5_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO5; + tmp |= value << RTC_MODE1_EVCTRL_PEREO5_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO6) >> RTC_MODE1_EVCTRL_PEREO6_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO6; + tmp |= value << RTC_MODE1_EVCTRL_PEREO6_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO7) >> RTC_MODE1_EVCTRL_PEREO7_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO7; + tmp |= value << RTC_MODE1_EVCTRL_PEREO7_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_CMPEO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO0) >> RTC_MODE1_EVCTRL_CMPEO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_CMPEO0; + tmp |= value << RTC_MODE1_EVCTRL_CMPEO0_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_CMPEO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO1) >> RTC_MODE1_EVCTRL_CMPEO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_CMPEO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_CMPEO1; + tmp |= value << RTC_MODE1_EVCTRL_CMPEO1_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_OVFEO) >> RTC_MODE1_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_OVFEO; + tmp |= value << RTC_MODE1_EVCTRL_OVFEO_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_get_EVCTRL_reg(const void *const hw, + hri_rtcmode1_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_read_EVCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.EVCTRL.reg; +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO0) >> RTC_MODE2_EVCTRL_PEREO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO0; + tmp |= value << RTC_MODE2_EVCTRL_PEREO0_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO1) >> RTC_MODE2_EVCTRL_PEREO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO1; + tmp |= value << RTC_MODE2_EVCTRL_PEREO1_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO2) >> RTC_MODE2_EVCTRL_PEREO2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO2; + tmp |= value << RTC_MODE2_EVCTRL_PEREO2_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO3) >> RTC_MODE2_EVCTRL_PEREO3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO3; + tmp |= value << RTC_MODE2_EVCTRL_PEREO3_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO4) >> RTC_MODE2_EVCTRL_PEREO4_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO4; + tmp |= value << RTC_MODE2_EVCTRL_PEREO4_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO5) >> RTC_MODE2_EVCTRL_PEREO5_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO5; + tmp |= value << RTC_MODE2_EVCTRL_PEREO5_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO6) >> RTC_MODE2_EVCTRL_PEREO6_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO6; + tmp |= value << RTC_MODE2_EVCTRL_PEREO6_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO7) >> RTC_MODE2_EVCTRL_PEREO7_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO7; + tmp |= value << RTC_MODE2_EVCTRL_PEREO7_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_ALARMEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_ALARMEO0) >> RTC_MODE2_EVCTRL_ALARMEO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_ALARMEO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_ALARMEO0; + tmp |= value << RTC_MODE2_EVCTRL_ALARMEO0_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_ALARMEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_ALARMEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_OVFEO) >> RTC_MODE2_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_OVFEO; + tmp |= value << RTC_MODE2_EVCTRL_OVFEO_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_get_EVCTRL_reg(const void *const hw, + hri_rtcmode2_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_read_EVCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.EVCTRL.reg; +} + +static inline void hri_rtc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg |= RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; + tmp = (tmp & RTC_DBGCTRL_DBGRUN) >> RTC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; + tmp &= ~RTC_DBGCTRL_DBGRUN; + tmp |= value << RTC_DBGCTRL_DBGRUN_Pos; + ((Rtc *)hw)->MODE0.DBGCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg ^= RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_dbgctrl_reg_t hri_rtc_get_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_dbgctrl_reg_t hri_rtc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.DBGCTRL.reg; +} + +static inline void hri_rtc_set_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_SIGN; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_FREQCORR_SIGN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_SIGN) >> RTC_FREQCORR_SIGN_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_FREQCORR_SIGN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp &= ~RTC_FREQCORR_SIGN; + tmp |= value << RTC_FREQCORR_SIGN_Pos; + ((Rtc *)hw)->MODE0.FREQCORR.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_SIGN; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_SIGN; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_VALUE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_freqcorr_reg_t hri_rtc_get_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_VALUE(mask)) >> RTC_FREQCORR_VALUE_Pos; + return tmp; +} + +static inline void hri_rtc_write_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t data) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp &= ~RTC_FREQCORR_VALUE_Msk; + tmp |= RTC_FREQCORR_VALUE(data); + ((Rtc *)hw)->MODE0.FREQCORR.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_VALUE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_VALUE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_freqcorr_reg_t hri_rtc_read_FREQCORR_VALUE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_VALUE_Msk) >> RTC_FREQCORR_VALUE_Pos; + return tmp; +} + +static inline void hri_rtc_set_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg |= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_freqcorr_reg_t hri_rtc_get_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + uint8_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg = data; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg ^= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_freqcorr_reg_t hri_rtc_read_FREQCORR_reg(const void *const hw) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + return ((Rtc *)hw)->MODE0.FREQCORR.reg; +} + +static inline void hri_rtcmode0_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg |= RTC_MODE0_COUNT_COUNT(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_COUNT_bf(const void *const hw, + hri_rtcmode0_count_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp = (tmp & RTC_MODE0_COUNT_COUNT(mask)) >> RTC_MODE0_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp &= ~RTC_MODE0_COUNT_COUNT_Msk; + tmp |= RTC_MODE0_COUNT_COUNT(data); + ((Rtc *)hw)->MODE0.COUNT.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg &= ~RTC_MODE0_COUNT_COUNT(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg ^= RTC_MODE0_COUNT_COUNT(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp = (tmp & RTC_MODE0_COUNT_COUNT_Msk) >> RTC_MODE0_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg |= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg = data; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg &= ~mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg ^= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_reg(const void *const hw) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + return ((Rtc *)hw)->MODE0.COUNT.reg; +} + +static inline void hri_rtcmode1_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg |= RTC_MODE1_COUNT_COUNT(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_COUNT_bf(const void *const hw, + hri_rtcmode1_count_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp = (tmp & RTC_MODE1_COUNT_COUNT(mask)) >> RTC_MODE1_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp &= ~RTC_MODE1_COUNT_COUNT_Msk; + tmp |= RTC_MODE1_COUNT_COUNT(data); + ((Rtc *)hw)->MODE1.COUNT.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg &= ~RTC_MODE1_COUNT_COUNT(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg ^= RTC_MODE1_COUNT_COUNT(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_COUNT_bf(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp = (tmp & RTC_MODE1_COUNT_COUNT_Msk) >> RTC_MODE1_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg |= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg = data; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg &= ~mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg ^= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_reg(const void *const hw) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + return ((Rtc *)hw)->MODE1.COUNT.reg; +} + +static inline void hri_rtcmode2_set_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_SECOND(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_SECOND_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_SECOND(mask)) >> RTC_MODE2_CLOCK_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_SECOND_Msk; + tmp |= RTC_MODE2_CLOCK_SECOND(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_SECOND(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_SECOND(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_SECOND_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_SECOND_Msk) >> RTC_MODE2_CLOCK_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MINUTE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MINUTE_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MINUTE(mask)) >> RTC_MODE2_CLOCK_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_MINUTE_Msk; + tmp |= RTC_MODE2_CLOCK_MINUTE(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MINUTE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MINUTE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MINUTE_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MINUTE_Msk) >> RTC_MODE2_CLOCK_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_HOUR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_HOUR_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_HOUR(mask)) >> RTC_MODE2_CLOCK_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_HOUR_Msk; + tmp |= RTC_MODE2_CLOCK_HOUR(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_HOUR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_HOUR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_HOUR_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_HOUR_Msk) >> RTC_MODE2_CLOCK_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_DAY(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_DAY_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_DAY(mask)) >> RTC_MODE2_CLOCK_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_DAY_Msk; + tmp |= RTC_MODE2_CLOCK_DAY(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_DAY(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_DAY(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_DAY_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_DAY_Msk) >> RTC_MODE2_CLOCK_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MONTH(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MONTH_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MONTH(mask)) >> RTC_MODE2_CLOCK_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_MONTH_Msk; + tmp |= RTC_MODE2_CLOCK_MONTH(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MONTH(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MONTH(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MONTH_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MONTH_Msk) >> RTC_MODE2_CLOCK_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_YEAR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_YEAR_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_YEAR(mask)) >> RTC_MODE2_CLOCK_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_YEAR_Msk; + tmp |= RTC_MODE2_CLOCK_YEAR(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_YEAR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_YEAR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_YEAR_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_YEAR_Msk) >> RTC_MODE2_CLOCK_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg = data; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_reg(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return ((Rtc *)hw)->MODE2.CLOCK.reg; +} + +static inline void hri_rtcmode1_set_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg |= RTC_MODE1_PER_PER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp = (tmp & RTC_MODE1_PER_PER(mask)) >> RTC_MODE1_PER_PER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp &= ~RTC_MODE1_PER_PER_Msk; + tmp |= RTC_MODE1_PER_PER(data); + ((Rtc *)hw)->MODE1.PER.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg &= ~RTC_MODE1_PER_PER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg ^= RTC_MODE1_PER_PER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_PER_bf(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp = (tmp & RTC_MODE1_PER_PER_Msk) >> RTC_MODE1_PER_PER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg |= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg = data; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg &= ~mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg ^= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_reg(const void *const hw) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + return ((Rtc *)hw)->MODE1.PER.reg; +} + +static inline void hri_rtcmode0_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg |= RTC_MODE0_COMP_COMP(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_COMP_bf(const void *const hw, uint8_t index, + hri_rtcmode0_comp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp = (tmp & RTC_MODE0_COMP_COMP(mask)) >> RTC_MODE0_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp &= ~RTC_MODE0_COMP_COMP_Msk; + tmp |= RTC_MODE0_COMP_COMP(data); + ((Rtc *)hw)->MODE0.COMP[index].reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg &= ~RTC_MODE0_COMP_COMP(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg ^= RTC_MODE0_COMP_COMP(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_COMP_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp = (tmp & RTC_MODE0_COMP_COMP_Msk) >> RTC_MODE0_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg |= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_reg(const void *const hw, uint8_t index, + hri_rtcmode0_comp_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg = data; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg &= ~mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg ^= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_reg(const void *const hw, uint8_t index) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + return ((Rtc *)hw)->MODE0.COMP[index].reg; +} + +static inline void hri_rtcmode1_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg |= RTC_MODE1_COMP_COMP(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_COMP_bf(const void *const hw, uint8_t index, + hri_rtcmode1_comp_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp = (tmp & RTC_MODE1_COMP_COMP(mask)) >> RTC_MODE1_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp &= ~RTC_MODE1_COMP_COMP_Msk; + tmp |= RTC_MODE1_COMP_COMP(data); + ((Rtc *)hw)->MODE1.COMP[index].reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg &= ~RTC_MODE1_COMP_COMP(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg ^= RTC_MODE1_COMP_COMP(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_COMP_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp = (tmp & RTC_MODE1_COMP_COMP_Msk) >> RTC_MODE1_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg |= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_reg(const void *const hw, uint8_t index, + hri_rtcmode1_comp_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg = data; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg &= ~mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg ^= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_reg(const void *const hw, uint8_t index) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + return ((Rtc *)hw)->MODE1.COMP[index].reg; +} + +static inline void hri_rtc_set_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_gp_reg_t hri_rtc_get_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.GP[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_gp_reg_t hri_rtc_read_GP_reg(const void *const hw, uint8_t index) +{ + return ((Rtc *)hw)->MODE0.GP[index].reg; +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_rtcmode2_set_DBGCTRL_DBGRUN_bit(a) hri_rtc_set_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode2_get_DBGCTRL_DBGRUN_bit(a) hri_rtc_get_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode2_write_DBGCTRL_DBGRUN_bit(a, b) hri_rtc_write_DBGCTRL_DBGRUN_bit(a, b) +#define hri_rtcmode2_clear_DBGCTRL_DBGRUN_bit(a) hri_rtc_clear_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode2_toggle_DBGCTRL_DBGRUN_bit(a) hri_rtc_toggle_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode2_set_DBGCTRL_reg(a, b) hri_rtc_set_DBGCTRL_reg(a, b) +#define hri_rtcmode2_get_DBGCTRL_reg(a, b) hri_rtc_get_DBGCTRL_reg(a, b) +#define hri_rtcmode2_write_DBGCTRL_reg(a, b) hri_rtc_write_DBGCTRL_reg(a, b) +#define hri_rtcmode2_clear_DBGCTRL_reg(a, b) hri_rtc_clear_DBGCTRL_reg(a, b) +#define hri_rtcmode2_toggle_DBGCTRL_reg(a, b) hri_rtc_toggle_DBGCTRL_reg(a, b) +#define hri_rtcmode2_read_DBGCTRL_reg(a) hri_rtc_read_DBGCTRL_reg(a) +#define hri_rtcmode2_set_FREQCORR_SIGN_bit(a) hri_rtc_set_FREQCORR_SIGN_bit(a) +#define hri_rtcmode2_get_FREQCORR_SIGN_bit(a) hri_rtc_get_FREQCORR_SIGN_bit(a) +#define hri_rtcmode2_write_FREQCORR_SIGN_bit(a, b) hri_rtc_write_FREQCORR_SIGN_bit(a, b) +#define hri_rtcmode2_clear_FREQCORR_SIGN_bit(a) hri_rtc_clear_FREQCORR_SIGN_bit(a) +#define hri_rtcmode2_toggle_FREQCORR_SIGN_bit(a) hri_rtc_toggle_FREQCORR_SIGN_bit(a) +#define hri_rtcmode2_set_FREQCORR_VALUE_bf(a, b) hri_rtc_set_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode2_get_FREQCORR_VALUE_bf(a, b) hri_rtc_get_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode2_write_FREQCORR_VALUE_bf(a, b) hri_rtc_write_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode2_clear_FREQCORR_VALUE_bf(a, b) hri_rtc_clear_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode2_toggle_FREQCORR_VALUE_bf(a, b) hri_rtc_toggle_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode2_read_FREQCORR_VALUE_bf(a) hri_rtc_read_FREQCORR_VALUE_bf(a) +#define hri_rtcmode2_set_FREQCORR_reg(a, b) hri_rtc_set_FREQCORR_reg(a, b) +#define hri_rtcmode2_get_FREQCORR_reg(a, b) hri_rtc_get_FREQCORR_reg(a, b) +#define hri_rtcmode2_write_FREQCORR_reg(a, b) hri_rtc_write_FREQCORR_reg(a, b) +#define hri_rtcmode2_clear_FREQCORR_reg(a, b) hri_rtc_clear_FREQCORR_reg(a, b) +#define hri_rtcmode2_toggle_FREQCORR_reg(a, b) hri_rtc_toggle_FREQCORR_reg(a, b) +#define hri_rtcmode2_read_FREQCORR_reg(a) hri_rtc_read_FREQCORR_reg(a) +#define hri_rtcmode2_set_GP_reg(a, b, c) hri_rtc_set_GP_reg(a, b, c) +#define hri_rtcmode2_get_GP_reg(a, b, c) hri_rtc_get_GP_reg(a, b, c) +#define hri_rtcmode2_write_GP_reg(a, b, c) hri_rtc_write_GP_reg(a, b, c) +#define hri_rtcmode2_clear_GP_reg(a, b, c) hri_rtc_clear_GP_reg(a, b, c) +#define hri_rtcmode2_toggle_GP_reg(a, b, c) hri_rtc_toggle_GP_reg(a, b, c) +#define hri_rtcmode2_read_GP_reg(a, b) hri_rtc_read_GP_reg(a, b) +#define hri_rtcmode0_set_DBGCTRL_DBGRUN_bit(a) hri_rtc_set_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode0_get_DBGCTRL_DBGRUN_bit(a) hri_rtc_get_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode0_write_DBGCTRL_DBGRUN_bit(a, b) hri_rtc_write_DBGCTRL_DBGRUN_bit(a, b) +#define hri_rtcmode0_clear_DBGCTRL_DBGRUN_bit(a) hri_rtc_clear_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode0_toggle_DBGCTRL_DBGRUN_bit(a) hri_rtc_toggle_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode0_set_DBGCTRL_reg(a, b) hri_rtc_set_DBGCTRL_reg(a, b) +#define hri_rtcmode0_get_DBGCTRL_reg(a, b) hri_rtc_get_DBGCTRL_reg(a, b) +#define hri_rtcmode0_write_DBGCTRL_reg(a, b) hri_rtc_write_DBGCTRL_reg(a, b) +#define hri_rtcmode0_clear_DBGCTRL_reg(a, b) hri_rtc_clear_DBGCTRL_reg(a, b) +#define hri_rtcmode0_toggle_DBGCTRL_reg(a, b) hri_rtc_toggle_DBGCTRL_reg(a, b) +#define hri_rtcmode0_read_DBGCTRL_reg(a) hri_rtc_read_DBGCTRL_reg(a) +#define hri_rtcmode0_set_FREQCORR_SIGN_bit(a) hri_rtc_set_FREQCORR_SIGN_bit(a) +#define hri_rtcmode0_get_FREQCORR_SIGN_bit(a) hri_rtc_get_FREQCORR_SIGN_bit(a) +#define hri_rtcmode0_write_FREQCORR_SIGN_bit(a, b) hri_rtc_write_FREQCORR_SIGN_bit(a, b) +#define hri_rtcmode0_clear_FREQCORR_SIGN_bit(a) hri_rtc_clear_FREQCORR_SIGN_bit(a) +#define hri_rtcmode0_toggle_FREQCORR_SIGN_bit(a) hri_rtc_toggle_FREQCORR_SIGN_bit(a) +#define hri_rtcmode0_set_FREQCORR_VALUE_bf(a, b) hri_rtc_set_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode0_get_FREQCORR_VALUE_bf(a, b) hri_rtc_get_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode0_write_FREQCORR_VALUE_bf(a, b) hri_rtc_write_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode0_clear_FREQCORR_VALUE_bf(a, b) hri_rtc_clear_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode0_toggle_FREQCORR_VALUE_bf(a, b) hri_rtc_toggle_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode0_read_FREQCORR_VALUE_bf(a) hri_rtc_read_FREQCORR_VALUE_bf(a) +#define hri_rtcmode0_set_FREQCORR_reg(a, b) hri_rtc_set_FREQCORR_reg(a, b) +#define hri_rtcmode0_get_FREQCORR_reg(a, b) hri_rtc_get_FREQCORR_reg(a, b) +#define hri_rtcmode0_write_FREQCORR_reg(a, b) hri_rtc_write_FREQCORR_reg(a, b) +#define hri_rtcmode0_clear_FREQCORR_reg(a, b) hri_rtc_clear_FREQCORR_reg(a, b) +#define hri_rtcmode0_toggle_FREQCORR_reg(a, b) hri_rtc_toggle_FREQCORR_reg(a, b) +#define hri_rtcmode0_read_FREQCORR_reg(a) hri_rtc_read_FREQCORR_reg(a) +#define hri_rtcmode0_set_GP_reg(a, b, c) hri_rtc_set_GP_reg(a, b, c) +#define hri_rtcmode0_get_GP_reg(a, b, c) hri_rtc_get_GP_reg(a, b, c) +#define hri_rtcmode0_write_GP_reg(a, b, c) hri_rtc_write_GP_reg(a, b, c) +#define hri_rtcmode0_clear_GP_reg(a, b, c) hri_rtc_clear_GP_reg(a, b, c) +#define hri_rtcmode0_toggle_GP_reg(a, b, c) hri_rtc_toggle_GP_reg(a, b, c) +#define hri_rtcmode0_read_GP_reg(a, b) hri_rtc_read_GP_reg(a, b) +#define hri_rtcmode1_set_DBGCTRL_DBGRUN_bit(a) hri_rtc_set_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode1_get_DBGCTRL_DBGRUN_bit(a) hri_rtc_get_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode1_write_DBGCTRL_DBGRUN_bit(a, b) hri_rtc_write_DBGCTRL_DBGRUN_bit(a, b) +#define hri_rtcmode1_clear_DBGCTRL_DBGRUN_bit(a) hri_rtc_clear_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode1_toggle_DBGCTRL_DBGRUN_bit(a) hri_rtc_toggle_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode1_set_DBGCTRL_reg(a, b) hri_rtc_set_DBGCTRL_reg(a, b) +#define hri_rtcmode1_get_DBGCTRL_reg(a, b) hri_rtc_get_DBGCTRL_reg(a, b) +#define hri_rtcmode1_write_DBGCTRL_reg(a, b) hri_rtc_write_DBGCTRL_reg(a, b) +#define hri_rtcmode1_clear_DBGCTRL_reg(a, b) hri_rtc_clear_DBGCTRL_reg(a, b) +#define hri_rtcmode1_toggle_DBGCTRL_reg(a, b) hri_rtc_toggle_DBGCTRL_reg(a, b) +#define hri_rtcmode1_read_DBGCTRL_reg(a) hri_rtc_read_DBGCTRL_reg(a) +#define hri_rtcmode1_set_FREQCORR_SIGN_bit(a) hri_rtc_set_FREQCORR_SIGN_bit(a) +#define hri_rtcmode1_get_FREQCORR_SIGN_bit(a) hri_rtc_get_FREQCORR_SIGN_bit(a) +#define hri_rtcmode1_write_FREQCORR_SIGN_bit(a, b) hri_rtc_write_FREQCORR_SIGN_bit(a, b) +#define hri_rtcmode1_clear_FREQCORR_SIGN_bit(a) hri_rtc_clear_FREQCORR_SIGN_bit(a) +#define hri_rtcmode1_toggle_FREQCORR_SIGN_bit(a) hri_rtc_toggle_FREQCORR_SIGN_bit(a) +#define hri_rtcmode1_set_FREQCORR_VALUE_bf(a, b) hri_rtc_set_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode1_get_FREQCORR_VALUE_bf(a, b) hri_rtc_get_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode1_write_FREQCORR_VALUE_bf(a, b) hri_rtc_write_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode1_clear_FREQCORR_VALUE_bf(a, b) hri_rtc_clear_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode1_toggle_FREQCORR_VALUE_bf(a, b) hri_rtc_toggle_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode1_read_FREQCORR_VALUE_bf(a) hri_rtc_read_FREQCORR_VALUE_bf(a) +#define hri_rtcmode1_set_FREQCORR_reg(a, b) hri_rtc_set_FREQCORR_reg(a, b) +#define hri_rtcmode1_get_FREQCORR_reg(a, b) hri_rtc_get_FREQCORR_reg(a, b) +#define hri_rtcmode1_write_FREQCORR_reg(a, b) hri_rtc_write_FREQCORR_reg(a, b) +#define hri_rtcmode1_clear_FREQCORR_reg(a, b) hri_rtc_clear_FREQCORR_reg(a, b) +#define hri_rtcmode1_toggle_FREQCORR_reg(a, b) hri_rtc_toggle_FREQCORR_reg(a, b) +#define hri_rtcmode1_read_FREQCORR_reg(a) hri_rtc_read_FREQCORR_reg(a) +#define hri_rtcmode1_set_GP_reg(a, b, c) hri_rtc_set_GP_reg(a, b, c) +#define hri_rtcmode1_get_GP_reg(a, b, c) hri_rtc_get_GP_reg(a, b, c) +#define hri_rtcmode1_write_GP_reg(a, b, c) hri_rtc_write_GP_reg(a, b, c) +#define hri_rtcmode1_clear_GP_reg(a, b, c) hri_rtc_clear_GP_reg(a, b, c) +#define hri_rtcmode1_toggle_GP_reg(a, b, c) hri_rtc_toggle_GP_reg(a, b, c) +#define hri_rtcmode1_read_GP_reg(a, b) hri_rtc_read_GP_reg(a, b) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_RTC_L21_H_INCLUDED */ +#endif /* _SAML21_RTC_COMPONENT_ */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_sercom_l21.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_sercom_l21.h new file mode 100644 index 00000000..abc55703 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_sercom_l21.h @@ -0,0 +1,7499 @@ +/** + * \file + * + * \brief SAM SERCOM + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_SERCOM_COMPONENT_ +#ifndef _HRI_SERCOM_L21_H_INCLUDED_ +#define _HRI_SERCOM_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SERCOM_CRITICAL_SECTIONS) +#define SERCOM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SERCOM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SERCOM_CRITICAL_SECTION_ENTER() +#define SERCOM_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_sercomi2cm_status_reg_t; +typedef uint16_t hri_sercomi2cs_status_reg_t; +typedef uint16_t hri_sercomspi_status_reg_t; +typedef uint16_t hri_sercomusart_baud_reg_t; +typedef uint16_t hri_sercomusart_data_reg_t; +typedef uint16_t hri_sercomusart_status_reg_t; +typedef uint32_t hri_sercomi2cm_addr_reg_t; +typedef uint32_t hri_sercomi2cm_baud_reg_t; +typedef uint32_t hri_sercomi2cm_ctrla_reg_t; +typedef uint32_t hri_sercomi2cm_ctrlb_reg_t; +typedef uint32_t hri_sercomi2cm_syncbusy_reg_t; +typedef uint32_t hri_sercomi2cs_addr_reg_t; +typedef uint32_t hri_sercomi2cs_ctrla_reg_t; +typedef uint32_t hri_sercomi2cs_ctrlb_reg_t; +typedef uint32_t hri_sercomi2cs_syncbusy_reg_t; +typedef uint32_t hri_sercomspi_addr_reg_t; +typedef uint32_t hri_sercomspi_ctrla_reg_t; +typedef uint32_t hri_sercomspi_ctrlb_reg_t; +typedef uint32_t hri_sercomspi_data_reg_t; +typedef uint32_t hri_sercomspi_syncbusy_reg_t; +typedef uint32_t hri_sercomusart_ctrla_reg_t; +typedef uint32_t hri_sercomusart_ctrlb_reg_t; +typedef uint32_t hri_sercomusart_syncbusy_reg_t; +typedef uint8_t hri_sercomi2cm_data_reg_t; +typedef uint8_t hri_sercomi2cm_dbgctrl_reg_t; +typedef uint8_t hri_sercomi2cm_intenset_reg_t; +typedef uint8_t hri_sercomi2cm_intflag_reg_t; +typedef uint8_t hri_sercomi2cs_data_reg_t; +typedef uint8_t hri_sercomi2cs_intenset_reg_t; +typedef uint8_t hri_sercomi2cs_intflag_reg_t; +typedef uint8_t hri_sercomspi_baud_reg_t; +typedef uint8_t hri_sercomspi_dbgctrl_reg_t; +typedef uint8_t hri_sercomspi_intenset_reg_t; +typedef uint8_t hri_sercomspi_intflag_reg_t; +typedef uint8_t hri_sercomusart_dbgctrl_reg_t; +typedef uint8_t hri_sercomusart_intenset_reg_t; +typedef uint8_t hri_sercomusart_intflag_reg_t; +typedef uint8_t hri_sercomusart_rxpl_reg_t; + +static inline void hri_sercomi2cm_wait_for_sync(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomi2cm_is_syncing(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg; +} + +static inline void hri_sercomi2cs_wait_for_sync(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomi2cs_is_syncing(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg; +} + +static inline void hri_sercomspi_wait_for_sync(const void *const hw, hri_sercomspi_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->SPI.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomspi_is_syncing(const void *const hw, hri_sercomspi_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg; +} + +static inline void hri_sercomusart_wait_for_sync(const void *const hw, hri_sercomusart_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->USART.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomusart_is_syncing(const void *const hw, hri_sercomusart_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->USART.SYNCBUSY.reg & reg; +} + +static inline bool hri_sercomi2cm_get_INTFLAG_MB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB; +} + +static inline bool hri_sercomi2cm_get_INTFLAG_SB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB; +} + +static inline bool hri_sercomi2cm_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR; +} + +static inline bool hri_sercomi2cm_get_interrupt_MB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos; +} + +static inline void hri_sercomi2cm_clear_interrupt_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB; +} + +static inline bool hri_sercomi2cm_get_interrupt_SB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos; +} + +static inline void hri_sercomi2cm_clear_interrupt_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB; +} + +static inline bool hri_sercomi2cm_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cm_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR; +} + +static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_get_INTFLAG_reg(const void *const hw, + hri_sercomi2cm_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.INTFLAG.reg; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cm_intflag_reg_t mask) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = mask; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_PREC_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_AMATCH_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_DRDY_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR; +} + +static inline bool hri_sercomi2cs_get_interrupt_PREC_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; +} + +static inline bool hri_sercomi2cs_get_interrupt_AMATCH_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; +} + +static inline bool hri_sercomi2cs_get_interrupt_DRDY_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY; +} + +static inline bool hri_sercomi2cs_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR; +} + +static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_get_INTFLAG_reg(const void *const hw, + hri_sercomi2cs_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CS.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.INTFLAG.reg; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cs_intflag_reg_t mask) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = mask; +} + +static inline bool hri_sercomspi_get_INTFLAG_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE; +} + +static inline bool hri_sercomspi_get_INTFLAG_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC; +} + +static inline bool hri_sercomspi_get_INTFLAG_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC; +} + +static inline bool hri_sercomspi_get_INTFLAG_SSL_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL; +} + +static inline bool hri_sercomspi_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR; +} + +static inline bool hri_sercomspi_get_interrupt_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE; +} + +static inline bool hri_sercomspi_get_interrupt_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC; +} + +static inline bool hri_sercomspi_get_interrupt_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC; +} + +static inline bool hri_sercomspi_get_interrupt_SSL_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL; +} + +static inline bool hri_sercomspi_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR; +} + +static inline hri_sercomspi_intflag_reg_t hri_sercomspi_get_INTFLAG_reg(const void *const hw, + hri_sercomspi_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomspi_intflag_reg_t hri_sercomspi_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.INTFLAG.reg; +} + +static inline void hri_sercomspi_clear_INTFLAG_reg(const void *const hw, hri_sercomspi_intflag_reg_t mask) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = mask; +} + +static inline bool hri_sercomusart_get_INTFLAG_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE; +} + +static inline bool hri_sercomusart_get_INTFLAG_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC; +} + +static inline bool hri_sercomusart_get_INTFLAG_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC; +} + +static inline bool hri_sercomusart_get_INTFLAG_RXS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS; +} + +static inline bool hri_sercomusart_get_INTFLAG_CTSIC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC; +} + +static inline bool hri_sercomusart_get_INTFLAG_RXBRK_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK; +} + +static inline bool hri_sercomusart_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR; +} + +static inline bool hri_sercomusart_get_interrupt_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE; +} + +static inline bool hri_sercomusart_get_interrupt_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC; +} + +static inline bool hri_sercomusart_get_interrupt_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC; +} + +static inline bool hri_sercomusart_get_interrupt_RXS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS; +} + +static inline bool hri_sercomusart_get_interrupt_CTSIC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC; +} + +static inline bool hri_sercomusart_get_interrupt_RXBRK_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK; +} + +static inline bool hri_sercomusart_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR; +} + +static inline hri_sercomusart_intflag_reg_t hri_sercomusart_get_INTFLAG_reg(const void *const hw, + hri_sercomusart_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomusart_intflag_reg_t hri_sercomusart_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.INTFLAG.reg; +} + +static inline void hri_sercomusart_clear_INTFLAG_reg(const void *const hw, hri_sercomusart_intflag_reg_t mask) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = mask; +} + +static inline void hri_sercomi2cm_set_INTEN_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB; +} + +static inline bool hri_sercomi2cm_get_INTEN_MB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_MB) >> SERCOM_I2CM_INTENSET_MB_Pos; +} + +static inline void hri_sercomi2cm_write_INTEN_MB_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB; + } else { + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB; + } +} + +static inline void hri_sercomi2cm_clear_INTEN_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB; +} + +static inline void hri_sercomi2cm_set_INTEN_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB; +} + +static inline bool hri_sercomi2cm_get_INTEN_SB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_SB) >> SERCOM_I2CM_INTENSET_SB_Pos; +} + +static inline void hri_sercomi2cm_write_INTEN_SB_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB; + } else { + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB; + } +} + +static inline void hri_sercomi2cm_clear_INTEN_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB; +} + +static inline void hri_sercomi2cm_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR; +} + +static inline bool hri_sercomi2cm_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_ERROR) >> SERCOM_I2CM_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomi2cm_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR; + } else { + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR; + } +} + +static inline void hri_sercomi2cm_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR; +} + +static inline void hri_sercomi2cm_set_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = mask; +} + +static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_get_INTEN_reg(const void *const hw, + hri_sercomi2cm_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.INTENSET.reg; +} + +static inline void hri_sercomi2cm_write_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t data) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = data; + ((Sercom *)hw)->I2CM.INTENCLR.reg = ~data; +} + +static inline void hri_sercomi2cm_clear_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = mask; +} + +static inline void hri_sercomi2cs_set_INTEN_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC; +} + +static inline bool hri_sercomi2cs_get_INTEN_PREC_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_PREC) >> SERCOM_I2CS_INTENSET_PREC_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_PREC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC; +} + +static inline void hri_sercomi2cs_set_INTEN_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH; +} + +static inline bool hri_sercomi2cs_get_INTEN_AMATCH_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_AMATCH) >> SERCOM_I2CS_INTENSET_AMATCH_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_AMATCH_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH; +} + +static inline void hri_sercomi2cs_set_INTEN_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY; +} + +static inline bool hri_sercomi2cs_get_INTEN_DRDY_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_DRDY) >> SERCOM_I2CS_INTENSET_DRDY_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_DRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY; +} + +static inline void hri_sercomi2cs_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR; +} + +static inline bool hri_sercomi2cs_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_ERROR) >> SERCOM_I2CS_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR; +} + +static inline void hri_sercomi2cs_set_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = mask; +} + +static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_get_INTEN_reg(const void *const hw, + hri_sercomi2cs_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CS.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.INTENSET.reg; +} + +static inline void hri_sercomi2cs_write_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t data) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = data; + ((Sercom *)hw)->I2CS.INTENCLR.reg = ~data; +} + +static inline void hri_sercomi2cs_clear_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = mask; +} + +static inline void hri_sercomspi_set_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE; +} + +static inline bool hri_sercomspi_get_INTEN_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_DRE) >> SERCOM_SPI_INTENSET_DRE_Pos; +} + +static inline void hri_sercomspi_write_INTEN_DRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE; + } +} + +static inline void hri_sercomspi_clear_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE; +} + +static inline void hri_sercomspi_set_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC; +} + +static inline bool hri_sercomspi_get_INTEN_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_TXC) >> SERCOM_SPI_INTENSET_TXC_Pos; +} + +static inline void hri_sercomspi_write_INTEN_TXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC; + } +} + +static inline void hri_sercomspi_clear_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC; +} + +static inline void hri_sercomspi_set_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC; +} + +static inline bool hri_sercomspi_get_INTEN_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_RXC) >> SERCOM_SPI_INTENSET_RXC_Pos; +} + +static inline void hri_sercomspi_write_INTEN_RXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC; + } +} + +static inline void hri_sercomspi_clear_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC; +} + +static inline void hri_sercomspi_set_INTEN_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL; +} + +static inline bool hri_sercomspi_get_INTEN_SSL_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_SSL) >> SERCOM_SPI_INTENSET_SSL_Pos; +} + +static inline void hri_sercomspi_write_INTEN_SSL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL; + } +} + +static inline void hri_sercomspi_clear_INTEN_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL; +} + +static inline void hri_sercomspi_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR; +} + +static inline bool hri_sercomspi_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_ERROR) >> SERCOM_SPI_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomspi_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR; + } +} + +static inline void hri_sercomspi_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR; +} + +static inline void hri_sercomspi_set_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = mask; +} + +static inline hri_sercomspi_intenset_reg_t hri_sercomspi_get_INTEN_reg(const void *const hw, + hri_sercomspi_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomspi_intenset_reg_t hri_sercomspi_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.INTENSET.reg; +} + +static inline void hri_sercomspi_write_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t data) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = data; + ((Sercom *)hw)->SPI.INTENCLR.reg = ~data; +} + +static inline void hri_sercomspi_clear_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = mask; +} + +static inline void hri_sercomusart_set_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE; +} + +static inline bool hri_sercomusart_get_INTEN_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_DRE) >> SERCOM_USART_INTENSET_DRE_Pos; +} + +static inline void hri_sercomusart_write_INTEN_DRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE; + } +} + +static inline void hri_sercomusart_clear_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE; +} + +static inline void hri_sercomusart_set_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC; +} + +static inline bool hri_sercomusart_get_INTEN_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_TXC) >> SERCOM_USART_INTENSET_TXC_Pos; +} + +static inline void hri_sercomusart_write_INTEN_TXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC; + } +} + +static inline void hri_sercomusart_clear_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC; +} + +static inline void hri_sercomusart_set_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC; +} + +static inline bool hri_sercomusart_get_INTEN_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXC) >> SERCOM_USART_INTENSET_RXC_Pos; +} + +static inline void hri_sercomusart_write_INTEN_RXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC; + } +} + +static inline void hri_sercomusart_clear_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC; +} + +static inline void hri_sercomusart_set_INTEN_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS; +} + +static inline bool hri_sercomusart_get_INTEN_RXS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXS) >> SERCOM_USART_INTENSET_RXS_Pos; +} + +static inline void hri_sercomusart_write_INTEN_RXS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS; + } +} + +static inline void hri_sercomusart_clear_INTEN_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS; +} + +static inline void hri_sercomusart_set_INTEN_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC; +} + +static inline bool hri_sercomusart_get_INTEN_CTSIC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_CTSIC) >> SERCOM_USART_INTENSET_CTSIC_Pos; +} + +static inline void hri_sercomusart_write_INTEN_CTSIC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC; + } +} + +static inline void hri_sercomusart_clear_INTEN_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC; +} + +static inline void hri_sercomusart_set_INTEN_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK; +} + +static inline bool hri_sercomusart_get_INTEN_RXBRK_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXBRK) >> SERCOM_USART_INTENSET_RXBRK_Pos; +} + +static inline void hri_sercomusart_write_INTEN_RXBRK_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK; + } +} + +static inline void hri_sercomusart_clear_INTEN_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK; +} + +static inline void hri_sercomusart_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR; +} + +static inline bool hri_sercomusart_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_ERROR) >> SERCOM_USART_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomusart_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR; + } +} + +static inline void hri_sercomusart_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR; +} + +static inline void hri_sercomusart_set_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask) +{ + ((Sercom *)hw)->USART.INTENSET.reg = mask; +} + +static inline hri_sercomusart_intenset_reg_t hri_sercomusart_get_INTEN_reg(const void *const hw, + hri_sercomusart_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomusart_intenset_reg_t hri_sercomusart_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.INTENSET.reg; +} + +static inline void hri_sercomusart_write_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t data) +{ + ((Sercom *)hw)->USART.INTENSET.reg = data; + ((Sercom *)hw)->USART.INTENCLR.reg = ~data; +} + +static inline void hri_sercomusart_clear_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = mask; +} + +static inline bool hri_sercomi2cm_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SWRST) >> SERCOM_I2CM_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomi2cm_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_ENABLE) >> SERCOM_I2CM_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_sercomi2cm_get_SYNCBUSY_SYSOP_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SYSOP) >> SERCOM_I2CM_SYNCBUSY_SYSOP_Pos; +} + +static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_get_SYNCBUSY_reg(const void *const hw, + hri_sercomi2cm_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.SYNCBUSY.reg; +} + +static inline bool hri_sercomi2cs_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_SWRST) >> SERCOM_I2CS_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomi2cs_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_ENABLE) >> SERCOM_I2CS_SYNCBUSY_ENABLE_Pos; +} + +static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_get_SYNCBUSY_reg(const void *const hw, + hri_sercomi2cs_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.SYNCBUSY.reg; +} + +static inline bool hri_sercomspi_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_SWRST) >> SERCOM_SPI_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomspi_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_ENABLE) >> SERCOM_SPI_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_sercomspi_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_CTRLB) >> SERCOM_SPI_SYNCBUSY_CTRLB_Pos; +} + +static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_get_SYNCBUSY_reg(const void *const hw, + hri_sercomspi_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.SYNCBUSY.reg; +} + +static inline bool hri_sercomusart_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_SWRST) >> SERCOM_USART_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomusart_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_ENABLE) >> SERCOM_USART_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_sercomusart_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_CTRLB) >> SERCOM_USART_SYNCBUSY_CTRLB_Pos; +} + +static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_get_SYNCBUSY_reg(const void *const hw, + hri_sercomusart_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.SYNCBUSY.reg; +} + +static inline void hri_sercomi2cm_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SWRST; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SWRST) >> SERCOM_I2CM_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_ENABLE) >> SERCOM_I2CM_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_ENABLE; + tmp |= value << SERCOM_I2CM_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_ENABLE; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_RUNSTDBY; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_RUNSTDBY) >> SERCOM_I2CM_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_RUNSTDBY; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_RUNSTDBY; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_PINOUT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_PINOUT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_PINOUT) >> SERCOM_I2CM_CTRLA_PINOUT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_PINOUT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_PINOUT; + tmp |= value << SERCOM_I2CM_CTRLA_PINOUT_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_PINOUT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_PINOUT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_MEXTTOEN) >> SERCOM_I2CM_CTRLA_MEXTTOEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_MEXTTOEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_MEXTTOEN; + tmp |= value << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SEXTTOEN) >> SERCOM_I2CM_CTRLA_SEXTTOEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SEXTTOEN; + tmp |= value << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SCLSM; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_SCLSM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SCLSM) >> SERCOM_I2CM_CTRLA_SCLSM_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SCLSM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SCLSM; + tmp |= value << SERCOM_I2CM_CTRLA_SCLSM_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SCLSM; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SCLSM; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_LOWTOUTEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_LOWTOUTEN) >> SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN; + tmp |= value << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_LOWTOUTEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MODE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_MODE(mask)) >> SERCOM_I2CM_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_MODE_Msk; + tmp |= SERCOM_I2CM_CTRLA_MODE(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MODE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MODE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_MODE_Msk) >> SERCOM_I2CM_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SDAHOLD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SDAHOLD_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SDAHOLD_Msk; + tmp |= SERCOM_I2CM_CTRLA_SDAHOLD(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SDAHOLD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SDAHOLD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SDAHOLD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SPEED(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SPEED_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED(mask)) >> SERCOM_I2CM_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SPEED_Msk; + tmp |= SERCOM_I2CM_CTRLA_SPEED(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SPEED(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SPEED(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SPEED_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_INACTOUT(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_INACTOUT_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT(mask)) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_INACTOUT_Msk; + tmp |= SERCOM_I2CM_CTRLA_INACTOUT(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_INACTOUT(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_INACTOUT(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_INACTOUT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT_Msk) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_reg(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg = data; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + return ((Sercom *)hw)->I2CM.CTRLA.reg; +} + +static inline void hri_sercomi2cs_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SWRST; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SWRST) >> SERCOM_I2CS_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_ENABLE; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_ENABLE) >> SERCOM_I2CS_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_ENABLE; + tmp |= value << SERCOM_I2CS_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_ENABLE; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_ENABLE; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_RUNSTDBY; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_RUNSTDBY) >> SERCOM_I2CS_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_RUNSTDBY; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_RUNSTDBY; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_PINOUT; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_PINOUT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_PINOUT) >> SERCOM_I2CS_CTRLA_PINOUT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_PINOUT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_PINOUT; + tmp |= value << SERCOM_I2CS_CTRLA_PINOUT_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_PINOUT; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_PINOUT; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SEXTTOEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SEXTTOEN) >> SERCOM_I2CS_CTRLA_SEXTTOEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SEXTTOEN; + tmp |= value << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SEXTTOEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SEXTTOEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SCLSM; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_SCLSM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SCLSM) >> SERCOM_I2CS_CTRLA_SCLSM_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SCLSM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SCLSM; + tmp |= value << SERCOM_I2CS_CTRLA_SCLSM_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SCLSM; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SCLSM; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_LOWTOUTEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_LOWTOUTEN) >> SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN; + tmp |= value << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_LOWTOUTEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_MODE(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_MODE(mask)) >> SERCOM_I2CS_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_MODE_Msk; + tmp |= SERCOM_I2CS_CTRLA_MODE(data); + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_MODE(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_MODE(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_MODE_Msk) >> SERCOM_I2CS_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SDAHOLD(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SDAHOLD_bf(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SDAHOLD_Msk; + tmp |= SERCOM_I2CS_CTRLA_SDAHOLD(data); + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SDAHOLD(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SDAHOLD(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SDAHOLD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SPEED(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SPEED_bf(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED(mask)) >> SERCOM_I2CS_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SPEED_Msk; + tmp |= SERCOM_I2CS_CTRLA_SPEED(data); + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SPEED(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SPEED(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SPEED_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED_Msk) >> SERCOM_I2CS_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= mask; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_reg(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg = data; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~mask; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= mask; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_reg(const void *const hw) +{ + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + return ((Sercom *)hw)->I2CS.CTRLA.reg; +} + +static inline void hri_sercomspi_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_SWRST; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_SWRST) >> SERCOM_SPI_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_ENABLE) >> SERCOM_SPI_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_ENABLE; + tmp |= value << SERCOM_SPI_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_ENABLE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_RUNSTDBY; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_RUNSTDBY) >> SERCOM_SPI_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_SPI_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_RUNSTDBY; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_RUNSTDBY; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_IBON; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_IBON_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_IBON) >> SERCOM_SPI_CTRLA_IBON_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_IBON_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_IBON; + tmp |= value << SERCOM_SPI_CTRLA_IBON_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_IBON; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_IBON; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_CPHA_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPHA; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_CPHA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_CPHA) >> SERCOM_SPI_CTRLA_CPHA_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_CPHA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_CPHA; + tmp |= value << SERCOM_SPI_CTRLA_CPHA_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_CPHA_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPHA; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_CPHA_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPHA; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPOL; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_CPOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_CPOL) >> SERCOM_SPI_CTRLA_CPOL_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_CPOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_CPOL; + tmp |= value << SERCOM_SPI_CTRLA_CPOL_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPOL; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPOL; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DORD; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_DORD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DORD) >> SERCOM_SPI_CTRLA_DORD_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_DORD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_DORD; + tmp |= value << SERCOM_SPI_CTRLA_DORD_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DORD; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DORD; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_MODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_MODE(mask)) >> SERCOM_SPI_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_MODE_Msk; + tmp |= SERCOM_SPI_CTRLA_MODE(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_MODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_MODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_MODE_Msk) >> SERCOM_SPI_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DOPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DOPO_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DOPO(mask)) >> SERCOM_SPI_CTRLA_DOPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_DOPO_Msk; + tmp |= SERCOM_SPI_CTRLA_DOPO(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DOPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DOPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DOPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DOPO_Msk) >> SERCOM_SPI_CTRLA_DOPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DIPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DIPO_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DIPO(mask)) >> SERCOM_SPI_CTRLA_DIPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_DIPO_Msk; + tmp |= SERCOM_SPI_CTRLA_DIPO(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DIPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DIPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DIPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DIPO_Msk) >> SERCOM_SPI_CTRLA_DIPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_FORM(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_FORM_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_FORM(mask)) >> SERCOM_SPI_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_FORM_Msk; + tmp |= SERCOM_SPI_CTRLA_FORM(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_FORM(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_FORM(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_FORM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_FORM_Msk) >> SERCOM_SPI_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_reg(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg = data; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_reg(const void *const hw) +{ + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + return ((Sercom *)hw)->SPI.CTRLA.reg; +} + +static inline void hri_sercomusart_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SWRST; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SWRST) >> SERCOM_USART_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_ENABLE) >> SERCOM_USART_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_ENABLE; + tmp |= value << SERCOM_USART_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_ENABLE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RUNSTDBY; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_RUNSTDBY) >> SERCOM_USART_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_USART_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RUNSTDBY; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RUNSTDBY; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_IBON; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_IBON_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_IBON) >> SERCOM_USART_CTRLA_IBON_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_IBON_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_IBON; + tmp |= value << SERCOM_USART_CTRLA_IBON_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_IBON; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_IBON; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_CMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_CMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_CMODE) >> SERCOM_USART_CTRLA_CMODE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_CMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_CMODE; + tmp |= value << SERCOM_USART_CTRLA_CMODE_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_CMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_CMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CPOL; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_CPOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_CPOL) >> SERCOM_USART_CTRLA_CPOL_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_CPOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_CPOL; + tmp |= value << SERCOM_USART_CTRLA_CPOL_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CPOL; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CPOL; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_DORD; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_DORD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_DORD) >> SERCOM_USART_CTRLA_DORD_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_DORD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_DORD; + tmp |= value << SERCOM_USART_CTRLA_DORD_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_DORD; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_DORD; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_MODE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_MODE(mask)) >> SERCOM_USART_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_MODE_Msk; + tmp |= SERCOM_USART_CTRLA_MODE(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_MODE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_MODE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_MODE_Msk) >> SERCOM_USART_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPR(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPR_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPR(mask)) >> SERCOM_USART_CTRLA_SAMPR_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_SAMPR_Msk; + tmp |= SERCOM_USART_CTRLA_SAMPR(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPR(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPR(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPR_Msk) >> SERCOM_USART_CTRLA_SAMPR_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_TXPO_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_TXPO(mask)) >> SERCOM_USART_CTRLA_TXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_TXPO_Msk; + tmp |= SERCOM_USART_CTRLA_TXPO(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_TXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_TXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_TXPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_TXPO_Msk) >> SERCOM_USART_CTRLA_TXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_RXPO_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_RXPO(mask)) >> SERCOM_USART_CTRLA_RXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_RXPO_Msk; + tmp |= SERCOM_USART_CTRLA_RXPO(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_RXPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_RXPO_Msk) >> SERCOM_USART_CTRLA_RXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPA(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPA_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPA(mask)) >> SERCOM_USART_CTRLA_SAMPA_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_SAMPA_Msk; + tmp |= SERCOM_USART_CTRLA_SAMPA(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPA(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPA(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPA_Msk) >> SERCOM_USART_CTRLA_SAMPA_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_FORM(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_FORM_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_FORM(mask)) >> SERCOM_USART_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_FORM_Msk; + tmp |= SERCOM_USART_CTRLA_FORM(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_FORM(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_FORM(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_FORM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_FORM_Msk) >> SERCOM_USART_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_reg(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg = data; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_reg(const void *const hw) +{ + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + return ((Sercom *)hw)->USART.CTRLA.reg; +} + +static inline void hri_sercomi2cm_set_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_SMEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLB_SMEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_SMEN) >> SERCOM_I2CM_CTRLB_SMEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_SMEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_SMEN; + tmp |= value << SERCOM_I2CM_CTRLB_SMEN_Pos; + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_SMEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_SMEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLB_QCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_QCEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLB_QCEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_QCEN) >> SERCOM_I2CM_CTRLB_QCEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_QCEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_QCEN; + tmp |= value << SERCOM_I2CM_CTRLB_QCEN_Pos; + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_QCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_QCEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_QCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_QCEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLB_ACKACT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_ACKACT) >> SERCOM_I2CM_CTRLB_ACKACT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_ACKACT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_ACKACT; + tmp |= value << SERCOM_I2CM_CTRLB_ACKACT_Pos; + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_ACKACT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_CMD_bf(const void *const hw, + hri_sercomi2cm_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_CMD(mask)) >> SERCOM_I2CM_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_CMD_Msk; + tmp |= SERCOM_I2CM_CTRLB_CMD(data); + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_CMD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_CMD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_CMD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_CMD_Msk) >> SERCOM_I2CM_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_reg(const void *const hw, + hri_sercomi2cm_ctrlb_reg_t mask) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg = data; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return ((Sercom *)hw)->I2CM.CTRLB.reg; +} + +static inline void hri_sercomi2cs_set_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_SMEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_SMEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_SMEN) >> SERCOM_I2CS_CTRLB_SMEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_SMEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_SMEN; + tmp |= value << SERCOM_I2CS_CTRLB_SMEN_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_SMEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_SMEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_GCMD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_GCMD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_GCMD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_GCMD) >> SERCOM_I2CS_CTRLB_GCMD_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_GCMD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_GCMD; + tmp |= value << SERCOM_I2CS_CTRLB_GCMD_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_GCMD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_GCMD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_GCMD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_GCMD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_AACKEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AACKEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_AACKEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_AACKEN) >> SERCOM_I2CS_CTRLB_AACKEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_AACKEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_AACKEN; + tmp |= value << SERCOM_I2CS_CTRLB_AACKEN_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_AACKEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AACKEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_AACKEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AACKEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_ACKACT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_ACKACT) >> SERCOM_I2CS_CTRLB_ACKACT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_ACKACT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_ACKACT; + tmp |= value << SERCOM_I2CS_CTRLB_ACKACT_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_ACKACT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AMODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_AMODE_bf(const void *const hw, + hri_sercomi2cs_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE(mask)) >> SERCOM_I2CS_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_AMODE_Msk; + tmp |= SERCOM_I2CS_CTRLB_AMODE(data); + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AMODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AMODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_AMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE_Msk) >> SERCOM_I2CS_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_CMD_bf(const void *const hw, + hri_sercomi2cs_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_CMD(mask)) >> SERCOM_I2CS_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_CMD_Msk; + tmp |= SERCOM_I2CS_CTRLB_CMD(data); + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_CMD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_CMD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_CMD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_CMD_Msk) >> SERCOM_I2CS_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_reg(const void *const hw, + hri_sercomi2cs_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.CTRLB.reg; +} + +static inline void hri_sercomspi_set_CTRLB_PLOADEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_PLOADEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_PLOADEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_PLOADEN) >> SERCOM_SPI_CTRLB_PLOADEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_PLOADEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_PLOADEN; + tmp |= value << SERCOM_SPI_CTRLB_PLOADEN_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_PLOADEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_PLOADEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_PLOADEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_PLOADEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_SSDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_SSDE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_SSDE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_SSDE) >> SERCOM_SPI_CTRLB_SSDE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_SSDE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_SSDE; + tmp |= value << SERCOM_SPI_CTRLB_SSDE_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_SSDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_SSDE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_SSDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_SSDE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_MSSEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_MSSEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_MSSEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_MSSEN) >> SERCOM_SPI_CTRLB_MSSEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_MSSEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_MSSEN; + tmp |= value << SERCOM_SPI_CTRLB_MSSEN_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_MSSEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_MSSEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_MSSEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_MSSEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_RXEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_RXEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_RXEN) >> SERCOM_SPI_CTRLB_RXEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_RXEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_RXEN; + tmp |= value << SERCOM_SPI_CTRLB_RXEN_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_RXEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_RXEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_CHSIZE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_CHSIZE_bf(const void *const hw, + hri_sercomspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE(mask)) >> SERCOM_SPI_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_CHSIZE_Msk; + tmp |= SERCOM_SPI_CTRLB_CHSIZE(data); + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_CHSIZE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_CHSIZE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_CHSIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE_Msk) >> SERCOM_SPI_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_AMODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_AMODE_bf(const void *const hw, + hri_sercomspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_AMODE(mask)) >> SERCOM_SPI_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_AMODE_Msk; + tmp |= SERCOM_SPI_CTRLB_AMODE(data); + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_AMODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_AMODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_AMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_AMODE_Msk) >> SERCOM_SPI_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_reg(const void *const hw, + hri_sercomspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg = data; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_reg(const void *const hw) +{ + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + return ((Sercom *)hw)->SPI.CTRLB.reg; +} + +static inline void hri_sercomusart_set_CTRLB_SBMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SBMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_SBMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_SBMODE) >> SERCOM_USART_CTRLB_SBMODE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_SBMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_SBMODE; + tmp |= value << SERCOM_USART_CTRLB_SBMODE_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_SBMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SBMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_SBMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SBMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_COLDEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_COLDEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_COLDEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_COLDEN) >> SERCOM_USART_CTRLB_COLDEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_COLDEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_COLDEN; + tmp |= value << SERCOM_USART_CTRLB_COLDEN_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_COLDEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_COLDEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_COLDEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_COLDEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_SFDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SFDE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_SFDE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_SFDE) >> SERCOM_USART_CTRLB_SFDE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_SFDE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_SFDE; + tmp |= value << SERCOM_USART_CTRLB_SFDE_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_SFDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SFDE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_SFDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SFDE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_ENC_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_ENC; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_ENC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_ENC) >> SERCOM_USART_CTRLB_ENC_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_ENC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_ENC; + tmp |= value << SERCOM_USART_CTRLB_ENC_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_ENC_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_ENC; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_ENC_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_ENC; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_PMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_PMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_PMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_PMODE) >> SERCOM_USART_CTRLB_PMODE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_PMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_PMODE; + tmp |= value << SERCOM_USART_CTRLB_PMODE_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_PMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_PMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_PMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_PMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_TXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_TXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_TXEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_TXEN) >> SERCOM_USART_CTRLB_TXEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_TXEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_TXEN; + tmp |= value << SERCOM_USART_CTRLB_TXEN_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_TXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_TXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_TXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_TXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_RXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_RXEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_RXEN) >> SERCOM_USART_CTRLB_RXEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_RXEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_RXEN; + tmp |= value << SERCOM_USART_CTRLB_RXEN_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_RXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_RXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_CHSIZE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_CHSIZE_bf(const void *const hw, + hri_sercomusart_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE(mask)) >> SERCOM_USART_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_CHSIZE_Msk; + tmp |= SERCOM_USART_CTRLB_CHSIZE(data); + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_CHSIZE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_CHSIZE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_CHSIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE_Msk) >> SERCOM_USART_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_reg(const void *const hw, + hri_sercomusart_ctrlb_reg_t mask) +{ + uint32_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg = data; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_reg(const void *const hw) +{ + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + return ((Sercom *)hw)->USART.CTRLB.reg; +} + +static inline void hri_sercomi2cm_set_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUD_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUD(mask)) >> SERCOM_I2CM_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_BAUD_Msk; + tmp |= SERCOM_I2CM_BAUD_BAUD(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUD_Msk) >> SERCOM_I2CM_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUDLOW_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW(mask)) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_BAUDLOW_Msk; + tmp |= SERCOM_I2CM_BAUD_BAUDLOW(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUDLOW_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW_Msk) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUD_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD(mask)) >> SERCOM_I2CM_BAUD_HSBAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_HSBAUD_Msk; + tmp |= SERCOM_I2CM_BAUD_HSBAUD(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD_Msk) >> SERCOM_I2CM_BAUD_HSBAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUDLOW_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW(mask)) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_HSBAUDLOW_Msk; + tmp |= SERCOM_I2CM_BAUD_HSBAUDLOW(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUDLOW_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW_Msk) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_reg(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.BAUD.reg; +} + +static inline void hri_sercomspi_set_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg |= SERCOM_SPI_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_BAUD_bf(const void *const hw, + hri_sercomspi_baud_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp = (tmp & SERCOM_SPI_BAUD_BAUD(mask)) >> SERCOM_SPI_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t data) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp &= ~SERCOM_SPI_BAUD_BAUD_Msk; + tmp |= SERCOM_SPI_BAUD_BAUD(data); + ((Sercom *)hw)->SPI.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg &= ~SERCOM_SPI_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg ^= SERCOM_SPI_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_BAUD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp = (tmp & SERCOM_SPI_BAUD_BAUD_Msk) >> SERCOM_SPI_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.BAUD.reg; +} + +static inline void hri_sercomusart_set_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_write_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRAC_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRACFP_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_FP_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP(mask)) >> SERCOM_USART_BAUD_FRAC_FP_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_FP_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP(mask)) >> SERCOM_USART_BAUD_FRACFP_FP_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_FRAC_FP_Msk; + tmp |= SERCOM_USART_BAUD_FRAC_FP(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_write_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_FRACFP_FP_Msk; + tmp |= SERCOM_USART_BAUD_FRACFP_FP(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRAC_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRACFP_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRAC_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRACFP_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_FP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP_Msk) >> SERCOM_USART_BAUD_FRAC_FP_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_FP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP_Msk) >> SERCOM_USART_BAUD_FRACFP_FP_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_USARTFP_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_write_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_USARTFP_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_reg(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.BAUD.reg; +} + +static inline void hri_sercomusart_set_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg |= SERCOM_USART_RXPL_RXPL(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_RXPL_bf(const void *const hw, + hri_sercomusart_rxpl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp = (tmp & SERCOM_USART_RXPL_RXPL(mask)) >> SERCOM_USART_RXPL_RXPL_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t data) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp &= ~SERCOM_USART_RXPL_RXPL_Msk; + tmp |= SERCOM_USART_RXPL_RXPL(data); + ((Sercom *)hw)->USART.RXPL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg &= ~SERCOM_USART_RXPL_RXPL(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg ^= SERCOM_USART_RXPL_RXPL(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_RXPL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp = (tmp & SERCOM_USART_RXPL_RXPL_Msk) >> SERCOM_USART_RXPL_RXPL_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_reg(const void *const hw, + hri_sercomusart_rxpl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.RXPL.reg; +} + +static inline void hri_sercomi2cm_set_ADDR_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LENEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_ADDR_LENEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_LENEN) >> SERCOM_I2CM_ADDR_LENEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_LENEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_LENEN; + tmp |= value << SERCOM_I2CM_ADDR_LENEN_Pos; + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LENEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LENEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_ADDR_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_HS; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_ADDR_HS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_HS) >> SERCOM_I2CM_ADDR_HS_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_HS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_HS; + tmp |= value << SERCOM_I2CM_ADDR_HS_Pos; + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_HS; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_HS; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_TENBITEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_ADDR_TENBITEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_TENBITEN) >> SERCOM_I2CM_ADDR_TENBITEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_TENBITEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_TENBITEN; + tmp |= value << SERCOM_I2CM_ADDR_TENBITEN_Pos; + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_TENBITEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_TENBITEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_ADDR(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_ADDR_bf(const void *const hw, + hri_sercomi2cm_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_ADDR(mask)) >> SERCOM_I2CM_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_ADDR_Msk; + tmp |= SERCOM_I2CM_ADDR_ADDR(data); + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_ADDR(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_ADDR(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_ADDR_Msk) >> SERCOM_I2CM_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LEN(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_LEN_bf(const void *const hw, + hri_sercomi2cm_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_LEN(mask)) >> SERCOM_I2CM_ADDR_LEN_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_LEN_Msk; + tmp |= SERCOM_I2CM_ADDR_LEN(data); + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LEN(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LEN(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_LEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_LEN_Msk) >> SERCOM_I2CM_ADDR_LEN_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_reg(const void *const hw, + hri_sercomi2cm_addr_reg_t mask) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg = data; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return ((Sercom *)hw)->I2CM.ADDR.reg; +} + +static inline void hri_sercomi2cs_set_ADDR_GENCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_GENCEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_ADDR_GENCEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_GENCEN) >> SERCOM_I2CS_ADDR_GENCEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_GENCEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_GENCEN; + tmp |= value << SERCOM_I2CS_ADDR_GENCEN_Pos; + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_GENCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_GENCEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_GENCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_GENCEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_TENBITEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_ADDR_TENBITEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_TENBITEN) >> SERCOM_I2CS_ADDR_TENBITEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_TENBITEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_TENBITEN; + tmp |= value << SERCOM_I2CS_ADDR_TENBITEN_Pos; + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_TENBITEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_TENBITEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDR_bf(const void *const hw, + hri_sercomi2cs_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDR(mask)) >> SERCOM_I2CS_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_ADDR_Msk; + tmp |= SERCOM_I2CS_ADDR_ADDR(data); + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDR_Msk) >> SERCOM_I2CS_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDRMASK_bf(const void *const hw, + hri_sercomi2cs_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK(mask)) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_ADDRMASK_Msk; + tmp |= SERCOM_I2CS_ADDR_ADDRMASK(data); + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDRMASK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK_Msk) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_reg(const void *const hw, + hri_sercomi2cs_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.ADDR.reg; +} + +static inline void hri_sercomspi_set_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDR_bf(const void *const hw, + hri_sercomspi_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDR(mask)) >> SERCOM_SPI_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp &= ~SERCOM_SPI_ADDR_ADDR_Msk; + tmp |= SERCOM_SPI_ADDR_ADDR(data); + ((Sercom *)hw)->SPI.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDR_Msk) >> SERCOM_SPI_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDRMASK_bf(const void *const hw, + hri_sercomspi_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK(mask)) >> SERCOM_SPI_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp &= ~SERCOM_SPI_ADDR_ADDRMASK_Msk; + tmp |= SERCOM_SPI_ADDR_ADDRMASK(data); + ((Sercom *)hw)->SPI.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDRMASK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK_Msk) >> SERCOM_SPI_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.ADDR.reg; +} + +static inline void hri_sercomi2cm_set_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg |= SERCOM_I2CM_DATA_DATA(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_get_DATA_DATA_bf(const void *const hw, + hri_sercomi2cm_data_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.DATA.reg; + tmp = (tmp & SERCOM_I2CM_DATA_DATA(mask)) >> SERCOM_I2CM_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t data) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.DATA.reg; + tmp &= ~SERCOM_I2CM_DATA_DATA_Msk; + tmp |= SERCOM_I2CM_DATA_DATA(data); + ((Sercom *)hw)->I2CM.DATA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg &= ~SERCOM_I2CM_DATA_DATA(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg ^= SERCOM_I2CM_DATA_DATA(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_DATA_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.DATA.reg; + tmp = (tmp & SERCOM_I2CM_DATA_DATA_Msk) >> SERCOM_I2CM_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg |= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_get_DATA_reg(const void *const hw, + hri_sercomi2cm_data_reg_t mask) +{ + uint8_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg = data; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg &= ~mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg ^= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return ((Sercom *)hw)->I2CM.DATA.reg; +} + +static inline void hri_sercomi2cs_set_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg |= SERCOM_I2CS_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_get_DATA_DATA_bf(const void *const hw, + hri_sercomi2cs_data_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CS.DATA.reg; + tmp = (tmp & SERCOM_I2CS_DATA_DATA(mask)) >> SERCOM_I2CS_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t data) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.DATA.reg; + tmp &= ~SERCOM_I2CS_DATA_DATA_Msk; + tmp |= SERCOM_I2CS_DATA_DATA(data); + ((Sercom *)hw)->I2CS.DATA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg &= ~SERCOM_I2CS_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg ^= SERCOM_I2CS_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_DATA_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CS.DATA.reg; + tmp = (tmp & SERCOM_I2CS_DATA_DATA_Msk) >> SERCOM_I2CS_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_get_DATA_reg(const void *const hw, + hri_sercomi2cs_data_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CS.DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.DATA.reg; +} + +static inline void hri_sercomspi_set_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg |= SERCOM_SPI_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_data_reg_t hri_sercomspi_get_DATA_DATA_bf(const void *const hw, + hri_sercomspi_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.DATA.reg; + tmp = (tmp & SERCOM_SPI_DATA_DATA(mask)) >> SERCOM_SPI_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.DATA.reg; + tmp &= ~SERCOM_SPI_DATA_DATA_Msk; + tmp |= SERCOM_SPI_DATA_DATA(data); + ((Sercom *)hw)->SPI.DATA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg &= ~SERCOM_SPI_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg ^= SERCOM_SPI_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_data_reg_t hri_sercomspi_read_DATA_DATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.DATA.reg; + tmp = (tmp & SERCOM_SPI_DATA_DATA_Msk) >> SERCOM_SPI_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_data_reg_t hri_sercomspi_get_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_data_reg_t hri_sercomspi_read_DATA_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.DATA.reg; +} + +static inline void hri_sercomusart_set_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg |= SERCOM_USART_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_data_reg_t hri_sercomusart_get_DATA_DATA_bf(const void *const hw, + hri_sercomusart_data_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.DATA.reg; + tmp = (tmp & SERCOM_USART_DATA_DATA(mask)) >> SERCOM_USART_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.DATA.reg; + tmp &= ~SERCOM_USART_DATA_DATA_Msk; + tmp |= SERCOM_USART_DATA_DATA(data); + ((Sercom *)hw)->USART.DATA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg &= ~SERCOM_USART_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg ^= SERCOM_USART_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_DATA_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.DATA.reg; + tmp = (tmp & SERCOM_USART_DATA_DATA_Msk) >> SERCOM_USART_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_data_reg_t hri_sercomusart_get_DATA_reg(const void *const hw, + hri_sercomusart_data_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.DATA.reg; +} + +static inline void hri_sercomi2cm_set_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg |= SERCOM_I2CM_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; + tmp = (tmp & SERCOM_I2CM_DBGCTRL_DBGSTOP) >> SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; + tmp &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP; + tmp |= value << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos; + ((Sercom *)hw)->I2CM.DBGCTRL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg ^= SERCOM_I2CM_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_get_DBGCTRL_reg(const void *const hw, + hri_sercomi2cm_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_read_DBGCTRL_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.DBGCTRL.reg; +} + +static inline void hri_sercomspi_set_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg |= SERCOM_SPI_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; + tmp = (tmp & SERCOM_SPI_DBGCTRL_DBGSTOP) >> SERCOM_SPI_DBGCTRL_DBGSTOP_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; + tmp &= ~SERCOM_SPI_DBGCTRL_DBGSTOP; + tmp |= value << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos; + ((Sercom *)hw)->SPI.DBGCTRL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg &= ~SERCOM_SPI_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg ^= SERCOM_SPI_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_get_DBGCTRL_reg(const void *const hw, + hri_sercomspi_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_read_DBGCTRL_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.DBGCTRL.reg; +} + +static inline void hri_sercomusart_set_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg |= SERCOM_USART_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; + tmp = (tmp & SERCOM_USART_DBGCTRL_DBGSTOP) >> SERCOM_USART_DBGCTRL_DBGSTOP_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; + tmp &= ~SERCOM_USART_DBGCTRL_DBGSTOP; + tmp |= value << SERCOM_USART_DBGCTRL_DBGSTOP_Pos; + ((Sercom *)hw)->USART.DBGCTRL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg &= ~SERCOM_USART_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg ^= SERCOM_USART_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_get_DBGCTRL_reg(const void *const hw, + hri_sercomusart_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_read_DBGCTRL_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.DBGCTRL.reg; +} + +static inline bool hri_sercomi2cs_get_STATUS_BUSERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_BUSERR) >> SERCOM_I2CS_STATUS_BUSERR_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_COLL_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_COLL) >> SERCOM_I2CS_STATUS_COLL_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_COLL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_COLL; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_RXNACK_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_RXNACK) >> SERCOM_I2CS_STATUS_RXNACK_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_DIR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_DIR) >> SERCOM_I2CS_STATUS_DIR_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_DIR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_DIR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_SR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SR) >> SERCOM_I2CS_STATUS_SR_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_SR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_LOWTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_LOWTOUT) >> SERCOM_I2CS_STATUS_LOWTOUT_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_CLKHOLD_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_CLKHOLD) >> SERCOM_I2CS_STATUS_CLKHOLD_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_SEXTTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SEXTTOUT) >> SERCOM_I2CS_STATUS_SEXTTOUT_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_HS_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_HS) >> SERCOM_I2CS_STATUS_HS_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_HS; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_get_STATUS_reg(const void *const hw, + hri_sercomi2cs_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->I2CS.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_clear_STATUS_reg(const void *const hw, hri_sercomi2cs_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_read_STATUS_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.STATUS.reg; +} + +static inline bool hri_sercomspi_get_STATUS_BUFOVF_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.STATUS.reg & SERCOM_SPI_STATUS_BUFOVF) >> SERCOM_SPI_STATUS_BUFOVF_Pos; +} + +static inline void hri_sercomspi_clear_STATUS_BUFOVF_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.STATUS.reg = SERCOM_SPI_STATUS_BUFOVF; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_status_reg_t hri_sercomspi_get_STATUS_reg(const void *const hw, + hri_sercomspi_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->SPI.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_clear_STATUS_reg(const void *const hw, hri_sercomspi_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.STATUS.reg = mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_status_reg_t hri_sercomspi_read_STATUS_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.STATUS.reg; +} + +static inline bool hri_sercomusart_get_STATUS_PERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_PERR) >> SERCOM_USART_STATUS_PERR_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_PERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_PERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_FERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_FERR) >> SERCOM_USART_STATUS_FERR_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_FERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_FERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_BUFOVF_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_BUFOVF) >> SERCOM_USART_STATUS_BUFOVF_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_BUFOVF_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_BUFOVF; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_CTS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_CTS) >> SERCOM_USART_STATUS_CTS_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_CTS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_CTS; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_ISF_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_ISF) >> SERCOM_USART_STATUS_ISF_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_ISF_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_ISF; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_COLL_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_COLL) >> SERCOM_USART_STATUS_COLL_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_COLL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_COLL; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_status_reg_t hri_sercomusart_get_STATUS_reg(const void *const hw, + hri_sercomusart_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_clear_STATUS_reg(const void *const hw, hri_sercomusart_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_status_reg_t hri_sercomusart_read_STATUS_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.STATUS.reg; +} + +static inline void hri_sercomi2cm_set_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_BUSERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSERR) >> SERCOM_I2CM_STATUS_BUSERR_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_BUSERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_BUSERR; + tmp |= value << SERCOM_I2CM_STATUS_BUSERR_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_ARBLOST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_ARBLOST; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_ARBLOST_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) >> SERCOM_I2CM_STATUS_ARBLOST_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_ARBLOST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_ARBLOST; + tmp |= value << SERCOM_I2CM_STATUS_ARBLOST_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_ARBLOST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_ARBLOST; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_ARBLOST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_ARBLOST; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_RXNACK_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) >> SERCOM_I2CM_STATUS_RXNACK_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_RXNACK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_RXNACK; + tmp |= value << SERCOM_I2CM_STATUS_RXNACK_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_LOWTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LOWTOUT) >> SERCOM_I2CM_STATUS_LOWTOUT_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_LOWTOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_LOWTOUT; + tmp |= value << SERCOM_I2CM_STATUS_LOWTOUT_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_CLKHOLD_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_CLKHOLD) >> SERCOM_I2CM_STATUS_CLKHOLD_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_CLKHOLD_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_CLKHOLD; + tmp |= value << SERCOM_I2CM_STATUS_CLKHOLD_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_MEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_MEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_MEXTTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_MEXTTOUT) >> SERCOM_I2CM_STATUS_MEXTTOUT_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_MEXTTOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_MEXTTOUT; + tmp |= value << SERCOM_I2CM_STATUS_MEXTTOUT_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_MEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_MEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_MEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_MEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_SEXTTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_SEXTTOUT) >> SERCOM_I2CM_STATUS_SEXTTOUT_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_SEXTTOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_SEXTTOUT; + tmp |= value << SERCOM_I2CM_STATUS_SEXTTOUT_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_LENERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LENERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_LENERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LENERR) >> SERCOM_I2CM_STATUS_LENERR_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_LENERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_LENERR; + tmp |= value << SERCOM_I2CM_STATUS_LENERR_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_LENERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LENERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_LENERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LENERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_BUSSTATE_bf(const void *const hw, + hri_sercomi2cm_status_reg_t mask) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(mask)) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos; +} + +static inline void hri_sercomi2cm_set_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSSTATE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_BUSSTATE_bf(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE_Msk) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_BUSSTATE_Msk; + tmp |= SERCOM_I2CM_STATUS_BUSSTATE(data); + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSSTATE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSSTATE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_reg(const void *const hw, + hri_sercomi2cm_status_reg_t mask) +{ + uint16_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_set_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + ((Sercom *)hw)->I2CM.STATUS.reg |= mask; +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return ((Sercom *)hw)->I2CM.STATUS.reg; +} + +static inline void hri_sercomi2cm_write_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t data) +{ + ((Sercom *)hw)->I2CM.STATUS.reg = data; +} + +static inline void hri_sercomi2cm_toggle_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + ((Sercom *)hw)->I2CM.STATUS.reg ^= mask; +} + +static inline void hri_sercomi2cm_clear_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_sercomusart_set_BAUD_FRAC_reg(a, b) hri_sercomusart_set_BAUD_reg(a, b) +#define hri_sercomusart_get_BAUD_FRAC_reg(a, b) hri_sercomusart_get_BAUD_reg(a, b) +#define hri_sercomusart_write_BAUD_FRAC_reg(a, b) hri_sercomusart_write_BAUD_reg(a, b) +#define hri_sercomusart_clear_BAUD_FRAC_reg(a, b) hri_sercomusart_clear_BAUD_reg(a, b) +#define hri_sercomusart_toggle_BAUD_FRAC_reg(a, b) hri_sercomusart_toggle_BAUD_reg(a, b) +#define hri_sercomusart_read_BAUD_FRAC_reg(a) hri_sercomusart_read_BAUD_reg(a) +#define hri_sercomusart_set_BAUD_FRACFP_reg(a, b) hri_sercomusart_set_BAUD_reg(a, b) +#define hri_sercomusart_get_BAUD_FRACFP_reg(a, b) hri_sercomusart_get_BAUD_reg(a, b) +#define hri_sercomusart_write_BAUD_FRACFP_reg(a, b) hri_sercomusart_write_BAUD_reg(a, b) +#define hri_sercomusart_clear_BAUD_FRACFP_reg(a, b) hri_sercomusart_clear_BAUD_reg(a, b) +#define hri_sercomusart_toggle_BAUD_FRACFP_reg(a, b) hri_sercomusart_toggle_BAUD_reg(a, b) +#define hri_sercomusart_read_BAUD_FRACFP_reg(a) hri_sercomusart_read_BAUD_reg(a) +#define hri_sercomusart_set_BAUD_USARTFP_reg(a, b) hri_sercomusart_set_BAUD_reg(a, b) +#define hri_sercomusart_get_BAUD_USARTFP_reg(a, b) hri_sercomusart_get_BAUD_reg(a, b) +#define hri_sercomusart_write_BAUD_USARTFP_reg(a, b) hri_sercomusart_write_BAUD_reg(a, b) +#define hri_sercomusart_clear_BAUD_USARTFP_reg(a, b) hri_sercomusart_clear_BAUD_reg(a, b) +#define hri_sercomusart_toggle_BAUD_USARTFP_reg(a, b) hri_sercomusart_toggle_BAUD_reg(a, b) +#define hri_sercomusart_read_BAUD_USARTFP_reg(a) hri_sercomusart_read_BAUD_reg(a) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SERCOM_L21_H_INCLUDED */ +#endif /* _SAML21_SERCOM_COMPONENT_ */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_supc_l21.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_supc_l21.h new file mode 100644 index 00000000..5d569345 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_supc_l21.h @@ -0,0 +1,2492 @@ +/** + * \file + * + * \brief SAM SUPC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_SUPC_COMPONENT_ +#ifndef _HRI_SUPC_L21_H_INCLUDED_ +#define _HRI_SUPC_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SUPC_CRITICAL_SECTIONS) +#define SUPC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SUPC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SUPC_CRITICAL_SECTION_ENTER() +#define SUPC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_supc_bbps_reg_t; +typedef uint32_t hri_supc_bkin_reg_t; +typedef uint32_t hri_supc_bkout_reg_t; +typedef uint32_t hri_supc_bod12_reg_t; +typedef uint32_t hri_supc_bod33_reg_t; +typedef uint32_t hri_supc_intenset_reg_t; +typedef uint32_t hri_supc_intflag_reg_t; +typedef uint32_t hri_supc_status_reg_t; +typedef uint32_t hri_supc_vref_reg_t; +typedef uint32_t hri_supc_vreg_reg_t; + +static inline bool hri_supc_get_INTFLAG_BOD33RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33RDY) >> SUPC_INTFLAG_BOD33RDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_BOD33RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY; +} + +static inline bool hri_supc_get_INTFLAG_BOD33DET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33DET) >> SUPC_INTFLAG_BOD33DET_Pos; +} + +static inline void hri_supc_clear_INTFLAG_BOD33DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33DET; +} + +static inline bool hri_supc_get_INTFLAG_B33SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B33SRDY) >> SUPC_INTFLAG_B33SRDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_B33SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B33SRDY; +} + +static inline bool hri_supc_get_INTFLAG_BOD12RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12RDY) >> SUPC_INTFLAG_BOD12RDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_BOD12RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12RDY; +} + +static inline bool hri_supc_get_INTFLAG_BOD12DET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12DET) >> SUPC_INTFLAG_BOD12DET_Pos; +} + +static inline void hri_supc_clear_INTFLAG_BOD12DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12DET; +} + +static inline bool hri_supc_get_INTFLAG_B12SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B12SRDY) >> SUPC_INTFLAG_B12SRDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_B12SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B12SRDY; +} + +static inline bool hri_supc_get_INTFLAG_VREGRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VREGRDY) >> SUPC_INTFLAG_VREGRDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_VREGRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VREGRDY; +} + +static inline bool hri_supc_get_INTFLAG_APWSRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_APWSRDY) >> SUPC_INTFLAG_APWSRDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_APWSRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_APWSRDY; +} + +static inline bool hri_supc_get_INTFLAG_VCORERDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VCORERDY) >> SUPC_INTFLAG_VCORERDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_VCORERDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VCORERDY; +} + +static inline bool hri_supc_get_interrupt_BOD33RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33RDY) >> SUPC_INTFLAG_BOD33RDY_Pos; +} + +static inline void hri_supc_clear_interrupt_BOD33RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY; +} + +static inline bool hri_supc_get_interrupt_BOD33DET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33DET) >> SUPC_INTFLAG_BOD33DET_Pos; +} + +static inline void hri_supc_clear_interrupt_BOD33DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33DET; +} + +static inline bool hri_supc_get_interrupt_B33SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B33SRDY) >> SUPC_INTFLAG_B33SRDY_Pos; +} + +static inline void hri_supc_clear_interrupt_B33SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B33SRDY; +} + +static inline bool hri_supc_get_interrupt_BOD12RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12RDY) >> SUPC_INTFLAG_BOD12RDY_Pos; +} + +static inline void hri_supc_clear_interrupt_BOD12RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12RDY; +} + +static inline bool hri_supc_get_interrupt_BOD12DET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12DET) >> SUPC_INTFLAG_BOD12DET_Pos; +} + +static inline void hri_supc_clear_interrupt_BOD12DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12DET; +} + +static inline bool hri_supc_get_interrupt_B12SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B12SRDY) >> SUPC_INTFLAG_B12SRDY_Pos; +} + +static inline void hri_supc_clear_interrupt_B12SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B12SRDY; +} + +static inline bool hri_supc_get_interrupt_VREGRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VREGRDY) >> SUPC_INTFLAG_VREGRDY_Pos; +} + +static inline void hri_supc_clear_interrupt_VREGRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VREGRDY; +} + +static inline bool hri_supc_get_interrupt_APWSRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_APWSRDY) >> SUPC_INTFLAG_APWSRDY_Pos; +} + +static inline void hri_supc_clear_interrupt_APWSRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_APWSRDY; +} + +static inline bool hri_supc_get_interrupt_VCORERDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VCORERDY) >> SUPC_INTFLAG_VCORERDY_Pos; +} + +static inline void hri_supc_clear_interrupt_VCORERDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VCORERDY; +} + +static inline hri_supc_intflag_reg_t hri_supc_get_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_supc_intflag_reg_t hri_supc_read_INTFLAG_reg(const void *const hw) +{ + return ((Supc *)hw)->INTFLAG.reg; +} + +static inline void hri_supc_clear_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask) +{ + ((Supc *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_supc_set_INTEN_BOD33RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY; +} + +static inline bool hri_supc_get_INTEN_BOD33RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33RDY) >> SUPC_INTENSET_BOD33RDY_Pos; +} + +static inline void hri_supc_write_INTEN_BOD33RDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY; + } +} + +static inline void hri_supc_clear_INTEN_BOD33RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY; +} + +static inline void hri_supc_set_INTEN_BOD33DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET; +} + +static inline bool hri_supc_get_INTEN_BOD33DET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33DET) >> SUPC_INTENSET_BOD33DET_Pos; +} + +static inline void hri_supc_write_INTEN_BOD33DET_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET; + } +} + +static inline void hri_supc_clear_INTEN_BOD33DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET; +} + +static inline void hri_supc_set_INTEN_B33SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B33SRDY; +} + +static inline bool hri_supc_get_INTEN_B33SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_B33SRDY) >> SUPC_INTENSET_B33SRDY_Pos; +} + +static inline void hri_supc_write_INTEN_B33SRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B33SRDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B33SRDY; + } +} + +static inline void hri_supc_clear_INTEN_B33SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B33SRDY; +} + +static inline void hri_supc_set_INTEN_BOD12RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12RDY; +} + +static inline bool hri_supc_get_INTEN_BOD12RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD12RDY) >> SUPC_INTENSET_BOD12RDY_Pos; +} + +static inline void hri_supc_write_INTEN_BOD12RDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12RDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12RDY; + } +} + +static inline void hri_supc_clear_INTEN_BOD12RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12RDY; +} + +static inline void hri_supc_set_INTEN_BOD12DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12DET; +} + +static inline bool hri_supc_get_INTEN_BOD12DET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD12DET) >> SUPC_INTENSET_BOD12DET_Pos; +} + +static inline void hri_supc_write_INTEN_BOD12DET_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12DET; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12DET; + } +} + +static inline void hri_supc_clear_INTEN_BOD12DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12DET; +} + +static inline void hri_supc_set_INTEN_B12SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B12SRDY; +} + +static inline bool hri_supc_get_INTEN_B12SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_B12SRDY) >> SUPC_INTENSET_B12SRDY_Pos; +} + +static inline void hri_supc_write_INTEN_B12SRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B12SRDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B12SRDY; + } +} + +static inline void hri_supc_clear_INTEN_B12SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B12SRDY; +} + +static inline void hri_supc_set_INTEN_VREGRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VREGRDY; +} + +static inline bool hri_supc_get_INTEN_VREGRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_VREGRDY) >> SUPC_INTENSET_VREGRDY_Pos; +} + +static inline void hri_supc_write_INTEN_VREGRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VREGRDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VREGRDY; + } +} + +static inline void hri_supc_clear_INTEN_VREGRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VREGRDY; +} + +static inline void hri_supc_set_INTEN_APWSRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_APWSRDY; +} + +static inline bool hri_supc_get_INTEN_APWSRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_APWSRDY) >> SUPC_INTENSET_APWSRDY_Pos; +} + +static inline void hri_supc_write_INTEN_APWSRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_APWSRDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_APWSRDY; + } +} + +static inline void hri_supc_clear_INTEN_APWSRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_APWSRDY; +} + +static inline void hri_supc_set_INTEN_VCORERDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VCORERDY; +} + +static inline bool hri_supc_get_INTEN_VCORERDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_VCORERDY) >> SUPC_INTENSET_VCORERDY_Pos; +} + +static inline void hri_supc_write_INTEN_VCORERDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VCORERDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VCORERDY; + } +} + +static inline void hri_supc_clear_INTEN_VCORERDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VCORERDY; +} + +static inline void hri_supc_set_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) +{ + ((Supc *)hw)->INTENSET.reg = mask; +} + +static inline hri_supc_intenset_reg_t hri_supc_get_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_supc_intenset_reg_t hri_supc_read_INTEN_reg(const void *const hw) +{ + return ((Supc *)hw)->INTENSET.reg; +} + +static inline void hri_supc_write_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t data) +{ + ((Supc *)hw)->INTENSET.reg = data; + ((Supc *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_supc_clear_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) +{ + ((Supc *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_supc_get_STATUS_BOD33RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD33RDY) >> SUPC_STATUS_BOD33RDY_Pos; +} + +static inline bool hri_supc_get_STATUS_BOD33DET_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD33DET) >> SUPC_STATUS_BOD33DET_Pos; +} + +static inline bool hri_supc_get_STATUS_B33SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_B33SRDY) >> SUPC_STATUS_B33SRDY_Pos; +} + +static inline bool hri_supc_get_STATUS_BOD12RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD12RDY) >> SUPC_STATUS_BOD12RDY_Pos; +} + +static inline bool hri_supc_get_STATUS_BOD12DET_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD12DET) >> SUPC_STATUS_BOD12DET_Pos; +} + +static inline bool hri_supc_get_STATUS_B12SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_B12SRDY) >> SUPC_STATUS_B12SRDY_Pos; +} + +static inline bool hri_supc_get_STATUS_VREGRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_VREGRDY) >> SUPC_STATUS_VREGRDY_Pos; +} + +static inline bool hri_supc_get_STATUS_APWSRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_APWSRDY) >> SUPC_STATUS_APWSRDY_Pos; +} + +static inline bool hri_supc_get_STATUS_VCORERDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_VCORERDY) >> SUPC_STATUS_VCORERDY_Pos; +} + +static inline bool hri_supc_get_STATUS_BBPS_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BBPS) >> SUPC_STATUS_BBPS_Pos; +} + +static inline hri_supc_status_reg_t hri_supc_get_STATUS_reg(const void *const hw, hri_supc_status_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_supc_status_reg_t hri_supc_read_STATUS_reg(const void *const hw) +{ + return ((Supc *)hw)->STATUS.reg; +} + +static inline hri_supc_bkin_reg_t hri_supc_get_BKIN_BKIN_bf(const void *const hw, hri_supc_bkin_reg_t mask) +{ + return (((Supc *)hw)->BKIN.reg & SUPC_BKIN_BKIN(mask)) >> SUPC_BKIN_BKIN_Pos; +} + +static inline hri_supc_bkin_reg_t hri_supc_read_BKIN_BKIN_bf(const void *const hw) +{ + return (((Supc *)hw)->BKIN.reg & SUPC_BKIN_BKIN_Msk) >> SUPC_BKIN_BKIN_Pos; +} + +static inline hri_supc_bkin_reg_t hri_supc_get_BKIN_reg(const void *const hw, hri_supc_bkin_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKIN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_supc_bkin_reg_t hri_supc_read_BKIN_reg(const void *const hw) +{ + return ((Supc *)hw)->BKIN.reg; +} + +static inline void hri_supc_set_BOD33_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_ENABLE) >> SUPC_BOD33_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_ENABLE; + tmp |= value << SUPC_BOD33_ENABLE_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_HYST_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_HYST; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_HYST_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_HYST) >> SUPC_BOD33_HYST_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_HYST_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_HYST; + tmp |= value << SUPC_BOD33_HYST_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_HYST_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_HYST; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_HYST_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_HYST; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_STDBYCFG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_STDBYCFG) >> SUPC_BOD33_STDBYCFG_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_STDBYCFG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_STDBYCFG; + tmp |= value << SUPC_BOD33_STDBYCFG_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_RUNSTDBY) >> SUPC_BOD33_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_RUNSTDBY; + tmp |= value << SUPC_BOD33_RUNSTDBY_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_RUNBKUP_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNBKUP; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_RUNBKUP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_RUNBKUP) >> SUPC_BOD33_RUNBKUP_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_RUNBKUP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_RUNBKUP; + tmp |= value << SUPC_BOD33_RUNBKUP_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_RUNBKUP_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNBKUP; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_RUNBKUP_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNBKUP; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_ACTCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ACTCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_ACTCFG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_ACTCFG) >> SUPC_BOD33_ACTCFG_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_ACTCFG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_ACTCFG; + tmp |= value << SUPC_BOD33_ACTCFG_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_ACTCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ACTCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_ACTCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ACTCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_VMON_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_VMON; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_VMON_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_VMON) >> SUPC_BOD33_VMON_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_VMON_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_VMON; + tmp |= value << SUPC_BOD33_VMON_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_VMON_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_VMON; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_VMON_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_VMON; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_ACTION(mask)) >> SUPC_BOD33_ACTION_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_ACTION_Msk; + tmp |= SUPC_BOD33_ACTION(data); + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_ACTION_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_ACTION_Msk) >> SUPC_BOD33_ACTION_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_PSEL(mask)) >> SUPC_BOD33_PSEL_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_PSEL_Msk; + tmp |= SUPC_BOD33_PSEL(data); + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_PSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_PSEL_Msk) >> SUPC_BOD33_PSEL_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_LEVEL(mask)) >> SUPC_BOD33_LEVEL_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_LEVEL_Msk; + tmp |= SUPC_BOD33_LEVEL(data); + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_LEVEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_LEVEL_Msk) >> SUPC_BOD33_LEVEL_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD33_BKUPLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_BKUPLEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_BKUPLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_BKUPLEVEL(mask)) >> SUPC_BOD33_BKUPLEVEL_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD33_BKUPLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_BKUPLEVEL_Msk; + tmp |= SUPC_BOD33_BKUPLEVEL(data); + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_BKUPLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_BKUPLEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_BKUPLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_BKUPLEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_BKUPLEVEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_BKUPLEVEL_Msk) >> SUPC_BOD33_BKUPLEVEL_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_reg(const void *const hw) +{ + return ((Supc *)hw)->BOD33.reg; +} + +static inline void hri_supc_set_BOD12_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD12_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_ENABLE) >> SUPC_BOD12_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD12_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD12.reg; + tmp &= ~SUPC_BOD12_ENABLE; + tmp |= value << SUPC_BOD12_ENABLE_Pos; + ((Supc *)hw)->BOD12.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD12_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD12_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD12_HYST_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_HYST; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD12_HYST_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_HYST) >> SUPC_BOD12_HYST_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD12_HYST_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD12.reg; + tmp &= ~SUPC_BOD12_HYST; + tmp |= value << SUPC_BOD12_HYST_Pos; + ((Supc *)hw)->BOD12.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD12_HYST_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_HYST; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD12_HYST_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_HYST; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD12_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD12_STDBYCFG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_STDBYCFG) >> SUPC_BOD12_STDBYCFG_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD12_STDBYCFG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD12.reg; + tmp &= ~SUPC_BOD12_STDBYCFG; + tmp |= value << SUPC_BOD12_STDBYCFG_Pos; + ((Supc *)hw)->BOD12.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD12_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD12_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD12_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD12_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_RUNSTDBY) >> SUPC_BOD12_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD12_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD12.reg; + tmp &= ~SUPC_BOD12_RUNSTDBY; + tmp |= value << SUPC_BOD12_RUNSTDBY_Pos; + ((Supc *)hw)->BOD12.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD12_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD12_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD12_ACTCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_ACTCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD12_ACTCFG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_ACTCFG) >> SUPC_BOD12_ACTCFG_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD12_ACTCFG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD12.reg; + tmp &= ~SUPC_BOD12_ACTCFG; + tmp |= value << SUPC_BOD12_ACTCFG_Pos; + ((Supc *)hw)->BOD12.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD12_ACTCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_ACTCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD12_ACTCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_ACTCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_ACTION(mask)) >> SUPC_BOD12_ACTION_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD12.reg; + tmp &= ~SUPC_BOD12_ACTION_Msk; + tmp |= SUPC_BOD12_ACTION(data); + ((Supc *)hw)->BOD12.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_ACTION_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_ACTION_Msk) >> SUPC_BOD12_ACTION_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_PSEL(mask)) >> SUPC_BOD12_PSEL_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD12.reg; + tmp &= ~SUPC_BOD12_PSEL_Msk; + tmp |= SUPC_BOD12_PSEL(data); + ((Supc *)hw)->BOD12.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_PSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_PSEL_Msk) >> SUPC_BOD12_PSEL_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_LEVEL(mask)) >> SUPC_BOD12_LEVEL_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD12.reg; + tmp &= ~SUPC_BOD12_LEVEL_Msk; + tmp |= SUPC_BOD12_LEVEL(data); + ((Supc *)hw)->BOD12.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_LEVEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_LEVEL_Msk) >> SUPC_BOD12_LEVEL_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_reg(const void *const hw) +{ + return ((Supc *)hw)->BOD12.reg; +} + +static inline void hri_supc_set_VREG_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREG_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_ENABLE) >> SUPC_VREG_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREG_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_ENABLE; + tmp |= value << SUPC_VREG_ENABLE_Pos; + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREG_STDBYPL0_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_STDBYPL0; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREG_STDBYPL0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_STDBYPL0) >> SUPC_VREG_STDBYPL0_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREG_STDBYPL0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_STDBYPL0; + tmp |= value << SUPC_VREG_STDBYPL0_Pos; + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_STDBYPL0_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_STDBYPL0; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_STDBYPL0_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_STDBYPL0; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREG_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREG_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_RUNSTDBY) >> SUPC_VREG_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREG_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_RUNSTDBY; + tmp |= value << SUPC_VREG_RUNSTDBY_Pos; + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREG_LPEFF_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_LPEFF; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREG_LPEFF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_LPEFF) >> SUPC_VREG_LPEFF_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREG_LPEFF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_LPEFF; + tmp |= value << SUPC_VREG_LPEFF_Pos; + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_LPEFF_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_LPEFF; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_LPEFF_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_LPEFF; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREG_SEL_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_SEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_get_VREG_SEL_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_SEL(mask)) >> SUPC_VREG_SEL_Pos; + return tmp; +} + +static inline void hri_supc_write_VREG_SEL_bf(const void *const hw, hri_supc_vreg_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_SEL_Msk; + tmp |= SUPC_VREG_SEL(data); + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_SEL_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_SEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_SEL_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_SEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_read_VREG_SEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_SEL_Msk) >> SUPC_VREG_SEL_Pos; + return tmp; +} + +static inline void hri_supc_set_VREG_VSVSTEP_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_VSVSTEP(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_get_VREG_VSVSTEP_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_VSVSTEP(mask)) >> SUPC_VREG_VSVSTEP_Pos; + return tmp; +} + +static inline void hri_supc_write_VREG_VSVSTEP_bf(const void *const hw, hri_supc_vreg_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_VSVSTEP_Msk; + tmp |= SUPC_VREG_VSVSTEP(data); + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_VSVSTEP_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_VSVSTEP(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_VSVSTEP_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_VSVSTEP(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_read_VREG_VSVSTEP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_VSVSTEP_Msk) >> SUPC_VREG_VSVSTEP_Pos; + return tmp; +} + +static inline void hri_supc_set_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_VSPER(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_get_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_VSPER(mask)) >> SUPC_VREG_VSPER_Pos; + return tmp; +} + +static inline void hri_supc_write_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_VSPER_Msk; + tmp |= SUPC_VREG_VSPER(data); + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_VSPER(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_VSPER(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_read_VREG_VSPER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_VSPER_Msk) >> SUPC_VREG_VSPER_Pos; + return tmp; +} + +static inline void hri_supc_set_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_get_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_VREG_reg(const void *const hw, hri_supc_vreg_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_read_VREG_reg(const void *const hw) +{ + return ((Supc *)hw)->VREG.reg; +} + +static inline void hri_supc_set_VREF_TSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_TSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_TSEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_TSEN) >> SUPC_VREF_TSEN_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_TSEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_TSEN; + tmp |= value << SUPC_VREF_TSEN_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_TSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_TSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_TSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_TSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_VREFOE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_VREFOE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_VREFOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_VREFOE) >> SUPC_VREF_VREFOE_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_VREFOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_VREFOE; + tmp |= value << SUPC_VREF_VREFOE_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_VREFOE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_VREFOE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_VREFOE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_VREFOE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_RUNSTDBY) >> SUPC_VREF_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_RUNSTDBY; + tmp |= value << SUPC_VREF_RUNSTDBY_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_ONDEMAND_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_ONDEMAND; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_ONDEMAND_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_ONDEMAND) >> SUPC_VREF_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_ONDEMAND_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_ONDEMAND; + tmp |= value << SUPC_VREF_ONDEMAND_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_ONDEMAND_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_ONDEMAND; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_ONDEMAND_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_ONDEMAND; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_SEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vref_reg_t hri_supc_get_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_SEL(mask)) >> SUPC_VREF_SEL_Pos; + return tmp; +} + +static inline void hri_supc_write_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_SEL_Msk; + tmp |= SUPC_VREF_SEL(data); + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_SEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_SEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vref_reg_t hri_supc_read_VREF_SEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_SEL_Msk) >> SUPC_VREF_SEL_Pos; + return tmp; +} + +static inline void hri_supc_set_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vref_reg_t hri_supc_get_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_VREF_reg(const void *const hw, hri_supc_vref_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vref_reg_t hri_supc_read_VREF_reg(const void *const hw) +{ + return ((Supc *)hw)->VREF.reg; +} + +static inline void hri_supc_set_BBPS_WAKEEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg |= SUPC_BBPS_WAKEEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BBPS_WAKEEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BBPS.reg; + tmp = (tmp & SUPC_BBPS_WAKEEN) >> SUPC_BBPS_WAKEEN_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BBPS_WAKEEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BBPS.reg; + tmp &= ~SUPC_BBPS_WAKEEN; + tmp |= value << SUPC_BBPS_WAKEEN_Pos; + ((Supc *)hw)->BBPS.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BBPS_WAKEEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_WAKEEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BBPS_WAKEEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_WAKEEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BBPS_PSOKEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg |= SUPC_BBPS_PSOKEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BBPS_PSOKEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BBPS.reg; + tmp = (tmp & SUPC_BBPS_PSOKEN) >> SUPC_BBPS_PSOKEN_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BBPS_PSOKEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BBPS.reg; + tmp &= ~SUPC_BBPS_PSOKEN; + tmp |= value << SUPC_BBPS_PSOKEN_Pos; + ((Supc *)hw)->BBPS.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BBPS_PSOKEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_PSOKEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BBPS_PSOKEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_PSOKEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BBPS_CONF_bf(const void *const hw, hri_supc_bbps_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg |= SUPC_BBPS_CONF(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bbps_reg_t hri_supc_get_BBPS_CONF_bf(const void *const hw, hri_supc_bbps_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BBPS.reg; + tmp = (tmp & SUPC_BBPS_CONF(mask)) >> SUPC_BBPS_CONF_Pos; + return tmp; +} + +static inline void hri_supc_write_BBPS_CONF_bf(const void *const hw, hri_supc_bbps_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BBPS.reg; + tmp &= ~SUPC_BBPS_CONF_Msk; + tmp |= SUPC_BBPS_CONF(data); + ((Supc *)hw)->BBPS.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BBPS_CONF_bf(const void *const hw, hri_supc_bbps_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_CONF(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BBPS_CONF_bf(const void *const hw, hri_supc_bbps_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_CONF(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bbps_reg_t hri_supc_read_BBPS_CONF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BBPS.reg; + tmp = (tmp & SUPC_BBPS_CONF_Msk) >> SUPC_BBPS_CONF_Pos; + return tmp; +} + +static inline void hri_supc_set_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bbps_reg_t hri_supc_get_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BBPS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bbps_reg_t hri_supc_read_BBPS_reg(const void *const hw) +{ + return ((Supc *)hw)->BBPS.reg; +} + +static inline void hri_supc_set_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_EN(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_EN(mask)) >> SUPC_BKOUT_EN_Pos; + return tmp; +} + +static inline void hri_supc_write_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BKOUT.reg; + tmp &= ~SUPC_BKOUT_EN_Msk; + tmp |= SUPC_BKOUT_EN(data); + ((Supc *)hw)->BKOUT.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_EN(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_EN(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_EN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_EN_Msk) >> SUPC_BKOUT_EN_Pos; + return tmp; +} + +static inline void hri_supc_set_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_CLR(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_CLR(mask)) >> SUPC_BKOUT_CLR_Pos; + return tmp; +} + +static inline void hri_supc_write_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BKOUT.reg; + tmp &= ~SUPC_BKOUT_CLR_Msk; + tmp |= SUPC_BKOUT_CLR(data); + ((Supc *)hw)->BKOUT.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_CLR(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_CLR(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_CLR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_CLR_Msk) >> SUPC_BKOUT_CLR_Pos; + return tmp; +} + +static inline void hri_supc_set_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_SET(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_SET(mask)) >> SUPC_BKOUT_SET_Pos; + return tmp; +} + +static inline void hri_supc_write_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BKOUT.reg; + tmp &= ~SUPC_BKOUT_SET_Msk; + tmp |= SUPC_BKOUT_SET(data); + ((Supc *)hw)->BKOUT.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_SET(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_SET(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_SET_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_SET_Msk) >> SUPC_BKOUT_SET_Pos; + return tmp; +} + +static inline void hri_supc_set_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_RTCTGL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_RTCTGL(mask)) >> SUPC_BKOUT_RTCTGL_Pos; + return tmp; +} + +static inline void hri_supc_write_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BKOUT.reg; + tmp &= ~SUPC_BKOUT_RTCTGL_Msk; + tmp |= SUPC_BKOUT_RTCTGL(data); + ((Supc *)hw)->BKOUT.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_RTCTGL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_RTCTGL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_RTCTGL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_RTCTGL_Msk) >> SUPC_BKOUT_RTCTGL_Pos; + return tmp; +} + +static inline void hri_supc_set_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_reg(const void *const hw) +{ + return ((Supc *)hw)->BKOUT.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SUPC_L21_H_INCLUDED */ +#endif /* _SAML21_SUPC_COMPONENT_ */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_systemcontrol_l21.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_systemcontrol_l21.h new file mode 100644 index 00000000..619b62f0 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_systemcontrol_l21.h @@ -0,0 +1,498 @@ +/** + * \file + * + * \brief SAM SystemControl + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_SystemControl_COMPONENT_ +#ifndef _HRI_SystemControl_L21_H_INCLUDED_ +#define _HRI_SystemControl_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SystemControl_CRITICAL_SECTIONS) +#define SystemControl_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SystemControl_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SystemControl_CRITICAL_SECTION_ENTER() +#define SystemControl_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_systemcontrol_aircr_reg_t; +typedef uint32_t hri_systemcontrol_ccr_reg_t; +typedef uint32_t hri_systemcontrol_cpuid_reg_t; +typedef uint32_t hri_systemcontrol_dfsr_reg_t; +typedef uint32_t hri_systemcontrol_icsr_reg_t; +typedef uint32_t hri_systemcontrol_scr_reg_t; +typedef uint32_t hri_systemcontrol_shcsr_reg_t; +typedef uint32_t hri_systemcontrol_shpr2_reg_t; +typedef uint32_t hri_systemcontrol_shpr3_reg_t; +typedef uint32_t hri_systemcontrol_vtor_reg_t; + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_REVISION_bf(const void *const hw, + hri_systemcontrol_cpuid_reg_t mask) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_REVISION(mask)) >> 0; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_REVISION_bf(const void *const hw) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_REVISION_Msk) >> 0; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_PARTNO_bf(const void *const hw, + hri_systemcontrol_cpuid_reg_t mask) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_PARTNO(mask)) >> 4; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_PARTNO_bf(const void *const hw) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_PARTNO_Msk) >> 4; +} + +static inline hri_systemcontrol_cpuid_reg_t +hri_systemcontrol_get_CPUID_ARCHITECTURE_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_ARCHITECTURE(mask)) >> 16; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_ARCHITECTURE_bf(const void *const hw) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_ARCHITECTURE_Msk) >> 16; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_VARIANT_bf(const void *const hw, + hri_systemcontrol_cpuid_reg_t mask) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_VARIANT(mask)) >> 20; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_VARIANT_bf(const void *const hw) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_VARIANT_Msk) >> 20; +} + +static inline hri_systemcontrol_cpuid_reg_t +hri_systemcontrol_get_CPUID_IMPLEMENTER_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_IMPLEMENTER(mask)) >> 24; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_IMPLEMENTER_bf(const void *const hw) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_IMPLEMENTER_Msk) >> 24; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_reg(const void *const hw, + hri_systemcontrol_cpuid_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->CPUID.reg; + tmp &= mask; + return tmp; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->CPUID.reg; +} + +static inline bool hri_systemcontrol_get_CCR_UNALIGN_TRP_bit(const void *const hw) +{ + return (((Systemcontrol *)hw)->CCR.reg & SystemControl_CCR_UNALIGN_TRP) >> 3; +} + +static inline bool hri_systemcontrol_get_CCR_STKALIGN_bit(const void *const hw) +{ + return (((Systemcontrol *)hw)->CCR.reg & SystemControl_CCR_STKALIGN) >> 9; +} + +static inline hri_systemcontrol_ccr_reg_t hri_systemcontrol_get_CCR_reg(const void *const hw, + hri_systemcontrol_ccr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->CCR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_systemcontrol_ccr_reg_t hri_systemcontrol_read_CCR_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->CCR.reg; +} + +static inline void hri_systemcontrol_set_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->ICSR.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_icsr_reg_t hri_systemcontrol_get_ICSR_reg(const void *const hw, + hri_systemcontrol_icsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->ICSR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->ICSR.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->ICSR.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->ICSR.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_icsr_reg_t hri_systemcontrol_read_ICSR_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->ICSR.reg; +} + +static inline void hri_systemcontrol_set_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->VTOR.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_vtor_reg_t hri_systemcontrol_get_VTOR_reg(const void *const hw, + hri_systemcontrol_vtor_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->VTOR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->VTOR.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->VTOR.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->VTOR.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_vtor_reg_t hri_systemcontrol_read_VTOR_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->VTOR.reg; +} + +static inline void hri_systemcontrol_set_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->AIRCR.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_aircr_reg_t hri_systemcontrol_get_AIRCR_reg(const void *const hw, + hri_systemcontrol_aircr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->AIRCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->AIRCR.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->AIRCR.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->AIRCR.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_aircr_reg_t hri_systemcontrol_read_AIRCR_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->AIRCR.reg; +} + +static inline void hri_systemcontrol_set_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SCR.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_scr_reg_t hri_systemcontrol_get_SCR_reg(const void *const hw, + hri_systemcontrol_scr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->SCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SCR.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SCR.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SCR.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_scr_reg_t hri_systemcontrol_read_SCR_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->SCR.reg; +} + +static inline void hri_systemcontrol_set_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR2.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_shpr2_reg_t hri_systemcontrol_get_SHPR2_reg(const void *const hw, + hri_systemcontrol_shpr2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->SHPR2.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR2.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR2.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR2.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_shpr2_reg_t hri_systemcontrol_read_SHPR2_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->SHPR2.reg; +} + +static inline void hri_systemcontrol_set_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR3.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_get_SHPR3_reg(const void *const hw, + hri_systemcontrol_shpr3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->SHPR3.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR3.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR3.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR3.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_read_SHPR3_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->SHPR3.reg; +} + +static inline void hri_systemcontrol_set_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHCSR.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_shcsr_reg_t hri_systemcontrol_get_SHCSR_reg(const void *const hw, + hri_systemcontrol_shcsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->SHCSR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHCSR.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHCSR.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHCSR.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_shcsr_reg_t hri_systemcontrol_read_SHCSR_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->SHCSR.reg; +} + +static inline void hri_systemcontrol_set_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->DFSR.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_dfsr_reg_t hri_systemcontrol_get_DFSR_reg(const void *const hw, + hri_systemcontrol_dfsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->DFSR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->DFSR.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->DFSR.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->DFSR.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_dfsr_reg_t hri_systemcontrol_read_DFSR_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->DFSR.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SystemControl_L21_H_INCLUDED */ +#endif /* _SAML21_SystemControl_COMPONENT_ */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_systick_l21.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_systick_l21.h new file mode 100644 index 00000000..1dda6dc9 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_systick_l21.h @@ -0,0 +1,219 @@ +/** + * \file + * + * \brief SAM SysTick + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_SysTick_COMPONENT_ +#ifndef _HRI_SysTick_L21_H_INCLUDED_ +#define _HRI_SysTick_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SysTick_CRITICAL_SECTIONS) +#define SysTick_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SysTick_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SysTick_CRITICAL_SECTION_ENTER() +#define SysTick_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_systick_calib_reg_t; +typedef uint32_t hri_systick_csr_reg_t; +typedef uint32_t hri_systick_cvr_reg_t; +typedef uint32_t hri_systick_rvr_reg_t; + +static inline bool hri_systick_get_CALIB_SKEW_bit(const void *const hw) +{ + return (((Systick *)hw)->CALIB.reg & SysTick_CALIB_SKEW) >> 30; +} + +static inline bool hri_systick_get_CALIB_NOREF_bit(const void *const hw) +{ + return (((Systick *)hw)->CALIB.reg & SysTick_CALIB_NOREF) >> 31; +} + +static inline hri_systick_calib_reg_t hri_systick_get_CALIB_TENMS_bf(const void *const hw, hri_systick_calib_reg_t mask) +{ + return (((Systick *)hw)->CALIB.reg & SysTick_CALIB_TENMS(mask)) >> 0; +} + +static inline hri_systick_calib_reg_t hri_systick_read_CALIB_TENMS_bf(const void *const hw) +{ + return (((Systick *)hw)->CALIB.reg & SysTick_CALIB_TENMS_Msk) >> 0; +} + +static inline hri_systick_calib_reg_t hri_systick_get_CALIB_reg(const void *const hw, hri_systick_calib_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systick *)hw)->CALIB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_systick_calib_reg_t hri_systick_read_CALIB_reg(const void *const hw) +{ + return ((Systick *)hw)->CALIB.reg; +} + +static inline void hri_systick_set_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CSR.reg |= mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_csr_reg_t hri_systick_get_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systick *)hw)->CSR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systick_write_CSR_reg(const void *const hw, hri_systick_csr_reg_t data) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CSR.reg = data; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_clear_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CSR.reg &= ~mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_toggle_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CSR.reg ^= mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_csr_reg_t hri_systick_read_CSR_reg(const void *const hw) +{ + return ((Systick *)hw)->CSR.reg; +} + +static inline void hri_systick_set_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->RVR.reg |= mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_rvr_reg_t hri_systick_get_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systick *)hw)->RVR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systick_write_RVR_reg(const void *const hw, hri_systick_rvr_reg_t data) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->RVR.reg = data; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_clear_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->RVR.reg &= ~mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_toggle_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->RVR.reg ^= mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_rvr_reg_t hri_systick_read_RVR_reg(const void *const hw) +{ + return ((Systick *)hw)->RVR.reg; +} + +static inline void hri_systick_set_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CVR.reg |= mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_cvr_reg_t hri_systick_get_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systick *)hw)->CVR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systick_write_CVR_reg(const void *const hw, hri_systick_cvr_reg_t data) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CVR.reg = data; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_clear_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CVR.reg &= ~mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_toggle_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CVR.reg ^= mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_cvr_reg_t hri_systick_read_CVR_reg(const void *const hw) +{ + return ((Systick *)hw)->CVR.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SysTick_L21_H_INCLUDED */ +#endif /* _SAML21_SysTick_COMPONENT_ */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_tc_l21.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_tc_l21.h new file mode 100644 index 00000000..3d536905 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_tc_l21.h @@ -0,0 +1,2899 @@ +/** + * \file + * + * \brief SAM TC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_TC_COMPONENT_ +#ifndef _HRI_TC_L21_H_INCLUDED_ +#define _HRI_TC_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_TC_CRITICAL_SECTIONS) +#define TC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define TC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define TC_CRITICAL_SECTION_ENTER() +#define TC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_tc_evctrl_reg_t; +typedef uint16_t hri_tccount16_cc_reg_t; +typedef uint16_t hri_tccount16_ccbuf_reg_t; +typedef uint16_t hri_tccount16_count_reg_t; +typedef uint32_t hri_tc_ctrla_reg_t; +typedef uint32_t hri_tc_syncbusy_reg_t; +typedef uint32_t hri_tccount32_cc_reg_t; +typedef uint32_t hri_tccount32_ccbuf_reg_t; +typedef uint32_t hri_tccount32_count_reg_t; +typedef uint8_t hri_tc_ctrlbset_reg_t; +typedef uint8_t hri_tc_dbgctrl_reg_t; +typedef uint8_t hri_tc_drvctrl_reg_t; +typedef uint8_t hri_tc_intenset_reg_t; +typedef uint8_t hri_tc_intflag_reg_t; +typedef uint8_t hri_tc_status_reg_t; +typedef uint8_t hri_tc_wave_reg_t; +typedef uint8_t hri_tccount8_cc_reg_t; +typedef uint8_t hri_tccount8_ccbuf_reg_t; +typedef uint8_t hri_tccount8_count_reg_t; +typedef uint8_t hri_tccount8_per_reg_t; +typedef uint8_t hri_tccount8_perbuf_reg_t; + +static inline void hri_tc_wait_for_sync(const void *const hw, hri_tc_syncbusy_reg_t reg) +{ + while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_tc_is_syncing(const void *const hw, hri_tc_syncbusy_reg_t reg) +{ + return ((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg; +} + +static inline bool hri_tc_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos; +} + +static inline void hri_tc_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_OVF; +} + +static inline bool hri_tc_get_INTFLAG_ERR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos; +} + +static inline void hri_tc_clear_INTFLAG_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_ERR; +} + +static inline bool hri_tc_get_INTFLAG_MC0_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos; +} + +static inline void hri_tc_clear_INTFLAG_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC0; +} + +static inline bool hri_tc_get_INTFLAG_MC1_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos; +} + +static inline void hri_tc_clear_INTFLAG_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC1; +} + +static inline bool hri_tc_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos; +} + +static inline void hri_tc_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_OVF; +} + +static inline bool hri_tc_get_interrupt_ERR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos; +} + +static inline void hri_tc_clear_interrupt_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_ERR; +} + +static inline bool hri_tc_get_interrupt_MC0_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos; +} + +static inline void hri_tc_clear_interrupt_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC0; +} + +static inline bool hri_tc_get_interrupt_MC1_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos; +} + +static inline void hri_tc_clear_interrupt_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC1; +} + +static inline hri_tc_intflag_reg_t hri_tc_get_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_intflag_reg_t hri_tc_read_INTFLAG_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.INTFLAG.reg; +} + +static inline void hri_tc_clear_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = mask; +} + +static inline void hri_tc_set_CTRLB_DIR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_DIR; +} + +static inline bool hri_tc_get_CTRLB_DIR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_DIR) >> TC_CTRLBSET_DIR_Pos; +} + +static inline void hri_tc_write_CTRLB_DIR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_DIR; + } else { + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_DIR; + } +} + +static inline void hri_tc_clear_CTRLB_DIR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_DIR; +} + +static inline void hri_tc_set_CTRLB_LUPD_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_LUPD; +} + +static inline bool hri_tc_get_CTRLB_LUPD_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_LUPD) >> TC_CTRLBSET_LUPD_Pos; +} + +static inline void hri_tc_write_CTRLB_LUPD_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_LUPD; + } else { + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_LUPD; + } +} + +static inline void hri_tc_clear_CTRLB_LUPD_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_LUPD; +} + +static inline void hri_tc_set_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_ONESHOT; +} + +static inline bool hri_tc_get_CTRLB_ONESHOT_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_ONESHOT) >> TC_CTRLBSET_ONESHOT_Pos; +} + +static inline void hri_tc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT; + } else { + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_ONESHOT; + } +} + +static inline void hri_tc_clear_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT; +} + +static inline void hri_tc_set_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD(mask); +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg; + tmp = (tmp & TC_CTRLBSET_CMD(mask)) >> TC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_CMD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg; + tmp = (tmp & TC_CTRLBSET_CMD_Msk) >> TC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t data) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD(data); + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = ~TC_CTRLBSET_CMD(data); +} + +static inline void hri_tc_clear_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_CMD(mask); +} + +static inline void hri_tc_set_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = mask; +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.CTRLBSET.reg; +} + +static inline void hri_tc_write_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t data) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = data; + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = ~data; +} + +static inline void hri_tc_clear_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = mask; +} + +static inline void hri_tc_set_INTEN_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_OVF; +} + +static inline bool hri_tc_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_OVF) >> TC_INTENSET_OVF_Pos; +} + +static inline void hri_tc_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_OVF; + } else { + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_OVF; + } +} + +static inline void hri_tc_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_OVF; +} + +static inline void hri_tc_set_INTEN_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_ERR; +} + +static inline bool hri_tc_get_INTEN_ERR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_ERR) >> TC_INTENSET_ERR_Pos; +} + +static inline void hri_tc_write_INTEN_ERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_ERR; + } else { + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_ERR; + } +} + +static inline void hri_tc_clear_INTEN_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_ERR; +} + +static inline void hri_tc_set_INTEN_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC0; +} + +static inline bool hri_tc_get_INTEN_MC0_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_MC0) >> TC_INTENSET_MC0_Pos; +} + +static inline void hri_tc_write_INTEN_MC0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC0; + } else { + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC0; + } +} + +static inline void hri_tc_clear_INTEN_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC0; +} + +static inline void hri_tc_set_INTEN_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC1; +} + +static inline bool hri_tc_get_INTEN_MC1_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_MC1) >> TC_INTENSET_MC1_Pos; +} + +static inline void hri_tc_write_INTEN_MC1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC1; + } else { + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC1; + } +} + +static inline void hri_tc_clear_INTEN_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC1; +} + +static inline void hri_tc_set_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = mask; +} + +static inline hri_tc_intenset_reg_t hri_tc_get_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_intenset_reg_t hri_tc_read_INTEN_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.INTENSET.reg; +} + +static inline void hri_tc_write_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t data) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = data; + ((Tc *)hw)->COUNT16.INTENCLR.reg = ~data; +} + +static inline void hri_tc_clear_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = mask; +} + +static inline bool hri_tc_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_SWRST) >> TC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_ENABLE) >> TC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CTRLB) >> TC_SYNCBUSY_CTRLB_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_STATUS_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_STATUS) >> TC_SYNCBUSY_STATUS_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_COUNT) >> TC_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_PER_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_PER) >> TC_SYNCBUSY_PER_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_CC0_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CC0) >> TC_SYNCBUSY_CC0_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_CC1_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CC1) >> TC_SYNCBUSY_CC1_Pos; +} + +static inline hri_tc_syncbusy_reg_t hri_tc_get_SYNCBUSY_reg(const void *const hw, hri_tc_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_syncbusy_reg_t hri_tc_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.SYNCBUSY.reg; +} + +static inline void hri_tc_set_CTRLA_SWRST_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_SWRST; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_SWRST) >> TC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_tc_set_CTRLA_ENABLE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ENABLE; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_ENABLE) >> TC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_ENABLE; + tmp |= value << TC_CTRLA_ENABLE_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ENABLE; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ENABLE; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_RUNSTDBY; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_RUNSTDBY) >> TC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_RUNSTDBY; + tmp |= value << TC_CTRLA_RUNSTDBY_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_RUNSTDBY; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_RUNSTDBY; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_ONDEMAND_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ONDEMAND; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_ONDEMAND_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_ONDEMAND) >> TC_CTRLA_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_ONDEMAND_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_ONDEMAND; + tmp |= value << TC_CTRLA_ONDEMAND_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_ONDEMAND_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ONDEMAND; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_ONDEMAND_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ONDEMAND; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_ALOCK_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ALOCK; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_ALOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_ALOCK) >> TC_CTRLA_ALOCK_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_ALOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_ALOCK; + tmp |= value << TC_CTRLA_ALOCK_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_ALOCK_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ALOCK; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_ALOCK_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ALOCK; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_CAPTEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_CAPTEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_CAPTEN0) >> TC_CTRLA_CAPTEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_CAPTEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_CAPTEN0; + tmp |= value << TC_CTRLA_CAPTEN0_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_CAPTEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_CAPTEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_CAPTEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_CAPTEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_CAPTEN1) >> TC_CTRLA_CAPTEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_CAPTEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_CAPTEN1; + tmp |= value << TC_CTRLA_CAPTEN1_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_CAPTEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_CAPTEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_COPEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_COPEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_COPEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_COPEN0) >> TC_CTRLA_COPEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_COPEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_COPEN0; + tmp |= value << TC_CTRLA_COPEN0_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_COPEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_COPEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_COPEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_COPEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_COPEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_COPEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_COPEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_COPEN1) >> TC_CTRLA_COPEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_COPEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_COPEN1; + tmp |= value << TC_CTRLA_COPEN1_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_COPEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_COPEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_COPEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_COPEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_MODE(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_MODE(mask)) >> TC_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_MODE_Msk; + tmp |= TC_CTRLA_MODE(data); + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_MODE(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_MODE(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_MODE_Msk) >> TC_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_PRESCSYNC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCSYNC(mask)) >> TC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_PRESCSYNC_Msk; + tmp |= TC_CTRLA_PRESCSYNC(data); + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_PRESCSYNC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_PRESCSYNC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCSYNC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCSYNC_Msk) >> TC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_PRESCALER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCALER(mask)) >> TC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_PRESCALER_Msk; + tmp |= TC_CTRLA_PRESCALER(data); + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_PRESCALER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_PRESCALER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCALER_Msk) >> TC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + return ((Tc *)hw)->COUNT16.CTRLA.reg; +} + +static inline void hri_tc_set_EVCTRL_TCINV_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_TCINV; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_TCINV_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_TCINV) >> TC_EVCTRL_TCINV_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_TCINV_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_TCINV; + tmp |= value << TC_EVCTRL_TCINV_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_TCINV_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_TCINV; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_TCINV_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_TCINV; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_TCEI_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_TCEI; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_TCEI_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_TCEI) >> TC_EVCTRL_TCEI_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_TCEI_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_TCEI; + tmp |= value << TC_EVCTRL_TCEI_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_TCEI_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_TCEI; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_TCEI_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_TCEI; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_OVFEO; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_OVFEO) >> TC_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_OVFEO; + tmp |= value << TC_EVCTRL_OVFEO_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_OVFEO; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_OVFEO; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_MCEO0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_MCEO0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_MCEO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_MCEO0) >> TC_EVCTRL_MCEO0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_MCEO0; + tmp |= value << TC_EVCTRL_MCEO0_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_MCEO0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_MCEO0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_MCEO0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_MCEO0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_MCEO1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_MCEO1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_MCEO1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_MCEO1) >> TC_EVCTRL_MCEO1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_MCEO1; + tmp |= value << TC_EVCTRL_MCEO1_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_MCEO1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_MCEO1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_MCEO1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_MCEO1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_EVACT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_EVACT(mask)) >> TC_EVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_tc_write_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_EVACT_Msk; + tmp |= TC_EVCTRL_EVACT(data); + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_EVACT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_EVACT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_EVACT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_EVACT_Msk) >> TC_EVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_tc_set_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.EVCTRL.reg; +} + +static inline void hri_tc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg |= TC_WAVE_WAVEGEN(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wave_reg_t hri_tc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.WAVE.reg; + tmp = (tmp & TC_WAVE_WAVEGEN(mask)) >> TC_WAVE_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.WAVE.reg; + tmp &= ~TC_WAVE_WAVEGEN_Msk; + tmp |= TC_WAVE_WAVEGEN(data); + ((Tc *)hw)->COUNT16.WAVE.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg &= ~TC_WAVE_WAVEGEN(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg ^= TC_WAVE_WAVEGEN(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wave_reg_t hri_tc_read_WAVE_WAVEGEN_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.WAVE.reg; + tmp = (tmp & TC_WAVE_WAVEGEN_Msk) >> TC_WAVE_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tc_set_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wave_reg_t hri_tc_get_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.WAVE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_WAVE_reg(const void *const hw, hri_tc_wave_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wave_reg_t hri_tc_read_WAVE_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.WAVE.reg; +} + +static inline void hri_tc_set_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg |= TC_DRVCTRL_INVEN0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_DRVCTRL_INVEN0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp = (tmp & TC_DRVCTRL_INVEN0) >> TC_DRVCTRL_INVEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp &= ~TC_DRVCTRL_INVEN0; + tmp |= value << TC_DRVCTRL_INVEN0_Pos; + ((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= TC_DRVCTRL_INVEN0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg |= TC_DRVCTRL_INVEN1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_DRVCTRL_INVEN1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp = (tmp & TC_DRVCTRL_INVEN1) >> TC_DRVCTRL_INVEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp &= ~TC_DRVCTRL_INVEN1; + tmp |= value << TC_DRVCTRL_INVEN1_Pos; + ((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= TC_DRVCTRL_INVEN1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_drvctrl_reg_t hri_tc_get_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_drvctrl_reg_t hri_tc_read_DRVCTRL_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.DRVCTRL.reg; +} + +static inline void hri_tc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg |= TC_DBGCTRL_DBGRUN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg; + tmp = (tmp & TC_DBGCTRL_DBGRUN) >> TC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg; + tmp &= ~TC_DBGCTRL_DBGRUN; + tmp |= value << TC_DBGCTRL_DBGRUN_Pos; + ((Tc *)hw)->COUNT16.DBGCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg &= ~TC_DBGCTRL_DBGRUN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg ^= TC_DBGCTRL_DBGRUN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_dbgctrl_reg_t hri_tc_get_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_dbgctrl_reg_t hri_tc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.DBGCTRL.reg; +} + +static inline void hri_tccount8_set_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg |= TC_COUNT8_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_count_reg_t hri_tccount8_get_COUNT_COUNT_bf(const void *const hw, + hri_tccount8_count_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp = (tmp & TC_COUNT8_COUNT_COUNT(mask)) >> TC_COUNT8_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount8_write_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp &= ~TC_COUNT8_COUNT_COUNT_Msk; + tmp |= TC_COUNT8_COUNT_COUNT(data); + ((Tc *)hw)->COUNT8.COUNT.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg &= ~TC_COUNT8_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg ^= TC_COUNT8_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_count_reg_t hri_tccount8_read_COUNT_COUNT_bf(const void *const hw) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp = (tmp & TC_COUNT8_COUNT_COUNT_Msk) >> TC_COUNT8_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount8_set_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_count_reg_t hri_tccount8_get_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_count_reg_t hri_tccount8_read_COUNT_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + return ((Tc *)hw)->COUNT8.COUNT.reg; +} + +static inline void hri_tccount16_set_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg |= TC_COUNT16_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_count_reg_t hri_tccount16_get_COUNT_COUNT_bf(const void *const hw, + hri_tccount16_count_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp = (tmp & TC_COUNT16_COUNT_COUNT(mask)) >> TC_COUNT16_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount16_write_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp &= ~TC_COUNT16_COUNT_COUNT_Msk; + tmp |= TC_COUNT16_COUNT_COUNT(data); + ((Tc *)hw)->COUNT16.COUNT.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg &= ~TC_COUNT16_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg ^= TC_COUNT16_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_count_reg_t hri_tccount16_read_COUNT_COUNT_bf(const void *const hw) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp = (tmp & TC_COUNT16_COUNT_COUNT_Msk) >> TC_COUNT16_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount16_set_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_count_reg_t hri_tccount16_get_COUNT_reg(const void *const hw, + hri_tccount16_count_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount16_write_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_count_reg_t hri_tccount16_read_COUNT_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + return ((Tc *)hw)->COUNT16.COUNT.reg; +} + +static inline void hri_tccount32_set_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg |= TC_COUNT32_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_count_reg_t hri_tccount32_get_COUNT_COUNT_bf(const void *const hw, + hri_tccount32_count_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp = (tmp & TC_COUNT32_COUNT_COUNT(mask)) >> TC_COUNT32_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount32_write_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp &= ~TC_COUNT32_COUNT_COUNT_Msk; + tmp |= TC_COUNT32_COUNT_COUNT(data); + ((Tc *)hw)->COUNT32.COUNT.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg &= ~TC_COUNT32_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg ^= TC_COUNT32_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_count_reg_t hri_tccount32_read_COUNT_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp = (tmp & TC_COUNT32_COUNT_COUNT_Msk) >> TC_COUNT32_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount32_set_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_count_reg_t hri_tccount32_get_COUNT_reg(const void *const hw, + hri_tccount32_count_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount32_write_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_count_reg_t hri_tccount32_read_COUNT_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + return ((Tc *)hw)->COUNT32.COUNT.reg; +} + +static inline void hri_tccount8_set_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg |= TC_COUNT8_PER_PER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_per_reg_t hri_tccount8_get_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp = (tmp & TC_COUNT8_PER_PER(mask)) >> TC_COUNT8_PER_PER_Pos; + return tmp; +} + +static inline void hri_tccount8_write_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp &= ~TC_COUNT8_PER_PER_Msk; + tmp |= TC_COUNT8_PER_PER(data); + ((Tc *)hw)->COUNT8.PER.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg &= ~TC_COUNT8_PER_PER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg ^= TC_COUNT8_PER_PER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_per_reg_t hri_tccount8_read_PER_PER_bf(const void *const hw) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp = (tmp & TC_COUNT8_PER_PER_Msk) >> TC_COUNT8_PER_PER_Pos; + return tmp; +} + +static inline void hri_tccount8_set_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_per_reg_t hri_tccount8_get_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_PER_reg(const void *const hw, hri_tccount8_per_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_per_reg_t hri_tccount8_read_PER_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + return ((Tc *)hw)->COUNT8.PER.reg; +} + +static inline void hri_tccount8_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg |= TC_COUNT8_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_cc_reg_t hri_tccount8_get_CC_CC_bf(const void *const hw, uint8_t index, + hri_tccount8_cc_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp = (tmp & TC_COUNT8_CC_CC(mask)) >> TC_COUNT8_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount8_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp &= ~TC_COUNT8_CC_CC_Msk; + tmp |= TC_COUNT8_CC_CC(data); + ((Tc *)hw)->COUNT8.CC[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg &= ~TC_COUNT8_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg ^= TC_COUNT8_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_cc_reg_t hri_tccount8_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp = (tmp & TC_COUNT8_CC_CC_Msk) >> TC_COUNT8_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount8_set_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_cc_reg_t hri_tccount8_get_CC_reg(const void *const hw, uint8_t index, + hri_tccount8_cc_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_cc_reg_t hri_tccount8_read_CC_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + return ((Tc *)hw)->COUNT8.CC[index].reg; +} + +static inline void hri_tccount16_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg |= TC_COUNT16_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_cc_reg_t hri_tccount16_get_CC_CC_bf(const void *const hw, uint8_t index, + hri_tccount16_cc_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp = (tmp & TC_COUNT16_CC_CC(mask)) >> TC_COUNT16_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount16_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp &= ~TC_COUNT16_CC_CC_Msk; + tmp |= TC_COUNT16_CC_CC(data); + ((Tc *)hw)->COUNT16.CC[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg &= ~TC_COUNT16_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg ^= TC_COUNT16_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_cc_reg_t hri_tccount16_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp = (tmp & TC_COUNT16_CC_CC_Msk) >> TC_COUNT16_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount16_set_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_cc_reg_t hri_tccount16_get_CC_reg(const void *const hw, uint8_t index, + hri_tccount16_cc_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount16_write_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_cc_reg_t hri_tccount16_read_CC_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + return ((Tc *)hw)->COUNT16.CC[index].reg; +} + +static inline void hri_tccount32_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg |= TC_COUNT32_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_cc_reg_t hri_tccount32_get_CC_CC_bf(const void *const hw, uint8_t index, + hri_tccount32_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp = (tmp & TC_COUNT32_CC_CC(mask)) >> TC_COUNT32_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount32_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp &= ~TC_COUNT32_CC_CC_Msk; + tmp |= TC_COUNT32_CC_CC(data); + ((Tc *)hw)->COUNT32.CC[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg &= ~TC_COUNT32_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg ^= TC_COUNT32_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_cc_reg_t hri_tccount32_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp = (tmp & TC_COUNT32_CC_CC_Msk) >> TC_COUNT32_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount32_set_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_cc_reg_t hri_tccount32_get_CC_reg(const void *const hw, uint8_t index, + hri_tccount32_cc_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount32_write_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_cc_reg_t hri_tccount32_read_CC_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + return ((Tc *)hw)->COUNT32.CC[index].reg; +} + +static inline void hri_tccount8_set_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg |= TC_COUNT8_PERBUF_PERBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_perbuf_reg_t hri_tccount8_get_PERBUF_PERBUF_bf(const void *const hw, + hri_tccount8_perbuf_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; + tmp = (tmp & TC_COUNT8_PERBUF_PERBUF(mask)) >> TC_COUNT8_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tccount8_write_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; + tmp &= ~TC_COUNT8_PERBUF_PERBUF_Msk; + tmp |= TC_COUNT8_PERBUF_PERBUF(data); + ((Tc *)hw)->COUNT8.PERBUF.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg &= ~TC_COUNT8_PERBUF_PERBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg ^= TC_COUNT8_PERBUF_PERBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_perbuf_reg_t hri_tccount8_read_PERBUF_PERBUF_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; + tmp = (tmp & TC_COUNT8_PERBUF_PERBUF_Msk) >> TC_COUNT8_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tccount8_set_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_perbuf_reg_t hri_tccount8_get_PERBUF_reg(const void *const hw, + hri_tccount8_perbuf_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_perbuf_reg_t hri_tccount8_read_PERBUF_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT8.PERBUF.reg; +} + +static inline void hri_tccount8_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg |= TC_COUNT8_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_ccbuf_reg_t hri_tccount8_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount8_ccbuf_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; + tmp = (tmp & TC_COUNT8_CCBUF_CCBUF(mask)) >> TC_COUNT8_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount8_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; + tmp &= ~TC_COUNT8_CCBUF_CCBUF_Msk; + tmp |= TC_COUNT8_CCBUF_CCBUF(data); + ((Tc *)hw)->COUNT8.CCBUF[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg &= ~TC_COUNT8_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg ^= TC_COUNT8_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_ccbuf_reg_t hri_tccount8_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; + tmp = (tmp & TC_COUNT8_CCBUF_CCBUF_Msk) >> TC_COUNT8_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount8_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_ccbuf_reg_t hri_tccount8_get_CCBUF_reg(const void *const hw, uint8_t index, + hri_tccount8_ccbuf_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_ccbuf_reg_t hri_tccount8_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT8.CCBUF[index].reg; +} + +static inline void hri_tccount16_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg |= TC_COUNT16_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_ccbuf_reg_t hri_tccount16_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; + tmp = (tmp & TC_COUNT16_CCBUF_CCBUF(mask)) >> TC_COUNT16_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount16_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; + tmp &= ~TC_COUNT16_CCBUF_CCBUF_Msk; + tmp |= TC_COUNT16_CCBUF_CCBUF(data); + ((Tc *)hw)->COUNT16.CCBUF[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg &= ~TC_COUNT16_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg ^= TC_COUNT16_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_ccbuf_reg_t hri_tccount16_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; + tmp = (tmp & TC_COUNT16_CCBUF_CCBUF_Msk) >> TC_COUNT16_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount16_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_ccbuf_reg_t hri_tccount16_get_CCBUF_reg(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount16_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_ccbuf_reg_t hri_tccount16_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT16.CCBUF[index].reg; +} + +static inline void hri_tccount32_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg |= TC_COUNT32_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_ccbuf_reg_t hri_tccount32_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; + tmp = (tmp & TC_COUNT32_CCBUF_CCBUF(mask)) >> TC_COUNT32_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount32_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; + tmp &= ~TC_COUNT32_CCBUF_CCBUF_Msk; + tmp |= TC_COUNT32_CCBUF_CCBUF(data); + ((Tc *)hw)->COUNT32.CCBUF[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg &= ~TC_COUNT32_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg ^= TC_COUNT32_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_ccbuf_reg_t hri_tccount32_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; + tmp = (tmp & TC_COUNT32_CCBUF_CCBUF_Msk) >> TC_COUNT32_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount32_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_ccbuf_reg_t hri_tccount32_get_CCBUF_reg(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount32_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_ccbuf_reg_t hri_tccount32_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT32.CCBUF[index].reg; +} + +static inline bool hri_tc_get_STATUS_STOP_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_STOP) >> TC_STATUS_STOP_Pos; +} + +static inline void hri_tc_clear_STATUS_STOP_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_STOP; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_STATUS_SLAVE_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_SLAVE) >> TC_STATUS_SLAVE_Pos; +} + +static inline void hri_tc_clear_STATUS_SLAVE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_SLAVE; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_STATUS_PERBUFV_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_PERBUFV) >> TC_STATUS_PERBUFV_Pos; +} + +static inline void hri_tc_clear_STATUS_PERBUFV_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_PERBUFV; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_STATUS_CCBUFV0_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_CCBUFV0) >> TC_STATUS_CCBUFV0_Pos; +} + +static inline void hri_tc_clear_STATUS_CCBUFV0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_CCBUFV0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_STATUS_CCBUFV1_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_CCBUFV1) >> TC_STATUS_CCBUFV1_Pos; +} + +static inline void hri_tc_clear_STATUS_CCBUFV1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_CCBUFV1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_status_reg_t hri_tc_get_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT16.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_clear_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_status_reg_t hri_tc_read_STATUS_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT16.STATUS.reg; +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_tc_set_PER_PER_bf(a, b) hri_tccount8_set_PER_PER_bf(a, b) +#define hri_tc_get_PER_PER_bf(a, b) hri_tccount8_get_PER_PER_bf(a, b) +#define hri_tc_write_PER_PER_bf(a, b) hri_tccount8_write_PER_PER_bf(a, b) +#define hri_tc_clear_PER_PER_bf(a, b) hri_tccount8_clear_PER_PER_bf(a, b) +#define hri_tc_toggle_PER_PER_bf(a, b) hri_tccount8_toggle_PER_PER_bf(a, b) +#define hri_tc_read_PER_PER_bf(a) hri_tccount8_read_PER_PER_bf(a) +#define hri_tc_set_PER_reg(a, b) hri_tccount8_set_PER_reg(a, b) +#define hri_tc_get_PER_reg(a, b) hri_tccount8_get_PER_reg(a, b) +#define hri_tc_write_PER_reg(a, b) hri_tccount8_write_PER_reg(a, b) +#define hri_tc_clear_PER_reg(a, b) hri_tccount8_clear_PER_reg(a, b) +#define hri_tc_toggle_PER_reg(a, b) hri_tccount8_toggle_PER_reg(a, b) +#define hri_tc_read_PER_reg(a) hri_tccount8_read_PER_reg(a) +#define hri_tc_set_PERBUF_PERBUF_bf(a, b) hri_tccount8_set_PERBUF_PERBUF_bf(a, b) +#define hri_tc_get_PERBUF_PERBUF_bf(a, b) hri_tccount8_get_PERBUF_PERBUF_bf(a, b) +#define hri_tc_write_PERBUF_PERBUF_bf(a, b) hri_tccount8_write_PERBUF_PERBUF_bf(a, b) +#define hri_tc_clear_PERBUF_PERBUF_bf(a, b) hri_tccount8_clear_PERBUF_PERBUF_bf(a, b) +#define hri_tc_toggle_PERBUF_PERBUF_bf(a, b) hri_tccount8_toggle_PERBUF_PERBUF_bf(a, b) +#define hri_tc_read_PERBUF_PERBUF_bf(a) hri_tccount8_read_PERBUF_PERBUF_bf(a) +#define hri_tc_set_PERBUF_reg(a, b) hri_tccount8_set_PERBUF_reg(a, b) +#define hri_tc_get_PERBUF_reg(a, b) hri_tccount8_get_PERBUF_reg(a, b) +#define hri_tc_write_PERBUF_reg(a, b) hri_tccount8_write_PERBUF_reg(a, b) +#define hri_tc_clear_PERBUF_reg(a, b) hri_tccount8_clear_PERBUF_reg(a, b) +#define hri_tc_toggle_PERBUF_reg(a, b) hri_tccount8_toggle_PERBUF_reg(a, b) +#define hri_tc_read_PERBUF_reg(a) hri_tccount8_read_PERBUF_reg(a) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_TC_L21_H_INCLUDED */ +#endif /* _SAML21_TC_COMPONENT_ */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_tcc_l21.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_tcc_l21.h new file mode 100644 index 00000000..b0e61b84 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_tcc_l21.h @@ -0,0 +1,9462 @@ +/** + * \file + * + * \brief SAM TCC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_TCC_COMPONENT_ +#ifndef _HRI_TCC_L21_H_INCLUDED_ +#define _HRI_TCC_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_TCC_CRITICAL_SECTIONS) +#define TCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define TCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define TCC_CRITICAL_SECTION_ENTER() +#define TCC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_tcc_patt_reg_t; +typedef uint16_t hri_tcc_pattbuf_reg_t; +typedef uint32_t hri_tcc_cc_reg_t; +typedef uint32_t hri_tcc_ccbuf_reg_t; +typedef uint32_t hri_tcc_count_reg_t; +typedef uint32_t hri_tcc_ctrla_reg_t; +typedef uint32_t hri_tcc_drvctrl_reg_t; +typedef uint32_t hri_tcc_evctrl_reg_t; +typedef uint32_t hri_tcc_fctrla_reg_t; +typedef uint32_t hri_tcc_fctrlb_reg_t; +typedef uint32_t hri_tcc_intenset_reg_t; +typedef uint32_t hri_tcc_intflag_reg_t; +typedef uint32_t hri_tcc_per_reg_t; +typedef uint32_t hri_tcc_perbuf_reg_t; +typedef uint32_t hri_tcc_status_reg_t; +typedef uint32_t hri_tcc_syncbusy_reg_t; +typedef uint32_t hri_tcc_wave_reg_t; +typedef uint32_t hri_tcc_wexctrl_reg_t; +typedef uint8_t hri_tcc_ctrlbset_reg_t; +typedef uint8_t hri_tcc_dbgctrl_reg_t; + +static inline void hri_tcc_wait_for_sync(const void *const hw, hri_tcc_syncbusy_reg_t reg) +{ + while (((Tcc *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_tcc_is_syncing(const void *const hw, hri_tcc_syncbusy_reg_t reg) +{ + return ((Tcc *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_tcc_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF; +} + +static inline bool hri_tcc_get_INTFLAG_TRG_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG; +} + +static inline bool hri_tcc_get_INTFLAG_CNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT; +} + +static inline bool hri_tcc_get_INTFLAG_ERR_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR; +} + +static inline bool hri_tcc_get_INTFLAG_UFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_UFS) >> TCC_INTFLAG_UFS_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_UFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_UFS; +} + +static inline bool hri_tcc_get_INTFLAG_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS; +} + +static inline bool hri_tcc_get_INTFLAG_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA; +} + +static inline bool hri_tcc_get_INTFLAG_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB; +} + +static inline bool hri_tcc_get_INTFLAG_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0; +} + +static inline bool hri_tcc_get_INTFLAG_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1; +} + +static inline bool hri_tcc_get_INTFLAG_MC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0; +} + +static inline bool hri_tcc_get_INTFLAG_MC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1; +} + +static inline bool hri_tcc_get_INTFLAG_MC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2; +} + +static inline bool hri_tcc_get_INTFLAG_MC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3; +} + +static inline bool hri_tcc_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos; +} + +static inline void hri_tcc_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF; +} + +static inline bool hri_tcc_get_interrupt_TRG_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos; +} + +static inline void hri_tcc_clear_interrupt_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG; +} + +static inline bool hri_tcc_get_interrupt_CNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos; +} + +static inline void hri_tcc_clear_interrupt_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT; +} + +static inline bool hri_tcc_get_interrupt_ERR_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos; +} + +static inline void hri_tcc_clear_interrupt_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR; +} + +static inline bool hri_tcc_get_interrupt_UFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_UFS) >> TCC_INTFLAG_UFS_Pos; +} + +static inline void hri_tcc_clear_interrupt_UFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_UFS; +} + +static inline bool hri_tcc_get_interrupt_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos; +} + +static inline void hri_tcc_clear_interrupt_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS; +} + +static inline bool hri_tcc_get_interrupt_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA; +} + +static inline bool hri_tcc_get_interrupt_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB; +} + +static inline bool hri_tcc_get_interrupt_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0; +} + +static inline bool hri_tcc_get_interrupt_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1; +} + +static inline bool hri_tcc_get_interrupt_MC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0; +} + +static inline bool hri_tcc_get_interrupt_MC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1; +} + +static inline bool hri_tcc_get_interrupt_MC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2; +} + +static inline bool hri_tcc_get_interrupt_MC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3; +} + +static inline hri_tcc_intflag_reg_t hri_tcc_get_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_intflag_reg_t hri_tcc_read_INTFLAG_reg(const void *const hw) +{ + return ((Tcc *)hw)->INTFLAG.reg; +} + +static inline void hri_tcc_clear_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask) +{ + ((Tcc *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_tcc_set_CTRLB_DIR_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR; +} + +static inline bool hri_tcc_get_CTRLB_DIR_bit(const void *const hw) +{ + return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_DIR) >> TCC_CTRLBSET_DIR_Pos; +} + +static inline void hri_tcc_write_CTRLB_DIR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR; + } else { + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR; + } +} + +static inline void hri_tcc_clear_CTRLB_DIR_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR; +} + +static inline void hri_tcc_set_CTRLB_LUPD_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD; +} + +static inline bool hri_tcc_get_CTRLB_LUPD_bit(const void *const hw) +{ + return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_LUPD) >> TCC_CTRLBSET_LUPD_Pos; +} + +static inline void hri_tcc_write_CTRLB_LUPD_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD; + } else { + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD; + } +} + +static inline void hri_tcc_clear_CTRLB_LUPD_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD; +} + +static inline void hri_tcc_set_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT; +} + +static inline bool hri_tcc_get_CTRLB_ONESHOT_bit(const void *const hw) +{ + return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_ONESHOT) >> TCC_CTRLBSET_ONESHOT_Pos; +} + +static inline void hri_tcc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT; + } else { + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT; + } +} + +static inline void hri_tcc_clear_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT; +} + +static inline void hri_tcc_set_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(mask); +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_IDXCMD(mask)) >> TCC_CTRLBSET_IDXCMD_Pos; + return tmp; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_IDXCMD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_IDXCMD_Msk) >> TCC_CTRLBSET_IDXCMD_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(data); + ((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_IDXCMD(data); +} + +static inline void hri_tcc_clear_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_IDXCMD(mask); +} + +static inline void hri_tcc_set_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(mask); +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_CMD(mask)) >> TCC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_CMD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_CMD_Msk) >> TCC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(data); + ((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_CMD(data); +} + +static inline void hri_tcc_clear_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_CMD(mask); +} + +static inline void hri_tcc_set_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBSET.reg = mask; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_reg(const void *const hw) +{ + return ((Tcc *)hw)->CTRLBSET.reg; +} + +static inline void hri_tcc_write_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t data) +{ + ((Tcc *)hw)->CTRLBSET.reg = data; + ((Tcc *)hw)->CTRLBCLR.reg = ~data; +} + +static inline void hri_tcc_clear_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBCLR.reg = mask; +} + +static inline void hri_tcc_set_INTEN_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF; +} + +static inline bool hri_tcc_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_OVF) >> TCC_INTENSET_OVF_Pos; +} + +static inline void hri_tcc_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF; + } +} + +static inline void hri_tcc_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF; +} + +static inline void hri_tcc_set_INTEN_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG; +} + +static inline bool hri_tcc_get_INTEN_TRG_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_TRG) >> TCC_INTENSET_TRG_Pos; +} + +static inline void hri_tcc_write_INTEN_TRG_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG; + } +} + +static inline void hri_tcc_clear_INTEN_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG; +} + +static inline void hri_tcc_set_INTEN_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT; +} + +static inline bool hri_tcc_get_INTEN_CNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_CNT) >> TCC_INTENSET_CNT_Pos; +} + +static inline void hri_tcc_write_INTEN_CNT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT; + } +} + +static inline void hri_tcc_clear_INTEN_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT; +} + +static inline void hri_tcc_set_INTEN_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR; +} + +static inline bool hri_tcc_get_INTEN_ERR_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_ERR) >> TCC_INTENSET_ERR_Pos; +} + +static inline void hri_tcc_write_INTEN_ERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR; + } +} + +static inline void hri_tcc_clear_INTEN_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR; +} + +static inline void hri_tcc_set_INTEN_UFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_UFS; +} + +static inline bool hri_tcc_get_INTEN_UFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_UFS) >> TCC_INTENSET_UFS_Pos; +} + +static inline void hri_tcc_write_INTEN_UFS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_UFS; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_UFS; + } +} + +static inline void hri_tcc_clear_INTEN_UFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_UFS; +} + +static inline void hri_tcc_set_INTEN_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS; +} + +static inline bool hri_tcc_get_INTEN_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_DFS) >> TCC_INTENSET_DFS_Pos; +} + +static inline void hri_tcc_write_INTEN_DFS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS; + } +} + +static inline void hri_tcc_clear_INTEN_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS; +} + +static inline void hri_tcc_set_INTEN_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA; +} + +static inline bool hri_tcc_get_INTEN_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTA) >> TCC_INTENSET_FAULTA_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULTA_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA; + } +} + +static inline void hri_tcc_clear_INTEN_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA; +} + +static inline void hri_tcc_set_INTEN_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB; +} + +static inline bool hri_tcc_get_INTEN_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTB) >> TCC_INTENSET_FAULTB_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULTB_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB; + } +} + +static inline void hri_tcc_clear_INTEN_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB; +} + +static inline void hri_tcc_set_INTEN_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0; +} + +static inline bool hri_tcc_get_INTEN_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT0) >> TCC_INTENSET_FAULT0_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULT0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0; + } +} + +static inline void hri_tcc_clear_INTEN_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0; +} + +static inline void hri_tcc_set_INTEN_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1; +} + +static inline bool hri_tcc_get_INTEN_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT1) >> TCC_INTENSET_FAULT1_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULT1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1; + } +} + +static inline void hri_tcc_clear_INTEN_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1; +} + +static inline void hri_tcc_set_INTEN_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0; +} + +static inline bool hri_tcc_get_INTEN_MC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC0) >> TCC_INTENSET_MC0_Pos; +} + +static inline void hri_tcc_write_INTEN_MC0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0; + } +} + +static inline void hri_tcc_clear_INTEN_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0; +} + +static inline void hri_tcc_set_INTEN_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1; +} + +static inline bool hri_tcc_get_INTEN_MC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC1) >> TCC_INTENSET_MC1_Pos; +} + +static inline void hri_tcc_write_INTEN_MC1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1; + } +} + +static inline void hri_tcc_clear_INTEN_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1; +} + +static inline void hri_tcc_set_INTEN_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2; +} + +static inline bool hri_tcc_get_INTEN_MC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC2) >> TCC_INTENSET_MC2_Pos; +} + +static inline void hri_tcc_write_INTEN_MC2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2; + } +} + +static inline void hri_tcc_clear_INTEN_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2; +} + +static inline void hri_tcc_set_INTEN_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3; +} + +static inline bool hri_tcc_get_INTEN_MC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC3) >> TCC_INTENSET_MC3_Pos; +} + +static inline void hri_tcc_write_INTEN_MC3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3; + } +} + +static inline void hri_tcc_clear_INTEN_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3; +} + +static inline void hri_tcc_set_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) +{ + ((Tcc *)hw)->INTENSET.reg = mask; +} + +static inline hri_tcc_intenset_reg_t hri_tcc_get_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_intenset_reg_t hri_tcc_read_INTEN_reg(const void *const hw) +{ + return ((Tcc *)hw)->INTENSET.reg; +} + +static inline void hri_tcc_write_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t data) +{ + ((Tcc *)hw)->INTENSET.reg = data; + ((Tcc *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_tcc_clear_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) +{ + ((Tcc *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_tcc_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_SWRST) >> TCC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_ENABLE) >> TCC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) >> TCC_SYNCBUSY_CTRLB_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_STATUS_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_STATUS) >> TCC_SYNCBUSY_STATUS_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_COUNT) >> TCC_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_PATT_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PATT) >> TCC_SYNCBUSY_PATT_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_WAVE_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_WAVE) >> TCC_SYNCBUSY_WAVE_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_PER_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PER) >> TCC_SYNCBUSY_PER_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC0) >> TCC_SYNCBUSY_CC0_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC1) >> TCC_SYNCBUSY_CC1_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC2) >> TCC_SYNCBUSY_CC2_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC3) >> TCC_SYNCBUSY_CC3_Pos; +} + +static inline hri_tcc_syncbusy_reg_t hri_tcc_get_SYNCBUSY_reg(const void *const hw, hri_tcc_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_syncbusy_reg_t hri_tcc_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Tcc *)hw)->SYNCBUSY.reg; +} + +static inline void hri_tcc_set_CTRLA_SWRST_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_SWRST; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_SWRST) >> TCC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_set_CTRLA_ENABLE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ENABLE; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_ENABLE) >> TCC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_ENABLE; + tmp |= value << TCC_CTRLA_ENABLE_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ENABLE; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ENABLE; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RUNSTDBY; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_RUNSTDBY) >> TCC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_RUNSTDBY; + tmp |= value << TCC_CTRLA_RUNSTDBY_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RUNSTDBY; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RUNSTDBY; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_ALOCK_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ALOCK; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_ALOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_ALOCK) >> TCC_CTRLA_ALOCK_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_ALOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_ALOCK; + tmp |= value << TCC_CTRLA_ALOCK_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_ALOCK_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ALOCK; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_ALOCK_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ALOCK; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_MSYNC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_MSYNC; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_MSYNC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_MSYNC) >> TCC_CTRLA_MSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_MSYNC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_MSYNC; + tmp |= value << TCC_CTRLA_MSYNC_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_MSYNC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_MSYNC; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_MSYNC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_MSYNC; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_DMAOS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_DMAOS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_DMAOS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_DMAOS) >> TCC_CTRLA_DMAOS_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_DMAOS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_DMAOS; + tmp |= value << TCC_CTRLA_DMAOS_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_DMAOS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_DMAOS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_DMAOS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_DMAOS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN0) >> TCC_CTRLA_CPTEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN0; + tmp |= value << TCC_CTRLA_CPTEN0_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN1) >> TCC_CTRLA_CPTEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN1; + tmp |= value << TCC_CTRLA_CPTEN1_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN2) >> TCC_CTRLA_CPTEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN2; + tmp |= value << TCC_CTRLA_CPTEN2_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN3) >> TCC_CTRLA_CPTEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN3; + tmp |= value << TCC_CTRLA_CPTEN3_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RESOLUTION(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_RESOLUTION(mask)) >> TCC_CTRLA_RESOLUTION_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_RESOLUTION_Msk; + tmp |= TCC_CTRLA_RESOLUTION(data); + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RESOLUTION(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RESOLUTION(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_RESOLUTION_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_RESOLUTION_Msk) >> TCC_CTRLA_RESOLUTION_Pos; + return tmp; +} + +static inline void hri_tcc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCALER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCALER(mask)) >> TCC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_PRESCALER_Msk; + tmp |= TCC_CTRLA_PRESCALER(data); + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCALER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCALER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCALER_Msk) >> TCC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tcc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCSYNC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCSYNC(mask)) >> TCC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_PRESCSYNC_Msk; + tmp |= TCC_CTRLA_PRESCSYNC(data); + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCSYNC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCSYNC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCSYNC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCSYNC_Msk) >> TCC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + return ((Tcc *)hw)->CTRLA.reg; +} + +static inline void hri_tcc_set_FCTRLA_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLA_KEEP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_KEEP) >> TCC_FCTRLA_KEEP_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLA_KEEP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_KEEP; + tmp |= value << TCC_FCTRLA_KEEP_Pos; + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLA_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLA_QUAL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_QUAL) >> TCC_FCTRLA_QUAL_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLA_QUAL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_QUAL; + tmp |= value << TCC_FCTRLA_QUAL_Pos; + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLA_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLA_RESTART_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_RESTART) >> TCC_FCTRLA_RESTART_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLA_RESTART_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_RESTART; + tmp |= value << TCC_FCTRLA_RESTART_Pos; + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLA_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLA_BLANKPRESC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANKPRESC) >> TCC_FCTRLA_BLANKPRESC_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLA_BLANKPRESC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_BLANKPRESC; + tmp |= value << TCC_FCTRLA_BLANKPRESC_Pos; + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_SRC(mask)) >> TCC_FCTRLA_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_SRC_Msk; + tmp |= TCC_FCTRLA_SRC(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_SRC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_SRC_Msk) >> TCC_FCTRLA_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANK(mask)) >> TCC_FCTRLA_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_BLANK_Msk; + tmp |= TCC_FCTRLA_BLANK(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANK_Msk) >> TCC_FCTRLA_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_HALT(mask)) >> TCC_FCTRLA_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_HALT_Msk; + tmp |= TCC_FCTRLA_HALT(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_HALT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_HALT_Msk) >> TCC_FCTRLA_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CHSEL(mask)) >> TCC_FCTRLA_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_CHSEL_Msk; + tmp |= TCC_FCTRLA_CHSEL(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CHSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CHSEL_Msk) >> TCC_FCTRLA_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CAPTURE(mask)) >> TCC_FCTRLA_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_CAPTURE_Msk; + tmp |= TCC_FCTRLA_CAPTURE(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CAPTURE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CAPTURE_Msk) >> TCC_FCTRLA_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANKVAL(mask)) >> TCC_FCTRLA_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_BLANKVAL_Msk; + tmp |= TCC_FCTRLA_BLANKVAL(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANKVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANKVAL_Msk) >> TCC_FCTRLA_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_FILTERVAL(mask)) >> TCC_FCTRLA_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_FILTERVAL_Msk; + tmp |= TCC_FCTRLA_FILTERVAL(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_FILTERVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_FILTERVAL_Msk) >> TCC_FCTRLA_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_reg(const void *const hw) +{ + return ((Tcc *)hw)->FCTRLA.reg; +} + +static inline void hri_tcc_set_FCTRLB_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLB_KEEP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_KEEP) >> TCC_FCTRLB_KEEP_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLB_KEEP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_KEEP; + tmp |= value << TCC_FCTRLB_KEEP_Pos; + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLB_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLB_QUAL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_QUAL) >> TCC_FCTRLB_QUAL_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLB_QUAL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_QUAL; + tmp |= value << TCC_FCTRLB_QUAL_Pos; + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLB_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLB_RESTART_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_RESTART) >> TCC_FCTRLB_RESTART_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLB_RESTART_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_RESTART; + tmp |= value << TCC_FCTRLB_RESTART_Pos; + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLB_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLB_BLANKPRESC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANKPRESC) >> TCC_FCTRLB_BLANKPRESC_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLB_BLANKPRESC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_BLANKPRESC; + tmp |= value << TCC_FCTRLB_BLANKPRESC_Pos; + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_SRC(mask)) >> TCC_FCTRLB_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_SRC_Msk; + tmp |= TCC_FCTRLB_SRC(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_SRC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_SRC_Msk) >> TCC_FCTRLB_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANK(mask)) >> TCC_FCTRLB_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_BLANK_Msk; + tmp |= TCC_FCTRLB_BLANK(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANK_Msk) >> TCC_FCTRLB_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_HALT(mask)) >> TCC_FCTRLB_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_HALT_Msk; + tmp |= TCC_FCTRLB_HALT(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_HALT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_HALT_Msk) >> TCC_FCTRLB_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CHSEL(mask)) >> TCC_FCTRLB_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_CHSEL_Msk; + tmp |= TCC_FCTRLB_CHSEL(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CHSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CHSEL_Msk) >> TCC_FCTRLB_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CAPTURE(mask)) >> TCC_FCTRLB_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_CAPTURE_Msk; + tmp |= TCC_FCTRLB_CAPTURE(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CAPTURE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CAPTURE_Msk) >> TCC_FCTRLB_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANKVAL(mask)) >> TCC_FCTRLB_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_BLANKVAL_Msk; + tmp |= TCC_FCTRLB_BLANKVAL(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANKVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANKVAL_Msk) >> TCC_FCTRLB_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_FILTERVAL(mask)) >> TCC_FCTRLB_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_FILTERVAL_Msk; + tmp |= TCC_FCTRLB_FILTERVAL(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_FILTERVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_FILTERVAL_Msk) >> TCC_FCTRLB_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_reg(const void *const hw) +{ + return ((Tcc *)hw)->FCTRLB.reg; +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN0) >> TCC_WEXCTRL_DTIEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN0; + tmp |= value << TCC_WEXCTRL_DTIEN0_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN1) >> TCC_WEXCTRL_DTIEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN1; + tmp |= value << TCC_WEXCTRL_DTIEN1_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN2) >> TCC_WEXCTRL_DTIEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN2; + tmp |= value << TCC_WEXCTRL_DTIEN2_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN3) >> TCC_WEXCTRL_DTIEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN3; + tmp |= value << TCC_WEXCTRL_DTIEN3_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_OTMX(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_OTMX(mask)) >> TCC_WEXCTRL_OTMX_Pos; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_OTMX_Msk; + tmp |= TCC_WEXCTRL_OTMX(data); + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_OTMX(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_OTMX(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_OTMX_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_OTMX_Msk) >> TCC_WEXCTRL_OTMX_Pos; + return tmp; +} + +static inline void hri_tcc_set_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTLS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTLS(mask)) >> TCC_WEXCTRL_DTLS_Pos; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTLS_Msk; + tmp |= TCC_WEXCTRL_DTLS(data); + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTLS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTLS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTLS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTLS_Msk) >> TCC_WEXCTRL_DTLS_Pos; + return tmp; +} + +static inline void hri_tcc_set_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTHS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTHS(mask)) >> TCC_WEXCTRL_DTHS_Pos; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTHS_Msk; + tmp |= TCC_WEXCTRL_DTHS(data); + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTHS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTHS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTHS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTHS_Msk) >> TCC_WEXCTRL_DTHS_Pos; + return tmp; +} + +static inline void hri_tcc_set_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->WEXCTRL.reg; +} + +static inline void hri_tcc_set_DRVCTRL_NRE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE0) >> TCC_DRVCTRL_NRE0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE0; + tmp |= value << TCC_DRVCTRL_NRE0_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE1) >> TCC_DRVCTRL_NRE1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE1; + tmp |= value << TCC_DRVCTRL_NRE1_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE2) >> TCC_DRVCTRL_NRE2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE2; + tmp |= value << TCC_DRVCTRL_NRE2_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE3) >> TCC_DRVCTRL_NRE3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE3; + tmp |= value << TCC_DRVCTRL_NRE3_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE4) >> TCC_DRVCTRL_NRE4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE4; + tmp |= value << TCC_DRVCTRL_NRE4_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE5) >> TCC_DRVCTRL_NRE5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE5; + tmp |= value << TCC_DRVCTRL_NRE5_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE6) >> TCC_DRVCTRL_NRE6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE6; + tmp |= value << TCC_DRVCTRL_NRE6_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE7) >> TCC_DRVCTRL_NRE7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE7; + tmp |= value << TCC_DRVCTRL_NRE7_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV0) >> TCC_DRVCTRL_NRV0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV0; + tmp |= value << TCC_DRVCTRL_NRV0_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV1) >> TCC_DRVCTRL_NRV1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV1; + tmp |= value << TCC_DRVCTRL_NRV1_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV2) >> TCC_DRVCTRL_NRV2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV2; + tmp |= value << TCC_DRVCTRL_NRV2_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV3) >> TCC_DRVCTRL_NRV3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV3; + tmp |= value << TCC_DRVCTRL_NRV3_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV4) >> TCC_DRVCTRL_NRV4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV4; + tmp |= value << TCC_DRVCTRL_NRV4_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV5) >> TCC_DRVCTRL_NRV5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV5; + tmp |= value << TCC_DRVCTRL_NRV5_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV6) >> TCC_DRVCTRL_NRV6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV6; + tmp |= value << TCC_DRVCTRL_NRV6_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV7) >> TCC_DRVCTRL_NRV7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV7; + tmp |= value << TCC_DRVCTRL_NRV7_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN0) >> TCC_DRVCTRL_INVEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN0; + tmp |= value << TCC_DRVCTRL_INVEN0_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN1) >> TCC_DRVCTRL_INVEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN1; + tmp |= value << TCC_DRVCTRL_INVEN1_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN2) >> TCC_DRVCTRL_INVEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN2; + tmp |= value << TCC_DRVCTRL_INVEN2_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN3) >> TCC_DRVCTRL_INVEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN3; + tmp |= value << TCC_DRVCTRL_INVEN3_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN4) >> TCC_DRVCTRL_INVEN4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN4; + tmp |= value << TCC_DRVCTRL_INVEN4_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN5) >> TCC_DRVCTRL_INVEN5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN5; + tmp |= value << TCC_DRVCTRL_INVEN5_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN6) >> TCC_DRVCTRL_INVEN6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN6; + tmp |= value << TCC_DRVCTRL_INVEN6_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN7) >> TCC_DRVCTRL_INVEN7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN7; + tmp |= value << TCC_DRVCTRL_INVEN7_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL0(mask)) >> TCC_DRVCTRL_FILTERVAL0_Pos; + return tmp; +} + +static inline void hri_tcc_write_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_FILTERVAL0_Msk; + tmp |= TCC_DRVCTRL_FILTERVAL0(data); + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL0_Msk) >> TCC_DRVCTRL_FILTERVAL0_Pos; + return tmp; +} + +static inline void hri_tcc_set_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL1(mask)) >> TCC_DRVCTRL_FILTERVAL1_Pos; + return tmp; +} + +static inline void hri_tcc_write_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_FILTERVAL1_Msk; + tmp |= TCC_DRVCTRL_FILTERVAL1(data); + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL1_Msk) >> TCC_DRVCTRL_FILTERVAL1_Pos; + return tmp; +} + +static inline void hri_tcc_set_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->DRVCTRL.reg; +} + +static inline void hri_tcc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_DBGRUN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp = (tmp & TCC_DBGCTRL_DBGRUN) >> TCC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp &= ~TCC_DBGCTRL_DBGRUN; + tmp |= value << TCC_DBGCTRL_DBGRUN_Pos; + ((Tcc *)hw)->DBGCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_DBGRUN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_DBGRUN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DBGCTRL_FDDBD_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_FDDBD; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DBGCTRL_FDDBD_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp = (tmp & TCC_DBGCTRL_FDDBD) >> TCC_DBGCTRL_FDDBD_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DBGCTRL_FDDBD_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp &= ~TCC_DBGCTRL_FDDBD; + tmp |= value << TCC_DBGCTRL_FDDBD_Pos; + ((Tcc *)hw)->DBGCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DBGCTRL_FDDBD_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_FDDBD; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DBGCTRL_FDDBD_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_FDDBD; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_dbgctrl_reg_t hri_tcc_get_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_dbgctrl_reg_t hri_tcc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->DBGCTRL.reg; +} + +static inline void hri_tcc_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_OVFEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_OVFEO) >> TCC_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_OVFEO; + tmp |= value << TCC_EVCTRL_OVFEO_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_OVFEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_OVFEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TRGEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TRGEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TRGEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TRGEO) >> TCC_EVCTRL_TRGEO_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TRGEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TRGEO; + tmp |= value << TCC_EVCTRL_TRGEO_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TRGEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TRGEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TRGEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TRGEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_CNTEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_CNTEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_CNTEO) >> TCC_EVCTRL_CNTEO_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_CNTEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_CNTEO; + tmp |= value << TCC_EVCTRL_CNTEO_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_CNTEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_CNTEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCINV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCINV0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCINV0) >> TCC_EVCTRL_TCINV0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCINV0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCINV0; + tmp |= value << TCC_EVCTRL_TCINV0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCINV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCINV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCINV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCINV1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCINV1) >> TCC_EVCTRL_TCINV1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCINV1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCINV1; + tmp |= value << TCC_EVCTRL_TCINV1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCINV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCINV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCEI0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCEI0) >> TCC_EVCTRL_TCEI0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCEI0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCEI0; + tmp |= value << TCC_EVCTRL_TCEI0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCEI1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCEI1) >> TCC_EVCTRL_TCEI1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCEI1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCEI1; + tmp |= value << TCC_EVCTRL_TCEI1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI0) >> TCC_EVCTRL_MCEI0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI0; + tmp |= value << TCC_EVCTRL_MCEI0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI1) >> TCC_EVCTRL_MCEI1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI1; + tmp |= value << TCC_EVCTRL_MCEI1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI2) >> TCC_EVCTRL_MCEI2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI2; + tmp |= value << TCC_EVCTRL_MCEI2_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI3) >> TCC_EVCTRL_MCEI3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI3; + tmp |= value << TCC_EVCTRL_MCEI3_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO0) >> TCC_EVCTRL_MCEO0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO0; + tmp |= value << TCC_EVCTRL_MCEO0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO1) >> TCC_EVCTRL_MCEO1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO1; + tmp |= value << TCC_EVCTRL_MCEO1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO2) >> TCC_EVCTRL_MCEO2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO2; + tmp |= value << TCC_EVCTRL_MCEO2_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO3) >> TCC_EVCTRL_MCEO3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO3; + tmp |= value << TCC_EVCTRL_MCEO3_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT0(mask)) >> TCC_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_EVACT0_Msk; + tmp |= TCC_EVCTRL_EVACT0(data); + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT0_Msk) >> TCC_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_tcc_set_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT1(mask)) >> TCC_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_EVACT1_Msk; + tmp |= TCC_EVCTRL_EVACT1(data); + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT1_Msk) >> TCC_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_tcc_set_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_CNTSEL(mask)) >> TCC_EVCTRL_CNTSEL_Pos; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_CNTSEL_Msk; + tmp |= TCC_EVCTRL_CNTSEL(data); + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_CNTSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_CNTSEL_Msk) >> TCC_EVCTRL_CNTSEL_Pos; + return tmp; +} + +static inline void hri_tcc_set_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->EVCTRL.reg; +} + +static inline void hri_tcc_set_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_COUNT_Msk; + tmp |= TCC_COUNT_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH6_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_COUNT_Msk; + tmp |= TCC_COUNT_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH5_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_COUNT_Msk; + tmp |= TCC_COUNT_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH4_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_COUNT_Msk; + tmp |= TCC_COUNT_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_COUNT_reg(const void *const hw, hri_tcc_count_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + return ((Tcc *)hw)->COUNT.reg; +} + +static inline void hri_tcc_set_PATT_PGE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE0) >> TCC_PATT_PGE0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE0; + tmp |= value << TCC_PATT_PGE0_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE1) >> TCC_PATT_PGE1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE1; + tmp |= value << TCC_PATT_PGE1_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE2) >> TCC_PATT_PGE2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE2; + tmp |= value << TCC_PATT_PGE2_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE3) >> TCC_PATT_PGE3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE3; + tmp |= value << TCC_PATT_PGE3_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE4) >> TCC_PATT_PGE4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE4; + tmp |= value << TCC_PATT_PGE4_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE5) >> TCC_PATT_PGE5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE5; + tmp |= value << TCC_PATT_PGE5_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE6) >> TCC_PATT_PGE6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE6; + tmp |= value << TCC_PATT_PGE6_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE7) >> TCC_PATT_PGE7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE7; + tmp |= value << TCC_PATT_PGE7_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV0) >> TCC_PATT_PGV0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV0; + tmp |= value << TCC_PATT_PGV0_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV1) >> TCC_PATT_PGV1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV1; + tmp |= value << TCC_PATT_PGV1_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV2) >> TCC_PATT_PGV2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV2; + tmp |= value << TCC_PATT_PGV2_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV3) >> TCC_PATT_PGV3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV3; + tmp |= value << TCC_PATT_PGV3_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV4) >> TCC_PATT_PGV4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV4; + tmp |= value << TCC_PATT_PGV4_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV5) >> TCC_PATT_PGV5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV5; + tmp |= value << TCC_PATT_PGV5_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV6) >> TCC_PATT_PGV6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV6; + tmp |= value << TCC_PATT_PGV6_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV7) >> TCC_PATT_PGV7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV7; + tmp |= value << TCC_PATT_PGV7_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_patt_reg_t hri_tcc_get_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + uint16_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PATT_reg(const void *const hw, hri_tcc_patt_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_patt_reg_t hri_tcc_read_PATT_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + return ((Tcc *)hw)->PATT.reg; +} + +static inline void hri_tcc_set_WAVE_CIPEREN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CIPEREN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CIPEREN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CIPEREN) >> TCC_WAVE_CIPEREN_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CIPEREN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CIPEREN; + tmp |= value << TCC_WAVE_CIPEREN_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CIPEREN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CIPEREN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CIPEREN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CIPEREN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN0) >> TCC_WAVE_CICCEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN0; + tmp |= value << TCC_WAVE_CICCEN0_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN1) >> TCC_WAVE_CICCEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN1; + tmp |= value << TCC_WAVE_CICCEN1_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN2) >> TCC_WAVE_CICCEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN2; + tmp |= value << TCC_WAVE_CICCEN2_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN3) >> TCC_WAVE_CICCEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN3; + tmp |= value << TCC_WAVE_CICCEN3_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL0) >> TCC_WAVE_POL0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL0; + tmp |= value << TCC_WAVE_POL0_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL1) >> TCC_WAVE_POL1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL1; + tmp |= value << TCC_WAVE_POL1_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL2) >> TCC_WAVE_POL2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL2; + tmp |= value << TCC_WAVE_POL2_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL3) >> TCC_WAVE_POL3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL3; + tmp |= value << TCC_WAVE_POL3_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP0) >> TCC_WAVE_SWAP0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP0; + tmp |= value << TCC_WAVE_SWAP0_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP1) >> TCC_WAVE_SWAP1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP1; + tmp |= value << TCC_WAVE_SWAP1_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP2) >> TCC_WAVE_SWAP2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP2; + tmp |= value << TCC_WAVE_SWAP2_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP3) >> TCC_WAVE_SWAP3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP3; + tmp |= value << TCC_WAVE_SWAP3_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_WAVEGEN(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_WAVEGEN(mask)) >> TCC_WAVE_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tcc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_WAVEGEN_Msk; + tmp |= TCC_WAVE_WAVEGEN(data); + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_WAVEGEN(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_WAVEGEN(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_WAVEGEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_WAVEGEN_Msk) >> TCC_WAVE_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tcc_set_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_RAMP(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_RAMP(mask)) >> TCC_WAVE_RAMP_Pos; + return tmp; +} + +static inline void hri_tcc_write_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_RAMP_Msk; + tmp |= TCC_WAVE_RAMP(data); + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_RAMP(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_RAMP(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_RAMP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_RAMP_Msk) >> TCC_WAVE_RAMP_Pos; + return tmp; +} + +static inline void hri_tcc_set_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + return ((Tcc *)hw)->WAVE.reg; +} + +static inline void hri_tcc_set_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH4_DITHER(mask)) >> TCC_PER_DITH4_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_DITH4_DITHER_Msk; + tmp |= TCC_PER_DITH4_DITHER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_DITHER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH4_DITHER_Msk) >> TCC_PER_DITH4_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH5_DITHER(mask)) >> TCC_PER_DITH5_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_DITH5_DITHER_Msk; + tmp |= TCC_PER_DITH5_DITHER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_DITHER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH5_DITHER_Msk) >> TCC_PER_DITH5_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH6_DITHER(mask)) >> TCC_PER_DITH6_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_DITH6_DITHER_Msk; + tmp |= TCC_PER_DITH6_DITHER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_DITHER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH6_DITHER_Msk) >> TCC_PER_DITH6_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_PER_Msk; + tmp |= TCC_PER_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_PER_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_PER_Msk; + tmp |= TCC_PER_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_PER_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_PER_Msk; + tmp |= TCC_PER_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_PER_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_PER_Msk; + tmp |= TCC_PER_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_PER_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PER_reg(const void *const hw, hri_tcc_per_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + return ((Tcc *)hw)->PER.reg; +} + +static inline void hri_tcc_set_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, + hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH4_DITHER(mask)) >> TCC_CC_DITH4_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_DITH4_DITHER_Msk; + tmp |= TCC_CC_DITH4_DITHER(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH4_DITHER_Msk) >> TCC_CC_DITH4_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, + hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH5_DITHER(mask)) >> TCC_CC_DITH5_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_DITH5_DITHER_Msk; + tmp |= TCC_CC_DITH5_DITHER(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH5_DITHER_Msk) >> TCC_CC_DITH5_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, + hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH6_DITHER(mask)) >> TCC_CC_DITH6_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_DITH6_DITHER_Msk; + tmp |= TCC_CC_DITH6_DITHER(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH6_DITHER_Msk) >> TCC_CC_DITH6_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_CC_Msk; + tmp |= TCC_CC_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_CC_Msk; + tmp |= TCC_CC_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_CC_Msk; + tmp |= TCC_CC_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_CC_Msk; + tmp |= TCC_CC_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_reg(const void *const hw, uint8_t index) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + return ((Tcc *)hw)->CC[index].reg; +} + +static inline void hri_tcc_set_PATTBUF_PGEB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB0) >> TCC_PATTBUF_PGEB0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB0; + tmp |= value << TCC_PATTBUF_PGEB0_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB1) >> TCC_PATTBUF_PGEB1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB1; + tmp |= value << TCC_PATTBUF_PGEB1_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB2) >> TCC_PATTBUF_PGEB2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB2; + tmp |= value << TCC_PATTBUF_PGEB2_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB3) >> TCC_PATTBUF_PGEB3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB3; + tmp |= value << TCC_PATTBUF_PGEB3_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB4) >> TCC_PATTBUF_PGEB4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB4; + tmp |= value << TCC_PATTBUF_PGEB4_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB5) >> TCC_PATTBUF_PGEB5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB5; + tmp |= value << TCC_PATTBUF_PGEB5_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB6) >> TCC_PATTBUF_PGEB6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB6; + tmp |= value << TCC_PATTBUF_PGEB6_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB7) >> TCC_PATTBUF_PGEB7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB7; + tmp |= value << TCC_PATTBUF_PGEB7_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB0) >> TCC_PATTBUF_PGVB0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB0; + tmp |= value << TCC_PATTBUF_PGVB0_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB1) >> TCC_PATTBUF_PGVB1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB1; + tmp |= value << TCC_PATTBUF_PGVB1_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB2) >> TCC_PATTBUF_PGVB2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB2; + tmp |= value << TCC_PATTBUF_PGVB2_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB3) >> TCC_PATTBUF_PGVB3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB3; + tmp |= value << TCC_PATTBUF_PGVB3_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB4) >> TCC_PATTBUF_PGVB4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB4; + tmp |= value << TCC_PATTBUF_PGVB4_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB5) >> TCC_PATTBUF_PGVB5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB5; + tmp |= value << TCC_PATTBUF_PGVB5_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB6) >> TCC_PATTBUF_PGVB6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB6; + tmp |= value << TCC_PATTBUF_PGVB6_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB7) >> TCC_PATTBUF_PGVB7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB7; + tmp |= value << TCC_PATTBUF_PGVB7_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_pattbuf_reg_t hri_tcc_get_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_pattbuf_reg_t hri_tcc_read_PATTBUF_reg(const void *const hw) +{ + return ((Tcc *)hw)->PATTBUF.reg; +} + +static inline void hri_tcc_set_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, + hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH4_DITHERBUF(mask)) >> TCC_PERBUF_DITH4_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_DITH4_DITHERBUF_Msk; + tmp |= TCC_PERBUF_DITH4_DITHERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH4_DITHERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH4_DITHERBUF_Msk) >> TCC_PERBUF_DITH4_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, + hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH5_DITHERBUF(mask)) >> TCC_PERBUF_DITH5_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_DITH5_DITHERBUF_Msk; + tmp |= TCC_PERBUF_DITH5_DITHERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH5_DITHERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH5_DITHERBUF_Msk) >> TCC_PERBUF_DITH5_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, + hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH6_DITHERBUF(mask)) >> TCC_PERBUF_DITH6_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_DITH6_DITHERBUF_Msk; + tmp |= TCC_PERBUF_DITH6_DITHERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH6_DITHERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH6_DITHERBUF_Msk) >> TCC_PERBUF_DITH6_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_PERBUF_Msk; + tmp |= TCC_PERBUF_PERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH6_PERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_PERBUF_Msk; + tmp |= TCC_PERBUF_PERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH5_PERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_PERBUF_Msk; + tmp |= TCC_PERBUF_PERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH4_PERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_PERBUF_Msk; + tmp |= TCC_PERBUF_PERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_PERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_reg(const void *const hw) +{ + return ((Tcc *)hw)->PERBUF.reg; +} + +static inline void hri_tcc_set_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_CCBUF_Msk; + tmp |= TCC_CCBUF_CCBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH5_DITHERBUF(mask)) >> TCC_CCBUF_DITH5_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_DITH5_DITHERBUF_Msk; + tmp |= TCC_CCBUF_DITH5_DITHERBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH5_DITHERBUF_Msk) >> TCC_CCBUF_DITH5_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH6_DITHERBUF(mask)) >> TCC_CCBUF_DITH6_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_DITH6_DITHERBUF_Msk; + tmp |= TCC_CCBUF_DITH6_DITHERBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH6_DITHERBUF_Msk) >> TCC_CCBUF_DITH6_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_CCBUF_Msk; + tmp |= TCC_CCBUF_CCBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_CCBUF_Msk; + tmp |= TCC_CCBUF_CCBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH4_DITHERBUF(mask)) >> TCC_CCBUF_DITH4_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_DITH4_DITHERBUF_Msk; + tmp |= TCC_CCBUF_DITH4_DITHERBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH4_DITHERBUF_Msk) >> TCC_CCBUF_DITH4_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_CCBUF_Msk; + tmp |= TCC_CCBUF_CCBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + return ((Tcc *)hw)->CCBUF[index].reg; +} + +static inline bool hri_tcc_get_STATUS_STOP_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_STOP) >> TCC_STATUS_STOP_Pos; +} + +static inline void hri_tcc_clear_STATUS_STOP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_STOP; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_IDX_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_IDX) >> TCC_STATUS_IDX_Pos; +} + +static inline void hri_tcc_clear_STATUS_IDX_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_IDX; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_UFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_UFS) >> TCC_STATUS_UFS_Pos; +} + +static inline void hri_tcc_clear_STATUS_UFS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_UFS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_DFS) >> TCC_STATUS_DFS_Pos; +} + +static inline void hri_tcc_clear_STATUS_DFS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_DFS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_SLAVE_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_SLAVE) >> TCC_STATUS_SLAVE_Pos; +} + +static inline void hri_tcc_clear_STATUS_SLAVE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_SLAVE; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_PATTBUFV_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PATTBUFV) >> TCC_STATUS_PATTBUFV_Pos; +} + +static inline void hri_tcc_clear_STATUS_PATTBUFV_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_PATTBUFV; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_PERBUFV_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PERBUFV) >> TCC_STATUS_PERBUFV_Pos; +} + +static inline void hri_tcc_clear_STATUS_PERBUFV_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_PERBUFV; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTAIN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTAIN) >> TCC_STATUS_FAULTAIN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTAIN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTAIN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTBIN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTBIN) >> TCC_STATUS_FAULTBIN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTBIN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTBIN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT0IN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0IN) >> TCC_STATUS_FAULT0IN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT0IN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0IN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT1IN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1IN) >> TCC_STATUS_FAULT1IN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT1IN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1IN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTA) >> TCC_STATUS_FAULTA_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTA_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTA; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTB) >> TCC_STATUS_FAULTB_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTB_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTB; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0) >> TCC_STATUS_FAULT0_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1) >> TCC_STATUS_FAULT1_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV0_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV0) >> TCC_STATUS_CCBUFV0_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV1_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV1) >> TCC_STATUS_CCBUFV1_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV2_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV2) >> TCC_STATUS_CCBUFV2_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV3_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV3) >> TCC_STATUS_CCBUFV3_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP0_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP0) >> TCC_STATUS_CMP0_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP1_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP1) >> TCC_STATUS_CMP1_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP2_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP2) >> TCC_STATUS_CMP2_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP3_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP3) >> TCC_STATUS_CMP3_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_status_reg_t hri_tcc_get_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_clear_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_status_reg_t hri_tcc_read_STATUS_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + return ((Tcc *)hw)->STATUS.reg; +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_tcc_set_COUNT_DITH4_reg(a, b) hri_tcc_set_COUNT_reg(a, b) +#define hri_tcc_get_COUNT_DITH4_reg(a, b) hri_tcc_get_COUNT_reg(a, b) +#define hri_tcc_write_COUNT_DITH4_reg(a, b) hri_tcc_write_COUNT_reg(a, b) +#define hri_tcc_clear_COUNT_DITH4_reg(a, b) hri_tcc_clear_COUNT_reg(a, b) +#define hri_tcc_toggle_COUNT_DITH4_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b) +#define hri_tcc_read_COUNT_DITH4_reg(a) hri_tcc_read_COUNT_reg(a) +#define hri_tcc_set_COUNT_DITH5_reg(a, b) hri_tcc_set_COUNT_reg(a, b) +#define hri_tcc_get_COUNT_DITH5_reg(a, b) hri_tcc_get_COUNT_reg(a, b) +#define hri_tcc_write_COUNT_DITH5_reg(a, b) hri_tcc_write_COUNT_reg(a, b) +#define hri_tcc_clear_COUNT_DITH5_reg(a, b) hri_tcc_clear_COUNT_reg(a, b) +#define hri_tcc_toggle_COUNT_DITH5_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b) +#define hri_tcc_read_COUNT_DITH5_reg(a) hri_tcc_read_COUNT_reg(a) +#define hri_tcc_set_COUNT_DITH6_reg(a, b) hri_tcc_set_COUNT_reg(a, b) +#define hri_tcc_get_COUNT_DITH6_reg(a, b) hri_tcc_get_COUNT_reg(a, b) +#define hri_tcc_write_COUNT_DITH6_reg(a, b) hri_tcc_write_COUNT_reg(a, b) +#define hri_tcc_clear_COUNT_DITH6_reg(a, b) hri_tcc_clear_COUNT_reg(a, b) +#define hri_tcc_toggle_COUNT_DITH6_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b) +#define hri_tcc_read_COUNT_DITH6_reg(a) hri_tcc_read_COUNT_reg(a) +#define hri_tcc_set_PER_DITH4_reg(a, b) hri_tcc_set_PER_reg(a, b) +#define hri_tcc_get_PER_DITH4_reg(a, b) hri_tcc_get_PER_reg(a, b) +#define hri_tcc_write_PER_DITH4_reg(a, b) hri_tcc_write_PER_reg(a, b) +#define hri_tcc_clear_PER_DITH4_reg(a, b) hri_tcc_clear_PER_reg(a, b) +#define hri_tcc_toggle_PER_DITH4_reg(a, b) hri_tcc_toggle_PER_reg(a, b) +#define hri_tcc_read_PER_DITH4_reg(a) hri_tcc_read_PER_reg(a) +#define hri_tcc_set_PER_DITH5_reg(a, b) hri_tcc_set_PER_reg(a, b) +#define hri_tcc_get_PER_DITH5_reg(a, b) hri_tcc_get_PER_reg(a, b) +#define hri_tcc_write_PER_DITH5_reg(a, b) hri_tcc_write_PER_reg(a, b) +#define hri_tcc_clear_PER_DITH5_reg(a, b) hri_tcc_clear_PER_reg(a, b) +#define hri_tcc_toggle_PER_DITH5_reg(a, b) hri_tcc_toggle_PER_reg(a, b) +#define hri_tcc_read_PER_DITH5_reg(a) hri_tcc_read_PER_reg(a) +#define hri_tcc_set_PER_DITH6_reg(a, b) hri_tcc_set_PER_reg(a, b) +#define hri_tcc_get_PER_DITH6_reg(a, b) hri_tcc_get_PER_reg(a, b) +#define hri_tcc_write_PER_DITH6_reg(a, b) hri_tcc_write_PER_reg(a, b) +#define hri_tcc_clear_PER_DITH6_reg(a, b) hri_tcc_clear_PER_reg(a, b) +#define hri_tcc_toggle_PER_DITH6_reg(a, b) hri_tcc_toggle_PER_reg(a, b) +#define hri_tcc_read_PER_DITH6_reg(a) hri_tcc_read_PER_reg(a) +#define hri_tcc_set_CC_DITH4_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c) +#define hri_tcc_get_CC_DITH4_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c) +#define hri_tcc_write_CC_DITH4_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c) +#define hri_tcc_clear_CC_DITH4_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c) +#define hri_tcc_toggle_CC_DITH4_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c) +#define hri_tcc_read_CC_DITH4_reg(a, b) hri_tcc_read_CC_reg(a, b) +#define hri_tcc_set_CC_DITH5_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c) +#define hri_tcc_get_CC_DITH5_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c) +#define hri_tcc_write_CC_DITH5_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c) +#define hri_tcc_clear_CC_DITH5_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c) +#define hri_tcc_toggle_CC_DITH5_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c) +#define hri_tcc_read_CC_DITH5_reg(a, b) hri_tcc_read_CC_reg(a, b) +#define hri_tcc_set_CC_DITH6_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c) +#define hri_tcc_get_CC_DITH6_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c) +#define hri_tcc_write_CC_DITH6_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c) +#define hri_tcc_clear_CC_DITH6_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c) +#define hri_tcc_toggle_CC_DITH6_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c) +#define hri_tcc_read_CC_DITH6_reg(a, b) hri_tcc_read_CC_reg(a, b) +#define hri_tcc_set_PERBUF_DITH4_reg(a, b) hri_tcc_set_PERBUF_reg(a, b) +#define hri_tcc_get_PERBUF_DITH4_reg(a, b) hri_tcc_get_PERBUF_reg(a, b) +#define hri_tcc_write_PERBUF_DITH4_reg(a, b) hri_tcc_write_PERBUF_reg(a, b) +#define hri_tcc_clear_PERBUF_DITH4_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b) +#define hri_tcc_toggle_PERBUF_DITH4_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b) +#define hri_tcc_read_PERBUF_DITH4_reg(a) hri_tcc_read_PERBUF_reg(a) +#define hri_tcc_set_PERBUF_DITH5_reg(a, b) hri_tcc_set_PERBUF_reg(a, b) +#define hri_tcc_get_PERBUF_DITH5_reg(a, b) hri_tcc_get_PERBUF_reg(a, b) +#define hri_tcc_write_PERBUF_DITH5_reg(a, b) hri_tcc_write_PERBUF_reg(a, b) +#define hri_tcc_clear_PERBUF_DITH5_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b) +#define hri_tcc_toggle_PERBUF_DITH5_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b) +#define hri_tcc_read_PERBUF_DITH5_reg(a) hri_tcc_read_PERBUF_reg(a) +#define hri_tcc_set_PERBUF_DITH6_reg(a, b) hri_tcc_set_PERBUF_reg(a, b) +#define hri_tcc_get_PERBUF_DITH6_reg(a, b) hri_tcc_get_PERBUF_reg(a, b) +#define hri_tcc_write_PERBUF_DITH6_reg(a, b) hri_tcc_write_PERBUF_reg(a, b) +#define hri_tcc_clear_PERBUF_DITH6_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b) +#define hri_tcc_toggle_PERBUF_DITH6_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b) +#define hri_tcc_read_PERBUF_DITH6_reg(a) hri_tcc_read_PERBUF_reg(a) +#define hri_tcc_set_CCBUF_DITH4_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c) +#define hri_tcc_get_CCBUF_DITH4_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c) +#define hri_tcc_write_CCBUF_DITH4_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c) +#define hri_tcc_clear_CCBUF_DITH4_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c) +#define hri_tcc_toggle_CCBUF_DITH4_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c) +#define hri_tcc_read_CCBUF_DITH4_reg(a, b) hri_tcc_read_CCBUF_reg(a, b) +#define hri_tcc_set_CCBUF_DITH5_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c) +#define hri_tcc_get_CCBUF_DITH5_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c) +#define hri_tcc_write_CCBUF_DITH5_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c) +#define hri_tcc_clear_CCBUF_DITH5_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c) +#define hri_tcc_toggle_CCBUF_DITH5_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c) +#define hri_tcc_read_CCBUF_DITH5_reg(a, b) hri_tcc_read_CCBUF_reg(a, b) +#define hri_tcc_set_CCBUF_DITH6_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c) +#define hri_tcc_get_CCBUF_DITH6_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c) +#define hri_tcc_write_CCBUF_DITH6_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c) +#define hri_tcc_clear_CCBUF_DITH6_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c) +#define hri_tcc_toggle_CCBUF_DITH6_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c) +#define hri_tcc_read_CCBUF_DITH6_reg(a, b) hri_tcc_read_CCBUF_reg(a, b) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_TCC_L21_H_INCLUDED */ +#endif /* _SAML21_TCC_COMPONENT_ */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_trng_l21.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_trng_l21.h new file mode 100644 index 00000000..ad4476d1 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_trng_l21.h @@ -0,0 +1,380 @@ +/** + * \file + * + * \brief SAM TRNG + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_TRNG_COMPONENT_ +#ifndef _HRI_TRNG_L21_H_INCLUDED_ +#define _HRI_TRNG_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_TRNG_CRITICAL_SECTIONS) +#define TRNG_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define TRNG_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define TRNG_CRITICAL_SECTION_ENTER() +#define TRNG_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_trng_data_reg_t; +typedef uint8_t hri_trng_ctrla_reg_t; +typedef uint8_t hri_trng_evctrl_reg_t; +typedef uint8_t hri_trng_intenset_reg_t; +typedef uint8_t hri_trng_intflag_reg_t; + +static inline bool hri_trng_get_INTFLAG_DATARDY_bit(const void *const hw) +{ + return (((Trng *)hw)->INTFLAG.reg & TRNG_INTFLAG_DATARDY) >> TRNG_INTFLAG_DATARDY_Pos; +} + +static inline void hri_trng_clear_INTFLAG_DATARDY_bit(const void *const hw) +{ + ((Trng *)hw)->INTFLAG.reg = TRNG_INTFLAG_DATARDY; +} + +static inline bool hri_trng_get_interrupt_DATARDY_bit(const void *const hw) +{ + return (((Trng *)hw)->INTFLAG.reg & TRNG_INTFLAG_DATARDY) >> TRNG_INTFLAG_DATARDY_Pos; +} + +static inline void hri_trng_clear_interrupt_DATARDY_bit(const void *const hw) +{ + ((Trng *)hw)->INTFLAG.reg = TRNG_INTFLAG_DATARDY; +} + +static inline hri_trng_intflag_reg_t hri_trng_get_INTFLAG_reg(const void *const hw, hri_trng_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_trng_intflag_reg_t hri_trng_read_INTFLAG_reg(const void *const hw) +{ + return ((Trng *)hw)->INTFLAG.reg; +} + +static inline void hri_trng_clear_INTFLAG_reg(const void *const hw, hri_trng_intflag_reg_t mask) +{ + ((Trng *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_trng_set_INTEN_DATARDY_bit(const void *const hw) +{ + ((Trng *)hw)->INTENSET.reg = TRNG_INTENSET_DATARDY; +} + +static inline bool hri_trng_get_INTEN_DATARDY_bit(const void *const hw) +{ + return (((Trng *)hw)->INTENSET.reg & TRNG_INTENSET_DATARDY) >> TRNG_INTENSET_DATARDY_Pos; +} + +static inline void hri_trng_write_INTEN_DATARDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Trng *)hw)->INTENCLR.reg = TRNG_INTENSET_DATARDY; + } else { + ((Trng *)hw)->INTENSET.reg = TRNG_INTENSET_DATARDY; + } +} + +static inline void hri_trng_clear_INTEN_DATARDY_bit(const void *const hw) +{ + ((Trng *)hw)->INTENCLR.reg = TRNG_INTENSET_DATARDY; +} + +static inline void hri_trng_set_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask) +{ + ((Trng *)hw)->INTENSET.reg = mask; +} + +static inline hri_trng_intenset_reg_t hri_trng_get_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_trng_intenset_reg_t hri_trng_read_INTEN_reg(const void *const hw) +{ + return ((Trng *)hw)->INTENSET.reg; +} + +static inline void hri_trng_write_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t data) +{ + ((Trng *)hw)->INTENSET.reg = data; + ((Trng *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_trng_clear_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask) +{ + ((Trng *)hw)->INTENCLR.reg = mask; +} + +static inline hri_trng_data_reg_t hri_trng_get_DATA_DATA_bf(const void *const hw, hri_trng_data_reg_t mask) +{ + return (((Trng *)hw)->DATA.reg & TRNG_DATA_DATA(mask)) >> TRNG_DATA_DATA_Pos; +} + +static inline hri_trng_data_reg_t hri_trng_read_DATA_DATA_bf(const void *const hw) +{ + return (((Trng *)hw)->DATA.reg & TRNG_DATA_DATA_Msk) >> TRNG_DATA_DATA_Pos; +} + +static inline hri_trng_data_reg_t hri_trng_get_DATA_reg(const void *const hw, hri_trng_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Trng *)hw)->DATA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_trng_data_reg_t hri_trng_read_DATA_reg(const void *const hw) +{ + return ((Trng *)hw)->DATA.reg; +} + +static inline void hri_trng_set_CTRLA_ENABLE_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg |= TRNG_CTRLA_ENABLE; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_trng_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->CTRLA.reg; + tmp = (tmp & TRNG_CTRLA_ENABLE) >> TRNG_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_trng_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TRNG_CRITICAL_SECTION_ENTER(); + tmp = ((Trng *)hw)->CTRLA.reg; + tmp &= ~TRNG_CTRLA_ENABLE; + tmp |= value << TRNG_CTRLA_ENABLE_Pos; + ((Trng *)hw)->CTRLA.reg = tmp; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg &= ~TRNG_CTRLA_ENABLE; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg ^= TRNG_CTRLA_ENABLE; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg |= TRNG_CTRLA_RUNSTDBY; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_trng_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->CTRLA.reg; + tmp = (tmp & TRNG_CTRLA_RUNSTDBY) >> TRNG_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_trng_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TRNG_CRITICAL_SECTION_ENTER(); + tmp = ((Trng *)hw)->CTRLA.reg; + tmp &= ~TRNG_CTRLA_RUNSTDBY; + tmp |= value << TRNG_CTRLA_RUNSTDBY_Pos; + ((Trng *)hw)->CTRLA.reg = tmp; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg &= ~TRNG_CTRLA_RUNSTDBY; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg ^= TRNG_CTRLA_RUNSTDBY; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_set_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg |= mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_trng_ctrla_reg_t hri_trng_get_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_trng_write_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t data) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg = data; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_clear_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg &= ~mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_toggle_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg ^= mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_trng_ctrla_reg_t hri_trng_read_CTRLA_reg(const void *const hw) +{ + return ((Trng *)hw)->CTRLA.reg; +} + +static inline void hri_trng_set_EVCTRL_DATARDYEO_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg |= TRNG_EVCTRL_DATARDYEO; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_trng_get_EVCTRL_DATARDYEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->EVCTRL.reg; + tmp = (tmp & TRNG_EVCTRL_DATARDYEO) >> TRNG_EVCTRL_DATARDYEO_Pos; + return (bool)tmp; +} + +static inline void hri_trng_write_EVCTRL_DATARDYEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TRNG_CRITICAL_SECTION_ENTER(); + tmp = ((Trng *)hw)->EVCTRL.reg; + tmp &= ~TRNG_EVCTRL_DATARDYEO; + tmp |= value << TRNG_EVCTRL_DATARDYEO_Pos; + ((Trng *)hw)->EVCTRL.reg = tmp; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_clear_EVCTRL_DATARDYEO_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg &= ~TRNG_EVCTRL_DATARDYEO; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_toggle_EVCTRL_DATARDYEO_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg ^= TRNG_EVCTRL_DATARDYEO; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_set_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg |= mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_trng_evctrl_reg_t hri_trng_get_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_trng_write_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t data) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg = data; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_clear_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg &= ~mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_toggle_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg ^= mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_trng_evctrl_reg_t hri_trng_read_EVCTRL_reg(const void *const hw) +{ + return ((Trng *)hw)->EVCTRL.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_TRNG_L21_H_INCLUDED */ +#endif /* _SAML21_TRNG_COMPONENT_ */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_usb_l21.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_usb_l21.h new file mode 100644 index 00000000..40d2a846 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_usb_l21.h @@ -0,0 +1,9335 @@ +/** + * \file + * + * \brief SAM USB + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_USB_COMPONENT_ +#ifndef _HRI_USB_L21_H_INCLUDED_ +#define _HRI_USB_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_USB_CRITICAL_SECTIONS) +#define USB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define USB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define USB_CRITICAL_SECTION_ENTER() +#define USB_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_usb_padcal_reg_t; +typedef uint16_t hri_usbdesc_bank_ctrl_pipe_reg_t; +typedef uint16_t hri_usbdesc_bank_extreg_reg_t; +typedef uint16_t hri_usbdesc_bank_status_pipe_reg_t; +typedef uint16_t hri_usbdescriptordevice_extreg_reg_t; +typedef uint16_t hri_usbdescriptorhost_ctrl_pipe_reg_t; +typedef uint16_t hri_usbdescriptorhost_extreg_reg_t; +typedef uint16_t hri_usbdescriptorhost_status_pipe_reg_t; +typedef uint16_t hri_usbdevice_ctrlb_reg_t; +typedef uint16_t hri_usbdevice_epintsmry_reg_t; +typedef uint16_t hri_usbdevice_fnum_reg_t; +typedef uint16_t hri_usbdevice_intenset_reg_t; +typedef uint16_t hri_usbdevice_intflag_reg_t; +typedef uint16_t hri_usbhost_ctrlb_reg_t; +typedef uint16_t hri_usbhost_fnum_reg_t; +typedef uint16_t hri_usbhost_intenset_reg_t; +typedef uint16_t hri_usbhost_intflag_reg_t; +typedef uint16_t hri_usbhost_pintsmry_reg_t; +typedef uint32_t hri_usb_descadd_reg_t; +typedef uint32_t hri_usbdesc_bank_addr_reg_t; +typedef uint32_t hri_usbdesc_bank_pcksize_reg_t; +typedef uint32_t hri_usbdescriptordevice_addr_reg_t; +typedef uint32_t hri_usbdescriptordevice_pcksize_reg_t; +typedef uint32_t hri_usbdescriptorhost_addr_reg_t; +typedef uint32_t hri_usbdescriptorhost_pcksize_reg_t; +typedef uint8_t hri_usb_ctrla_reg_t; +typedef uint8_t hri_usb_fsmstatus_reg_t; +typedef uint8_t hri_usb_qosctrl_reg_t; +typedef uint8_t hri_usb_syncbusy_reg_t; +typedef uint8_t hri_usbdesc_bank_status_bk_reg_t; +typedef uint8_t hri_usbdescriptordevice_status_bk_reg_t; +typedef uint8_t hri_usbdescriptorhost_status_bk_reg_t; +typedef uint8_t hri_usbdevice_dadd_reg_t; +typedef uint8_t hri_usbdevice_epcfg_reg_t; +typedef uint8_t hri_usbdevice_epintenset_reg_t; +typedef uint8_t hri_usbdevice_epintflag_reg_t; +typedef uint8_t hri_usbdevice_epstatus_reg_t; +typedef uint8_t hri_usbdevice_status_reg_t; +typedef uint8_t hri_usbendpoint_epcfg_reg_t; +typedef uint8_t hri_usbendpoint_epintenset_reg_t; +typedef uint8_t hri_usbendpoint_epintflag_reg_t; +typedef uint8_t hri_usbendpoint_epstatus_reg_t; +typedef uint8_t hri_usbhost_binterval_reg_t; +typedef uint8_t hri_usbhost_flenhigh_reg_t; +typedef uint8_t hri_usbhost_hsofc_reg_t; +typedef uint8_t hri_usbhost_pcfg_reg_t; +typedef uint8_t hri_usbhost_pintenset_reg_t; +typedef uint8_t hri_usbhost_pintflag_reg_t; +typedef uint8_t hri_usbhost_pstatus_reg_t; +typedef uint8_t hri_usbhost_status_reg_t; +typedef uint8_t hri_usbpipe_binterval_reg_t; +typedef uint8_t hri_usbpipe_pcfg_reg_t; +typedef uint8_t hri_usbpipe_pintenset_reg_t; +typedef uint8_t hri_usbpipe_pintflag_reg_t; +typedef uint8_t hri_usbpipe_pstatus_reg_t; + +static inline void hri_usb_wait_for_sync(const void *const hw, hri_usb_syncbusy_reg_t reg) +{ + while (((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_usb_is_syncing(const void *const hw, hri_usb_syncbusy_reg_t reg) +{ + return ((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg; +} + +static inline bool hri_usbpipe_get_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) + >> USB_HOST_PINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; +} + +static inline bool hri_usbpipe_get_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) + >> USB_HOST_PINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; +} + +static inline bool hri_usbpipe_get_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) + >> USB_HOST_PINTFLAG_TRFAIL_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; +} + +static inline bool hri_usbpipe_get_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) + >> USB_HOST_PINTFLAG_PERR_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; +} + +static inline bool hri_usbpipe_get_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) + >> USB_HOST_PINTFLAG_TXSTP_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; +} + +static inline bool hri_usbpipe_get_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) + >> USB_HOST_PINTFLAG_STALL_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; +} + +static inline bool hri_usbpipe_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) + >> USB_HOST_PINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; +} + +static inline bool hri_usbpipe_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) + >> USB_HOST_PINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; +} + +static inline bool hri_usbpipe_get_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) + >> USB_HOST_PINTFLAG_TRFAIL_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; +} + +static inline bool hri_usbpipe_get_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) + >> USB_HOST_PINTFLAG_PERR_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; +} + +static inline bool hri_usbpipe_get_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) + >> USB_HOST_PINTFLAG_TXSTP_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; +} + +static inline bool hri_usbpipe_get_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) + >> USB_HOST_PINTFLAG_STALL_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; +} + +static inline hri_usbpipe_pintflag_reg_t hri_usbpipe_get_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbpipe_pintflag_reg_t hri_usbpipe_read_PINTFLAG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg; +} + +static inline void hri_usbpipe_clear_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintflag_reg_t mask) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = mask; +} + +static inline void hri_usbpipe_set_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; +} + +static inline bool hri_usbpipe_get_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_DTGL) + >> USB_HOST_PSTATUS_DTGL_Pos; +} + +static inline void hri_usbpipe_write_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; + } +} + +static inline void hri_usbpipe_clear_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; +} + +static inline void hri_usbpipe_set_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; +} + +static inline bool hri_usbpipe_get_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_CURBK) + >> USB_HOST_PSTATUS_CURBK_Pos; +} + +static inline void hri_usbpipe_write_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; + } +} + +static inline void hri_usbpipe_clear_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; +} + +static inline void hri_usbpipe_set_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; +} + +static inline bool hri_usbpipe_get_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_PFREEZE) + >> USB_HOST_PSTATUS_PFREEZE_Pos; +} + +static inline void hri_usbpipe_write_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; + } +} + +static inline void hri_usbpipe_clear_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; +} + +static inline void hri_usbpipe_set_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; +} + +static inline bool hri_usbpipe_get_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK0RDY) + >> USB_HOST_PSTATUS_BK0RDY_Pos; +} + +static inline void hri_usbpipe_write_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; + } +} + +static inline void hri_usbpipe_clear_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; +} + +static inline void hri_usbpipe_set_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; +} + +static inline bool hri_usbpipe_get_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK1RDY) + >> USB_HOST_PSTATUS_BK1RDY_Pos; +} + +static inline void hri_usbpipe_write_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; + } +} + +static inline void hri_usbpipe_clear_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; +} + +static inline void hri_usbpipe_set_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pstatus_reg_t mask) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = mask; +} + +static inline hri_usbpipe_pstatus_reg_t hri_usbpipe_get_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbpipe_pstatus_reg_t hri_usbpipe_read_PSTATUS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg; +} + +static inline void hri_usbpipe_write_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pstatus_reg_t data) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = data; + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = ~data; +} + +static inline void hri_usbpipe_clear_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pstatus_reg_t mask) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = mask; +} + +static inline void hri_usbpipe_set_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; +} + +static inline bool hri_usbpipe_get_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT0) + >> USB_HOST_PINTENSET_TRCPT0_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; + } +} + +static inline void hri_usbpipe_clear_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; +} + +static inline void hri_usbpipe_set_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; +} + +static inline bool hri_usbpipe_get_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT1) + >> USB_HOST_PINTENSET_TRCPT1_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; + } +} + +static inline void hri_usbpipe_clear_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; +} + +static inline void hri_usbpipe_set_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; +} + +static inline bool hri_usbpipe_get_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRFAIL) + >> USB_HOST_PINTENSET_TRFAIL_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; + } +} + +static inline void hri_usbpipe_clear_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; +} + +static inline void hri_usbpipe_set_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; +} + +static inline bool hri_usbpipe_get_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_PERR) + >> USB_HOST_PINTENSET_PERR_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; + } +} + +static inline void hri_usbpipe_clear_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; +} + +static inline void hri_usbpipe_set_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; +} + +static inline bool hri_usbpipe_get_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TXSTP) + >> USB_HOST_PINTENSET_TXSTP_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; + } +} + +static inline void hri_usbpipe_clear_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; +} + +static inline void hri_usbpipe_set_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; +} + +static inline bool hri_usbpipe_get_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_STALL) + >> USB_HOST_PINTENSET_STALL_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; + } +} + +static inline void hri_usbpipe_clear_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; +} + +static inline void hri_usbpipe_set_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintenset_reg_t mask) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = mask; +} + +static inline hri_usbpipe_pintenset_reg_t hri_usbpipe_get_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbpipe_pintenset_reg_t hri_usbpipe_read_PINTEN_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg; +} + +static inline void hri_usbpipe_write_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintenset_reg_t data) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = data; + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = ~data; +} + +static inline void hri_usbpipe_clear_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintenset_reg_t mask) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = mask; +} + +static inline void hri_usbpipe_set_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbpipe_get_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_BK) >> USB_HOST_PCFG_BK_Pos; + return (bool)tmp; +} + +static inline void hri_usbpipe_write_PCFG_BK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_BK; + tmp |= value << USB_HOST_PCFG_BK_Pos; + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_set_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTOKEN(mask)) >> USB_HOST_PCFG_PTOKEN_Pos; + return tmp; +} + +static inline void hri_usbpipe_write_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_PTOKEN_Msk; + tmp |= USB_HOST_PCFG_PTOKEN(data); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTOKEN_Msk) >> USB_HOST_PCFG_PTOKEN_Pos; + return tmp; +} + +static inline void hri_usbpipe_set_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTYPE(mask)) >> USB_HOST_PCFG_PTYPE_Pos; + return tmp; +} + +static inline void hri_usbpipe_write_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_PTYPE_Msk; + tmp |= USB_HOST_PCFG_PTYPE(data); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTYPE_Msk) >> USB_HOST_PCFG_PTYPE_Pos; + return tmp; +} + +static inline void hri_usbpipe_set_PCFG_reg(const void *const hw, uint8_t submodule_index, hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbpipe_write_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; +} + +static inline void hri_usbpipe_set_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg |= USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_binterval_reg_t hri_usbpipe_get_BINTERVAL_BITINTERVAL_bf(const void *const hw, + uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; + tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL(mask)) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; + return tmp; +} + +static inline void hri_usbpipe_write_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; + tmp &= ~USB_HOST_BINTERVAL_BITINTERVAL_Msk; + tmp |= USB_HOST_BINTERVAL_BITINTERVAL(data); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg &= ~USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg ^= USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_binterval_reg_t hri_usbpipe_read_BINTERVAL_BITINTERVAL_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; + tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL_Msk) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; + return tmp; +} + +static inline void hri_usbpipe_set_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_binterval_reg_t hri_usbpipe_get_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbpipe_write_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_binterval_reg_t hri_usbpipe_read_BINTERVAL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; +} + +static inline bool hri_usbhost_get_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) + >> USB_HOST_PINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; +} + +static inline bool hri_usbhost_get_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) + >> USB_HOST_PINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; +} + +static inline bool hri_usbhost_get_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) + >> USB_HOST_PINTFLAG_TRFAIL_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; +} + +static inline bool hri_usbhost_get_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) + >> USB_HOST_PINTFLAG_PERR_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; +} + +static inline bool hri_usbhost_get_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) + >> USB_HOST_PINTFLAG_TXSTP_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; +} + +static inline bool hri_usbhost_get_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) + >> USB_HOST_PINTFLAG_STALL_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; +} + +static inline bool hri_usbhost_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) + >> USB_HOST_PINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbhost_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; +} + +static inline bool hri_usbhost_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) + >> USB_HOST_PINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbhost_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; +} + +static inline bool hri_usbhost_get_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) + >> USB_HOST_PINTFLAG_TRFAIL_Pos; +} + +static inline void hri_usbhost_clear_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; +} + +static inline bool hri_usbhost_get_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) + >> USB_HOST_PINTFLAG_PERR_Pos; +} + +static inline void hri_usbhost_clear_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; +} + +static inline bool hri_usbhost_get_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) + >> USB_HOST_PINTFLAG_TXSTP_Pos; +} + +static inline void hri_usbhost_clear_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; +} + +static inline bool hri_usbhost_get_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) + >> USB_HOST_PINTFLAG_STALL_Pos; +} + +static inline void hri_usbhost_clear_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; +} + +static inline hri_usbhost_pintflag_reg_t hri_usbhost_get_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_pintflag_reg_t hri_usbhost_read_PINTFLAG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg; +} + +static inline void hri_usbhost_clear_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintflag_reg_t mask) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = mask; +} + +static inline void hri_usbhost_set_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; +} + +static inline bool hri_usbhost_get_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_DTGL) + >> USB_HOST_PSTATUS_DTGL_Pos; +} + +static inline void hri_usbhost_write_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; + } +} + +static inline void hri_usbhost_clear_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; +} + +static inline void hri_usbhost_set_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; +} + +static inline bool hri_usbhost_get_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_CURBK) + >> USB_HOST_PSTATUS_CURBK_Pos; +} + +static inline void hri_usbhost_write_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; + } +} + +static inline void hri_usbhost_clear_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; +} + +static inline void hri_usbhost_set_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; +} + +static inline bool hri_usbhost_get_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_PFREEZE) + >> USB_HOST_PSTATUS_PFREEZE_Pos; +} + +static inline void hri_usbhost_write_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; + } +} + +static inline void hri_usbhost_clear_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; +} + +static inline void hri_usbhost_set_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; +} + +static inline bool hri_usbhost_get_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK0RDY) + >> USB_HOST_PSTATUS_BK0RDY_Pos; +} + +static inline void hri_usbhost_write_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; + } +} + +static inline void hri_usbhost_clear_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; +} + +static inline void hri_usbhost_set_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; +} + +static inline bool hri_usbhost_get_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK1RDY) + >> USB_HOST_PSTATUS_BK1RDY_Pos; +} + +static inline void hri_usbhost_write_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; + } +} + +static inline void hri_usbhost_clear_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; +} + +static inline void hri_usbhost_set_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pstatus_reg_t mask) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = mask; +} + +static inline hri_usbhost_pstatus_reg_t hri_usbhost_get_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_pstatus_reg_t hri_usbhost_read_PSTATUS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg; +} + +static inline void hri_usbhost_write_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pstatus_reg_t data) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = data; + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = ~data; +} + +static inline void hri_usbhost_clear_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pstatus_reg_t mask) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = mask; +} + +static inline void hri_usbhost_set_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; +} + +static inline bool hri_usbhost_get_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT0) + >> USB_HOST_PINTENSET_TRCPT0_Pos; +} + +static inline void hri_usbhost_write_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; + } +} + +static inline void hri_usbhost_clear_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; +} + +static inline void hri_usbhost_set_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; +} + +static inline bool hri_usbhost_get_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT1) + >> USB_HOST_PINTENSET_TRCPT1_Pos; +} + +static inline void hri_usbhost_write_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; + } +} + +static inline void hri_usbhost_clear_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; +} + +static inline void hri_usbhost_set_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; +} + +static inline bool hri_usbhost_get_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRFAIL) + >> USB_HOST_PINTENSET_TRFAIL_Pos; +} + +static inline void hri_usbhost_write_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; + } +} + +static inline void hri_usbhost_clear_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; +} + +static inline void hri_usbhost_set_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; +} + +static inline bool hri_usbhost_get_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_PERR) + >> USB_HOST_PINTENSET_PERR_Pos; +} + +static inline void hri_usbhost_write_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; + } +} + +static inline void hri_usbhost_clear_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; +} + +static inline void hri_usbhost_set_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; +} + +static inline bool hri_usbhost_get_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TXSTP) + >> USB_HOST_PINTENSET_TXSTP_Pos; +} + +static inline void hri_usbhost_write_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; + } +} + +static inline void hri_usbhost_clear_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; +} + +static inline void hri_usbhost_set_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; +} + +static inline bool hri_usbhost_get_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_STALL) + >> USB_HOST_PINTENSET_STALL_Pos; +} + +static inline void hri_usbhost_write_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; + } +} + +static inline void hri_usbhost_clear_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; +} + +static inline void hri_usbhost_set_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintenset_reg_t mask) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = mask; +} + +static inline hri_usbhost_pintenset_reg_t hri_usbhost_get_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_pintenset_reg_t hri_usbhost_read_PINTEN_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg; +} + +static inline void hri_usbhost_write_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintenset_reg_t data) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = data; + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = ~data; +} + +static inline void hri_usbhost_clear_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintenset_reg_t mask) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = mask; +} + +static inline void hri_usbhost_set_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_BK) >> USB_HOST_PCFG_BK_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_PCFG_BK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_BK; + tmp |= value << USB_HOST_PCFG_BK_Pos; + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTOKEN(mask)) >> USB_HOST_PCFG_PTOKEN_Pos; + return tmp; +} + +static inline void hri_usbhost_write_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_PTOKEN_Msk; + tmp |= USB_HOST_PCFG_PTOKEN(data); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTOKEN_Msk) >> USB_HOST_PCFG_PTOKEN_Pos; + return tmp; +} + +static inline void hri_usbhost_set_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTYPE(mask)) >> USB_HOST_PCFG_PTYPE_Pos; + return tmp; +} + +static inline void hri_usbhost_write_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_PTYPE_Msk; + tmp |= USB_HOST_PCFG_PTYPE(data); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTYPE_Msk) >> USB_HOST_PCFG_PTYPE_Pos; + return tmp; +} + +static inline void hri_usbhost_set_PCFG_reg(const void *const hw, uint8_t submodule_index, hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; +} + +static inline void hri_usbhost_set_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg |= USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_binterval_reg_t hri_usbhost_get_BINTERVAL_BITINTERVAL_bf(const void *const hw, + uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; + tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL(mask)) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; + return tmp; +} + +static inline void hri_usbhost_write_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; + tmp &= ~USB_HOST_BINTERVAL_BITINTERVAL_Msk; + tmp |= USB_HOST_BINTERVAL_BITINTERVAL(data); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg &= ~USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg ^= USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_binterval_reg_t hri_usbhost_read_BINTERVAL_BITINTERVAL_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; + tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL_Msk) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; + return tmp; +} + +static inline void hri_usbhost_set_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_binterval_reg_t hri_usbhost_get_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_binterval_reg_t hri_usbhost_read_BINTERVAL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; +} + +static inline void hri_usbhostdescbank_set_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg |= USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_get_ADDR_ADDR_bf(const void *const hw, + hri_usbdesc_bank_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->ADDR.reg; + tmp = (tmp & USB_HOST_ADDR_ADDR(mask)) >> USB_HOST_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->ADDR.reg; + tmp &= ~USB_HOST_ADDR_ADDR_Msk; + tmp |= USB_HOST_ADDR_ADDR(data); + ((UsbHostDescBank *)hw)->ADDR.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg &= ~USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg ^= USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->ADDR.reg; + tmp = (tmp & USB_HOST_ADDR_ADDR_Msk) >> USB_HOST_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_get_ADDR_reg(const void *const hw, + hri_usbdesc_bank_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_write_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_read_ADDR_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->ADDR.reg; +} + +static inline void hri_usbhostdescbank_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_AUTO_ZLP) >> USB_HOST_PCKSIZE_AUTO_ZLP_Pos; + return (bool)tmp; +} + +static inline void hri_usbhostdescbank_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_AUTO_ZLP; + tmp |= value << USB_HOST_PCKSIZE_AUTO_ZLP_Pos; + ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbhostdescbank_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT(mask)) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_BYTE_COUNT_Msk; + tmp |= USB_HOST_PCKSIZE_BYTE_COUNT(data); + ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT_Msk) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbhostdescbank_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk; + tmp |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(data); + ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbhostdescbank_get_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_SIZE(mask)) >> USB_HOST_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_SIZE_Msk; + tmp |= USB_HOST_PCKSIZE_SIZE(data); + ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_SIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_SIZE_Msk) >> USB_HOST_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_get_PCKSIZE_reg(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_write_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->PCKSIZE.reg; +} + +static inline void hri_usbhostdescbank_set_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg |= USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_get_EXTREG_SUBPID_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_SUBPID(mask)) >> USB_HOST_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp &= ~USB_HOST_EXTREG_SUBPID_Msk; + tmp |= USB_HOST_EXTREG_SUBPID(data); + ((UsbHostDescBank *)hw)->EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg &= ~USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg ^= USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_SUBPID_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_SUBPID_Msk) >> USB_HOST_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg |= USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t +hri_usbhostdescbank_get_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_VARIABLE(mask)) >> USB_HOST_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp &= ~USB_HOST_EXTREG_VARIABLE_Msk; + tmp |= USB_HOST_EXTREG_VARIABLE(data); + ((UsbHostDescBank *)hw)->EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg &= ~USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg ^= USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_VARIABLE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_VARIABLE_Msk) >> USB_HOST_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_get_EXTREG_reg(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_write_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->EXTREG.reg; +} + +static inline void hri_usbhostdescbank_set_CTRL_PIPE_PDADDR_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t +hri_usbhostdescbank_get_CTRL_PIPE_PDADDR_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR(mask)) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_CTRL_PIPE_PDADDR_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PDADDR_Msk; + tmp |= USB_HOST_CTRL_PIPE_PDADDR(data); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PDADDR_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PDADDR_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PDADDR_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR_Msk) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_CTRL_PIPE_PEPNUM_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t +hri_usbhostdescbank_get_CTRL_PIPE_PEPNUM_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM(mask)) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_CTRL_PIPE_PEPNUM_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PEPNUM_Msk; + tmp |= USB_HOST_CTRL_PIPE_PEPNUM(data); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PEPNUM_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PEPNUM_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PEPNUM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM_Msk) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_CTRL_PIPE_PERMAX_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t +hri_usbhostdescbank_get_CTRL_PIPE_PERMAX_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX(mask)) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_CTRL_PIPE_PERMAX_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PERMAX_Msk; + tmp |= USB_HOST_CTRL_PIPE_PERMAX(data); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PERMAX_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PERMAX_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PERMAX_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX_Msk) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t +hri_usbhostdescbank_get_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_write_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; +} + +static inline bool hri_usbhostdescbank_get_STATUS_BK_CRCERR_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_BK.reg & USB_HOST_STATUS_BK_CRCERR) >> USB_HOST_STATUS_BK_CRCERR_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_BK_CRCERR_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_BK.reg = USB_HOST_STATUS_BK_CRCERR; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_STATUS_BK_ERRORFLOW_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_BK.reg & USB_HOST_STATUS_BK_ERRORFLOW) >> USB_HOST_STATUS_BK_ERRORFLOW_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_BK.reg = USB_HOST_STATUS_BK_ERRORFLOW; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_bk_reg_t +hri_usbhostdescbank_get_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHostDescBank *)hw)->STATUS_BK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_clear_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_BK.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_bk_reg_t hri_usbhostdescbank_read_STATUS_BK_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->STATUS_BK.reg; +} + +static inline bool hri_usbhostdescbank_get_STATUS_PIPE_DTGLER_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DTGLER) >> USB_HOST_STATUS_PIPE_DTGLER_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_DTGLER_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DTGLER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_STATUS_PIPE_DAPIDER_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DAPIDER) + >> USB_HOST_STATUS_PIPE_DAPIDER_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_DAPIDER_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DAPIDER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_STATUS_PIPE_PIDER_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_PIDER) >> USB_HOST_STATUS_PIPE_PIDER_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_PIDER_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_PIDER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_STATUS_PIPE_TOUTER_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_TOUTER) >> USB_HOST_STATUS_PIPE_TOUTER_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_TOUTER_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_TOUTER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_STATUS_PIPE_CRC16ER_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_CRC16ER) + >> USB_HOST_STATUS_PIPE_CRC16ER_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_CRC16ER_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_CRC16ER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_pipe_reg_t +hri_usbhostdescbank_get_STATUS_PIPE_ERCNT_bf(const void *const hw, hri_usbdesc_bank_status_pipe_reg_t mask) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT(mask)) + >> USB_HOST_STATUS_PIPE_ERCNT_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_ERCNT_bf(const void *const hw, + hri_usbdesc_bank_status_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_ERCNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_pipe_reg_t hri_usbhostdescbank_read_STATUS_PIPE_ERCNT_bf(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT_Msk) + >> USB_HOST_STATUS_PIPE_ERCNT_Pos; +} + +static inline hri_usbdesc_bank_status_pipe_reg_t +hri_usbhostdescbank_get_STATUS_PIPE_reg(const void *const hw, hri_usbdesc_bank_status_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->STATUS_PIPE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_reg(const void *const hw, + hri_usbdesc_bank_status_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_pipe_reg_t hri_usbhostdescbank_read_STATUS_PIPE_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->STATUS_PIPE.reg; +} + +static inline void hri_usbhostdescriptor_set_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg |= USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_addr_reg_t +hri_usbhostdescriptor_get_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; + tmp = (tmp & USB_HOST_ADDR_ADDR(mask)) >> USB_HOST_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; + tmp &= ~USB_HOST_ADDR_ADDR_Msk; + tmp |= USB_HOST_ADDR_ADDR(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg &= ~USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg ^= USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_addr_reg_t hri_usbhostdescriptor_read_ADDR_ADDR_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; + tmp = (tmp & USB_HOST_ADDR_ADDR_Msk) >> USB_HOST_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_addr_reg_t +hri_usbhostdescriptor_get_ADDR_reg(const void *const hw, uint8_t submodule_index, hri_usbdescriptorhost_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_addr_reg_t hri_usbhostdescriptor_read_ADDR_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; +} + +static inline void hri_usbhostdescriptor_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_AUTO_ZLP) >> USB_HOST_PCKSIZE_AUTO_ZLP_Pos; + return (bool)tmp; +} + +static inline void hri_usbhostdescriptor_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_AUTO_ZLP; + tmp |= value << USB_HOST_PCKSIZE_AUTO_ZLP_Pos; + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t +hri_usbhostdescriptor_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT(mask)) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_BYTE_COUNT_Msk; + tmp |= USB_HOST_PCKSIZE_BYTE_COUNT(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t +hri_usbhostdescriptor_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT_Msk) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t +hri_usbhostdescriptor_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk; + tmp |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t +hri_usbhostdescriptor_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t +hri_usbhostdescriptor_get_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_SIZE(mask)) >> USB_HOST_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_SIZE_Msk; + tmp |= USB_HOST_PCKSIZE_SIZE(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t hri_usbhostdescriptor_read_PCKSIZE_SIZE_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_SIZE_Msk) >> USB_HOST_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t +hri_usbhostdescriptor_get_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t hri_usbhostdescriptor_read_PCKSIZE_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; +} + +static inline void hri_usbhostdescriptor_set_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_extreg_reg_t +hri_usbhostdescriptor_get_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_SUBPID(mask)) >> USB_HOST_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp &= ~USB_HOST_EXTREG_SUBPID_Msk; + tmp |= USB_HOST_EXTREG_SUBPID(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_SUBPID_bf(const void *const hw, + uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_SUBPID_Msk) >> USB_HOST_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_extreg_reg_t +hri_usbhostdescriptor_get_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_VARIABLE(mask)) >> USB_HOST_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp &= ~USB_HOST_EXTREG_VARIABLE_Msk; + tmp |= USB_HOST_EXTREG_VARIABLE(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_VARIABLE_bf(const void *const hw, + uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_VARIABLE_Msk) >> USB_HOST_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_extreg_reg_t +hri_usbhostdescriptor_get_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; +} + +static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t +hri_usbhostdescriptor_get_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR(mask)) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PDADDR_Msk; + tmp |= USB_HOST_CTRL_PIPE_PDADDR(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t +hri_usbhostdescriptor_read_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR_Msk) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t +hri_usbhostdescriptor_get_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM(mask)) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PEPNUM_Msk; + tmp |= USB_HOST_CTRL_PIPE_PEPNUM(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t +hri_usbhostdescriptor_read_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM_Msk) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t +hri_usbhostdescriptor_get_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX(mask)) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PERMAX_Msk; + tmp |= USB_HOST_CTRL_PIPE_PERMAX(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t +hri_usbhostdescriptor_read_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX_Msk) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t +hri_usbhostdescriptor_get_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t hri_usbhostdescriptor_read_CTRL_PIPE_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; +} + +static inline bool hri_usbhostdescriptor_get_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg & USB_HOST_STATUS_BK_CRCERR) + >> USB_HOST_STATUS_BK_CRCERR_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = USB_HOST_STATUS_BK_CRCERR; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg & USB_HOST_STATUS_BK_ERRORFLOW) + >> USB_HOST_STATUS_BK_ERRORFLOW_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = USB_HOST_STATUS_BK_ERRORFLOW; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_status_bk_reg_t +hri_usbhostdescriptor_get_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_status_bk_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_status_bk_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_status_bk_reg_t hri_usbhostdescriptor_read_STATUS_BK_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg; +} + +static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_DTGLER_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DTGLER) + >> USB_HOST_STATUS_PIPE_DTGLER_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_DTGLER_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DTGLER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_DAPIDER_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DAPIDER) + >> USB_HOST_STATUS_PIPE_DAPIDER_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_DAPIDER_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DAPIDER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_PIDER_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_PIDER) + >> USB_HOST_STATUS_PIPE_PIDER_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_PIDER_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_PIDER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_TOUTER_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_TOUTER) + >> USB_HOST_STATUS_PIPE_TOUTER_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_TOUTER_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_TOUTER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_CRC16ER_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_CRC16ER) + >> USB_HOST_STATUS_PIPE_CRC16ER_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_CRC16ER_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_CRC16ER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_status_pipe_reg_t +hri_usbhostdescriptor_get_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_status_pipe_reg_t mask) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT(mask)) + >> USB_HOST_STATUS_PIPE_ERCNT_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_status_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_ERCNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_status_pipe_reg_t +hri_usbhostdescriptor_read_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT_Msk) + >> USB_HOST_STATUS_PIPE_ERCNT_Pos; +} + +static inline hri_usbdescriptorhost_status_pipe_reg_t +hri_usbhostdescriptor_get_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_status_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_status_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_status_pipe_reg_t +hri_usbhostdescriptor_read_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) + >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) + >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) + >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) + >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) + >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) + >> USB_DEVICE_EPINTFLAG_STALL0_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) + >> USB_DEVICE_EPINTFLAG_STALL1_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; +} + +static inline bool hri_usbendpoint_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) + >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; +} + +static inline bool hri_usbendpoint_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) + >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; +} + +static inline bool hri_usbendpoint_get_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) + >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; +} + +static inline bool hri_usbendpoint_get_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) + >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; +} + +static inline bool hri_usbendpoint_get_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) + >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; +} + +static inline bool hri_usbendpoint_get_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) + >> USB_DEVICE_EPINTFLAG_STALL0_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; +} + +static inline bool hri_usbendpoint_get_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) + >> USB_DEVICE_EPINTFLAG_STALL1_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; +} + +static inline hri_usbendpoint_epintflag_reg_t +hri_usbendpoint_get_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbendpoint_epintflag_reg_t hri_usbendpoint_read_EPINTFLAG_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epintflag_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = mask; +} + +static inline void hri_usbendpoint_set_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLOUT) + >> USB_DEVICE_EPSTATUS_DTGLOUT_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; +} + +static inline void hri_usbendpoint_set_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLIN) + >> USB_DEVICE_EPSTATUS_DTGLIN_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; +} + +static inline void hri_usbendpoint_set_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_CURBK) + >> USB_DEVICE_EPSTATUS_CURBK_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; +} + +static inline void hri_usbendpoint_set_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ0) + >> USB_DEVICE_EPSTATUS_STALLRQ0_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; +} + +static inline void hri_usbendpoint_set_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ1) + >> USB_DEVICE_EPSTATUS_STALLRQ1_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; +} + +static inline void hri_usbendpoint_set_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK0RDY) + >> USB_DEVICE_EPSTATUS_BK0RDY_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; +} + +static inline void hri_usbendpoint_set_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK1RDY) + >> USB_DEVICE_EPSTATUS_BK1RDY_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; +} + +static inline void hri_usbendpoint_set_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epstatus_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = mask; +} + +static inline hri_usbendpoint_epstatus_reg_t +hri_usbendpoint_get_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbendpoint_epstatus_reg_t hri_usbendpoint_read_EPSTATUS_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg; +} + +static inline void hri_usbendpoint_write_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epstatus_reg_t data) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = data; + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = ~data; +} + +static inline void hri_usbendpoint_clear_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epstatus_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = mask; +} + +static inline void hri_usbendpoint_set_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; +} + +static inline bool hri_usbendpoint_get_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT0) + >> USB_DEVICE_EPINTENSET_TRCPT0_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; +} + +static inline void hri_usbendpoint_set_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; +} + +static inline bool hri_usbendpoint_get_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT1) + >> USB_DEVICE_EPINTENSET_TRCPT1_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; +} + +static inline void hri_usbendpoint_set_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; +} + +static inline bool hri_usbendpoint_get_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL0) + >> USB_DEVICE_EPINTENSET_TRFAIL0_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; +} + +static inline void hri_usbendpoint_set_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; +} + +static inline bool hri_usbendpoint_get_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL1) + >> USB_DEVICE_EPINTENSET_TRFAIL1_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; +} + +static inline void hri_usbendpoint_set_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; +} + +static inline bool hri_usbendpoint_get_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_RXSTP) + >> USB_DEVICE_EPINTENSET_RXSTP_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; +} + +static inline void hri_usbendpoint_set_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; +} + +static inline bool hri_usbendpoint_get_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL0) + >> USB_DEVICE_EPINTENSET_STALL0_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; +} + +static inline void hri_usbendpoint_set_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; +} + +static inline bool hri_usbendpoint_get_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL1) + >> USB_DEVICE_EPINTENSET_STALL1_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; +} + +static inline void hri_usbendpoint_set_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epintenset_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = mask; +} + +static inline hri_usbendpoint_epintenset_reg_t +hri_usbendpoint_get_EPINTEN_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbendpoint_epintenset_reg_t hri_usbendpoint_read_EPINTEN_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg; +} + +static inline void hri_usbendpoint_write_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epintenset_reg_t data) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = data; + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = ~data; +} + +static inline void hri_usbendpoint_clear_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epintenset_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = mask; +} + +static inline void hri_usbendpoint_set_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbendpoint_get_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_NYETDIS) >> USB_DEVICE_EPCFG_NYETDIS_Pos; + return (bool)tmp; +} + +static inline void hri_usbendpoint_write_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_NYETDIS; + tmp |= value << USB_DEVICE_EPCFG_NYETDIS_Pos; + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_clear_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_toggle_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_set_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t +hri_usbendpoint_get_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0(mask)) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; + return tmp; +} + +static inline void hri_usbendpoint_write_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk; + tmp |= USB_DEVICE_EPCFG_EPTYPE0(data); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_clear_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_toggle_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_EPTYPE0_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0_Msk) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; + return tmp; +} + +static inline void hri_usbendpoint_set_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t +hri_usbendpoint_get_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1(mask)) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; + return tmp; +} + +static inline void hri_usbendpoint_write_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk; + tmp |= USB_DEVICE_EPCFG_EPTYPE1(data); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_clear_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_toggle_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_EPTYPE1_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1_Msk) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; + return tmp; +} + +static inline void hri_usbendpoint_set_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_get_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbendpoint_write_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_clear_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_toggle_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) + >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) + >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) + >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) + >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) + >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) + >> USB_DEVICE_EPINTFLAG_STALL0_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) + >> USB_DEVICE_EPINTFLAG_STALL1_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; +} + +static inline bool hri_usbdevice_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) + >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; +} + +static inline bool hri_usbdevice_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) + >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; +} + +static inline bool hri_usbdevice_get_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) + >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; +} + +static inline bool hri_usbdevice_get_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) + >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; +} + +static inline bool hri_usbdevice_get_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) + >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; +} + +static inline bool hri_usbdevice_get_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) + >> USB_DEVICE_EPINTFLAG_STALL0_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; +} + +static inline bool hri_usbdevice_get_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) + >> USB_DEVICE_EPINTFLAG_STALL1_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; +} + +static inline hri_usbdevice_epintflag_reg_t +hri_usbdevice_get_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, hri_usbdevice_epintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_epintflag_reg_t hri_usbdevice_read_EPINTFLAG_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epintflag_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = mask; +} + +static inline void hri_usbdevice_set_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; +} + +static inline bool hri_usbdevice_get_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLOUT) + >> USB_DEVICE_EPSTATUS_DTGLOUT_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; +} + +static inline void hri_usbdevice_set_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; +} + +static inline bool hri_usbdevice_get_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLIN) + >> USB_DEVICE_EPSTATUS_DTGLIN_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; +} + +static inline void hri_usbdevice_set_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; +} + +static inline bool hri_usbdevice_get_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_CURBK) + >> USB_DEVICE_EPSTATUS_CURBK_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; +} + +static inline void hri_usbdevice_set_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; +} + +static inline bool hri_usbdevice_get_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ0) + >> USB_DEVICE_EPSTATUS_STALLRQ0_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; +} + +static inline void hri_usbdevice_set_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; +} + +static inline bool hri_usbdevice_get_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ1) + >> USB_DEVICE_EPSTATUS_STALLRQ1_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; +} + +static inline void hri_usbdevice_set_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; +} + +static inline bool hri_usbdevice_get_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK0RDY) + >> USB_DEVICE_EPSTATUS_BK0RDY_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; +} + +static inline void hri_usbdevice_set_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; +} + +static inline bool hri_usbdevice_get_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK1RDY) + >> USB_DEVICE_EPSTATUS_BK1RDY_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; +} + +static inline void hri_usbdevice_set_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epstatus_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = mask; +} + +static inline hri_usbdevice_epstatus_reg_t hri_usbdevice_get_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_epstatus_reg_t hri_usbdevice_read_EPSTATUS_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg; +} + +static inline void hri_usbdevice_write_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epstatus_reg_t data) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = data; + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = ~data; +} + +static inline void hri_usbdevice_clear_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epstatus_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = mask; +} + +static inline void hri_usbdevice_set_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; +} + +static inline bool hri_usbdevice_get_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT0) + >> USB_DEVICE_EPINTENSET_TRCPT0_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; +} + +static inline void hri_usbdevice_set_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; +} + +static inline bool hri_usbdevice_get_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT1) + >> USB_DEVICE_EPINTENSET_TRCPT1_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; +} + +static inline void hri_usbdevice_set_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; +} + +static inline bool hri_usbdevice_get_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL0) + >> USB_DEVICE_EPINTENSET_TRFAIL0_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; +} + +static inline void hri_usbdevice_set_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; +} + +static inline bool hri_usbdevice_get_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL1) + >> USB_DEVICE_EPINTENSET_TRFAIL1_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; +} + +static inline void hri_usbdevice_set_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; +} + +static inline bool hri_usbdevice_get_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_RXSTP) + >> USB_DEVICE_EPINTENSET_RXSTP_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; +} + +static inline void hri_usbdevice_set_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; +} + +static inline bool hri_usbdevice_get_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL0) + >> USB_DEVICE_EPINTENSET_STALL0_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; +} + +static inline void hri_usbdevice_set_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; +} + +static inline bool hri_usbdevice_get_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL1) + >> USB_DEVICE_EPINTENSET_STALL1_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; +} + +static inline void hri_usbdevice_set_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epintenset_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = mask; +} + +static inline hri_usbdevice_epintenset_reg_t +hri_usbdevice_get_EPINTEN_reg(const void *const hw, uint8_t submodule_index, hri_usbdevice_epintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_epintenset_reg_t hri_usbdevice_read_EPINTEN_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg; +} + +static inline void hri_usbdevice_write_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epintenset_reg_t data) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = data; + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = ~data; +} + +static inline void hri_usbdevice_clear_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epintenset_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = mask; +} + +static inline void hri_usbdevice_set_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_NYETDIS) >> USB_DEVICE_EPCFG_NYETDIS_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_NYETDIS; + tmp |= value << USB_DEVICE_EPCFG_NYETDIS_Pos; + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t +hri_usbdevice_get_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, hri_usbdevice_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0(mask)) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk; + tmp |= USB_DEVICE_EPCFG_EPTYPE0(data); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_EPTYPE0_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0_Msk) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t +hri_usbdevice_get_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, hri_usbdevice_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1(mask)) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk; + tmp |= USB_DEVICE_EPCFG_EPTYPE1(data); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_EPTYPE1_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1_Msk) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_get_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevice_write_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; +} + +static inline bool hri_usbdevice_get_INTFLAG_SUSPEND_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SUSPEND) >> USB_DEVICE_INTFLAG_SUSPEND_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_SUSPEND_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SUSPEND; +} + +static inline bool hri_usbdevice_get_INTFLAG_MSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_MSOF) >> USB_DEVICE_INTFLAG_MSOF_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_MSOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MSOF; +} + +static inline bool hri_usbdevice_get_INTFLAG_SOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SOF) >> USB_DEVICE_INTFLAG_SOF_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_SOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF; +} + +static inline bool hri_usbdevice_get_INTFLAG_EORST_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORST) >> USB_DEVICE_INTFLAG_EORST_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_EORST_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST; +} + +static inline bool hri_usbdevice_get_INTFLAG_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_WAKEUP) >> USB_DEVICE_INTFLAG_WAKEUP_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP; +} + +static inline bool hri_usbdevice_get_INTFLAG_EORSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORSM) >> USB_DEVICE_INTFLAG_EORSM_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_EORSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORSM; +} + +static inline bool hri_usbdevice_get_INTFLAG_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_UPRSM) >> USB_DEVICE_INTFLAG_UPRSM_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_UPRSM; +} + +static inline bool hri_usbdevice_get_INTFLAG_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_RAMACER) >> USB_DEVICE_INTFLAG_RAMACER_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_RAMACER; +} + +static inline bool hri_usbdevice_get_INTFLAG_LPMNYET_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMNYET) >> USB_DEVICE_INTFLAG_LPMNYET_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_LPMNYET_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMNYET; +} + +static inline bool hri_usbdevice_get_INTFLAG_LPMSUSP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMSUSP) >> USB_DEVICE_INTFLAG_LPMSUSP_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_LPMSUSP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMSUSP; +} + +static inline bool hri_usbdevice_get_interrupt_SUSPEND_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SUSPEND) >> USB_DEVICE_INTFLAG_SUSPEND_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_SUSPEND_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SUSPEND; +} + +static inline bool hri_usbdevice_get_interrupt_MSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_MSOF) >> USB_DEVICE_INTFLAG_MSOF_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_MSOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MSOF; +} + +static inline bool hri_usbdevice_get_interrupt_SOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SOF) >> USB_DEVICE_INTFLAG_SOF_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_SOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF; +} + +static inline bool hri_usbdevice_get_interrupt_EORST_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORST) >> USB_DEVICE_INTFLAG_EORST_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_EORST_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST; +} + +static inline bool hri_usbdevice_get_interrupt_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_WAKEUP) >> USB_DEVICE_INTFLAG_WAKEUP_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP; +} + +static inline bool hri_usbdevice_get_interrupt_EORSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORSM) >> USB_DEVICE_INTFLAG_EORSM_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_EORSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORSM; +} + +static inline bool hri_usbdevice_get_interrupt_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_UPRSM) >> USB_DEVICE_INTFLAG_UPRSM_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_UPRSM; +} + +static inline bool hri_usbdevice_get_interrupt_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_RAMACER) >> USB_DEVICE_INTFLAG_RAMACER_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_RAMACER; +} + +static inline bool hri_usbdevice_get_interrupt_LPMNYET_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMNYET) >> USB_DEVICE_INTFLAG_LPMNYET_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_LPMNYET_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMNYET; +} + +static inline bool hri_usbdevice_get_interrupt_LPMSUSP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMSUSP) >> USB_DEVICE_INTFLAG_LPMSUSP_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_LPMSUSP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMSUSP; +} + +static inline hri_usbdevice_intflag_reg_t hri_usbdevice_get_INTFLAG_reg(const void *const hw, + hri_usbdevice_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_intflag_reg_t hri_usbdevice_read_INTFLAG_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.INTFLAG.reg; +} + +static inline void hri_usbdevice_clear_INTFLAG_reg(const void *const hw, hri_usbdevice_intflag_reg_t mask) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = mask; +} + +static inline bool hri_usbhost_get_INTFLAG_HSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_HSOF) >> USB_HOST_INTFLAG_HSOF_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_HSOF_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_HSOF; +} + +static inline bool hri_usbhost_get_INTFLAG_RST_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RST) >> USB_HOST_INTFLAG_RST_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_RST_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST; +} + +static inline bool hri_usbhost_get_INTFLAG_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_WAKEUP) >> USB_HOST_INTFLAG_WAKEUP_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_WAKEUP; +} + +static inline bool hri_usbhost_get_INTFLAG_DNRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DNRSM) >> USB_HOST_INTFLAG_DNRSM_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_DNRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DNRSM; +} + +static inline bool hri_usbhost_get_INTFLAG_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_UPRSM) >> USB_HOST_INTFLAG_UPRSM_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_UPRSM; +} + +static inline bool hri_usbhost_get_INTFLAG_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RAMACER) >> USB_HOST_INTFLAG_RAMACER_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RAMACER; +} + +static inline bool hri_usbhost_get_INTFLAG_DCONN_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DCONN) >> USB_HOST_INTFLAG_DCONN_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_DCONN_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DCONN; +} + +static inline bool hri_usbhost_get_INTFLAG_DDISC_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DDISC) >> USB_HOST_INTFLAG_DDISC_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_DDISC_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DDISC; +} + +static inline bool hri_usbhost_get_interrupt_HSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_HSOF) >> USB_HOST_INTFLAG_HSOF_Pos; +} + +static inline void hri_usbhost_clear_interrupt_HSOF_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_HSOF; +} + +static inline bool hri_usbhost_get_interrupt_RST_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RST) >> USB_HOST_INTFLAG_RST_Pos; +} + +static inline void hri_usbhost_clear_interrupt_RST_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST; +} + +static inline bool hri_usbhost_get_interrupt_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_WAKEUP) >> USB_HOST_INTFLAG_WAKEUP_Pos; +} + +static inline void hri_usbhost_clear_interrupt_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_WAKEUP; +} + +static inline bool hri_usbhost_get_interrupt_DNRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DNRSM) >> USB_HOST_INTFLAG_DNRSM_Pos; +} + +static inline void hri_usbhost_clear_interrupt_DNRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DNRSM; +} + +static inline bool hri_usbhost_get_interrupt_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_UPRSM) >> USB_HOST_INTFLAG_UPRSM_Pos; +} + +static inline void hri_usbhost_clear_interrupt_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_UPRSM; +} + +static inline bool hri_usbhost_get_interrupt_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RAMACER) >> USB_HOST_INTFLAG_RAMACER_Pos; +} + +static inline void hri_usbhost_clear_interrupt_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RAMACER; +} + +static inline bool hri_usbhost_get_interrupt_DCONN_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DCONN) >> USB_HOST_INTFLAG_DCONN_Pos; +} + +static inline void hri_usbhost_clear_interrupt_DCONN_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DCONN; +} + +static inline bool hri_usbhost_get_interrupt_DDISC_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DDISC) >> USB_HOST_INTFLAG_DDISC_Pos; +} + +static inline void hri_usbhost_clear_interrupt_DDISC_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DDISC; +} + +static inline hri_usbhost_intflag_reg_t hri_usbhost_get_INTFLAG_reg(const void *const hw, + hri_usbhost_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_intflag_reg_t hri_usbhost_read_INTFLAG_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.INTFLAG.reg; +} + +static inline void hri_usbhost_clear_INTFLAG_reg(const void *const hw, hri_usbhost_intflag_reg_t mask) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = mask; +} + +static inline void hri_usbdevice_set_INTEN_SUSPEND_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND; +} + +static inline bool hri_usbdevice_get_INTEN_SUSPEND_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_SUSPEND) >> USB_DEVICE_INTENSET_SUSPEND_Pos; +} + +static inline void hri_usbdevice_write_INTEN_SUSPEND_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SUSPEND; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND; + } +} + +static inline void hri_usbdevice_clear_INTEN_SUSPEND_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SUSPEND; +} + +static inline void hri_usbdevice_set_INTEN_MSOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_MSOF; +} + +static inline bool hri_usbdevice_get_INTEN_MSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_MSOF) >> USB_DEVICE_INTENSET_MSOF_Pos; +} + +static inline void hri_usbdevice_write_INTEN_MSOF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_MSOF; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_MSOF; + } +} + +static inline void hri_usbdevice_clear_INTEN_MSOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_MSOF; +} + +static inline void hri_usbdevice_set_INTEN_SOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SOF; +} + +static inline bool hri_usbdevice_get_INTEN_SOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_SOF) >> USB_DEVICE_INTENSET_SOF_Pos; +} + +static inline void hri_usbdevice_write_INTEN_SOF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SOF; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SOF; + } +} + +static inline void hri_usbdevice_clear_INTEN_SOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SOF; +} + +static inline void hri_usbdevice_set_INTEN_EORST_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORST; +} + +static inline bool hri_usbdevice_get_INTEN_EORST_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_EORST) >> USB_DEVICE_INTENSET_EORST_Pos; +} + +static inline void hri_usbdevice_write_INTEN_EORST_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORST; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORST; + } +} + +static inline void hri_usbdevice_clear_INTEN_EORST_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORST; +} + +static inline void hri_usbdevice_set_INTEN_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_WAKEUP; +} + +static inline bool hri_usbdevice_get_INTEN_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_WAKEUP) >> USB_DEVICE_INTENSET_WAKEUP_Pos; +} + +static inline void hri_usbdevice_write_INTEN_WAKEUP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_WAKEUP; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_WAKEUP; + } +} + +static inline void hri_usbdevice_clear_INTEN_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_WAKEUP; +} + +static inline void hri_usbdevice_set_INTEN_EORSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORSM; +} + +static inline bool hri_usbdevice_get_INTEN_EORSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_EORSM) >> USB_DEVICE_INTENSET_EORSM_Pos; +} + +static inline void hri_usbdevice_write_INTEN_EORSM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORSM; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORSM; + } +} + +static inline void hri_usbdevice_clear_INTEN_EORSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORSM; +} + +static inline void hri_usbdevice_set_INTEN_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_UPRSM; +} + +static inline bool hri_usbdevice_get_INTEN_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_UPRSM) >> USB_DEVICE_INTENSET_UPRSM_Pos; +} + +static inline void hri_usbdevice_write_INTEN_UPRSM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_UPRSM; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_UPRSM; + } +} + +static inline void hri_usbdevice_clear_INTEN_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_UPRSM; +} + +static inline void hri_usbdevice_set_INTEN_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_RAMACER; +} + +static inline bool hri_usbdevice_get_INTEN_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_RAMACER) >> USB_DEVICE_INTENSET_RAMACER_Pos; +} + +static inline void hri_usbdevice_write_INTEN_RAMACER_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_RAMACER; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_RAMACER; + } +} + +static inline void hri_usbdevice_clear_INTEN_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_RAMACER; +} + +static inline void hri_usbdevice_set_INTEN_LPMNYET_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMNYET; +} + +static inline bool hri_usbdevice_get_INTEN_LPMNYET_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_LPMNYET) >> USB_DEVICE_INTENSET_LPMNYET_Pos; +} + +static inline void hri_usbdevice_write_INTEN_LPMNYET_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMNYET; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMNYET; + } +} + +static inline void hri_usbdevice_clear_INTEN_LPMNYET_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMNYET; +} + +static inline void hri_usbdevice_set_INTEN_LPMSUSP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMSUSP; +} + +static inline bool hri_usbdevice_get_INTEN_LPMSUSP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_LPMSUSP) >> USB_DEVICE_INTENSET_LPMSUSP_Pos; +} + +static inline void hri_usbdevice_write_INTEN_LPMSUSP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMSUSP; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMSUSP; + } +} + +static inline void hri_usbdevice_clear_INTEN_LPMSUSP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMSUSP; +} + +static inline void hri_usbdevice_set_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t mask) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = mask; +} + +static inline hri_usbdevice_intenset_reg_t hri_usbdevice_get_INTEN_reg(const void *const hw, + hri_usbdevice_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_intenset_reg_t hri_usbdevice_read_INTEN_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.INTENSET.reg; +} + +static inline void hri_usbdevice_write_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t data) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = data; + ((Usb *)hw)->DEVICE.INTENCLR.reg = ~data; +} + +static inline void hri_usbdevice_clear_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t mask) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = mask; +} + +static inline void hri_usbhost_set_INTEN_HSOF_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_HSOF; +} + +static inline bool hri_usbhost_get_INTEN_HSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_HSOF) >> USB_HOST_INTENSET_HSOF_Pos; +} + +static inline void hri_usbhost_write_INTEN_HSOF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_HSOF; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_HSOF; + } +} + +static inline void hri_usbhost_clear_INTEN_HSOF_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_HSOF; +} + +static inline void hri_usbhost_set_INTEN_RST_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RST; +} + +static inline bool hri_usbhost_get_INTEN_RST_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_RST) >> USB_HOST_INTENSET_RST_Pos; +} + +static inline void hri_usbhost_write_INTEN_RST_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RST; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RST; + } +} + +static inline void hri_usbhost_clear_INTEN_RST_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RST; +} + +static inline void hri_usbhost_set_INTEN_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP; +} + +static inline bool hri_usbhost_get_INTEN_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_WAKEUP) >> USB_HOST_INTENSET_WAKEUP_Pos; +} + +static inline void hri_usbhost_write_INTEN_WAKEUP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_WAKEUP; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP; + } +} + +static inline void hri_usbhost_clear_INTEN_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_WAKEUP; +} + +static inline void hri_usbhost_set_INTEN_DNRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DNRSM; +} + +static inline bool hri_usbhost_get_INTEN_DNRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DNRSM) >> USB_HOST_INTENSET_DNRSM_Pos; +} + +static inline void hri_usbhost_write_INTEN_DNRSM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DNRSM; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DNRSM; + } +} + +static inline void hri_usbhost_clear_INTEN_DNRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DNRSM; +} + +static inline void hri_usbhost_set_INTEN_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_UPRSM; +} + +static inline bool hri_usbhost_get_INTEN_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_UPRSM) >> USB_HOST_INTENSET_UPRSM_Pos; +} + +static inline void hri_usbhost_write_INTEN_UPRSM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_UPRSM; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_UPRSM; + } +} + +static inline void hri_usbhost_clear_INTEN_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_UPRSM; +} + +static inline void hri_usbhost_set_INTEN_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RAMACER; +} + +static inline bool hri_usbhost_get_INTEN_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_RAMACER) >> USB_HOST_INTENSET_RAMACER_Pos; +} + +static inline void hri_usbhost_write_INTEN_RAMACER_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RAMACER; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RAMACER; + } +} + +static inline void hri_usbhost_clear_INTEN_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RAMACER; +} + +static inline void hri_usbhost_set_INTEN_DCONN_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN; +} + +static inline bool hri_usbhost_get_INTEN_DCONN_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DCONN) >> USB_HOST_INTENSET_DCONN_Pos; +} + +static inline void hri_usbhost_write_INTEN_DCONN_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DCONN; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN; + } +} + +static inline void hri_usbhost_clear_INTEN_DCONN_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DCONN; +} + +static inline void hri_usbhost_set_INTEN_DDISC_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC; +} + +static inline bool hri_usbhost_get_INTEN_DDISC_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DDISC) >> USB_HOST_INTENSET_DDISC_Pos; +} + +static inline void hri_usbhost_write_INTEN_DDISC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DDISC; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC; + } +} + +static inline void hri_usbhost_clear_INTEN_DDISC_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DDISC; +} + +static inline void hri_usbhost_set_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t mask) +{ + ((Usb *)hw)->HOST.INTENSET.reg = mask; +} + +static inline hri_usbhost_intenset_reg_t hri_usbhost_get_INTEN_reg(const void *const hw, + hri_usbhost_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_intenset_reg_t hri_usbhost_read_INTEN_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.INTENSET.reg; +} + +static inline void hri_usbhost_write_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t data) +{ + ((Usb *)hw)->HOST.INTENSET.reg = data; + ((Usb *)hw)->HOST.INTENCLR.reg = ~data; +} + +static inline void hri_usbhost_clear_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t mask) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = mask; +} + +static inline bool hri_usb_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.SYNCBUSY.reg & USB_SYNCBUSY_SWRST) >> USB_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_usb_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.SYNCBUSY.reg & USB_SYNCBUSY_ENABLE) >> USB_SYNCBUSY_ENABLE_Pos; +} + +static inline hri_usb_syncbusy_reg_t hri_usb_get_SYNCBUSY_reg(const void *const hw, hri_usb_syncbusy_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usb_syncbusy_reg_t hri_usb_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.SYNCBUSY.reg; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_SPEED_bf(const void *const hw, + hri_usbdevice_status_reg_t mask) +{ + return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED(mask)) >> USB_DEVICE_STATUS_SPEED_Pos; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_SPEED_bf(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED_Msk) >> USB_DEVICE_STATUS_SPEED_Pos; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_LINESTATE_bf(const void *const hw, + hri_usbdevice_status_reg_t mask) +{ + return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_LINESTATE(mask)) >> USB_DEVICE_STATUS_LINESTATE_Pos; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_LINESTATE_bf(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_LINESTATE_Msk) >> USB_DEVICE_STATUS_LINESTATE_Pos; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_reg(const void *const hw, + hri_usbdevice_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.STATUS.reg; +} + +static inline hri_usb_fsmstatus_reg_t hri_usb_get_FSMSTATUS_FSMSTATE_bf(const void *const hw, + hri_usb_fsmstatus_reg_t mask) +{ + return (((Usb *)hw)->HOST.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE(mask)) >> USB_FSMSTATUS_FSMSTATE_Pos; +} + +static inline hri_usb_fsmstatus_reg_t hri_usb_read_FSMSTATUS_FSMSTATE_bf(const void *const hw) +{ + return (((Usb *)hw)->HOST.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE_Msk) >> USB_FSMSTATUS_FSMSTATE_Pos; +} + +static inline hri_usb_fsmstatus_reg_t hri_usb_get_FSMSTATUS_reg(const void *const hw, hri_usb_fsmstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.FSMSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usb_fsmstatus_reg_t hri_usb_read_FSMSTATUS_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.FSMSTATUS.reg; +} + +static inline bool hri_usbdevice_get_FNUM_FNCERR_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNCERR) >> USB_DEVICE_FNUM_FNCERR_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_MFNUM_bf(const void *const hw, + hri_usbdevice_fnum_reg_t mask) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_MFNUM(mask)) >> USB_DEVICE_FNUM_MFNUM_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_MFNUM_bf(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_MFNUM_Msk) >> USB_DEVICE_FNUM_MFNUM_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_FNUM_bf(const void *const hw, + hri_usbdevice_fnum_reg_t mask) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNUM(mask)) >> USB_DEVICE_FNUM_FNUM_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_FNUM_bf(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNUM_Msk) >> USB_DEVICE_FNUM_FNUM_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_reg(const void *const hw, hri_usbdevice_fnum_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.FNUM.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.FNUM.reg; +} + +static inline hri_usbhost_flenhigh_reg_t hri_usbhost_get_FLENHIGH_FLENHIGH_bf(const void *const hw, + hri_usbhost_flenhigh_reg_t mask) +{ + return (((Usb *)hw)->HOST.FLENHIGH.reg & USB_HOST_FLENHIGH_FLENHIGH(mask)) >> USB_HOST_FLENHIGH_FLENHIGH_Pos; +} + +static inline hri_usbhost_flenhigh_reg_t hri_usbhost_read_FLENHIGH_FLENHIGH_bf(const void *const hw) +{ + return (((Usb *)hw)->HOST.FLENHIGH.reg & USB_HOST_FLENHIGH_FLENHIGH_Msk) >> USB_HOST_FLENHIGH_FLENHIGH_Pos; +} + +static inline hri_usbhost_flenhigh_reg_t hri_usbhost_get_FLENHIGH_reg(const void *const hw, + hri_usbhost_flenhigh_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.FLENHIGH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_flenhigh_reg_t hri_usbhost_read_FLENHIGH_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.FLENHIGH.reg; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT0_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT0) >> USB_DEVICE_EPINTSMRY_EPINT0_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT1_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT1) >> USB_DEVICE_EPINTSMRY_EPINT1_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT2_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT2) >> USB_DEVICE_EPINTSMRY_EPINT2_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT3_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT3) >> USB_DEVICE_EPINTSMRY_EPINT3_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT4_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT4) >> USB_DEVICE_EPINTSMRY_EPINT4_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT5_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT5) >> USB_DEVICE_EPINTSMRY_EPINT5_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT6_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT6) >> USB_DEVICE_EPINTSMRY_EPINT6_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT7_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT7) >> USB_DEVICE_EPINTSMRY_EPINT7_Pos; +} + +static inline hri_usbdevice_epintsmry_reg_t hri_usbdevice_get_EPINTSMRY_reg(const void *const hw, + hri_usbdevice_epintsmry_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.EPINTSMRY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_epintsmry_reg_t hri_usbdevice_read_EPINTSMRY_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.EPINTSMRY.reg; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT0_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT0) >> USB_HOST_PINTSMRY_EPINT0_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT1_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT1) >> USB_HOST_PINTSMRY_EPINT1_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT2_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT2) >> USB_HOST_PINTSMRY_EPINT2_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT3_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT3) >> USB_HOST_PINTSMRY_EPINT3_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT4_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT4) >> USB_HOST_PINTSMRY_EPINT4_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT5_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT5) >> USB_HOST_PINTSMRY_EPINT5_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT6_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT6) >> USB_HOST_PINTSMRY_EPINT6_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT7_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT7) >> USB_HOST_PINTSMRY_EPINT7_Pos; +} + +static inline hri_usbhost_pintsmry_reg_t hri_usbhost_get_PINTSMRY_reg(const void *const hw, + hri_usbhost_pintsmry_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PINTSMRY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_pintsmry_reg_t hri_usbhost_read_PINTSMRY_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.PINTSMRY.reg; +} + +static inline void hri_usb_set_CTRLA_SWRST_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_SWRST; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usb_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp = (tmp & USB_CTRLA_SWRST) >> USB_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_usb_set_CTRLA_ENABLE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_ENABLE; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usb_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp = (tmp & USB_CTRLA_ENABLE) >> USB_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_usb_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp &= ~USB_CTRLA_ENABLE; + tmp |= value << USB_CTRLA_ENABLE_Pos; + ((Usb *)hw)->HOST.CTRLA.reg = tmp; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_ENABLE; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_ENABLE; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_RUNSTDBY; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usb_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp = (tmp & USB_CTRLA_RUNSTDBY) >> USB_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_usb_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp &= ~USB_CTRLA_RUNSTDBY; + tmp |= value << USB_CTRLA_RUNSTDBY_Pos; + ((Usb *)hw)->HOST.CTRLA.reg = tmp; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_RUNSTDBY; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_RUNSTDBY; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_set_CTRLA_MODE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_MODE; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usb_get_CTRLA_MODE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp = (tmp & USB_CTRLA_MODE) >> USB_CTRLA_MODE_Pos; + return (bool)tmp; +} + +static inline void hri_usb_write_CTRLA_MODE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp &= ~USB_CTRLA_MODE; + tmp |= value << USB_CTRLA_MODE_Pos; + ((Usb *)hw)->HOST.CTRLA.reg = tmp; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_CTRLA_MODE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_MODE; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_CTRLA_MODE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_MODE; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_set_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg |= mask; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_ctrla_reg_t hri_usb_get_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usb_write_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg = data; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg &= ~mask; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg ^= mask; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_ctrla_reg_t hri_usb_read_CTRLA_reg(const void *const hw) +{ + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + return ((Usb *)hw)->HOST.CTRLA.reg; +} + +static inline void hri_usb_set_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg |= USB_QOSCTRL_CQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_CQOS(mask)) >> USB_QOSCTRL_CQOS_Pos; + return tmp; +} + +static inline void hri_usb_write_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp &= ~USB_QOSCTRL_CQOS_Msk; + tmp |= USB_QOSCTRL_CQOS(data); + ((Usb *)hw)->HOST.QOSCTRL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg &= ~USB_QOSCTRL_CQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg ^= USB_QOSCTRL_CQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_CQOS_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_CQOS_Msk) >> USB_QOSCTRL_CQOS_Pos; + return tmp; +} + +static inline void hri_usb_set_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg |= USB_QOSCTRL_DQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_DQOS(mask)) >> USB_QOSCTRL_DQOS_Pos; + return tmp; +} + +static inline void hri_usb_write_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp &= ~USB_QOSCTRL_DQOS_Msk; + tmp |= USB_QOSCTRL_DQOS(data); + ((Usb *)hw)->HOST.QOSCTRL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg &= ~USB_QOSCTRL_DQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg ^= USB_QOSCTRL_DQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_DQOS_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_DQOS_Msk) >> USB_QOSCTRL_DQOS_Pos; + return tmp; +} + +static inline void hri_usb_set_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usb_write_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.QOSCTRL.reg; +} + +static inline void hri_usbdevice_set_CTRLB_DETACH_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_DETACH; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_DETACH_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_DETACH) >> USB_DEVICE_CTRLB_DETACH_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_DETACH_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_DETACH; + tmp |= value << USB_DEVICE_CTRLB_DETACH_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_DETACH_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_DETACH; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_DETACH_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_DETACH; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_UPRSM_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_UPRSM; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_UPRSM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_UPRSM) >> USB_DEVICE_CTRLB_UPRSM_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_UPRSM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_UPRSM; + tmp |= value << USB_DEVICE_CTRLB_UPRSM_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_UPRSM_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_UPRSM; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_UPRSM_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_UPRSM; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_NREPLY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_NREPLY; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_NREPLY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_NREPLY) >> USB_DEVICE_CTRLB_NREPLY_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_NREPLY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_NREPLY; + tmp |= value << USB_DEVICE_CTRLB_NREPLY_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_NREPLY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_NREPLY; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_NREPLY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_NREPLY; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_TSTJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_TSTJ) >> USB_DEVICE_CTRLB_TSTJ_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_TSTJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_TSTJ; + tmp |= value << USB_DEVICE_CTRLB_TSTJ_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_TSTK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_TSTK) >> USB_DEVICE_CTRLB_TSTK_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_TSTK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_TSTK; + tmp |= value << USB_DEVICE_CTRLB_TSTK_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_TSTPCKT_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTPCKT; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_TSTPCKT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_TSTPCKT) >> USB_DEVICE_CTRLB_TSTPCKT_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_TSTPCKT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_TSTPCKT; + tmp |= value << USB_DEVICE_CTRLB_TSTPCKT_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_TSTPCKT_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTPCKT; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_TSTPCKT_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTPCKT; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_OPMODE2_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_OPMODE2; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_OPMODE2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_OPMODE2) >> USB_DEVICE_CTRLB_OPMODE2_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_OPMODE2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_OPMODE2; + tmp |= value << USB_DEVICE_CTRLB_OPMODE2_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_OPMODE2_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_OPMODE2; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_OPMODE2_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_OPMODE2; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_GNAK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_GNAK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_GNAK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_GNAK) >> USB_DEVICE_CTRLB_GNAK_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_GNAK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_GNAK; + tmp |= value << USB_DEVICE_CTRLB_GNAK_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_GNAK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_GNAK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_GNAK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_GNAK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_SPDCONF_bf(const void *const hw, + hri_usbdevice_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_SPDCONF(mask)) >> USB_DEVICE_CTRLB_SPDCONF_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_SPDCONF_Msk; + tmp |= USB_DEVICE_CTRLB_SPDCONF(data); + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_SPDCONF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_SPDCONF_Msk) >> USB_DEVICE_CTRLB_SPDCONF_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_LPMHDSK(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_LPMHDSK_bf(const void *const hw, + hri_usbdevice_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_LPMHDSK(mask)) >> USB_DEVICE_CTRLB_LPMHDSK_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_LPMHDSK_Msk; + tmp |= USB_DEVICE_CTRLB_LPMHDSK(data); + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_LPMHDSK(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_LPMHDSK(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_LPMHDSK_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_LPMHDSK_Msk) >> USB_DEVICE_CTRLB_LPMHDSK_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_reg(const void *const hw, + hri_usbdevice_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevice_write_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.CTRLB.reg; +} + +static inline void hri_usbhost_set_CTRLB_RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_RESUME_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_RESUME) >> USB_HOST_CTRLB_RESUME_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_RESUME_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_RESUME; + tmp |= value << USB_HOST_CTRLB_RESUME_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_AUTORESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_AUTORESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_AUTORESUME_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_AUTORESUME) >> USB_HOST_CTRLB_AUTORESUME_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_AUTORESUME_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_AUTORESUME; + tmp |= value << USB_HOST_CTRLB_AUTORESUME_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_AUTORESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_AUTORESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_AUTORESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_AUTORESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_TSTJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_TSTJ) >> USB_HOST_CTRLB_TSTJ_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_TSTJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_TSTJ; + tmp |= value << USB_HOST_CTRLB_TSTJ_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_TSTK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_TSTK) >> USB_HOST_CTRLB_TSTK_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_TSTK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_TSTK; + tmp |= value << USB_HOST_CTRLB_TSTK_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_SOFE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_SOFE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_SOFE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_SOFE) >> USB_HOST_CTRLB_SOFE_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_SOFE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_SOFE; + tmp |= value << USB_HOST_CTRLB_SOFE_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_SOFE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_SOFE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_SOFE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_SOFE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_BUSRESET_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_BUSRESET; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_BUSRESET_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_BUSRESET) >> USB_HOST_CTRLB_BUSRESET_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_BUSRESET_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_BUSRESET; + tmp |= value << USB_HOST_CTRLB_BUSRESET_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_BUSRESET_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_BUSRESET; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_BUSRESET_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_BUSRESET; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_VBUSOK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_VBUSOK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_VBUSOK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_VBUSOK) >> USB_HOST_CTRLB_VBUSOK_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_VBUSOK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_VBUSOK; + tmp |= value << USB_HOST_CTRLB_VBUSOK_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_VBUSOK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_VBUSOK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_VBUSOK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_VBUSOK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_L1RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_L1RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_L1RESUME_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_L1RESUME) >> USB_HOST_CTRLB_L1RESUME_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_L1RESUME_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_L1RESUME; + tmp |= value << USB_HOST_CTRLB_L1RESUME_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_L1RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_L1RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_L1RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_L1RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_ctrlb_reg_t hri_usbhost_get_CTRLB_SPDCONF_bf(const void *const hw, + hri_usbhost_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_SPDCONF(mask)) >> USB_HOST_CTRLB_SPDCONF_Pos; + return tmp; +} + +static inline void hri_usbhost_write_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_SPDCONF_Msk; + tmp |= USB_HOST_CTRLB_SPDCONF(data); + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_ctrlb_reg_t hri_usbhost_read_CTRLB_SPDCONF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_SPDCONF_Msk) >> USB_HOST_CTRLB_SPDCONF_Pos; + return tmp; +} + +static inline void hri_usbhost_set_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_ctrlb_reg_t hri_usbhost_get_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_ctrlb_reg_t hri_usbhost_read_CTRLB_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.CTRLB.reg; +} + +static inline void hri_usbdevice_set_DADD_ADDEN_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg |= USB_DEVICE_DADD_ADDEN; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_DADD_ADDEN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp = (tmp & USB_DEVICE_DADD_ADDEN) >> USB_DEVICE_DADD_ADDEN_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_DADD_ADDEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp &= ~USB_DEVICE_DADD_ADDEN; + tmp |= value << USB_DEVICE_DADD_ADDEN_Pos; + ((Usb *)hw)->DEVICE.DADD.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_DADD_ADDEN_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg &= ~USB_DEVICE_DADD_ADDEN; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_DADD_ADDEN_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg ^= USB_DEVICE_DADD_ADDEN; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg |= USB_DEVICE_DADD_DADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_dadd_reg_t hri_usbdevice_get_DADD_DADD_bf(const void *const hw, + hri_usbdevice_dadd_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp = (tmp & USB_DEVICE_DADD_DADD(mask)) >> USB_DEVICE_DADD_DADD_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp &= ~USB_DEVICE_DADD_DADD_Msk; + tmp |= USB_DEVICE_DADD_DADD(data); + ((Usb *)hw)->DEVICE.DADD.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg &= ~USB_DEVICE_DADD_DADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg ^= USB_DEVICE_DADD_DADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_dadd_reg_t hri_usbdevice_read_DADD_DADD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp = (tmp & USB_DEVICE_DADD_DADD_Msk) >> USB_DEVICE_DADD_DADD_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_dadd_reg_t hri_usbdevice_get_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevice_write_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_dadd_reg_t hri_usbdevice_read_DADD_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.DADD.reg; +} + +static inline void hri_usbhost_set_HSOFC_FLENCE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg |= USB_HOST_HSOFC_FLENCE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_HSOFC_FLENCE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp = (tmp & USB_HOST_HSOFC_FLENCE) >> USB_HOST_HSOFC_FLENCE_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_HSOFC_FLENCE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp &= ~USB_HOST_HSOFC_FLENCE; + tmp |= value << USB_HOST_HSOFC_FLENCE_Pos; + ((Usb *)hw)->HOST.HSOFC.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_HSOFC_FLENCE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg &= ~USB_HOST_HSOFC_FLENCE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_HSOFC_FLENCE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg ^= USB_HOST_HSOFC_FLENCE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg |= USB_HOST_HSOFC_FLENC(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_hsofc_reg_t hri_usbhost_get_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp = (tmp & USB_HOST_HSOFC_FLENC(mask)) >> USB_HOST_HSOFC_FLENC_Pos; + return tmp; +} + +static inline void hri_usbhost_write_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp &= ~USB_HOST_HSOFC_FLENC_Msk; + tmp |= USB_HOST_HSOFC_FLENC(data); + ((Usb *)hw)->HOST.HSOFC.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg &= ~USB_HOST_HSOFC_FLENC(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg ^= USB_HOST_HSOFC_FLENC(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_hsofc_reg_t hri_usbhost_read_HSOFC_FLENC_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp = (tmp & USB_HOST_HSOFC_FLENC_Msk) >> USB_HOST_HSOFC_FLENC_Pos; + return tmp; +} + +static inline void hri_usbhost_set_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_hsofc_reg_t hri_usbhost_get_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_hsofc_reg_t hri_usbhost_read_HSOFC_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.HSOFC.reg; +} + +static inline void hri_usbhost_set_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg |= USB_HOST_FNUM_MFNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp = (tmp & USB_HOST_FNUM_MFNUM(mask)) >> USB_HOST_FNUM_MFNUM_Pos; + return tmp; +} + +static inline void hri_usbhost_write_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp &= ~USB_HOST_FNUM_MFNUM_Msk; + tmp |= USB_HOST_FNUM_MFNUM(data); + ((Usb *)hw)->HOST.FNUM.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg &= ~USB_HOST_FNUM_MFNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg ^= USB_HOST_FNUM_MFNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_MFNUM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp = (tmp & USB_HOST_FNUM_MFNUM_Msk) >> USB_HOST_FNUM_MFNUM_Pos; + return tmp; +} + +static inline void hri_usbhost_set_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg |= USB_HOST_FNUM_FNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp = (tmp & USB_HOST_FNUM_FNUM(mask)) >> USB_HOST_FNUM_FNUM_Pos; + return tmp; +} + +static inline void hri_usbhost_write_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp &= ~USB_HOST_FNUM_FNUM_Msk; + tmp |= USB_HOST_FNUM_FNUM(data); + ((Usb *)hw)->HOST.FNUM.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg &= ~USB_HOST_FNUM_FNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg ^= USB_HOST_FNUM_FNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_FNUM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp = (tmp & USB_HOST_FNUM_FNUM_Msk) >> USB_HOST_FNUM_FNUM_Pos; + return tmp; +} + +static inline void hri_usbhost_set_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.FNUM.reg; +} + +static inline void hri_usb_set_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg |= USB_DESCADD_DESCADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_descadd_reg_t hri_usb_get_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usb *)hw)->HOST.DESCADD.reg; + tmp = (tmp & USB_DESCADD_DESCADD(mask)) >> USB_DESCADD_DESCADD_Pos; + return tmp; +} + +static inline void hri_usb_write_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.DESCADD.reg; + tmp &= ~USB_DESCADD_DESCADD_Msk; + tmp |= USB_DESCADD_DESCADD(data); + ((Usb *)hw)->HOST.DESCADD.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg &= ~USB_DESCADD_DESCADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg ^= USB_DESCADD_DESCADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_descadd_reg_t hri_usb_read_DESCADD_DESCADD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usb *)hw)->HOST.DESCADD.reg; + tmp = (tmp & USB_DESCADD_DESCADD_Msk) >> USB_DESCADD_DESCADD_Pos; + return tmp; +} + +static inline void hri_usb_set_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_descadd_reg_t hri_usb_get_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usb *)hw)->HOST.DESCADD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usb_write_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_descadd_reg_t hri_usb_read_DESCADD_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.DESCADD.reg; +} + +static inline void hri_usb_set_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRANSP(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSP(mask)) >> USB_PADCAL_TRANSP_Pos; + return tmp; +} + +static inline void hri_usb_write_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp &= ~USB_PADCAL_TRANSP_Msk; + tmp |= USB_PADCAL_TRANSP(data); + ((Usb *)hw)->HOST.PADCAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRANSP(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRANSP(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRANSP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSP_Msk) >> USB_PADCAL_TRANSP_Pos; + return tmp; +} + +static inline void hri_usb_set_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRANSN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSN(mask)) >> USB_PADCAL_TRANSN_Pos; + return tmp; +} + +static inline void hri_usb_write_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp &= ~USB_PADCAL_TRANSN_Msk; + tmp |= USB_PADCAL_TRANSN(data); + ((Usb *)hw)->HOST.PADCAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRANSN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRANSN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRANSN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSN_Msk) >> USB_PADCAL_TRANSN_Pos; + return tmp; +} + +static inline void hri_usb_set_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRIM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRIM(mask)) >> USB_PADCAL_TRIM_Pos; + return tmp; +} + +static inline void hri_usb_write_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp &= ~USB_PADCAL_TRIM_Msk; + tmp |= USB_PADCAL_TRIM(data); + ((Usb *)hw)->HOST.PADCAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRIM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRIM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRIM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRIM_Msk) >> USB_PADCAL_TRIM_Pos; + return tmp; +} + +static inline void hri_usb_set_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usb_write_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.PADCAL.reg; +} + +static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_SPEED_bf(const void *const hw, + hri_usbhost_status_reg_t mask) +{ + return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_SPEED(mask)) >> USB_HOST_STATUS_SPEED_Pos; +} + +static inline void hri_usbhost_clear_STATUS_SPEED_bf(const void *const hw, hri_usbhost_status_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.STATUS.reg = USB_HOST_STATUS_SPEED(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_SPEED_bf(const void *const hw) +{ + return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_SPEED_Msk) >> USB_HOST_STATUS_SPEED_Pos; +} + +static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_LINESTATE_bf(const void *const hw, + hri_usbhost_status_reg_t mask) +{ + return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_LINESTATE(mask)) >> USB_HOST_STATUS_LINESTATE_Pos; +} + +static inline void hri_usbhost_clear_STATUS_LINESTATE_bf(const void *const hw, hri_usbhost_status_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.STATUS.reg = USB_HOST_STATUS_LINESTATE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_LINESTATE_bf(const void *const hw) +{ + return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_LINESTATE_Msk) >> USB_HOST_STATUS_LINESTATE_Pos; +} + +static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_reg(const void *const hw, hri_usbhost_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_clear_STATUS_reg(const void *const hw, hri_usbhost_status_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.STATUS.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.STATUS.reg; +} + +static inline void hri_usbdevicedescbank_set_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg |= USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_get_ADDR_ADDR_bf(const void *const hw, + hri_usbdesc_bank_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; + tmp = (tmp & USB_DEVICE_ADDR_ADDR(mask)) >> USB_DEVICE_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; + tmp &= ~USB_DEVICE_ADDR_ADDR_Msk; + tmp |= USB_DEVICE_ADDR_ADDR(data); + ((UsbDeviceDescBank *)hw)->ADDR.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg &= ~USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg ^= USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; + tmp = (tmp & USB_DEVICE_ADDR_ADDR_Msk) >> USB_DEVICE_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_get_ADDR_reg(const void *const hw, + hri_usbdesc_bank_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_read_ADDR_reg(const void *const hw) +{ + return ((UsbDeviceDescBank *)hw)->ADDR.reg; +} + +static inline void hri_usbdevicedescbank_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevicedescbank_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_AUTO_ZLP) >> USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevicedescbank_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; + tmp |= value << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbdevicedescbank_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT(mask)) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk; + tmp |= USB_DEVICE_PCKSIZE_BYTE_COUNT(data); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbdevicedescbank_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk; + tmp |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(data); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbdevicedescbank_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbdevicedescbank_get_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE(mask)) >> USB_DEVICE_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_PCKSIZE_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_SIZE_Msk; + tmp |= USB_DEVICE_PCKSIZE_SIZE(data); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_PCKSIZE_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_PCKSIZE_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_SIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE_Msk) >> USB_DEVICE_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_get_PCKSIZE_reg(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_reg(const void *const hw) +{ + return ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; +} + +static inline void hri_usbdevicedescbank_set_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg |= USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t +hri_usbdevicedescbank_get_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_SUBPID(mask)) >> USB_DEVICE_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_EXTREG_SUBPID_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp &= ~USB_DEVICE_EXTREG_SUBPID_Msk; + tmp |= USB_DEVICE_EXTREG_SUBPID(data); + ((UsbDeviceDescBank *)hw)->EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_EXTREG_SUBPID_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_EXTREG_SUBPID_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg ^= USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_SUBPID_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_SUBPID_Msk) >> USB_DEVICE_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg |= USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t +hri_usbdevicedescbank_get_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE(mask)) >> USB_DEVICE_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp &= ~USB_DEVICE_EXTREG_VARIABLE_Msk; + tmp |= USB_DEVICE_EXTREG_VARIABLE(data); + ((UsbDeviceDescBank *)hw)->EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg ^= USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_VARIABLE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE_Msk) >> USB_DEVICE_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_get_EXTREG_reg(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_reg(const void *const hw) +{ + return ((UsbDeviceDescBank *)hw)->EXTREG.reg; +} + +static inline bool hri_usbdevicedescbank_get_STATUS_BK_CRCERR_bit(const void *const hw) +{ + return (((UsbDeviceDescBank *)hw)->STATUS_BK.reg & USB_DEVICE_STATUS_BK_CRCERR) >> USB_DEVICE_STATUS_BK_CRCERR_Pos; +} + +static inline void hri_usbdevicedescbank_clear_STATUS_BK_CRCERR_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->STATUS_BK.reg = USB_DEVICE_STATUS_BK_CRCERR; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevicedescbank_get_STATUS_BK_ERRORFLOW_bit(const void *const hw) +{ + return (((UsbDeviceDescBank *)hw)->STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW) + >> USB_DEVICE_STATUS_BK_ERRORFLOW_Pos; +} + +static inline void hri_usbdevicedescbank_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->STATUS_BK.reg = USB_DEVICE_STATUS_BK_ERRORFLOW; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_bk_reg_t +hri_usbdevicedescbank_get_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->STATUS_BK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescbank_clear_STATUS_BK_reg(const void *const hw, + hri_usbdesc_bank_status_bk_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->STATUS_BK.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_bk_reg_t hri_usbdevicedescbank_read_STATUS_BK_reg(const void *const hw) +{ + return ((UsbDeviceDescBank *)hw)->STATUS_BK.reg; +} + +static inline void hri_usbdevicedescriptor_set_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg |= USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_addr_reg_t +hri_usbdevicedescriptor_get_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; + tmp = (tmp & USB_DEVICE_ADDR_ADDR(mask)) >> USB_DEVICE_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; + tmp &= ~USB_DEVICE_ADDR_ADDR_Msk; + tmp |= USB_DEVICE_ADDR_ADDR(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg &= ~USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg ^= USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_addr_reg_t hri_usbdevicedescriptor_read_ADDR_ADDR_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; + tmp = (tmp & USB_DEVICE_ADDR_ADDR_Msk) >> USB_DEVICE_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_addr_reg_t +hri_usbdevicedescriptor_get_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_addr_reg_t hri_usbdevicedescriptor_read_ADDR_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevicedescriptor_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_AUTO_ZLP) >> USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevicedescriptor_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; + tmp |= value << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT(mask)) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk; + tmp |= USB_DEVICE_PCKSIZE_BYTE_COUNT(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg + |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void +hri_usbdevicedescriptor_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk; + tmp |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void +hri_usbdevicedescriptor_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg + &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void +hri_usbdevicedescriptor_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg + ^= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_get_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE(mask)) >> USB_DEVICE_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_SIZE_Msk; + tmp |= USB_DEVICE_PCKSIZE_SIZE(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_read_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE_Msk) >> USB_DEVICE_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_get_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t hri_usbdevicedescriptor_read_PCKSIZE_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; +} + +static inline void hri_usbdevicedescriptor_set_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_extreg_reg_t +hri_usbdevicedescriptor_get_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_SUBPID(mask)) >> USB_DEVICE_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp &= ~USB_DEVICE_EXTREG_SUBPID_Msk; + tmp |= USB_DEVICE_EXTREG_SUBPID(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_extreg_reg_t +hri_usbdevicedescriptor_read_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_SUBPID_Msk) >> USB_DEVICE_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_extreg_reg_t +hri_usbdevicedescriptor_get_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE(mask)) >> USB_DEVICE_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp &= ~USB_DEVICE_EXTREG_VARIABLE_Msk; + tmp |= USB_DEVICE_EXTREG_VARIABLE(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_extreg_reg_t +hri_usbdevicedescriptor_read_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE_Msk) >> USB_DEVICE_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_extreg_reg_t +hri_usbdevicedescriptor_get_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_extreg_reg_t hri_usbdevicedescriptor_read_EXTREG_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; +} + +static inline bool hri_usbdevicedescriptor_get_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg & USB_DEVICE_STATUS_BK_CRCERR) + >> USB_DEVICE_STATUS_BK_CRCERR_Pos; +} + +static inline void hri_usbdevicedescriptor_clear_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = USB_DEVICE_STATUS_BK_CRCERR; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevicedescriptor_get_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW) + >> USB_DEVICE_STATUS_BK_ERRORFLOW_Pos; +} + +static inline void hri_usbdevicedescriptor_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = USB_DEVICE_STATUS_BK_ERRORFLOW; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_status_bk_reg_t +hri_usbdevicedescriptor_get_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_status_bk_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescriptor_clear_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_status_bk_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_status_bk_reg_t +hri_usbdevicedescriptor_read_STATUS_BK_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg; +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_usbdevice_wait_for_sync(a, b) hri_usb_wait_for_sync(a, b) +#define hri_usbdevice_is_syncing(a, b) hri_usb_is_syncing(a, b) +#define hri_usbhost_wait_for_sync(a, b) hri_usb_wait_for_sync(a, b) +#define hri_usbhost_is_syncing(a, b) hri_usb_is_syncing(a, b) +#define hri_usbhost_get_SYNCBUSY_SWRST_bit(a) hri_usb_get_SYNCBUSY_SWRST_bit(a) +#define hri_usbhost_get_SYNCBUSY_ENABLE_bit(a) hri_usb_get_SYNCBUSY_ENABLE_bit(a) +#define hri_usbhost_get_SYNCBUSY_reg(a, b) hri_usb_get_SYNCBUSY_reg(a, b) +#define hri_usbhost_read_SYNCBUSY_reg(a) hri_usb_read_SYNCBUSY_reg(a) +#define hri_usbhost_get_FSMSTATUS_FSMSTATE_bf(a, b) hri_usb_get_FSMSTATUS_FSMSTATE_bf(a, b) +#define hri_usbhost_read_FSMSTATUS_FSMSTATE_bf(a) hri_usb_read_FSMSTATUS_FSMSTATE_bf(a) +#define hri_usbhost_get_FSMSTATUS_reg(a, b) hri_usb_get_FSMSTATUS_reg(a, b) +#define hri_usbhost_read_FSMSTATUS_reg(a) hri_usb_read_FSMSTATUS_reg(a) +#define hri_usbhost_set_CTRLA_SWRST_bit(a) hri_usb_set_CTRLA_SWRST_bit(a) +#define hri_usbhost_get_CTRLA_SWRST_bit(a) hri_usb_get_CTRLA_SWRST_bit(a) +#define hri_usbhost_set_CTRLA_ENABLE_bit(a) hri_usb_set_CTRLA_ENABLE_bit(a) +#define hri_usbhost_get_CTRLA_ENABLE_bit(a) hri_usb_get_CTRLA_ENABLE_bit(a) +#define hri_usbhost_write_CTRLA_ENABLE_bit(a, b) hri_usb_write_CTRLA_ENABLE_bit(a, b) +#define hri_usbhost_clear_CTRLA_ENABLE_bit(a) hri_usb_clear_CTRLA_ENABLE_bit(a) +#define hri_usbhost_toggle_CTRLA_ENABLE_bit(a) hri_usb_toggle_CTRLA_ENABLE_bit(a) +#define hri_usbhost_set_CTRLA_RUNSTDBY_bit(a) hri_usb_set_CTRLA_RUNSTDBY_bit(a) +#define hri_usbhost_get_CTRLA_RUNSTDBY_bit(a) hri_usb_get_CTRLA_RUNSTDBY_bit(a) +#define hri_usbhost_write_CTRLA_RUNSTDBY_bit(a, b) hri_usb_write_CTRLA_RUNSTDBY_bit(a, b) +#define hri_usbhost_clear_CTRLA_RUNSTDBY_bit(a) hri_usb_clear_CTRLA_RUNSTDBY_bit(a) +#define hri_usbhost_toggle_CTRLA_RUNSTDBY_bit(a) hri_usb_toggle_CTRLA_RUNSTDBY_bit(a) +#define hri_usbhost_set_CTRLA_MODE_bit(a) hri_usb_set_CTRLA_MODE_bit(a) +#define hri_usbhost_get_CTRLA_MODE_bit(a) hri_usb_get_CTRLA_MODE_bit(a) +#define hri_usbhost_write_CTRLA_MODE_bit(a, b) hri_usb_write_CTRLA_MODE_bit(a, b) +#define hri_usbhost_clear_CTRLA_MODE_bit(a) hri_usb_clear_CTRLA_MODE_bit(a) +#define hri_usbhost_toggle_CTRLA_MODE_bit(a) hri_usb_toggle_CTRLA_MODE_bit(a) +#define hri_usbhost_set_CTRLA_reg(a, b) hri_usb_set_CTRLA_reg(a, b) +#define hri_usbhost_get_CTRLA_reg(a, b) hri_usb_get_CTRLA_reg(a, b) +#define hri_usbhost_write_CTRLA_reg(a, b) hri_usb_write_CTRLA_reg(a, b) +#define hri_usbhost_clear_CTRLA_reg(a, b) hri_usb_clear_CTRLA_reg(a, b) +#define hri_usbhost_toggle_CTRLA_reg(a, b) hri_usb_toggle_CTRLA_reg(a, b) +#define hri_usbhost_read_CTRLA_reg(a) hri_usb_read_CTRLA_reg(a) +#define hri_usbhost_set_QOSCTRL_CQOS_bf(a, b) hri_usb_set_QOSCTRL_CQOS_bf(a, b) +#define hri_usbhost_get_QOSCTRL_CQOS_bf(a, b) hri_usb_get_QOSCTRL_CQOS_bf(a, b) +#define hri_usbhost_write_QOSCTRL_CQOS_bf(a, b) hri_usb_write_QOSCTRL_CQOS_bf(a, b) +#define hri_usbhost_clear_QOSCTRL_CQOS_bf(a, b) hri_usb_clear_QOSCTRL_CQOS_bf(a, b) +#define hri_usbhost_toggle_QOSCTRL_CQOS_bf(a, b) hri_usb_toggle_QOSCTRL_CQOS_bf(a, b) +#define hri_usbhost_read_QOSCTRL_CQOS_bf(a) hri_usb_read_QOSCTRL_CQOS_bf(a) +#define hri_usbhost_set_QOSCTRL_DQOS_bf(a, b) hri_usb_set_QOSCTRL_DQOS_bf(a, b) +#define hri_usbhost_get_QOSCTRL_DQOS_bf(a, b) hri_usb_get_QOSCTRL_DQOS_bf(a, b) +#define hri_usbhost_write_QOSCTRL_DQOS_bf(a, b) hri_usb_write_QOSCTRL_DQOS_bf(a, b) +#define hri_usbhost_clear_QOSCTRL_DQOS_bf(a, b) hri_usb_clear_QOSCTRL_DQOS_bf(a, b) +#define hri_usbhost_toggle_QOSCTRL_DQOS_bf(a, b) hri_usb_toggle_QOSCTRL_DQOS_bf(a, b) +#define hri_usbhost_read_QOSCTRL_DQOS_bf(a) hri_usb_read_QOSCTRL_DQOS_bf(a) +#define hri_usbhost_set_QOSCTRL_reg(a, b) hri_usb_set_QOSCTRL_reg(a, b) +#define hri_usbhost_get_QOSCTRL_reg(a, b) hri_usb_get_QOSCTRL_reg(a, b) +#define hri_usbhost_write_QOSCTRL_reg(a, b) hri_usb_write_QOSCTRL_reg(a, b) +#define hri_usbhost_clear_QOSCTRL_reg(a, b) hri_usb_clear_QOSCTRL_reg(a, b) +#define hri_usbhost_toggle_QOSCTRL_reg(a, b) hri_usb_toggle_QOSCTRL_reg(a, b) +#define hri_usbhost_read_QOSCTRL_reg(a) hri_usb_read_QOSCTRL_reg(a) +#define hri_usbhost_set_DESCADD_DESCADD_bf(a, b) hri_usb_set_DESCADD_DESCADD_bf(a, b) +#define hri_usbhost_get_DESCADD_DESCADD_bf(a, b) hri_usb_get_DESCADD_DESCADD_bf(a, b) +#define hri_usbhost_write_DESCADD_DESCADD_bf(a, b) hri_usb_write_DESCADD_DESCADD_bf(a, b) +#define hri_usbhost_clear_DESCADD_DESCADD_bf(a, b) hri_usb_clear_DESCADD_DESCADD_bf(a, b) +#define hri_usbhost_toggle_DESCADD_DESCADD_bf(a, b) hri_usb_toggle_DESCADD_DESCADD_bf(a, b) +#define hri_usbhost_read_DESCADD_DESCADD_bf(a) hri_usb_read_DESCADD_DESCADD_bf(a) +#define hri_usbhost_set_DESCADD_reg(a, b) hri_usb_set_DESCADD_reg(a, b) +#define hri_usbhost_get_DESCADD_reg(a, b) hri_usb_get_DESCADD_reg(a, b) +#define hri_usbhost_write_DESCADD_reg(a, b) hri_usb_write_DESCADD_reg(a, b) +#define hri_usbhost_clear_DESCADD_reg(a, b) hri_usb_clear_DESCADD_reg(a, b) +#define hri_usbhost_toggle_DESCADD_reg(a, b) hri_usb_toggle_DESCADD_reg(a, b) +#define hri_usbhost_read_DESCADD_reg(a) hri_usb_read_DESCADD_reg(a) +#define hri_usbhost_set_PADCAL_TRANSP_bf(a, b) hri_usb_set_PADCAL_TRANSP_bf(a, b) +#define hri_usbhost_get_PADCAL_TRANSP_bf(a, b) hri_usb_get_PADCAL_TRANSP_bf(a, b) +#define hri_usbhost_write_PADCAL_TRANSP_bf(a, b) hri_usb_write_PADCAL_TRANSP_bf(a, b) +#define hri_usbhost_clear_PADCAL_TRANSP_bf(a, b) hri_usb_clear_PADCAL_TRANSP_bf(a, b) +#define hri_usbhost_toggle_PADCAL_TRANSP_bf(a, b) hri_usb_toggle_PADCAL_TRANSP_bf(a, b) +#define hri_usbhost_read_PADCAL_TRANSP_bf(a) hri_usb_read_PADCAL_TRANSP_bf(a) +#define hri_usbhost_set_PADCAL_TRANSN_bf(a, b) hri_usb_set_PADCAL_TRANSN_bf(a, b) +#define hri_usbhost_get_PADCAL_TRANSN_bf(a, b) hri_usb_get_PADCAL_TRANSN_bf(a, b) +#define hri_usbhost_write_PADCAL_TRANSN_bf(a, b) hri_usb_write_PADCAL_TRANSN_bf(a, b) +#define hri_usbhost_clear_PADCAL_TRANSN_bf(a, b) hri_usb_clear_PADCAL_TRANSN_bf(a, b) +#define hri_usbhost_toggle_PADCAL_TRANSN_bf(a, b) hri_usb_toggle_PADCAL_TRANSN_bf(a, b) +#define hri_usbhost_read_PADCAL_TRANSN_bf(a) hri_usb_read_PADCAL_TRANSN_bf(a) +#define hri_usbhost_set_PADCAL_TRIM_bf(a, b) hri_usb_set_PADCAL_TRIM_bf(a, b) +#define hri_usbhost_get_PADCAL_TRIM_bf(a, b) hri_usb_get_PADCAL_TRIM_bf(a, b) +#define hri_usbhost_write_PADCAL_TRIM_bf(a, b) hri_usb_write_PADCAL_TRIM_bf(a, b) +#define hri_usbhost_clear_PADCAL_TRIM_bf(a, b) hri_usb_clear_PADCAL_TRIM_bf(a, b) +#define hri_usbhost_toggle_PADCAL_TRIM_bf(a, b) hri_usb_toggle_PADCAL_TRIM_bf(a, b) +#define hri_usbhost_read_PADCAL_TRIM_bf(a) hri_usb_read_PADCAL_TRIM_bf(a) +#define hri_usbhost_set_PADCAL_reg(a, b) hri_usb_set_PADCAL_reg(a, b) +#define hri_usbhost_get_PADCAL_reg(a, b) hri_usb_get_PADCAL_reg(a, b) +#define hri_usbhost_write_PADCAL_reg(a, b) hri_usb_write_PADCAL_reg(a, b) +#define hri_usbhost_clear_PADCAL_reg(a, b) hri_usb_clear_PADCAL_reg(a, b) +#define hri_usbhost_toggle_PADCAL_reg(a, b) hri_usb_toggle_PADCAL_reg(a, b) +#define hri_usbhost_read_PADCAL_reg(a) hri_usb_read_PADCAL_reg(a) +#define hri_usbdevice_get_SYNCBUSY_SWRST_bit(a) hri_usb_get_SYNCBUSY_SWRST_bit(a) +#define hri_usbdevice_get_SYNCBUSY_ENABLE_bit(a) hri_usb_get_SYNCBUSY_ENABLE_bit(a) +#define hri_usbdevice_get_SYNCBUSY_reg(a, b) hri_usb_get_SYNCBUSY_reg(a, b) +#define hri_usbdevice_read_SYNCBUSY_reg(a) hri_usb_read_SYNCBUSY_reg(a) +#define hri_usbdevice_get_FSMSTATUS_FSMSTATE_bf(a, b) hri_usb_get_FSMSTATUS_FSMSTATE_bf(a, b) +#define hri_usbdevice_read_FSMSTATUS_FSMSTATE_bf(a) hri_usb_read_FSMSTATUS_FSMSTATE_bf(a) +#define hri_usbdevice_get_FSMSTATUS_reg(a, b) hri_usb_get_FSMSTATUS_reg(a, b) +#define hri_usbdevice_read_FSMSTATUS_reg(a) hri_usb_read_FSMSTATUS_reg(a) +#define hri_usbdevice_set_CTRLA_SWRST_bit(a) hri_usb_set_CTRLA_SWRST_bit(a) +#define hri_usbdevice_get_CTRLA_SWRST_bit(a) hri_usb_get_CTRLA_SWRST_bit(a) +#define hri_usbdevice_set_CTRLA_ENABLE_bit(a) hri_usb_set_CTRLA_ENABLE_bit(a) +#define hri_usbdevice_get_CTRLA_ENABLE_bit(a) hri_usb_get_CTRLA_ENABLE_bit(a) +#define hri_usbdevice_write_CTRLA_ENABLE_bit(a, b) hri_usb_write_CTRLA_ENABLE_bit(a, b) +#define hri_usbdevice_clear_CTRLA_ENABLE_bit(a) hri_usb_clear_CTRLA_ENABLE_bit(a) +#define hri_usbdevice_toggle_CTRLA_ENABLE_bit(a) hri_usb_toggle_CTRLA_ENABLE_bit(a) +#define hri_usbdevice_set_CTRLA_RUNSTDBY_bit(a) hri_usb_set_CTRLA_RUNSTDBY_bit(a) +#define hri_usbdevice_get_CTRLA_RUNSTDBY_bit(a) hri_usb_get_CTRLA_RUNSTDBY_bit(a) +#define hri_usbdevice_write_CTRLA_RUNSTDBY_bit(a, b) hri_usb_write_CTRLA_RUNSTDBY_bit(a, b) +#define hri_usbdevice_clear_CTRLA_RUNSTDBY_bit(a) hri_usb_clear_CTRLA_RUNSTDBY_bit(a) +#define hri_usbdevice_toggle_CTRLA_RUNSTDBY_bit(a) hri_usb_toggle_CTRLA_RUNSTDBY_bit(a) +#define hri_usbdevice_set_CTRLA_MODE_bit(a) hri_usb_set_CTRLA_MODE_bit(a) +#define hri_usbdevice_get_CTRLA_MODE_bit(a) hri_usb_get_CTRLA_MODE_bit(a) +#define hri_usbdevice_write_CTRLA_MODE_bit(a, b) hri_usb_write_CTRLA_MODE_bit(a, b) +#define hri_usbdevice_clear_CTRLA_MODE_bit(a) hri_usb_clear_CTRLA_MODE_bit(a) +#define hri_usbdevice_toggle_CTRLA_MODE_bit(a) hri_usb_toggle_CTRLA_MODE_bit(a) +#define hri_usbdevice_set_CTRLA_reg(a, b) hri_usb_set_CTRLA_reg(a, b) +#define hri_usbdevice_get_CTRLA_reg(a, b) hri_usb_get_CTRLA_reg(a, b) +#define hri_usbdevice_write_CTRLA_reg(a, b) hri_usb_write_CTRLA_reg(a, b) +#define hri_usbdevice_clear_CTRLA_reg(a, b) hri_usb_clear_CTRLA_reg(a, b) +#define hri_usbdevice_toggle_CTRLA_reg(a, b) hri_usb_toggle_CTRLA_reg(a, b) +#define hri_usbdevice_read_CTRLA_reg(a) hri_usb_read_CTRLA_reg(a) +#define hri_usbdevice_set_QOSCTRL_CQOS_bf(a, b) hri_usb_set_QOSCTRL_CQOS_bf(a, b) +#define hri_usbdevice_get_QOSCTRL_CQOS_bf(a, b) hri_usb_get_QOSCTRL_CQOS_bf(a, b) +#define hri_usbdevice_write_QOSCTRL_CQOS_bf(a, b) hri_usb_write_QOSCTRL_CQOS_bf(a, b) +#define hri_usbdevice_clear_QOSCTRL_CQOS_bf(a, b) hri_usb_clear_QOSCTRL_CQOS_bf(a, b) +#define hri_usbdevice_toggle_QOSCTRL_CQOS_bf(a, b) hri_usb_toggle_QOSCTRL_CQOS_bf(a, b) +#define hri_usbdevice_read_QOSCTRL_CQOS_bf(a) hri_usb_read_QOSCTRL_CQOS_bf(a) +#define hri_usbdevice_set_QOSCTRL_DQOS_bf(a, b) hri_usb_set_QOSCTRL_DQOS_bf(a, b) +#define hri_usbdevice_get_QOSCTRL_DQOS_bf(a, b) hri_usb_get_QOSCTRL_DQOS_bf(a, b) +#define hri_usbdevice_write_QOSCTRL_DQOS_bf(a, b) hri_usb_write_QOSCTRL_DQOS_bf(a, b) +#define hri_usbdevice_clear_QOSCTRL_DQOS_bf(a, b) hri_usb_clear_QOSCTRL_DQOS_bf(a, b) +#define hri_usbdevice_toggle_QOSCTRL_DQOS_bf(a, b) hri_usb_toggle_QOSCTRL_DQOS_bf(a, b) +#define hri_usbdevice_read_QOSCTRL_DQOS_bf(a) hri_usb_read_QOSCTRL_DQOS_bf(a) +#define hri_usbdevice_set_QOSCTRL_reg(a, b) hri_usb_set_QOSCTRL_reg(a, b) +#define hri_usbdevice_get_QOSCTRL_reg(a, b) hri_usb_get_QOSCTRL_reg(a, b) +#define hri_usbdevice_write_QOSCTRL_reg(a, b) hri_usb_write_QOSCTRL_reg(a, b) +#define hri_usbdevice_clear_QOSCTRL_reg(a, b) hri_usb_clear_QOSCTRL_reg(a, b) +#define hri_usbdevice_toggle_QOSCTRL_reg(a, b) hri_usb_toggle_QOSCTRL_reg(a, b) +#define hri_usbdevice_read_QOSCTRL_reg(a) hri_usb_read_QOSCTRL_reg(a) +#define hri_usbdevice_set_DESCADD_DESCADD_bf(a, b) hri_usb_set_DESCADD_DESCADD_bf(a, b) +#define hri_usbdevice_get_DESCADD_DESCADD_bf(a, b) hri_usb_get_DESCADD_DESCADD_bf(a, b) +#define hri_usbdevice_write_DESCADD_DESCADD_bf(a, b) hri_usb_write_DESCADD_DESCADD_bf(a, b) +#define hri_usbdevice_clear_DESCADD_DESCADD_bf(a, b) hri_usb_clear_DESCADD_DESCADD_bf(a, b) +#define hri_usbdevice_toggle_DESCADD_DESCADD_bf(a, b) hri_usb_toggle_DESCADD_DESCADD_bf(a, b) +#define hri_usbdevice_read_DESCADD_DESCADD_bf(a) hri_usb_read_DESCADD_DESCADD_bf(a) +#define hri_usbdevice_set_DESCADD_reg(a, b) hri_usb_set_DESCADD_reg(a, b) +#define hri_usbdevice_get_DESCADD_reg(a, b) hri_usb_get_DESCADD_reg(a, b) +#define hri_usbdevice_write_DESCADD_reg(a, b) hri_usb_write_DESCADD_reg(a, b) +#define hri_usbdevice_clear_DESCADD_reg(a, b) hri_usb_clear_DESCADD_reg(a, b) +#define hri_usbdevice_toggle_DESCADD_reg(a, b) hri_usb_toggle_DESCADD_reg(a, b) +#define hri_usbdevice_read_DESCADD_reg(a) hri_usb_read_DESCADD_reg(a) +#define hri_usbdevice_set_PADCAL_TRANSP_bf(a, b) hri_usb_set_PADCAL_TRANSP_bf(a, b) +#define hri_usbdevice_get_PADCAL_TRANSP_bf(a, b) hri_usb_get_PADCAL_TRANSP_bf(a, b) +#define hri_usbdevice_write_PADCAL_TRANSP_bf(a, b) hri_usb_write_PADCAL_TRANSP_bf(a, b) +#define hri_usbdevice_clear_PADCAL_TRANSP_bf(a, b) hri_usb_clear_PADCAL_TRANSP_bf(a, b) +#define hri_usbdevice_toggle_PADCAL_TRANSP_bf(a, b) hri_usb_toggle_PADCAL_TRANSP_bf(a, b) +#define hri_usbdevice_read_PADCAL_TRANSP_bf(a) hri_usb_read_PADCAL_TRANSP_bf(a) +#define hri_usbdevice_set_PADCAL_TRANSN_bf(a, b) hri_usb_set_PADCAL_TRANSN_bf(a, b) +#define hri_usbdevice_get_PADCAL_TRANSN_bf(a, b) hri_usb_get_PADCAL_TRANSN_bf(a, b) +#define hri_usbdevice_write_PADCAL_TRANSN_bf(a, b) hri_usb_write_PADCAL_TRANSN_bf(a, b) +#define hri_usbdevice_clear_PADCAL_TRANSN_bf(a, b) hri_usb_clear_PADCAL_TRANSN_bf(a, b) +#define hri_usbdevice_toggle_PADCAL_TRANSN_bf(a, b) hri_usb_toggle_PADCAL_TRANSN_bf(a, b) +#define hri_usbdevice_read_PADCAL_TRANSN_bf(a) hri_usb_read_PADCAL_TRANSN_bf(a) +#define hri_usbdevice_set_PADCAL_TRIM_bf(a, b) hri_usb_set_PADCAL_TRIM_bf(a, b) +#define hri_usbdevice_get_PADCAL_TRIM_bf(a, b) hri_usb_get_PADCAL_TRIM_bf(a, b) +#define hri_usbdevice_write_PADCAL_TRIM_bf(a, b) hri_usb_write_PADCAL_TRIM_bf(a, b) +#define hri_usbdevice_clear_PADCAL_TRIM_bf(a, b) hri_usb_clear_PADCAL_TRIM_bf(a, b) +#define hri_usbdevice_toggle_PADCAL_TRIM_bf(a, b) hri_usb_toggle_PADCAL_TRIM_bf(a, b) +#define hri_usbdevice_read_PADCAL_TRIM_bf(a) hri_usb_read_PADCAL_TRIM_bf(a) +#define hri_usbdevice_set_PADCAL_reg(a, b) hri_usb_set_PADCAL_reg(a, b) +#define hri_usbdevice_get_PADCAL_reg(a, b) hri_usb_get_PADCAL_reg(a, b) +#define hri_usbdevice_write_PADCAL_reg(a, b) hri_usb_write_PADCAL_reg(a, b) +#define hri_usbdevice_clear_PADCAL_reg(a, b) hri_usb_clear_PADCAL_reg(a, b) +#define hri_usbdevice_toggle_PADCAL_reg(a, b) hri_usb_toggle_PADCAL_reg(a, b) +#define hri_usbdevice_read_PADCAL_reg(a) hri_usb_read_PADCAL_reg(a) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_USB_L21_H_INCLUDED */ +#endif /* _SAML21_USB_COMPONENT_ */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_wdt_l21.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_wdt_l21.h new file mode 100644 index 00000000..f4148c3f --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/hri/hri_wdt_l21.h @@ -0,0 +1,617 @@ +/** + * \file + * + * \brief SAM WDT + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_WDT_COMPONENT_ +#ifndef _HRI_WDT_L21_H_INCLUDED_ +#define _HRI_WDT_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_WDT_CRITICAL_SECTIONS) +#define WDT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define WDT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define WDT_CRITICAL_SECTION_ENTER() +#define WDT_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_wdt_syncbusy_reg_t; +typedef uint8_t hri_wdt_clear_reg_t; +typedef uint8_t hri_wdt_config_reg_t; +typedef uint8_t hri_wdt_ctrla_reg_t; +typedef uint8_t hri_wdt_ewctrl_reg_t; +typedef uint8_t hri_wdt_intenset_reg_t; +typedef uint8_t hri_wdt_intflag_reg_t; + +static inline void hri_wdt_wait_for_sync(const void *const hw, hri_wdt_syncbusy_reg_t reg) +{ + while (((Wdt *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_wdt_is_syncing(const void *const hw, hri_wdt_syncbusy_reg_t reg) +{ + return ((Wdt *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_wdt_get_INTFLAG_EW_bit(const void *const hw) +{ + return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos; +} + +static inline void hri_wdt_clear_INTFLAG_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW; +} + +static inline bool hri_wdt_get_interrupt_EW_bit(const void *const hw) +{ + return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos; +} + +static inline void hri_wdt_clear_interrupt_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW; +} + +static inline hri_wdt_intflag_reg_t hri_wdt_get_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_wdt_intflag_reg_t hri_wdt_read_INTFLAG_reg(const void *const hw) +{ + return ((Wdt *)hw)->INTFLAG.reg; +} + +static inline void hri_wdt_clear_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask) +{ + ((Wdt *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_wdt_set_INTEN_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW; +} + +static inline bool hri_wdt_get_INTEN_EW_bit(const void *const hw) +{ + return (((Wdt *)hw)->INTENSET.reg & WDT_INTENSET_EW) >> WDT_INTENSET_EW_Pos; +} + +static inline void hri_wdt_write_INTEN_EW_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW; + } else { + ((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW; + } +} + +static inline void hri_wdt_clear_INTEN_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW; +} + +static inline void hri_wdt_set_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) +{ + ((Wdt *)hw)->INTENSET.reg = mask; +} + +static inline hri_wdt_intenset_reg_t hri_wdt_get_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_wdt_intenset_reg_t hri_wdt_read_INTEN_reg(const void *const hw) +{ + return ((Wdt *)hw)->INTENSET.reg; +} + +static inline void hri_wdt_write_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t data) +{ + ((Wdt *)hw)->INTENSET.reg = data; + ((Wdt *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_wdt_clear_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) +{ + ((Wdt *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_wdt_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ENABLE) >> WDT_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_wdt_get_SYNCBUSY_WEN_bit(const void *const hw) +{ + return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_WEN) >> WDT_SYNCBUSY_WEN_Pos; +} + +static inline bool hri_wdt_get_SYNCBUSY_ALWAYSON_bit(const void *const hw) +{ + return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ALWAYSON) >> WDT_SYNCBUSY_ALWAYSON_Pos; +} + +static inline bool hri_wdt_get_SYNCBUSY_CLEAR_bit(const void *const hw) +{ + return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_CLEAR) >> WDT_SYNCBUSY_CLEAR_Pos; +} + +static inline hri_wdt_syncbusy_reg_t hri_wdt_get_SYNCBUSY_reg(const void *const hw, hri_wdt_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Wdt *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_wdt_syncbusy_reg_t hri_wdt_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Wdt *)hw)->SYNCBUSY.reg; +} + +static inline void hri_wdt_set_CTRLA_ENABLE_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ENABLE; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_wdt_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp = (tmp & WDT_CTRLA_ENABLE) >> WDT_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_wdt_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp &= ~WDT_CTRLA_ENABLE; + tmp |= value << WDT_CTRLA_ENABLE_Pos; + ((Wdt *)hw)->CTRLA.reg = tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ENABLE; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ENABLE; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_set_CTRLA_WEN_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_WEN; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_wdt_get_CTRLA_WEN_bit(const void *const hw) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp = (tmp & WDT_CTRLA_WEN) >> WDT_CTRLA_WEN_Pos; + return (bool)tmp; +} + +static inline void hri_wdt_write_CTRLA_WEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp &= ~WDT_CTRLA_WEN; + tmp |= value << WDT_CTRLA_WEN_Pos; + ((Wdt *)hw)->CTRLA.reg = tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRLA_WEN_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_WEN; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRLA_WEN_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_WEN; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_set_CTRLA_ALWAYSON_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ALWAYSON; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_wdt_get_CTRLA_ALWAYSON_bit(const void *const hw) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp = (tmp & WDT_CTRLA_ALWAYSON) >> WDT_CTRLA_ALWAYSON_Pos; + return (bool)tmp; +} + +static inline void hri_wdt_write_CTRLA_ALWAYSON_bit(const void *const hw, bool value) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp &= ~WDT_CTRLA_ALWAYSON; + tmp |= value << WDT_CTRLA_ALWAYSON_Pos; + ((Wdt *)hw)->CTRLA.reg = tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRLA_ALWAYSON_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ALWAYSON; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRLA_ALWAYSON_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ALWAYSON; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_set_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg |= mask; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ctrla_reg_t hri_wdt_get_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_wdt_write_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg = data; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg &= ~mask; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg ^= mask; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ctrla_reg_t hri_wdt_read_CTRLA_reg(const void *const hw) +{ + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + return ((Wdt *)hw)->CTRLA.reg; +} + +static inline void hri_wdt_set_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_PER(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_PER(mask)) >> WDT_CONFIG_PER_Pos; + return tmp; +} + +static inline void hri_wdt_write_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t data) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp &= ~WDT_CONFIG_PER_Msk; + tmp |= WDT_CONFIG_PER(data); + ((Wdt *)hw)->CONFIG.reg = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_PER(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_PER(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_PER_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_PER_Msk) >> WDT_CONFIG_PER_Pos; + return tmp; +} + +static inline void hri_wdt_set_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_WINDOW(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_WINDOW(mask)) >> WDT_CONFIG_WINDOW_Pos; + return tmp; +} + +static inline void hri_wdt_write_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t data) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp &= ~WDT_CONFIG_WINDOW_Msk; + tmp |= WDT_CONFIG_WINDOW(data); + ((Wdt *)hw)->CONFIG.reg = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_WINDOW(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_WINDOW(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_WINDOW_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_WINDOW_Msk) >> WDT_CONFIG_WINDOW_Pos; + return tmp; +} + +static inline void hri_wdt_set_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg |= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_wdt_write_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg = data; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg &= ~mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg ^= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_reg(const void *const hw) +{ + return ((Wdt *)hw)->CONFIG.reg; +} + +static inline void hri_wdt_set_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg |= WDT_EWCTRL_EWOFFSET(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp = (tmp & WDT_EWCTRL_EWOFFSET(mask)) >> WDT_EWCTRL_EWOFFSET_Pos; + return tmp; +} + +static inline void hri_wdt_write_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t data) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp &= ~WDT_EWCTRL_EWOFFSET_Msk; + tmp |= WDT_EWCTRL_EWOFFSET(data); + ((Wdt *)hw)->EWCTRL.reg = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg &= ~WDT_EWCTRL_EWOFFSET(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg ^= WDT_EWCTRL_EWOFFSET(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_EWOFFSET_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp = (tmp & WDT_EWCTRL_EWOFFSET_Msk) >> WDT_EWCTRL_EWOFFSET_Pos; + return tmp; +} + +static inline void hri_wdt_set_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg |= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_wdt_write_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg = data; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg &= ~mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg ^= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_reg(const void *const hw) +{ + return ((Wdt *)hw)->EWCTRL.reg; +} + +static inline void hri_wdt_write_CLEAR_reg(const void *const hw, hri_wdt_clear_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CLEAR.reg = data; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_CLEAR); + WDT_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_WDT_L21_H_INCLUDED */ +#endif /* _SAML21_WDT_COMPONENT_ */ diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/lora.c b/prototype/firmware/EDBG UART erert/EDBG UART erert/lora.c new file mode 100644 index 00000000..5991c54d --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/lora.c @@ -0,0 +1,391 @@ +/* + * Drivers for RFM98W chip + * + * + */ +#include +#include +#include "driver_init.h" +#include "RFM98W.h" +#include "lora.h" + +// RFM98 +uint8_t currentMode = 0x81; +struct TRadioConfig RadioConfig; + +struct TLoRaMode LoRaModes[] = +{ + {EXPLICIT_MODE, ERROR_CODING_4_8, BANDWIDTH_20K8, SPREADING_11, 8, 60, "Telemetry"}, // 0: Normal mode for telemetry + {IMPLICIT_MODE, ERROR_CODING_4_5, BANDWIDTH_20K8, SPREADING_6, 0, 1400, "SSDV"}, // 1: Normal mode for SSDV + {EXPLICIT_MODE, ERROR_CODING_4_8, BANDWIDTH_62K5, SPREADING_8, 0, 2000, "Repeater"}, // 2: Normal mode for repeater network + {EXPLICIT_MODE, ERROR_CODING_4_6, BANDWIDTH_250K, SPREADING_7, 0, 8000, "Turbo"}, // 3: Normal mode for high speed images in 868MHz band + {IMPLICIT_MODE, ERROR_CODING_4_5, BANDWIDTH_250K, SPREADING_6, 0, 16828, "TurboX"}, // Fastest mode within IR2030 in 868MHz band + {EXPLICIT_MODE, ERROR_CODING_4_8, BANDWIDTH_41K7, SPREADING_11, 0, 200, "Calling"}, // Calling mode + {IMPLICIT_MODE, ERROR_CODING_4_5, BANDWIDTH_41K7, SPREADING_6, 0, 2800, "Uplink"}, // Uplink mode for 868 + {EXPLICIT_MODE, ERROR_CODING_4_5, BANDWIDTH_20K8, SPREADING_7, 0, 2800, "Telnet"}, // 7: Telnet-style comms with HAB on 434 + {IMPLICIT_MODE, ERROR_CODING_4_5, BANDWIDTH_62K5, SPREADING_6, 0, 4500, "SSDV Repeater"}, // 8: SSDV Repeater Network +}; + + + +void SetLoraMode(uint8_t newMode) +{ + if(newMode == currentMode) + return; + + switch (newMode) + { + case RF98_MODE_TX: + write_RFM98W_Register(REG_LNA, LNA_OFF_GAIN); // TURN LNA OFF FOR TRANSMIT + write_RFM98W_Register(REG_PA_CONFIG, RadioConfig.Power); + write_RFM98W_Register(REG_OPMODE, newMode); + currentMode = newMode; + break; + + case RF98_MODE_RX_CONTINUOUS: + write_RFM98W_Register(REG_PA_CONFIG, PA_OFF_BOOST); // TURN PA OFF FOR RECIEVE?? + write_RFM98W_Register(REG_LNA, LNA_MAX_GAIN); // LNA_MAX_GAIN); // MAX GAIN FOR RECIEVE + write_RFM98W_Register( REG_OPMODE, newMode); + currentMode = newMode; + break; + + case RF98_MODE_SLEEP: + write_RFM98W_Register(REG_OPMODE, newMode); + currentMode = newMode; + break; + + case RF98_MODE_STANDBY: + write_RFM98W_Register(REG_OPMODE, newMode); + currentMode = newMode; + break; + + default: return; + } + + if(newMode != RF98_MODE_SLEEP) + { + + //while(get_RFM98W_DIO(DIO5) == 0) + //{ + //} + } + else + { + delay_ms(10); + } +} + + +void SetLoRaFrequency(double Frequency) +{ + uint64_t FrequencyValue; + + SetLoraMode(RF98_MODE_STANDBY); + SetLoraMode(RF98_MODE_SLEEP); + write_RFM98W_Register(REG_OPMODE, 0x80); + SetLoraMode(RF98_MODE_SLEEP); + + FrequencyValue = ((uint64_t) Frequency << 19)/32000000; + + + write_RFM98W_Register(REG_FRF_MSB, (FrequencyValue >> 16) & 0xFF); // Set frequency + write_RFM98W_Register(REG_FRF_MID, (FrequencyValue >> 8) & 0xFF); + write_RFM98W_Register(REG_FRF_LSB, FrequencyValue & 0xFF); +} + +void UpdateLoRaFrequency(void) +{ + + SetLoRaFrequency(RadioConfig.Frequency); + +} + +void SetLoRaParameters(int ImplicitOrExplicit, int ErrorCoding, int Bandwidth, int SpreadingFactor, int LowDataRateOptimize) +{ + write_RFM98W_Register(REG_MODEM_CONFIG, ImplicitOrExplicit | ErrorCoding | Bandwidth); + write_RFM98W_Register(REG_MODEM_CONFIG2, SpreadingFactor | CRC_ON); + write_RFM98W_Register(REG_MODEM_CONFIG3, 0x04 | LowDataRateOptimize); // 0x04: AGC sets LNA gain + write_RFM98W_Register(REG_DETECT_OPT, (read_RFM98W_Register(REG_DETECT_OPT) & 0xF8) | ((SpreadingFactor == SPREADING_6) ? 0x05 : 0x03)); // 0x05 For SF6; 0x03 otherwise + write_RFM98W_Register(REG_DETECTION_THRESHOLD, (SpreadingFactor == SPREADING_6) ? 0x0C : 0x0A); // 0x0C for SF6, 0x0A otherwise + + RadioConfig.PayloadLength = ImplicitOrExplicit == IMPLICIT_MODE ? 255 : 0; + + write_RFM98W_Register(REG_PAYLOAD_LENGTH, RadioConfig.PayloadLength); + write_RFM98W_Register(REG_RX_NB_BYTES, RadioConfig.PayloadLength); +} + +uint8_t lora_init(void) + +{ + RFM98W_Setup(); + + reset_RFM98W(); + + if (read_RFM98W_Register(REG_VERSION) != 0x12) return 0; + + + RadioConfig.Frequency = FREQUENCY; + RadioConfig.Power = PA_MAX_UK; + + + + RadioConfig.RTTYBaudRate = RTTY_BAUDRATE; + + ConfigRTTYFSK(); + + + UpdateLoRaFrequency(); + + SetLoRaParameters( + LoRaModes[0].ImplicitOrExplicit, + LoRaModes[0].ErrorCoding, + LoRaModes[0].Bandwidth, + LoRaModes[0]. SpreadingFactor, + LoRaModes[0].LowDataRateOptimize); + + write_RFM98W_Register(REG_FIFO_ADDR_PTR, 0); + + write_RFM98W_Register(REG_DIO_MAPPING_2,0x00); + + return 1; +} + +void SwitchToLoRaMode(void) +{ + UpdateLoRaFrequency(); + + SetLoRaParameters( + LoRaModes[RadioConfig.LoraMode].ImplicitOrExplicit, + LoRaModes[RadioConfig.LoraMode].ErrorCoding, + LoRaModes[RadioConfig.LoraMode].Bandwidth, + LoRaModes[RadioConfig.LoraMode]. SpreadingFactor, + LoRaModes[RadioConfig.LoraMode].LowDataRateOptimize); + + +} + + + +void SendLoRaData(unsigned char *buffer, int Length) +{ + + + if (RadioConfig.InRTTYMode != 0) + { + // Set LoRa mode + SwitchToLoRaMode(); + RadioConfig.InRTTYMode = 0; + } + + RadioConfig.MillisSinceLastPacket = 0; + + SetLoraMode(RF98_MODE_STANDBY); + + write_RFM98W_Register(REG_DIO_MAPPING_1, 0x40); // 01 00 00 00 maps DIO0 to TxDone + + write_RFM98W_Register(REG_FIFO_TX_BASE_AD, 0x00); // Update the address ptr to the current tx base address + write_RFM98W_Register(REG_FIFO_ADDR_PTR, 0x00); + + write_RFM98W_FIFO(buffer, Length); + + // Set the length. For implicit mode, since the length needs to match what the receiver expects, we have to set a value which is 255 for an SSDV packet + write_RFM98W_Register(REG_PAYLOAD_LENGTH, Length); + + // go into transmit mode + SetLoraMode(RF98_MODE_TX); + + RadioConfig.LoraOpMode = lmSending; + RadioConfig.SendingRTTY = 0; +} + +void SwitchToFSKMode(void) +{ + + + uint8_t mode = read_RFM98W_Register(REG_OPMODE); + mode |= (1<<3); //set LF range + + if (mode & (1<<7)) //if in lora mode + { + write_RFM98W_Register(REG_OPMODE,(mode & ~(uint8_t)7)); //set to sleep mode so fsk bit can be written + } + else + { + write_RFM98W_Register(REG_OPMODE,(mode & ~(uint8_t)7) | 1); //set to standby mode so various settings can be written + } + + mode = read_RFM98W_Register(REG_OPMODE); + write_RFM98W_Register(REG_OPMODE, mode & ~(uint8_t)(7<<5)); //set to FSK + + write_RFM98W_Register(REG_LNA, LNA_OFF_GAIN); // TURN LNA OFF FOR TRANSMIT + write_RFM98W_Register(REG_PA_CONFIG, RadioConfig.Power); + + + + //write modem config + write_RFM98W_Register(REG_BITRATE_LSB, RadioConfig.FSKBitRate & 0xFF); + write_RFM98W_Register(REG_BITRATE_MSB, (RadioConfig.FSKBitRate >> 8) & 0xFF); + write_RFM98W_Register(REG_FDEV_LSB, (RadioConfig.RTTYShift / 122) & 0xFF); + write_RFM98W_Register(REG_FDEV_MSB, 0); + write_RFM98W_Register(REG_PREAMBLE_LSB_FSK, 0); // Preamble + write_RFM98W_Register(REG_PREAMBLE_MSB_FSK, 0); + + // writeRegister(LoRaChannel, REG_PACKET_CONFIG1, 0x80); // variable length, no DC fix, no CRC, no addressing + write_RFM98W_Register(REG_PACKET_CONFIG1, 0x00); // fixed length, no DC fix, no CRC, no addressing + write_RFM98W_Register(REG_PAYLOAD_LENGTH_FSK, 0); + +} + +int FSKPacketSent(void) +{ + return ((read_RFM98W_Register(REG_IRQ_FLAGS2) & 0x48) != 0); +} + +int FSKBufferLow(void) +{ + return ((read_RFM98W_Register(REG_IRQ_FLAGS2) & 0x20) == 0); +} + +void AddBytesToFSKBuffer(int MaxBytes) +{ + unsigned char data[64], temp; + + uint8_t BytesWritten = 0; + + if (RadioConfig.RTTYIndex < RadioConfig.RTTYLength) + { + + while((BytesWritten <= (MaxBytes - RadioConfig.FSKOverSample + 1)) && + (RadioConfig.RTTYIndex < RadioConfig.RTTYLength)) + { + if (RadioConfig.RTTYMask < 0) //start bit + { + temp = 0xFF; + RadioConfig.RTTYMask++; + } + else if (RadioConfig.RTTYMask == 0) //start bit + { + temp = 0; + RadioConfig.RTTYMask = 1; + } + else if (RadioConfig.RTTYMask >= (1<= (1<<(RadioConfig.RTTYBitLength+2))) + { + RadioConfig.RTTYMask = 0; + RadioConfig.RTTYIndex++; + } + } + else //data bits + { + if (RadioConfig.RTTYBuffer[RadioConfig.RTTYIndex] & RadioConfig.RTTYMask) + { + temp = 0xFF; + } + else + { + temp = 0x0; + } + RadioConfig.RTTYMask <<= 1; + } + + for (uint8_t i = 0; i < RadioConfig.FSKOverSample; i++) + { + data[BytesWritten++] = temp; + } + } + + write_RFM98W_FIFO(data, BytesWritten); + + + } +} + + +void SendLoRaRTTY(unsigned char *buffer, int Length) +{ + + + if (RadioConfig.InRTTYMode != 1) + { + // Set RTTY mode + SwitchToFSKMode(); + RadioConfig.InRTTYMode = 1; + } + + RadioConfig.MillisSinceLastPacket = 0; + + // Fill in RTTY buffer + memcpy(RadioConfig.RTTYBuffer, buffer, Length); + RadioConfig.RTTYLength = Length; + RadioConfig.RTTYIndex = 0; + RadioConfig.RTTYMask = RadioConfig.RTTYPreamble; + + // Set FIFO threshold + uint8_t r = read_RFM98W_Register( REG_FIFO_THRESH); + write_RFM98W_Register(REG_FIFO_THRESH,(r&(~0x3F)) | 20); // 20 = FIFO threshold + + write_RFM98W_Register(REG_OPMODE, 0x0B); // Tx mode + + // Populate FIFO + AddBytesToFSKBuffer(64); + + // Set channel state + RadioConfig.LoraOpMode = lmSending; + RadioConfig.SendingRTTY = 1; +} + + +void ConfigRTTYFSK(void) +{ + + + RadioConfig.RTTYShift = 450; + RadioConfig.RTTYPreamble = 8; + if (RadioConfig.RTTYBaudRate == 50) + { + RadioConfig.FSKBitRate = 40000; + RadioConfig.FSKOverSample = 2; + RadioConfig.RTTYBitLength = 7; + } + else + { + // 300 baud + RadioConfig.FSKBitRate = 13333; // 53333; + RadioConfig.FSKOverSample = 1; + RadioConfig.RTTYBitLength = 8; + } + +} + + + + + +void CheckFSKBuffers(void) +{ + + + if ((RadioConfig.LoraOpMode == lmSending) && RadioConfig.SendingRTTY) + { + // Check if packet sent + if (FSKPacketSent()) + { + + RadioConfig.LoraOpMode = lmIdle; + RadioConfig.SendingRTTY = 0; + } + else if (FSKBufferLow()) + { + AddBytesToFSKBuffer(64 - 20); + } + } + +} + +int RadioState(void) +{ + return RadioConfig.LoraOpMode; +} \ No newline at end of file diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/lora.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/lora.h new file mode 100644 index 00000000..a5d74b1c --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/lora.h @@ -0,0 +1,83 @@ +/* + * Header File for LoRa Radio. + * + * + */ +#ifndef LORA_INCLUDED +#define LORA_INCLUDED + +#include "RFM98W.h" + +#define FREQUENCY 434000000; +#define POWER 0x88; +#define RTTY_BAUDRATE 50; + + +typedef enum {lmIdle, lmListening, lmSending} tLoRaMode; + +struct TBinaryPacket +{ + uint8_t PayloadIDs; + uint16_t Counter; + uint16_t Seconds; + float Latitude; + float Longitude; + uint16_t Altitude; +}; + +struct TLoRaMode +{ + int ImplicitOrExplicit; + int ErrorCoding; + int Bandwidth; + int SpreadingFactor; + int LowDataRateOptimize; + int BaudRate; + char *Description; +}; + +struct TRadioConfig +{ + double Frequency; + int PayloadLength; + int Power; + + + int MillisSinceLastPacket; + int LoraMode; + int LoraOpMode; + + int InRTTYMode; + int SendingRTTY; + int RTTYBaudRate; + int RTTYShift; + int RTTYIndex; + int RTTYLength; + int RTTYBitLength; + int RTTYPreamble; + int RTTYMask; + char RTTYBuffer[256]; + int FSKOverSample; + unsigned int FSKBitRate; + +}; + + +void SetLoraMode(uint8_t newMode); +void SetLoRaFrequency(double Frequency); +void setLoRaChannel(int LoRaChannel); +void SetLoRaParameters(int, int, int Bandwidth, int SpreadingFactor, int LowDataRateOptimize); +uint8_t lora_init(void); +void SwitchToLoRaMode(void); +void SendLoRaData(unsigned char *buffer, int Length); +void SwitchToFSKMode(void); +int FSKPacketSent(void); +int FSKBufferLow(void); +void AddBytesToFSKBuffer(int MaxBytes); +void SendLoRaRTTY(unsigned char *buffer, int Length); +void ConfigRTTYFSK(void); +void CheckFSKBuffers(void); +int RadioState(void); + + +#endif // LORA_INCLUDED \ No newline at end of file diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/main.c b/prototype/firmware/EDBG UART erert/EDBG UART erert/main.c new file mode 100644 index 00000000..f1cb1f57 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/main.c @@ -0,0 +1,219 @@ +/** +* \file +* +* \brief Application implement +* +* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. +* +* \asf_license_start +* +* \page License +* +* Subject to your compliance with these terms, you may use Microchip +* software and any derivatives exclusively with Microchip products. +* It is your responsibility to comply with third party license terms applicable +* to your use of third party software (including open source software) that +* may accompany Microchip software. +* +* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, +* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, +* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, +* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE +* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL +* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE +* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE +* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT +* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY +* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, +* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. +* +* \asf_license_stop +* +*/ +/* +* Support and FAQ: visit Microchip Support +*/ + +#include "atmel_start.h" +#include "atmel_start_pins.h" +#include +#include "main.h" +#include "fix.h" +#include "gps.h" +#include "BME280.h" +#include "lora.h" + + +/* +* the TX data buffer +* contains ASCII data, which is either transmitted as CW over RTTY +*/ +uint16_t tx_buf_rdy = 0; /* the read-flag (main -> main) */ +uint16_t tx_buf_length = 0; /* how many chars to send */ +char tx_buf[TX_BUF_MAX_LENGTH] = {SYNC_PREFIX "$$" PAYLOAD_NAME ","}; /* the telemetry buffer initialised with $$ */ +/* Retry counters and Operational Status*/ +uint8_t ubx_cfg_fail = 0; +uint8_t ubx_retry_count; +uint8_t ubx_poll_fail = 0; +extern uint16_t tlm_sent_id_length; +extern uint16_t tlm_alt_length; + + + +/* for the temperature, humidity, pressure sensor */ +int i; +uint16_t T, P, H; // calibrated values +float fP, fH; + +/* The pip tone */ +uint8_t pip[1] = {0}; // Try to use the center frequency instead of the mark or space. + + +/* + +* telemetry format: +* - callsign +* - sentence id +* - time +* - latitude +* - longitude +* - altitude +* - available satellites +* - voltage of the AAA cell(after boosting) +* - op status +* - temperature of radio + +*/ + +/* current (latest) GPS fix and measurements */ +struct gps_fix current_fix; + +void send_pips(int n){ + int i; + for(i = 0; i < n; i++){ + SendLoRaRTTY(pip, 1); + delay_ms(500); + } +} + + +void get_fix(void) { + ubx_poll_fail = 0; + + /* + * The tracker outputs Pips while waiting for a good GPS fix. + */ + + current_fix.num_svs = 0; + current_fix.type = 3; + + while (1) { + + /* check if we have a fix*/ + gps_get_fix(¤t_fix); + + // TODO: use the GPS status bit to check if the fix is valid + //current_fix.type = 3; // TEMP + + /* check if we have a 3D fix */ + if (current_fix.type == 3){ + break; + }; + + /* send pip */ + send_pips(4); + + } + +} + + +void get_measurements(void){ + bme280ReadValues(&T, &P, &H); + T -= 150; // for some reason, the sensor reports temperatures too high + //fP = (float) P / 2.56; + //fH = (float) H / 10.24; + + current_fix.temp_BME280 = T; + current_fix.op_status = ((ubx_cfg_fail & 0x03) << 2) | ((ubx_poll_fail & 0x03)); //send operational status +} + +void transmit_sequence(){ + /* now wake up the GPS */ + gps_wake_up(); + + /* now put the gps in full power mode */ + while(!(gps_power_save(0))); + + /* get the gps fix */ + get_fix(); + + /* put the gps back to power save mode(sleep) */ + while(!(gps_power_save(1))); + + /* get voltage and temperature*/ + get_measurements(); + + /* create the telemetry string */ + prepare_tx_buffer(); + + /* send out the data */ + tx_buf_length = TX_BUF_FRAME_END; + SendLoRaRTTY(tx_buf, tx_buf_length); +} + +int main(void) +{ + + /* Initializes MCU, drivers and middleware */ + atmel_start_init(); + usart_sync_enable(&USART_0); + + lora_init(); + + /* Initialise BME280 */ + while(BME280Init(0x76)); + delay_ms(100); // wait for data to settle for first read + + /* Initialise GPS */ + gps_wake_up(); + + // TODO: add to the op byte + //while(!(gps_cfg_reset())); + while(!(gps_disable_nmea_output())); + while(!(gps_set_power_save())); + while(!(gps_set_gps_only())); + while(!(gps_set_airborne_model())); + + /* Get a single GPS fix from a cold start. Does not carry on until it has a + * solid fix + */ + get_fix(); + get_measurements(); + + while(!(gps_power_save(1))); + while(!(gps_save_settings())); + + SendLoRaRTTY(tx_buf, tx_buf_length); + + /* MAIN */ + while (1) { + + // shift: 365Hz, 7 bit ASCII, no parity, 2 stop bits, 434.000Mhz + + CheckFSKBuffers(); + delay_us(100); + + if(FSKPacketSent()) + { + transmit_sequence(); + /* sleep */ + // Make it sleep here + // TODO clean this area up. + + }else{ + + } + + } /* MAIN */ +} \ No newline at end of file diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/main.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/main.h new file mode 100644 index 00000000..350bff88 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/main.h @@ -0,0 +1,76 @@ +/* + * main tracker software + * + */ + + + +#ifndef MAIN_H_ +#define MAIN_H_ + +/* payload name */ +#define PAYLOAD_NAME "ICSPACE12" +/* payload telemetry interval + * can be set for APRS only and for RTTY + APRS + */ +#define TLM_APRS_INTERVAL 120 +#define TLM_RTTY_INTERVAL 120 +/* time offset for APRS backlog transmissions */ +#define TLM_BACKLOG_OFFSET 15 +/* how often a fix should be requested when transmitting blips (after power up) */ +#define BLIP_FIX_INTERVAL 1 + +/* whether RTTY telemetry shall be transmitted at all */ +#define TLM_RTTY +//#define TLM_RTTY_ONLY +#define SOLAR_POWER + +/* telemetry string prefix for RX syncronisation */ +#define SYNC_PREFIX " $$" +/* telemetry string postfix for tlm parser */ +#define TX_BUF_POSTFIX "\n\n" + +/* number of idle bits to transmit before beginning tlm string tx */ +#define NUM_IDLE_BITS 32 + +/* length of non-GPS-telemetry fields */ +#define LAT_LENGTH 9 +#define LON_LENGTH 10 +#define TIME_LENGTH 6 +#define SAT_LENGTH 2 +#define ALT_LENGTH_MAX 5 +#define VOLT_LENGTH 4 +#define OP_STAT_LENGTH 4 +#define TEMP_LENGTH 4 +#define CHECKSUM_LENGTH 4 +/* sentence id is variable length */ +#define SENT_ID_LENGTH_MAX 5 + +#define TX_BUF_POSTFIX_LENGTH sizeof(TX_BUF_POSTFIX) - 1 +/* offset from buffer start to telemetry data */ +#define TX_BUF_START_OFFSET sizeof(SYNC_PREFIX "$$" PAYLOAD_NAME ",") - 1 +#define TX_BUF_SENT_ID_START TX_BUF_START_OFFSET +#define TX_BUF_TIME_START TX_BUF_SENT_ID_START + tlm_sent_id_length + 1 +#define TX_BUF_LAT_START TX_BUF_TIME_START + TIME_LENGTH + 1 +/* lat and lon fields are one char longer for +/- */ +#define TX_BUF_LON_START TX_BUF_LAT_START + LAT_LENGTH + 1 + 1 +#define TX_BUF_ALT_START TX_BUF_LON_START + LON_LENGTH + 1 + 1 +#define TX_BUF_SAT_START TX_BUF_ALT_START + tlm_alt_length + 1 +#define TX_BUF_VOLT_START TX_BUF_SAT_START + SAT_LENGTH + 1 +#define TX_BUF_OP_STAT_START TX_BUF_VOLT_START + VOLT_LENGTH + 1 +/* temperature field is one char longer for +/- */ +#define TX_BUF_TEMP_START TX_BUF_OP_STAT_START + OP_STAT_LENGTH + 1 +#define TX_BUF_CHECKSUM_START TX_BUF_TEMP_START + TEMP_LENGTH + 1 + 1 +#define TX_BUF_POSTFIX_START TX_BUF_CHECKSUM_START + CHECKSUM_LENGTH +#define TX_BUF_FRAME_END TX_BUF_POSTFIX_START + sizeof(TX_BUF_POSTFIX) - 1; +/* checksum parameters */ +#define TX_BUF_CHECKSUM_BEGIN sizeof(SYNC_PREFIX "$$") - 1 +#define TX_BUF_CHECKSUM_END TX_BUF_CHECKSUM_START - 1 + +#define TX_BUF_MAX_LENGTH sizeof(SYNC_PREFIX "$$" PAYLOAD_NAME) + 1 + \ + SENT_ID_LENGTH_MAX + 1 + TIME_LENGTH + 1 + LAT_LENGTH + 1 + LON_LENGTH + 1 + \ + ALT_LENGTH_MAX + 1 + SAT_LENGTH + 1 + VOLT_LENGTH + 1 + OP_STAT_LENGTH + 1 + TEMP_LENGTH + \ + sizeof("*") + CHECKSUM_LENGTH + TX_BUF_POSTFIX_LENGTH + + +#endif diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/string.c b/prototype/firmware/EDBG UART erert/EDBG UART erert/string.c new file mode 100644 index 00000000..b95e12a0 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/string.c @@ -0,0 +1,194 @@ +/* + * helper functions - string conversion + * + * Stefan Biereigel + * + */ + +#include + +/* atoid32 + * converts a fixed-length input string to 32bit integers, + * containing respective integer and decimal parts of input string + */ +void atoid32(char *string, uint8_t len, uint32_t *integer, uint32_t *decimal) { + uint8_t j; + uint32_t mult = 1; + uint8_t int_port = 0; + + *integer = 0; + *decimal = 0; + for (j = 0; j < len; j++) { + if (*(string + len - j - 1) == '.') { + mult = 1; + int_port = 1; + } else { + if (int_port) { + *integer += mult * (*(string + len - j - 1) - '0'); + } else { + *decimal += mult * (*(string + len - j - 1) - '0'); + } + mult *= 10; + } + } +} + +/* atod32 + * converts a fixed-length input string to 32bit integer, representing its decimal part, + */ +void atod32(char *string, uint8_t len, uint32_t *decimal) { + uint8_t j; + uint32_t mult = 1; + + *decimal = 0; + for (j = 0; j < len; j++) { + if (*(string + len - j - 1) == '.') { + return; + } else { + *decimal += mult * (*(string + len - j - 1) - '0'); + mult *= 10; + } + } +} + +/* atoi32 + * converts a fixed-length input string to 32bit integer, stops at decimal points, + * so only integer part is returned + * + * the number MUST include a decimal portion (XX.XX) + */ +void atoi32(volatile char *string, uint8_t len, uint32_t *integer) { + uint8_t j; + uint32_t mult = 1; + uint8_t start = 0; + + *integer = 0; + for (j = 0; j < len; j++) { + if (*(string + len - j - 1) == '.') { + start = 1; + } else { + if (start) { + *integer += mult * (*(string + len - j - 1) - '0'); + mult *= 10; + } + } + } +} + +/* atoi16 + * converts a fixed-length input string to 16bit integer, stops at decimal points, + * so only integer part is returned + * + * the number MUST include a decimal portion (XX.XX) + */ +void atoi16(volatile char *string, uint8_t len, uint16_t *integer) { + uint8_t j; + uint16_t mult = 1; + uint8_t start = 0; + + *integer = 0; + for (j = 0; j < len; j++) { + if (*(string + len - j - 1) == '.') { + start = 1; + } else { + if (start) { + *integer += mult * (*(string + len - j - 1) - '0'); + mult *= 10; + } + } + } +} + +/* atoi8 + * converts a fixed-length input string to 8bit integer, stops at decimal points, + * so only integer part is returned + * + * the input MUST NOT include a decimal portion + */ +void atoi8(volatile char *string, uint8_t len, uint8_t *integer) { + uint8_t j; + uint32_t mult = 1; + + *integer = 0; + for (j = 0; j < len; j++) { + *integer += mult * (*(string + len - j - 1) - '0'); + mult *= 10; + } +} + +/* i32toa + * 32 bit number to fixed-length output char + */ +void i32toa(uint32_t in, uint8_t len, volatile char *out) { + uint8_t i; + uint32_t mult = 1; + for (i = len; i > 0; i--) { + *(out + i - 1) = ((in % (mult*10)) / mult) + '0'; + mult *= 10; + } +} + +/* i16toa + * 16 bit number to fixed-length output char + */ +void i16toa(uint16_t in, uint8_t len, volatile char *out) { + uint8_t i; + uint16_t mult = 1; + for (i = len; i > 0; i--) { + *(out + i - 1) = ((in % (mult*10)) / mult) + '0'; + mult *= 10; + } +} + +/* i16toa + * 16 bit number to variable-length output char + * + * returns: length of string + */ +uint8_t i16toav(uint16_t in, volatile char *out) { + uint16_t mult = 10000; + uint8_t cnt = 0; + uint8_t start = 0; + uint8_t len = 0; + if (in == 0) { + *out = '0'; + return 1; + } + + while(mult > 0) { + if (in >= mult) { + in = in - mult; + cnt++; + start = 1; + } else { + *out = cnt + '0'; + cnt = 0; + mult /= 10; + if (start) { + out++; + len++; + } + } + } + + return len; +} + +/* i16tox + * 16 bit number to hexadecimal char representation + * + * writes 4 chars to the output pointer + */ +void i16tox(uint16_t x, char *out) { + uint8_t i; + uint8_t tmp; + for (i = 0; i < 4; i++) { + tmp = (uint8_t) ((x >> (4*i)) & 0x000f); + if (tmp < 10) { + *(out+3-i) = '0' + tmp; + } else { + *(out+3-i) = 'A' + tmp - 10; + } + } +} + diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/string.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/string.h new file mode 100644 index 00000000..95ea6dd8 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/string.h @@ -0,0 +1,16 @@ +#ifndef STRING_H_ +#define STRING_H_ + +#include + +void atoi32(volatile char *string, uint8_t len, uint32_t *integer); +void atoi16(volatile char *string, uint8_t len, uint16_t *integer); +void atoi8(volatile char *string, uint8_t len, uint8_t *integer); +void atoid32(char *string, uint8_t len, uint32_t *integer, uint32_t *decimal); +void atod32(char *string, uint8_t len, uint32_t *decimal); +void i32toa(uint32_t in, uint8_t len, volatile char *out); +void i16toa(uint16_t in, uint8_t len, volatile char *out); +uint8_t i16toav(uint16_t in, volatile char *out); +void i16tox(uint16_t x, char *out); + +#endif diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/telemetry.c b/prototype/firmware/EDBG UART erert/EDBG UART erert/telemetry.c new file mode 100644 index 00000000..c7364206 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/telemetry.c @@ -0,0 +1,240 @@ +/* +* Telemetry strings and formatting +* +* for Pico Balloon Tracker using HC12 radio module and GPS +* HC12 Module with STM8S003F3 processor and silabs Si4463 Radio +* +* Derived Work Copyright (c) 2018 Imperial College Space Society +* From original work Copyright (C) 2014 Richard Meadows +* +* +* Permission is hereby granted, free of charge, to any person obtaining +* a copy of this software and associated documentation files (the +* "Software"), to deal in the Software without restriction, including +* without limitation the rights to use, copy, modify, merge, publish, +* distribute, sublicense, and/or sell copies of the Software, and to +* permit persons to whom the Software is furnished to do so, subject to +* the following conditions: +* +* The above copyright notice and this permission notice shall be +* included in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE +* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*/ + +#include +#include +#include +#include +#include "telemetry.h" +#include "string.h" +#include "fix.h" +#include "main.h" + + +/* A lot of work for the telemetry and gps communication is taken from +* https://github.com/thasti/utrak +*/ + + + +extern volatile uint16_t tlm_tick; +extern uint16_t tx_buf_rdy; +extern uint16_t tx_buf_length; +extern char tx_buf[TX_BUF_MAX_LENGTH]; +extern char telemetry_string[TX_BUF_MAX_LENGTH]; +extern struct gps_fix current_fix; + +/* calculated sentence ID length, used for variable length buffer */ +uint16_t tlm_sent_id_length; +uint16_t tlm_alt_length; + +/** +* TELEMETRY OUTPUT +* ============================================================================= +*/ + +/** +* The type of telemetry we're currently outputting +*/ +enum telemetry_t telemetry_type; +/** +* Current output +*/ +int8_t telemetry_string_length = 0; +/** +* Where we are in the current output +*/ +int8_t telemetry_index; +/** +* Is the radio currently on? +*/ +uint8_t radio_on = 0; + + + +/** +* CYCLIC REDUNDANCY CHECK (CRC) +* ============================================================================= +*/ + +/** +* CRC Function for the XMODEM protocol. +* http://www.nongnu.org/avr-libc/user-manual/group__util__crc.html#gaca726c22a1900f9bad52594c8846115f +*/ +uint16_t crc_xmodem_update(uint16_t crc, uint8_t data) +{ + int i; + + crc = crc ^ ((uint16_t)data << 8); + for (i = 0; i < 8; i++) { + if (crc & 0x8000) { + crc = (crc << 1) ^ 0x1021; + } else { + crc <<= 1; + } + } + + return crc; +} + +/** +* Calcuates the CRC checksum for a communications string +* See http://ukhas.org.uk/communication:protocol +*/ +uint16_t calculate_txbuf_checksum(void) +{ + size_t i; + uint16_t crc; + crc = 0xFFFF; + + for (i = TX_BUF_CHECKSUM_BEGIN; i < TX_BUF_CHECKSUM_END; i++) { + crc = crc_xmodem_update(crc, tx_buf[i]); + } + + return crc; +} + + +/* +* prepare_tx_buffer +* +* fills tx_buf with telemetry values. this depends on the +* GPS having a fix and telemetry being extracted before +* +* telemetry format: +* - callsign +* - sentence id +* - time +* - latitude +* - longitude +* - altitude +* - available satellites +* - voltage of the AAA cell(after boosting) +* - op status +* - temperature of radio + +*/ +void prepare_tx_buffer(void) { + static uint16_t sent_id = 0; + int i; + uint16_t crc; + + sent_id++; + tlm_sent_id_length = i16toav(sent_id, &tx_buf[TX_BUF_SENT_ID_START]); + tx_buf[TX_BUF_SENT_ID_START + tlm_sent_id_length] = ','; + + i16toa(current_fix.hour, 2, &tx_buf[TX_BUF_TIME_START]); + i16toa(current_fix.min, 2, &tx_buf[TX_BUF_TIME_START + 2]); + i16toa(current_fix.sec, 2, &tx_buf[TX_BUF_TIME_START + 4]); + tx_buf[TX_BUF_TIME_START + TIME_LENGTH] = ','; + + if (current_fix.lat > 0) { + tx_buf[TX_BUF_LAT_START] = '+'; + i32toa(current_fix.lat, 9, &tx_buf[TX_BUF_LAT_START + 1]); + } else { + tx_buf[TX_BUF_LAT_START] = '-'; + i32toa(0 - current_fix.lat, 9, &tx_buf[TX_BUF_LAT_START + 1]); + } + /* copy fraction of degrees one character towards the end, insert dot */ + /* 012XXXXXX -> 012 XXXXXX */ + for (i = 8; i >= 3; i--) { + tx_buf[TX_BUF_LAT_START + i + 1] = tx_buf[TX_BUF_LAT_START + i]; + } + tx_buf[TX_BUF_LAT_START + 3] = '.'; + tx_buf[TX_BUF_LAT_START + LAT_LENGTH + 1] = ','; + + if (current_fix.lon > 0) { + tx_buf[TX_BUF_LON_START] = '+'; + i32toa(current_fix.lon, 10, &tx_buf[TX_BUF_LON_START + 1]); + } else { + tx_buf[TX_BUF_LON_START] = '-'; + i32toa(0 - current_fix.lon, 10, &tx_buf[TX_BUF_LON_START + 1]); + } + /* copy fraction of degrees one character towards the end, insert dot */ + /* 51XXXXXX -> 51 XXXXXX */ + for (i = 9; i >= 4; i--) { + tx_buf[TX_BUF_LON_START + i + 1] = tx_buf[TX_BUF_LON_START + i]; + } + tx_buf[TX_BUF_LON_START + 4] = '.'; + tx_buf[TX_BUF_LON_START + LON_LENGTH + 1] = ','; + + tlm_alt_length = i16toav(current_fix.alt, &tx_buf[TX_BUF_ALT_START]); + tx_buf[TX_BUF_ALT_START + tlm_alt_length] = ','; + + i16toa(current_fix.num_svs, SAT_LENGTH, &tx_buf[TX_BUF_SAT_START]); + tx_buf[TX_BUF_SAT_START + SAT_LENGTH] = ','; + + i16toa(current_fix.voltage_radio, VOLT_LENGTH, &tx_buf[TX_BUF_VOLT_START]); + tx_buf[TX_BUF_VOLT_START + VOLT_LENGTH] = ','; + + i16toa(current_fix.op_status, OP_STAT_LENGTH, &tx_buf[TX_BUF_OP_STAT_START]); + tx_buf[TX_BUF_OP_STAT_START + OP_STAT_LENGTH] = ','; + + if (current_fix.temp_BME280 < 0) { + tx_buf[TX_BUF_TEMP_START] = '-'; + i16toa(0 - current_fix.temp_BME280, TEMP_LENGTH, &tx_buf[TX_BUF_TEMP_START + 1]); + } else { + tx_buf[TX_BUF_TEMP_START] = '+'; + i16toa(current_fix.temp_BME280, TEMP_LENGTH, &tx_buf[TX_BUF_TEMP_START + 1]); + } + + tx_buf[TX_BUF_TEMP_START + TEMP_LENGTH + 1] = '*'; + + crc = calculate_txbuf_checksum(); + i16tox(crc, &tx_buf[TX_BUF_CHECKSUM_START]); + + for (i = 0; i < TX_BUF_POSTFIX_LENGTH; i++) + tx_buf[TX_BUF_POSTFIX_START + i] = TX_BUF_POSTFIX[i]; + + tx_buf_length = TX_BUF_FRAME_END; + /* trigger transmission */ + tx_buf_rdy = 1; +} + +void tlm_init(void) { + tx_buf_rdy = 1; +} + +/* +* init_tx_buffer +* +* helper routine to fill the TX buffer with "x"es - if any of those get transmitted, +* the field handling is not correct +*/ +void init_tx_buffer(void) { + uint16_t i; + + for (i = TX_BUF_START_OFFSET; i < TX_BUF_MAX_LENGTH; i++) { + tx_buf[i] = 'x'; + } +} + + + diff --git a/prototype/firmware/EDBG UART erert/EDBG UART erert/telemetry.h b/prototype/firmware/EDBG UART erert/EDBG UART erert/telemetry.h new file mode 100644 index 00000000..92542886 --- /dev/null +++ b/prototype/firmware/EDBG UART erert/EDBG UART erert/telemetry.h @@ -0,0 +1,54 @@ +/* + * Telemetry strings and formatting + * + * for Pico Balloon Tracker using HC12 radio module and GPS + * HC12 Module with STM8S003F3 processor and silabs Si4463 Radio + * + * Derived Work Copyright (c) 2018 Imperial College Space Society + * From original work Copyright (C) 2014 Richard Meadows + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef TELEMETRY_H +#define TELEMETRY_H + +#include +#include + + +enum telemetry_t { + TELEMETRY_RTTY, + TELEMETRY_PIPS, +}; + + + +int telemetry_active(void); +int telemetry_start(enum telemetry_t type, int8_t length); +void timer1_tick_init(uint16_t millisecs); +void timer1_tick_time(uint16_t millisecs); +void timer1_tick_deinit(); +void init_tx_buffer(void); +void prepare_tx_buffer(void); + + + +#endif /* TELEMETRY_H */ diff --git a/prototype/firmware/EDBG UART erert/README.md b/prototype/firmware/EDBG UART erert/README.md new file mode 100644 index 00000000..d41c892d --- /dev/null +++ b/prototype/firmware/EDBG UART erert/README.md @@ -0,0 +1 @@ +# tracker MKII test diff --git a/prototype/firmware/EDBG UART erert/debug.log b/prototype/firmware/EDBG UART erert/debug.log new file mode 100644 index 00000000..e69de29b diff --git a/prototype/firmware/GPS_EGDB_bridge/.vs/GPS_EGDB_bridge/v14/.atsuo b/prototype/firmware/GPS_EGDB_bridge/.vs/GPS_EGDB_bridge/v14/.atsuo new file mode 100644 index 00000000..fa5aa366 Binary files /dev/null and b/prototype/firmware/GPS_EGDB_bridge/.vs/GPS_EGDB_bridge/v14/.atsuo differ diff --git a/prototype/firmware/GPS_EGDB_bridge/GPS_EGDB_bridge.atsln b/prototype/firmware/GPS_EGDB_bridge/GPS_EGDB_bridge.atsln new file mode 100644 index 00000000..543aad91 --- /dev/null +++ b/prototype/firmware/GPS_EGDB_bridge/GPS_EGDB_bridge.atsln @@ -0,0 +1,22 @@ + +Microsoft Visual Studio Solution File, Format Version 12.00 +# Atmel Studio Solution File, Format Version 11.00 +VisualStudioVersion = 14.0.23107.0 +MinimumVisualStudioVersion = 10.0.40219.1 +Project("{54F91283-7BC4-4236-8FF9-10F437C3AD48}") = "GPS_EGDB_bridge_ASYN_UART", "GPS_EGDB_bridge\GPS_EGDB_bridge_ASYN_UART.cproj", "{DCE6C7E3-EE26-4D79-826B-08594B9AD897}" +EndProject +Global + GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug|ARM = Debug|ARM + Release|ARM = Release|ARM + EndGlobalSection + GlobalSection(ProjectConfigurationPlatforms) = postSolution + {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|ARM.ActiveCfg = Debug|ARM + {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|ARM.Build.0 = Debug|ARM + {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|ARM.ActiveCfg = Release|ARM + {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|ARM.Build.0 = Release|ARM + EndGlobalSection + GlobalSection(SolutionProperties) = preSolution + HideSolutionNode = FALSE + EndGlobalSection +EndGlobal diff --git a/prototype/firmware/GPS_EGDB_bridge/GPS_EGDB_bridge/.atmelstart/AtmelStart.env_conf b/prototype/firmware/GPS_EGDB_bridge/GPS_EGDB_bridge/.atmelstart/AtmelStart.env_conf new file mode 100644 index 00000000..ecbeeb71 --- /dev/null +++ b/prototype/firmware/GPS_EGDB_bridge/GPS_EGDB_bridge/.atmelstart/AtmelStart.env_conf @@ -0,0 +1,6 @@ + + + + + + diff --git a/prototype/firmware/GPS_EGDB_bridge/GPS_EGDB_bridge/.atmelstart/AtmelStart.gpdsc b/prototype/firmware/GPS_EGDB_bridge/GPS_EGDB_bridge/.atmelstart/AtmelStart.gpdsc new file mode 100644 index 00000000..94cb8c58 --- /dev/null +++ b/prototype/firmware/GPS_EGDB_bridge/GPS_EGDB_bridge/.atmelstart/AtmelStart.gpdsc @@ -0,0 +1,181 @@ + + Atmel + EDBG UART + Project generated by Atmel Start + http://start.atmel.com/ + + Initial version + + + Configuration Files generated by Atmel Start + + + + Atmel Start + + http://start.atmel.com/ + + + + + + + + + Dependency on CMSIS core and Device Startup components + + + + + + + + + + + + + + + + + + + + + + + + + Atmel Start Framework + #define ATMEL_START + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/.atmelstart/atmel_start_config.atstart b/prototype/firmware/I2C_scanner/I2C_scanner/.atmelstart/atmel_start_config.atstart new file mode 100644 index 00000000..65d97d54 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/.atmelstart/atmel_start_config.atstart @@ -0,0 +1,692 @@ +format_version: '2' +name: My Project +versions: + api: '1.0' + backend: 1.5.122 + commit: 820baecf7dd115d94b0d42ee3b0b9d6ba2da7113 + content: 1.0.1465 + content_pack_name: acme-packs-all + format: '2' + frontend: 1.5.1826 +board: + identifier: SAML21XplainedPro + device: SAML21J18B-AU +details: null +application: null +middlewares: + STDIO_REDIRECT_0: + user_label: STDIO_REDIRECT_0 + configuration: {} + definition: Atmel:STDIO_redirect:0.0.1::STDIO_Redirect + functionality: STDIO_Redirect + api: STDIO:Redirect:IO + dependencies: + Target IO: TARGET_IO +drivers: + DMAC: + user_label: DMAC + definition: Atmel:SAML21_Drivers:0.0.1::SAML21J18B-AU::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC + functionality: System + api: HAL:HPL:DMAC + configuration: + dmac_beatsize_0: 8-bit bus transfer + dmac_beatsize_1: 8-bit bus transfer + dmac_beatsize_10: 8-bit bus transfer + dmac_beatsize_11: 8-bit bus transfer + dmac_beatsize_12: 8-bit bus transfer + dmac_beatsize_13: 8-bit bus transfer + dmac_beatsize_14: 8-bit bus transfer + dmac_beatsize_15: 8-bit bus transfer + dmac_beatsize_2: 8-bit bus transfer + dmac_beatsize_3: 8-bit bus transfer + dmac_beatsize_4: 8-bit bus transfer + dmac_beatsize_5: 8-bit bus transfer + dmac_beatsize_6: 8-bit bus transfer + dmac_beatsize_7: 8-bit bus transfer + dmac_beatsize_8: 8-bit bus transfer + dmac_beatsize_9: 8-bit bus transfer + dmac_blockact_0: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_1: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_10: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_11: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_12: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_13: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_14: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_15: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_2: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_3: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_4: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_5: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_6: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_7: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_8: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_9: Channel will be disabled if it is the last block transfer in + the transaction + dmac_channel_0_settings: false + dmac_channel_10_settings: false + dmac_channel_11_settings: false + dmac_channel_12_settings: false + dmac_channel_13_settings: false + dmac_channel_14_settings: false + dmac_channel_15_settings: false + dmac_channel_1_settings: false + dmac_channel_2_settings: false + dmac_channel_3_settings: false + dmac_channel_4_settings: false + dmac_channel_5_settings: false + dmac_channel_6_settings: false + dmac_channel_7_settings: false + dmac_channel_8_settings: false + dmac_channel_9_settings: false + dmac_dbgrun: false + dmac_dqos: Background (no sensitive operation) + dmac_dstinc_0: false + dmac_dstinc_1: false + dmac_dstinc_10: false + dmac_dstinc_11: false + dmac_dstinc_12: false + dmac_dstinc_13: false + dmac_dstinc_14: false + dmac_dstinc_15: false + dmac_dstinc_2: false + dmac_dstinc_3: false + dmac_dstinc_4: false + dmac_dstinc_5: false + dmac_dstinc_6: false + dmac_dstinc_7: false + dmac_dstinc_8: false + dmac_dstinc_9: false + dmac_enable: false + dmac_enable_0: false + dmac_enable_1: false + dmac_enable_10: false + dmac_enable_11: false + dmac_enable_12: false + dmac_enable_13: false + dmac_enable_14: false + dmac_enable_15: false + dmac_enable_2: false + dmac_enable_3: false + dmac_enable_4: false + dmac_enable_5: false + dmac_enable_6: false + dmac_enable_7: false + dmac_enable_8: false + dmac_enable_9: false + dmac_evact_0: No action + dmac_evact_1: No action + dmac_evact_10: No action + dmac_evact_11: No action + dmac_evact_12: No action + dmac_evact_13: No action + dmac_evact_14: No action + dmac_evact_15: No action + dmac_evact_2: No action + dmac_evact_3: No action + dmac_evact_4: No action + dmac_evact_5: No action + dmac_evact_6: No action + dmac_evact_7: No action + dmac_evact_8: No action + dmac_evact_9: No action + dmac_evie_0: false + dmac_evie_1: false + dmac_evie_10: false + dmac_evie_11: false + dmac_evie_12: false + dmac_evie_13: false + dmac_evie_14: false + dmac_evie_15: false + dmac_evie_2: false + dmac_evie_3: false + dmac_evie_4: false + dmac_evie_5: false + dmac_evie_6: false + dmac_evie_7: false + dmac_evie_8: false + dmac_evie_9: false + dmac_evoe_0: false + dmac_evoe_1: false + dmac_evoe_10: false + dmac_evoe_11: false + dmac_evoe_12: false + dmac_evoe_13: false + dmac_evoe_14: false + dmac_evoe_15: false + dmac_evoe_2: false + dmac_evoe_3: false + dmac_evoe_4: false + dmac_evoe_5: false + dmac_evoe_6: false + dmac_evoe_7: false + dmac_evoe_8: false + dmac_evoe_9: false + dmac_evosel_0: Event generation disabled + dmac_evosel_1: Event generation disabled + dmac_evosel_10: Event generation disabled + dmac_evosel_11: Event generation disabled + dmac_evosel_12: Event generation disabled + dmac_evosel_13: Event generation disabled + dmac_evosel_14: Event generation disabled + dmac_evosel_15: Event generation disabled + dmac_evosel_2: Event generation disabled + dmac_evosel_3: Event generation disabled + dmac_evosel_4: Event generation disabled + dmac_evosel_5: Event generation disabled + dmac_evosel_6: Event generation disabled + dmac_evosel_7: Event generation disabled + dmac_evosel_8: Event generation disabled + dmac_evosel_9: Event generation disabled + dmac_fqos: Background (no sensitive operation) + dmac_lvl_0: Channel priority 0 + dmac_lvl_1: Channel priority 0 + dmac_lvl_10: Channel priority 0 + dmac_lvl_11: Channel priority 0 + dmac_lvl_12: Channel priority 0 + dmac_lvl_13: Channel priority 0 + dmac_lvl_14: Channel priority 0 + dmac_lvl_15: Channel priority 0 + dmac_lvl_2: Channel priority 0 + dmac_lvl_3: Channel priority 0 + dmac_lvl_4: Channel priority 0 + dmac_lvl_5: Channel priority 0 + dmac_lvl_6: Channel priority 0 + dmac_lvl_7: Channel priority 0 + dmac_lvl_8: Channel priority 0 + dmac_lvl_9: Channel priority 0 + dmac_lvlen0: false + dmac_lvlen1: false + dmac_lvlen2: false + dmac_lvlen3: false + dmac_lvlpri0: 0 + dmac_lvlpri1: 0 + dmac_lvlpri2: 0 + dmac_lvlpri3: 0 + dmac_rrlvlen0: Static arbitration scheme for channel with priority 0 + dmac_rrlvlen1: Static arbitration scheme for channel with priority 1 + dmac_rrlvlen2: Static arbitration scheme for channel with priority 2 + dmac_rrlvlen3: Static arbitration scheme for channel with priority 3 + dmac_runstdby_0: false + dmac_runstdby_1: false + dmac_runstdby_10: false + dmac_runstdby_11: false + dmac_runstdby_12: false + dmac_runstdby_13: false + dmac_runstdby_14: false + dmac_runstdby_15: false + dmac_runstdby_2: false + dmac_runstdby_3: false + dmac_runstdby_4: false + dmac_runstdby_5: false + dmac_runstdby_6: false + dmac_runstdby_7: false + dmac_runstdby_8: false + dmac_runstdby_9: false + dmac_srcinc_0: false + dmac_srcinc_1: false + dmac_srcinc_10: false + dmac_srcinc_11: false + dmac_srcinc_12: false + dmac_srcinc_13: false + dmac_srcinc_14: false + dmac_srcinc_15: false + dmac_srcinc_2: false + dmac_srcinc_3: false + dmac_srcinc_4: false + dmac_srcinc_5: false + dmac_srcinc_6: false + dmac_srcinc_7: false + dmac_srcinc_8: false + dmac_srcinc_9: false + dmac_stepsel_0: Step size settings apply to the destination address + dmac_stepsel_1: Step size settings apply to the destination address + dmac_stepsel_10: Step size settings apply to the destination address + dmac_stepsel_11: Step size settings apply to the destination address + dmac_stepsel_12: Step size settings apply to the destination address + dmac_stepsel_13: Step size settings apply to the destination address + dmac_stepsel_14: Step size settings apply to the destination address + dmac_stepsel_15: Step size settings apply to the destination address + dmac_stepsel_2: Step size settings apply to the destination address + dmac_stepsel_3: Step size settings apply to the destination address + dmac_stepsel_4: Step size settings apply to the destination address + dmac_stepsel_5: Step size settings apply to the destination address + dmac_stepsel_6: Step size settings apply to the destination address + dmac_stepsel_7: Step size settings apply to the destination address + dmac_stepsel_8: Step size settings apply to the destination address + dmac_stepsel_9: Step size settings apply to the destination address + dmac_stepsize_0: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_1: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_10: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_11: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_12: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_13: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_14: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_15: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_2: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_3: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_4: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_5: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_6: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_7: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_8: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_9: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_trifsrc_0: Only software/event triggers + dmac_trifsrc_1: Only software/event triggers + dmac_trifsrc_10: Only software/event triggers + dmac_trifsrc_11: Only software/event triggers + dmac_trifsrc_12: Only software/event triggers + dmac_trifsrc_13: Only software/event triggers + dmac_trifsrc_14: Only software/event triggers + dmac_trifsrc_15: Only software/event triggers + dmac_trifsrc_2: Only software/event triggers + dmac_trifsrc_3: Only software/event triggers + dmac_trifsrc_4: Only software/event triggers + dmac_trifsrc_5: Only software/event triggers + dmac_trifsrc_6: Only software/event triggers + dmac_trifsrc_7: Only software/event triggers + dmac_trifsrc_8: Only software/event triggers + dmac_trifsrc_9: Only software/event triggers + dmac_trigact_0: One trigger required for each block transfer + dmac_trigact_1: One trigger required for each block transfer + dmac_trigact_10: One trigger required for each block transfer + dmac_trigact_11: One trigger required for each block transfer + dmac_trigact_12: One trigger required for each block transfer + dmac_trigact_13: One trigger required for each block transfer + dmac_trigact_14: One trigger required for each block transfer + dmac_trigact_15: One trigger required for each block transfer + dmac_trigact_2: One trigger required for each block transfer + dmac_trigact_3: One trigger required for each block transfer + dmac_trigact_4: One trigger required for each block transfer + dmac_trigact_5: One trigger required for each block transfer + dmac_trigact_6: One trigger required for each block transfer + dmac_trigact_7: One trigger required for each block transfer + dmac_trigact_8: One trigger required for each block transfer + dmac_trigact_9: One trigger required for each block transfer + dmac_wrbqos: Background (no sensitive operation) + optional_signals: [] + variant: null + clocks: + domain_group: null + GCLK: + user_label: GCLK + definition: Atmel:SAML21_Drivers:0.0.1::SAML21J18B-AU::GCLK::driver_config_definition::GCLK::HAL:HPL:GCLK + functionality: System + api: HAL:HPL:GCLK + configuration: + enable_gclk_gen_0: true + enable_gclk_gen_1: false + enable_gclk_gen_2: false + enable_gclk_gen_3: false + enable_gclk_gen_4: false + enable_gclk_gen_5: false + enable_gclk_gen_6: false + enable_gclk_gen_7: false + gclk_arch_gen_0_enable: true + gclk_arch_gen_0_idc: false + gclk_arch_gen_0_oe: false + gclk_arch_gen_0_oov: false + gclk_arch_gen_0_runstdby: false + gclk_arch_gen_1_enable: false + gclk_arch_gen_1_idc: false + gclk_arch_gen_1_oe: false + gclk_arch_gen_1_oov: false + gclk_arch_gen_1_runstdby: false + gclk_arch_gen_2_enable: false + gclk_arch_gen_2_idc: false + gclk_arch_gen_2_oe: false + gclk_arch_gen_2_oov: false + gclk_arch_gen_2_runstdby: false + gclk_arch_gen_3_enable: false + gclk_arch_gen_3_idc: false + gclk_arch_gen_3_oe: false + gclk_arch_gen_3_oov: false + gclk_arch_gen_3_runstdby: false + gclk_arch_gen_4_enable: false + gclk_arch_gen_4_idc: false + gclk_arch_gen_4_oe: false + gclk_arch_gen_4_oov: false + gclk_arch_gen_4_runstdby: false + gclk_arch_gen_5_enable: false + gclk_arch_gen_5_idc: false + gclk_arch_gen_5_oe: false + gclk_arch_gen_5_oov: false + gclk_arch_gen_5_runstdby: false + gclk_arch_gen_6_enable: false + gclk_arch_gen_6_idc: false + gclk_arch_gen_6_oe: false + gclk_arch_gen_6_oov: false + gclk_arch_gen_6_runstdby: false + gclk_arch_gen_7_enable: false + gclk_arch_gen_7_idc: false + gclk_arch_gen_7_oe: false + gclk_arch_gen_7_oov: false + gclk_arch_gen_7_runstdby: false + gclk_gen_0_div: 1 + gclk_gen_0_div_sel: false + gclk_gen_0_oscillator: 16MHz Internal Oscillator (OSC16M) + gclk_gen_1_div: 1 + gclk_gen_1_div_sel: false + gclk_gen_1_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC) + gclk_gen_2_div: 1 + gclk_gen_2_div_sel: false + gclk_gen_2_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC) + gclk_gen_3_div: 1 + gclk_gen_3_div_sel: false + gclk_gen_3_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC) + gclk_gen_4_div: 1 + gclk_gen_4_div_sel: false + gclk_gen_4_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC) + gclk_gen_5_div: 1 + gclk_gen_5_div_sel: false + gclk_gen_5_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC) + gclk_gen_6_div: 1 + gclk_gen_6_div_sel: false + gclk_gen_6_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC) + gclk_gen_7_div: 1 + gclk_gen_7_div_sel: false + gclk_gen_7_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC) + optional_signals: [] + variant: null + clocks: + domain_group: null + MCLK: + user_label: MCLK + definition: Atmel:SAML21_Drivers:0.0.1::SAML21J18B-AU::MCLK::driver_config_definition::MCLK::HAL:HPL:MCLK + functionality: System + api: HAL:HPL:MCLK + configuration: + cpu_clock_source: Generic clock generator 0 + cpu_div: '1' + enable_cpu_clock: true + mclk_arch_bupdiv: Divide by 8 + mclk_arch_lpdiv: Divide by 4 + nvm_wait_states: '0' + optional_signals: [] + variant: null + clocks: + domain_group: + nodes: + - name: CPU + input: CPU + external: false + external_frequency: 0 + configuration: {} + OSC32KCTRL: + user_label: OSC32KCTRL + definition: Atmel:SAML21_Drivers:0.0.1::SAML21J18B-AU::OSC32KCTRL::driver_config_definition::OSC32KCTRL::HAL:HPL:OSC32KCTRL + functionality: System + api: HAL:HPL:OSC32KCTRL + configuration: + enable_osc32k: false + enable_osculp32k: true + enable_rtc_source: false + enable_xosc32k: false + osc32k_arch_calib: 0 + osc32k_arch_calib_enable: false + osc32k_arch_en1k: false + osc32k_arch_en32k: false + osc32k_arch_enable: false + osc32k_arch_ondemand: false + osc32k_arch_runstdby: false + osc32k_arch_startup: 92us + osculp32k_calib: 0 + osculp32k_calib_enable: false + rtc_1khz_selection: false + rtc_source_oscillator: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) + xosc32k_arch_en1k: false + xosc32k_arch_en32k: false + xosc32k_arch_enable: false + xosc32k_arch_ondemand: true + xosc32k_arch_runstdby: false + xosc32k_arch_startup: 62592us + xosc32k_arch_xtalen: true + optional_signals: [] + variant: null + clocks: + domain_group: null + OSCCTRL: + user_label: OSCCTRL + definition: Atmel:SAML21_Drivers:0.0.1::SAML21J18B-AU::OSCCTRL::driver_config_definition::OSCCTRL::HAL:HPL:OSCCTRL + functionality: System + api: HAL:HPL:OSCCTRL + configuration: + dfll48m_arch_enable: false + dfll48m_mode: Open Loop Mode + dfll48m_mul: 0 + dfll48m_ref_clock: Generic clock generator 3 + dfll_arch_bplckc: false + dfll_arch_calibration: false + dfll_arch_ccdis: false + dfll_arch_coarse: 31 + dfll_arch_cstep: 1 + dfll_arch_fine: 512 + dfll_arch_fstep: 1 + dfll_arch_llaw: false + dfll_arch_ondemand: true + dfll_arch_qldis: false + dfll_arch_runstdby: false + dfll_arch_stable: false + dfll_arch_usbcrm: false + dfll_arch_waitlock: false + enable_dfll48m: false + enable_fdpll96m: false + enable_osc16m: true + enable_xosc: false + fdpll96m_arch_enable: false + fdpll96m_arch_filter: Default filter mode + fdpll96m_arch_lbypass: false + fdpll96m_arch_lpen: false + fdpll96m_arch_ltime: No time-out, automatic lock + fdpll96m_arch_ondemand: true + fdpll96m_arch_refclk: XOSC32K clock reference + fdpll96m_arch_runstdby: false + fdpll96m_arch_wuf: false + fdpll96m_clock_div: 0 + fdpll96m_ldr: 1463 + fdpll96m_ldrfrac: 13 + fdpll96m_presc: '1' + fdpll96m_ref_clock: 32kHz External Crystal Oscillator (XOSC32K) + osc16m_arch_12m_fcal: 0 + osc16m_arch_12m_tcal: 0 + osc16m_arch_16m_tcal: 0 + osc16m_arch_4m_fcal: 0 + osc16m_arch_4m_tcal: 0 + osc16m_arch_8m_fcal: 0 + osc16m_arch_8m_tcal: 0 + osc16m_arch_calib_enable: false + osc16m_arch_enable: true + osc16m_arch_fcal: 0 + osc16m_arch_ondemand: true + osc16m_arch_runstdby: false + osc16m_freq: '16' + xosc_arch_ampgc: false + xosc_arch_enable: false + xosc_arch_gain: 2MHz + xosc_arch_ondemand: true + xosc_arch_runstdby: false + xosc_arch_startup: 31us + xosc_arch_xtalen: false + xosc_frequency: 400000 + optional_signals: [] + variant: null + clocks: + domain_group: null + PORT: + user_label: PORT + definition: Atmel:SAML21_Drivers:0.0.1::SAML21J18B-AU::PORT::driver_config_definition::PORT::HAL:HPL:PORT + functionality: System + api: HAL:HPL:PORT + configuration: + enable_port_input_event_0: false + enable_port_input_event_1: false + enable_port_input_event_2: false + enable_port_input_event_3: false + porta_event_action_0: Output register of pin will be set to level of event + porta_event_action_1: Output register of pin will be set to level of event + porta_event_action_2: Output register of pin will be set to level of event + porta_event_action_3: Output register of pin will be set to level of event + porta_event_pin_identifier_0: 0 + porta_event_pin_identifier_1: 0 + porta_event_pin_identifier_2: 0 + porta_event_pin_identifier_3: 0 + porta_input_event_enable_0: false + porta_input_event_enable_1: false + porta_input_event_enable_2: false + porta_input_event_enable_3: false + portb_event_action_0: Output register of pin will be set to level of event + portb_event_action_1: Output register of pin will be set to level of event + portb_event_action_2: Output register of pin will be set to level of event + portb_event_action_3: Output register of pin will be set to level of event + portb_event_pin_identifier_0: 0 + portb_event_pin_identifier_1: 0 + portb_event_pin_identifier_2: 0 + portb_event_pin_identifier_3: 0 + portb_input_event_enable_0: false + portb_input_event_enable_1: false + portb_input_event_enable_2: false + portb_input_event_enable_3: false + optional_signals: [] + variant: null + clocks: + domain_group: null + I2C_0: + user_label: I2C_0 + definition: Atmel:SAML21_Drivers:0.0.1::SAML21J18B-AU::SERCOM0::driver_config_definition::I2C.Master.Standard~2FFast-mode::HAL:Driver:I2C.Master.Sync + functionality: I2C + api: HAL:Driver:I2C_Master_Sync + configuration: + i2c_master_advanced: false + i2c_master_arch_dbgstop: Keep running + i2c_master_arch_inactout: Disabled + i2c_master_arch_lowtout: false + i2c_master_arch_mexttoen: false + i2c_master_arch_runstdby: false + i2c_master_arch_sdahold: 300-600ns hold time + i2c_master_arch_sexttoen: false + i2c_master_arch_trise: 215 + i2c_master_baud_rate: 100000 + optional_signals: [] + variant: + specification: SDA=0, SCL=1 + required_signals: + - name: SERCOM0/PAD/0 + pad: PA08 + label: SDA + - name: SERCOM0/PAD/1 + pad: PA09 + label: SCL + clocks: + domain_group: + nodes: + - name: Core + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Slow + input: Generic clock generator 3 + external: false + external_frequency: 0 + configuration: + core_gclk_selection: Generic clock generator 0 + slow_gclk_selection: Generic clock generator 3 + TARGET_IO: + user_label: TARGET_IO + definition: Atmel:SAML21_Drivers:0.0.1::SAML21J18B-AU::SERCOM3::driver_config_definition::UART::HAL:Driver:USART.Sync + functionality: USART + api: HAL:Driver:USART_Sync + configuration: + usart_advanced: false + usart_arch_clock_mode: USART with internal clock + usart_arch_cloden: false + usart_arch_dbgstop: Keep running + usart_arch_dord: LSB is transmitted first + usart_arch_enc: No encoding + usart_arch_fractional: 0 + usart_arch_ibon: false + usart_arch_lin_slave_enable: Disable + usart_arch_runstdby: false + usart_arch_sampa: 7-8-9 (3-4-5 8-bit over-sampling) + usart_arch_sampr: 16x arithmetic + usart_arch_sfde: false + usart_baud_rate: 9600 + usart_character_size: 8 bits + usart_parity: No parity + usart_rx_enable: true + usart_stop_bit: One stop bit + usart_tx_enable: true + optional_signals: [] + variant: + specification: TXPO=0, RXPO=1, CMODE=0 + required_signals: + - name: SERCOM3/PAD/0 + pad: PA22 + label: TX + - name: SERCOM3/PAD/1 + pad: PA23 + label: RX + clocks: + domain_group: + nodes: + - name: Core + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Slow + input: Generic clock generator 3 + external: false + external_frequency: 0 + configuration: + core_gclk_selection: Generic clock generator 0 + slow_gclk_selection: Generic clock generator 3 + DELAY_0: + user_label: DELAY_0 + definition: Atmel:SAML21_Drivers:0.0.1::SAML21J18B-AU::SysTick::driver_config_definition::Delay::HAL:Driver:Delay + functionality: Delay + api: HAL:Driver:Delay + configuration: + systick_arch_tickint: false + optional_signals: [] + variant: null + clocks: + domain_group: null +pads: + PA08: + name: PA08 + definition: Atmel:SAML21_Drivers:0.0.1::SAML21J18B-AU::pad::PA08 + mode: I2C + user_label: PA08 + configuration: null + PA09: + name: PA09 + definition: Atmel:SAML21_Drivers:0.0.1::SAML21J18B-AU::pad::PA09 + mode: I2C + user_label: PA09 + configuration: null + PA22: + name: PA22 + definition: Atmel:SAML21_Drivers:0.0.1::SAML21J18B-AU::pad::PA22 + mode: Peripheral IO + user_label: PA22 + configuration: null + PA23: + name: PA23 + definition: Atmel:SAML21_Drivers:0.0.1::SAML21J18B-AU::pad::PA23 + mode: Peripheral IO + user_label: PA23 + configuration: null +toolchain_options: [] diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/Config/RTE_Components.h b/prototype/firmware/I2C_scanner/I2C_scanner/Config/RTE_Components.h new file mode 100644 index 00000000..b0c81ec6 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/Config/RTE_Components.h @@ -0,0 +1,54 @@ + /** + * \file + * + * \brief Autogenerated API include file for the Atmel Configuration Management Engine (ACME) + * + * Copyright (c) 2012 Atmel Corporation. All rights reserved. + * + * \acme_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \acme_license_stop + * + * Project: I2C_scanner + * Target: ATSAML21J18B + * + **/ + + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +#define ATMEL_START + +#endif /* RTE_COMPONENTS_H */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/Config/hpl_dmac_config.h b/prototype/firmware/I2C_scanner/I2C_scanner/Config/hpl_dmac_config.h new file mode 100644 index 00000000..78aed2d5 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/Config/hpl_dmac_config.h @@ -0,0 +1,3154 @@ +/* Auto-generated config file hpl_dmac_config.h */ +#ifndef HPL_DMAC_CONFIG_H +#define HPL_DMAC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// DMAC enable +// Indicates whether dmac is enabled or not +// dmac_enable +#ifndef CONF_DMAC_ENABLE +#define CONF_DMAC_ENABLE 0 +#endif + +// Priority Level 0 +// Indicates whether Priority Level 0 is enabled or not +// dmac_lvlen0 +#ifndef CONF_DMAC_LVLEN0 +#define CONF_DMAC_LVLEN0 0 +#endif + +// Level 0 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 0 +// <1=> Round-robin arbitration scheme for channel with priority 0 +// Defines Level 0 Arbitration for DMA channels +// dmac_rrlvlen0 +#ifndef CONF_DMAC_RRLVLEN0 +#define CONF_DMAC_RRLVLEN0 0 +#endif + +// Level 0 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri0 +#ifndef CONF_DMAC_LVLPRI0 +#define CONF_DMAC_LVLPRI0 0 +#endif + +// Priority Level 1 +// Indicates whether Priority Level 1 is enabled or not +// dmac_lvlen1 +#ifndef CONF_DMAC_LVLEN1 +#define CONF_DMAC_LVLEN1 0 +#endif + +// Level 1 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 1 +// <1=> Round-robin arbitration scheme for channel with priority 1 +// Defines Level 1 Arbitration for DMA channels +// dmac_rrlvlen1 +#ifndef CONF_DMAC_RRLVLEN1 +#define CONF_DMAC_RRLVLEN1 0 +#endif + +// Level 1 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri1 +#ifndef CONF_DMAC_LVLPRI1 +#define CONF_DMAC_LVLPRI1 0 +#endif + +// Priority Level 2 +// Indicates whether Priority Level 2 is enabled or not +// dmac_lvlen2 +#ifndef CONF_DMAC_LVLEN2 +#define CONF_DMAC_LVLEN2 0 +#endif + +// Level 2 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 2 +// <1=> Round-robin arbitration scheme for channel with priority 2 +// Defines Level 2 Arbitration for DMA channels +// dmac_rrlvlen2 +#ifndef CONF_DMAC_RRLVLEN2 +#define CONF_DMAC_RRLVLEN2 0 +#endif + +// Level 2 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri2 +#ifndef CONF_DMAC_LVLPRI2 +#define CONF_DMAC_LVLPRI2 0 +#endif + +// Priority Level 3 +// Indicates whether Priority Level 3 is enabled or not +// dmac_lvlen3 +#ifndef CONF_DMAC_LVLEN3 +#define CONF_DMAC_LVLEN3 0 +#endif + +// Level 3 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 3 +// <1=> Round-robin arbitration scheme for channel with priority 3 +// Defines Level 3 Arbitration for DMA channels +// dmac_rrlvlen3 +#ifndef CONF_DMAC_RRLVLEN3 +#define CONF_DMAC_RRLVLEN3 0 +#endif + +// Level 3 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri3 +#ifndef CONF_DMAC_LVLPRI3 +#define CONF_DMAC_LVLPRI3 0 +#endif + +// Data Transfer Quality of Service +// <0=> Background (no sensitive operation) +// <1=> Sensitive bandwidth +// <2=> Sensitive latency +// <3=> Critical latency +// Defines the memory priority access during the data transfer operation +// dmac_dqos +#ifndef CONF_DMAC_DQOS +#define CONF_DMAC_DQOS 0 +#endif + +// Fetch Quality of Service +// <0=> Background (no sensitive operation) +// <1=> Sensitive bandwidth +// <2=> Sensitive latency +// <3=> Critical latency +// Defines the memory priority access during the fetch operation +// dmac_fqos +#ifndef CONF_DMAC_FQOS +#define CONF_DMAC_FQOS 0 +#endif + +// Write-Back Quality of Service +// <0=> Background (no sensitive operation) +// <1=> Sensitive bandwidth +// <2=> Sensitive latency +// <3=> Critical latency +// Defines the memory priority access during the write-back operation +// dmac_wrbqos +#ifndef CONF_DMAC_WRBQOS +#define CONF_DMAC_WRBQOS 0 +#endif + +// Debug Run +// Indicates whether Debug Run is enabled or not +// dmac_dbgrun +#ifndef CONF_DMAC_DBGRUN +#define CONF_DMAC_DBGRUN 0 +#endif + +// Channel 0 settings +// dmac_channel_0_settings +#ifndef CONF_DMAC_CHANNEL_0_SETTINGS +#define CONF_DMAC_CHANNEL_0_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 0 is enabled or not +// dmac_enable_0 +#ifndef CONF_DMAC_ENABLE_0 +#define CONF_DMAC_ENABLE_0 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 0 is running in standby mode or not +// dmac_runstdby_0 +#ifndef CONF_DMAC_RUNSTDBY_0 +#define CONF_DMAC_RUNSTDBY_0 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_0 +#ifndef CONF_DMAC_TRIGACT_0 +#define CONF_DMAC_TRIGACT_0 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_0 +#ifndef CONF_DMAC_TRIGSRC_0 +#define CONF_DMAC_TRIGSRC_0 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_0 +#ifndef CONF_DMAC_LVL_0 +#define CONF_DMAC_LVL_0 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_0 +#ifndef CONF_DMAC_EVOE_0 +#define CONF_DMAC_EVOE_0 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_0 +#ifndef CONF_DMAC_EVIE_0 +#define CONF_DMAC_EVIE_0 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_0 +#ifndef CONF_DMAC_EVACT_0 +#define CONF_DMAC_EVACT_0 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_0 +#ifndef CONF_DMAC_STEPSIZE_0 +#define CONF_DMAC_STEPSIZE_0 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_0 +#ifndef CONF_DMAC_STEPSEL_0 +#define CONF_DMAC_STEPSEL_0 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_0 +#ifndef CONF_DMAC_SRCINC_0 +#define CONF_DMAC_SRCINC_0 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_0 +#ifndef CONF_DMAC_DSTINC_0 +#define CONF_DMAC_DSTINC_0 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_0 +#ifndef CONF_DMAC_BEATSIZE_0 +#define CONF_DMAC_BEATSIZE_0 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_0 +#ifndef CONF_DMAC_BLOCKACT_0 +#define CONF_DMAC_BLOCKACT_0 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_0 +#ifndef CONF_DMAC_EVOSEL_0 +#define CONF_DMAC_EVOSEL_0 0 +#endif +// + +// Channel 1 settings +// dmac_channel_1_settings +#ifndef CONF_DMAC_CHANNEL_1_SETTINGS +#define CONF_DMAC_CHANNEL_1_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 1 is enabled or not +// dmac_enable_1 +#ifndef CONF_DMAC_ENABLE_1 +#define CONF_DMAC_ENABLE_1 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 1 is running in standby mode or not +// dmac_runstdby_1 +#ifndef CONF_DMAC_RUNSTDBY_1 +#define CONF_DMAC_RUNSTDBY_1 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_1 +#ifndef CONF_DMAC_TRIGACT_1 +#define CONF_DMAC_TRIGACT_1 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_1 +#ifndef CONF_DMAC_TRIGSRC_1 +#define CONF_DMAC_TRIGSRC_1 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_1 +#ifndef CONF_DMAC_LVL_1 +#define CONF_DMAC_LVL_1 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_1 +#ifndef CONF_DMAC_EVOE_1 +#define CONF_DMAC_EVOE_1 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_1 +#ifndef CONF_DMAC_EVIE_1 +#define CONF_DMAC_EVIE_1 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_1 +#ifndef CONF_DMAC_EVACT_1 +#define CONF_DMAC_EVACT_1 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_1 +#ifndef CONF_DMAC_STEPSIZE_1 +#define CONF_DMAC_STEPSIZE_1 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_1 +#ifndef CONF_DMAC_STEPSEL_1 +#define CONF_DMAC_STEPSEL_1 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_1 +#ifndef CONF_DMAC_SRCINC_1 +#define CONF_DMAC_SRCINC_1 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_1 +#ifndef CONF_DMAC_DSTINC_1 +#define CONF_DMAC_DSTINC_1 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_1 +#ifndef CONF_DMAC_BEATSIZE_1 +#define CONF_DMAC_BEATSIZE_1 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_1 +#ifndef CONF_DMAC_BLOCKACT_1 +#define CONF_DMAC_BLOCKACT_1 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_1 +#ifndef CONF_DMAC_EVOSEL_1 +#define CONF_DMAC_EVOSEL_1 0 +#endif +// + +// Channel 2 settings +// dmac_channel_2_settings +#ifndef CONF_DMAC_CHANNEL_2_SETTINGS +#define CONF_DMAC_CHANNEL_2_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 2 is enabled or not +// dmac_enable_2 +#ifndef CONF_DMAC_ENABLE_2 +#define CONF_DMAC_ENABLE_2 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 2 is running in standby mode or not +// dmac_runstdby_2 +#ifndef CONF_DMAC_RUNSTDBY_2 +#define CONF_DMAC_RUNSTDBY_2 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_2 +#ifndef CONF_DMAC_TRIGACT_2 +#define CONF_DMAC_TRIGACT_2 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_2 +#ifndef CONF_DMAC_TRIGSRC_2 +#define CONF_DMAC_TRIGSRC_2 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_2 +#ifndef CONF_DMAC_LVL_2 +#define CONF_DMAC_LVL_2 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_2 +#ifndef CONF_DMAC_EVOE_2 +#define CONF_DMAC_EVOE_2 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_2 +#ifndef CONF_DMAC_EVIE_2 +#define CONF_DMAC_EVIE_2 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_2 +#ifndef CONF_DMAC_EVACT_2 +#define CONF_DMAC_EVACT_2 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_2 +#ifndef CONF_DMAC_STEPSIZE_2 +#define CONF_DMAC_STEPSIZE_2 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_2 +#ifndef CONF_DMAC_STEPSEL_2 +#define CONF_DMAC_STEPSEL_2 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_2 +#ifndef CONF_DMAC_SRCINC_2 +#define CONF_DMAC_SRCINC_2 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_2 +#ifndef CONF_DMAC_DSTINC_2 +#define CONF_DMAC_DSTINC_2 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_2 +#ifndef CONF_DMAC_BEATSIZE_2 +#define CONF_DMAC_BEATSIZE_2 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_2 +#ifndef CONF_DMAC_BLOCKACT_2 +#define CONF_DMAC_BLOCKACT_2 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_2 +#ifndef CONF_DMAC_EVOSEL_2 +#define CONF_DMAC_EVOSEL_2 0 +#endif +// + +// Channel 3 settings +// dmac_channel_3_settings +#ifndef CONF_DMAC_CHANNEL_3_SETTINGS +#define CONF_DMAC_CHANNEL_3_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 3 is enabled or not +// dmac_enable_3 +#ifndef CONF_DMAC_ENABLE_3 +#define CONF_DMAC_ENABLE_3 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 3 is running in standby mode or not +// dmac_runstdby_3 +#ifndef CONF_DMAC_RUNSTDBY_3 +#define CONF_DMAC_RUNSTDBY_3 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_3 +#ifndef CONF_DMAC_TRIGACT_3 +#define CONF_DMAC_TRIGACT_3 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_3 +#ifndef CONF_DMAC_TRIGSRC_3 +#define CONF_DMAC_TRIGSRC_3 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_3 +#ifndef CONF_DMAC_LVL_3 +#define CONF_DMAC_LVL_3 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_3 +#ifndef CONF_DMAC_EVOE_3 +#define CONF_DMAC_EVOE_3 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_3 +#ifndef CONF_DMAC_EVIE_3 +#define CONF_DMAC_EVIE_3 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_3 +#ifndef CONF_DMAC_EVACT_3 +#define CONF_DMAC_EVACT_3 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_3 +#ifndef CONF_DMAC_STEPSIZE_3 +#define CONF_DMAC_STEPSIZE_3 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_3 +#ifndef CONF_DMAC_STEPSEL_3 +#define CONF_DMAC_STEPSEL_3 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_3 +#ifndef CONF_DMAC_SRCINC_3 +#define CONF_DMAC_SRCINC_3 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_3 +#ifndef CONF_DMAC_DSTINC_3 +#define CONF_DMAC_DSTINC_3 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_3 +#ifndef CONF_DMAC_BEATSIZE_3 +#define CONF_DMAC_BEATSIZE_3 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_3 +#ifndef CONF_DMAC_BLOCKACT_3 +#define CONF_DMAC_BLOCKACT_3 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_3 +#ifndef CONF_DMAC_EVOSEL_3 +#define CONF_DMAC_EVOSEL_3 0 +#endif +// + +// Channel 4 settings +// dmac_channel_4_settings +#ifndef CONF_DMAC_CHANNEL_4_SETTINGS +#define CONF_DMAC_CHANNEL_4_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 4 is enabled or not +// dmac_enable_4 +#ifndef CONF_DMAC_ENABLE_4 +#define CONF_DMAC_ENABLE_4 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 4 is running in standby mode or not +// dmac_runstdby_4 +#ifndef CONF_DMAC_RUNSTDBY_4 +#define CONF_DMAC_RUNSTDBY_4 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_4 +#ifndef CONF_DMAC_TRIGACT_4 +#define CONF_DMAC_TRIGACT_4 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_4 +#ifndef CONF_DMAC_TRIGSRC_4 +#define CONF_DMAC_TRIGSRC_4 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_4 +#ifndef CONF_DMAC_LVL_4 +#define CONF_DMAC_LVL_4 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_4 +#ifndef CONF_DMAC_EVOE_4 +#define CONF_DMAC_EVOE_4 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_4 +#ifndef CONF_DMAC_EVIE_4 +#define CONF_DMAC_EVIE_4 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_4 +#ifndef CONF_DMAC_EVACT_4 +#define CONF_DMAC_EVACT_4 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_4 +#ifndef CONF_DMAC_STEPSIZE_4 +#define CONF_DMAC_STEPSIZE_4 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_4 +#ifndef CONF_DMAC_STEPSEL_4 +#define CONF_DMAC_STEPSEL_4 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_4 +#ifndef CONF_DMAC_SRCINC_4 +#define CONF_DMAC_SRCINC_4 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_4 +#ifndef CONF_DMAC_DSTINC_4 +#define CONF_DMAC_DSTINC_4 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_4 +#ifndef CONF_DMAC_BEATSIZE_4 +#define CONF_DMAC_BEATSIZE_4 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_4 +#ifndef CONF_DMAC_BLOCKACT_4 +#define CONF_DMAC_BLOCKACT_4 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_4 +#ifndef CONF_DMAC_EVOSEL_4 +#define CONF_DMAC_EVOSEL_4 0 +#endif +// + +// Channel 5 settings +// dmac_channel_5_settings +#ifndef CONF_DMAC_CHANNEL_5_SETTINGS +#define CONF_DMAC_CHANNEL_5_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 5 is enabled or not +// dmac_enable_5 +#ifndef CONF_DMAC_ENABLE_5 +#define CONF_DMAC_ENABLE_5 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 5 is running in standby mode or not +// dmac_runstdby_5 +#ifndef CONF_DMAC_RUNSTDBY_5 +#define CONF_DMAC_RUNSTDBY_5 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_5 +#ifndef CONF_DMAC_TRIGACT_5 +#define CONF_DMAC_TRIGACT_5 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_5 +#ifndef CONF_DMAC_TRIGSRC_5 +#define CONF_DMAC_TRIGSRC_5 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_5 +#ifndef CONF_DMAC_LVL_5 +#define CONF_DMAC_LVL_5 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_5 +#ifndef CONF_DMAC_EVOE_5 +#define CONF_DMAC_EVOE_5 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_5 +#ifndef CONF_DMAC_EVIE_5 +#define CONF_DMAC_EVIE_5 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_5 +#ifndef CONF_DMAC_EVACT_5 +#define CONF_DMAC_EVACT_5 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_5 +#ifndef CONF_DMAC_STEPSIZE_5 +#define CONF_DMAC_STEPSIZE_5 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_5 +#ifndef CONF_DMAC_STEPSEL_5 +#define CONF_DMAC_STEPSEL_5 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_5 +#ifndef CONF_DMAC_SRCINC_5 +#define CONF_DMAC_SRCINC_5 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_5 +#ifndef CONF_DMAC_DSTINC_5 +#define CONF_DMAC_DSTINC_5 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_5 +#ifndef CONF_DMAC_BEATSIZE_5 +#define CONF_DMAC_BEATSIZE_5 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_5 +#ifndef CONF_DMAC_BLOCKACT_5 +#define CONF_DMAC_BLOCKACT_5 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_5 +#ifndef CONF_DMAC_EVOSEL_5 +#define CONF_DMAC_EVOSEL_5 0 +#endif +// + +// Channel 6 settings +// dmac_channel_6_settings +#ifndef CONF_DMAC_CHANNEL_6_SETTINGS +#define CONF_DMAC_CHANNEL_6_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 6 is enabled or not +// dmac_enable_6 +#ifndef CONF_DMAC_ENABLE_6 +#define CONF_DMAC_ENABLE_6 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 6 is running in standby mode or not +// dmac_runstdby_6 +#ifndef CONF_DMAC_RUNSTDBY_6 +#define CONF_DMAC_RUNSTDBY_6 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_6 +#ifndef CONF_DMAC_TRIGACT_6 +#define CONF_DMAC_TRIGACT_6 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_6 +#ifndef CONF_DMAC_TRIGSRC_6 +#define CONF_DMAC_TRIGSRC_6 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_6 +#ifndef CONF_DMAC_LVL_6 +#define CONF_DMAC_LVL_6 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_6 +#ifndef CONF_DMAC_EVOE_6 +#define CONF_DMAC_EVOE_6 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_6 +#ifndef CONF_DMAC_EVIE_6 +#define CONF_DMAC_EVIE_6 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_6 +#ifndef CONF_DMAC_EVACT_6 +#define CONF_DMAC_EVACT_6 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_6 +#ifndef CONF_DMAC_STEPSIZE_6 +#define CONF_DMAC_STEPSIZE_6 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_6 +#ifndef CONF_DMAC_STEPSEL_6 +#define CONF_DMAC_STEPSEL_6 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_6 +#ifndef CONF_DMAC_SRCINC_6 +#define CONF_DMAC_SRCINC_6 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_6 +#ifndef CONF_DMAC_DSTINC_6 +#define CONF_DMAC_DSTINC_6 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_6 +#ifndef CONF_DMAC_BEATSIZE_6 +#define CONF_DMAC_BEATSIZE_6 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_6 +#ifndef CONF_DMAC_BLOCKACT_6 +#define CONF_DMAC_BLOCKACT_6 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_6 +#ifndef CONF_DMAC_EVOSEL_6 +#define CONF_DMAC_EVOSEL_6 0 +#endif +// + +// Channel 7 settings +// dmac_channel_7_settings +#ifndef CONF_DMAC_CHANNEL_7_SETTINGS +#define CONF_DMAC_CHANNEL_7_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 7 is enabled or not +// dmac_enable_7 +#ifndef CONF_DMAC_ENABLE_7 +#define CONF_DMAC_ENABLE_7 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 7 is running in standby mode or not +// dmac_runstdby_7 +#ifndef CONF_DMAC_RUNSTDBY_7 +#define CONF_DMAC_RUNSTDBY_7 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_7 +#ifndef CONF_DMAC_TRIGACT_7 +#define CONF_DMAC_TRIGACT_7 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_7 +#ifndef CONF_DMAC_TRIGSRC_7 +#define CONF_DMAC_TRIGSRC_7 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_7 +#ifndef CONF_DMAC_LVL_7 +#define CONF_DMAC_LVL_7 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_7 +#ifndef CONF_DMAC_EVOE_7 +#define CONF_DMAC_EVOE_7 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_7 +#ifndef CONF_DMAC_EVIE_7 +#define CONF_DMAC_EVIE_7 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_7 +#ifndef CONF_DMAC_EVACT_7 +#define CONF_DMAC_EVACT_7 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_7 +#ifndef CONF_DMAC_STEPSIZE_7 +#define CONF_DMAC_STEPSIZE_7 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_7 +#ifndef CONF_DMAC_STEPSEL_7 +#define CONF_DMAC_STEPSEL_7 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_7 +#ifndef CONF_DMAC_SRCINC_7 +#define CONF_DMAC_SRCINC_7 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_7 +#ifndef CONF_DMAC_DSTINC_7 +#define CONF_DMAC_DSTINC_7 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_7 +#ifndef CONF_DMAC_BEATSIZE_7 +#define CONF_DMAC_BEATSIZE_7 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_7 +#ifndef CONF_DMAC_BLOCKACT_7 +#define CONF_DMAC_BLOCKACT_7 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_7 +#ifndef CONF_DMAC_EVOSEL_7 +#define CONF_DMAC_EVOSEL_7 0 +#endif +// + +// Channel 8 settings +// dmac_channel_8_settings +#ifndef CONF_DMAC_CHANNEL_8_SETTINGS +#define CONF_DMAC_CHANNEL_8_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 8 is enabled or not +// dmac_enable_8 +#ifndef CONF_DMAC_ENABLE_8 +#define CONF_DMAC_ENABLE_8 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 8 is running in standby mode or not +// dmac_runstdby_8 +#ifndef CONF_DMAC_RUNSTDBY_8 +#define CONF_DMAC_RUNSTDBY_8 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_8 +#ifndef CONF_DMAC_TRIGACT_8 +#define CONF_DMAC_TRIGACT_8 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_8 +#ifndef CONF_DMAC_TRIGSRC_8 +#define CONF_DMAC_TRIGSRC_8 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_8 +#ifndef CONF_DMAC_LVL_8 +#define CONF_DMAC_LVL_8 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_8 +#ifndef CONF_DMAC_EVOE_8 +#define CONF_DMAC_EVOE_8 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_8 +#ifndef CONF_DMAC_EVIE_8 +#define CONF_DMAC_EVIE_8 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_8 +#ifndef CONF_DMAC_EVACT_8 +#define CONF_DMAC_EVACT_8 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_8 +#ifndef CONF_DMAC_STEPSIZE_8 +#define CONF_DMAC_STEPSIZE_8 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_8 +#ifndef CONF_DMAC_STEPSEL_8 +#define CONF_DMAC_STEPSEL_8 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_8 +#ifndef CONF_DMAC_SRCINC_8 +#define CONF_DMAC_SRCINC_8 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_8 +#ifndef CONF_DMAC_DSTINC_8 +#define CONF_DMAC_DSTINC_8 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_8 +#ifndef CONF_DMAC_BEATSIZE_8 +#define CONF_DMAC_BEATSIZE_8 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_8 +#ifndef CONF_DMAC_BLOCKACT_8 +#define CONF_DMAC_BLOCKACT_8 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_8 +#ifndef CONF_DMAC_EVOSEL_8 +#define CONF_DMAC_EVOSEL_8 0 +#endif +// + +// Channel 9 settings +// dmac_channel_9_settings +#ifndef CONF_DMAC_CHANNEL_9_SETTINGS +#define CONF_DMAC_CHANNEL_9_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 9 is enabled or not +// dmac_enable_9 +#ifndef CONF_DMAC_ENABLE_9 +#define CONF_DMAC_ENABLE_9 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 9 is running in standby mode or not +// dmac_runstdby_9 +#ifndef CONF_DMAC_RUNSTDBY_9 +#define CONF_DMAC_RUNSTDBY_9 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_9 +#ifndef CONF_DMAC_TRIGACT_9 +#define CONF_DMAC_TRIGACT_9 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_9 +#ifndef CONF_DMAC_TRIGSRC_9 +#define CONF_DMAC_TRIGSRC_9 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_9 +#ifndef CONF_DMAC_LVL_9 +#define CONF_DMAC_LVL_9 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_9 +#ifndef CONF_DMAC_EVOE_9 +#define CONF_DMAC_EVOE_9 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_9 +#ifndef CONF_DMAC_EVIE_9 +#define CONF_DMAC_EVIE_9 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_9 +#ifndef CONF_DMAC_EVACT_9 +#define CONF_DMAC_EVACT_9 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_9 +#ifndef CONF_DMAC_STEPSIZE_9 +#define CONF_DMAC_STEPSIZE_9 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_9 +#ifndef CONF_DMAC_STEPSEL_9 +#define CONF_DMAC_STEPSEL_9 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_9 +#ifndef CONF_DMAC_SRCINC_9 +#define CONF_DMAC_SRCINC_9 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_9 +#ifndef CONF_DMAC_DSTINC_9 +#define CONF_DMAC_DSTINC_9 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_9 +#ifndef CONF_DMAC_BEATSIZE_9 +#define CONF_DMAC_BEATSIZE_9 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_9 +#ifndef CONF_DMAC_BLOCKACT_9 +#define CONF_DMAC_BLOCKACT_9 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_9 +#ifndef CONF_DMAC_EVOSEL_9 +#define CONF_DMAC_EVOSEL_9 0 +#endif +// + +// Channel 10 settings +// dmac_channel_10_settings +#ifndef CONF_DMAC_CHANNEL_10_SETTINGS +#define CONF_DMAC_CHANNEL_10_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 10 is enabled or not +// dmac_enable_10 +#ifndef CONF_DMAC_ENABLE_10 +#define CONF_DMAC_ENABLE_10 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 10 is running in standby mode or not +// dmac_runstdby_10 +#ifndef CONF_DMAC_RUNSTDBY_10 +#define CONF_DMAC_RUNSTDBY_10 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_10 +#ifndef CONF_DMAC_TRIGACT_10 +#define CONF_DMAC_TRIGACT_10 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_10 +#ifndef CONF_DMAC_TRIGSRC_10 +#define CONF_DMAC_TRIGSRC_10 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_10 +#ifndef CONF_DMAC_LVL_10 +#define CONF_DMAC_LVL_10 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_10 +#ifndef CONF_DMAC_EVOE_10 +#define CONF_DMAC_EVOE_10 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_10 +#ifndef CONF_DMAC_EVIE_10 +#define CONF_DMAC_EVIE_10 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_10 +#ifndef CONF_DMAC_EVACT_10 +#define CONF_DMAC_EVACT_10 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_10 +#ifndef CONF_DMAC_STEPSIZE_10 +#define CONF_DMAC_STEPSIZE_10 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_10 +#ifndef CONF_DMAC_STEPSEL_10 +#define CONF_DMAC_STEPSEL_10 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_10 +#ifndef CONF_DMAC_SRCINC_10 +#define CONF_DMAC_SRCINC_10 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_10 +#ifndef CONF_DMAC_DSTINC_10 +#define CONF_DMAC_DSTINC_10 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_10 +#ifndef CONF_DMAC_BEATSIZE_10 +#define CONF_DMAC_BEATSIZE_10 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_10 +#ifndef CONF_DMAC_BLOCKACT_10 +#define CONF_DMAC_BLOCKACT_10 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_10 +#ifndef CONF_DMAC_EVOSEL_10 +#define CONF_DMAC_EVOSEL_10 0 +#endif +// + +// Channel 11 settings +// dmac_channel_11_settings +#ifndef CONF_DMAC_CHANNEL_11_SETTINGS +#define CONF_DMAC_CHANNEL_11_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 11 is enabled or not +// dmac_enable_11 +#ifndef CONF_DMAC_ENABLE_11 +#define CONF_DMAC_ENABLE_11 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 11 is running in standby mode or not +// dmac_runstdby_11 +#ifndef CONF_DMAC_RUNSTDBY_11 +#define CONF_DMAC_RUNSTDBY_11 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_11 +#ifndef CONF_DMAC_TRIGACT_11 +#define CONF_DMAC_TRIGACT_11 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_11 +#ifndef CONF_DMAC_TRIGSRC_11 +#define CONF_DMAC_TRIGSRC_11 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_11 +#ifndef CONF_DMAC_LVL_11 +#define CONF_DMAC_LVL_11 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_11 +#ifndef CONF_DMAC_EVOE_11 +#define CONF_DMAC_EVOE_11 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_11 +#ifndef CONF_DMAC_EVIE_11 +#define CONF_DMAC_EVIE_11 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_11 +#ifndef CONF_DMAC_EVACT_11 +#define CONF_DMAC_EVACT_11 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_11 +#ifndef CONF_DMAC_STEPSIZE_11 +#define CONF_DMAC_STEPSIZE_11 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_11 +#ifndef CONF_DMAC_STEPSEL_11 +#define CONF_DMAC_STEPSEL_11 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_11 +#ifndef CONF_DMAC_SRCINC_11 +#define CONF_DMAC_SRCINC_11 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_11 +#ifndef CONF_DMAC_DSTINC_11 +#define CONF_DMAC_DSTINC_11 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_11 +#ifndef CONF_DMAC_BEATSIZE_11 +#define CONF_DMAC_BEATSIZE_11 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_11 +#ifndef CONF_DMAC_BLOCKACT_11 +#define CONF_DMAC_BLOCKACT_11 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_11 +#ifndef CONF_DMAC_EVOSEL_11 +#define CONF_DMAC_EVOSEL_11 0 +#endif +// + +// Channel 12 settings +// dmac_channel_12_settings +#ifndef CONF_DMAC_CHANNEL_12_SETTINGS +#define CONF_DMAC_CHANNEL_12_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 12 is enabled or not +// dmac_enable_12 +#ifndef CONF_DMAC_ENABLE_12 +#define CONF_DMAC_ENABLE_12 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 12 is running in standby mode or not +// dmac_runstdby_12 +#ifndef CONF_DMAC_RUNSTDBY_12 +#define CONF_DMAC_RUNSTDBY_12 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_12 +#ifndef CONF_DMAC_TRIGACT_12 +#define CONF_DMAC_TRIGACT_12 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_12 +#ifndef CONF_DMAC_TRIGSRC_12 +#define CONF_DMAC_TRIGSRC_12 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_12 +#ifndef CONF_DMAC_LVL_12 +#define CONF_DMAC_LVL_12 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_12 +#ifndef CONF_DMAC_EVOE_12 +#define CONF_DMAC_EVOE_12 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_12 +#ifndef CONF_DMAC_EVIE_12 +#define CONF_DMAC_EVIE_12 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_12 +#ifndef CONF_DMAC_EVACT_12 +#define CONF_DMAC_EVACT_12 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_12 +#ifndef CONF_DMAC_STEPSIZE_12 +#define CONF_DMAC_STEPSIZE_12 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_12 +#ifndef CONF_DMAC_STEPSEL_12 +#define CONF_DMAC_STEPSEL_12 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_12 +#ifndef CONF_DMAC_SRCINC_12 +#define CONF_DMAC_SRCINC_12 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_12 +#ifndef CONF_DMAC_DSTINC_12 +#define CONF_DMAC_DSTINC_12 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_12 +#ifndef CONF_DMAC_BEATSIZE_12 +#define CONF_DMAC_BEATSIZE_12 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_12 +#ifndef CONF_DMAC_BLOCKACT_12 +#define CONF_DMAC_BLOCKACT_12 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_12 +#ifndef CONF_DMAC_EVOSEL_12 +#define CONF_DMAC_EVOSEL_12 0 +#endif +// + +// Channel 13 settings +// dmac_channel_13_settings +#ifndef CONF_DMAC_CHANNEL_13_SETTINGS +#define CONF_DMAC_CHANNEL_13_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 13 is enabled or not +// dmac_enable_13 +#ifndef CONF_DMAC_ENABLE_13 +#define CONF_DMAC_ENABLE_13 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 13 is running in standby mode or not +// dmac_runstdby_13 +#ifndef CONF_DMAC_RUNSTDBY_13 +#define CONF_DMAC_RUNSTDBY_13 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_13 +#ifndef CONF_DMAC_TRIGACT_13 +#define CONF_DMAC_TRIGACT_13 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_13 +#ifndef CONF_DMAC_TRIGSRC_13 +#define CONF_DMAC_TRIGSRC_13 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_13 +#ifndef CONF_DMAC_LVL_13 +#define CONF_DMAC_LVL_13 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_13 +#ifndef CONF_DMAC_EVOE_13 +#define CONF_DMAC_EVOE_13 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_13 +#ifndef CONF_DMAC_EVIE_13 +#define CONF_DMAC_EVIE_13 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_13 +#ifndef CONF_DMAC_EVACT_13 +#define CONF_DMAC_EVACT_13 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_13 +#ifndef CONF_DMAC_STEPSIZE_13 +#define CONF_DMAC_STEPSIZE_13 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_13 +#ifndef CONF_DMAC_STEPSEL_13 +#define CONF_DMAC_STEPSEL_13 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_13 +#ifndef CONF_DMAC_SRCINC_13 +#define CONF_DMAC_SRCINC_13 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_13 +#ifndef CONF_DMAC_DSTINC_13 +#define CONF_DMAC_DSTINC_13 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_13 +#ifndef CONF_DMAC_BEATSIZE_13 +#define CONF_DMAC_BEATSIZE_13 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_13 +#ifndef CONF_DMAC_BLOCKACT_13 +#define CONF_DMAC_BLOCKACT_13 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_13 +#ifndef CONF_DMAC_EVOSEL_13 +#define CONF_DMAC_EVOSEL_13 0 +#endif +// + +// Channel 14 settings +// dmac_channel_14_settings +#ifndef CONF_DMAC_CHANNEL_14_SETTINGS +#define CONF_DMAC_CHANNEL_14_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 14 is enabled or not +// dmac_enable_14 +#ifndef CONF_DMAC_ENABLE_14 +#define CONF_DMAC_ENABLE_14 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 14 is running in standby mode or not +// dmac_runstdby_14 +#ifndef CONF_DMAC_RUNSTDBY_14 +#define CONF_DMAC_RUNSTDBY_14 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_14 +#ifndef CONF_DMAC_TRIGACT_14 +#define CONF_DMAC_TRIGACT_14 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_14 +#ifndef CONF_DMAC_TRIGSRC_14 +#define CONF_DMAC_TRIGSRC_14 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_14 +#ifndef CONF_DMAC_LVL_14 +#define CONF_DMAC_LVL_14 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_14 +#ifndef CONF_DMAC_EVOE_14 +#define CONF_DMAC_EVOE_14 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_14 +#ifndef CONF_DMAC_EVIE_14 +#define CONF_DMAC_EVIE_14 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_14 +#ifndef CONF_DMAC_EVACT_14 +#define CONF_DMAC_EVACT_14 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_14 +#ifndef CONF_DMAC_STEPSIZE_14 +#define CONF_DMAC_STEPSIZE_14 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_14 +#ifndef CONF_DMAC_STEPSEL_14 +#define CONF_DMAC_STEPSEL_14 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_14 +#ifndef CONF_DMAC_SRCINC_14 +#define CONF_DMAC_SRCINC_14 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_14 +#ifndef CONF_DMAC_DSTINC_14 +#define CONF_DMAC_DSTINC_14 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_14 +#ifndef CONF_DMAC_BEATSIZE_14 +#define CONF_DMAC_BEATSIZE_14 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_14 +#ifndef CONF_DMAC_BLOCKACT_14 +#define CONF_DMAC_BLOCKACT_14 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_14 +#ifndef CONF_DMAC_EVOSEL_14 +#define CONF_DMAC_EVOSEL_14 0 +#endif +// + +// Channel 15 settings +// dmac_channel_15_settings +#ifndef CONF_DMAC_CHANNEL_15_SETTINGS +#define CONF_DMAC_CHANNEL_15_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 15 is enabled or not +// dmac_enable_15 +#ifndef CONF_DMAC_ENABLE_15 +#define CONF_DMAC_ENABLE_15 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 15 is running in standby mode or not +// dmac_runstdby_15 +#ifndef CONF_DMAC_RUNSTDBY_15 +#define CONF_DMAC_RUNSTDBY_15 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_15 +#ifndef CONF_DMAC_TRIGACT_15 +#define CONF_DMAC_TRIGACT_15 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> TCC0 Overflow Trigger +// <0x0C=> TCC0 Match/Compare 0 Trigger +// <0x0D=> TCC0 Match/Compare 1 Trigger +// <0x0E=> TCC0 Match/Compare 2 Trigger +// <0x0F=> TCC0 Match/Compare 3 Trigger +// <0x10=> TCC1 Overflow Trigger +// <0x11=> TCC1 Match/Compare 0 Trigger +// <0x12=> TCC1 Match/Compare 1 Trigger +// <0x13=> TCC2 Overflow Trigger +// <0x14=> TCC2 Match/Compare 0 Trigger +// <0x15=> TCC2 Match/Compare 1 Trigger +// <0x16=> TC0 Overflow Trigger +// <0x17=> TC0 Match/Compare 0 Trigger +// <0x18=> TC0 Match/Compare 1 Trigger +// <0x19=> TC1 Overflow Trigger +// <0x1A=> TC1 Match/Compare 0 Trigger +// <0x1B=> TC1 Match/Compare 1 Trigger +// <0x1C=> TC2 Overflow Trigger +// <0x1D=> TC2 Match/Compare 0 Trigger +// <0x1E=> TC2 Match/Compare 1 Trigger +// <0x1F=> TC3 Overflow Trigger +// <0x20=> TC3 Match/Compare 0 Trigger +// <0x21=> TC3 Match/Compare 1 Trigger +// <0x22=> TC4 Overflow Trigger +// <0x23=> TC4 Match/Compare 0 Trigger +// <0x24=> TC4 Match/Compare 1 Trigger +// <0x25=> ADC Result Ready Trigger +// <0x26=> DAC0 Empty Trigger +// <0x27=> DAC1 Empty Trigger +// <0x2C=> AES Write Trigger +// <0x2D=> AES Read Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_15 +#ifndef CONF_DMAC_TRIGSRC_15 +#define CONF_DMAC_TRIGSRC_15 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_15 +#ifndef CONF_DMAC_LVL_15 +#define CONF_DMAC_LVL_15 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_15 +#ifndef CONF_DMAC_EVOE_15 +#define CONF_DMAC_EVOE_15 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_15 +#ifndef CONF_DMAC_EVIE_15 +#define CONF_DMAC_EVIE_15 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_15 +#ifndef CONF_DMAC_EVACT_15 +#define CONF_DMAC_EVACT_15 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_15 +#ifndef CONF_DMAC_STEPSIZE_15 +#define CONF_DMAC_STEPSIZE_15 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_15 +#ifndef CONF_DMAC_STEPSEL_15 +#define CONF_DMAC_STEPSEL_15 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_15 +#ifndef CONF_DMAC_SRCINC_15 +#define CONF_DMAC_SRCINC_15 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_15 +#ifndef CONF_DMAC_DSTINC_15 +#define CONF_DMAC_DSTINC_15 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_15 +#ifndef CONF_DMAC_BEATSIZE_15 +#define CONF_DMAC_BEATSIZE_15 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_15 +#ifndef CONF_DMAC_BLOCKACT_15 +#define CONF_DMAC_BLOCKACT_15 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_15 +#ifndef CONF_DMAC_EVOSEL_15 +#define CONF_DMAC_EVOSEL_15 0 +#endif +// + +// + +// <<< end of configuration section >>> + +#endif // HPL_DMAC_CONFIG_H diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/Config/hpl_gclk_config.h b/prototype/firmware/I2C_scanner/I2C_scanner/Config/hpl_gclk_config.h new file mode 100644 index 00000000..97b9a036 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/Config/hpl_gclk_config.h @@ -0,0 +1,616 @@ +/* Auto-generated config file hpl_gclk_config.h */ +#ifndef HPL_GCLK_CONFIG_H +#define HPL_GCLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Generic clock generator 0 configuration +// Indicates whether generic clock 0 configuration is enabled or not +// enable_gclk_gen_0 +#ifndef CONF_GCLK_GENERATOR_0_CONFIG +#define CONF_GCLK_GENERATOR_0_CONFIG 1 +#endif + +// Generic Clock Generator Control +// Generic clock generator 0 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 16MHz Internal Oscillator (OSC16M) +// Digital Frequency Locked Loop (DFLL48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 0 +// gclk_gen_0_oscillator +#ifndef CONF_GCLK_GEN_0_SOURCE +#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_OSC16M +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_0_runstdby +#ifndef CONF_GCLK_GEN_0_RUNSTDBY +#define CONF_GCLK_GEN_0_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_0_div_sel +#ifndef CONF_GCLK_GEN_0_DIVSEL +#define CONF_GCLK_GEN_0_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_0_oe +#ifndef CONF_GCLK_GEN_0_OE +#define CONF_GCLK_GEN_0_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_0_oov +#ifndef CONF_GCLK_GEN_0_OOV +#define CONF_GCLK_GEN_0_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_0_idc +#ifndef CONF_GCLK_GEN_0_IDC +#define CONF_GCLK_GEN_0_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_0_enable +#ifndef CONF_GCLK_GEN_0_GENEN +#define CONF_GCLK_GEN_0_GENEN 1 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 0 division <0x0000-0xFFFF> +// gclk_gen_0_div +#ifndef CONF_GCLK_GEN_0_DIV +#define CONF_GCLK_GEN_0_DIV 1 +#endif +// +// + +// Generic clock generator 1 configuration +// Indicates whether generic clock 1 configuration is enabled or not +// enable_gclk_gen_1 +#ifndef CONF_GCLK_GENERATOR_1_CONFIG +#define CONF_GCLK_GENERATOR_1_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 1 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 16MHz Internal Oscillator (OSC16M) +// Digital Frequency Locked Loop (DFLL48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 1 +// gclk_gen_1_oscillator +#ifndef CONF_GCLK_GEN_1_SOURCE +#define CONF_GCLK_GEN_1_SOURCE GCLK_GENCTRL_SRC_XOSC +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_1_runstdby +#ifndef CONF_GCLK_GEN_1_RUNSTDBY +#define CONF_GCLK_GEN_1_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_1_div_sel +#ifndef CONF_GCLK_GEN_1_DIVSEL +#define CONF_GCLK_GEN_1_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_1_oe +#ifndef CONF_GCLK_GEN_1_OE +#define CONF_GCLK_GEN_1_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_1_oov +#ifndef CONF_GCLK_GEN_1_OOV +#define CONF_GCLK_GEN_1_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_1_idc +#ifndef CONF_GCLK_GEN_1_IDC +#define CONF_GCLK_GEN_1_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_1_enable +#ifndef CONF_GCLK_GEN_1_GENEN +#define CONF_GCLK_GEN_1_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 1 division <0x0000-0xFFFF> +// gclk_gen_1_div +#ifndef CONF_GCLK_GEN_1_DIV +#define CONF_GCLK_GEN_1_DIV 1 +#endif +// +// + +// Generic clock generator 2 configuration +// Indicates whether generic clock 2 configuration is enabled or not +// enable_gclk_gen_2 +#ifndef CONF_GCLK_GENERATOR_2_CONFIG +#define CONF_GCLK_GENERATOR_2_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 2 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 16MHz Internal Oscillator (OSC16M) +// Digital Frequency Locked Loop (DFLL48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 2 +// gclk_gen_2_oscillator +#ifndef CONF_GCLK_GEN_2_SOURCE +#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_XOSC +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_2_runstdby +#ifndef CONF_GCLK_GEN_2_RUNSTDBY +#define CONF_GCLK_GEN_2_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_2_div_sel +#ifndef CONF_GCLK_GEN_2_DIVSEL +#define CONF_GCLK_GEN_2_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_2_oe +#ifndef CONF_GCLK_GEN_2_OE +#define CONF_GCLK_GEN_2_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_2_oov +#ifndef CONF_GCLK_GEN_2_OOV +#define CONF_GCLK_GEN_2_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_2_idc +#ifndef CONF_GCLK_GEN_2_IDC +#define CONF_GCLK_GEN_2_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_2_enable +#ifndef CONF_GCLK_GEN_2_GENEN +#define CONF_GCLK_GEN_2_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 2 division <0x0000-0xFFFF> +// gclk_gen_2_div +#ifndef CONF_GCLK_GEN_2_DIV +#define CONF_GCLK_GEN_2_DIV 1 +#endif +// +// + +// Generic clock generator 3 configuration +// Indicates whether generic clock 3 configuration is enabled or not +// enable_gclk_gen_3 +#ifndef CONF_GCLK_GENERATOR_3_CONFIG +#define CONF_GCLK_GENERATOR_3_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 3 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 16MHz Internal Oscillator (OSC16M) +// Digital Frequency Locked Loop (DFLL48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 3 +// gclk_gen_3_oscillator +#ifndef CONF_GCLK_GEN_3_SOURCE +#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_XOSC +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_3_runstdby +#ifndef CONF_GCLK_GEN_3_RUNSTDBY +#define CONF_GCLK_GEN_3_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_3_div_sel +#ifndef CONF_GCLK_GEN_3_DIVSEL +#define CONF_GCLK_GEN_3_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_3_oe +#ifndef CONF_GCLK_GEN_3_OE +#define CONF_GCLK_GEN_3_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_3_oov +#ifndef CONF_GCLK_GEN_3_OOV +#define CONF_GCLK_GEN_3_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_3_idc +#ifndef CONF_GCLK_GEN_3_IDC +#define CONF_GCLK_GEN_3_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_3_enable +#ifndef CONF_GCLK_GEN_3_GENEN +#define CONF_GCLK_GEN_3_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 3 division <0x0000-0xFFFF> +// gclk_gen_3_div +#ifndef CONF_GCLK_GEN_3_DIV +#define CONF_GCLK_GEN_3_DIV 1 +#endif +// +// + +// Generic clock generator 4 configuration +// Indicates whether generic clock 4 configuration is enabled or not +// enable_gclk_gen_4 +#ifndef CONF_GCLK_GENERATOR_4_CONFIG +#define CONF_GCLK_GENERATOR_4_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 4 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 16MHz Internal Oscillator (OSC16M) +// Digital Frequency Locked Loop (DFLL48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 4 +// gclk_gen_4_oscillator +#ifndef CONF_GCLK_GEN_4_SOURCE +#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_XOSC +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_4_runstdby +#ifndef CONF_GCLK_GEN_4_RUNSTDBY +#define CONF_GCLK_GEN_4_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_4_div_sel +#ifndef CONF_GCLK_GEN_4_DIVSEL +#define CONF_GCLK_GEN_4_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_4_oe +#ifndef CONF_GCLK_GEN_4_OE +#define CONF_GCLK_GEN_4_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_4_oov +#ifndef CONF_GCLK_GEN_4_OOV +#define CONF_GCLK_GEN_4_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_4_idc +#ifndef CONF_GCLK_GEN_4_IDC +#define CONF_GCLK_GEN_4_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_4_enable +#ifndef CONF_GCLK_GEN_4_GENEN +#define CONF_GCLK_GEN_4_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 4 division <0x0000-0xFFFF> +// gclk_gen_4_div +#ifndef CONF_GCLK_GEN_4_DIV +#define CONF_GCLK_GEN_4_DIV 1 +#endif +// +// + +// Generic clock generator 5 configuration +// Indicates whether generic clock 5 configuration is enabled or not +// enable_gclk_gen_5 +#ifndef CONF_GCLK_GENERATOR_5_CONFIG +#define CONF_GCLK_GENERATOR_5_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 5 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 16MHz Internal Oscillator (OSC16M) +// Digital Frequency Locked Loop (DFLL48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 5 +// gclk_gen_5_oscillator +#ifndef CONF_GCLK_GEN_5_SOURCE +#define CONF_GCLK_GEN_5_SOURCE GCLK_GENCTRL_SRC_XOSC +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_5_runstdby +#ifndef CONF_GCLK_GEN_5_RUNSTDBY +#define CONF_GCLK_GEN_5_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_5_div_sel +#ifndef CONF_GCLK_GEN_5_DIVSEL +#define CONF_GCLK_GEN_5_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_5_oe +#ifndef CONF_GCLK_GEN_5_OE +#define CONF_GCLK_GEN_5_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_5_oov +#ifndef CONF_GCLK_GEN_5_OOV +#define CONF_GCLK_GEN_5_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_5_idc +#ifndef CONF_GCLK_GEN_5_IDC +#define CONF_GCLK_GEN_5_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_5_enable +#ifndef CONF_GCLK_GEN_5_GENEN +#define CONF_GCLK_GEN_5_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 5 division <0x0000-0xFFFF> +// gclk_gen_5_div +#ifndef CONF_GCLK_GEN_5_DIV +#define CONF_GCLK_GEN_5_DIV 1 +#endif +// +// + +// Generic clock generator 6 configuration +// Indicates whether generic clock 6 configuration is enabled or not +// enable_gclk_gen_6 +#ifndef CONF_GCLK_GENERATOR_6_CONFIG +#define CONF_GCLK_GENERATOR_6_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 6 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 16MHz Internal Oscillator (OSC16M) +// Digital Frequency Locked Loop (DFLL48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 6 +// gclk_gen_6_oscillator +#ifndef CONF_GCLK_GEN_6_SOURCE +#define CONF_GCLK_GEN_6_SOURCE GCLK_GENCTRL_SRC_XOSC +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_6_runstdby +#ifndef CONF_GCLK_GEN_6_RUNSTDBY +#define CONF_GCLK_GEN_6_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_6_div_sel +#ifndef CONF_GCLK_GEN_6_DIVSEL +#define CONF_GCLK_GEN_6_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_6_oe +#ifndef CONF_GCLK_GEN_6_OE +#define CONF_GCLK_GEN_6_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_6_oov +#ifndef CONF_GCLK_GEN_6_OOV +#define CONF_GCLK_GEN_6_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_6_idc +#ifndef CONF_GCLK_GEN_6_IDC +#define CONF_GCLK_GEN_6_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_6_enable +#ifndef CONF_GCLK_GEN_6_GENEN +#define CONF_GCLK_GEN_6_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 6 division <0x0000-0xFFFF> +// gclk_gen_6_div +#ifndef CONF_GCLK_GEN_6_DIV +#define CONF_GCLK_GEN_6_DIV 1 +#endif +// +// + +// Generic clock generator 7 configuration +// Indicates whether generic clock 7 configuration is enabled or not +// enable_gclk_gen_7 +#ifndef CONF_GCLK_GENERATOR_7_CONFIG +#define CONF_GCLK_GENERATOR_7_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 7 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 16MHz Internal Oscillator (OSC16M) +// Digital Frequency Locked Loop (DFLL48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 7 +// gclk_gen_7_oscillator +#ifndef CONF_GCLK_GEN_7_SOURCE +#define CONF_GCLK_GEN_7_SOURCE GCLK_GENCTRL_SRC_XOSC +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_7_runstdby +#ifndef CONF_GCLK_GEN_7_RUNSTDBY +#define CONF_GCLK_GEN_7_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_7_div_sel +#ifndef CONF_GCLK_GEN_7_DIVSEL +#define CONF_GCLK_GEN_7_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_7_oe +#ifndef CONF_GCLK_GEN_7_OE +#define CONF_GCLK_GEN_7_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_7_oov +#ifndef CONF_GCLK_GEN_7_OOV +#define CONF_GCLK_GEN_7_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_7_idc +#ifndef CONF_GCLK_GEN_7_IDC +#define CONF_GCLK_GEN_7_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_7_enable +#ifndef CONF_GCLK_GEN_7_GENEN +#define CONF_GCLK_GEN_7_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 7 division <0x0000-0xFFFF> +// gclk_gen_7_div +#ifndef CONF_GCLK_GEN_7_DIV +#define CONF_GCLK_GEN_7_DIV 1 +#endif +// +// + +// <<< end of configuration section >>> + +#endif // HPL_GCLK_CONFIG_H diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/Config/hpl_mclk_config.h b/prototype/firmware/I2C_scanner/I2C_scanner/Config/hpl_mclk_config.h new file mode 100644 index 00000000..94bf182d --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/Config/hpl_mclk_config.h @@ -0,0 +1,98 @@ +/* Auto-generated config file hpl_mclk_config.h */ +#ifndef HPL_MCLK_CONFIG_H +#define HPL_MCLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include + +// System Configuration +// Indicates whether configuration for system is enabled or not +// enable_cpu_clock +#ifndef CONF_SYSTEM_CONFIG +#define CONF_SYSTEM_CONFIG 1 +#endif + +// Basic settings +// CPU Clock source +// Generic clock generator 0 +// This defines the clock source for the CPU +// cpu_clock_source +#ifndef CONF_CPU_SRC +#define CONF_CPU_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// CPU Clock Division Factor +// 1 +// 2 +// 4 +// 8 +// 16 +// 32 +// 64 +// 128 +// Prescalar for CPU clock +// cpu_div +#ifndef CONF_MCLK_CPUDIV +#define CONF_MCLK_CPUDIV MCLK_CPUDIV_CPUDIV_DIV1_Val +#endif +// Low Power Clock Division +// Divide by 1 +// Divide by 2 +// Divide by 4 +// Divide by 8 +// Divide by 16 +// Divide by 32 +// Divide by 64 +// Divide by 128 +// mclk_arch_lpdiv +#ifndef CONF_MCLK_LPDIV +#define CONF_MCLK_LPDIV MCLK_LPDIV_LPDIV_DIV4_Val +#endif + +// Backup Clock Division +// Divide by 1 +// Divide by 2 +// Divide by 4 +// Divide by 8 +// Divide by 16 +// Divide by 32 +// Divide by 64 +// Divide by 128 +// mclk_arch_bupdiv +#ifndef CONF_MCLK_BUPDIV +#define CONF_MCLK_BUPDIV MCLK_BUPDIV_BUPDIV_DIV8_Val +#endif +// + +// NVM Settings +// NVM Wait States +// These bits select the number of wait states for a read operation. +// <0=> 0 +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +// <10=> 10 +// <11=> 11 +// <12=> 12 +// <13=> 13 +// <14=> 14 +// <15=> 15 +// nvm_wait_states +#ifndef CONF_NVM_WAIT_STATE +#define CONF_NVM_WAIT_STATE 0 +#endif + +// + +// + +// <<< end of configuration section >>> + +#endif // HPL_MCLK_CONFIG_H diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/Config/hpl_osc32kctrl_config.h b/prototype/firmware/I2C_scanner/I2C_scanner/Config/hpl_osc32kctrl_config.h new file mode 100644 index 00000000..897774b9 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/Config/hpl_osc32kctrl_config.h @@ -0,0 +1,208 @@ +/* Auto-generated config file hpl_osc32kctrl_config.h */ +#ifndef HPL_OSC32KCTRL_CONFIG_H +#define HPL_OSC32KCTRL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// RTC Source configuration +// enable_rtc_source +#ifndef CONF_RTCCTRL_CONFIG +#define CONF_RTCCTRL_CONFIG 0 +#endif + +// RTC source control +// RTC Clock Source Selection +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// This defines the clock source for RTC +// rtc_source_oscillator +#ifndef CONF_RTCCTRL_SRC +#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_OSCULP32K +#endif + +// Use 1 kHz output +// rtc_1khz_selection +#ifndef CONF_RTCCTRL_1KHZ + +#define CONF_RTCCTRL_1KHZ 0 + +#endif + +#if CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSCULP32K +#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val) +#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSC32K +#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K_Val) +#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_XOSC32K +#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val) +#else +#error unexpected CONF_RTCCTRL_SRC +#endif + +// +// +// 32kHz External Crystal Oscillator Configuration +// Indicates whether configuration for External 32K Osc is enabled or not +// enable_xosc32k +#ifndef CONF_XOSC32K_CONFIG +#define CONF_XOSC32K_CONFIG 0 +#endif + +// 32kHz External Crystal Oscillator Control +// Oscillator enable +// Indicates whether 32kHz External Crystal Oscillator is enabled or not +// xosc32k_arch_enable +#ifndef CONF_XOSC32K_ENABLE +#define CONF_XOSC32K_ENABLE 0 +#endif + +// Start-Up Time +// <0x0=>62592us +// <0x1=>125092us +// <0x2=>500092us +// <0x3=>1000092us +// <0x4=>2000092us +// <0x5=>4000092us +// <0x6=>8000092us +// xosc32k_arch_startup +#ifndef CONF_XOSC32K_STARTUP +#define CONF_XOSC32K_STARTUP 0x0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// xosc32k_arch_ondemand +#ifndef CONF_XOSC32K_ONDEMAND +#define CONF_XOSC32K_ONDEMAND 1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// xosc32k_arch_runstdby +#ifndef CONF_XOSC32K_RUNSTDBY +#define CONF_XOSC32K_RUNSTDBY 0 +#endif + +// 1kHz Output Enable +// Indicates whether 1kHz Output is enabled or not +// xosc32k_arch_en1k +#ifndef CONF_XOSC32K_EN1K +#define CONF_XOSC32K_EN1K 0 +#endif + +// 32kHz Output Enable +// Indicates whether 32kHz Output is enabled or not +// xosc32k_arch_en32k +#ifndef CONF_XOSC32K_EN32K +#define CONF_XOSC32K_EN32K 0 +#endif + +// Crystal connected to XIN32/XOUT32 Enable +// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not +// xosc32k_arch_xtalen +#ifndef CONF_XOSC32K_XTALEN +#define CONF_XOSC32K_XTALEN 1 +#endif + +// +// +// 32kHz Internal Oscillator Configuration +// Indicates whether configuration for OSC32K is enabled or not +// enable_osc32k +#ifndef CONF_OSC32K_CONFIG +#define CONF_OSC32K_CONFIG 0 +#endif + +// 32kHz Internal Oscillator Control +// Enable +// Indicates whether 32kHz Internal Oscillator is enabled or not +// osc32k_arch_enable +#ifndef CONF_OSC32K_ENABLE +#define CONF_OSC32K_ENABLE 0 +#endif + +// Oscillator Calibration Control +// Indicates whether Oscillator Calibration is enabled or not +// osc32k_arch_calib_enable +#ifndef CONF_OSC32K_CALIB_ENABLE +#define CONF_OSC32K_CALIB_ENABLE 0 +#endif + +// Oscillator Calibration <0x0-0x7F> +// osc32k_arch_calib +#ifndef CONF_OSC32K_CALIB +#define CONF_OSC32K_CALIB 0x0 +#endif + +// Start-Up Time +// <0x0=>92us +// <0x1=>122us +// <0x2=>183us +// <0x3=>305us +// <0x4=>549us +// <0x5=>1038us +// <0x6=>2014us +// <0x7=>3967us +// osc32k_arch_startup +#ifndef CONF_OSC32K_STARTUP +#define CONF_OSC32K_STARTUP 0x0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// osc32k_arch_ondemand +#ifndef CONF_OSC32K_ONDEMAND +#define CONF_OSC32K_ONDEMAND 0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// osc32k_arch_runstdby +#ifndef CONF_OSC32K_RUNSTDBY +#define CONF_OSC32K_RUNSTDBY 0 +#endif + +// 1kHz Output Enable +// Indicates whether 1kHz Output is enabled or not +// osc32k_arch_en1k +#ifndef CONF_OSC32K_EN1K +#define CONF_OSC32K_EN1K 0 +#endif + +// 32kHz Output Enable +// Indicates whether 32kHz Output is enabled or not +// osc32k_arch_en32k +#ifndef CONF_OSC32K_EN32K +#define CONF_OSC32K_EN32K 0 +#endif +// +// + +// 32kHz Ultra Low Power Internal Oscillator Configuration +// Indicates whether configuration for OSCULP32K is enabled or not +// enable_osculp32k +#ifndef CONF_OSCULP32K_CONFIG +#define CONF_OSCULP32K_CONFIG 1 +#endif + +// 32kHz Ultra Low Power Internal Oscillator Control + +// Oscillator Calibration Control +// Indicates whether Oscillator Calibration is enabled or not +// osculp32k_calib_enable +#ifndef CONF_OSCULP32K_CALIB_ENABLE +#define CONF_OSCULP32K_CALIB_ENABLE 0 +#endif + +// Oscillator Calibration <0x0-0x1F> +// osculp32k_calib +#ifndef CONF_OSCULP32K_CALIB +#define CONF_OSCULP32K_CALIB 0x0 +#endif + +// +// + +// <<< end of configuration section >>> + +#endif // HPL_OSC32KCTRL_CONFIG_H diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/Config/hpl_oscctrl_config.h b/prototype/firmware/I2C_scanner/I2C_scanner/Config/hpl_oscctrl_config.h new file mode 100644 index 00000000..45fbd040 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/Config/hpl_oscctrl_config.h @@ -0,0 +1,462 @@ +/* Auto-generated config file hpl_oscctrl_config.h */ +#ifndef HPL_OSCCTRL_CONFIG_H +#define HPL_OSCCTRL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// External Multipurpose Crystal Oscillator Configuration +// Indicates whether configuration for XOSC is enabled or not +// enable_xosc +#ifndef CONF_XOSC_CONFIG +#define CONF_XOSC_CONFIG 0 +#endif + +// Frequency <400000-32000000> +// Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator. +// xosc_frequency +#ifndef CONF_XOSC_FREQUENCY +#define CONF_XOSC_FREQUENCY 400000 +#endif + +// External Multipurpose Crystal Oscillator Control +// Oscillator enable +// Indicates whether External Multipurpose Crystal Oscillator is enabled or not +// xosc_arch_enable +#ifndef CONF_XOSC_ENABLE +#define CONF_XOSC_ENABLE 0 +#endif + +// Start-Up Time +// <0x0=>31us +// <0x1=>61us +// <0x2=>122us +// <0x3=>244us +// <0x4=>488us +// <0x5=>977us +// <0x6=>1953us +// <0x7=>3906us +// <0x8=>7813us +// <0x9=>15625us +// <0xA=>31250us +// <0xB=>62500us +// <0xC=>125000us +// <0xD=>250000us +// <0xE=>500000us +// <0xF=>1000000us +// xosc_arch_startup +#ifndef CONF_XOSC_STARTUP +#define CONF_XOSC_STARTUP 0x0 +#endif + +// Automatic Amplitude Gain Control +// Indicates whether Automatic Amplitude Gain Control is enabled or not +// xosc_arch_ampgc +#ifndef CONF_XOSC_AMPGC +#define CONF_XOSC_AMPGC 0 +#endif + +// External Multipurpose Crystal Oscillator Gain +// <0x0=>2MHz +// <0x1=>4MHz +// <0x2=>8MHz +// <0x3=>16MHz +// <0x4=>30MHz +// xosc_arch_gain +#ifndef CONF_XOSC_GAIN +#define CONF_XOSC_GAIN 0x0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// xosc_arch_ondemand +#ifndef CONF_XOSC_ONDEMAND +#define CONF_XOSC_ONDEMAND 1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// xosc_arch_runstdby +#ifndef CONF_XOSC_RUNSTDBY +#define CONF_XOSC_RUNSTDBY 0 +#endif + +// Crystal connected to XIN/XOUT Enable +// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not +// xosc_arch_xtalen +#ifndef CONF_XOSC_XTALEN +#define CONF_XOSC_XTALEN 0 +#endif +// +// + +// 16MHz Internal Oscillator Configuration +// Indicates whether configuration for OSC8M is enabled or not +// enable_osc16m +#ifndef CONF_OSC16M_CONFIG +#define CONF_OSC16M_CONFIG 1 +#endif + +// 16MHz Internal Oscillator Control +// Enable +// Indicates whether 16MHz Internal Oscillator is enabled or not +// osc16m_arch_enable +#ifndef CONF_OSC16M_ENABLE +#define CONF_OSC16M_ENABLE 1 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// osc16m_arch_ondemand +#ifndef CONF_OSC16M_ONDEMAND +#define CONF_OSC16M_ONDEMAND 1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// osc16m_arch_runstdby +#ifndef CONF_OSC16M_RUNSTDBY +#define CONF_OSC16M_RUNSTDBY 0 +#endif + +// Oscillator Frequency Selection(Mhz) +// 4 +// 8 +// 12 +// 16 +// This defines the oscillator frequency (Mhz) +// osc16m_freq +#ifndef CONF_OSC16M_FSEL +#define CONF_OSC16M_FSEL OSCCTRL_OSC16MCTRL_FSEL_16_Val +#endif + +// Oscillator Calibration Control +// Indicates whether Oscillator Calibration is enabled or not +// osc16m_arch_calib_enable +#ifndef CONF_OSC16M_CALIB_ENABLE +#define CONF_OSC16M_CALIB_ENABLE 0 +#endif + +// 4MHz Frequency Calibration <0x0-0x3F> +// osc16m_arch_4m_fcal +#ifndef CONF_OSC16M_FCAL +#define CONF_OSC16M_4M_FCAL 0 +#endif + +// 4MHz Temperature Calibration <0x0-0x3F> +// osc16m_arch_4m_tcal +#ifndef CONF_OSC16M_TCAL +#define CONF_OSC16M_4M_TCAL 0 +#endif + +// 8MHz Frequency Calibration <0x0-0x3F> +// osc16m_arch_8m_fcal +#ifndef CONF_OSC16M_FCAL +#define CONF_OSC16M_8M_FCAL 0 +#endif + +// 8MHz Temperature Calibration <0x0-0x3F> +// osc16m_arch_8m_tcal +#ifndef CONF_OSC16M_TCAL +#define CONF_OSC16M_8M_TCAL 0 +#endif + +// 12MHz Frequency Calibration <0x0-0x3F> +// osc16m_arch_12m_fcal +#ifndef CONF_OSC16M_FCAL +#define CONF_OSC16M_12M_FCAL 0 +#endif + +// 12MHz Temperature Calibration <0x0-0x3F> +// osc16m_arch_12m_tcal +#ifndef CONF_OSC16M_TCAL +#define CONF_OSC16M_12M_TCAL 0 +#endif + +// 16MHz Frequency Calibration <0x0-0x3F> +// osc16m_arch_fcal +#ifndef CONF_OSC16M_FCAL +#define CONF_OSC16M_16M_FCAL 0 +#endif + +// 16MHz Temperature Calibration <0x0-0x3F> +// osc16m_arch_16m_tcal +#ifndef CONF_OSC16M_TCAL +#define CONF_OSC16M_16M_TCAL 0 +#endif +// +// + +// DFLL Configuration +// Indicates whether configuration for DFLL is enabled or not +// enable_dfll48m +#ifndef CONF_DFLL_CONFIG +#define CONF_DFLL_CONFIG 0 +#endif + +// Reference Clock Source +// Generic clock generator 0 +// Generic clock generator 1 +// Generic clock generator 2 +// Generic clock generator 3 +// Generic clock generator 4 +// Generic clock generator 5 +// Generic clock generator 6 +// Generic clock generator 7 +// Select the clock source. +// dfll48m_ref_clock +#ifndef CONF_DFLL_GCLK +#define CONF_DFLL_GCLK GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +// Digital Frequency Locked Loop Control +// DFLL Enable +// Indicates whether DFLL is enabled or not +// dfll48m_arch_enable +#ifndef CONF_DFLL_ENABLE +#define CONF_DFLL_ENABLE 0 +#endif + +// Wait Lock +// Indicates whether Wait Lock is enabled or not +// dfll_arch_waitlock +#ifndef CONF_DFLL_WAITLOCK +#define CONF_DFLL_WAITLOCK 0 +#endif + +// Bypass Coarse Lock +// Indicates whether Bypass Coarse Lock is enabled or not +// dfll_arch_bplckc +#ifndef CONF_DFLL_BPLCKC +#define CONF_DFLL_BPLCKC 0 +#endif + +// Quick Lock Disable +// Indicates whether Quick Lock Disable is enabled or not +// dfll_arch_qldis +#ifndef CONF_DFLL_QLDIS +#define CONF_DFLL_QLDIS 0 +#endif + +// Chill Cycle Disable +// Indicates whether Chill Cycle Disable is enabled or not +// dfll_arch_ccdis +#ifndef CONF_DFLL_CCDIS +#define CONF_DFLL_CCDIS 0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// dfll_arch_ondemand +#ifndef CONF_DFLL_ONDEMAND +#define CONF_DFLL_ONDEMAND 1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// dfll_arch_runstdby +#ifndef CONF_DFLL_RUNSTDBY +#define CONF_DFLL_RUNSTDBY 0 +#endif + +// USB Clock Recovery Mode +// Indicates whether USB Clock Recovery Mode is enabled or not +// dfll_arch_usbcrm +#ifndef CONF_DFLL_USBCRM +#define CONF_DFLL_USBCRM 0 +#endif + +// Lose Lock After Wake +// Indicates whether Lose Lock After Wake is enabled or not +// dfll_arch_llaw +#ifndef CONF_DFLL_LLAW +#define CONF_DFLL_LLAW 0 +#endif + +// Stable DFLL Frequency +// Indicates whether Stable DFLL Frequency is enabled or not +// dfll_arch_stable +#ifndef CONF_DFLL_STABLE +#define CONF_DFLL_STABLE 0 +#endif + +// Operating Mode Selection +// <0=>Open Loop Mode +// <1=>Closed Loop Mode +// dfll48m_mode +#ifndef CONF_DFLL_MODE +#define CONF_DFLL_MODE 0 +#endif + +// Coarse Maximum Step <0x0-0x1F> +// dfll_arch_cstep +#ifndef CONF_DFLL_CSTEP +#define CONF_DFLL_CSTEP 1 +#endif + +// Fine Maximum Step <0x0-0x3FF> +// dfll_arch_fstep +#ifndef CONF_DFLL_FSTEP +#define CONF_DFLL_FSTEP 1 +#endif + +// DFLL Multiply Factor <0x0-0xFFFF> +// dfll48m_mul +#ifndef CONF_DFLL_MUL +#define CONF_DFLL_MUL 0 +#endif + +// DFLL Calibration Overwrite +// Indicates whether Overwrite Calibration value of DFLL +// dfll_arch_calibration +#ifndef CONF_DFLL_OVERWRITE_CALIBRATION +#define CONF_DFLL_OVERWRITE_CALIBRATION 0 +#endif + +// Coarse Value <0x0-0x3F> +// dfll_arch_coarse +#ifndef CONF_DFLL_COARSE +#define CONF_DFLL_COARSE (0x1f / 4) +#endif + +// Fine Value <0x0-0x3FF> +// dfll_arch_fine +#ifndef CONF_DFLL_FINE +#define CONF_DFLL_FINE (0x200) +#endif + +// + +// + +// + +// DPLL Configuration +// Indicates whether configuration for DPLL is enabled or not +// enable_fdpll96m +#ifndef CONF_DPLL_CONFIG +#define CONF_DPLL_CONFIG 0 +#endif + +// Reference Clock Source +// 32kHz External Crystal Oscillator (XOSC32K) +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator 0 +// Generic clock generator 1 +// Generic clock generator 2 +// Generic clock generator 3 +// Generic clock generator 4 +// Generic clock generator 5 +// Generic clock generator 6 +// Generic clock generator 7 +// Select the clock source. +// fdpll96m_ref_clock +#ifndef CONF_DPLL_GCLK +#define CONF_DPLL_GCLK GCLK_GENCTRL_SRC_XOSC32K + +#endif + +// Digital Phase Locked Loop Control +// Enable +// Indicates whether Digital Phase Locked Loop is enabled or not +// fdpll96m_arch_enable +#ifndef CONF_DPLL_ENABLE +#define CONF_DPLL_ENABLE 0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// fdpll96m_arch_ondemand +#ifndef CONF_DPLL_ONDEMAND +#define CONF_DPLL_ONDEMAND 1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// fdpll96m_arch_runstdby +#ifndef CONF_DPLL_RUNSTDBY +#define CONF_DPLL_RUNSTDBY 0 +#endif + +// Loop Divider Ratio Fractional Part <0x0-0xF> +// fdpll96m_ldrfrac +#ifndef CONF_DPLL_LDRFRAC +#define CONF_DPLL_LDRFRAC 0xd +#endif + +// Loop Divider Ratio Integer Part <0x0-0xFFF> +// fdpll96m_ldr +#ifndef CONF_DPLL_LDR +#define CONF_DPLL_LDR 0x5b7 +#endif + +// Clock Divider <0x0-0x3FF> +// fdpll96m_clock_div +#ifndef CONF_DPLL_DIV +#define CONF_DPLL_DIV 0 +#endif + +// Lock Bypass +// Indicates whether Lock Bypass is enabled or not +// fdpll96m_arch_lbypass +#ifndef CONF_DPLL_LBYPASS +#define CONF_DPLL_LBYPASS 0 +#endif + +// Lock Time +// <0=>No time-out, automatic lock +// <4=>The Time-out if no lock within 8 ms +// <5=>The Time-out if no lock within 9 ms +// <6=>The Time-out if no lock within 10 ms +// <7=>The Time-out if no lock within 11 ms +// fdpll96m_arch_ltime +#ifndef CONF_DPLL_LTIME +#define CONF_DPLL_LTIME 0 +#endif + +// Reference Clock Selection +// <0=>XOSC32K clock reference +// <1=>XOSC clock reference +// <2=>GCLK clock reference +// fdpll96m_arch_refclk +#ifndef CONF_DPLL_REFCLK +#define CONF_DPLL_REFCLK 0 +#endif + +// Wake Up Fast +// Indicates whether Wake Up Fast is enabled or not +// fdpll96m_arch_wuf +#ifndef CONF_DPLL_WUF +#define CONF_DPLL_WUF 0 +#endif + +// Low-Power Enable +// Indicates whether Low-Power Enable is enabled or not +// fdpll96m_arch_lpen +#ifndef CONF_DPLL_LPEN +#define CONF_DPLL_LPEN 0 +#endif + +// Reference Clock Selection +// <0=>Default filter mode +// <1=>Low bandwidth filter +// <2=>High bandwidth filter +// <3=>High damping filter +// fdpll96m_arch_filter +#ifndef CONF_DPLL_FILTER +#define CONF_DPLL_FILTER 0 +#endif + +// Output Clock Prescaler +// 1 +// 2 +// 4 +// fdpll96m_presc +#ifndef CONF_DPLL_PRESC +#define CONF_DPLL_PRESC OSCCTRL_DPLLPRESC_PRESC_DIV1_Val +#endif +// +// + +// <<< end of configuration section >>> + +#endif // HPL_OSCCTRL_CONFIG_H diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/Config/hpl_port_config.h b/prototype/firmware/I2C_scanner/I2C_scanner/Config/hpl_port_config.h new file mode 100644 index 00000000..1efce33e --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/Config/hpl_port_config.h @@ -0,0 +1,284 @@ +/* Auto-generated config file hpl_port_config.h */ +#ifndef HPL_PORT_CONFIG_H +#define HPL_PORT_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// PORT Input Event 0 configuration +// enable_port_input_event_0 +#ifndef CONF_PORT_EVCTRL_PORT_0 +#define CONF_PORT_EVCTRL_PORT_0 0 +#endif + +// PORT Input Event 0 configuration on PORT A + +// PORTA Input Event 0 Enable +// The event action will be triggered on any incoming event if PORT A Input Event 0 configuration is enabled +// porta_input_event_enable_0 +#ifndef CONF_PORTA_EVCTRL_PORTEI_0 +#define CONF_PORTA_EVCTRL_PORTEI_0 0x0 +#endif + +// PORTA Event 0 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port A on which the event action will be performed +// porta_event_pin_identifier_0 +#ifndef CONF_PORTA_EVCTRL_PID_0 +#define CONF_PORTA_EVCTRL_PID_0 0x0 +#endif + +// PORTA Event 0 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT A will perform on event input 0 +// porta_event_action_0 +#ifndef CONF_PORTA_EVCTRL_EVACT_0 +#define CONF_PORTA_EVCTRL_EVACT_0 0 +#endif + +// +// PORT Input Event 0 configuration on PORT B + +// PORTB Input Event 0 Enable +// The event action will be triggered on any incoming event if PORT B Input Event 0 configuration is enabled +// portb_input_event_enable_0 +#ifndef CONF_PORTB_EVCTRL_PORTEI_0 +#define CONF_PORTB_EVCTRL_PORTEI_0 0x0 +#endif + +// PORTB Event 0 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port B on which the event action will be performed +// portb_event_pin_identifier_0 +#ifndef CONF_PORTB_EVCTRL_PID_0 +#define CONF_PORTB_EVCTRL_PID_0 0x0 +#endif + +// PORTB Event 0 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT B will perform on event input 0 +// portb_event_action_0 +#ifndef CONF_PORTB_EVCTRL_EVACT_0 +#define CONF_PORTB_EVCTRL_EVACT_0 0 +#endif + +// + +// + +// PORT Input Event 1 configuration +// enable_port_input_event_1 +#ifndef CONF_PORT_EVCTRL_PORT_1 +#define CONF_PORT_EVCTRL_PORT_1 0 +#endif + +// PORT Input Event 1 configuration on PORT A + +// PORTA Input Event 1 Enable +// The event action will be triggered on any incoming event if PORT A Input Event 1 configuration is enabled +// porta_input_event_enable_1 +#ifndef CONF_PORTA_EVCTRL_PORTEI_1 +#define CONF_PORTA_EVCTRL_PORTEI_1 0x0 +#endif + +// PORTA Event 1 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port A on which the event action will be performed +// porta_event_pin_identifier_1 +#ifndef CONF_PORTA_EVCTRL_PID_1 +#define CONF_PORTA_EVCTRL_PID_1 0x0 +#endif + +// PORTA Event 1 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT A will perform on event input 1 +// porta_event_action_1 +#ifndef CONF_PORTA_EVCTRL_EVACT_1 +#define CONF_PORTA_EVCTRL_EVACT_1 0 +#endif + +// +// PORT Input Event 1 configuration on PORT B + +// PORTB Input Event 1 Enable +// The event action will be triggered on any incoming event if PORT B Input Event 1 configuration is enabled +// portb_input_event_enable_1 +#ifndef CONF_PORTB_EVCTRL_PORTEI_1 +#define CONF_PORTB_EVCTRL_PORTEI_1 0x0 +#endif + +// PORTB Event 1 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port B on which the event action will be performed +// portb_event_pin_identifier_1 +#ifndef CONF_PORTB_EVCTRL_PID_1 +#define CONF_PORTB_EVCTRL_PID_1 0x0 +#endif + +// PORTB Event 1 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT B will perform on event input 1 +// portb_event_action_1 +#ifndef CONF_PORTB_EVCTRL_EVACT_1 +#define CONF_PORTB_EVCTRL_EVACT_1 0 +#endif + +// + +// + +// PORT Input Event 2 configuration +// enable_port_input_event_2 +#ifndef CONF_PORT_EVCTRL_PORT_2 +#define CONF_PORT_EVCTRL_PORT_2 0 +#endif + +// PORT Input Event 2 configuration on PORT A + +// PORTA Input Event 2 Enable +// The event action will be triggered on any incoming event if PORT A Input Event 2 configuration is enabled +// porta_input_event_enable_2 +#ifndef CONF_PORTA_EVCTRL_PORTEI_2 +#define CONF_PORTA_EVCTRL_PORTEI_2 0x0 +#endif + +// PORTA Event 2 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port A on which the event action will be performed +// porta_event_pin_identifier_2 +#ifndef CONF_PORTA_EVCTRL_PID_2 +#define CONF_PORTA_EVCTRL_PID_2 0x0 +#endif + +// PORTA Event 2 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT A will perform on event input 2 +// porta_event_action_2 +#ifndef CONF_PORTA_EVCTRL_EVACT_2 +#define CONF_PORTA_EVCTRL_EVACT_2 0 +#endif + +// +// PORT Input Event 2 configuration on PORT B + +// PORTB Input Event 2 Enable +// The event action will be triggered on any incoming event if PORT B Input Event 2 configuration is enabled +// portb_input_event_enable_2 +#ifndef CONF_PORTB_EVCTRL_PORTEI_2 +#define CONF_PORTB_EVCTRL_PORTEI_2 0x0 +#endif + +// PORTB Event 2 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port B on which the event action will be performed +// portb_event_pin_identifier_2 +#ifndef CONF_PORTB_EVCTRL_PID_2 +#define CONF_PORTB_EVCTRL_PID_2 0x0 +#endif + +// PORTB Event 2 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT B will perform on event input 2 +// portb_event_action_2 +#ifndef CONF_PORTB_EVCTRL_EVACT_2 +#define CONF_PORTB_EVCTRL_EVACT_2 0 +#endif + +// + +// + +// PORT Input Event 3 configuration +// enable_port_input_event_3 +#ifndef CONF_PORT_EVCTRL_PORT_3 +#define CONF_PORT_EVCTRL_PORT_3 0 +#endif + +// PORT Input Event 3 configuration on PORT A + +// PORTA Input Event 3 Enable +// The event action will be triggered on any incoming event if PORT A Input Event 3 configuration is enabled +// porta_input_event_enable_3 +#ifndef CONF_PORTA_EVCTRL_PORTEI_3 +#define CONF_PORTA_EVCTRL_PORTEI_3 0x0 +#endif + +// PORTA Event 3 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port A on which the event action will be performed +// porta_event_pin_identifier_3 +#ifndef CONF_PORTA_EVCTRL_PID_3 +#define CONF_PORTA_EVCTRL_PID_3 0x0 +#endif + +// PORTA Event 3 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT A will perform on event input 3 +// porta_event_action_3 +#ifndef CONF_PORTA_EVCTRL_EVACT_3 +#define CONF_PORTA_EVCTRL_EVACT_3 0 +#endif + +// +// PORT Input Event 3 configuration on PORT B + +// PORTB Input Event 3 Enable +// The event action will be triggered on any incoming event if PORT B Input Event 3 configuration is enabled +// portb_input_event_enable_3 +#ifndef CONF_PORTB_EVCTRL_PORTEI_3 +#define CONF_PORTB_EVCTRL_PORTEI_3 0x0 +#endif + +// PORTB Event 3 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port B on which the event action will be performed +// portb_event_pin_identifier_3 +#ifndef CONF_PORTB_EVCTRL_PID_3 +#define CONF_PORTB_EVCTRL_PID_3 0x0 +#endif + +// PORTB Event 3 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT B will perform on event input 3 +// portb_event_action_3 +#ifndef CONF_PORTB_EVCTRL_EVACT_3 +#define CONF_PORTB_EVCTRL_EVACT_3 0 +#endif + +// + +// + +#define CONF_PORTA_EVCTRL \ + (0 | PORT_EVCTRL_EVACT0(CONF_PORTA_EVCTRL_EVACT_0) | CONF_PORTA_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ + | PORT_EVCTRL_PID0(CONF_PORTA_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTA_EVCTRL_EVACT_1) \ + | CONF_PORTA_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTA_EVCTRL_PID_1) \ + | PORT_EVCTRL_EVACT2(CONF_PORTA_EVCTRL_EVACT_2) | CONF_PORTA_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ + | PORT_EVCTRL_PID2(CONF_PORTA_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTA_EVCTRL_EVACT_3) \ + | CONF_PORTA_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTA_EVCTRL_PID_3)) +#define CONF_PORTB_EVCTRL \ + (0 | PORT_EVCTRL_EVACT0(CONF_PORTB_EVCTRL_EVACT_0) | CONF_PORTB_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ + | PORT_EVCTRL_PID0(CONF_PORTB_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTB_EVCTRL_EVACT_1) \ + | CONF_PORTB_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTB_EVCTRL_PID_1) \ + | PORT_EVCTRL_EVACT2(CONF_PORTB_EVCTRL_EVACT_2) | CONF_PORTB_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ + | PORT_EVCTRL_PID2(CONF_PORTB_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTB_EVCTRL_EVACT_3) \ + | CONF_PORTB_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTB_EVCTRL_PID_3)) + +// <<< end of configuration section >>> + +#endif // HPL_PORT_CONFIG_H diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/Config/hpl_sercom_config.h b/prototype/firmware/I2C_scanner/I2C_scanner/Config/hpl_sercom_config.h new file mode 100644 index 00000000..1c5e8b91 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/Config/hpl_sercom_config.h @@ -0,0 +1,394 @@ +/* Auto-generated config file hpl_sercom_config.h */ +#ifndef HPL_SERCOM_CONFIG_H +#define HPL_SERCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include + +#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER +#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2) +#endif + +#ifndef CONF_SERCOM_0_I2CM_ENABLE +#define CONF_SERCOM_0_I2CM_ENABLE 1 +#endif + +// Basic + +// I2C Bus clock speed (Hz) <1-400000> +// I2C Bus clock (SCL) speed measured in Hz +// i2c_master_baud_rate +#ifndef CONF_SERCOM_0_I2CM_BAUD +#define CONF_SERCOM_0_I2CM_BAUD 100000 +#endif + +// + +// Advanced +// i2c_master_advanced +#ifndef CONF_SERCOM_0_I2CM_ADVANCED_CONFIG +#define CONF_SERCOM_0_I2CM_ADVANCED_CONFIG 0 +#endif + +// TRise (ns) <0-300> +// Determined by the bus impedance, check electric characteristics in the datasheet +// Standard Fast Mode: typical 215ns, max 300ns +// Fast Mode +: typical 60ns, max 100ns +// High Speed Mode: typical 20ns, max 40ns +// i2c_master_arch_trise + +#ifndef CONF_SERCOM_0_I2CM_TRISE +#define CONF_SERCOM_0_I2CM_TRISE 215 +#endif + +// Master SCL Low Extended Time-Out (MEXTTOEN) +// This enables the master SCL low extend time-out +// i2c_master_arch_mexttoen +#ifndef CONF_SERCOM_0_I2CM_MEXTTOEN +#define CONF_SERCOM_0_I2CM_MEXTTOEN 0 +#endif + +// Slave SCL Low Extend Time-Out (SEXTTOEN) +// Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine +// i2c_master_arch_sexttoen +#ifndef CONF_SERCOM_0_I2CM_SEXTTOEN +#define CONF_SERCOM_0_I2CM_SEXTTOEN 0 +#endif + +// SCL Low Time-Out (LOWTOUT) +// Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold +// i2c_master_arch_lowtout +#ifndef CONF_SERCOM_0_I2CM_LOWTOUT +#define CONF_SERCOM_0_I2CM_LOWTOUT 0 +#endif + +// Inactive Time-Out (INACTOUT) +// <0x0=>Disabled +// <0x1=>5-6 SCL cycle time-out(50-60us) +// <0x2=>10-11 SCL cycle time-out(100-110us) +// <0x3=>20-21 SCL cycle time-out(200-210us) +// Defines if inactivity time-out should be enabled, and how long the time-out should be +// i2c_master_arch_inactout +#ifndef CONF_SERCOM_0_I2CM_INACTOUT +#define CONF_SERCOM_0_I2CM_INACTOUT 0x0 +#endif + +// SDA Hold Time (SDAHOLD) +// <0=>Disabled +// <1=>50-100ns hold time +// <2=>300-600ns hold time +// <3=>400-800ns hold time +// Defines the SDA hold time with respect to the negative edge of SCL +// i2c_master_arch_sdahold +#ifndef CONF_SERCOM_0_I2CM_SDAHOLD +#define CONF_SERCOM_0_I2CM_SDAHOLD 0x2 +#endif + +// Run in stand-by +// Determine if the module shall run in standby sleep mode +// i2c_master_arch_runstdby +#ifndef CONF_SERCOM_0_I2CM_RUNSTDBY +#define CONF_SERCOM_0_I2CM_RUNSTDBY 0 +#endif + +// Debug Stop Mode +// Behavior of the baud-rate generator when CPU is halted by external debugger. +// <0=>Keep running +// <1=>Halt +// i2c_master_arch_dbgstop +#ifndef CONF_SERCOM_0_I2CM_DEBUG_STOP_MODE +#define CONF_SERCOM_0_I2CM_DEBUG_STOP_MODE 0 +#endif + +// + +#ifndef CONF_SERCOM_0_I2CM_SPEED +#define CONF_SERCOM_0_I2CM_SPEED 0x00 // Speed: Standard/Fast mode +#endif +#if CONF_SERCOM_0_I2CM_TRISE < 215 || CONF_SERCOM_0_I2CM_TRISE > 300 +#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns +#undef CONF_SERCOM_0_I2CM_TRISE +#define CONF_SERCOM_0_I2CM_TRISE 215U +#endif + +// gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise) +// BAUD + BAUDLOW = -------------------------------------------------------------------- +// i2c_scl_freq +// BAUD: register value low [7:0] +// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW +#define CONF_SERCOM_0_I2CM_BAUD_BAUDLOW \ + (((CONF_GCLK_SERCOM0_CORE_FREQUENCY - (CONF_SERCOM_0_I2CM_BAUD * 10U) \ + - (CONF_SERCOM_0_I2CM_TRISE * (CONF_SERCOM_0_I2CM_BAUD / 100U) * (CONF_GCLK_SERCOM0_CORE_FREQUENCY / 10000U) \ + / 1000U)) \ + * 10U \ + + 5U) \ + / (CONF_SERCOM_0_I2CM_BAUD * 10U)) +#ifndef CONF_SERCOM_0_I2CM_BAUD_RATE +#if CONF_SERCOM_0_I2CM_BAUD_BAUDLOW > (0xFF * 2) +#warning Requested I2C baudrate too low, please check +#define CONF_SERCOM_0_I2CM_BAUD_RATE 0xFF +#elif CONF_SERCOM_0_I2CM_BAUD_BAUDLOW <= 1 +#warning Requested I2C baudrate too high, please check +#define CONF_SERCOM_0_I2CM_BAUD_RATE 1 +#else +#define CONF_SERCOM_0_I2CM_BAUD_RATE \ + ((CONF_SERCOM_0_I2CM_BAUD_BAUDLOW & 0x1) \ + ? (CONF_SERCOM_0_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_0_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \ + : (CONF_SERCOM_0_I2CM_BAUD_BAUDLOW / 2)) +#endif +#endif + +#include + +#ifndef CONF_SERCOM_3_USART_ENABLE +#define CONF_SERCOM_3_USART_ENABLE 1 +#endif + +// Basic Configuration + +// Receive buffer enable +// Enable input buffer in SERCOM module +// usart_rx_enable +#ifndef CONF_SERCOM_3_USART_RXEN +#define CONF_SERCOM_3_USART_RXEN 1 +#endif + +// Transmitt buffer enable +// Enable output buffer in SERCOM module +// usart_tx_enable +#ifndef CONF_SERCOM_3_USART_TXEN +#define CONF_SERCOM_3_USART_TXEN 1 +#endif + +// Frame parity +// <0x0=>No parity +// <0x1=>Even parity +// <0x2=>Odd parity +// Parity bit mode for USART frame +// usart_parity +#ifndef CONF_SERCOM_3_USART_PARITY +#define CONF_SERCOM_3_USART_PARITY 0x0 +#endif + +// Character Size +// <0x0=>8 bits +// <0x1=>9 bits +// <0x5=>5 bits +// <0x6=>6 bits +// <0x7=>7 bits +// Data character size in USART frame +// usart_character_size +#ifndef CONF_SERCOM_3_USART_CHSIZE +#define CONF_SERCOM_3_USART_CHSIZE 0x0 +#endif + +// Stop Bit +// <0=>One stop bit +// <1=>Two stop bits +// Number of stop bits in USART frame +// usart_stop_bit +#ifndef CONF_SERCOM_3_USART_SBMODE +#define CONF_SERCOM_3_USART_SBMODE 0 +#endif + +// Baud rate <1-3000000> +// USART baud rate setting +// usart_baud_rate +#ifndef CONF_SERCOM_3_USART_BAUD +#define CONF_SERCOM_3_USART_BAUD 9600 +#endif + +// + +// Advanced configuration +// usart_advanced +#ifndef CONF_SERCOM_3_USART_ADVANCED_CONFIG +#define CONF_SERCOM_3_USART_ADVANCED_CONFIG 0 +#endif + +// Run in stand-by +// Keep the module running in standby sleep mode +// usart_arch_runstdby +#ifndef CONF_SERCOM_3_USART_RUNSTDBY +#define CONF_SERCOM_3_USART_RUNSTDBY 0 +#endif + +// Immediate Buffer Overflow Notification +// Controls when the BUFOVF status bit is asserted +// usart_arch_ibon +#ifndef CONF_SERCOM_3_USART_IBON +#define CONF_SERCOM_3_USART_IBON 0 +#endif + +// Start of Frame Detection Enable +// Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled) +// usart_arch_sfde +#ifndef CONF_SERCOM_3_USART_SFDE +#define CONF_SERCOM_3_USART_SFDE 0 +#endif + +// Collision Detection Enable +// Collision detection enable +// usart_arch_cloden +#ifndef CONF_SERCOM_3_USART_CLODEN +#define CONF_SERCOM_3_USART_CLODEN 0 +#endif + +// Operating Mode +// <0x0=>USART with external clock +// <0x1=>USART with internal clock +// Drive the shift register by an internal clock generated by the baud rate generator or an external clock supplied on the XCK pin. +// usart_arch_clock_mode +#ifndef CONF_SERCOM_3_USART_MODE +#define CONF_SERCOM_3_USART_MODE 0x1 +#endif + +// Sample Rate +// <0x0=>16x arithmetic +// <0x1=>16x fractional +// <0x2=>8x arithmetic +// <0x3=>8x fractional +// <0x4=>3x arithmetic +// How many over-sampling bits used when sampling data state +// usart_arch_sampr +#ifndef CONF_SERCOM_3_USART_SAMPR +#define CONF_SERCOM_3_USART_SAMPR 0x0 +#endif + +// Sample Adjustment +// <0x0=>7-8-9 (3-4-5 8-bit over-sampling) +// <0x1=>9-10-11 (4-5-6 8-bit over-sampling) +// <0x2=>11-12-13 (5-6-7 8-bit over-sampling) +// <0x3=>13-14-15 (6-7-8 8-bit over-sampling) +// Adjust which samples to use for data sampling in asynchronous mode +// usart_arch_sampa +#ifndef CONF_SERCOM_3_USART_SAMPA +#define CONF_SERCOM_3_USART_SAMPA 0x0 +#endif + +// Fractional Part <0-7> +// Fractional part of the baud rate if baud rate generator is in fractional mode +// usart_arch_fractional +#ifndef CONF_SERCOM_3_USART_FRACTIONAL +#define CONF_SERCOM_3_USART_FRACTIONAL 0x0 +#endif + +// Data Order +// <0=>MSB is transmitted first +// <1=>LSB is transmitted first +// Data order of the data bits in the frame +// usart_arch_dord +#ifndef CONF_SERCOM_3_USART_DORD +#define CONF_SERCOM_3_USART_DORD 1 +#endif + +// Does not do anything in UART mode +#define CONF_SERCOM_3_USART_CPOL 0 + +// Encoding Format +// <0=>No encoding +// <1=>IrDA encoded +// usart_arch_enc +#ifndef CONF_SERCOM_3_USART_ENC +#define CONF_SERCOM_3_USART_ENC 0 +#endif + +// LIN Slave Enable +// Break Character Detection and Auto-Baud/LIN Slave Enable. +// Additional setting needed: 16x sample rate using fractional baud rate generation (CTRLA.SAMPR = 1). +// <0=>Disable +// <1=>Enable +// usart_arch_lin_slave_enable +#ifndef CONF_SERCOM_3_USART_LIN_SLAVE_ENABLE +#define CONF_SERCOM_3_USART_LIN_SLAVE_ENABLE 0 +#endif + +// Debug Stop Mode +// Behavior of the baud-rate generator when CPU is halted by external debugger. +// <0=>Keep running +// <1=>Halt +// usart_arch_dbgstop +#ifndef CONF_SERCOM_3_USART_DEBUG_STOP_MODE +#define CONF_SERCOM_3_USART_DEBUG_STOP_MODE 0 +#endif + +// + +#ifndef CONF_SERCOM_3_USART_CMODE +#define CONF_SERCOM_3_USART_CMODE 0 +#endif + +#ifndef CONF_SERCOM_3_USART_RXPO +#define CONF_SERCOM_3_USART_RXPO 1 /* RX is on PIN_PA23 */ +#endif + +#ifndef CONF_SERCOM_3_USART_TXPO +#define CONF_SERCOM_3_USART_TXPO 0 /* TX is on PIN_PA16 */ +#endif + +/* Set correct parity settings in register interface based on PARITY setting */ +#if CONF_SERCOM_3_USART_LIN_SLAVE_ENABLE == 1 +#if CONF_SERCOM_3_USART_PARITY == 0 +#define CONF_SERCOM_3_USART_PMODE 0 +#define CONF_SERCOM_3_USART_FORM 4 +#else +#define CONF_SERCOM_3_USART_PMODE CONF_SERCOM_3_USART_PARITY - 1 +#define CONF_SERCOM_3_USART_FORM 5 +#endif +#else /* #if CONF_SERCOM_3_USART_LIN_SLAVE_ENABLE == 0 */ +#if CONF_SERCOM_3_USART_PARITY == 0 +#define CONF_SERCOM_3_USART_PMODE 0 +#define CONF_SERCOM_3_USART_FORM 0 +#else +#define CONF_SERCOM_3_USART_PMODE CONF_SERCOM_3_USART_PARITY - 1 +#define CONF_SERCOM_3_USART_FORM 1 +#endif +#endif + +// Calculate BAUD register value in UART mode +#if CONF_SERCOM_3_USART_SAMPR == 0 +#ifndef CONF_SERCOM_3_USART_BAUD_RATE +#define CONF_SERCOM_3_USART_BAUD_RATE \ + 65536 - ((65536 * 16.0f * CONF_SERCOM_3_USART_BAUD) / CONF_GCLK_SERCOM3_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_3_USART_SAMPR == 1 +#ifndef CONF_SERCOM_3_USART_BAUD_RATE +#define CONF_SERCOM_3_USART_BAUD_RATE \ + ((CONF_GCLK_SERCOM3_CORE_FREQUENCY) / (CONF_SERCOM_3_USART_BAUD * 16)) - (CONF_SERCOM_3_USART_FRACTIONAL / 8) +#endif +#ifndef CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_3_USART_SAMPR == 2 +#ifndef CONF_SERCOM_3_USART_BAUD_RATE +#define CONF_SERCOM_3_USART_BAUD_RATE \ + 65536 - ((65536 * 8.0f * CONF_SERCOM_3_USART_BAUD) / CONF_GCLK_SERCOM3_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_3_USART_SAMPR == 3 +#ifndef CONF_SERCOM_3_USART_BAUD_RATE +#define CONF_SERCOM_3_USART_BAUD_RATE \ + ((CONF_GCLK_SERCOM3_CORE_FREQUENCY) / (CONF_SERCOM_3_USART_BAUD * 8)) - (CONF_SERCOM_3_USART_FRACTIONAL / 8) +#endif +#ifndef CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_3_USART_SAMPR == 4 +#ifndef CONF_SERCOM_3_USART_BAUD_RATE +#define CONF_SERCOM_3_USART_BAUD_RATE \ + 65536 - ((65536 * 3.0f * CONF_SERCOM_3_USART_BAUD) / CONF_GCLK_SERCOM3_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#endif + +// <<< end of configuration section >>> + +#endif // HPL_SERCOM_CONFIG_H diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/Config/hpl_systick_config.h b/prototype/firmware/I2C_scanner/I2C_scanner/Config/hpl_systick_config.h new file mode 100644 index 00000000..a7f2f362 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/Config/hpl_systick_config.h @@ -0,0 +1,18 @@ +/* Auto-generated config file hpl_systick_config.h */ +#ifndef HPL_SYSTICK_CONFIG_H +#define HPL_SYSTICK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Advanced settings +// SysTick exception request +// Indicates whether the generation of SysTick exception is enabled or not +// systick_arch_tickint +#ifndef CONF_SYSTICK_TICKINT +#define CONF_SYSTICK_TICKINT 0 +#endif +// + +// <<< end of configuration section >>> + +#endif // HPL_SYSTICK_CONFIG_H diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/Config/peripheral_clk_config.h b/prototype/firmware/I2C_scanner/I2C_scanner/Config/peripheral_clk_config.h new file mode 100644 index 00000000..c3e10776 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/Config/peripheral_clk_config.h @@ -0,0 +1,145 @@ +/* Auto-generated config file peripheral_clk_config.h */ +#ifndef PERIPHERAL_CLK_CONFIG_H +#define PERIPHERAL_CLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +/** + * \def CONF_CPU_FREQUENCY + * \brief CPU's Clock frequency + */ +#ifndef CONF_CPU_FREQUENCY +#define CONF_CPU_FREQUENCY 16000000 +#endif + +// Core Clock Source +// core_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM0_CORE_SRC +#define CONF_GCLK_SERCOM0_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// Slow Clock Source +// slow_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the slow clock source. +#ifndef CONF_GCLK_SERCOM0_SLOW_SRC +#define CONF_GCLK_SERCOM0_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM0_CORE_FREQUENCY + * \brief SERCOM0's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM0_CORE_FREQUENCY +#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 16000000 +#endif + +/** + * \def CONF_GCLK_SERCOM0_SLOW_FREQUENCY + * \brief SERCOM0's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM0_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM0_SLOW_FREQUENCY 400000 +#endif + +// Core Clock Source +// core_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM3_CORE_SRC +#define CONF_GCLK_SERCOM3_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// Slow Clock Source +// slow_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the slow clock source. +#ifndef CONF_GCLK_SERCOM3_SLOW_SRC +#define CONF_GCLK_SERCOM3_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM3_CORE_FREQUENCY + * \brief SERCOM3's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM3_CORE_FREQUENCY +#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 16000000 +#endif + +/** + * \def CONF_GCLK_SERCOM3_SLOW_FREQUENCY + * \brief SERCOM3's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM3_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM3_SLOW_FREQUENCY 400000 +#endif + +// <<< end of configuration section >>> + +#endif // PERIPHERAL_CLK_CONFIG_H diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/Config/stdio_redirect_config.h b/prototype/firmware/I2C_scanner/I2C_scanner/Config/stdio_redirect_config.h new file mode 100644 index 00000000..3515c0c5 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/Config/stdio_redirect_config.h @@ -0,0 +1,9 @@ +/* Auto-generated config file stdio_redirect_config.h */ +#ifndef STDIO_REDIRECT_CONFIG_H +#define STDIO_REDIRECT_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// <<< end of configuration section >>> + +#endif // STDIO_REDIRECT_CONFIG_H diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/Debug.xml b/prototype/firmware/I2C_scanner/I2C_scanner/Debug.xml new file mode 100644 index 00000000..989ebb21 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/Debug.xml @@ -0,0 +1,100 @@ + + True + True + True + True + True + + + DEBUG + + + + + %24(PackRepoDir)\ARM\CMSIS\5.4.0\CMSIS\Core\Include\ + ../Config + ../ + ../examples + ../hal/include + ../hal/utils/include + ../hpl/core + ../hpl/dmac + ../hpl/gclk + ../hpl/mclk + ../hpl/osc32kctrl + ../hpl/oscctrl + ../hpl/pm + ../hpl/port + ../hpl/sercom + ../hpl/systick + ../hri + ../stdio_redirect + %24(PackRepoDir)\Atmel\SAML21_DFP\1.2.125\saml21b\include + + + Optimize (-O1) + True + Maximum (-g3) + True + True + + + libm + + + + + %24(ProjectDir)\Device_Startup + + + True + -Tsaml21j18b_flash.ld + + + %24(PackRepoDir)\ARM\CMSIS\5.4.0\CMSIS\Core\Include\ + ../Config + ../ + ../examples + ../hal/include + ../hal/utils/include + ../hpl/core + ../hpl/dmac + ../hpl/gclk + ../hpl/mclk + ../hpl/osc32kctrl + ../hpl/oscctrl + ../hpl/pm + ../hpl/port + ../hpl/sercom + ../hpl/systick + ../hri + ../stdio_redirect + %24(PackRepoDir)\Atmel\SAML21_DFP\1.2.125\saml21b\include + + + Default (-g) + + + %24(PackRepoDir)\ARM\CMSIS\5.4.0\CMSIS\Core\Include\ + ../Config + ../ + ../examples + ../hal/include + ../hal/utils/include + ../hpl/core + ../hpl/dmac + ../hpl/gclk + ../hpl/mclk + ../hpl/osc32kctrl + ../hpl/oscctrl + ../hpl/pm + ../hpl/port + ../hpl/sercom + ../hpl/systick + ../hri + ../stdio_redirect + %24(PackRepoDir)\Atmel\SAML21_DFP\1.2.125\saml21b\include + + + Default (-Wa,-g) + \ No newline at end of file diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/Default.xml b/prototype/firmware/I2C_scanner/I2C_scanner/Default.xml new file mode 100644 index 00000000..c2b7fc10 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/Default.xml @@ -0,0 +1,475 @@ + + + + + + + DebugLevel + None + + + IncludePaths + NDEBUG + + + MiscellaneousSettings + -std=gnu99 + + + OptimizationLevel + Optimize for size (-Os) + + + SymbolDefines + NDEBUG + + + SymbolUndefines + + + + Verbose + False + + + WarningsAsErrors + False + + + armgcc.compiler.general.CLanguageExp + True + + + armgcc.compiler.general.ChangeDefaultCharTypeUnsigned + False + + + armgcc.compiler.general.ChangeDefaultBitFieldUnsigned + False + + + armgcc.compiler.general.processormode + + + + armgcc.compiler.preprocessor.DoNotSearchSystemDirectories + False + + + armgcc.compiler.preprocessor.PreprocessOnly + False + + + armgcc.compiler.symbols.Default + + + + armgcc.compiler.directories.DefaultIncludePath + True + + + armgcc.compiler.optimization.OtherFlags + + + + armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection + True + + + armgcc.compiler.optimization.PrepareDataForGarbageCollection + False + + + armgcc.compiler.optimization.EnableUnsafeMatchOptimizations + False + + + armgcc.compiler.optimization.EnableFastMath + False + + + armgcc.compiler.optimization.GeneratePositionIndependentCode + False + + + armgcc.compiler.optimization.EnableLongCalls + True + + + armgcc.compiler.optimization.OtherDebuggingFlags + + + + armgcc.compiler.optimization.GenerateGprofInformation + False + + + armgcc.compiler.optimization.GenerateProfInformation + False + + + armgcc.compiler.warnings.AllWarnings + True + + + armgcc.compiler.warnings.ExtraWarnings + False + + + armgcc.compiler.warnings.Undefined + False + + + armgcc.compiler.warnings.CheckSyntaxOnly + False + + + armgcc.compiler.warnings.Pedantic + False + + + armgcc.compiler.warnings.PedanticWarningsAsErrors + False + + + armgcc.compiler.warnings.InhibitAllWarnings + False + + + armgcc.compiler.miscellaneous.Device + True + + + armgcc.compiler.miscellaneous.CompileOnly + True + + + armgcc.compiler.miscellaneous.SupportAnsiPrograms + False + + + armgcc.compiler.miscellaneous.MakeFileDependent + True + + + + + Libraries + libm + + + LibrarySearchPath + $(ProjectDir)\Device_Startup + + + MiscellaneousSettings + -Tsaml21j18b_flash.ld + + + armgcc.linker.general.DoNotUseStandardStartFiles + False + + + armgcc.linker.general.DoNotUseDefaultLibraries + False + + + armgcc.linker.general.NoStartupOrDefaultLibs + False + + + armgcc.linker.general.OmitAllSymbolInformation + False + + + armgcc.linker.general.NoSharedLibraries + False + + + armgcc.linker.general.GenerateMAPFile + True + + + armgcc.linker.general.UseNewlibNano + False + + + armgcc.linker.general.AdditionalSpecs + None + + + armgcc.linker.optimization.GarbageCollectUnusedSections + True + + + armgcc.linker.optimization.EnableUnsafeMatchOptimizations + False + + + armgcc.linker.optimization.EnableFastMath + False + + + armgcc.linker.optimization.GeneratePositionIndependentCode + False + + + armgcc.linker.memorysettings.Flash + + + + armgcc.linker.memorysettings.Sram + + + + armgcc.linker.memorysettings.ExternalRAM + + + + armgcc.linker.miscellaneous.OtherOptions + + + + armgcc.linker.miscellaneous.OtherObjects + + + + Release + + + + + DebugLevel + Maximum (-g3) + + + IncludePaths + DEBUG + + + MiscellaneousSettings + -std=gnu99 + + + OptimizationLevel + Optimize (-O1) + + + SymbolDefines + DEBUG + + + SymbolUndefines + + + + Verbose + False + + + WarningsAsErrors + False + + + armgcc.compiler.general.CLanguageExp + True + + + armgcc.compiler.general.ChangeDefaultCharTypeUnsigned + False + + + armgcc.compiler.general.ChangeDefaultBitFieldUnsigned + False + + + armgcc.compiler.general.processormode + + + + armgcc.compiler.preprocessor.DoNotSearchSystemDirectories + False + + + armgcc.compiler.preprocessor.PreprocessOnly + False + + + armgcc.compiler.symbols.Default + + + + armgcc.compiler.directories.DefaultIncludePath + True + + + armgcc.compiler.optimization.OtherFlags + + + + armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection + True + + + armgcc.compiler.optimization.PrepareDataForGarbageCollection + False + + + armgcc.compiler.optimization.EnableUnsafeMatchOptimizations + False + + + armgcc.compiler.optimization.EnableFastMath + False + + + armgcc.compiler.optimization.GeneratePositionIndependentCode + False + + + armgcc.compiler.optimization.EnableLongCalls + True + + + armgcc.compiler.optimization.OtherDebuggingFlags + + + + armgcc.compiler.optimization.GenerateGprofInformation + False + + + armgcc.compiler.optimization.GenerateProfInformation + False + + + armgcc.compiler.warnings.AllWarnings + True + + + armgcc.compiler.warnings.ExtraWarnings + False + + + armgcc.compiler.warnings.Undefined + False + + + armgcc.compiler.warnings.CheckSyntaxOnly + False + + + armgcc.compiler.warnings.Pedantic + False + + + armgcc.compiler.warnings.PedanticWarningsAsErrors + False + + + armgcc.compiler.warnings.InhibitAllWarnings + False + + + armgcc.compiler.miscellaneous.Device + True + + + armgcc.compiler.miscellaneous.CompileOnly + True + + + armgcc.compiler.miscellaneous.SupportAnsiPrograms + False + + + armgcc.compiler.miscellaneous.MakeFileDependent + True + + + + + Libraries + libm + + + LibrarySearchPath + $(ProjectDir)\Device_Startup + + + MiscellaneousSettings + -Tsaml21j18b_flash.ld + + + armgcc.linker.general.DoNotUseStandardStartFiles + False + + + armgcc.linker.general.DoNotUseDefaultLibraries + False + + + armgcc.linker.general.NoStartupOrDefaultLibs + False + + + armgcc.linker.general.OmitAllSymbolInformation + False + + + armgcc.linker.general.NoSharedLibraries + False + + + armgcc.linker.general.GenerateMAPFile + True + + + armgcc.linker.general.UseNewlibNano + False + + + armgcc.linker.general.AdditionalSpecs + None + + + armgcc.linker.optimization.GarbageCollectUnusedSections + True + + + armgcc.linker.optimization.EnableUnsafeMatchOptimizations + False + + + armgcc.linker.optimization.EnableFastMath + False + + + armgcc.linker.optimization.GeneratePositionIndependentCode + False + + + armgcc.linker.memorysettings.Flash + + + + armgcc.linker.memorysettings.Sram + + + + armgcc.linker.memorysettings.ExternalRAM + + + + armgcc.linker.miscellaneous.OtherOptions + + + + armgcc.linker.miscellaneous.OtherObjects + + + + Debug + + + \ No newline at end of file diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/Device_Startup/saml21j18b_flash.ld b/prototype/firmware/I2C_scanner/I2C_scanner/Device_Startup/saml21j18b_flash.ld new file mode 100644 index 00000000..d890c8c0 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/Device_Startup/saml21j18b_flash.ld @@ -0,0 +1,153 @@ +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAML21J18B + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 + lpram (rwx) : ORIGIN = 0x30000000, LENGTH = 0x00002000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + .lpram (NOLOAD): + { + . = ALIGN(8); + _slpram = .; + *(.lpram .lpram.*); + . = ALIGN(8); + _elpram = .; + } > lpram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/Device_Startup/saml21j18b_sram.ld b/prototype/firmware/I2C_scanner/I2C_scanner/Device_Startup/saml21j18b_sram.ld new file mode 100644 index 00000000..05b56d60 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/Device_Startup/saml21j18b_sram.ld @@ -0,0 +1,152 @@ +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAML21J18B + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 + lpram (rwx) : ORIGIN = 0x30000000, LENGTH = 0x00002000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + .lpram (NOLOAD): + { + . = ALIGN(8); + _slpram = .; + *(.lpram .lpram.*); + . = ALIGN(8); + _elpram = .; + } > lpram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/Device_Startup/startup_saml21.c b/prototype/firmware/I2C_scanner/I2C_scanner/Device_Startup/startup_saml21.c new file mode 100644 index 00000000..01fab1cc --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/Device_Startup/startup_saml21.c @@ -0,0 +1,257 @@ +/** + * \file + * + * \brief gcc starttup file for SAML21 + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#include "saml21.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M0+ core handlers */ +void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* MCLK, OSC32KCTRL, OSCCTRL, PAC, PM, SUPC, TAL */ +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void NVMCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef ID_USB +void USB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +void EVSYS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef ID_SERCOM4 +void SERCOM4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_SERCOM5 +void SERCOM5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +void TCC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef ID_TC2 +void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_TC3 +void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef ID_ADC +void ADC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_AC +void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_DAC +void DAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_PTC +void PTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_AES +void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_TRNG +void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pvReservedM12 = (void*) (0UL), /* Reserved */ + .pvReservedM11 = (void*) (0UL), /* Reserved */ + .pvReservedM10 = (void*) (0UL), /* Reserved */ + .pvReservedM9 = (void*) (0UL), /* Reserved */ + .pvReservedM8 = (void*) (0UL), /* Reserved */ + .pvReservedM7 = (void*) (0UL), /* Reserved */ + .pvReservedM6 = (void*) (0UL), /* Reserved */ + .pfnSVCall_Handler = (void*) SVCall_Handler, + .pvReservedM4 = (void*) (0UL), /* Reserved */ + .pvReservedM3 = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnSYSTEM_Handler = (void*) SYSTEM_Handler, /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 1 Watchdog Timer */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 2 Real-Time Counter */ + .pfnEIC_Handler = (void*) EIC_Handler, /* 3 External Interrupt Controller */ + .pfnNVMCTRL_Handler = (void*) NVMCTRL_Handler, /* 4 Non-Volatile Memory Controller */ + .pfnDMAC_Handler = (void*) DMAC_Handler, /* 5 Direct Memory Access Controller */ +#ifdef ID_USB + .pfnUSB_Handler = (void*) USB_Handler, /* 6 Universal Serial Bus */ +#else + .pvReserved6 = (void*) (0UL), /* 6 Reserved */ +#endif + .pfnEVSYS_Handler = (void*) EVSYS_Handler, /* 7 Event System Interface */ + .pfnSERCOM0_Handler = (void*) SERCOM0_Handler, /* 8 Serial Communication Interface 0 */ + .pfnSERCOM1_Handler = (void*) SERCOM1_Handler, /* 9 Serial Communication Interface 1 */ + .pfnSERCOM2_Handler = (void*) SERCOM2_Handler, /* 10 Serial Communication Interface 2 */ + .pfnSERCOM3_Handler = (void*) SERCOM3_Handler, /* 11 Serial Communication Interface 3 */ +#ifdef ID_SERCOM4 + .pfnSERCOM4_Handler = (void*) SERCOM4_Handler, /* 12 Serial Communication Interface 4 */ +#else + .pvReserved12 = (void*) (0UL), /* 12 Reserved */ +#endif +#ifdef ID_SERCOM5 + .pfnSERCOM5_Handler = (void*) SERCOM5_Handler, /* 13 Serial Communication Interface 5 */ +#else + .pvReserved13 = (void*) (0UL), /* 13 Reserved */ +#endif + .pfnTCC0_Handler = (void*) TCC0_Handler, /* 14 Timer Counter Control 0 */ + .pfnTCC1_Handler = (void*) TCC1_Handler, /* 15 Timer Counter Control 1 */ + .pfnTCC2_Handler = (void*) TCC2_Handler, /* 16 Timer Counter Control 2 */ + .pfnTC0_Handler = (void*) TC0_Handler, /* 17 Basic Timer Counter 0 */ + .pfnTC1_Handler = (void*) TC1_Handler, /* 18 Basic Timer Counter 1 */ +#ifdef ID_TC2 + .pfnTC2_Handler = (void*) TC2_Handler, /* 19 Basic Timer Counter 2 */ +#else + .pvReserved19 = (void*) (0UL), /* 19 Reserved */ +#endif +#ifdef ID_TC3 + .pfnTC3_Handler = (void*) TC3_Handler, /* 20 Basic Timer Counter 3 */ +#else + .pvReserved20 = (void*) (0UL), /* 20 Reserved */ +#endif + .pfnTC4_Handler = (void*) TC4_Handler, /* 21 Basic Timer Counter 4 */ +#ifdef ID_ADC + .pfnADC_Handler = (void*) ADC_Handler, /* 22 Analog Digital Converter */ +#else + .pvReserved22 = (void*) (0UL), /* 22 Reserved */ +#endif +#ifdef ID_AC + .pfnAC_Handler = (void*) AC_Handler, /* 23 Analog Comparators */ +#else + .pvReserved23 = (void*) (0UL), /* 23 Reserved */ +#endif +#ifdef ID_DAC + .pfnDAC_Handler = (void*) DAC_Handler, /* 24 Digital-to-Analog Converter */ +#else + .pvReserved24 = (void*) (0UL), /* 24 Reserved */ +#endif +#ifdef ID_PTC + .pfnPTC_Handler = (void*) PTC_Handler, /* 25 Peripheral Touch Controller */ +#else + .pvReserved25 = (void*) (0UL), /* 25 Reserved */ +#endif +#ifdef ID_AES + .pfnAES_Handler = (void*) AES_Handler, /* 26 Advanced Encryption Standard */ +#else + .pvReserved26 = (void*) (0UL), /* 26 Reserved */ +#endif +#ifdef ID_TRNG + .pfnTRNG_Handler = (void*) TRNG_Handler, /* 27 True Random Generator */ +#else + .pvReserved27 = (void*) (0UL), /* 27 Reserved */ +#endif + .pvReserved28 = (void*) (0UL) /* 28 Reserved */ +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Overwriting the default value of the NVMCTRL.CTRLB.MANW bit (errata reference 13134) */ + NVMCTRL->CTRLB.bit.MANW = 1; + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/Device_Startup/system_saml21.c b/prototype/firmware/I2C_scanner/I2C_scanner/Device_Startup/system_saml21.c new file mode 100644 index 00000000..5ab3e70d --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/Device_Startup/system_saml21.c @@ -0,0 +1,64 @@ +/** + * \file + * + * \brief Low-level initialization functions called upon chip startup. + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#include "saml21.h" + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (4000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/I2C_scanner.componentinfo.xml b/prototype/firmware/I2C_scanner/I2C_scanner/I2C_scanner.componentinfo.xml new file mode 100644 index 00000000..2b36809a --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/I2C_scanner.componentinfo.xml @@ -0,0 +1,169 @@ + + + + + + + CMSIS + CORE + + + ARM + 5.1.2 + C:/Program Files (x86)\Atmel\Studio\7.0\Packs + + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\ARM\CMSIS\5.4.0\CMSIS\Documentation\Core\html\index.html + + doc + + Q8N76dSMXRCvBEtXHmDLig== + + CMSIS/Documentation/Core/html/index.html + + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\ARM\CMSIS\5.4.0\CMSIS\Core\Include\ + + include + + + + CMSIS/Core/Include/ + + + + + CMSIS + C:/Program Files (x86)/Atmel/Studio/7.0/Packs/ARM/CMSIS/5.4.0/ARM.CMSIS.pdsc + 5.4.0 + true + ARMv6_7_8-M Device + + + + Resolved + Fixed + true + + + + + Device + Startup + + + Atmel + 1.2.0 + C:/Program Files (x86)\Atmel\Studio\7.0\Packs + + + + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\Atmel\SAML21_DFP\1.2.125\saml21b\include + + include + C + + + saml21b/include + + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\Atmel\SAML21_DFP\1.2.125\saml21b\include\sam.h + + header + C + tUyaDQL2CUvpNPje1XBiew== + + saml21b/include/sam.h + + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\Atmel\SAML21_DFP\1.2.125\saml21b\templates\main.c + template + source + C Exe + 7o0SBhcRPxCa8YpY8PIcyA== + + saml21b/templates/main.c + Main file (.c) + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\Atmel\SAML21_DFP\1.2.125\saml21b\templates\main.cpp + template + source + C Exe + nU+WlKcYaWh0AWBBS+WVpA== + + saml21b/templates/main.cpp + Main file (.cpp) + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\Atmel\SAML21_DFP\1.2.125\saml21b\gcc\system_saml21.c + config + source + GCC Exe + U+bOrHkMSAjACDLHAKXn+Q== + + saml21b/gcc/system_saml21.c + + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\Atmel\SAML21_DFP\1.2.125\saml21b\gcc\gcc\startup_saml21.c + config + source + GCC Exe + zijEzWB7CmllWulJu1ACzw== + + saml21b/gcc/gcc/startup_saml21.c + + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\Atmel\SAML21_DFP\1.2.125\saml21b\gcc\gcc\saml21j18b_flash.ld + config + linkerScript + GCC Exe + 4Sn9xSQH3dWLaW/jxl0XUw== + + saml21b/gcc/gcc/saml21j18b_flash.ld + + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\Atmel\SAML21_DFP\1.2.125\saml21b\gcc\gcc\saml21j18b_sram.ld + config + other + GCC Exe + ftBhgaPqM4tW/jKmhVu3mg== + + saml21b/gcc/gcc/saml21j18b_sram.ld + + + + + SAML21_DFP + C:/Program Files (x86)/Atmel/Studio/7.0/Packs/Atmel/SAML21_DFP/1.2.125/Atmel.SAML21_DFP.pdsc + 1.2.125 + true + ATSAML21J18B + + + + Resolved + Fixed + true + + + \ No newline at end of file diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/I2C_scanner.cproj b/prototype/firmware/I2C_scanner/I2C_scanner/I2C_scanner.cproj new file mode 100644 index 00000000..85743675 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/I2C_scanner.cproj @@ -0,0 +1,811 @@ + + + + 2.0 + 7.0 + com.Atmel.ARMGCC.C + dce6c7e3-ee26-4d79-826b-08594b9ad897 + ATSAML21J18B + none + Executable + C + $(MSBuildProjectName) + .elf + $(MSBuildProjectDirectory)\$(Configuration) + I2C_scanner + I2C_scanner + I2C_scanner + Native + true + false + true + true + + + true + + 2 + 0 + 0 + + + + + + + + + + + + + + .atmelstart\atmel_start_config.atstart + .atmelstart\AtmelStart.gpdsc + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + True + True + True + True + True + + + NDEBUG + + + + + %24(PackRepoDir)\ARM\CMSIS\5.4.0\CMSIS\Core\Include\ + ../Config + ../ + ../examples + ../hal/include + ../hal/utils/include + ../hpl/core + ../hpl/dmac + ../hpl/gclk + ../hpl/mclk + ../hpl/osc32kctrl + ../hpl/oscctrl + ../hpl/pm + ../hpl/port + ../hpl/sercom + ../hpl/systick + ../hri + ../stdio_redirect + %24(PackRepoDir)\Atmel\SAML21_DFP\1.2.125\saml21b\include + + + Optimize for size (-Os) + True + True + True + + + libm + + + + + %24(ProjectDir)\Device_Startup + + + True + -Tsaml21j18b_flash.ld + + + %24(PackRepoDir)\ARM\CMSIS\5.4.0\CMSIS\Core\Include\ + ../Config + ../ + ../examples + ../hal/include + ../hal/utils/include + ../hpl/core + ../hpl/dmac + ../hpl/gclk + ../hpl/mclk + ../hpl/osc32kctrl + ../hpl/oscctrl + ../hpl/pm + ../hpl/port + ../hpl/sercom + ../hpl/systick + ../hri + ../stdio_redirect + %24(PackRepoDir)\Atmel\SAML21_DFP\1.2.125\saml21b\include + + + + + %24(PackRepoDir)\ARM\CMSIS\5.4.0\CMSIS\Core\Include\ + ../Config + ../ + ../examples + ../hal/include + ../hal/utils/include + ../hpl/core + ../hpl/dmac + ../hpl/gclk + ../hpl/mclk + ../hpl/osc32kctrl + ../hpl/oscctrl + ../hpl/pm + ../hpl/port + ../hpl/sercom + ../hpl/systick + ../hri + ../stdio_redirect + %24(PackRepoDir)\Atmel\SAML21_DFP\1.2.125\saml21b\include + + + + + + + + + True + True + True + True + True + + + DEBUG + + + + + %24(PackRepoDir)\ARM\CMSIS\5.4.0\CMSIS\Core\Include\ + ../Config + ../ + ../examples + ../hal/include + ../hal/utils/include + ../hpl/core + ../hpl/dmac + ../hpl/gclk + ../hpl/mclk + ../hpl/osc32kctrl + ../hpl/oscctrl + ../hpl/pm + ../hpl/port + ../hpl/sercom + ../hpl/systick + ../hri + ../stdio_redirect + %24(PackRepoDir)\Atmel\SAML21_DFP\1.2.125\saml21b\include + + + Optimize (-O1) + True + Maximum (-g3) + True + True + + + libm + + + + + %24(ProjectDir)\Device_Startup + + + True + -Tsaml21j18b_flash.ld + + + %24(PackRepoDir)\ARM\CMSIS\5.4.0\CMSIS\Core\Include\ + ../Config + ../ + ../examples + ../hal/include + ../hal/utils/include + ../hpl/core + ../hpl/dmac + ../hpl/gclk + ../hpl/mclk + ../hpl/osc32kctrl + ../hpl/oscctrl + ../hpl/pm + ../hpl/port + ../hpl/sercom + ../hpl/systick + ../hri + ../stdio_redirect + %24(PackRepoDir)\Atmel\SAML21_DFP\1.2.125\saml21b\include + + + Default (-g) + + + %24(PackRepoDir)\ARM\CMSIS\5.4.0\CMSIS\Core\Include\ + ../Config + ../ + ../examples + ../hal/include + ../hal/utils/include + ../hpl/core + ../hpl/dmac + ../hpl/gclk + ../hpl/mclk + ../hpl/osc32kctrl + ../hpl/oscctrl + ../hpl/pm + ../hpl/port + ../hpl/sercom + ../hpl/systick + ../hri + ../stdio_redirect + %24(PackRepoDir)\Atmel\SAML21_DFP\1.2.125\saml21b\include + + + Default (-Wa,-g) + + + + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + compile + + + compile + + + + \ No newline at end of file diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/Release.xml b/prototype/firmware/I2C_scanner/I2C_scanner/Release.xml new file mode 100644 index 00000000..18d0f2b1 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/Release.xml @@ -0,0 +1,97 @@ + + True + True + True + True + True + + + NDEBUG + + + + + %24(PackRepoDir)\ARM\CMSIS\5.4.0\CMSIS\Core\Include\ + ../Config + ../ + ../examples + ../hal/include + ../hal/utils/include + ../hpl/core + ../hpl/dmac + ../hpl/gclk + ../hpl/mclk + ../hpl/osc32kctrl + ../hpl/oscctrl + ../hpl/pm + ../hpl/port + ../hpl/sercom + ../hpl/systick + ../hri + ../stdio_redirect + %24(PackRepoDir)\Atmel\SAML21_DFP\1.2.125\saml21b\include + + + Optimize for size (-Os) + True + True + True + + + libm + + + + + %24(ProjectDir)\Device_Startup + + + True + -Tsaml21j18b_flash.ld + + + %24(PackRepoDir)\ARM\CMSIS\5.4.0\CMSIS\Core\Include\ + ../Config + ../ + ../examples + ../hal/include + ../hal/utils/include + ../hpl/core + ../hpl/dmac + ../hpl/gclk + ../hpl/mclk + ../hpl/osc32kctrl + ../hpl/oscctrl + ../hpl/pm + ../hpl/port + ../hpl/sercom + ../hpl/systick + ../hri + ../stdio_redirect + %24(PackRepoDir)\Atmel\SAML21_DFP\1.2.125\saml21b\include + + + + + %24(PackRepoDir)\ARM\CMSIS\5.4.0\CMSIS\Core\Include\ + ../Config + ../ + ../examples + ../hal/include + ../hal/utils/include + ../hpl/core + ../hpl/dmac + ../hpl/gclk + ../hpl/mclk + ../hpl/osc32kctrl + ../hpl/oscctrl + ../hpl/pm + ../hpl/port + ../hpl/sercom + ../hpl/systick + ../hri + ../stdio_redirect + %24(PackRepoDir)\Atmel\SAML21_DFP\1.2.125\saml21b\include + + + \ No newline at end of file diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/atmel_start.c b/prototype/firmware/I2C_scanner/I2C_scanner/atmel_start.c new file mode 100644 index 00000000..12895d0d --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/atmel_start.c @@ -0,0 +1,10 @@ +#include + +/** + * Initializes MCU, drivers and middleware in the project + **/ +void atmel_start_init(void) +{ + system_init(); + stdio_redirect_init(); +} diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/atmel_start.h b/prototype/firmware/I2C_scanner/I2C_scanner/atmel_start.h new file mode 100644 index 00000000..ace35cf1 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/atmel_start.h @@ -0,0 +1,19 @@ +#ifndef ATMEL_START_H_INCLUDED +#define ATMEL_START_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include "driver_init.h" +#include "stdio_start.h" + +/** + * Initializes MCU, drivers and middleware in the project + **/ +void atmel_start_init(void); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/atmel_start_pins.h b/prototype/firmware/I2C_scanner/I2C_scanner/atmel_start_pins.h new file mode 100644 index 00000000..758f9cd3 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/atmel_start_pins.h @@ -0,0 +1,30 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ +#ifndef ATMEL_START_PINS_H_INCLUDED +#define ATMEL_START_PINS_H_INCLUDED + +#include + +// SAML21 has 9 pin functions + +#define GPIO_PIN_FUNCTION_A 0 +#define GPIO_PIN_FUNCTION_B 1 +#define GPIO_PIN_FUNCTION_C 2 +#define GPIO_PIN_FUNCTION_D 3 +#define GPIO_PIN_FUNCTION_E 4 +#define GPIO_PIN_FUNCTION_F 5 +#define GPIO_PIN_FUNCTION_G 6 +#define GPIO_PIN_FUNCTION_H 7 +#define GPIO_PIN_FUNCTION_I 8 + +#define PA08 GPIO(GPIO_PORTA, 8) +#define PA09 GPIO(GPIO_PORTA, 9) +#define PA22 GPIO(GPIO_PORTA, 22) +#define PA23 GPIO(GPIO_PORTA, 23) + +#endif // ATMEL_START_PINS_H_INCLUDED diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/driver_init.c b/prototype/firmware/I2C_scanner/I2C_scanner/driver_init.c new file mode 100644 index 00000000..ccf97bfe --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/driver_init.c @@ -0,0 +1,94 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ + +#include "driver_init.h" +#include +#include +#include + +struct i2c_m_sync_desc I2C_0; + +struct usart_sync_descriptor TARGET_IO; + +void I2C_0_PORT_init(void) +{ + + gpio_set_pin_pull_mode(PA08, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PA08, PINMUX_PA08C_SERCOM0_PAD0); + + gpio_set_pin_pull_mode(PA09, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PA09, PINMUX_PA09C_SERCOM0_PAD1); +} + +void I2C_0_CLOCK_init(void) +{ + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_CORE, CONF_GCLK_SERCOM0_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_SLOW, CONF_GCLK_SERCOM0_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + + hri_mclk_set_APBCMASK_SERCOM0_bit(MCLK); +} + +void I2C_0_init(void) +{ + I2C_0_CLOCK_init(); + i2c_m_sync_init(&I2C_0, SERCOM0); + I2C_0_PORT_init(); +} + +void TARGET_IO_PORT_init(void) +{ + + gpio_set_pin_function(PA22, PINMUX_PA22C_SERCOM3_PAD0); + + gpio_set_pin_function(PA23, PINMUX_PA23C_SERCOM3_PAD1); +} + +void TARGET_IO_CLOCK_init(void) +{ + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM3_GCLK_ID_CORE, CONF_GCLK_SERCOM3_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM3_GCLK_ID_SLOW, CONF_GCLK_SERCOM3_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + + hri_mclk_set_APBCMASK_SERCOM3_bit(MCLK); +} + +void TARGET_IO_init(void) +{ + TARGET_IO_CLOCK_init(); + usart_sync_init(&TARGET_IO, SERCOM3, (void *)NULL); + TARGET_IO_PORT_init(); +} + +void delay_driver_init(void) +{ + delay_init(SysTick); +} + +void system_init(void) +{ + init_mcu(); + + I2C_0_init(); + + TARGET_IO_init(); + + delay_driver_init(); +} diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/driver_init.h b/prototype/firmware/I2C_scanner/I2C_scanner/driver_init.h new file mode 100644 index 00000000..ad905174 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/driver_init.h @@ -0,0 +1,53 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ +#ifndef DRIVER_INIT_INCLUDED +#define DRIVER_INIT_INCLUDED + +#include "atmel_start_pins.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include + +extern struct i2c_m_sync_desc I2C_0; + +extern struct usart_sync_descriptor TARGET_IO; + +void I2C_0_CLOCK_init(void); +void I2C_0_init(void); +void I2C_0_PORT_init(void); + +void TARGET_IO_PORT_init(void); +void TARGET_IO_CLOCK_init(void); +void TARGET_IO_init(void); + +void delay_driver_init(void); + +/** + * \brief Perform system initialization, initialize pins and clocks for + * peripherals + */ +void system_init(void); + +#ifdef __cplusplus +} +#endif +#endif // DRIVER_INIT_INCLUDED diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/examples/driver_examples.c b/prototype/firmware/I2C_scanner/I2C_scanner/examples/driver_examples.c new file mode 100644 index 00000000..605bbffe --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/examples/driver_examples.c @@ -0,0 +1,38 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ + +#include "driver_examples.h" +#include "driver_init.h" +#include "utils.h" + +void I2C_0_example(void) +{ + struct io_descriptor *I2C_0_io; + + i2c_m_sync_get_io_descriptor(&I2C_0, &I2C_0_io); + i2c_m_sync_enable(&I2C_0); + i2c_m_sync_set_slaveaddr(&I2C_0, 0x12, I2C_M_SEVEN); + io_write(I2C_0_io, (uint8_t *)"Hello World!", 12); +} + +/** + * Example of using TARGET_IO to write "Hello World" using the IO abstraction. + */ +void TARGET_IO_example(void) +{ + struct io_descriptor *io; + usart_sync_get_io_descriptor(&TARGET_IO, &io); + usart_sync_enable(&TARGET_IO); + + io_write(io, (uint8_t *)"Hello World!", 12); +} + +void delay_example(void) +{ + delay_ms(5000); +} diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/examples/driver_examples.h b/prototype/firmware/I2C_scanner/I2C_scanner/examples/driver_examples.h new file mode 100644 index 00000000..93e2a9f1 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/examples/driver_examples.h @@ -0,0 +1,24 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ +#ifndef DRIVER_EXAMPLES_H_INCLUDED +#define DRIVER_EXAMPLES_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +void I2C_0_example(void); + +void TARGET_IO_example(void); + +void delay_example(void); + +#ifdef __cplusplus +} +#endif +#endif // DRIVER_EXAMPLES_H_INCLUDED diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hal_atomic.h b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hal_atomic.h new file mode 100644 index 00000000..82151fc5 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hal_atomic.h @@ -0,0 +1,120 @@ +/** + * \file + * + * \brief Critical sections related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_ATOMIC_H_INCLUDED +#define _HAL_ATOMIC_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_helper_atomic + * + *@{ + */ + +/** + * \brief Type for the register holding global interrupt enable flag + */ +typedef uint32_t hal_atomic_t; + +/** + * \brief Helper macro for entering critical sections + * + * This macro is recommended to be used instead of a direct call + * hal_enterCritical() function to enter critical + * sections. No semicolon is required after the macro. + * + * \section atomic_usage Usage Example + * \code + * CRITICAL_SECTION_ENTER() + * Critical code + * CRITICAL_SECTION_LEAVE() + * \endcode + */ +#define CRITICAL_SECTION_ENTER() \ + { \ + volatile hal_atomic_t __atomic; \ + atomic_enter_critical(&__atomic); + +/** + * \brief Helper macro for leaving critical sections + * + * This macro is recommended to be used instead of a direct call + * hal_leaveCritical() function to leave critical + * sections. No semicolon is required after the macro. + */ +#define CRITICAL_SECTION_LEAVE() \ + atomic_leave_critical(&__atomic); \ + } + +/** + * \brief Disable interrupts, enter critical section + * + * Disables global interrupts. Supports nested critical sections, + * so that global interrupts are only re-enabled + * upon leaving the outermost nested critical section. + * + * \param[out] atomic The pointer to a variable to store the value of global + * interrupt enable flag + */ +void atomic_enter_critical(hal_atomic_t volatile *atomic); + +/** + * \brief Exit atomic section + * + * Enables global interrupts. Supports nested critical sections, + * so that global interrupts are only re-enabled + * upon leaving the outermost nested critical section. + * + * \param[in] atomic The pointer to a variable, which stores the latest stored + * value of the global interrupt enable flag + */ +void atomic_leave_critical(hal_atomic_t volatile *atomic); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t atomic_get_version(void); +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_ATOMIC_H_INCLUDED */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hal_delay.h b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hal_delay.h new file mode 100644 index 00000000..9d4aa5c1 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hal_delay.h @@ -0,0 +1,89 @@ +/** + * \file + * + * \brief HAL delay related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +#ifndef _HAL_DELAY_H_INCLUDED +#define _HAL_DELAY_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_delay Delay Driver + * + *@{ + */ + +/** + * \brief Initialize Delay driver + * + * \param[in] hw The pointer to hardware instance + */ +void delay_init(void *const hw); + +/** + * \brief Perform delay in us + * + * This function performs delay for the given amount of microseconds. + * + * \param[in] us The amount delay in us + */ +void delay_us(const uint16_t us); + +/** + * \brief Perform delay in ms + * + * This function performs delay for the given amount of milliseconds. + * + * \param[in] ms The amount delay in ms + */ +void delay_ms(const uint16_t ms); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t delay_get_version(void); + +/**@}*/ +#ifdef __cplusplus +} +#endif +#endif /* _HAL_DELAY_H_INCLUDED */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hal_gpio.h b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hal_gpio.h new file mode 100644 index 00000000..fbfa2d4a --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hal_gpio.h @@ -0,0 +1,201 @@ +/** + * \file + * + * \brief Port + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ +#ifndef _HAL_GPIO_INCLUDED_ +#define _HAL_GPIO_INCLUDED_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Set gpio pull mode + * + * Set pin pull mode, non existing pull modes throws an fatal assert + * + * \param[in] pin The pin number for device + * \param[in] pull_mode GPIO_PULL_DOWN = Pull pin low with internal resistor + * GPIO_PULL_UP = Pull pin high with internal resistor + * GPIO_PULL_OFF = Disable pin pull mode + */ +static inline void gpio_set_pin_pull_mode(const uint8_t pin, const enum gpio_pull_mode pull_mode) +{ + _gpio_set_pin_pull_mode((enum gpio_port)GPIO_PORT(pin), pin & 0x1F, pull_mode); +} + +/** + * \brief Set pin function + * + * Select which function a pin will be used for + * + * \param[in] pin The pin number for device + * \param[in] function The pin function is given by a 32-bit wide bitfield + * found in the header files for the device + * + */ +static inline void gpio_set_pin_function(const uint32_t pin, uint32_t function) +{ + _gpio_set_pin_function(pin, function); +} + +/** + * \brief Set port data direction + * + * Select if the pin data direction is input, output or disabled. + * If disabled state is not possible, this function throws an assert. + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to the + * corresponding pin + * \param[in] direction GPIO_DIRECTION_IN = Data direction in + * GPIO_DIRECTION_OUT = Data direction out + * GPIO_DIRECTION_OFF = Disables the pin + * (low power state) + */ +static inline void gpio_set_port_direction(const enum gpio_port port, const uint32_t mask, + const enum gpio_direction direction) +{ + _gpio_set_direction(port, mask, direction); +} + +/** + * \brief Set gpio data direction + * + * Select if the pin data direction is input, output or disabled. + * If disabled state is not possible, this function throws an assert. + * + * \param[in] pin The pin number for device + * \param[in] direction GPIO_DIRECTION_IN = Data direction in + * GPIO_DIRECTION_OUT = Data direction out + * GPIO_DIRECTION_OFF = Disables the pin + * (low power state) + */ +static inline void gpio_set_pin_direction(const uint8_t pin, const enum gpio_direction direction) +{ + _gpio_set_direction((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), direction); +} + +/** + * \brief Set port level + * + * Sets output level on the pins defined by the bit mask + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply port level to the corresponding + * pin + * \param[in] level true = Pin levels set to "high" state + * false = Pin levels set to "low" state + */ +static inline void gpio_set_port_level(const enum gpio_port port, const uint32_t mask, const bool level) +{ + _gpio_set_level(port, mask, level); +} + +/** + * \brief Set gpio level + * + * Sets output level on a pin + * + * \param[in] pin The pin number for device + * \param[in] level true = Pin level set to "high" state + * false = Pin level set to "low" state + */ +static inline void gpio_set_pin_level(const uint8_t pin, const bool level) +{ + _gpio_set_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), level); +} + +/** + * \brief Toggle out level on pins + * + * Toggle the pin levels on pins defined by bit mask + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means toggle pin level to the corresponding + * pin + */ +static inline void gpio_toggle_port_level(const enum gpio_port port, const uint32_t mask) +{ + _gpio_toggle_level(port, mask); +} + +/** + * \brief Toggle output level on pin + * + * Toggle the pin levels on pins defined by bit mask + * + * \param[in] pin The pin number for device + */ +static inline void gpio_toggle_pin_level(const uint8_t pin) +{ + _gpio_toggle_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin)); +} + +/** + * \brief Get input level on pins + * + * Read the input level on pins connected to a port + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + */ +static inline uint32_t gpio_get_port_level(const enum gpio_port port) +{ + return _gpio_get_level(port); +} + +/** + * \brief Get level on pin + * + * Reads the level on pins connected to a port + * + * \param[in] pin The pin number for device + */ +static inline bool gpio_get_pin_level(const uint8_t pin) +{ + return (bool)(_gpio_get_level((enum gpio_port)GPIO_PORT(pin)) & (0x01U << GPIO_PIN(pin))); +} +/** + * \brief Get current driver version + */ +uint32_t gpio_get_version(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hal_i2c_m_sync.h b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hal_i2c_m_sync.h new file mode 100644 index 00000000..24afd639 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hal_i2c_m_sync.h @@ -0,0 +1,244 @@ +/** + * \file + * + * \brief Sync I2C Hardware Abstraction Layer(HAL) declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_I2C_M_SYNC_H_INCLUDED +#define _HAL_I2C_M_SYNC_H_INCLUDED + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_i2c_master_sync + * + * @{ + */ + +#define I2C_M_MAX_RETRY 1 + +/** + * \brief I2C descriptor structure, embed i2c_device & i2c_interface + */ +struct i2c_m_sync_desc { + struct _i2c_m_sync_device device; + struct io_descriptor io; + uint16_t slave_addr; +}; + +/** + * \brief Initialize synchronous I2C interface + * + * This function initializes the given I/O descriptor to be used as a + * synchronous I2C interface descriptor. + * It checks if the given hardware is not initialized and if the given hardware + * is permitted to be initialized. + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status. + * \retval -1 The passed parameters were invalid or the interface is already initialized + * \retval 0 The initialization is completed successfully + */ +int32_t i2c_m_sync_init(struct i2c_m_sync_desc *i2c, void *hw); + +/** + * \brief Deinitialize I2C interface + * + * This function deinitializes the given I/O descriptor. + * It checks if the given hardware is initialized and if the given hardware is permitted to be deinitialized. + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * + * \return Uninitialization status. + * \retval -1 The passed parameters were invalid or the interface is already deinitialized + * \retval 0 The de-initialization is completed successfully + */ +int32_t i2c_m_sync_deinit(struct i2c_m_sync_desc *i2c); + +/** + * \brief Set the slave device address + * + * This function sets the next transfer target slave I2C device address. + * It takes no effect to any already started access. + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * \param[in] addr The slave address to access + * \param[in] addr_len The slave address length, can be I2C_M_TEN or I2C_M_SEVEN + * + * \return Masked slave address. The mask is a maximum 10-bit address, and 10th + * bit is set if a 10-bit address is used + */ +int32_t i2c_m_sync_set_slaveaddr(struct i2c_m_sync_desc *i2c, int16_t addr, int32_t addr_len); + +/** + * \brief Set baudrate + * + * This function sets the I2C device to the specified baudrate. + * It only takes effect when the hardware is disabled. + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * \param[in] clkrate Unused parameter. Should always be 0 + * \param[in] baudrate The baudrate value set to master + * + * \return Whether successfully set the baudrate + * \retval -1 The passed parameters were invalid or the device is already enabled + * \retval 0 The baudrate set is completed successfully + */ +int32_t i2c_m_sync_set_baudrate(struct i2c_m_sync_desc *i2c, uint32_t clkrate, uint32_t baudrate); + +/** + * \brief Sync version of enable hardware + * + * This function enables the I2C device, and then waits for this enabling operation to be done + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * + * \return Whether successfully enable the device + * \retval -1 The passed parameters were invalid or the device enable failed + * \retval 0 The hardware enabling is completed successfully + */ +int32_t i2c_m_sync_enable(struct i2c_m_sync_desc *i2c); + +/** + * \brief Sync version of disable hardware + * + * This function disables the I2C device and then waits for this disabling operation to be done + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * + * \return Whether successfully disable the device + * \retval -1 The passed parameters were invalid or the device disable failed + * \retval 0 The hardware disabling is completed successfully + */ +int32_t i2c_m_sync_disable(struct i2c_m_sync_desc *i2c); + +/** + * \brief Sync version of write command to I2C slave + * + * This function will write the value to a specified register in the I2C slave device and + * then wait for this operation to be done. + * + * The sequence of this routine is + * sta->address(write)->ack->reg address->ack->resta->address(write)->ack->reg value->nack->stt + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * \param[in] reg The internal address/register of the I2C slave device + * \param[in] buffer The buffer holding data to write to the I2C slave device + * \param[in] length The length (in bytes) to write to the I2C slave device + * + * \return Whether successfully write to the device + * \retval <0 The passed parameters were invalid or write fail + * \retval 0 Writing to register is completed successfully + */ +int32_t i2c_m_sync_cmd_write(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length); + +/** + * \brief Sync version of read register value from I2C slave + * + * This function will read a byte value from a specified register in the I2C slave device and + * then wait for this operation to be done. + * + * The sequence of this routine is + * sta->address(write)->ack->reg address->ack->resta->address(read)->ack->reg value->nack->stt + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * \param[in] reg The internal address/register of the I2C slave device + * \param[in] buffer The buffer to hold the read data from the I2C slave device + * \param[in] length The length (in bytes) to read from the I2C slave device + * + * \return Whether successfully read from the device + * \retval <0 The passed parameters were invalid or read fail + * \retval 0 Reading from register is completed successfully + */ +int32_t i2c_m_sync_cmd_read(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length); + +/** + * \brief Sync version of transfer message to/from the I2C slave + * + * This function will transfer a message between the I2C slave and the master. This function will wait for the operation + * to be done. + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * \param[in] msg An i2c_m_msg struct + * + * \return The status of the operation + * \retval 0 Operation completed successfully + * \retval <0 Operation failed + */ +int32_t i2c_m_sync_transfer(struct i2c_m_sync_desc *const i2c, struct _i2c_m_msg *msg); + +/** + * \brief Sync version of send stop condition on the i2c bus + * + * This function will create a stop condition on the i2c bus to release the bus + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * + * \return The status of the operation + * \retval 0 Operation completed successfully + * \retval <0 Operation failed + */ +int32_t i2c_m_sync_send_stop(struct i2c_m_sync_desc *const i2c); + +/** + * \brief Return I/O descriptor for this I2C instance + * + * This function will return a I/O instance for this I2C driver instance + * + * \param[in] i2c_m_sync_desc An I2C descriptor, which is used to communicate through I2C + * \param[in] io_descriptor A pointer to an I/O descriptor pointer type + * + * \return Error code + * \retval 0 No error detected + * \retval <0 Error code + */ +int32_t i2c_m_sync_get_io_descriptor(struct i2c_m_sync_desc *const i2c, struct io_descriptor **io); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t i2c_m_sync_get_version(void); + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hal_init.h b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hal_init.h new file mode 100644 index 00000000..d7bc6fe2 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hal_init.h @@ -0,0 +1,72 @@ +/** + * \file + * + * \brief HAL initialization related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_INIT_H_INCLUDED +#define _HAL_INIT_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_helper_init Init Driver + * + *@{ + */ + +/** + * \brief Initialize the hardware abstraction layer + * + * This function calls the various initialization functions. + * Currently the following initialization functions are supported: + * - System clock initialization + */ +static inline void init_mcu(void) +{ + _init_chip(); +} + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t init_get_version(void); + +/**@}*/ +#ifdef __cplusplus +} +#endif +#endif /* _HAL_INIT_H_INCLUDED */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hal_io.h b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hal_io.h new file mode 100644 index 00000000..f50401d7 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hal_io.h @@ -0,0 +1,110 @@ +/** + * \file + * + * \brief I/O related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_IO_INCLUDED +#define _HAL_IO_INCLUDED + +/** + * \addtogroup doc_driver_hal_helper_io I/O Driver + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief I/O descriptor + * + * The I/O descriptor forward declaration. + */ +struct io_descriptor; + +/** + * \brief I/O write function pointer type + */ +typedef int32_t (*io_write_t)(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); + +/** + * \brief I/O read function pointer type + */ +typedef int32_t (*io_read_t)(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); + +/** + * \brief I/O descriptor + */ +struct io_descriptor { + io_write_t write; /*! The write function pointer. */ + io_read_t read; /*! The read function pointer. */ +}; + +/** + * \brief I/O write interface + * + * This function writes up to \p length of bytes to a given I/O descriptor. + * It returns the number of bytes actually write. + * + * \param[in] descr An I/O descriptor to write + * \param[in] buf The buffer pointer to story the write data + * \param[in] length The number of bytes to write + * + * \return The number of bytes written + */ +int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); + +/** + * \brief I/O read interface + * + * This function reads up to \p length bytes from a given I/O descriptor, and + * stores it in the buffer pointed to by \p buf. It returns the number of bytes + * actually read. + * + * \param[in] descr An I/O descriptor to read + * \param[in] buf The buffer pointer to story the read data + * \param[in] length The number of bytes to read + * + * \return The number of bytes actually read. This number can be less than the + * requested length. E.g., in a driver that uses ring buffer for + * reception, it may depend on the availability of data in the + * ring buffer. + */ +int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HAL_IO_INCLUDED */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hal_sleep.h b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hal_sleep.h new file mode 100644 index 00000000..b90ef6a5 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hal_sleep.h @@ -0,0 +1,74 @@ +/** + * \file + * + * \brief Sleep related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_SLEEP_H_INCLUDED +#define _HAL_SLEEP_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_helper_sleep + * + *@{ + */ + +/** + * \brief Set the sleep mode of the device and put the MCU to sleep + * + * For an overview of which systems are disabled in sleep for the different + * sleep modes, see the data sheet. + * + * \param[in] mode Sleep mode to use + * + * \return The status of a sleep request + * \retval -1 The requested sleep mode was invalid or not available + * \retval 0 The operation completed successfully, returned after leaving the + * sleep + */ +int sleep(const uint8_t mode); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t sleep_get_version(void); +/**@}*/ +#ifdef __cplusplus +} +#endif +#endif /* _HAL_SLEEP_H_INCLUDED */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hal_usart_sync.h b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hal_usart_sync.h new file mode 100644 index 00000000..1ef22fc6 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hal_usart_sync.h @@ -0,0 +1,247 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_SYNC_USART_H_INCLUDED +#define _HAL_SYNC_USART_H_INCLUDED + +#include "hal_io.h" +#include + +/** + * \addtogroup doc_driver_hal_usart_sync + * + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Synchronous USART descriptor + */ +struct usart_sync_descriptor { + struct io_descriptor io; + struct _usart_sync_device device; +}; + +/** + * \brief Initialize USART interface + * + * This function initializes the given I/O descriptor to be used + * as USART interface descriptor. + * It checks if the given hardware is not initialized and + * if the given hardware is permitted to be initialized. + * + * \param[out] descr A USART descriptor which is used to communicate via USART + * \param[in] hw The pointer to hardware instance + * \param[in] func The pointer to as set of functions pointers + * + * \return Initialization status. + */ +int32_t usart_sync_init(struct usart_sync_descriptor *const descr, void *const hw, void *const func); + +/** + * \brief Deinitialize USART interface + * + * This function deinitializes the given I/O descriptor. + * It checks if the given hardware is initialized and + * if the given hardware is permitted to be deinitialized. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return De-initialization status. + */ +int32_t usart_sync_deinit(struct usart_sync_descriptor *const descr); + +/** + * \brief Enable USART interface + * + * Enables the USART interface + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return Enabling status. + */ +int32_t usart_sync_enable(struct usart_sync_descriptor *const descr); + +/** + * \brief Disable USART interface + * + * Disables the USART interface + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return Disabling status. + */ +int32_t usart_sync_disable(struct usart_sync_descriptor *const descr); + +/** + * \brief Retrieve I/O descriptor + * + * This function retrieves the I/O descriptor of the given USART descriptor. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[out] io An I/O descriptor to retrieve + * + * \return The status of the I/O descriptor retrieving. + */ +int32_t usart_sync_get_io_descriptor(struct usart_sync_descriptor *const descr, struct io_descriptor **io); + +/** + * \brief Specify action for flow control pins + * + * This function sets the action (or state) for the flow control pins + * if the flow control is enabled. + * It sets the state of flow control pins only if the automatic support of + * the flow control is not supported by the hardware. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] state A state to set the flow control pins + * + * \return The status of flow control action setup. + */ +int32_t usart_sync_set_flow_control(struct usart_sync_descriptor *const descr, + const union usart_flow_control_state state); + +/** + * \brief Set USART baud rate + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] baud_rate A baud rate to set + * + * \return The status of baud rate setting. + */ +int32_t usart_sync_set_baud_rate(struct usart_sync_descriptor *const descr, const uint32_t baud_rate); + +/** + * \brief Set USART data order + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] data_order A data order to set + * + * \return The status of data order setting. + */ +int32_t usart_sync_set_data_order(struct usart_sync_descriptor *const descr, const enum usart_data_order data_order); + +/** + * \brief Set USART mode + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] mode A mode to set + * + * \return The status of mode setting. + */ +int32_t usart_sync_set_mode(struct usart_sync_descriptor *const descr, const enum usart_mode mode); + +/** + * \brief Set USART parity + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] parity A parity to set + * + * \return The status of parity setting. + */ +int32_t usart_sync_set_parity(struct usart_sync_descriptor *const descr, const enum usart_parity parity); + +/** + * \brief Set USART stop bits + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] stop_bits Stop bits to set + * + * \return The status of stop bits setting. + */ +int32_t usart_sync_set_stopbits(struct usart_sync_descriptor *const descr, const enum usart_stop_bits stop_bits); + +/** + * \brief Set USART character size + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] size A character size to set + * + * \return The status of character size setting. + */ +int32_t usart_sync_set_character_size(struct usart_sync_descriptor *const descr, const enum usart_character_size size); + +/** + * \brief Retrieve the state of flow control pins + * + * This function retrieves the of flow control pins + * if the flow control is enabled. + * Function can return USART_FLOW_CONTROL_STATE_UNAVAILABLE in case + * if the flow control is done by the hardware + * and the pins state cannot be read out. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[out] state The state of flow control pins + * + * \return The status of flow control state reading. + */ +int32_t usart_sync_flow_control_status(const struct usart_sync_descriptor *const descr, + union usart_flow_control_state *const state); + +/** + * \brief Check if the USART transmitter is empty + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return The status of USART TX empty checking. + * \retval 0 The USART transmitter is not empty + * \retval 1 The USART transmitter is empty + */ +int32_t usart_sync_is_tx_empty(const struct usart_sync_descriptor *const descr); + +/** + * \brief Check if the USART receiver is not empty + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return The status of USART RX empty checking. + * \retval 1 The USART receiver is not empty + * \retval 0 The USART receiver is empty + */ +int32_t usart_sync_is_rx_not_empty(const struct usart_sync_descriptor *const descr); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t usart_sync_get_version(void); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HAL_SYNC_USART_H_INCLUDED */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_core.h b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_core.h new file mode 100644 index 00000000..9324c43e --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_core.h @@ -0,0 +1,56 @@ +/** + * \file + * + * \brief CPU core related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_CORE_H_INCLUDED +#define _HPL_CORE_H_INCLUDED + +/** + * \addtogroup HPL Core + * + * \section hpl_core_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include "hpl_core_port.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_CORE_H_INCLUDED */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_delay.h b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_delay.h new file mode 100644 index 00000000..a0f1ac81 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_delay.h @@ -0,0 +1,97 @@ +/** + * \file + * + * \brief Delay related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_DELAY_H_INCLUDED +#define _HPL_DELAY_H_INCLUDED + +/** + * \addtogroup HPL Delay + * + * \section hpl_delay_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifndef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name HPL functions + */ +//@{ + +/** + * \brief Initialize delay functionality + * + * \param[in] hw The pointer to hardware instance + */ +void _delay_init(void *const hw); + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of us + * + * \param[in] us The amount of us to delay for + * + * \return The amount of cycles + */ +uint32_t _get_cycles_for_us(const uint16_t us); + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of ms + * + * \param[in] ms The amount of ms to delay for + * + * \return The amount of cycles + */ +uint32_t _get_cycles_for_ms(const uint16_t ms); + +/** + * \brief Delay loop to delay n number of cycles + * + * \param[in] hw The pointer to hardware instance + * \param[in] cycles The amount of cycles to delay for + */ +void _delay_cycles(void *const hw, uint32_t cycles); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_DELAY_H_INCLUDED */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_dma.h b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_dma.h new file mode 100644 index 00000000..1e08434a --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_dma.h @@ -0,0 +1,176 @@ +/** + * \file + * + * \brief DMA related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_DMA_H_INCLUDED +#define _HPL_DMA_H_INCLUDED + +/** + * \addtogroup HPL DMA + * + * \section hpl_dma_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct _dma_resource; + +/** + * \brief DMA callback types + */ +enum _dma_callback_type { DMA_TRANSFER_COMPLETE_CB, DMA_TRANSFER_ERROR_CB }; + +/** + * \brief DMA interrupt callbacks + */ +struct _dma_callbacks { + void (*transfer_done)(struct _dma_resource *resource); + void (*error)(struct _dma_resource *resource); +}; + +/** + * \brief DMA resource structure + */ +struct _dma_resource { + struct _dma_callbacks dma_cb; + void * back; +}; + +/** + * \brief Initialize DMA + * + * This function does low level DMA configuration. + * + * \return initialize status + */ +int32_t _dma_init(void); + +/** + * \brief Set destination address + * + * \param[in] channel DMA channel to set destination address for + * \param[in] dst Destination address + * + * \return setting status + */ +int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst); + +/** + * \brief Set source address + * + * \param[in] channel DMA channel to set source address for + * \param[in] src Source address + * + * \return setting status + */ +int32_t _dma_set_source_address(const uint8_t channel, const void *const src); + +/** + * \brief Set next descriptor address + * + * \param[in] current_channel Current DMA channel to set next descriptor address + * \param[in] next_channel Next DMA channel used as next descriptor + * + * \return setting status + */ +int32_t _dma_set_next_descriptor(const uint8_t current_channel, const uint8_t next_channel); + +/** + * \brief Enable/disable source address incrementation during DMA transaction + * + * \param[in] channel DMA channel to set source address for + * \param[in] enable True to enable, false to disable + * + * \return status of operation + */ +int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable); + +/** + * \brief Enable/disable Destination address incrementation during DMA transaction + * + * \param[in] channel DMA channel to set destination address for + * \param[in] enable True to enable, false to disable + * + * \return status of operation + */ +int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable); +/** + * \brief Set the amount of data to be transfered per transaction + * + * \param[in] channel DMA channel to set data amount for + * \param[in] amount Data amount + * + * \return status of operation + */ +int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount); + +/** + * \brief Trigger DMA transaction on the given channel + * + * \param[in] channel DMA channel to trigger transaction on + * + * \return status of operation + */ +int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger); + +/** + * \brief Retrieves DMA resource structure + * + * \param[out] resource The resource to be retrieved + * \param[in] channel DMA channel to retrieve structure for + * + * \return status of operation + */ +int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel); + +/** + * \brief Enable/disable DMA interrupt + * + * \param[in] channel DMA channel to enable/disable interrupt for + * \param[in] type The type of interrupt to disable/enable if applicable + * \param[in] state Enable or disable + */ +void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state); + +#ifdef __cplusplus +} +#endif + +#endif /* HPL_DMA_H_INCLUDED */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_gpio.h b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_gpio.h new file mode 100644 index 00000000..5cdd387b --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_gpio.h @@ -0,0 +1,185 @@ +/** + * \file + * + * \brief Port related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_GPIO_H_INCLUDED +#define _HPL_GPIO_H_INCLUDED + +/** + * \addtogroup HPL Port + * + * \section hpl_port_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif +/** + * \brief Macros for the pin and port group, lower 5 + * bits stands for pin number in the group, higher 3 + * bits stands for port group + */ +#define GPIO_PIN(n) (((n)&0x1Fu) << 0) +#define GPIO_PORT(n) ((n) >> 5) +#define GPIO(port, pin) ((((port)&0x7u) << 5) + ((pin)&0x1Fu)) +#define GPIO_PIN_FUNCTION_OFF 0xffffffff + +/** + * \brief PORT pull mode settings + */ +enum gpio_pull_mode { GPIO_PULL_OFF, GPIO_PULL_UP, GPIO_PULL_DOWN }; + +/** + * \brief PORT direction settins + */ +enum gpio_direction { GPIO_DIRECTION_OFF, GPIO_DIRECTION_IN, GPIO_DIRECTION_OUT }; + +/** + * \brief PORT group abstraction + */ + +enum gpio_port { GPIO_PORTA, GPIO_PORTB, GPIO_PORTC, GPIO_PORTD, GPIO_PORTE }; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Port initialization function + * + * Port initialization function should setup the port module based + * on a static configuration file, this function should normally + * not be called directly, but is a part of hal_init() + */ +void _gpio_init(void); + +/** + * \brief Set direction on port with mask + * + * Set data direction for each pin, or disable the pin + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to the + * corresponding pin + * \param[in] direction GPIO_DIRECTION_OFF = set pin direction to input + * and disable input buffer to disable the pin + * GPIO_DIRECTION_IN = set pin direction to input + * and enable input buffer to enable the pin + * GPIO_DIRECTION_OUT = set pin direction to output + * and disable input buffer + */ +static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask, + const enum gpio_direction direction); + +/** + * \brief Set output level on port with mask + * + * Sets output state on pin to high or low with pin masking + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to + * the corresponding pin + * \param[in] level true = pin level is set to 1 + * false = pin level is set to 0 + */ +static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level); + +/** + * \brief Change output level to the opposite with mask + * + * Change pin output level to the opposite with pin masking + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to + * the corresponding pin + */ +static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask); + +/** + * \brief Get input levels on all port pins + * + * Get input level on all port pins, will read IN register if configured to + * input and OUT register if configured as output + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + */ +static inline uint32_t _gpio_get_level(const enum gpio_port port); + +/** + * \brief Set pin pull mode + * + * Set pull mode on a single pin + * + * \notice This function will automatically change pin direction to input + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] pin The pin in the group that pull mode should be selected + * for + * \param[in] pull_mode GPIO_PULL_OFF = pull resistor on pin is disabled + * GPIO_PULL_DOWN = pull resistor on pin will pull pin + * level to ground level + * GPIO_PULL_UP = pull resistor on pin will pull pin + * level to VCC + */ +static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin, + const enum gpio_pull_mode pull_mode); + +/** + * \brief Set gpio function + * + * Select which function a gpio is used for + * + * \param[in] gpio The gpio to set function for + * \param[in] function The gpio function is given by a 32-bit wide bitfield + * found in the header files for the device + * + */ +static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function); + +#include +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_GPIO_H_INCLUDED */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_i2c_m_async.h b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_i2c_m_async.h new file mode 100644 index 00000000..8a9491de --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_i2c_m_async.h @@ -0,0 +1,205 @@ +/** + * \file + * + * \brief I2C Master Hardware Proxy Layer(HPL) declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_M_ASYNC_H_INCLUDED +#define _HPL_I2C_M_ASYNC_H_INCLUDED + +#include "hpl_i2c_m_sync.h" +#include "hpl_irq.h" +#include "utils.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief i2c master callback names + */ +enum _i2c_m_async_callback_type { + I2C_M_ASYNC_DEVICE_ERROR, + I2C_M_ASYNC_DEVICE_TX_COMPLETE, + I2C_M_ASYNC_DEVICE_RX_COMPLETE +}; + +struct _i2c_m_async_device; + +typedef void (*_i2c_complete_cb_t)(struct _i2c_m_async_device *i2c_dev); +typedef void (*_i2c_error_cb_t)(struct _i2c_m_async_device *i2c_dev, int32_t errcode); + +/** + * \brief i2c callback pointers structure + */ +struct _i2c_m_async_callback { + _i2c_error_cb_t error; + _i2c_complete_cb_t tx_complete; + _i2c_complete_cb_t rx_complete; +}; + +/** + * \brief i2c device structure + */ +struct _i2c_m_async_device { + struct _i2c_m_service service; + void * hw; + struct _i2c_m_async_callback cb; + struct _irq_descriptor irq; +}; + +/** + * \name HPL functions + */ + +/** + * \brief Initialize I2C in interrupt mode + * + * This function does low level I2C configuration. + * + * \param[in] i2c_dev The pointer to i2c interrupt device structure + * \param[in] hw The pointer to hardware instance + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw); + +/** + * \brief Deinitialize I2C in interrupt mode + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Transfer data by I2C + * + * This function does low level I2C data transfer. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] msg The pointer to i2c msg structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *const i2c_dev, struct _i2c_m_msg *msg); + +/** + * \brief Set baud rate of I2C + * + * This function does low level I2C set baud rate. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] clkrate The clock rate(KHz) input to i2c module + * \param[in] baudrate The demand baud rate(KHz) of i2c module + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate); + +/** + * \brief Register callback to I2C + * + * This function does low level I2C callback register. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] cb_type The callback type request + * \param[in] func The callback function pointer + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *i2c_dev, enum _i2c_m_async_callback_type cb_type, + FUNC_PTR func); + +/** + * \brief Generate stop condition on the I2C bus + * + * This function will generate a stop condition on the I2C bus + * + * \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C + * + * \return Operation status + * \retval 0 Operation executed successfully + * \retval <0 Operation failed + */ +int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Returns the number of bytes left or not used in the I2C message buffer + * + * This function will return the number of bytes left (not written to the bus) or still free + * (not received from the bus) in the message buffer, depending on direction of transmission. + * + * \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C + * + * \return Number of bytes or error code + * \retval >0 Positive number indicating bytes left + * \retval 0 Buffer is full/empty depending on direction + * \retval <0 Error code + */ +int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Enable/disable I2C master interrupt + * + * param[in] device The pointer to I2C master device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type, + const bool state); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_i2c_m_sync.h b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_i2c_m_sync.h new file mode 100644 index 00000000..ce173ae2 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_i2c_m_sync.h @@ -0,0 +1,185 @@ +/** + * \file + * + * \brief I2C Master Hardware Proxy Layer(HPL) declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_M_SYNC_H_INCLUDED +#define _HPL_I2C_M_SYNC_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief i2c flags + */ +#define I2C_M_RD 0x0001 /* read data, from slave to master */ +#define I2C_M_BUSY 0x0100 +#define I2C_M_TEN 0x0400 /* this is a ten bit chip address */ +#define I2C_M_SEVEN 0x0800 /* this is a seven bit chip address */ +#define I2C_M_FAIL 0x1000 +#define I2C_M_STOP 0x8000 /* if I2C_FUNC_PROTOCOL_MANGLING */ + +/** + * \brief i2c Return codes + */ +#define I2C_OK 0 /* Operation successful */ +#define I2C_ACK -1 /* Received ACK from device on I2C bus */ +#define I2C_NACK -2 /* Received NACK from device on I2C bus */ +#define I2C_ERR_ARBLOST -3 /* Arbitration lost */ +#define I2C_ERR_BAD_ADDRESS -4 /* Bad address */ +#define I2C_ERR_BUS -5 /* Bus error */ +#define I2C_ERR_BUSY -6 /* Device busy */ +#define I2c_ERR_PACKAGE_COLLISION -7 /* Package collision */ + +/** + * \brief i2c I2C Modes + */ +#define I2C_STANDARD_MODE 0x00 +#define I2C_FASTMODE 0x01 +#define I2C_HIGHSPEED_MODE 0x02 + +/** + * \brief i2c master message structure + */ +struct _i2c_m_msg { + uint16_t addr; + volatile uint16_t flags; + int32_t len; + uint8_t * buffer; +}; + +/** + * \brief i2c master service + */ +struct _i2c_m_service { + struct _i2c_m_msg msg; + uint16_t mode; + uint16_t trise; +}; + +/** + * \brief i2c sync master device structure + */ +struct _i2c_m_sync_device { + struct _i2c_m_service service; + void * hw; +}; + +/** + * \name HPL functions + */ + +/** + * \brief Initialize I2C + * + * This function does low level I2C configuration. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] hw The pointer to hardware instance + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw); + +/** + * \brief Deinitialize I2C + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev); + +/** + * \brief Transfer data by I2C + * + * This function does low level I2C data transfer. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] msg The pointer to i2c msg structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg); + +/** + * \brief Set baud rate of I2C + * + * This function does low level I2C set baud rate. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] clkrate The clock rate(KHz) input to i2c module + * \param[in] baudrate The demand baud rate(KHz) of i2c module + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate); + +/** + * \brief Send send condition on the I2C bus + * + * This function will generate a stop condition on the I2C bus + * + * \param[in] i2c_dev The pointer to i2c device struct + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_i2c_s_async.h b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_i2c_s_async.h new file mode 100644 index 00000000..92a5765d --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_i2c_s_async.h @@ -0,0 +1,184 @@ +/** + * \file + * + * \brief I2C Slave Hardware Proxy Layer(HPL) declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_S_ASYNC_H_INCLUDED +#define _HPL_I2C_S_ASYNC_H_INCLUDED + +#include "hpl_i2c_s_sync.h" +#include "hpl_irq.h" +#include "utils.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief i2c callback types + */ +enum _i2c_s_async_callback_type { I2C_S_DEVICE_ERROR, I2C_S_DEVICE_TX, I2C_S_DEVICE_RX_COMPLETE }; + +/** + * \brief Forward declaration of I2C Slave device + */ +struct _i2c_s_async_device; + +/** + * \brief i2c slave callback function type + */ +typedef void (*_i2c_s_async_cb_t)(struct _i2c_s_async_device *device); + +/** + * \brief i2c slave callback pointers structure + */ +struct _i2c_s_async_callback { + void (*error)(struct _i2c_s_async_device *const device); + void (*tx)(struct _i2c_s_async_device *const device); + void (*rx_done)(struct _i2c_s_async_device *const device, const uint8_t data); +}; + +/** + * \brief i2c slave device structure + */ +struct _i2c_s_async_device { + void * hw; + struct _i2c_s_async_callback cb; + struct _irq_descriptor irq; +}; + +/** + * \name HPL functions + */ + +/** + * \brief Initialize asynchronous I2C slave + * + * This function does low level I2C configuration. + * + * \param[in] device The pointer to i2c interrupt device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw); + +/** + * \brief Deinitialize asynchronous I2C in interrupt mode + * + * \param[in] device The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device); + +/** + * \brief Check if 10-bit addressing mode is on + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Cheking status + * \retval 1 10-bit addressing mode is on + * \retval 0 10-bit addressing mode is off + */ +int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device); + +/** + * \brief Set I2C slave address + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] address Address to set + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address); + +/** + * \brief Write a byte to the given I2C instance + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] data Data to write + */ +void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data); + +/** + * \brief Retrieve I2C slave status + * + * \param[in] device The pointer to i2c slave device structure + * + *\return I2C slave status + */ +i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device); + +/** + * \brief Abort data transmission + * + * \param[in] device The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device); + +/** + * \brief Enable/disable I2C slave interrupt + * + * param[in] device The pointer to I2C slave device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] disable Enable or disable + */ +int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type, + const bool disable); + +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_I2C_S_ASYNC_H_INCLUDED */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_i2c_s_sync.h b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_i2c_s_sync.h new file mode 100644 index 00000000..93b59345 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_i2c_s_sync.h @@ -0,0 +1,184 @@ +/** + * \file + * + * \brief I2C Slave Hardware Proxy Layer(HPL) declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_S_SYNC_H_INCLUDED +#define _HPL_I2C_S_SYNC_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief I2C Slave status type + */ +typedef uint32_t i2c_s_status_t; + +/** + * \brief i2c slave device structure + */ +struct _i2c_s_sync_device { + void *hw; +}; + +#include + +/** + * \name HPL functions + */ + +/** + * \brief Initialize synchronous I2C slave + * + * This function does low level I2C configuration. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw); + +/** + * \brief Deinitialize synchronous I2C slave + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device); + +/** + * \brief Check if 10-bit addressing mode is on + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Cheking status + * \retval 1 10-bit addressing mode is on + * \retval 0 10-bit addressing mode is off + */ +int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device); + +/** + * \brief Set I2C slave address + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] address Address to set + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address); + +/** + * \brief Write a byte to the given I2C instance + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] data Data to write + */ +void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data); + +/** + * \brief Retrieve I2C slave status + * + * \param[in] device The pointer to i2c slave device structure + * + *\return I2C slave status + */ +i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device); + +/** + * \brief Clear the Data Ready interrupt flag + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_clear_data_ready_flag(const struct _i2c_s_sync_device *const device); + +/** + * \brief Read a byte from the given I2C instance + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Data received via I2C interface. + */ +uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device); + +/** + * \brief Check if I2C is ready to send next byte + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Status of the ready check. + * \retval true if the I2C is ready to send next byte + * \retval false if the I2C is not ready to send next byte + */ +bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device); + +/** + * \brief Check if there is data received by I2C + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Status of the data received check. + * \retval true if the I2C has received a byte + * \retval false if the I2C has not received a byte + */ +bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device); + +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_I2C_S_SYNC_H_INCLUDED */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_init.h b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_init.h new file mode 100644 index 00000000..71bf49c9 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_init.h @@ -0,0 +1,124 @@ +/** + * \file + * + * \brief Init related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_INIT_H_INCLUDED +#define _HPL_INIT_H_INCLUDED + +/** + * \addtogroup HPL Init + * + * \section hpl_init_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initializes clock sources + */ +void _sysctrl_init_sources(void); + +/** + * \brief Initializes Power Manager + */ +void _pm_init(void); + +/** + * \brief Initialize generators + */ +void _gclk_init_generators(void); + +/** + * \brief Initialize 32 kHz clock sources + */ +void _osc32kctrl_init_sources(void); + +/** + * \brief Initialize clock sources + */ +void _oscctrl_init_sources(void); + +/** + * \brief Initialize clock sources that need input reference clocks + */ +void _sysctrl_init_referenced_generators(void); + +/** + * \brief Initialize clock sources that need input reference clocks + */ +void _oscctrl_init_referenced_generators(void); + +/** + * \brief Initialize master clock generator + */ +void _mclk_init(void); + +/** + * \brief Initialize clock generator + */ +void _lpmcu_misc_regs_init(void); + +/** + * \brief Initialize clock generator + */ +void _pmc_init(void); + +/** + * \brief Set performance level + * + * \param[in] level The performance level to set + */ +void _set_performance_level(const uint8_t level); + +/** + * \brief Initialize the chip + */ +void _init_chip(void); + +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_INIT_H_INCLUDED */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_irq.h b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_irq.h new file mode 100644 index 00000000..2894944a --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_irq.h @@ -0,0 +1,116 @@ +/** + * \file + * + * \brief IRQ related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_IRQ_H_INCLUDED +#define _HPL_IRQ_H_INCLUDED + +/** + * \addtogroup HPL IRQ + * + * \section hpl_irq_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief IRQ descriptor + */ +struct _irq_descriptor { + void (*handler)(void *parameter); + void *parameter; +}; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Retrieve current IRQ number + * + * \return The current IRQ number + */ +uint8_t _irq_get_current(void); + +/** + * \brief Disable the given IRQ + * + * \param[in] n The number of IRQ to disable + */ +void _irq_disable(uint8_t n); + +/** + * \brief Set the given IRQ + * + * \param[in] n The number of IRQ to set + */ +void _irq_set(uint8_t n); + +/** + * \brief Clear the given IRQ + * + * \param[in] n The number of IRQ to clear + */ +void _irq_clear(uint8_t n); + +/** + * \brief Enable the given IRQ + * + * \param[in] n The number of IRQ to enable + */ +void _irq_enable(uint8_t n); + +/** + * \brief Register IRQ handler + * + * \param[in] number The number registered IRQ + * \param[in] irq The pointer to irq handler to register + * + * \return The status of IRQ handler registering + * \retval -1 Passed parameters were invalid + * \retval 0 The registering is completed successfully + */ +void _irq_register(const uint8_t number, struct _irq_descriptor *const irq); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_IRQ_H_INCLUDED */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_missing_features.h b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_missing_features.h new file mode 100644 index 00000000..7071db29 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_missing_features.h @@ -0,0 +1,37 @@ +/** + * \file + * + * \brief Family-dependent missing features expected by HAL + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_MISSING_FEATURES +#define _HPL_MISSING_FEATURES + +#endif /* _HPL_MISSING_FEATURES */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_reset.h b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_reset.h new file mode 100644 index 00000000..75738b6f --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_reset.h @@ -0,0 +1,92 @@ +/** + * \file + * + * \brief Reset related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_RESET_H_INCLUDED +#define _HPL_RESET_H_INCLUDED + +/** + * \addtogroup HPL Reset + * + * \section hpl_reset_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifndef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Reset reason enumeration + * + * The list of possible reset reasons. + */ +enum reset_reason { + RESET_REASON_POR = 1, + RESET_REASON_BOD12 = 2, + RESET_REASON_BOD33 = 4, + RESET_REASON_EXT = 16, + RESET_REASON_WDT = 32, + RESET_REASON_SYST = 64, + RESET_REASON_BACKUP = 128 +}; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Retrieve the reset reason + * + * Retrieves the reset reason of the last MCU reset. + * + *\return An enum value indicating the reason of the last reset. + */ +enum reset_reason _get_reset_reason(void); + +/** + * \brief Reset MCU + */ +void _reset_mcu(void); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_RESET_H_INCLUDED */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_sleep.h b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_sleep.h new file mode 100644 index 00000000..6731ec30 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_sleep.h @@ -0,0 +1,88 @@ +/** + * \file + * + * \brief Sleep related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SLEEP_H_INCLUDED +#define _HPL_SLEEP_H_INCLUDED + +/** + * \addtogroup HPL Sleep + * + * \section hpl_sleep_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifndef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Set the sleep mode for the device + * + * This function sets the sleep mode for the device. + * For an overview of which systems are disabled in sleep for the different + * sleep modes see datasheet. + * + * \param[in] mode Sleep mode to use + * + * \return the status of a sleep request + * \retval -1 The requested sleep mode was invalid + * \retval 0 The operation completed successfully, sleep mode is set + */ +int32_t _set_sleep_mode(const uint8_t mode); + +/** + * \brief Reset MCU + */ +void _reset_mcu(void); + +/** + * \brief Put MCU to sleep + */ +void _go_to_sleep(void); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_SLEEP_H_INCLUDED */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_spi.h b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_spi.h new file mode 100644 index 00000000..a5652e50 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_spi.h @@ -0,0 +1,163 @@ +/** + * \file + * + * \brief SPI related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_H_INCLUDED +#define _HPL_SPI_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief SPI Dummy char is used when reading data from the SPI slave + */ +#define SPI_DUMMY_CHAR 0x1ff + +/** + * \brief SPI message to let driver to process + */ +//@{ +struct spi_msg { + /** Pointer to the output data buffer */ + uint8_t *txbuf; + /** Pointer to the input data buffer */ + uint8_t *rxbuf; + /** Size of the message data in SPI characters */ + uint32_t size; +}; +//@} + +/** + * \brief SPI transfer modes + * SPI transfer mode controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + */ +enum spi_transfer_mode { + /** Leading edge is rising edge, data sample on leading edge. */ + SPI_MODE_0, + /** Leading edge is rising edge, data sample on trailing edge. */ + SPI_MODE_1, + /** Leading edge is falling edge, data sample on leading edge. */ + SPI_MODE_2, + /** Leading edge is falling edge, data sample on trailing edge. */ + SPI_MODE_3 +}; + +/** + * \brief SPI character sizes + * The character size influence the way the data is sent/received. + * For char size <= 8 data is stored byte by byte. + * For char size between 9 ~ 16 data is stored in 2-byte length. + * Note that the default and recommended char size is 8 bit since it's + * supported by all system. + */ +enum spi_char_size { + /** Character size is 8 bit. */ + SPI_CHAR_SIZE_8 = 0, + /** Character size is 9 bit. */ + SPI_CHAR_SIZE_9 = 1, + /** Character size is 10 bit. */ + SPI_CHAR_SIZE_10 = 2, + /** Character size is 11 bit. */ + SPI_CHAR_SIZE_11 = 3, + /** Character size is 12 bit. */ + SPI_CHAR_SIZE_12 = 4, + /** Character size is 13 bit. */ + SPI_CHAR_SIZE_13 = 5, + /** Character size is 14 bit. */ + SPI_CHAR_SIZE_14 = 6, + /** Character size is 15 bit. */ + SPI_CHAR_SIZE_15 = 7, + /** Character size is 16 bit. */ + SPI_CHAR_SIZE_16 = 8 +}; + +/** + * \brief SPI data order + */ +enum spi_data_order { + /** MSB goes first. */ + SPI_DATA_ORDER_MSB_1ST = 0, + /** LSB goes first. */ + SPI_DATA_ORDER_LSB_1ST = 1 +}; + +/** \brief Transfer descriptor for SPI + * Transfer descriptor holds TX and RX buffers + */ +struct spi_xfer { + /** Pointer to data buffer to TX */ + uint8_t *txbuf; + /** Pointer to data buffer to RX */ + uint8_t *rxbuf; + /** Size of data characters to TX & RX */ + uint32_t size; +}; + +/** SPI generic driver. */ +struct spi_dev { + /** Pointer to the hardware base or private data for special device. */ + void *prvt; + /** Reference start of sync/async variables */ + uint32_t sync_async_misc[1]; +}; + +/** + * \brief Calculate the baudrate value for hardware to use to set baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] clk Clock frequency (Hz) for baudrate generation. + * \param[in] baud Target baudrate (bps). + * \return Error or baudrate value. + * \retval >0 Baudrate value. + * \retval ERR_INVALID_ARG Calculation fail. + */ +int32_t _spi_calc_baud_val(struct spi_dev *dev, const uint32_t clk, const uint32_t baud); + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_H_INCLUDED */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_spi_async.h b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_spi_async.h new file mode 100644 index 00000000..8e5a8485 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_spi_async.h @@ -0,0 +1,131 @@ +/** + * \file + * + * \brief Common SPI related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_ASYNC_H_INCLUDED +#define _HPL_SPI_ASYNC_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Callbacks the SPI driver must offer in async mode + */ +//@{ +/** The callback types */ +enum _spi_async_dev_cb_type { + /** Callback type for transmit, see \ref _spi_async_dev_cb_xfer_t. */ + SPI_DEV_CB_TX, + /** Callback type for receive, see \ref _spi_async_dev_cb_xfer_t. */ + SPI_DEV_CB_RX, + /** Callback type for \ref _spi_async_dev_cb_complete_t. */ + SPI_DEV_CB_COMPLETE, + /** Callback type for error */ + SPI_DEV_CB_ERROR, + /** Number of callbacks. */ + SPI_DEV_CB_N +}; + +struct _spi_async_dev; + +/** \brief The prototype for callback on SPI transfer error. + * If status code is zero, it indicates the normal completion, that is, + * SS deactivation. + * If status code belows zero, it indicates complete. + */ +typedef void (*_spi_async_dev_cb_error_t)(struct _spi_async_dev *dev, int32_t status); + +/** \brief The prototype for callback on SPI transmit/receive event + * For TX, the callback is invoked when transmit is done or ready to start + * transmit. + * For RX, the callback is invoked when receive is done or ready to read data, + * see \ref _spi_async_dev_read_one_t on data reading. + * Without DMA enabled, the callback is invoked on each character event. + * With DMA enabled, the callback is invoked on DMA buffer done. + */ +typedef void (*_spi_async_dev_cb_xfer_t)(struct _spi_async_dev *dev); + +/** + * \brief The callbacks offered by SPI driver + */ +struct _spi_async_dev_callbacks { + /** TX callback, see \ref _spi_async_dev_cb_xfer_t. */ + _spi_async_dev_cb_xfer_t tx; + /** RX callback, see \ref _spi_async_dev_cb_xfer_t. */ + _spi_async_dev_cb_xfer_t rx; + /** Complete or complete callback, see \ref _spi_async_dev_cb_complete_t. */ + _spi_async_dev_cb_xfer_t complete; + /** Error callback, see \ref */ + _spi_async_dev_cb_error_t err; +}; +//@} + +/** + * \brief SPI async driver + */ +//@{ + +/** SPI driver to support async HAL */ +struct _spi_async_dev { + /** Pointer to the hardware base or private data for special device. */ + void *prvt; + /** Data size, number of bytes for each character */ + uint8_t char_size; + /** Dummy byte used in master mode when reading the slave */ + uint16_t dummy_byte; + + /** \brief Pointer to callback functions, ignored for polling mode + * Pointer to the callback functions so that initialize the driver to + * handle interrupts. + */ + struct _spi_async_dev_callbacks callbacks; + /** IRQ instance for SPI device. */ + struct _irq_descriptor irq; +}; +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_ASYNC_H_INCLUDED */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_spi_m_async.h b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_spi_m_async.h new file mode 100644 index 00000000..8d3555ed --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_spi_m_async.h @@ -0,0 +1,243 @@ +/** + * \file + * + * \brief SPI Slave Async related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_M_ASYNC_H_INCLUDED +#define _HPL_SPI_M_ASYNC_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI async device driver. */ +#define _spi_m_async_dev _spi_async_dev + +#define _spi_m_async_dev_cb_type _spi_async_dev_cb_type + +/** Uses common SPI async device driver complete callback type. */ +#define _spi_m_async_dev_cb_error_t _spi_async_dev_cb_error_t + +/** Uses common SPI async device driver transfer callback type. */ +#define _spi_m_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access with interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_init(struct _spi_m_async_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_deinit(struct _spi_m_async_dev *dev); + +/** + * \brief Enable SPI for access with interrupts + * Enable the SPI and enable callback generation of receive and error + * interrupts. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_enable(struct _spi_m_async_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI and interrupts. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_disable(struct _spi_m_async_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_mode(struct _spi_m_async_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on + * how it's generated. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_baudrate(struct _spi_m_async_dev *dev, const uint32_t baud_val); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_char_size(struct _spi_m_async_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_data_order(struct _spi_m_async_dev *dev, const enum spi_data_order dord); + +/** + * \brief Enable interrupt on character output + * + * Enable interrupt when a new character can be written + * to the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable output interrupt + * false = disable output interrupt + * + * \return Status code + * \retval 0 Ok status + */ +int32_t _spi_m_async_enable_tx(struct _spi_m_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on character input + * + * Enable interrupt when a new character is ready to be + * read from the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_m_async_enable_rx(struct _spi_m_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on after data transmission complate + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_m_async_enable_tx_complete(struct _spi_m_async_dev *dev, bool state); + +/** + * \brief Read one character to SPI device instance + * \param[in, out] dev Pointer to the SPI device instance. + * + * \return Character read from SPI module + */ +uint16_t _spi_m_async_read_one(struct _spi_m_async_dev *dev); + +/** + * \brief Write one character to assigned buffer + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] data + * + * \return Status code of write operation + * \retval 0 Write operation OK + */ +int32_t _spi_m_async_write_one(struct _spi_m_async_dev *dev, uint16_t data); + +/** + * \brief Register the SPI device callback + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] cb_type The callback type. + * \param[in] func The callback function to register. NULL to disable callback. + * \return Always 0. + */ +int32_t _spi_m_async_register_callback(struct _spi_m_async_dev *dev, const enum _spi_m_async_dev_cb_type cb_type, + const FUNC_PTR func); + +/** + * \brief Enable/disable SPI master interrupt + * + * param[in] device The pointer to SPI master device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _spi_m_async_set_irq_state(struct _spi_m_async_dev *const device, const enum _spi_m_async_dev_cb_type type, + const bool state); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_M_ASYNC_H_INCLUDED */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_spi_m_dma.h b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_spi_m_dma.h new file mode 100644 index 00000000..2b48300e --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_spi_m_dma.h @@ -0,0 +1,182 @@ +/** + * \file + * + * \brief SPI Master DMA related functionality declaration. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_M_DMA_H_INCLUDED +#define _HPL_SPI_M_DMA_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI dma device driver. */ +#define _spi_m_dma_dev _spi_dma_dev + +#define _spi_m_dma_dev_cb_type _spi_dma_dev_cb_type + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access with interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_init(struct _spi_m_dma_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_deinit(struct _spi_m_dma_dev *dev); + +/** + * \brief Enable SPI for access with interrupts + * Enable the SPI and enable callback generation of receive and error + * interrupts. + * \param[in] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_enable(struct _spi_m_dma_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI and interrupts. Deactivate all CS pins if works as master. + * \param[in] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_disable(struct _spi_m_dma_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_set_mode(struct _spi_m_dma_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in] dev Pointer to the SPI device instance. + * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on + * how it's generated. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_dma_set_baudrate(struct _spi_m_dma_dev *dev, const uint32_t baud_val); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_dma_set_char_size(struct _spi_m_dma_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_dma_set_data_order(struct _spi_m_dma_dev *dev, const enum spi_data_order dord); + +/** + * \brief Register the SPI device callback + * \param[in] dev Pointer to the SPI device instance. + * \param[in] cb_type The callback type. + * \param[in] func The callback function to register. NULL to disable callback. + * \return Always 0. + */ +void _spi_m_dma_register_callback(struct _spi_m_dma_dev *dev, enum _spi_dma_dev_cb_type, _spi_dma_cb_t func); + +/** \brief Do SPI data transfer (TX & RX) with DMA + * Log the TX & RX buffers and transfer them in background. It never blocks. + * + * \param[in] dev Pointer to the SPI device instance. + * \param[in] txbuf Pointer to the transfer information (\ref spi_transfer). + * \param[out] rxbuf Pointer to the receiver information (\ref spi_receive). + * \param[in] length spi transfer data length. + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval ERR_BUSY Busy. + */ +int32_t _spi_m_dma_transfer(struct _spi_m_dma_dev *dev, uint8_t const *txbuf, uint8_t *const rxbuf, + const uint16_t length); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_M_DMA_H_INCLUDED */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_spi_m_sync.h b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_spi_m_sync.h new file mode 100644 index 00000000..38df15b4 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_spi_m_sync.h @@ -0,0 +1,166 @@ +/** + * \file + * + * \brief SPI related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_M_SYNC_H_INCLUDED +#define _HPL_SPI_M_SYNC_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI sync device driver. */ +#define _spi_m_sync_dev _spi_sync_dev + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access without interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw); + +/** + * \brief Deinitialize SPI + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_deinit(struct _spi_m_sync_dev *dev); + +/** + * \brief Enable SPI for access without interrupts + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_enable(struct _spi_m_sync_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_disable(struct _spi_m_sync_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_mode(struct _spi_m_sync_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on + * how it's generated. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_baudrate(struct _spi_m_sync_dev *dev, const uint32_t baud_val); + +/** + * \brief Set SPI char size + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_char_size(struct _spi_m_sync_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_data_order(struct _spi_m_sync_dev *dev, const enum spi_data_order dord); + +/** + * \brief Transfer the whole message without interrupt + * Transfer the message, it will keep waiting until the message finish or + * error. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] msg Pointer to the message instance to process. + * \return Error or number of characters transferred. + * \retval ERR_BUSY SPI hardware is not ready to start transfer (not + * enabled, busy applying settings, ...). + * \retval SPI_ERR_OVERFLOW Overflow error. + * \retval >=0 Number of characters transferred. + */ +int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_M_SYNC_H_INCLUDED */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_spi_s_async.h b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_spi_s_async.h new file mode 100644 index 00000000..56472439 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_spi_s_async.h @@ -0,0 +1,232 @@ +/** + * \file + * + * \brief SPI Slave Async related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_S_ASYNC_H_INCLUDED +#define _HPL_SPI_S_ASYNC_H_INCLUDED + +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI async device driver. */ +#define _spi_s_async_dev _spi_async_dev + +#define _spi_s_async_dev_cb_type _spi_async_dev_cb_type + +/** Uses common SPI async device driver complete callback type. */ +#define _spi_m_async_dev_cb_error_t _spi_async_dev_cb_error_t + +/** Uses common SPI async device driver transfer callback type. */ +#define _spi_s_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access with interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev); + +/** + * \brief Enable SPI for access with interrupts + * Enable the SPI and enable callback generation of receive and error + * interrupts. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_enable(struct _spi_s_async_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI and interrupts. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_disable(struct _spi_s_async_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_set_mode(struct _spi_s_async_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_set_char_size(struct _spi_s_async_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_set_data_order(struct _spi_s_async_dev *dev, const enum spi_data_order dord); + +/** + * \brief Enable interrupt on character output + * + * Enable interrupt when a new character can be written + * to the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable output interrupt + * false = disable output interrupt + * + * \return Status code + * \retval 0 Ok status + */ +int32_t _spi_s_async_enable_tx(struct _spi_s_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on character input + * + * Enable interrupt when a new character is ready to be + * read from the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_s_async_enable_rx(struct _spi_s_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on Slave Select (SS) rising + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_s_async_enable_ss_detect(struct _spi_s_async_dev *dev, bool state); + +/** + * \brief Read one character to SPI device instance + * \param[in, out] dev Pointer to the SPI device instance. + * + * \return Character read from SPI module + */ +uint16_t _spi_s_async_read_one(struct _spi_s_async_dev *dev); + +/** + * \brief Write one character to assigned buffer + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] data + * + * \return Status code of write operation + * \retval 0 Write operation OK + */ +int32_t _spi_s_async_write_one(struct _spi_s_async_dev *dev, uint16_t data); + +/** + * \brief Register the SPI device callback + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] cb_type The callback type. + * \param[in] func The callback function to register. NULL to disable callback. + * \return Always 0. + */ +int32_t _spi_s_async_register_callback(struct _spi_s_async_dev *dev, const enum _spi_s_async_dev_cb_type cb_type, + const FUNC_PTR func); + +/** + * \brief Enable/disable SPI slave interrupt + * + * param[in] device The pointer to SPI slave device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _spi_s_async_set_irq_state(struct _spi_s_async_dev *const device, const enum _spi_async_dev_cb_type type, + const bool state); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_S_ASYNC_H_INCLUDED */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_spi_s_sync.h b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_spi_s_sync.h new file mode 100644 index 00000000..ff4c811a --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_spi_s_sync.h @@ -0,0 +1,232 @@ +/** + * \file + * + * \brief SPI related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_S_SYNC_H_INCLUDED +#define _HPL_SPI_S_SYNC_H_INCLUDED + +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI sync device driver. */ +#define _spi_s_sync_dev _spi_sync_dev + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access without interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev); + +/** + * \brief Enable SPI for access without interrupts + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord); + +/** + * \brief Enable interrupt on character output + * + * Enable interrupt when a new character can be written + * to the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable output interrupt + * false = disable output interrupt + * + * \return Status code + * \retval 0 Ok status + */ +int32_t _spi_s_sync_enable_tx(struct _spi_s_sync_dev *dev, bool state); + +/** + * \brief Enable interrupt on character input + * + * Enable interrupt when a new character is ready to be + * read from the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retval 0 OK Status + */ +int32_t _spi_s_sync_enable_rx(struct _spi_s_sync_dev *dev, bool state); + +/** + * \brief Read one character to SPI device instance + * \param[in, out] dev Pointer to the SPI device instance. + * + * \return Character read from SPI module + */ +uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev); + +/** + * \brief Write one character to assigned buffer + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] data + * + * \return Status code of write operation + * \retval 0 Write operation OK + */ +int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data); + +/** + * \brief Check if TX ready + * + * \param[in] dev Pointer to the SPI device instance + * + * \return TX ready state + * \retval true TX ready + * \retval false TX not ready + */ +bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev); + +/** + * \brief Check if RX character ready + * + * \param[in] dev Pointer to the SPI device instance + * + * \return RX character ready state + * \retval true RX character ready + * \retval false RX character not ready + */ +bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev); + +/** + * \brief Check if SS deactiviation detected + * + * \param[in] dev Pointer to the SPI device instance + * + * \return SS deactiviation state + * \retval true SS deactiviation detected + * \retval false SS deactiviation not detected + */ +bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev); + +/** + * \brief Check if error is detected + * + * \param[in] dev Pointer to the SPI device instance + * + * \return Error detection state + * \retval true Error detected + * \retval false Error not detected + */ +bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_S_SYNC_H_INCLUDED */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_spi_sync.h b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_spi_sync.h new file mode 100644 index 00000000..dc88648f --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_spi_sync.h @@ -0,0 +1,70 @@ +/** + * \file + * + * \brief Common SPI related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_SYNC_H_INCLUDED +#define _HPL_SPI_SYNC_H_INCLUDED + +#include +#include + +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * \section hpl_spi_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** SPI driver to support sync HAL */ +struct _spi_sync_dev { + /** Pointer to the hardware base or private data for special device. */ + void *prvt; + /** Data size, number of bytes for each character */ + uint8_t char_size; + /** Dummy byte used in master mode when reading the slave */ + uint16_t dummy_byte; +}; + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_SYNC_H_INCLUDED */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_time_measure.h b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_time_measure.h new file mode 100644 index 00000000..5d688df5 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_time_measure.h @@ -0,0 +1,94 @@ +/** + * \file + * + * \brief Time measure related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_TIME_MEASURE_H_INCLUDED +#define _HPL_TIME_MEASURE_H_INCLUDED + +/** + * \addtogroup HPL Time measure + * + * \section hpl_time_measure_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief System time type + */ +typedef uint32_t system_time_t; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize system time module + * + * \param[in] hw The pointer to hardware instance to initialize + */ +void _system_time_init(void *const hw); + +/** + * \brief Deinitialize system time module + * + * \param[in] hw The pointer to hardware instance to initialize + */ +void _system_time_deinit(void *const hw); + +/** + * \brief Get system time + * + * \param[in] hw The pointer to hardware instance to initialize + */ +system_time_t _system_time_get(const void *const hw); + +/** + * \brief Get maximum possible system time + * + * \param[in] hw The pointer to hardware instance to initialize + */ +system_time_t _system_time_get_max_time_value(const void *const hw); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_TIME_MEASURE_H_INCLUDED */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_usart.h b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_usart.h new file mode 100644 index 00000000..0e09501d --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_usart.h @@ -0,0 +1,113 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_USART_H_INCLUDED +#define _HPL_USART_H_INCLUDED + +/** + * \addtogroup HPL USART SYNC + * + * \section hpl_usart_sync_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief USART flow control state + */ +union usart_flow_control_state { + struct { + uint8_t cts : 1; + uint8_t rts : 1; + uint8_t unavailable : 1; + uint8_t reserved : 5; + } bit; + uint8_t value; +}; + +/** + * \brief USART baud rate mode + */ +enum usart_baud_rate_mode { USART_BAUDRATE_ASYNCH_ARITHMETIC, USART_BAUDRATE_ASYNCH_FRACTIONAL, USART_BAUDRATE_SYNCH }; + +/** + * \brief USART data order + */ +enum usart_data_order { USART_DATA_ORDER_MSB = 0, USART_DATA_ORDER_LSB = 1 }; + +/** + * \brief USART mode + */ +enum usart_mode { USART_MODE_ASYNCHRONOUS = 0, USART_MODE_SYNCHRONOUS = 1 }; + +/** + * \brief USART parity + */ +enum usart_parity { + USART_PARITY_EVEN = 0, + USART_PARITY_ODD = 1, + USART_PARITY_NONE = 2, + USART_PARITY_SPACE = 3, + USART_PARITY_MARK = 4 +}; + +/** + * \brief USART stop bits mode + */ +enum usart_stop_bits { USART_STOP_BITS_ONE = 0, USART_STOP_BITS_TWO = 1, USART_STOP_BITS_ONE_P_FIVE = 2 }; + +/** + * \brief USART character size + */ +enum usart_character_size { + USART_CHARACTER_SIZE_8BITS = 0, + USART_CHARACTER_SIZE_9BITS = 1, + USART_CHARACTER_SIZE_5BITS = 5, + USART_CHARACTER_SIZE_6BITS = 6, + USART_CHARACTER_SIZE_7BITS = 7 +}; + +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_USART_H_INCLUDED */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_usart_async.h b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_usart_async.h new file mode 100644 index 00000000..3f833d1a --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_usart_async.h @@ -0,0 +1,270 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_USART_ASYNC_H_INCLUDED +#define _HPL_USART_ASYNC_H_INCLUDED + +/** + * \addtogroup HPL USART + * + * \section hpl_usart_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include "hpl_usart.h" +#include "hpl_irq.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief USART callback types + */ +enum _usart_async_callback_type { USART_ASYNC_BYTE_SENT, USART_ASYNC_RX_DONE, USART_ASYNC_TX_DONE, USART_ASYNC_ERROR }; + +/** + * \brief USART device structure + * + * The USART device structure forward declaration. + */ +struct _usart_async_device; + +/** + * \brief USART interrupt callbacks + */ +struct _usart_async_callbacks { + void (*tx_byte_sent)(struct _usart_async_device *device); + void (*rx_done_cb)(struct _usart_async_device *device, uint8_t data); + void (*tx_done_cb)(struct _usart_async_device *device); + void (*error_cb)(struct _usart_async_device *device); +}; + +/** + * \brief USART descriptor device structure + */ +struct _usart_async_device { + struct _usart_async_callbacks usart_cb; + struct _irq_descriptor irq; + void * hw; +}; +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize asynchronous USART + * + * This function does low level USART configuration. + * + * \param[in] device The pointer to USART device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status + */ +int32_t _usart_async_init(struct _usart_async_device *const device, void *const hw); + +/** + * \brief Deinitialize USART + * + * This function closes the given USART by disabling its clock. + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_deinit(struct _usart_async_device *const device); + +/** + * \brief Enable usart module + * + * This function will enable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_enable(struct _usart_async_device *const device); + +/** + * \brief Disable usart module + * + * This function will disable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_disable(struct _usart_async_device *const device); + +/** + * \brief Calculate baud rate register value + * + * \param[in] baud Required baud rate + * \param[in] clock_rate clock frequency + * \param[in] samples The number of samples + * \param[in] mode USART mode + * \param[in] fraction A fraction value + * + * \return Calculated baud rate register value + */ +uint16_t _usart_async_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction); + +/** + * \brief Set baud rate + * + * \param[in] device The pointer to USART device instance + * \param[in] baud_rate A baud rate to set + */ +void _usart_async_set_baud_rate(struct _usart_async_device *const device, const uint32_t baud_rate); + +/** + * \brief Set data order + * + * \param[in] device The pointer to USART device instance + * \param[in] order A data order to set + */ +void _usart_async_set_data_order(struct _usart_async_device *const device, const enum usart_data_order order); + +/** + * \brief Set mode + * + * \param[in] device The pointer to USART device instance + * \param[in] mode A mode to set + */ +void _usart_async_set_mode(struct _usart_async_device *const device, const enum usart_mode mode); + +/** + * \brief Set parity + * + * \param[in] device The pointer to USART device instance + * \param[in] parity A parity to set + */ +void _usart_async_set_parity(struct _usart_async_device *const device, const enum usart_parity parity); + +/** + * \brief Set stop bits mode + * + * \param[in] device The pointer to USART device instance + * \param[in] stop_bits A stop bits mode to set + */ +void _usart_async_set_stop_bits(struct _usart_async_device *const device, const enum usart_stop_bits stop_bits); + +/** + * \brief Set character size + * + * \param[in] device The pointer to USART device instance + * \param[in] size A character size to set + */ +void _usart_async_set_character_size(struct _usart_async_device *const device, const enum usart_character_size size); + +/** + * \brief Retrieve usart status + * + * \param[in] device The pointer to USART device instance + */ +uint32_t _usart_async_get_status(const struct _usart_async_device *const device); + +/** + * \brief Write a byte to the given USART instance + * + * \param[in] device The pointer to USART device instance + * \param[in] data Data to write + */ +void _usart_async_write_byte(struct _usart_async_device *const device, uint8_t data); + +/** + * \brief Check if USART is ready to send next byte + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the ready check. + * \retval true if the USART is ready to send next byte + * \retval false if the USART is not ready to send next byte + */ +bool _usart_async_is_byte_sent(const struct _usart_async_device *const device); + +/** + * \brief Set the state of flow control pins + * + * \param[in] device The pointer to USART device instance + * \param[in] state - A state of flow control pins to set + */ +void _usart_async_set_flow_control_state(struct _usart_async_device *const device, + const union usart_flow_control_state state); + +/** + * \brief Retrieve the state of flow control pins + * + * This function retrieves the of flow control pins. + * + * \return USART_FLOW_CONTROL_STATE_UNAVAILABLE. + */ +union usart_flow_control_state _usart_async_get_flow_control_state(const struct _usart_async_device *const device); + +/** + * \brief Enable data register empty interrupt + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_enable_byte_sent_irq(struct _usart_async_device *const device); + +/** + * \brief Enable transmission complete interrupt + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_enable_tx_done_irq(struct _usart_async_device *const device); + +/** + * \brief Retrieve ordinal number of the given USART hardware instance + * + * \param[in] device The pointer to USART device instance + * + * \return The ordinal number of the given USART hardware instance + */ +uint8_t _usart_async_get_hardware_index(const struct _usart_async_device *const device); + +/** + * \brief Enable/disable USART interrupt + * + * param[in] device The pointer to USART device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _usart_async_set_irq_state(struct _usart_async_device *const device, const enum _usart_async_callback_type type, + const bool state); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_USART_ASYNC_H_INCLUDED */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_usart_sync.h b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_usart_sync.h new file mode 100644 index 00000000..abc7264f --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/include/hpl_usart_sync.h @@ -0,0 +1,254 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SYNC_USART_H_INCLUDED +#define _HPL_SYNC_USART_H_INCLUDED + +/** + * \addtogroup HPL USART SYNC + * + * \section hpl_usart_sync_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief USART descriptor device structure + */ +struct _usart_sync_device { + void *hw; +}; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize synchronous USART + * + * This function does low level USART configuration. + * + * \param[in] device The pointer to USART device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status + */ +int32_t _usart_sync_init(struct _usart_sync_device *const device, void *const hw); + +/** + * \brief Deinitialize USART + * + * This function closes the given USART by disabling its clock. + * + * \param[in] device The pointer to USART device instance + */ +void _usart_sync_deinit(struct _usart_sync_device *const device); + +/** + * \brief Enable usart module + * + * This function will enable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_sync_enable(struct _usart_sync_device *const device); + +/** + * \brief Disable usart module + * + * This function will disable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_sync_disable(struct _usart_sync_device *const device); + +/** + * \brief Calculate baud rate register value + * + * \param[in] baud Required baud rate + * \param[in] clock_rate clock frequency + * \param[in] samples The number of samples + * \param[in] mode USART mode + * \param[in] fraction A fraction value + * + * \return Calculated baud rate register value + */ +uint16_t _usart_sync_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction); + +/** + * \brief Set baud rate + * + * \param[in] device The pointer to USART device instance + * \param[in] baud_rate A baud rate to set + */ +void _usart_sync_set_baud_rate(struct _usart_sync_device *const device, const uint32_t baud_rate); + +/** + * \brief Set data order + * + * \param[in] device The pointer to USART device instance + * \param[in] order A data order to set + */ +void _usart_sync_set_data_order(struct _usart_sync_device *const device, const enum usart_data_order order); + +/** + * \brief Set mode + * + * \param[in] device The pointer to USART device instance + * \param[in] mode A mode to set + */ +void _usart_sync_set_mode(struct _usart_sync_device *const device, const enum usart_mode mode); + +/** + * \brief Set parity + * + * \param[in] device The pointer to USART device instance + * \param[in] parity A parity to set + */ +void _usart_sync_set_parity(struct _usart_sync_device *const device, const enum usart_parity parity); + +/** + * \brief Set stop bits mode + * + * \param[in] device The pointer to USART device instance + * \param[in] stop_bits A stop bits mode to set + */ +void _usart_sync_set_stop_bits(struct _usart_sync_device *const device, const enum usart_stop_bits stop_bits); + +/** + * \brief Set character size + * + * \param[in] device The pointer to USART device instance + * \param[in] size A character size to set + */ +void _usart_sync_set_character_size(struct _usart_sync_device *const device, const enum usart_character_size size); + +/** + * \brief Retrieve usart status + * + * \param[in] device The pointer to USART device instance + */ +uint32_t _usart_sync_get_status(const struct _usart_sync_device *const device); + +/** + * \brief Write a byte to the given USART instance + * + * \param[in] device The pointer to USART device instance + * \param[in] data Data to write + */ +void _usart_sync_write_byte(struct _usart_sync_device *const device, uint8_t data); + +/** + * \brief Read a byte from the given USART instance + * + * \param[in] device The pointer to USART device instance + * \param[in] data Data to write + * + * \return Data received via USART interface. + */ +uint8_t _usart_sync_read_byte(const struct _usart_sync_device *const device); + +/** + * \brief Check if USART is ready to send next byte + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the ready check. + * \retval true if the USART is ready to send next byte + * \retval false if the USART is not ready to send next byte + */ +bool _usart_sync_is_ready_to_send(const struct _usart_sync_device *const device); + +/** + * \brief Check if USART transmitter has sent the byte + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the ready check. + * \retval true if the USART transmitter has sent the byte + * \retval false if the USART transmitter has not send the byte + */ +bool _usart_sync_is_transmit_done(const struct _usart_sync_device *const device); + +/** + * \brief Check if there is data received by USART + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the data received check. + * \retval true if the USART has received a byte + * \retval false if the USART has not received a byte + */ +bool _usart_sync_is_byte_received(const struct _usart_sync_device *const device); + +/** + * \brief Set the state of flow control pins + * + * \param[in] device The pointer to USART device instance + * \param[in] state - A state of flow control pins to set + */ +void _usart_sync_set_flow_control_state(struct _usart_sync_device *const device, + const union usart_flow_control_state state); + +/** + * \brief Retrieve the state of flow control pins + * + * This function retrieves the of flow control pins. + * + * \return USART_FLOW_CONTROL_STATE_UNAVAILABLE. + */ +union usart_flow_control_state _usart_sync_get_flow_control_state(const struct _usart_sync_device *const device); + +/** + * \brief Retrieve ordinal number of the given USART hardware instance + * + * \param[in] device The pointer to USART device instance + * + * \return The ordinal number of the given USART hardware instance + */ +uint8_t _usart_sync_get_hardware_index(const struct _usart_sync_device *const device); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_SYNC_USART_H_INCLUDED */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/src/hal_atomic.c b/prototype/firmware/I2C_scanner/I2C_scanner/hal/src/hal_atomic.c new file mode 100644 index 00000000..f56418ee --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/src/hal_atomic.c @@ -0,0 +1,66 @@ +/** + * \file + * + * \brief Critical sections related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_atomic.h" + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Disable interrupts, enter critical section + */ +void atomic_enter_critical(hal_atomic_t volatile *atomic) +{ + *atomic = __get_PRIMASK(); + __disable_irq(); + __DMB(); +} + +/** + * \brief Exit atomic section + */ +void atomic_leave_critical(hal_atomic_t volatile *atomic) +{ + __DMB(); + __set_PRIMASK(*atomic); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t atomic_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/src/hal_delay.c b/prototype/firmware/I2C_scanner/I2C_scanner/hal/src/hal_delay.c new file mode 100644 index 00000000..6f77cc70 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/src/hal_delay.c @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief HAL delay related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include "hal_delay.h" +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief The pointer to a hardware instance used by the driver. + */ +static void *hardware; + +/** + * \brief Initialize Delay driver + */ +void delay_init(void *const hw) +{ + _delay_init(hardware = hw); +} + +/** + * \brief Perform delay in us + */ +void delay_us(const uint16_t us) +{ + _delay_cycles(hardware, _get_cycles_for_us(us)); +} + +/** + * \brief Perform delay in ms + */ +void delay_ms(const uint16_t ms) +{ + _delay_cycles(hardware, _get_cycles_for_ms(ms)); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t delay_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/src/hal_gpio.c b/prototype/firmware/I2C_scanner/I2C_scanner/hal/src/hal_gpio.c new file mode 100644 index 00000000..00dfea6f --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/src/hal_gpio.c @@ -0,0 +1,44 @@ +/** + * \file + * + * \brief Port + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_gpio.h" + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +uint32_t gpio_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/src/hal_i2c_m_sync.c b/prototype/firmware/I2C_scanner/I2C_scanner/hal/src/hal_i2c_m_sync.c new file mode 100644 index 00000000..30821a27 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/src/hal_i2c_m_sync.c @@ -0,0 +1,258 @@ +/** + * \file + * + * \brief I/O I2C related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Sync version of I2C I/O read + */ +static int32_t i2c_m_sync_read(struct io_descriptor *io, uint8_t *buf, const uint16_t n) +{ + struct i2c_m_sync_desc *i2c = CONTAINER_OF(io, struct i2c_m_sync_desc, io); + struct _i2c_m_msg msg; + int32_t ret; + + msg.addr = i2c->slave_addr; + msg.len = n; + msg.flags = I2C_M_STOP | I2C_M_RD; + msg.buffer = buf; + + ret = _i2c_m_sync_transfer(&i2c->device, &msg); + + if (ret) { + return ret; + } + + return n; +} + +/** + * \brief Sync version of I2C I/O write + */ +static int32_t i2c_m_sync_write(struct io_descriptor *io, const uint8_t *buf, const uint16_t n) +{ + struct i2c_m_sync_desc *i2c = CONTAINER_OF(io, struct i2c_m_sync_desc, io); + struct _i2c_m_msg msg; + int32_t ret; + + msg.addr = i2c->slave_addr; + msg.len = n; + msg.flags = I2C_M_STOP; + msg.buffer = (uint8_t *)buf; + + ret = _i2c_m_sync_transfer(&i2c->device, &msg); + + if (ret) { + return ret; + } + + return n; +} + +/** + * \brief Sync version of i2c initialize + */ +int32_t i2c_m_sync_init(struct i2c_m_sync_desc *i2c, void *hw) +{ + int32_t init_status; + ASSERT(i2c); + + init_status = _i2c_m_sync_init(&i2c->device, hw); + if (init_status) { + return init_status; + } + + /* Init I/O */ + i2c->io.read = i2c_m_sync_read; + i2c->io.write = i2c_m_sync_write; + + return ERR_NONE; +} + +/** + * \brief deinitialize + */ +int32_t i2c_m_sync_deinit(struct i2c_m_sync_desc *i2c) +{ + int32_t status; + ASSERT(i2c); + + status = _i2c_m_sync_deinit(&i2c->device); + if (status) { + return status; + } + + i2c->io.read = NULL; + i2c->io.write = NULL; + + return ERR_NONE; +} + +/** + * \brief Sync version of i2c enable + */ +int32_t i2c_m_sync_enable(struct i2c_m_sync_desc *i2c) +{ + return _i2c_m_sync_enable(&i2c->device); +} + +/** + * \brief Sync version of i2c disable + */ +int32_t i2c_m_sync_disable(struct i2c_m_sync_desc *i2c) +{ + return _i2c_m_sync_disable(&i2c->device); +} + +/** + * \brief Sync version of i2c set slave address + */ +int32_t i2c_m_sync_set_slaveaddr(struct i2c_m_sync_desc *i2c, int16_t addr, int32_t addr_len) +{ + return i2c->slave_addr = (addr & 0x3ff) | (addr_len & I2C_M_TEN); +} + +/** + * \brief Sync version of i2c set baudrate + */ +int32_t i2c_m_sync_set_baudrate(struct i2c_m_sync_desc *i2c, uint32_t clkrate, uint32_t baudrate) +{ + return _i2c_m_sync_set_baudrate(&i2c->device, clkrate, baudrate); +} + +/** + * \brief Sync version of i2c write command + */ +int32_t i2c_m_sync_cmd_write(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length) +{ + struct _i2c_m_msg msg; + int32_t ret; + + msg.addr = i2c->slave_addr; + msg.len = 1; + msg.flags = 0; + msg.buffer = ® + + ret = _i2c_m_sync_transfer(&i2c->device, &msg); + + if (ret != 0) { + /* error occurred */ + return ret; + } + + msg.flags = I2C_M_STOP; + msg.buffer = buffer; + msg.len = length; + + ret = _i2c_m_sync_transfer(&i2c->device, &msg); + + if (ret != 0) { + /* error occurred */ + return ret; + } + + return ERR_NONE; +} + +/** + * \brief Sync version of i2c read command + */ +int32_t i2c_m_sync_cmd_read(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length) +{ + struct _i2c_m_msg msg; + int32_t ret; + + msg.addr = i2c->slave_addr; + msg.len = 1; + msg.flags = 0; + msg.buffer = ® + + ret = _i2c_m_sync_transfer(&i2c->device, &msg); + + if (ret != 0) { + /* error occurred */ + return ret; + } + + msg.flags = I2C_M_STOP | I2C_M_RD; + msg.buffer = buffer; + msg.len = length; + + ret = _i2c_m_sync_transfer(&i2c->device, &msg); + + if (ret != 0) { + /* error occurred */ + return ret; + } + + return ERR_NONE; +} + +/** + * \brief Sync version of i2c transfer command + */ +int32_t i2c_m_sync_transfer(struct i2c_m_sync_desc *const i2c, struct _i2c_m_msg *msg) +{ + return _i2c_m_sync_transfer(&i2c->device, msg); +} + +/** + * \brief Sync version of i2c send stop condition command + */ +int32_t i2c_m_sync_send_stop(struct i2c_m_sync_desc *const i2c) +{ + return _i2c_m_sync_send_stop(&i2c->device); +} + +/** + * \brief Retrieve I/O descriptor + */ +int32_t i2c_m_sync_get_io_descriptor(struct i2c_m_sync_desc *const i2c, struct io_descriptor **io) +{ + *io = &i2c->io; + return ERR_NONE; +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t i2c_m_sync_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/src/hal_init.c b/prototype/firmware/I2C_scanner/I2C_scanner/hal/src/hal_init.c new file mode 100644 index 00000000..fb65341f --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/src/hal_init.c @@ -0,0 +1,47 @@ +/** + * \file + * + * \brief HAL initialization related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_init.h" + +/** + * \brief Driver version + */ +#define HAL_INIT_VERSION 0x00000001u + +/** + * \brief Retrieve the current driver version + */ +uint32_t init_get_version(void) +{ + return HAL_INIT_VERSION; +} diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/src/hal_io.c b/prototype/firmware/I2C_scanner/I2C_scanner/hal/src/hal_io.c new file mode 100644 index 00000000..7e8feb04 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/src/hal_io.c @@ -0,0 +1,63 @@ +/** + * \file + * + * \brief I/O functionality implementation. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +uint32_t io_get_version(void) +{ + return DRIVER_VERSION; +} + +/** + * \brief I/O write interface + */ +int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length) +{ + ASSERT(io_descr && buf); + return io_descr->write(io_descr, buf, length); +} + +/** + * \brief I/O read interface + */ +int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length) +{ + ASSERT(io_descr && buf); + return io_descr->read(io_descr, buf, length); +} diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/src/hal_sleep.c b/prototype/firmware/I2C_scanner/I2C_scanner/hal/src/hal_sleep.c new file mode 100644 index 00000000..89472f15 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/src/hal_sleep.c @@ -0,0 +1,73 @@ +/** + * \file + * + * \brief Sleep related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_sleep.h" +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Set the sleep mode of the device and put the MCU to sleep + * + * For an overview of which systems are disabled in sleep for the different + * sleep modes, see the data sheet. + * + * \param[in] mode Sleep mode to use + * + * \return The status of a sleep request + * \retval -1 The requested sleep mode was invalid or not available + * \retval 0 The operation completed successfully, returned after leaving the + * sleep + */ +int sleep(const uint8_t mode) +{ + if (ERR_NONE != _set_sleep_mode(mode)) + return ERR_INVALID_ARG; + + _go_to_sleep(); + + return ERR_NONE; +} + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version + */ +uint32_t sleep_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/src/hal_usart_sync.c b/prototype/firmware/I2C_scanner/I2C_scanner/hal/src/hal_usart_sync.c new file mode 100644 index 00000000..ab99c1d1 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/src/hal_usart_sync.c @@ -0,0 +1,276 @@ +/** + * \file + * + * \brief I/O USART related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_usart_sync.h" +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +static int32_t usart_sync_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); +static int32_t usart_sync_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); + +/** + * \brief Initialize usart interface + */ +int32_t usart_sync_init(struct usart_sync_descriptor *const descr, void *const hw, void *const func) +{ + int32_t init_status; + ASSERT(descr && hw); + init_status = _usart_sync_init(&descr->device, hw); + if (init_status) { + return init_status; + } + + descr->io.read = usart_sync_read; + descr->io.write = usart_sync_write; + + return ERR_NONE; +} + +/** + * \brief Uninitialize usart interface + */ +int32_t usart_sync_deinit(struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + _usart_sync_deinit(&descr->device); + + descr->io.read = NULL; + descr->io.write = NULL; + + return ERR_NONE; +} + +/** + * \brief Enable usart interface + */ +int32_t usart_sync_enable(struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + _usart_sync_enable(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Disable usart interface + */ +int32_t usart_sync_disable(struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + _usart_sync_disable(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Retrieve I/O descriptor + */ +int32_t usart_sync_get_io_descriptor(struct usart_sync_descriptor *const descr, struct io_descriptor **io) +{ + ASSERT(descr && io); + + *io = &descr->io; + return ERR_NONE; +} + +/** + * \brief Specify action for flow control pins + */ +int32_t usart_sync_set_flow_control(struct usart_sync_descriptor *const descr, + const union usart_flow_control_state state) +{ + ASSERT(descr); + _usart_sync_set_flow_control_state(&descr->device, state); + + return ERR_NONE; +} + +/** + * \brief Set usart baud rate + */ +int32_t usart_sync_set_baud_rate(struct usart_sync_descriptor *const descr, const uint32_t baud_rate) +{ + ASSERT(descr); + _usart_sync_set_baud_rate(&descr->device, baud_rate); + + return ERR_NONE; +} + +/** + * \brief Set usart data order + */ +int32_t usart_sync_set_data_order(struct usart_sync_descriptor *const descr, const enum usart_data_order data_order) +{ + ASSERT(descr); + _usart_sync_set_data_order(&descr->device, data_order); + + return ERR_NONE; +} + +/** + * \brief Set usart mode + */ +int32_t usart_sync_set_mode(struct usart_sync_descriptor *const descr, const enum usart_mode mode) +{ + ASSERT(descr); + _usart_sync_set_mode(&descr->device, mode); + + return ERR_NONE; +} + +/** + * \brief Set usart parity + */ +int32_t usart_sync_set_parity(struct usart_sync_descriptor *const descr, const enum usart_parity parity) +{ + ASSERT(descr); + _usart_sync_set_parity(&descr->device, parity); + + return ERR_NONE; +} + +/** + * \brief Set usart stop bits + */ +int32_t usart_sync_set_stopbits(struct usart_sync_descriptor *const descr, const enum usart_stop_bits stop_bits) +{ + ASSERT(descr); + _usart_sync_set_stop_bits(&descr->device, stop_bits); + + return ERR_NONE; +} + +/** + * \brief Set usart character size + */ +int32_t usart_sync_set_character_size(struct usart_sync_descriptor *const descr, const enum usart_character_size size) +{ + ASSERT(descr); + _usart_sync_set_character_size(&descr->device, size); + + return ERR_NONE; +} + +/** + * \brief Retrieve the state of flow control pins + */ +int32_t usart_sync_flow_control_status(const struct usart_sync_descriptor *const descr, + union usart_flow_control_state *const state) +{ + ASSERT(descr && state); + *state = _usart_sync_get_flow_control_state(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Check if the usart transmitter is empty + */ +int32_t usart_sync_is_tx_empty(const struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + return _usart_sync_is_ready_to_send(&descr->device); +} + +/** + * \brief Check if the usart receiver is not empty + */ +int32_t usart_sync_is_rx_not_empty(const struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + return _usart_sync_is_byte_received(&descr->device); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t usart_sync_get_version(void) +{ + return DRIVER_VERSION; +} + +/* + * \internal Write the given data to usart interface + * + * \param[in] descr The pointer to an io descriptor + * \param[in] buf Data to write to usart + * \param[in] length The number of bytes to write + * + * \return The number of bytes written. + */ +static int32_t usart_sync_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length) +{ + uint32_t offset = 0; + struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io); + + ASSERT(io_descr && buf && length); + while (!_usart_sync_is_ready_to_send(&descr->device)) + ; + do { + _usart_sync_write_byte(&descr->device, buf[offset]); + while (!_usart_sync_is_ready_to_send(&descr->device)) + ; + } while (++offset < length); + while (!_usart_sync_is_transmit_done(&descr->device)) + ; + return (int32_t)offset; +} + +/* + * \internal Read data from usart interface + * + * \param[in] descr The pointer to an io descriptor + * \param[in] buf A buffer to read data to + * \param[in] length The size of a buffer + * + * \return The number of bytes read. + */ +static int32_t usart_sync_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length) +{ + uint32_t offset = 0; + struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io); + + ASSERT(io_descr && buf && length); + do { + while (!_usart_sync_is_byte_received(&descr->device)) + ; + buf[offset] = _usart_sync_read_byte(&descr->device); + } while (++offset < length); + + return (int32_t)offset; +} diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/utils/include/compiler.h b/prototype/firmware/I2C_scanner/I2C_scanner/hal/utils/include/compiler.h new file mode 100644 index 00000000..f35db3df --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/utils/include/compiler.h @@ -0,0 +1,64 @@ +/** + * \file + * + * \brief Header + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +/****************************************************************************** + * compiler.h + * + * Created: 05.05.2014 + * Author: N. Fomin + ******************************************************************************/ + +#ifndef _COMPILER_H +#define _COMPILER_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#ifndef _UNIT_TEST_ +#include "parts.h" +#endif +#include "err_codes.h" + +#ifdef __cplusplus +} +#endif + +#endif /* _COMPILER_H */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/utils/include/err_codes.h b/prototype/firmware/I2C_scanner/I2C_scanner/hal/utils/include/err_codes.h new file mode 100644 index 00000000..a7aff018 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/utils/include/err_codes.h @@ -0,0 +1,73 @@ +/** + * \file + * + * \brief Error code definitions. + * + * This file defines various status codes returned by functions, + * indicating success or failure as well as what kind of failure. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef ERROR_CODES_H_INCLUDED +#define ERROR_CODES_H_INCLUDED + +#define ERR_NONE 0 +#define ERR_INVALID_DATA -1 +#define ERR_NO_CHANGE -2 +#define ERR_ABORTED -3 +#define ERR_BUSY -4 +#define ERR_SUSPEND -5 +#define ERR_IO -6 +#define ERR_REQ_FLUSHED -7 +#define ERR_TIMEOUT -8 +#define ERR_BAD_DATA -9 +#define ERR_NOT_FOUND -10 +#define ERR_UNSUPPORTED_DEV -11 +#define ERR_NO_MEMORY -12 +#define ERR_INVALID_ARG -13 +#define ERR_BAD_ADDRESS -14 +#define ERR_BAD_FORMAT -15 +#define ERR_BAD_FRQ -16 +#define ERR_DENIED -17 +#define ERR_ALREADY_INITIALIZED -18 +#define ERR_OVERFLOW -19 +#define ERR_NOT_INITIALIZED -20 +#define ERR_SAMPLERATE_UNAVAILABLE -21 +#define ERR_RESOLUTION_UNAVAILABLE -22 +#define ERR_BAUDRATE_UNAVAILABLE -23 +#define ERR_PACKET_COLLISION -24 +#define ERR_PROTOCOL -25 +#define ERR_PIN_MUX_INVALID -26 +#define ERR_UNSUPPORTED_OP -27 +#define ERR_NO_RESOURCE -28 +#define ERR_NOT_READY -29 +#define ERR_FAILURE -30 +#define ERR_WRONG_LENGTH -31 + +#endif diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/utils/include/events.h b/prototype/firmware/I2C_scanner/I2C_scanner/hal/utils/include/events.h new file mode 100644 index 00000000..3ee891a7 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/utils/include/events.h @@ -0,0 +1,54 @@ +/** + * \file + * + * \brief Events declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _EVENTS_H_INCLUDED +#define _EVENTS_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * \brief List of events. Must start with 0, be unique and follow numerical order. + */ +#define EVENT_IS_READY_TO_SLEEP_ID 0 +#define EVENT_PREPARE_TO_SLEEP_ID 1 +#define EVENT_WOKEN_UP_ID 2 + +#ifdef __cplusplus +} +#endif + +#endif /* _EVENTS_H_INCLUDED */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/utils/include/parts.h b/prototype/firmware/I2C_scanner/I2C_scanner/hal/utils/include/parts.h new file mode 100644 index 00000000..619fff29 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/utils/include/parts.h @@ -0,0 +1,41 @@ +/** + * \file + * + * \brief Atmel part identification macros + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef ATMEL_PARTS_H +#define ATMEL_PARTS_H + +#include "saml21.h" + +#include "hri_l21b.h" + +#endif /* ATMEL_PARTS_H */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/utils/include/utils.h b/prototype/firmware/I2C_scanner/I2C_scanner/hal/utils/include/utils.h new file mode 100644 index 00000000..1cf26996 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/utils/include/utils.h @@ -0,0 +1,368 @@ +/** + * \file + * + * \brief Different macros. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef UTILS_H_INCLUDED +#define UTILS_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_utils_macro + * + * @{ + */ + +/** + * \brief Retrieve pointer to parent structure + */ +#define CONTAINER_OF(ptr, type, field_name) ((type *)(((uint8_t *)ptr) - offsetof(type, field_name))) + +/** + * \brief Retrieve array size + */ +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) + +/** + * \brief Emit the compiler pragma \a arg. + * + * \param[in] arg The pragma directive as it would appear after \e \#pragma + * (i.e. not stringified). + */ +#define COMPILER_PRAGMA(arg) _Pragma(#arg) + +/** + * \def COMPILER_PACK_SET(alignment) + * \brief Set maximum alignment for subsequent struct and union definitions to \a alignment. + */ +#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment)) + +/** + * \def COMPILER_PACK_RESET() + * \brief Set default alignment for subsequent struct and union definitions. + */ +#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack()) + +/** + * \brief Set aligned boundary. + */ +#if defined __GNUC__ +#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) +#elif defined __ICCARM__ +#define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a) +#elif defined __CC_ARM +#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) +#endif + +/** + * \brief Flash located data macros + */ +#if defined __GNUC__ +#define PROGMEM_DECLARE(type, name) const type name +#define PROGMEM_T const +#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) +#define PROGMEM_PTR_T const * +#define PROGMEM_STRING_T const uint8_t * +#elif defined __ICCARM__ +#define PROGMEM_DECLARE(type, name) const type name +#define PROGMEM_T const +#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) +#define PROGMEM_PTR_T const * +#define PROGMEM_STRING_T const uint8_t * +#elif defined __CC_ARM +#define PROGMEM_DECLARE(type, name) const type name +#define PROGMEM_T const +#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) +#define PROGMEM_PTR_T const * +#define PROGMEM_STRING_T const uint8_t * +#endif + +/** + * \brief Optimization + */ +#if defined __GNUC__ +#define OPTIMIZE_HIGH __attribute__((optimize(s))) +#elif defined __CC_ARM +#define OPTIMIZE_HIGH _Pragma("O3") +#elif defined __ICCARM__ +#define OPTIMIZE_HIGH _Pragma("optimize=high") +#endif + +/** + * \brief RAM located function attribute + */ +#if defined(__CC_ARM) /* Keil ?Vision 4 */ +#define RAMFUNC __attribute__((section(".ramfunc"))) +#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */ +#define RAMFUNC __ramfunc +#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */ +#define RAMFUNC __attribute__((section(".ramfunc"))) +#endif + +/** + * \brief No-init section. + * Place a data object or a function in a no-init section. + */ +#if defined(__CC_ARM) +#define NO_INIT(a) __attribute__((zero_init)) +#elif defined(__ICCARM__) +#define NO_INIT(a) __no_init +#elif defined(__GNUC__) +#define NO_INIT(a) __attribute__((section(".no_init"))) +#endif + +/** + * \brief Set user-defined section. + * Place a data object or a function in a user-defined section. + */ +#if defined(__CC_ARM) +#define COMPILER_SECTION(a) __attribute__((__section__(a))) +#elif defined(__ICCARM__) +#define COMPILER_SECTION(a) COMPILER_PRAGMA(location = a) +#elif defined(__GNUC__) +#define COMPILER_SECTION(a) __attribute__((__section__(a))) +#endif + +/** + * \brief Define WEAK attribute. + */ +#if defined(__CC_ARM) /* Keil ?Vision 4 */ +#define WEAK __attribute__((weak)) +#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */ +#define WEAK __weak +#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */ +#define WEAK __attribute__((weak)) +#endif + +/** + * \brief Pointer to function + */ +typedef void (*FUNC_PTR)(void); + +#define LE_BYTE0(a) ((uint8_t)(a)) +#define LE_BYTE1(a) ((uint8_t)((a) >> 8)) +#define LE_BYTE2(a) ((uint8_t)((a) >> 16)) +#define LE_BYTE3(a) ((uint8_t)((a) >> 24)) + +#define LE_2_U16(p) ((p)[0] + ((p)[1] << 8)) +#define LE_2_U32(p) ((p)[0] + ((p)[1] << 8) + ((p)[2] << 16) + ((p)[3] << 24)) + +/** \name Zero-Bit Counting + * + * Under GCC, __builtin_clz and __builtin_ctz behave like macros when + * applied to constant expressions (values known at compile time), so they are + * more optimized than the use of the corresponding assembly instructions and + * they can be used as constant expressions e.g. to initialize objects having + * static storage duration, and like the corresponding assembly instructions + * when applied to non-constant expressions (values unknown at compile time), so + * they are more optimized than an assembly periphrasis. Hence, clz and ctz + * ensure a possible and optimized behavior for both constant and non-constant + * expressions. + * + * @{ */ + +/** \brief Counts the leading zero bits of the given value considered as a 32-bit integer. + * + * \param[in] u Value of which to count the leading zero bits. + * + * \return The count of leading zero bits in \a u. + */ +#if (defined __GNUC__) || (defined __CC_ARM) +#define clz(u) __builtin_clz(u) +#else +#define clz(u) \ + ( \ + ((u) == 0) \ + ? 32 \ + : ((u) & (1ul << 31)) \ + ? 0 \ + : ((u) & (1ul << 30)) \ + ? 1 \ + : ((u) & (1ul << 29)) \ + ? 2 \ + : ((u) & (1ul << 28)) \ + ? 3 \ + : ((u) & (1ul << 27)) \ + ? 4 \ + : ((u) & (1ul << 26)) \ + ? 5 \ + : ((u) & (1ul << 25)) \ + ? 6 \ + : ((u) & (1ul << 24)) \ + ? 7 \ + : ((u) & (1ul << 23)) \ + ? 8 \ + : ((u) & (1ul << 22)) \ + ? 9 \ + : ((u) & (1ul << 21)) \ + ? 10 \ + : ((u) & (1ul << 20)) \ + ? 11 \ + : ((u) & (1ul << 19)) \ + ? 12 \ + : ((u) & (1ul << 18)) \ + ? 13 \ + : ((u) & (1ul << 17)) ? 14 \ + : ((u) & (1ul << 16)) ? 15 \ + : ((u) & (1ul << 15)) ? 16 \ + : ((u) & (1ul << 14)) ? 17 \ + : ((u) & (1ul << 13)) ? 18 \ + : ((u) & (1ul << 12)) ? 19 \ + : ((u) \ + & (1ul \ + << 11)) \ + ? 20 \ + : ((u) \ + & (1ul \ + << 10)) \ + ? 21 \ + : ((u) \ + & (1ul \ + << 9)) \ + ? 22 \ + : ((u) \ + & (1ul \ + << 8)) \ + ? 23 \ + : ((u) & (1ul << 7)) ? 24 \ + : ((u) & (1ul << 6)) ? 25 \ + : ((u) \ + & (1ul \ + << 5)) \ + ? 26 \ + : ((u) & (1ul << 4)) ? 27 \ + : ((u) & (1ul << 3)) ? 28 \ + : ((u) & (1ul << 2)) ? 29 \ + : ( \ + (u) & (1ul << 1)) \ + ? 30 \ + : 31) +#endif + +/** \brief Counts the trailing zero bits of the given value considered as a 32-bit integer. + * + * \param[in] u Value of which to count the trailing zero bits. + * + * \return The count of trailing zero bits in \a u. + */ +#if (defined __GNUC__) || (defined __CC_ARM) +#define ctz(u) __builtin_ctz(u) +#else +#define ctz(u) \ + ( \ + (u) & (1ul << 0) \ + ? 0 \ + : (u) & (1ul << 1) \ + ? 1 \ + : (u) & (1ul << 2) \ + ? 2 \ + : (u) & (1ul << 3) \ + ? 3 \ + : (u) & (1ul << 4) \ + ? 4 \ + : (u) & (1ul << 5) \ + ? 5 \ + : (u) & (1ul << 6) \ + ? 6 \ + : (u) & (1ul << 7) \ + ? 7 \ + : (u) & (1ul << 8) \ + ? 8 \ + : (u) & (1ul << 9) \ + ? 9 \ + : (u) & (1ul << 10) \ + ? 10 \ + : (u) & (1ul << 11) \ + ? 11 \ + : (u) & (1ul << 12) \ + ? 12 \ + : (u) & (1ul << 13) \ + ? 13 \ + : (u) & (1ul << 14) \ + ? 14 \ + : (u) & (1ul << 15) \ + ? 15 \ + : (u) & (1ul << 16) \ + ? 16 \ + : (u) & (1ul << 17) \ + ? 17 \ + : (u) & (1ul << 18) \ + ? 18 \ + : (u) & (1ul << 19) ? 19 \ + : (u) & (1ul << 20) ? 20 \ + : (u) & (1ul << 21) ? 21 \ + : (u) & (1ul << 22) ? 22 \ + : (u) & (1ul << 23) ? 23 \ + : (u) & (1ul << 24) ? 24 \ + : (u) & (1ul << 25) ? 25 \ + : (u) & (1ul << 26) ? 26 \ + : (u) & (1ul << 27) ? 27 \ + : (u) & (1ul << 28) ? 28 : (u) & (1ul << 29) ? 29 : (u) & (1ul << 30) ? 30 : (u) & (1ul << 31) ? 31 : 32) +#endif +/** @} */ + +/** + * \brief Counts the number of bits in a mask (no more than 32 bits) + * \param[in] mask Mask of which to count the bits. + */ +#define size_of_mask(mask) (32 - clz(mask) - ctz(mask)) + +/** + * \brief Retrieve the start position of bits mask (no more than 32 bits) + * \param[in] mask Mask of which to retrieve the start position. + */ +#define pos_of_mask(mask) ctz(mask) + +/** + * \brief Return division result of a/b and round up the result to the closest + * number divisible by "b" + */ +#define round_up(a, b) (((a)-1) / (b) + 1) + +/** + * \brief Get the minimum of x and y + */ +#define min(x, y) ((x) > (y) ? (y) : (x)) + +/** + * \brief Get the maximum of x and y + */ +#define max(x, y) ((x) > (y) ? (x) : (y)) + +/**@}*/ + +#ifdef __cplusplus +} +#endif +#endif /* UTILS_H_INCLUDED */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/utils/include/utils_assert.h b/prototype/firmware/I2C_scanner/I2C_scanner/hal/utils/include/utils_assert.h new file mode 100644 index 00000000..c2328d6c --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/utils/include/utils_assert.h @@ -0,0 +1,93 @@ +/** + * \file + * + * \brief Asserts related functionality. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _ASSERT_H_INCLUDED +#define _ASSERT_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#ifndef USE_SIMPLE_ASSERT +//# define USE_SIMPLE_ASSERT +#endif + +/** + * \brief Assert macro + * + * This macro is used to throw asserts. It can be mapped to different function + * based on debug level. + * + * \param[in] condition A condition to be checked; + * assert is thrown if the given condition is false + */ +#define ASSERT(condition) ASSERT_IMPL((condition), __FILE__, __LINE__) + +#ifdef DEBUG + +#ifdef USE_SIMPLE_ASSERT +#define ASSERT_IMPL(condition, file, line) \ + if (!(condition)) \ + __asm("BKPT #0"); +#else +#define ASSERT_IMPL(condition, file, line) assert((condition), file, line) +#endif + +#else /* DEBUG */ + +#ifdef USE_SIMPLE_ASSERT +#define ASSERT_IMPL(condition, file, line) ((void)0) +#else +#define ASSERT_IMPL(condition, file, line) ((void)0) +#endif + +#endif /* DEBUG */ + +/** + * \brief Assert function + * + * This function is used to throw asserts. + * + * \param[in] condition A condition to be checked; assert is thrown if the given + * condition is false + * \param[in] file File name + * \param[in] line Line number + */ +void assert(const bool condition, const char *const file, const int line); + +#ifdef __cplusplus +} +#endif +#endif /* _ASSERT_H_INCLUDED */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/utils/include/utils_event.h b/prototype/firmware/I2C_scanner/I2C_scanner/hal/utils/include/utils_event.h new file mode 100644 index 00000000..13067c4f --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/utils/include/utils_event.h @@ -0,0 +1,115 @@ +/** + * \file + * + * \brief Events declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_EVENT_H_INCLUDED +#define _UTILS_EVENT_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +/** + * \brief The maximum amount of events + */ +#define EVENT_MAX_AMOUNT 8 + +/** + * \brief The size of event mask used, it is EVENT_MAX_AMOUNT rounded up to the + * closest number divisible by 8. + */ +#define EVENT_MASK_SIZE (round_up(EVENT_MAX_AMOUNT, 8)) + +/** + * \brief The type of event ID. IDs should start with 0 and be in numerical order. + */ +typedef uint8_t event_id_t; + +/** + * \brief The type of returned parameter. This type is big enough to contain + * pointer to data on any platform. + */ +typedef uintptr_t event_data_t; + +/** + * \brief The type of returned parameter. This type is big enough to contain + * pointer to data on any platform. + */ +typedef void (*event_cb_t)(event_id_t id, event_data_t data); + +/** + * \brief Event structure + */ +struct event { + struct list_element elem; /*! The pointer to next event */ + uint8_t mask[EVENT_MASK_SIZE]; /*! Mask of event IDs callback is called for */ + event_cb_t cb; /*! Callback to be called when an event occurs */ +}; + +/** + * \brief Subscribe to event + * + * \param[in] event The pointer to event structure + * \param[in] id The event ID to subscribe to + * \param[in] cb The callback function to call when the given event occurs + * + * \return The status of subscription + */ +int32_t event_subscribe(struct event *const event, const event_id_t id, event_cb_t cb); + +/** + * \brief Remove event from subscription + * + * \param[in] event The pointer to event structure + * \param[in] id The event ID to remove subscription from + * + * \return The status of subscription removing + */ +int32_t event_unsubscribe(struct event *const event, const event_id_t id); + +/** + * \brief Post event + * + * \param[in] id The event ID to post + * \param[in] data The event data to be passed to event subscribers + */ +void event_post(const event_id_t id, const event_data_t data); + +#ifdef __cplusplus +} +#endif + +#endif /* _UTILS_EVENT_H_INCLUDED */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/utils/include/utils_increment_macro.h b/prototype/firmware/I2C_scanner/I2C_scanner/hal/utils/include/utils_increment_macro.h new file mode 100644 index 00000000..464c6cbb --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/utils/include/utils_increment_macro.h @@ -0,0 +1,308 @@ +/** + * \file + * + * \brief Increment macro. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_INCREMENT_MACRO_H +#define _UTILS_INCREMENT_MACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Compile time increment, result value is entire integer literal + * + * \param[in] val - value to be incremented (254 max) + */ +#define INC_VALUE(val) SP_INC_##val + +// Preprocessor increment implementation +#define SP_INC_0 1 +#define SP_INC_1 2 +#define SP_INC_2 3 +#define SP_INC_3 4 +#define SP_INC_4 5 +#define SP_INC_5 6 +#define SP_INC_6 7 +#define SP_INC_7 8 +#define SP_INC_8 9 +#define SP_INC_9 10 +#define SP_INC_10 11 +#define SP_INC_11 12 +#define SP_INC_12 13 +#define SP_INC_13 14 +#define SP_INC_14 15 +#define SP_INC_15 16 +#define SP_INC_16 17 +#define SP_INC_17 18 +#define SP_INC_18 19 +#define SP_INC_19 20 +#define SP_INC_20 21 +#define SP_INC_21 22 +#define SP_INC_22 23 +#define SP_INC_23 24 +#define SP_INC_24 25 +#define SP_INC_25 26 +#define SP_INC_26 27 +#define SP_INC_27 28 +#define SP_INC_28 29 +#define SP_INC_29 30 +#define SP_INC_30 31 +#define SP_INC_31 32 +#define SP_INC_32 33 +#define SP_INC_33 34 +#define SP_INC_34 35 +#define SP_INC_35 36 +#define SP_INC_36 37 +#define SP_INC_37 38 +#define SP_INC_38 39 +#define SP_INC_39 40 +#define SP_INC_40 41 +#define SP_INC_41 42 +#define SP_INC_42 43 +#define SP_INC_43 44 +#define SP_INC_44 45 +#define SP_INC_45 46 +#define SP_INC_46 47 +#define SP_INC_47 48 +#define SP_INC_48 49 +#define SP_INC_49 50 +#define SP_INC_50 51 +#define SP_INC_51 52 +#define SP_INC_52 53 +#define SP_INC_53 54 +#define SP_INC_54 55 +#define SP_INC_55 56 +#define SP_INC_56 57 +#define SP_INC_57 58 +#define SP_INC_58 59 +#define SP_INC_59 60 +#define SP_INC_60 61 +#define SP_INC_61 62 +#define SP_INC_62 63 +#define SP_INC_63 64 +#define SP_INC_64 65 +#define SP_INC_65 66 +#define SP_INC_66 67 +#define SP_INC_67 68 +#define SP_INC_68 69 +#define SP_INC_69 70 +#define SP_INC_70 71 +#define SP_INC_71 72 +#define SP_INC_72 73 +#define SP_INC_73 74 +#define SP_INC_74 75 +#define SP_INC_75 76 +#define SP_INC_76 77 +#define SP_INC_77 78 +#define SP_INC_78 79 +#define SP_INC_79 80 +#define SP_INC_80 81 +#define SP_INC_81 82 +#define SP_INC_82 83 +#define SP_INC_83 84 +#define SP_INC_84 85 +#define SP_INC_85 86 +#define SP_INC_86 87 +#define SP_INC_87 88 +#define SP_INC_88 89 +#define SP_INC_89 90 +#define SP_INC_90 91 +#define SP_INC_91 92 +#define SP_INC_92 93 +#define SP_INC_93 94 +#define SP_INC_94 95 +#define SP_INC_95 96 +#define SP_INC_96 97 +#define SP_INC_97 98 +#define SP_INC_98 99 +#define SP_INC_99 100 +#define SP_INC_100 101 +#define SP_INC_101 102 +#define SP_INC_102 103 +#define SP_INC_103 104 +#define SP_INC_104 105 +#define SP_INC_105 106 +#define SP_INC_106 107 +#define SP_INC_107 108 +#define SP_INC_108 109 +#define SP_INC_109 110 +#define SP_INC_110 111 +#define SP_INC_111 112 +#define SP_INC_112 113 +#define SP_INC_113 114 +#define SP_INC_114 115 +#define SP_INC_115 116 +#define SP_INC_116 117 +#define SP_INC_117 118 +#define SP_INC_118 119 +#define SP_INC_119 120 +#define SP_INC_120 121 +#define SP_INC_121 122 +#define SP_INC_122 123 +#define SP_INC_123 124 +#define SP_INC_124 125 +#define SP_INC_125 126 +#define SP_INC_126 127 +#define SP_INC_127 128 +#define SP_INC_128 129 +#define SP_INC_129 130 +#define SP_INC_130 131 +#define SP_INC_131 132 +#define SP_INC_132 133 +#define SP_INC_133 134 +#define SP_INC_134 135 +#define SP_INC_135 136 +#define SP_INC_136 137 +#define SP_INC_137 138 +#define SP_INC_138 139 +#define SP_INC_139 140 +#define SP_INC_140 141 +#define SP_INC_141 142 +#define SP_INC_142 143 +#define SP_INC_143 144 +#define SP_INC_144 145 +#define SP_INC_145 146 +#define SP_INC_146 147 +#define SP_INC_147 148 +#define SP_INC_148 149 +#define SP_INC_149 150 +#define SP_INC_150 151 +#define SP_INC_151 152 +#define SP_INC_152 153 +#define SP_INC_153 154 +#define SP_INC_154 155 +#define SP_INC_155 156 +#define SP_INC_156 157 +#define SP_INC_157 158 +#define SP_INC_158 159 +#define SP_INC_159 160 +#define SP_INC_160 161 +#define SP_INC_161 162 +#define SP_INC_162 163 +#define SP_INC_163 164 +#define SP_INC_164 165 +#define SP_INC_165 166 +#define SP_INC_166 167 +#define SP_INC_167 168 +#define SP_INC_168 169 +#define SP_INC_169 170 +#define SP_INC_170 171 +#define SP_INC_171 172 +#define SP_INC_172 173 +#define SP_INC_173 174 +#define SP_INC_174 175 +#define SP_INC_175 176 +#define SP_INC_176 177 +#define SP_INC_177 178 +#define SP_INC_178 179 +#define SP_INC_179 180 +#define SP_INC_180 181 +#define SP_INC_181 182 +#define SP_INC_182 183 +#define SP_INC_183 184 +#define SP_INC_184 185 +#define SP_INC_185 186 +#define SP_INC_186 187 +#define SP_INC_187 188 +#define SP_INC_188 189 +#define SP_INC_189 190 +#define SP_INC_190 191 +#define SP_INC_191 192 +#define SP_INC_192 193 +#define SP_INC_193 194 +#define SP_INC_194 195 +#define SP_INC_195 196 +#define SP_INC_196 197 +#define SP_INC_197 198 +#define SP_INC_198 199 +#define SP_INC_199 200 +#define SP_INC_200 201 +#define SP_INC_201 202 +#define SP_INC_202 203 +#define SP_INC_203 204 +#define SP_INC_204 205 +#define SP_INC_205 206 +#define SP_INC_206 207 +#define SP_INC_207 208 +#define SP_INC_208 209 +#define SP_INC_209 210 +#define SP_INC_210 211 +#define SP_INC_211 212 +#define SP_INC_212 213 +#define SP_INC_213 214 +#define SP_INC_214 215 +#define SP_INC_215 216 +#define SP_INC_216 217 +#define SP_INC_217 218 +#define SP_INC_218 219 +#define SP_INC_219 220 +#define SP_INC_220 221 +#define SP_INC_221 222 +#define SP_INC_222 223 +#define SP_INC_223 224 +#define SP_INC_224 225 +#define SP_INC_225 226 +#define SP_INC_226 227 +#define SP_INC_227 228 +#define SP_INC_228 229 +#define SP_INC_229 230 +#define SP_INC_230 231 +#define SP_INC_231 232 +#define SP_INC_232 233 +#define SP_INC_233 234 +#define SP_INC_234 235 +#define SP_INC_235 236 +#define SP_INC_236 237 +#define SP_INC_237 238 +#define SP_INC_238 239 +#define SP_INC_239 240 +#define SP_INC_240 241 +#define SP_INC_241 242 +#define SP_INC_242 243 +#define SP_INC_243 244 +#define SP_INC_244 245 +#define SP_INC_245 246 +#define SP_INC_246 247 +#define SP_INC_247 248 +#define SP_INC_248 249 +#define SP_INC_249 250 +#define SP_INC_250 251 +#define SP_INC_251 252 +#define SP_INC_252 253 +#define SP_INC_253 254 +#define SP_INC_254 255 + +#ifdef __cplusplus +} +#endif +#endif /* _UTILS_INCREMENT_MACRO_H */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/utils/include/utils_list.h b/prototype/firmware/I2C_scanner/I2C_scanner/hal/utils/include/utils_list.h new file mode 100644 index 00000000..977e8cca --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/utils/include/utils_list.h @@ -0,0 +1,164 @@ +/** + * \file + * + * \brief List declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_LIST_H_INCLUDED +#define _UTILS_LIST_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_utils_list + * + * @{ + */ + +#include + +/** + * \brief List element type + */ +struct list_element { + struct list_element *next; +}; + +/** + * \brief List head type + */ +struct list_descriptor { + struct list_element *head; +}; + +/** + * \brief Reset list + * + * \param[in] list The pointer to a list descriptor + */ +static inline void list_reset(struct list_descriptor *const list) +{ + list->head = NULL; +} + +/** + * \brief Retrieve list head + * + * \param[in] list The pointer to a list descriptor + * + * \return A pointer to the head of the given list or NULL if the list is + * empty + */ +static inline void *list_get_head(const struct list_descriptor *const list) +{ + return (void *)list->head; +} + +/** + * \brief Retrieve next list head + * + * \param[in] list The pointer to a list element + * + * \return A pointer to the next list element or NULL if there is not next + * element + */ +static inline void *list_get_next_element(const void *const element) +{ + return element ? ((struct list_element *)element)->next : NULL; +} + +/** + * \brief Insert an element as list head + * + * \param[in] list The pointer to a list element + * \param[in] element An element to insert to the given list + */ +void list_insert_as_head(struct list_descriptor *const list, void *const element); + +/** + * \brief Insert an element after the given list element + * + * \param[in] after An element to insert after + * \param[in] element Element to insert to the given list + */ +void list_insert_after(void *const after, void *const element); + +/** + * \brief Insert an element at list end + * + * \param[in] after An element to insert after + * \param[in] element Element to insert to the given list + */ +void list_insert_at_end(struct list_descriptor *const list, void *const element); + +/** + * \brief Check whether an element belongs to a list + * + * \param[in] list The pointer to a list + * \param[in] element An element to check + * + * \return The result of checking + * \retval true If the given element is an element of the given list + * \retval false Otherwise + */ +bool is_list_element(const struct list_descriptor *const list, const void *const element); + +/** + * \brief Removes list head + * + * This function removes the list head and sets the next element after the list + * head as a new list head. + * + * \param[in] list The pointer to a list + * + * \return The pointer to the new list head of NULL if the list head is NULL + */ +void *list_remove_head(struct list_descriptor *const list); + +/** + * \brief Removes the list element + * + * \param[in] list The pointer to a list + * \param[in] element An element to remove + * + * \return The result of element removing + * \retval true The given element is removed from the given list + * \retval false The given element is not an element of the given list + */ +bool list_delete_element(struct list_descriptor *const list, const void *const element); + +/**@}*/ + +#ifdef __cplusplus +} +#endif +#endif /* _UTILS_LIST_H_INCLUDED */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/utils/include/utils_repeat_macro.h b/prototype/firmware/I2C_scanner/I2C_scanner/hal/utils/include/utils_repeat_macro.h new file mode 100644 index 00000000..89e6f52d --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/utils/include/utils_repeat_macro.h @@ -0,0 +1,322 @@ +/** + * \file + * + * \brief Repeat macro. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_REPEAT_MACRO_H +#define _UTILS_REPEAT_MACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * \brief Sequently repeates specified macro for n times (255 max). + * + * Specified macro shall have two arguments: macro(arg, i) + * arg - user defined argument, which have the same value for all iterations. + * i - iteration number; numbering begins from zero and increments on each + * iteration. + * + * \param[in] macro - macro to be repeated + * \param[in] arg - user defined argument for repeated macro + * \param[in] n - total number of iterations (255 max) + */ +#define REPEAT_MACRO(macro, arg, n) REPEAT_MACRO_I(macro, arg, n) + +/* + * \brief Second level is needed to get integer literal from "n" if it is + * defined as macro + */ +#define REPEAT_MACRO_I(macro, arg, n) REPEAT##n(macro, arg, 0) + +#define REPEAT1(macro, arg, n) macro(arg, n) +#define REPEAT2(macro, arg, n) macro(arg, n) REPEAT1(macro, arg, INC_VALUE(n)) +#define REPEAT3(macro, arg, n) macro(arg, n) REPEAT2(macro, arg, INC_VALUE(n)) +#define REPEAT4(macro, arg, n) macro(arg, n) REPEAT3(macro, arg, INC_VALUE(n)) +#define REPEAT5(macro, arg, n) macro(arg, n) REPEAT4(macro, arg, INC_VALUE(n)) +#define REPEAT6(macro, arg, n) macro(arg, n) REPEAT5(macro, arg, INC_VALUE(n)) +#define REPEAT7(macro, arg, n) macro(arg, n) REPEAT6(macro, arg, INC_VALUE(n)) +#define REPEAT8(macro, arg, n) macro(arg, n) REPEAT7(macro, arg, INC_VALUE(n)) +#define REPEAT9(macro, arg, n) macro(arg, n) REPEAT8(macro, arg, INC_VALUE(n)) +#define REPEAT10(macro, arg, n) macro(arg, n) REPEAT9(macro, arg, INC_VALUE(n)) +#define REPEAT11(macro, arg, n) macro(arg, n) REPEAT10(macro, arg, INC_VALUE(n)) +#define REPEAT12(macro, arg, n) macro(arg, n) REPEAT11(macro, arg, INC_VALUE(n)) +#define REPEAT13(macro, arg, n) macro(arg, n) REPEAT12(macro, arg, INC_VALUE(n)) +#define REPEAT14(macro, arg, n) macro(arg, n) REPEAT13(macro, arg, INC_VALUE(n)) +#define REPEAT15(macro, arg, n) macro(arg, n) REPEAT14(macro, arg, INC_VALUE(n)) +#define REPEAT16(macro, arg, n) macro(arg, n) REPEAT15(macro, arg, INC_VALUE(n)) +#define REPEAT17(macro, arg, n) macro(arg, n) REPEAT16(macro, arg, INC_VALUE(n)) +#define REPEAT18(macro, arg, n) macro(arg, n) REPEAT17(macro, arg, INC_VALUE(n)) +#define REPEAT19(macro, arg, n) macro(arg, n) REPEAT18(macro, arg, INC_VALUE(n)) +#define REPEAT20(macro, arg, n) macro(arg, n) REPEAT19(macro, arg, INC_VALUE(n)) +#define REPEAT21(macro, arg, n) macro(arg, n) REPEAT20(macro, arg, INC_VALUE(n)) +#define REPEAT22(macro, arg, n) macro(arg, n) REPEAT21(macro, arg, INC_VALUE(n)) +#define REPEAT23(macro, arg, n) macro(arg, n) REPEAT22(macro, arg, INC_VALUE(n)) +#define REPEAT24(macro, arg, n) macro(arg, n) REPEAT23(macro, arg, INC_VALUE(n)) +#define REPEAT25(macro, arg, n) macro(arg, n) REPEAT24(macro, arg, INC_VALUE(n)) +#define REPEAT26(macro, arg, n) macro(arg, n) REPEAT25(macro, arg, INC_VALUE(n)) +#define REPEAT27(macro, arg, n) macro(arg, n) REPEAT26(macro, arg, INC_VALUE(n)) +#define REPEAT28(macro, arg, n) macro(arg, n) REPEAT27(macro, arg, INC_VALUE(n)) +#define REPEAT29(macro, arg, n) macro(arg, n) REPEAT28(macro, arg, INC_VALUE(n)) +#define REPEAT30(macro, arg, n) macro(arg, n) REPEAT29(macro, arg, INC_VALUE(n)) +#define REPEAT31(macro, arg, n) macro(arg, n) REPEAT30(macro, arg, INC_VALUE(n)) +#define REPEAT32(macro, arg, n) macro(arg, n) REPEAT31(macro, arg, INC_VALUE(n)) +#define REPEAT33(macro, arg, n) macro(arg, n) REPEAT32(macro, arg, INC_VALUE(n)) +#define REPEAT34(macro, arg, n) macro(arg, n) REPEAT33(macro, arg, INC_VALUE(n)) +#define REPEAT35(macro, arg, n) macro(arg, n) REPEAT34(macro, arg, INC_VALUE(n)) +#define REPEAT36(macro, arg, n) macro(arg, n) REPEAT35(macro, arg, INC_VALUE(n)) +#define REPEAT37(macro, arg, n) macro(arg, n) REPEAT36(macro, arg, INC_VALUE(n)) +#define REPEAT38(macro, arg, n) macro(arg, n) REPEAT37(macro, arg, INC_VALUE(n)) +#define REPEAT39(macro, arg, n) macro(arg, n) REPEAT38(macro, arg, INC_VALUE(n)) +#define REPEAT40(macro, arg, n) macro(arg, n) REPEAT39(macro, arg, INC_VALUE(n)) +#define REPEAT41(macro, arg, n) macro(arg, n) REPEAT40(macro, arg, INC_VALUE(n)) +#define REPEAT42(macro, arg, n) macro(arg, n) REPEAT41(macro, arg, INC_VALUE(n)) +#define REPEAT43(macro, arg, n) macro(arg, n) REPEAT42(macro, arg, INC_VALUE(n)) +#define REPEAT44(macro, arg, n) macro(arg, n) REPEAT43(macro, arg, INC_VALUE(n)) +#define REPEAT45(macro, arg, n) macro(arg, n) REPEAT44(macro, arg, INC_VALUE(n)) +#define REPEAT46(macro, arg, n) macro(arg, n) REPEAT45(macro, arg, INC_VALUE(n)) +#define REPEAT47(macro, arg, n) macro(arg, n) REPEAT46(macro, arg, INC_VALUE(n)) +#define REPEAT48(macro, arg, n) macro(arg, n) REPEAT47(macro, arg, INC_VALUE(n)) +#define REPEAT49(macro, arg, n) macro(arg, n) REPEAT48(macro, arg, INC_VALUE(n)) +#define REPEAT50(macro, arg, n) macro(arg, n) REPEAT49(macro, arg, INC_VALUE(n)) +#define REPEAT51(macro, arg, n) macro(arg, n) REPEAT50(macro, arg, INC_VALUE(n)) +#define REPEAT52(macro, arg, n) macro(arg, n) REPEAT51(macro, arg, INC_VALUE(n)) +#define REPEAT53(macro, arg, n) macro(arg, n) REPEAT52(macro, arg, INC_VALUE(n)) +#define REPEAT54(macro, arg, n) macro(arg, n) REPEAT53(macro, arg, INC_VALUE(n)) +#define REPEAT55(macro, arg, n) macro(arg, n) REPEAT54(macro, arg, INC_VALUE(n)) +#define REPEAT56(macro, arg, n) macro(arg, n) REPEAT55(macro, arg, INC_VALUE(n)) +#define REPEAT57(macro, arg, n) macro(arg, n) REPEAT56(macro, arg, INC_VALUE(n)) +#define REPEAT58(macro, arg, n) macro(arg, n) REPEAT57(macro, arg, INC_VALUE(n)) +#define REPEAT59(macro, arg, n) macro(arg, n) REPEAT58(macro, arg, INC_VALUE(n)) +#define REPEAT60(macro, arg, n) macro(arg, n) REPEAT59(macro, arg, INC_VALUE(n)) +#define REPEAT61(macro, arg, n) macro(arg, n) REPEAT60(macro, arg, INC_VALUE(n)) +#define REPEAT62(macro, arg, n) macro(arg, n) REPEAT61(macro, arg, INC_VALUE(n)) +#define REPEAT63(macro, arg, n) macro(arg, n) REPEAT62(macro, arg, INC_VALUE(n)) +#define REPEAT64(macro, arg, n) macro(arg, n) REPEAT63(macro, arg, INC_VALUE(n)) +#define REPEAT65(macro, arg, n) macro(arg, n) REPEAT64(macro, arg, INC_VALUE(n)) +#define REPEAT66(macro, arg, n) macro(arg, n) REPEAT65(macro, arg, INC_VALUE(n)) +#define REPEAT67(macro, arg, n) macro(arg, n) REPEAT66(macro, arg, INC_VALUE(n)) +#define REPEAT68(macro, arg, n) macro(arg, n) REPEAT67(macro, arg, INC_VALUE(n)) +#define REPEAT69(macro, arg, n) macro(arg, n) REPEAT68(macro, arg, INC_VALUE(n)) +#define REPEAT70(macro, arg, n) macro(arg, n) REPEAT69(macro, arg, INC_VALUE(n)) +#define REPEAT71(macro, arg, n) macro(arg, n) REPEAT70(macro, arg, INC_VALUE(n)) +#define REPEAT72(macro, arg, n) macro(arg, n) REPEAT71(macro, arg, INC_VALUE(n)) +#define REPEAT73(macro, arg, n) macro(arg, n) REPEAT72(macro, arg, INC_VALUE(n)) +#define REPEAT74(macro, arg, n) macro(arg, n) REPEAT73(macro, arg, INC_VALUE(n)) +#define REPEAT75(macro, arg, n) macro(arg, n) REPEAT74(macro, arg, INC_VALUE(n)) +#define REPEAT76(macro, arg, n) macro(arg, n) REPEAT75(macro, arg, INC_VALUE(n)) +#define REPEAT77(macro, arg, n) macro(arg, n) REPEAT76(macro, arg, INC_VALUE(n)) +#define REPEAT78(macro, arg, n) macro(arg, n) REPEAT77(macro, arg, INC_VALUE(n)) +#define REPEAT79(macro, arg, n) macro(arg, n) REPEAT78(macro, arg, INC_VALUE(n)) +#define REPEAT80(macro, arg, n) macro(arg, n) REPEAT79(macro, arg, INC_VALUE(n)) +#define REPEAT81(macro, arg, n) macro(arg, n) REPEAT80(macro, arg, INC_VALUE(n)) +#define REPEAT82(macro, arg, n) macro(arg, n) REPEAT81(macro, arg, INC_VALUE(n)) +#define REPEAT83(macro, arg, n) macro(arg, n) REPEAT82(macro, arg, INC_VALUE(n)) +#define REPEAT84(macro, arg, n) macro(arg, n) REPEAT83(macro, arg, INC_VALUE(n)) +#define REPEAT85(macro, arg, n) macro(arg, n) REPEAT84(macro, arg, INC_VALUE(n)) +#define REPEAT86(macro, arg, n) macro(arg, n) REPEAT85(macro, arg, INC_VALUE(n)) +#define REPEAT87(macro, arg, n) macro(arg, n) REPEAT86(macro, arg, INC_VALUE(n)) +#define REPEAT88(macro, arg, n) macro(arg, n) REPEAT87(macro, arg, INC_VALUE(n)) +#define REPEAT89(macro, arg, n) macro(arg, n) REPEAT88(macro, arg, INC_VALUE(n)) +#define REPEAT90(macro, arg, n) macro(arg, n) REPEAT89(macro, arg, INC_VALUE(n)) +#define REPEAT91(macro, arg, n) macro(arg, n) REPEAT90(macro, arg, INC_VALUE(n)) +#define REPEAT92(macro, arg, n) macro(arg, n) REPEAT91(macro, arg, INC_VALUE(n)) +#define REPEAT93(macro, arg, n) macro(arg, n) REPEAT92(macro, arg, INC_VALUE(n)) +#define REPEAT94(macro, arg, n) macro(arg, n) REPEAT93(macro, arg, INC_VALUE(n)) +#define REPEAT95(macro, arg, n) macro(arg, n) REPEAT94(macro, arg, INC_VALUE(n)) +#define REPEAT96(macro, arg, n) macro(arg, n) REPEAT95(macro, arg, INC_VALUE(n)) +#define REPEAT97(macro, arg, n) macro(arg, n) REPEAT96(macro, arg, INC_VALUE(n)) +#define REPEAT98(macro, arg, n) macro(arg, n) REPEAT97(macro, arg, INC_VALUE(n)) +#define REPEAT99(macro, arg, n) macro(arg, n) REPEAT98(macro, arg, INC_VALUE(n)) +#define REPEAT100(macro, arg, n) macro(arg, n) REPEAT99(macro, arg, INC_VALUE(n)) +#define REPEAT101(macro, arg, n) macro(arg, n) REPEAT100(macro, arg, INC_VALUE(n)) +#define REPEAT102(macro, arg, n) macro(arg, n) REPEAT101(macro, arg, INC_VALUE(n)) +#define REPEAT103(macro, arg, n) macro(arg, n) REPEAT102(macro, arg, INC_VALUE(n)) +#define REPEAT104(macro, arg, n) macro(arg, n) REPEAT103(macro, arg, INC_VALUE(n)) +#define REPEAT105(macro, arg, n) macro(arg, n) REPEAT104(macro, arg, INC_VALUE(n)) +#define REPEAT106(macro, arg, n) macro(arg, n) REPEAT105(macro, arg, INC_VALUE(n)) +#define REPEAT107(macro, arg, n) macro(arg, n) REPEAT106(macro, arg, INC_VALUE(n)) +#define REPEAT108(macro, arg, n) macro(arg, n) REPEAT107(macro, arg, INC_VALUE(n)) +#define REPEAT109(macro, arg, n) macro(arg, n) REPEAT108(macro, arg, INC_VALUE(n)) +#define REPEAT110(macro, arg, n) macro(arg, n) REPEAT109(macro, arg, INC_VALUE(n)) +#define REPEAT111(macro, arg, n) macro(arg, n) REPEAT110(macro, arg, INC_VALUE(n)) +#define REPEAT112(macro, arg, n) macro(arg, n) REPEAT111(macro, arg, INC_VALUE(n)) +#define REPEAT113(macro, arg, n) macro(arg, n) REPEAT112(macro, arg, INC_VALUE(n)) +#define REPEAT114(macro, arg, n) macro(arg, n) REPEAT113(macro, arg, INC_VALUE(n)) +#define REPEAT115(macro, arg, n) macro(arg, n) REPEAT114(macro, arg, INC_VALUE(n)) +#define REPEAT116(macro, arg, n) macro(arg, n) REPEAT115(macro, arg, INC_VALUE(n)) +#define REPEAT117(macro, arg, n) macro(arg, n) REPEAT116(macro, arg, INC_VALUE(n)) +#define REPEAT118(macro, arg, n) macro(arg, n) REPEAT117(macro, arg, INC_VALUE(n)) +#define REPEAT119(macro, arg, n) macro(arg, n) REPEAT118(macro, arg, INC_VALUE(n)) +#define REPEAT120(macro, arg, n) macro(arg, n) REPEAT119(macro, arg, INC_VALUE(n)) +#define REPEAT121(macro, arg, n) macro(arg, n) REPEAT120(macro, arg, INC_VALUE(n)) +#define REPEAT122(macro, arg, n) macro(arg, n) REPEAT121(macro, arg, INC_VALUE(n)) +#define REPEAT123(macro, arg, n) macro(arg, n) REPEAT122(macro, arg, INC_VALUE(n)) +#define REPEAT124(macro, arg, n) macro(arg, n) REPEAT123(macro, arg, INC_VALUE(n)) +#define REPEAT125(macro, arg, n) macro(arg, n) REPEAT124(macro, arg, INC_VALUE(n)) +#define REPEAT126(macro, arg, n) macro(arg, n) REPEAT125(macro, arg, INC_VALUE(n)) +#define REPEAT127(macro, arg, n) macro(arg, n) REPEAT126(macro, arg, INC_VALUE(n)) +#define REPEAT128(macro, arg, n) macro(arg, n) REPEAT127(macro, arg, INC_VALUE(n)) +#define REPEAT129(macro, arg, n) macro(arg, n) REPEAT128(macro, arg, INC_VALUE(n)) +#define REPEAT130(macro, arg, n) macro(arg, n) REPEAT129(macro, arg, INC_VALUE(n)) +#define REPEAT131(macro, arg, n) macro(arg, n) REPEAT130(macro, arg, INC_VALUE(n)) +#define REPEAT132(macro, arg, n) macro(arg, n) REPEAT131(macro, arg, INC_VALUE(n)) +#define REPEAT133(macro, arg, n) macro(arg, n) REPEAT132(macro, arg, INC_VALUE(n)) +#define REPEAT134(macro, arg, n) macro(arg, n) REPEAT133(macro, arg, INC_VALUE(n)) +#define REPEAT135(macro, arg, n) macro(arg, n) REPEAT134(macro, arg, INC_VALUE(n)) +#define REPEAT136(macro, arg, n) macro(arg, n) REPEAT135(macro, arg, INC_VALUE(n)) +#define REPEAT137(macro, arg, n) macro(arg, n) REPEAT136(macro, arg, INC_VALUE(n)) +#define REPEAT138(macro, arg, n) macro(arg, n) REPEAT137(macro, arg, INC_VALUE(n)) +#define REPEAT139(macro, arg, n) macro(arg, n) REPEAT138(macro, arg, INC_VALUE(n)) +#define REPEAT140(macro, arg, n) macro(arg, n) REPEAT139(macro, arg, INC_VALUE(n)) +#define REPEAT141(macro, arg, n) macro(arg, n) REPEAT140(macro, arg, INC_VALUE(n)) +#define REPEAT142(macro, arg, n) macro(arg, n) REPEAT141(macro, arg, INC_VALUE(n)) +#define REPEAT143(macro, arg, n) macro(arg, n) REPEAT142(macro, arg, INC_VALUE(n)) +#define REPEAT144(macro, arg, n) macro(arg, n) REPEAT143(macro, arg, INC_VALUE(n)) +#define REPEAT145(macro, arg, n) macro(arg, n) REPEAT144(macro, arg, INC_VALUE(n)) +#define REPEAT146(macro, arg, n) macro(arg, n) REPEAT145(macro, arg, INC_VALUE(n)) +#define REPEAT147(macro, arg, n) macro(arg, n) REPEAT146(macro, arg, INC_VALUE(n)) +#define REPEAT148(macro, arg, n) macro(arg, n) REPEAT147(macro, arg, INC_VALUE(n)) +#define REPEAT149(macro, arg, n) macro(arg, n) REPEAT148(macro, arg, INC_VALUE(n)) +#define REPEAT150(macro, arg, n) macro(arg, n) REPEAT149(macro, arg, INC_VALUE(n)) +#define REPEAT151(macro, arg, n) macro(arg, n) REPEAT150(macro, arg, INC_VALUE(n)) +#define REPEAT152(macro, arg, n) macro(arg, n) REPEAT151(macro, arg, INC_VALUE(n)) +#define REPEAT153(macro, arg, n) macro(arg, n) REPEAT152(macro, arg, INC_VALUE(n)) +#define REPEAT154(macro, arg, n) macro(arg, n) REPEAT153(macro, arg, INC_VALUE(n)) +#define REPEAT155(macro, arg, n) macro(arg, n) REPEAT154(macro, arg, INC_VALUE(n)) +#define REPEAT156(macro, arg, n) macro(arg, n) REPEAT155(macro, arg, INC_VALUE(n)) +#define REPEAT157(macro, arg, n) macro(arg, n) REPEAT156(macro, arg, INC_VALUE(n)) +#define REPEAT158(macro, arg, n) macro(arg, n) REPEAT157(macro, arg, INC_VALUE(n)) +#define REPEAT159(macro, arg, n) macro(arg, n) REPEAT158(macro, arg, INC_VALUE(n)) +#define REPEAT160(macro, arg, n) macro(arg, n) REPEAT159(macro, arg, INC_VALUE(n)) +#define REPEAT161(macro, arg, n) macro(arg, n) REPEAT160(macro, arg, INC_VALUE(n)) +#define REPEAT162(macro, arg, n) macro(arg, n) REPEAT161(macro, arg, INC_VALUE(n)) +#define REPEAT163(macro, arg, n) macro(arg, n) REPEAT162(macro, arg, INC_VALUE(n)) +#define REPEAT164(macro, arg, n) macro(arg, n) REPEAT163(macro, arg, INC_VALUE(n)) +#define REPEAT165(macro, arg, n) macro(arg, n) REPEAT164(macro, arg, INC_VALUE(n)) +#define REPEAT166(macro, arg, n) macro(arg, n) REPEAT165(macro, arg, INC_VALUE(n)) +#define REPEAT167(macro, arg, n) macro(arg, n) REPEAT166(macro, arg, INC_VALUE(n)) +#define REPEAT168(macro, arg, n) macro(arg, n) REPEAT167(macro, arg, INC_VALUE(n)) +#define REPEAT169(macro, arg, n) macro(arg, n) REPEAT168(macro, arg, INC_VALUE(n)) +#define REPEAT170(macro, arg, n) macro(arg, n) REPEAT169(macro, arg, INC_VALUE(n)) +#define REPEAT171(macro, arg, n) macro(arg, n) REPEAT170(macro, arg, INC_VALUE(n)) +#define REPEAT172(macro, arg, n) macro(arg, n) REPEAT171(macro, arg, INC_VALUE(n)) +#define REPEAT173(macro, arg, n) macro(arg, n) REPEAT172(macro, arg, INC_VALUE(n)) +#define REPEAT174(macro, arg, n) macro(arg, n) REPEAT173(macro, arg, INC_VALUE(n)) +#define REPEAT175(macro, arg, n) macro(arg, n) REPEAT174(macro, arg, INC_VALUE(n)) +#define REPEAT176(macro, arg, n) macro(arg, n) REPEAT175(macro, arg, INC_VALUE(n)) +#define REPEAT177(macro, arg, n) macro(arg, n) REPEAT176(macro, arg, INC_VALUE(n)) +#define REPEAT178(macro, arg, n) macro(arg, n) REPEAT177(macro, arg, INC_VALUE(n)) +#define REPEAT179(macro, arg, n) macro(arg, n) REPEAT178(macro, arg, INC_VALUE(n)) +#define REPEAT180(macro, arg, n) macro(arg, n) REPEAT179(macro, arg, INC_VALUE(n)) +#define REPEAT181(macro, arg, n) macro(arg, n) REPEAT180(macro, arg, INC_VALUE(n)) +#define REPEAT182(macro, arg, n) macro(arg, n) REPEAT181(macro, arg, INC_VALUE(n)) +#define REPEAT183(macro, arg, n) macro(arg, n) REPEAT182(macro, arg, INC_VALUE(n)) +#define REPEAT184(macro, arg, n) macro(arg, n) REPEAT183(macro, arg, INC_VALUE(n)) +#define REPEAT185(macro, arg, n) macro(arg, n) REPEAT184(macro, arg, INC_VALUE(n)) +#define REPEAT186(macro, arg, n) macro(arg, n) REPEAT185(macro, arg, INC_VALUE(n)) +#define REPEAT187(macro, arg, n) macro(arg, n) REPEAT186(macro, arg, INC_VALUE(n)) +#define REPEAT188(macro, arg, n) macro(arg, n) REPEAT187(macro, arg, INC_VALUE(n)) +#define REPEAT189(macro, arg, n) macro(arg, n) REPEAT188(macro, arg, INC_VALUE(n)) +#define REPEAT190(macro, arg, n) macro(arg, n) REPEAT189(macro, arg, INC_VALUE(n)) +#define REPEAT191(macro, arg, n) macro(arg, n) REPEAT190(macro, arg, INC_VALUE(n)) +#define REPEAT192(macro, arg, n) macro(arg, n) REPEAT191(macro, arg, INC_VALUE(n)) +#define REPEAT193(macro, arg, n) macro(arg, n) REPEAT192(macro, arg, INC_VALUE(n)) +#define REPEAT194(macro, arg, n) macro(arg, n) REPEAT193(macro, arg, INC_VALUE(n)) +#define REPEAT195(macro, arg, n) macro(arg, n) REPEAT194(macro, arg, INC_VALUE(n)) +#define REPEAT196(macro, arg, n) macro(arg, n) REPEAT195(macro, arg, INC_VALUE(n)) +#define REPEAT197(macro, arg, n) macro(arg, n) REPEAT196(macro, arg, INC_VALUE(n)) +#define REPEAT198(macro, arg, n) macro(arg, n) REPEAT197(macro, arg, INC_VALUE(n)) +#define REPEAT199(macro, arg, n) macro(arg, n) REPEAT198(macro, arg, INC_VALUE(n)) +#define REPEAT200(macro, arg, n) macro(arg, n) REPEAT199(macro, arg, INC_VALUE(n)) +#define REPEAT201(macro, arg, n) macro(arg, n) REPEAT200(macro, arg, INC_VALUE(n)) +#define REPEAT202(macro, arg, n) macro(arg, n) REPEAT201(macro, arg, INC_VALUE(n)) +#define REPEAT203(macro, arg, n) macro(arg, n) REPEAT202(macro, arg, INC_VALUE(n)) +#define REPEAT204(macro, arg, n) macro(arg, n) REPEAT203(macro, arg, INC_VALUE(n)) +#define REPEAT205(macro, arg, n) macro(arg, n) REPEAT204(macro, arg, INC_VALUE(n)) +#define REPEAT206(macro, arg, n) macro(arg, n) REPEAT205(macro, arg, INC_VALUE(n)) +#define REPEAT207(macro, arg, n) macro(arg, n) REPEAT206(macro, arg, INC_VALUE(n)) +#define REPEAT208(macro, arg, n) macro(arg, n) REPEAT207(macro, arg, INC_VALUE(n)) +#define REPEAT209(macro, arg, n) macro(arg, n) REPEAT208(macro, arg, INC_VALUE(n)) +#define REPEAT210(macro, arg, n) macro(arg, n) REPEAT209(macro, arg, INC_VALUE(n)) +#define REPEAT211(macro, arg, n) macro(arg, n) REPEAT210(macro, arg, INC_VALUE(n)) +#define REPEAT212(macro, arg, n) macro(arg, n) REPEAT211(macro, arg, INC_VALUE(n)) +#define REPEAT213(macro, arg, n) macro(arg, n) REPEAT212(macro, arg, INC_VALUE(n)) +#define REPEAT214(macro, arg, n) macro(arg, n) REPEAT213(macro, arg, INC_VALUE(n)) +#define REPEAT215(macro, arg, n) macro(arg, n) REPEAT214(macro, arg, INC_VALUE(n)) +#define REPEAT216(macro, arg, n) macro(arg, n) REPEAT215(macro, arg, INC_VALUE(n)) +#define REPEAT217(macro, arg, n) macro(arg, n) REPEAT216(macro, arg, INC_VALUE(n)) +#define REPEAT218(macro, arg, n) macro(arg, n) REPEAT217(macro, arg, INC_VALUE(n)) +#define REPEAT219(macro, arg, n) macro(arg, n) REPEAT218(macro, arg, INC_VALUE(n)) +#define REPEAT220(macro, arg, n) macro(arg, n) REPEAT219(macro, arg, INC_VALUE(n)) +#define REPEAT221(macro, arg, n) macro(arg, n) REPEAT220(macro, arg, INC_VALUE(n)) +#define REPEAT222(macro, arg, n) macro(arg, n) REPEAT221(macro, arg, INC_VALUE(n)) +#define REPEAT223(macro, arg, n) macro(arg, n) REPEAT222(macro, arg, INC_VALUE(n)) +#define REPEAT224(macro, arg, n) macro(arg, n) REPEAT223(macro, arg, INC_VALUE(n)) +#define REPEAT225(macro, arg, n) macro(arg, n) REPEAT224(macro, arg, INC_VALUE(n)) +#define REPEAT226(macro, arg, n) macro(arg, n) REPEAT225(macro, arg, INC_VALUE(n)) +#define REPEAT227(macro, arg, n) macro(arg, n) REPEAT226(macro, arg, INC_VALUE(n)) +#define REPEAT228(macro, arg, n) macro(arg, n) REPEAT227(macro, arg, INC_VALUE(n)) +#define REPEAT229(macro, arg, n) macro(arg, n) REPEAT228(macro, arg, INC_VALUE(n)) +#define REPEAT230(macro, arg, n) macro(arg, n) REPEAT229(macro, arg, INC_VALUE(n)) +#define REPEAT231(macro, arg, n) macro(arg, n) REPEAT230(macro, arg, INC_VALUE(n)) +#define REPEAT232(macro, arg, n) macro(arg, n) REPEAT231(macro, arg, INC_VALUE(n)) +#define REPEAT233(macro, arg, n) macro(arg, n) REPEAT232(macro, arg, INC_VALUE(n)) +#define REPEAT234(macro, arg, n) macro(arg, n) REPEAT233(macro, arg, INC_VALUE(n)) +#define REPEAT235(macro, arg, n) macro(arg, n) REPEAT234(macro, arg, INC_VALUE(n)) +#define REPEAT236(macro, arg, n) macro(arg, n) REPEAT235(macro, arg, INC_VALUE(n)) +#define REPEAT237(macro, arg, n) macro(arg, n) REPEAT236(macro, arg, INC_VALUE(n)) +#define REPEAT238(macro, arg, n) macro(arg, n) REPEAT237(macro, arg, INC_VALUE(n)) +#define REPEAT239(macro, arg, n) macro(arg, n) REPEAT238(macro, arg, INC_VALUE(n)) +#define REPEAT240(macro, arg, n) macro(arg, n) REPEAT239(macro, arg, INC_VALUE(n)) +#define REPEAT241(macro, arg, n) macro(arg, n) REPEAT240(macro, arg, INC_VALUE(n)) +#define REPEAT242(macro, arg, n) macro(arg, n) REPEAT241(macro, arg, INC_VALUE(n)) +#define REPEAT243(macro, arg, n) macro(arg, n) REPEAT242(macro, arg, INC_VALUE(n)) +#define REPEAT244(macro, arg, n) macro(arg, n) REPEAT243(macro, arg, INC_VALUE(n)) +#define REPEAT245(macro, arg, n) macro(arg, n) REPEAT244(macro, arg, INC_VALUE(n)) +#define REPEAT246(macro, arg, n) macro(arg, n) REPEAT245(macro, arg, INC_VALUE(n)) +#define REPEAT247(macro, arg, n) macro(arg, n) REPEAT246(macro, arg, INC_VALUE(n)) +#define REPEAT248(macro, arg, n) macro(arg, n) REPEAT247(macro, arg, INC_VALUE(n)) +#define REPEAT249(macro, arg, n) macro(arg, n) REPEAT248(macro, arg, INC_VALUE(n)) +#define REPEAT250(macro, arg, n) macro(arg, n) REPEAT249(macro, arg, INC_VALUE(n)) +#define REPEAT251(macro, arg, n) macro(arg, n) REPEAT250(macro, arg, INC_VALUE(n)) +#define REPEAT252(macro, arg, n) macro(arg, n) REPEAT251(macro, arg, INC_VALUE(n)) +#define REPEAT253(macro, arg, n) macro(arg, n) REPEAT252(macro, arg, INC_VALUE(n)) +#define REPEAT254(macro, arg, n) macro(arg, n) REPEAT253(macro, arg, INC_VALUE(n)) +#define REPEAT255(macro, arg, n) macro(arg, n) REPEAT254(macro, arg, INC_VALUE(n)) + +#ifdef __cplusplus +} +#endif + +#include +#endif /* _UTILS_REPEAT_MACRO_H */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/utils/src/utils_assert.c b/prototype/firmware/I2C_scanner/I2C_scanner/hal/utils/src/utils_assert.c new file mode 100644 index 00000000..b376c970 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/utils/src/utils_assert.c @@ -0,0 +1,46 @@ +/** + * \file + * + * \brief Asserts related functionality. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include + +/** + * \brief Assert function + */ +void assert(const bool condition, const char *const file, const int line) +{ + if (!(condition)) { + __asm("BKPT #0"); + } + (void)file; + (void)line; +} diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/utils/src/utils_event.c b/prototype/firmware/I2C_scanner/I2C_scanner/hal/utils/src/utils_event.c new file mode 100644 index 00000000..d1af9d0c --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/utils/src/utils_event.c @@ -0,0 +1,125 @@ +/** + * \file + * + * \brief Events implementation. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +#define EVENT_WORD_BITS (sizeof(event_word_t) * 8) + +static struct list_descriptor events; +static uint8_t subscribed[EVENT_MASK_SIZE]; + +int32_t event_subscribe(struct event *const event, const event_id_t id, event_cb_t cb) +{ + /* get byte and bit number of the given event in the event mask */ + const uint8_t position = id >> 3; + const uint8_t mask = 1 << (id & 0x7); + + ASSERT(event && cb && (id < EVENT_MAX_AMOUNT)); + + if (event->mask[position] & mask) { + return ERR_NO_CHANGE; /* Already subscribed */ + } + + if (!is_list_element(&events, event)) { + memset(event->mask, 0, EVENT_MASK_SIZE); + list_insert_as_head(&events, event); + } + event->cb = cb; + event->mask[position] |= mask; + + subscribed[position] |= mask; + + return ERR_NONE; +} + +int32_t event_unsubscribe(struct event *const event, const event_id_t id) +{ + /* get byte and bit number of the given event in the event mask */ + const uint8_t position = id >> 3; + const uint8_t mask = 1 << (id & 0x7); + const struct event *current; + uint8_t i; + + ASSERT(event && (id < EVENT_MAX_AMOUNT)); + + if (!(event->mask[position] & mask)) { + return ERR_NO_CHANGE; /* Already unsubscribed */ + } + + event->mask[position] &= ~mask; + + /* Check if there are more subscribers */ + for ((current = (const struct event *)list_get_head(&events)); current; + current = (const struct event *)list_get_next_element(current)) { + if (current->mask[position] & mask) { + break; + } + } + if (!current) { + subscribed[position] &= ~mask; + } + + /* Remove event from the list. Can be unsave, document it! */ + for (i = 0; i < ARRAY_SIZE(event->mask); i++) { + if (event->mask[i]) { + return ERR_NONE; + } + } + list_delete_element(&events, event); + + return ERR_NONE; +} + +void event_post(const event_id_t id, const event_data_t data) +{ + /* get byte and bit number of the given event in the event mask */ + const uint8_t position = id >> 3; + const uint8_t mask = 1 << (id & 0x7); + const struct event *current; + + ASSERT((id < EVENT_MAX_AMOUNT)); + + if (!(subscribed[position] & mask)) { + return; /* No subscribers */ + } + + /* Find all subscribers */ + for ((current = (const struct event *)list_get_head(&events)); current; + current = (const struct event *)list_get_next_element(current)) { + if (current->mask[position] & mask) { + current->cb(id, data); + } + } +} diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/utils/src/utils_list.c b/prototype/firmware/I2C_scanner/I2C_scanner/hal/utils/src/utils_list.c new file mode 100644 index 00000000..4006a019 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/utils/src/utils_list.c @@ -0,0 +1,136 @@ +/** + * \file + * + * \brief List functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** + * \brief Check whether element belongs to list + */ +bool is_list_element(const struct list_descriptor *const list, const void *const element) +{ + struct list_element *it; + for (it = list->head; it; it = it->next) { + if (it == element) { + return true; + } + } + + return false; +} + +/** + * \brief Insert an element as list head + */ +void list_insert_as_head(struct list_descriptor *const list, void *const element) +{ + ASSERT(!is_list_element(list, element)); + + ((struct list_element *)element)->next = list->head; + list->head = (struct list_element *)element; +} + +/** + * \brief Insert an element after the given list element + */ +void list_insert_after(void *const after, void *const element) +{ + ((struct list_element *)element)->next = ((struct list_element *)after)->next; + ((struct list_element *)after)->next = (struct list_element *)element; +} + +/** + * \brief Insert an element at list end + */ +void list_insert_at_end(struct list_descriptor *const list, void *const element) +{ + struct list_element *it = list->head; + + ASSERT(!is_list_element(list, element)); + + if (!list->head) { + list->head = (struct list_element *)element; + ((struct list_element *)element)->next = NULL; + return; + } + + while (it->next) { + it = it->next; + } + it->next = (struct list_element *)element; + ((struct list_element *)element)->next = NULL; +} + +/** + * \brief Removes list head + */ +void *list_remove_head(struct list_descriptor *const list) +{ + if (list->head) { + struct list_element *tmp = list->head; + + list->head = list->head->next; + return (void *)tmp; + } + + return NULL; +} + +/** + * \brief Removes list element + */ +bool list_delete_element(struct list_descriptor *const list, const void *const element) +{ + if (!element) { + return false; + } + + if (list->head == element) { + list->head = list->head->next; + return true; + } else { + struct list_element *it = list->head; + + while (it && it->next != element) { + it = it->next; + } + if (it) { + it->next = ((struct list_element *)element)->next; + return true; + } + } + + return false; +} + +//@} diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hal/utils/src/utils_syscalls.c b/prototype/firmware/I2C_scanner/I2C_scanner/hal/utils/src/utils_syscalls.c new file mode 100644 index 00000000..79e2f1fe --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hal/utils/src/utils_syscalls.c @@ -0,0 +1,152 @@ +/** + * \file + * + * \brief Syscalls for SAM0 (GCC). + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#undef errno +extern int errno; +extern int _end; + +extern caddr_t _sbrk(int incr); +extern int link(char *old, char *_new); +extern int _close(int file); +extern int _fstat(int file, struct stat *st); +extern int _isatty(int file); +extern int _lseek(int file, int ptr, int dir); +extern void _exit(int status); +extern void _kill(int pid, int sig); +extern int _getpid(void); + +/** + * \brief Replacement of C library of _sbrk + */ +extern caddr_t _sbrk(int incr) +{ + static unsigned char *heap = NULL; + unsigned char * prev_heap; + + if (heap == NULL) { + heap = (unsigned char *)&_end; + } + prev_heap = heap; + + heap += incr; + + return (caddr_t)prev_heap; +} + +/** + * \brief Replacement of C library of link + */ +extern int link(char *old, char *_new) +{ + (void)old, (void)_new; + return -1; +} + +/** + * \brief Replacement of C library of _close + */ +extern int _close(int file) +{ + (void)file; + return -1; +} + +/** + * \brief Replacement of C library of _fstat + */ +extern int _fstat(int file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + + return 0; +} + +/** + * \brief Replacement of C library of _isatty + */ +extern int _isatty(int file) +{ + (void)file; + return 1; +} + +/** + * \brief Replacement of C library of _lseek + */ +extern int _lseek(int file, int ptr, int dir) +{ + (void)file, (void)ptr, (void)dir; + return 0; +} + +/** + * \brief Replacement of C library of _exit + */ +extern void _exit(int status) +{ + printf("Exiting with status %d.\n", status); + + for (;;) + ; +} + +/** + * \brief Replacement of C library of _kill + */ +extern void _kill(int pid, int sig) +{ + (void)pid, (void)sig; + return; +} + +/** + * \brief Replacement of C library of _getpid + */ +extern int _getpid(void) +{ + return -1; +} + +#ifdef __cplusplus +} +#endif diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hpl/core/hpl_core_m0plus_base.c b/prototype/firmware/I2C_scanner/I2C_scanner/hpl/core/hpl_core_m0plus_base.c new file mode 100644 index 00000000..1d32300a --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hpl/core/hpl_core_m0plus_base.c @@ -0,0 +1,200 @@ +/** + * \file + * + * \brief Core related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include +#include +#ifndef _UNIT_TEST_ +#include +#endif +#include +#include + +#ifndef CONF_CPU_FREQUENCY +#define CONF_CPU_FREQUENCY 1000000 +#endif + +#if CONF_CPU_FREQUENCY < 1000 +#define CPU_FREQ_POWER 3 +#elif CONF_CPU_FREQUENCY < 10000 +#define CPU_FREQ_POWER 4 +#elif CONF_CPU_FREQUENCY < 100000 +#define CPU_FREQ_POWER 5 +#elif CONF_CPU_FREQUENCY < 1000000 +#define CPU_FREQ_POWER 6 +#elif CONF_CPU_FREQUENCY < 10000000 +#define CPU_FREQ_POWER 7 +#elif CONF_CPU_FREQUENCY < 100000000 +#define CPU_FREQ_POWER 8 +#endif + +/** + * \brief The array of interrupt handlers + */ +struct _irq_descriptor *_irq_table[PERIPH_COUNT_IRQn]; + +/** + * \brief Reset MCU + */ +void _reset_mcu(void) +{ + NVIC_SystemReset(); +} + +/** + * \brief Put MCU to sleep + */ +void _go_to_sleep(void) +{ + __DSB(); + __WFI(); +} + +/** + * \brief Retrieve current IRQ number + */ +uint8_t _irq_get_current(void) +{ + return (uint8_t)__get_IPSR() - 16; +} + +/** + * \brief Disable the given IRQ + */ +void _irq_disable(uint8_t n) +{ + NVIC_DisableIRQ((IRQn_Type)n); +} + +/** + * \brief Set the given IRQ + */ +void _irq_set(uint8_t n) +{ + NVIC_SetPendingIRQ((IRQn_Type)n); +} + +/** + * \brief Clear the given IRQ + */ +void _irq_clear(uint8_t n) +{ + NVIC_ClearPendingIRQ((IRQn_Type)n); +} + +/** + * \brief Enable the given IRQ + */ +void _irq_enable(uint8_t n) +{ + NVIC_EnableIRQ((IRQn_Type)n); +} + +/** + * \brief Register IRQ handler + */ +void _irq_register(const uint8_t n, struct _irq_descriptor *const irq) +{ + ASSERT(n < PERIPH_COUNT_IRQn); + + _irq_table[n] = irq; +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Default_Handler(void) +{ + while (1) { + } +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of us + */ +static inline uint32_t _get_cycles_for_us_internal(const uint16_t us, const uint32_t freq, const uint8_t power) +{ + switch (power) { + case 8: + return (us * (freq / 100000) - 1) / 10 + 1; + case 7: + return (us * (freq / 10000) - 1) / 100 + 1; + case 6: + return (us * (freq / 1000) - 1) / 1000 + 1; + case 5: + return (us * (freq / 100) - 1) / 10000 + 1; + case 4: + return (us * (freq / 10) - 1) / 100000 + 1; + default: + return (us * freq - 1) / 1000000 + 1; + } +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of us + */ +uint32_t _get_cycles_for_us(const uint16_t us) +{ + return _get_cycles_for_us_internal(us, CONF_CPU_FREQUENCY, CPU_FREQ_POWER); +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of ms + */ +static inline uint32_t _get_cycles_for_ms_internal(const uint16_t ms, const uint32_t freq, const uint8_t power) +{ + switch (power) { + case 8: + return (ms * (freq / 100000)) * 100; + case 7: + return (ms * (freq / 10000)) * 10; + case 6: + return (ms * (freq / 1000)); + case 5: + return (ms * (freq / 100) - 1) / 10 + 1; + case 4: + return (ms * (freq / 10) - 1) / 100 + 1; + default: + return (ms * freq - 1) / 1000 + 1; + } +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of ms + */ +uint32_t _get_cycles_for_ms(const uint16_t ms) +{ + return _get_cycles_for_ms_internal(ms, CONF_CPU_FREQUENCY, CPU_FREQ_POWER); +} diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hpl/core/hpl_core_port.h b/prototype/firmware/I2C_scanner/I2C_scanner/hpl/core/hpl_core_port.h new file mode 100644 index 00000000..3f3e8f28 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hpl/core/hpl_core_port.h @@ -0,0 +1,61 @@ +/** + * \file + * + * \brief Core related functionality implementation. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_CORE_PORT_H_INCLUDED +#define _HPL_CORE_PORT_H_INCLUDED + +#include + +/* It's possible to include this file in ARM ASM files (e.g., in FreeRTOS IAR + * portable implement, portasm.s -> FreeRTOSConfig.h -> hpl_core_port.h), + * there will be assembling errors. + * So the following things are not included for assembling. + */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + +#ifndef _UNIT_TEST_ +#include +#endif + +/** + * \brief Check if it's in ISR handling + * \return \c true if it's in ISR + */ +static inline bool _is_in_isr(void) +{ + return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk); +} + +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _HPL_CORE_PORT_H_INCLUDED */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hpl/core/hpl_init.c b/prototype/firmware/I2C_scanner/I2C_scanner/hpl/core/hpl_init.c new file mode 100644 index 00000000..b77b840c --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hpl/core/hpl_init.c @@ -0,0 +1,74 @@ +/** + * \file + * + * \brief HPL initialization related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include + +#include +#include + +/* Referenced GCLKs (out of 0~7), should be initialized firstly + */ +#define _GCLK_INIT_1ST 0x00000000 +/* Not referenced GCLKs, initialized last */ +#define _GCLK_INIT_LAST 0x000000FF + +/** + * \brief Initialize the hardware abstraction layer + */ +void _init_chip(void) +{ + hri_nvmctrl_set_CTRLB_RWS_bf(NVMCTRL, CONF_NVM_WAIT_STATE); + + _set_performance_level(2); + + _osc32kctrl_init_sources(); + _oscctrl_init_sources(); + _mclk_init(); +#if _GCLK_INIT_1ST + _gclk_init_generators_by_fref(_GCLK_INIT_1ST); +#endif + _oscctrl_init_referenced_generators(); + _gclk_init_generators_by_fref(_GCLK_INIT_LAST); + +#if CONF_DMAC_ENABLE + hri_mclk_set_AHBMASK_DMAC_bit(MCLK); + _dma_init(); +#endif + +#if (CONF_PORT_EVCTRL_PORT_0 | CONF_PORT_EVCTRL_PORT_1 | CONF_PORT_EVCTRL_PORT_2 | CONF_PORT_EVCTRL_PORT_3) + _port_event_init(); +#endif +} diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hpl/dmac/hpl_dmac.c b/prototype/firmware/I2C_scanner/I2C_scanner/hpl/dmac/hpl_dmac.c new file mode 100644 index 00000000..460393c1 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hpl/dmac/hpl_dmac.c @@ -0,0 +1,249 @@ + +/** + * \file + * + * \brief Generic DMAC related functionality. + * + * Copyright (c) 2016-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include +#include +#include +#include + +#if CONF_DMAC_ENABLE + +#ifndef SECTION_DMAC_DESCRIPTOR +#define SECTION_DMAC_DESCRIPTOR +#warning Please double confirm if your DMA descriptor needs specific RAM +#endif + +/* Section containing first descriptors for all DMAC channels */ +COMPILER_ALIGNED(16) +DmacDescriptor _descriptor_section[DMAC_CH_NUM] SECTION_DMAC_DESCRIPTOR; + +/* Section containing current descriptors for all DMAC channels */ +COMPILER_ALIGNED(16) +DmacDescriptor _write_back_section[DMAC_CH_NUM] SECTION_DMAC_DESCRIPTOR; + +/* Array containing callbacks for DMAC channels */ +static struct _dma_resource _resources[DMAC_CH_NUM]; + +/* This macro DMAC configuration */ +#define DMAC_CHANNEL_CFG(i, n) \ + {(CONF_DMAC_RUNSTDBY_##n << DMAC_CHCTRLA_RUNSTDBY_Pos) | (CONF_DMAC_ENABLE_##n << DMAC_CHCTRLA_ENABLE_Pos), \ + DMAC_CHCTRLB_TRIGACT(CONF_DMAC_TRIGACT_##n) | DMAC_CHCTRLB_TRIGSRC(CONF_DMAC_TRIGSRC_##n) \ + | DMAC_CHCTRLB_LVL(CONF_DMAC_LVL_##n) | (CONF_DMAC_EVOE_##n << DMAC_CHCTRLB_EVOE_Pos) \ + | (CONF_DMAC_EVIE_##n << DMAC_CHCTRLB_EVIE_Pos) | DMAC_CHCTRLB_EVACT(CONF_DMAC_EVACT_##n), \ + DMAC_BTCTRL_STEPSIZE(CONF_DMAC_STEPSIZE_##n) | (CONF_DMAC_STEPSEL_##n << DMAC_BTCTRL_STEPSEL_Pos) \ + | (CONF_DMAC_DSTINC_##n << DMAC_BTCTRL_DSTINC_Pos) | (CONF_DMAC_SRCINC_##n << DMAC_BTCTRL_SRCINC_Pos) \ + | DMAC_BTCTRL_BEATSIZE(CONF_DMAC_BEATSIZE_##n) | DMAC_BTCTRL_BLOCKACT(CONF_DMAC_BLOCKACT_##n) \ + | DMAC_BTCTRL_EVOSEL(CONF_DMAC_EVOSEL_##n)}, + +/* DMAC channel configuration */ +struct dmac_channel_cfg { + uint8_t ctrla; + uint32_t ctrlb; + uint16_t btctrl; +}; + +/* DMAC channel configurations */ +const static struct dmac_channel_cfg _cfgs[] = {REPEAT_MACRO(DMAC_CHANNEL_CFG, i, DMAC_CH_NUM)}; + +/** + * \brief Initialize DMAC + */ +int32_t _dma_init(void) +{ + uint8_t i = 0; + + hri_dmac_clear_CTRL_DMAENABLE_bit(DMAC); + hri_dmac_clear_CTRL_CRCENABLE_bit(DMAC); + hri_dmac_set_CHCTRLA_SWRST_bit(DMAC); + + hri_dmac_write_CTRL_reg(DMAC, + (CONF_DMAC_LVLEN0 << DMAC_CTRL_LVLEN0_Pos) | (CONF_DMAC_LVLEN1 << DMAC_CTRL_LVLEN1_Pos) + | (CONF_DMAC_LVLEN2 << DMAC_CTRL_LVLEN2_Pos) + | (CONF_DMAC_LVLEN3 << DMAC_CTRL_LVLEN3_Pos)); + hri_dmac_write_DBGCTRL_DBGRUN_bit(DMAC, CONF_DMAC_DBGRUN); + + hri_dmac_write_QOSCTRL_reg(DMAC, + DMAC_QOSCTRL_WRBQOS(CONF_DMAC_WRBQOS) | DMAC_QOSCTRL_FQOS(CONF_DMAC_FQOS) + | DMAC_QOSCTRL_DQOS(CONF_DMAC_DQOS)); + + hri_dmac_write_PRICTRL0_reg( + DMAC, + DMAC_PRICTRL0_LVLPRI0(CONF_DMAC_LVLPRI0) | DMAC_PRICTRL0_LVLPRI1(CONF_DMAC_LVLPRI1) + | DMAC_PRICTRL0_LVLPRI2(CONF_DMAC_LVLPRI2) | DMAC_PRICTRL0_LVLPRI3(CONF_DMAC_LVLPRI3) + | (CONF_DMAC_RRLVLEN0 << DMAC_PRICTRL0_RRLVLEN0_Pos) | (CONF_DMAC_RRLVLEN1 << DMAC_PRICTRL0_RRLVLEN1_Pos) + | (CONF_DMAC_RRLVLEN2 << DMAC_PRICTRL0_RRLVLEN2_Pos) | (CONF_DMAC_RRLVLEN3 << DMAC_PRICTRL0_RRLVLEN3_Pos)); + hri_dmac_write_BASEADDR_reg(DMAC, (uint32_t)_descriptor_section); + hri_dmac_write_WRBADDR_reg(DMAC, (uint32_t)_write_back_section); + + for (; i < DMAC_CH_NUM; i++) { + hri_dmac_write_CHID_reg(DMAC, i); + + hri_dmac_write_CHCTRLA_RUNSTDBY_bit(DMAC, _cfgs[i].ctrla & DMAC_CHCTRLA_RUNSTDBY); + + hri_dmac_write_CHCTRLB_reg(DMAC, _cfgs[i].ctrlb); + hri_dmacdescriptor_write_BTCTRL_reg(&_descriptor_section[i], _cfgs[i].btctrl); + hri_dmacdescriptor_write_DESCADDR_reg(&_descriptor_section[i], 0x0); + } + + NVIC_DisableIRQ(DMAC_IRQn); + NVIC_ClearPendingIRQ(DMAC_IRQn); + NVIC_EnableIRQ(DMAC_IRQn); + + hri_dmac_set_CTRL_DMAENABLE_bit(DMAC); + + return ERR_NONE; +} + +/** + * \brief Enable/disable DMA interrupt + */ +void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state) +{ + hri_dmac_write_CHID_reg(DMAC, channel); + + if (DMA_TRANSFER_COMPLETE_CB == type) { + hri_dmac_write_CHINTEN_TCMPL_bit(DMAC, state); + } else if (DMA_TRANSFER_ERROR_CB == type) { + hri_dmac_write_CHINTEN_TERR_bit(DMAC, state); + } +} + +int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst) +{ + hri_dmacdescriptor_write_DSTADDR_reg(&_descriptor_section[channel], (uint32_t)dst); + + return ERR_NONE; +} + +int32_t _dma_set_source_address(const uint8_t channel, const void *const src) +{ + hri_dmacdescriptor_write_SRCADDR_reg(&_descriptor_section[channel], (uint32_t)src); + + return ERR_NONE; +} + +int32_t _dma_set_next_descriptor(const uint8_t current_channel, const uint8_t next_channel) +{ + hri_dmacdescriptor_write_DESCADDR_reg(&_descriptor_section[current_channel], + (uint32_t)&_descriptor_section[next_channel]); + + return ERR_NONE; +} + +int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable) +{ + hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(&_descriptor_section[channel], enable); + + return ERR_NONE; +} + +int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount) +{ + uint32_t address = hri_dmacdescriptor_read_DSTADDR_reg(&_descriptor_section[channel]); + uint8_t beat_size = hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(&_descriptor_section[channel]); + + if (hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(&_descriptor_section[channel])) { + hri_dmacdescriptor_write_DSTADDR_reg(&_descriptor_section[channel], address + amount * (1 << beat_size)); + } + + address = hri_dmacdescriptor_read_SRCADDR_reg(&_descriptor_section[channel]); + + if (hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(&_descriptor_section[channel])) { + hri_dmacdescriptor_write_SRCADDR_reg(&_descriptor_section[channel], address + amount * (1 << beat_size)); + } + + hri_dmacdescriptor_write_BTCNT_reg(&_descriptor_section[channel], amount); + + return ERR_NONE; +} + +int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger) +{ + hri_dmac_write_CHID_reg(DMAC, channel); + hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[channel]); + hri_dmac_set_CHCTRLA_ENABLE_bit(DMAC); + if (software_trigger) { + hri_dmac_set_SWTRIGCTRL_reg(DMAC, 1 << channel); + } + + return ERR_NONE; +} + +int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel) +{ + *resource = &_resources[channel]; + + return ERR_NONE; +} + +int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable) +{ + hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(&_descriptor_section[channel], enable); + + return ERR_NONE; +} + +/** + * \internal DMAC interrupt handler + */ +static inline void _dmac_handler(void) +{ + uint8_t channel = hri_dmac_read_INTPEND_ID_bf(DMAC); + uint8_t current_channel = hri_dmac_read_CHID_reg(DMAC); + uint8_t flag_status; + struct _dma_resource *tmp_resource = &_resources[channel]; + + hri_dmac_write_CHID_reg(DMAC, channel); + flag_status = hri_dmac_get_CHINTFLAG_reg(DMAC, DMAC_CHINTFLAG_MASK); + hri_dmac_write_CHID_reg(DMAC, current_channel); + + if (flag_status & DMAC_CHINTFLAG_TERR) { + hri_dmac_clear_CHINTFLAG_TERR_bit(DMAC); + tmp_resource->dma_cb.error(tmp_resource); + } else if (flag_status & DMAC_CHINTFLAG_TCMPL) { + hri_dmac_clear_CHINTFLAG_TCMPL_bit(DMAC); + tmp_resource->dma_cb.transfer_done(tmp_resource); + } +} + +/** + * \brief DMAC interrupt handler + */ +void DMAC_Handler(void) +{ + _dmac_handler(); +} + +#endif /* CONF_DMAC_ENABLE */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hpl/gclk/hpl_gclk.c b/prototype/firmware/I2C_scanner/I2C_scanner/hpl/gclk/hpl_gclk.c new file mode 100644 index 00000000..f93ec0c9 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hpl/gclk/hpl_gclk.c @@ -0,0 +1,246 @@ + +/** + * \file + * + * \brief Generic Clock Controller related functionality. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +/** + * \brief Initializes generators + */ +void _gclk_init_generators(void) +{ + +#if CONF_GCLK_GENERATOR_0_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 0, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_0_DIV) | (CONF_GCLK_GEN_0_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_0_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_0_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_0_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_0_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_0_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_0_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_1_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 1, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_1_DIV) | (CONF_GCLK_GEN_1_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_1_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_1_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_1_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_1_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_1_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_1_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_2_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 2, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_2_DIV) | (CONF_GCLK_GEN_2_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_2_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_2_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_2_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_2_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_2_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_2_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_3_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 3, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_3_DIV) | (CONF_GCLK_GEN_3_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_3_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_3_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_3_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_3_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_3_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_3_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_4_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 4, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_4_DIV) | (CONF_GCLK_GEN_4_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_4_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_4_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_4_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_4_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_4_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_5_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 5, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_5_DIV) | (CONF_GCLK_GEN_5_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_5_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_5_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_5_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_5_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_5_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_5_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_6_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 6, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_6_DIV) | (CONF_GCLK_GEN_6_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_6_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_6_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_6_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_6_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_6_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_6_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_7_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 7, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_7_DIV) | (CONF_GCLK_GEN_7_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_7_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_7_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_7_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_7_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_7_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_7_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_8_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 8, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_8_DIV) | (CONF_GCLK_GEN_8_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_8_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_8_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_8_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_8_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_8_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_8_SOURCE); +#endif +} + +void _gclk_init_generators_by_fref(uint32_t bm) +{ + +#if CONF_GCLK_GENERATOR_0_CONFIG == 1 + if (bm & (1ul << 0)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 0, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_0_DIV) | (CONF_GCLK_GEN_0_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_0_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_0_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_0_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_0_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_0_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_0_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_1_CONFIG == 1 + if (bm & (1ul << 1)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 1, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_1_DIV) | (CONF_GCLK_GEN_1_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_1_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_1_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_1_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_1_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_1_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_1_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_2_CONFIG == 1 + if (bm & (1ul << 2)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 2, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_2_DIV) | (CONF_GCLK_GEN_2_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_2_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_2_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_2_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_2_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_2_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_2_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_3_CONFIG == 1 + if (bm & (1ul << 3)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 3, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_3_DIV) | (CONF_GCLK_GEN_3_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_3_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_3_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_3_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_3_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_3_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_3_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_4_CONFIG == 1 + if (bm & (1ul << 4)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 4, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_4_DIV) | (CONF_GCLK_GEN_4_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_4_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_4_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_4_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_4_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_4_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_5_CONFIG == 1 + if (bm & (1ul << 5)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 5, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_5_DIV) | (CONF_GCLK_GEN_5_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_5_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_5_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_5_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_5_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_5_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_5_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_6_CONFIG == 1 + if (bm & (1ul << 6)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 6, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_6_DIV) | (CONF_GCLK_GEN_6_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_6_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_6_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_6_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_6_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_6_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_6_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_7_CONFIG == 1 + if (bm & (1ul << 7)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 7, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_7_DIV) | (CONF_GCLK_GEN_7_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_7_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_7_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_7_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_7_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_7_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_7_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_8_CONFIG == 1 + if (bm & (1ul << 8)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 8, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_8_DIV) | (CONF_GCLK_GEN_8_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_8_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_8_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_8_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_8_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_8_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_8_SOURCE); + } +#endif +} diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hpl/gclk/hpl_gclk_base.h b/prototype/firmware/I2C_scanner/I2C_scanner/hpl/gclk/hpl_gclk_base.h new file mode 100644 index 00000000..3e7d2825 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hpl/gclk/hpl_gclk_base.h @@ -0,0 +1,87 @@ +/** + * \file + * + * \brief Generic Clock Controller. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_GCLK_H_INCLUDED +#define _HPL_GCLK_H_INCLUDED + +#include +#ifdef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup gclk_group GCLK Hardware Proxy Layer + * + * \section gclk_hpl_rev Revision History + * - v0.0.0.1 Initial Commit + * + *@{ + */ + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Enable clock on the given channel with the given clock source + * + * This function maps the given clock source to the given clock channel + * and enables channel. + * + * \param[in] channel The channel to enable clock for + * \param[in] source The clock source for the given channel + */ +static inline void _gclk_enable_channel(const uint8_t channel, const uint8_t source) +{ + + hri_gclk_write_PCHCTRL_reg(GCLK, channel, source | GCLK_PCHCTRL_CHEN); +} + +/** + * \brief Initialize GCLK generators by function references + * \param[in] bm Bit mapping for referenced generators, + * a bit 1 in position triggers generator initialization. + */ +void _gclk_init_generators_by_fref(uint32_t bm); + +//@} +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_GCLK_H_INCLUDED */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hpl/mclk/hpl_mclk.c b/prototype/firmware/I2C_scanner/I2C_scanner/hpl/mclk/hpl_mclk.c new file mode 100644 index 00000000..cd27f094 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hpl/mclk/hpl_mclk.c @@ -0,0 +1,46 @@ +/** + * \file + * + * \brief SAM Main Clock. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** + * \brief Initialize master clock generator + */ +void _mclk_init(void) +{ + void *hw = (void *)MCLK; + hri_mclk_write_BUPDIV_reg(hw, MCLK_BUPDIV_BUPDIV(CONF_MCLK_BUPDIV)); + hri_mclk_write_LPDIV_reg(hw, MCLK_LPDIV_LPDIV(CONF_MCLK_LPDIV)); + hri_mclk_write_CPUDIV_reg(hw, MCLK_CPUDIV_CPUDIV(CONF_MCLK_CPUDIV)); +} diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hpl/osc32kctrl/hpl_osc32kctrl.c b/prototype/firmware/I2C_scanner/I2C_scanner/hpl/osc32kctrl/hpl_osc32kctrl.c new file mode 100644 index 00000000..0d543ad0 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hpl/osc32kctrl/hpl_osc32kctrl.c @@ -0,0 +1,102 @@ +/** + * \file + * + * \brief SAM 32k Oscillators Controller. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include + +/** + * \brief Initialize 32 kHz clock sources + */ +void _osc32kctrl_init_sources(void) +{ + void * hw = (void *)OSC32KCTRL; + uint16_t calib = 0; + +#if CONF_XOSC32K_CONFIG == 1 + hri_osc32kctrl_write_XOSC32K_reg( + hw, + OSC32KCTRL_XOSC32K_STARTUP(CONF_XOSC32K_STARTUP) | (CONF_XOSC32K_ONDEMAND << OSC32KCTRL_XOSC32K_ONDEMAND_Pos) + | (CONF_XOSC32K_RUNSTDBY << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos) + | (CONF_XOSC32K_EN1K << OSC32KCTRL_XOSC32K_EN1K_Pos) | (CONF_XOSC32K_EN32K << OSC32KCTRL_XOSC32K_EN32K_Pos) + | (CONF_XOSC32K_XTALEN << OSC32KCTRL_XOSC32K_XTALEN_Pos) + | (CONF_XOSC32K_ENABLE << OSC32KCTRL_XOSC32K_ENABLE_Pos)); + +#endif + +#if CONF_OSC32K_CONFIG == 1 + /* OSC32K calibration value at bit 12:6 of memory 0x00806020 */ + calib = (*((uint32_t *)0x00806020) & 0x0001FC0) >> 6; + hri_osc32kctrl_write_OSC32K_reg( + hw, +#if CONF_OSC32K_CALIB_ENABLE == 1 + OSC32KCTRL_OSC32K_CALIB(CONF_OSC32K_CALIB) | +#else + OSC32KCTRL_OSC32K_CALIB(calib) | +#endif + OSC32KCTRL_OSC32K_STARTUP(CONF_OSC32K_STARTUP) | (CONF_OSC32K_ONDEMAND << OSC32KCTRL_OSC32K_ONDEMAND_Pos) + | (CONF_OSC32K_RUNSTDBY << OSC32KCTRL_OSC32K_RUNSTDBY_Pos) + | (CONF_OSC32K_EN1K << OSC32KCTRL_OSC32K_EN1K_Pos) | (CONF_OSC32K_EN32K << OSC32KCTRL_OSC32K_EN32K_Pos) + | (CONF_OSC32K_ENABLE << OSC32KCTRL_OSC32K_ENABLE_Pos)); +#endif +#if CONF_OSCULP32K_CONFIG == 1 + calib = hri_osc32kctrl_read_OSCULP32K_CALIB_bf(hw); + hri_osc32kctrl_write_OSCULP32K_reg(hw, +#if CONF_OSC32K_CALIB_ENABLE == 1 + OSC32KCTRL_OSCULP32K_CALIB(CONF_OSC32K_CALIB) +#else + OSC32KCTRL_OSCULP32K_CALIB(calib) +#endif + ); +#endif + +#if CONF_XOSC32K_CONFIG +#if CONF_XOSC32K_ENABLE == 1 && CONF_XOSC32K_ONDEMAND == 0 + while (!hri_osc32kctrl_get_STATUS_XOSC32KRDY_bit(hw)) + ; +#endif +#if CONF_OSCULP32K_ULP32KSW == 1 + hri_osc32kctrl_set_OSCULP32K_reg(hw, OSC32KCTRL_OSCULP32K_ULP32KSW); + while (!hri_osc32kctrl_get_STATUS_ULP32KSW_bit(hw)) + ; +#endif +#endif + +#if CONF_OSC32K_CONFIG == 1 +#if CONF_OSC32K_ENABLE == 1 && CONF_OSC32K_ONDEMAND == 0 + while (!hri_osc32kctrl_get_STATUS_OSC32KRDY_bit(hw)) + ; +#endif +#endif + hri_osc32kctrl_write_RTCCTRL_reg(hw, OSC32KCTRL_RTCCTRL_RTCSEL(CONF_RTCCTRL)); + (void)calib; +} diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hpl/oscctrl/hpl_oscctrl.c b/prototype/firmware/I2C_scanner/I2C_scanner/hpl/oscctrl/hpl_oscctrl.c new file mode 100644 index 00000000..5b38cb77 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hpl/oscctrl/hpl_oscctrl.c @@ -0,0 +1,177 @@ + +/** + * \file + * + * \brief SAM Oscillators Controller. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include + +/** + * \brief Initialize clock sources + */ +void _oscctrl_init_sources(void) +{ + void *hw = (void *)OSCCTRL; + +#if CONF_XOSC_CONFIG == 1 + hri_oscctrl_write_XOSCCTRL_reg(hw, + OSCCTRL_XOSCCTRL_STARTUP(CONF_XOSC_STARTUP) | (0 << OSCCTRL_XOSCCTRL_AMPGC_Pos) + | OSCCTRL_XOSCCTRL_GAIN(CONF_XOSC_GAIN) | (0 << OSCCTRL_XOSCCTRL_ONDEMAND_Pos) + | (CONF_XOSC_RUNSTDBY << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos) + | (CONF_XOSC_XTALEN << OSCCTRL_XOSCCTRL_XTALEN_Pos) + | (CONF_XOSC_ENABLE << OSCCTRL_XOSCCTRL_ENABLE_Pos)); + +#endif + +#if CONF_OSC16M_CONFIG == 1 + hri_oscctrl_write_OSC16MCTRL_reg(hw, + (CONF_OSC16M_ONDEMAND << OSCCTRL_OSC16MCTRL_ONDEMAND_Pos) + | (CONF_OSC16M_RUNSTDBY << OSCCTRL_OSC16MCTRL_RUNSTDBY_Pos) + | (CONF_OSC16M_ENABLE << OSCCTRL_OSC16MCTRL_ENABLE_Pos) + | OSCCTRL_OSC16MCTRL_FSEL(CONF_OSC16M_FSEL)); +#endif + +#if CONF_XOSC_CONFIG == 1 +#if CONF_XOSC_ENABLE == 1 + while (!hri_oscctrl_get_STATUS_XOSCRDY_bit(hw)) + ; +#endif +#if CONF_XOSC_AMPGC == 1 + hri_oscctrl_set_XOSCCTRL_AMPGC_bit(hw); +#endif +#if CONF_XOSC_ONDEMAND == 1 + hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(hw); +#endif +#endif + +#if CONF_OSC16M_CONFIG == 1 +#if CONF_OSC16M_ENABLE == 1 + while (!hri_oscctrl_get_STATUS_OSC16MRDY_bit(hw)) + ; +#endif +#if CONF_OSC16M_ONDEMAND == 1 + hri_oscctrl_set_OSC16MCTRL_ONDEMAND_bit(hw); +#endif +#endif + (void)hw; +} + +void _oscctrl_init_referenced_generators(void) +{ + void * hw = (void *)OSCCTRL; + hri_oscctrl_dfllctrl_reg_t tmp = 0; + +#if CONF_DFLL_CONFIG == 1 +#if CONF_DFLL_OVERWRITE_CALIBRATION == 0 +#define NVM_DFLL_COARSE_POS 26 +#define NVM_DFLL_COARSE_SIZE 6 + uint32_t coarse; + coarse = *((uint32_t *)(NVMCTRL_OTP5)) >> NVM_DFLL_COARSE_POS; +#endif +#if CONF_DFLL_USBCRM != 1 && CONF_DFLL_MODE != 0 + hri_gclk_write_PCHCTRL_reg(GCLK, 0, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_DFLL_GCLK)); +#endif + hri_oscctrl_write_DFLLCTRL_reg(hw, OSCCTRL_DFLLCTRL_ENABLE); + while (!hri_oscctrl_get_STATUS_DFLLRDY_bit(hw)) + ; + hri_oscctrl_write_DFLLMUL_reg(hw, + OSCCTRL_DFLLMUL_CSTEP(CONF_DFLL_CSTEP) | OSCCTRL_DFLLMUL_FSTEP(CONF_DFLL_FSTEP) + | OSCCTRL_DFLLMUL_MUL(CONF_DFLL_MUL)); + while (!hri_oscctrl_get_STATUS_DFLLRDY_bit(hw)) + ; + +#if CONF_DFLL_OVERWRITE_CALIBRATION == 0 + /* FINE is set to fixed value, which defined by DFLL48M Characteristics */ + hri_oscctrl_write_DFLLVAL_reg(hw, OSCCTRL_DFLLVAL_COARSE(coarse) | OSCCTRL_DFLLVAL_FINE(512)); +#else + hri_oscctrl_write_DFLLVAL_reg(hw, OSCCTRL_DFLLVAL_COARSE(CONF_DFLL_COARSE) | OSCCTRL_DFLLVAL_FINE(CONF_DFLL_FINE)); +#endif + + tmp = (CONF_DFLL_WAITLOCK << OSCCTRL_DFLLCTRL_WAITLOCK_Pos) | (CONF_DFLL_BPLCKC << OSCCTRL_DFLLCTRL_BPLCKC_Pos) + | (CONF_DFLL_QLDIS << OSCCTRL_DFLLCTRL_QLDIS_Pos) | (CONF_DFLL_CCDIS << OSCCTRL_DFLLCTRL_CCDIS_Pos) + | (CONF_DFLL_RUNSTDBY << OSCCTRL_DFLLCTRL_RUNSTDBY_Pos) | (CONF_DFLL_USBCRM << OSCCTRL_DFLLCTRL_USBCRM_Pos) + | (CONF_DFLL_LLAW << OSCCTRL_DFLLCTRL_LLAW_Pos) | (CONF_DFLL_STABLE << OSCCTRL_DFLLCTRL_STABLE_Pos) + | (CONF_DFLL_MODE << OSCCTRL_DFLLCTRL_MODE_Pos) | (CONF_DFLL_ENABLE << OSCCTRL_DFLLCTRL_ENABLE_Pos); + hri_oscctrl_write_DFLLCTRL_reg(hw, tmp); + +#endif + +#if CONF_DPLL_CONFIG == 1 +#if CONF_DPLL_REFCLK == 2 + hri_gclk_write_PCHCTRL_reg(GCLK, 1, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_DPLL_GCLK)); +#endif + hri_oscctrl_write_DPLLRATIO_reg( + hw, OSCCTRL_DPLLRATIO_LDRFRAC(CONF_DPLL_LDRFRAC) | OSCCTRL_DPLLRATIO_LDR(CONF_DPLL_LDR)); + hri_oscctrl_write_DPLLCTRLB_reg( + hw, + OSCCTRL_DPLLCTRLB_DIV(CONF_DPLL_DIV) | (CONF_DPLL_LBYPASS << OSCCTRL_DPLLCTRLB_LBYPASS_Pos) + | OSCCTRL_DPLLCTRLB_LTIME(CONF_DPLL_LTIME) | OSCCTRL_DPLLCTRLB_REFCLK(CONF_DPLL_REFCLK) + | (CONF_DPLL_WUF << OSCCTRL_DPLLCTRLB_WUF_Pos) | (CONF_DPLL_LPEN << OSCCTRL_DPLLCTRLB_LPEN_Pos) + | OSCCTRL_DPLLCTRLB_FILTER(CONF_DPLL_FILTER)); + hri_oscctrl_write_DPLLPRESC_reg(hw, OSCCTRL_DPLLPRESC_PRESC(CONF_DPLL_PRESC)); + hri_oscctrl_write_DPLLCTRLA_reg(hw, + (0 << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos) + | (CONF_DPLL_RUNSTDBY << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos) + | (CONF_DPLL_ENABLE << OSCCTRL_DPLLCTRLA_ENABLE_Pos)); +#endif + +#if CONF_DFLL_CONFIG == 1 + if (hri_oscctrl_get_DFLLCTRL_MODE_bit(hw)) { + hri_oscctrl_status_reg_t status_mask = OSCCTRL_STATUS_DFLLRDY | OSCCTRL_STATUS_DFLLLCKC; + + while (hri_oscctrl_get_STATUS_reg(hw, status_mask) != status_mask) + ; + } else { + while (!hri_oscctrl_get_STATUS_DFLLRDY_bit(hw)) + ; + } +#if CONF_DFLL_ONDEMAND == 1 + hri_oscctrl_set_DFLLCTRL_ONDEMAND_bit(hw); +#endif +#endif + +#if CONF_DPLL_CONFIG == 1 +#if CONF_DPLL_ENABLE == 1 + while (!(hri_oscctrl_get_DPLLSTATUS_LOCK_bit(hw) || hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(hw))) + ; +#endif +#if CONF_DPLL_ONDEMAND == 1 + hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(hw); +#endif +#endif + +#if CONF_DFLL_CONFIG == 1 + while (hri_gclk_read_SYNCBUSY_reg(GCLK)) + ; +#endif + (void)hw, (void)tmp; +} diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hpl/pm/hpl_pm.c b/prototype/firmware/I2C_scanner/I2C_scanner/hpl/pm/hpl_pm.c new file mode 100644 index 00000000..d6439f1d --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hpl/pm/hpl_pm.c @@ -0,0 +1,77 @@ + +/** + * \file + * + * \brief SAM Power manager + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +/** + * \brief Retrieve the reset reason + */ +enum reset_reason _get_reset_reason(void) +{ + return (enum reset_reason)hri_rstc_read_RCAUSE_reg(RSTC); +} + +/** + * \brief Set the sleep mode for the device + */ +int32_t _set_sleep_mode(const uint8_t mode) +{ + switch (mode) { + case 2: /* IDLE */ + case 4: /* STANDBY */ + case 5: /* BACKUP */ + case 6: /* OFF */ + hri_pm_write_SLEEPCFG_SLEEPMODE_bf(PM, mode); + break; + default: + return ERR_INVALID_ARG; + } + + return ERR_NONE; +} + +/** + * \brief Set performance level + */ +void _set_performance_level(const uint8_t level) +{ + if (hri_pm_get_PLCFG_PLSEL_bf(PM, PM_PLCFG_PLSEL_Msk) != level) { + hri_pm_clear_INTFLAG_reg(PM, 0xFF); + hri_pm_write_PLCFG_PLSEL_bf(PM, level); + while (!hri_pm_read_INTFLAG_reg(PM)) + ; + } +} diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hpl/pm/hpl_pm_base.h b/prototype/firmware/I2C_scanner/I2C_scanner/hpl/pm/hpl_pm_base.h new file mode 100644 index 00000000..5a50a914 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hpl/pm/hpl_pm_base.h @@ -0,0 +1,45 @@ +/** + * \file + * + * \brief SAM Power manager + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifndef _HPL_PM_BASE_H_INCLUDED +#define _HPL_PM_BASE_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#ifdef __cplusplus +} +#endif +#endif /* _HPL_PM_BASE_H_INCLUDED */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hpl/port/hpl_gpio_base.h b/prototype/firmware/I2C_scanner/I2C_scanner/hpl/port/hpl_gpio_base.h new file mode 100644 index 00000000..3cc1981f --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hpl/port/hpl_gpio_base.h @@ -0,0 +1,170 @@ + +/** + * \file + * + * \brief SAM PORT. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include +#include + +/** + * \brief Set direction on port with mask + */ +static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask, + const enum gpio_direction direction) +{ + switch (direction) { + case GPIO_DIRECTION_OFF: + hri_port_clear_DIR_reg(PORT_IOBUS, port, mask); + hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff)); + hri_port_write_WRCONFIG_reg( + PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16)); + break; + + case GPIO_DIRECTION_IN: + hri_port_clear_DIR_reg(PORT_IOBUS, port, mask); + hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN | (mask & 0xffff)); + hri_port_write_WRCONFIG_reg(PORT, + port, + PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN + | ((mask & 0xffff0000) >> 16)); + break; + + case GPIO_DIRECTION_OUT: + hri_port_set_DIR_reg(PORT_IOBUS, port, mask); + hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff)); + hri_port_write_WRCONFIG_reg( + PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16)); + break; + + default: + ASSERT(false); + } +} + +/** + * \brief Set output level on port with mask + */ +static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level) +{ + if (level) { + hri_port_set_OUT_reg(PORT_IOBUS, port, mask); + } else { + hri_port_clear_OUT_reg(PORT_IOBUS, port, mask); + } +} + +/** + * \brief Change output level to the opposite with mask + */ +static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask) +{ + hri_port_toggle_OUT_reg(PORT_IOBUS, port, mask); +} + +/** + * \brief Get input levels on all port pins + */ +static inline uint32_t _gpio_get_level(const enum gpio_port port) +{ + uint32_t tmp; + + CRITICAL_SECTION_ENTER(); + + uint32_t dir_tmp = hri_port_read_DIR_reg(PORT_IOBUS, port); + + tmp = hri_port_read_IN_reg(PORT, port) & ~dir_tmp; + tmp |= hri_port_read_OUT_reg(PORT_IOBUS, port) & dir_tmp; + + CRITICAL_SECTION_LEAVE(); + + return tmp; +} + +/** + * \brief Set pin pull mode + */ +static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin, + const enum gpio_pull_mode pull_mode) +{ + switch (pull_mode) { + case GPIO_PULL_OFF: + hri_port_clear_PINCFG_PULLEN_bit(PORT, port, pin); + break; + + case GPIO_PULL_UP: + hri_port_clear_DIR_reg(PORT_IOBUS, port, 1U << pin); + hri_port_set_PINCFG_PULLEN_bit(PORT, port, pin); + hri_port_set_OUT_reg(PORT_IOBUS, port, 1U << pin); + break; + + case GPIO_PULL_DOWN: + hri_port_clear_DIR_reg(PORT_IOBUS, port, 1U << pin); + hri_port_set_PINCFG_PULLEN_bit(PORT, port, pin); + hri_port_clear_OUT_reg(PORT_IOBUS, port, 1U << pin); + break; + + default: + ASSERT(false); + break; + } +} + +/** + * \brief Set gpio pin function + */ +static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function) +{ + uint8_t port = GPIO_PORT(gpio); + uint8_t pin = GPIO_PIN(gpio); + + if (function == GPIO_PIN_FUNCTION_OFF) { + hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, false); + + } else { + hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, true); + + if (pin & 1) { + // Odd numbered pin + hri_port_write_PMUX_PMUXO_bf(PORT, port, pin >> 1, function & 0xffff); + } else { + // Even numbered pin + hri_port_write_PMUX_PMUXE_bf(PORT, port, pin >> 1, function & 0xffff); + } + } +} + +static inline void _port_event_init() +{ + hri_port_set_EVCTRL_reg(PORT, 0, CONF_PORTA_EVCTRL); + hri_port_set_EVCTRL_reg(PORT, 1, CONF_PORTB_EVCTRL); +} diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hpl/sercom/hpl_sercom.c b/prototype/firmware/I2C_scanner/I2C_scanner/hpl/sercom/hpl_sercom.c new file mode 100644 index 00000000..7a448e61 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hpl/sercom/hpl_sercom.c @@ -0,0 +1,2920 @@ + +/** + * \file + * + * \brief SAM Serial Communication Interface + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef CONF_SERCOM_0_USART_ENABLE +#define CONF_SERCOM_0_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_USART_ENABLE +#define CONF_SERCOM_1_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_USART_ENABLE +#define CONF_SERCOM_2_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_USART_ENABLE +#define CONF_SERCOM_3_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_USART_ENABLE +#define CONF_SERCOM_4_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_USART_ENABLE +#define CONF_SERCOM_5_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_USART_ENABLE +#define CONF_SERCOM_6_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_USART_ENABLE +#define CONF_SERCOM_7_USART_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as USART. */ +#define SERCOM_USART_AMOUNT \ + (CONF_SERCOM_0_USART_ENABLE + CONF_SERCOM_1_USART_ENABLE + CONF_SERCOM_2_USART_ENABLE + CONF_SERCOM_3_USART_ENABLE \ + + CONF_SERCOM_4_USART_ENABLE + CONF_SERCOM_5_USART_ENABLE + CONF_SERCOM_6_USART_ENABLE \ + + CONF_SERCOM_7_USART_ENABLE) + +/** + * \brief Macro is used to fill usart configuration structure based on + * its number + * + * \param[in] n The number of structures + */ +#define SERCOM_CONFIGURATION(n) \ + { \ + n, \ + SERCOM_USART_CTRLA_MODE(CONF_SERCOM_##n##_USART_MODE) \ + | (CONF_SERCOM_##n##_USART_RUNSTDBY << SERCOM_USART_CTRLA_RUNSTDBY_Pos) \ + | (CONF_SERCOM_##n##_USART_IBON << SERCOM_USART_CTRLA_IBON_Pos) \ + | SERCOM_USART_CTRLA_SAMPR(CONF_SERCOM_##n##_USART_SAMPR) \ + | SERCOM_USART_CTRLA_TXPO(CONF_SERCOM_##n##_USART_TXPO) \ + | SERCOM_USART_CTRLA_RXPO(CONF_SERCOM_##n##_USART_RXPO) \ + | SERCOM_USART_CTRLA_SAMPA(CONF_SERCOM_##n##_USART_SAMPA) \ + | SERCOM_USART_CTRLA_FORM(CONF_SERCOM_##n##_USART_FORM) \ + | (CONF_SERCOM_##n##_USART_CMODE << SERCOM_USART_CTRLA_CMODE_Pos) \ + | (CONF_SERCOM_##n##_USART_CPOL << SERCOM_USART_CTRLA_CPOL_Pos) \ + | (CONF_SERCOM_##n##_USART_DORD << SERCOM_USART_CTRLA_DORD_Pos), \ + SERCOM_USART_CTRLB_CHSIZE(CONF_SERCOM_##n##_USART_CHSIZE) \ + | (CONF_SERCOM_##n##_USART_SBMODE << SERCOM_USART_CTRLB_SBMODE_Pos) \ + | (CONF_SERCOM_##n##_USART_CLODEN << SERCOM_USART_CTRLB_COLDEN_Pos) \ + | (CONF_SERCOM_##n##_USART_SFDE << SERCOM_USART_CTRLB_SFDE_Pos) \ + | (CONF_SERCOM_##n##_USART_ENC << SERCOM_USART_CTRLB_ENC_Pos) \ + | (CONF_SERCOM_##n##_USART_PMODE << SERCOM_USART_CTRLB_PMODE_Pos) \ + | (CONF_SERCOM_##n##_USART_TXEN << SERCOM_USART_CTRLB_TXEN_Pos) \ + | (CONF_SERCOM_##n##_USART_RXEN << SERCOM_USART_CTRLB_RXEN_Pos), \ + (uint16_t)(CONF_SERCOM_##n##_USART_BAUD_RATE), CONF_SERCOM_##n##_USART_FRACTIONAL, \ + CONF_SERCOM_##n##_USART_RECEIVE_PULSE_LENGTH, CONF_SERCOM_##n##_USART_DEBUG_STOP_MODE, \ + } + +/** + * \brief SERCOM USART configuration type + */ +struct usart_configuration { + uint8_t number; + hri_sercomusart_ctrla_reg_t ctrl_a; + hri_sercomusart_ctrlb_reg_t ctrl_b; + hri_sercomusart_baud_reg_t baud; + uint8_t fractional; + hri_sercomusart_rxpl_reg_t rxpl; + hri_sercomusart_dbgctrl_reg_t debug_ctrl; +}; + +#if SERCOM_USART_AMOUNT < 1 +/** Dummy array to pass compiling. */ +static struct usart_configuration _usarts[1] = {{0}}; +#else +/** + * \brief Array of SERCOM USART configurations + */ +static struct usart_configuration _usarts[] = { +#if CONF_SERCOM_0_USART_ENABLE == 1 + SERCOM_CONFIGURATION(0), +#endif +#if CONF_SERCOM_1_USART_ENABLE == 1 + SERCOM_CONFIGURATION(1), +#endif +#if CONF_SERCOM_2_USART_ENABLE == 1 + SERCOM_CONFIGURATION(2), +#endif +#if CONF_SERCOM_3_USART_ENABLE == 1 + SERCOM_CONFIGURATION(3), +#endif +#if CONF_SERCOM_4_USART_ENABLE == 1 + SERCOM_CONFIGURATION(4), +#endif +#if CONF_SERCOM_5_USART_ENABLE == 1 + SERCOM_CONFIGURATION(5), +#endif +#if CONF_SERCOM_6_USART_ENABLE == 1 + SERCOM_CONFIGURATION(6), +#endif +#if CONF_SERCOM_7_USART_ENABLE == 1 + SERCOM_CONFIGURATION(7), +#endif +}; +#endif + +static uint8_t _get_sercom_index(const void *const hw); +static uint8_t _sercom_get_irq_num(const void *const hw); +static void _sercom_init_irq_param(const void *const hw, void *dev); +static uint8_t _sercom_get_hardware_index(const void *const hw); + +static int32_t _usart_init(void *const hw); +static inline void _usart_deinit(void *const hw); +static uint16_t _usart_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction); +static void _usart_set_baud_rate(void *const hw, const uint32_t baud_rate); +static void _usart_set_data_order(void *const hw, const enum usart_data_order order); +static void _usart_set_mode(void *const hw, const enum usart_mode mode); +static void _usart_set_parity(void *const hw, const enum usart_parity parity); +static void _usart_set_stop_bits(void *const hw, const enum usart_stop_bits stop_bits); +static void _usart_set_character_size(void *const hw, const enum usart_character_size size); + +/** + * \brief Initialize synchronous SERCOM USART + */ +int32_t _usart_sync_init(struct _usart_sync_device *const device, void *const hw) +{ + ASSERT(device); + + device->hw = hw; + + return _usart_init(hw); +} + +/** + * \brief Initialize asynchronous SERCOM USART + */ +int32_t _usart_async_init(struct _usart_async_device *const device, void *const hw) +{ + int32_t init_status; + + ASSERT(device); + + init_status = _usart_init(hw); + if (init_status) { + return init_status; + } + device->hw = hw; + _sercom_init_irq_param(hw, (void *)device); + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + + return ERR_NONE; +} + +/** + * \brief De-initialize SERCOM USART + */ +void _usart_sync_deinit(struct _usart_sync_device *const device) +{ + _usart_deinit(device->hw); +} + +/** + * \brief De-initialize SERCOM USART + */ +void _usart_async_deinit(struct _usart_async_device *const device) +{ + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(device->hw)); + _usart_deinit(device->hw); +} + +/** + * \brief Calculate baud rate register value + */ +uint16_t _usart_sync_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction) +{ + return _usart_calculate_baud_rate(baud, clock_rate, samples, mode, fraction); +} + +/** + * \brief Calculate baud rate register value + */ +uint16_t _usart_async_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction) +{ + return _usart_calculate_baud_rate(baud, clock_rate, samples, mode, fraction); +} + +/** + * \brief Enable SERCOM module + */ +void _usart_sync_enable(struct _usart_sync_device *const device) +{ + hri_sercomusart_set_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Enable SERCOM module + */ +void _usart_async_enable(struct _usart_async_device *const device) +{ + hri_sercomusart_set_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Disable SERCOM module + */ +void _usart_sync_disable(struct _usart_sync_device *const device) +{ + hri_sercomusart_clear_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Disable SERCOM module + */ +void _usart_async_disable(struct _usart_async_device *const device) +{ + hri_sercomusart_clear_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Set baud rate + */ +void _usart_sync_set_baud_rate(struct _usart_sync_device *const device, const uint32_t baud_rate) +{ + _usart_set_baud_rate(device->hw, baud_rate); +} + +/** + * \brief Set baud rate + */ +void _usart_async_set_baud_rate(struct _usart_async_device *const device, const uint32_t baud_rate) +{ + _usart_set_baud_rate(device->hw, baud_rate); +} + +/** + * \brief Set data order + */ +void _usart_sync_set_data_order(struct _usart_sync_device *const device, const enum usart_data_order order) +{ + _usart_set_data_order(device->hw, order); +} + +/** + * \brief Set data order + */ +void _usart_async_set_data_order(struct _usart_async_device *const device, const enum usart_data_order order) +{ + _usart_set_data_order(device->hw, order); +} + +/** + * \brief Set mode + */ +void _usart_sync_set_mode(struct _usart_sync_device *const device, const enum usart_mode mode) +{ + _usart_set_mode(device->hw, mode); +} + +/** + * \brief Set mode + */ +void _usart_async_set_mode(struct _usart_async_device *const device, const enum usart_mode mode) +{ + _usart_set_mode(device->hw, mode); +} + +/** + * \brief Set parity + */ +void _usart_sync_set_parity(struct _usart_sync_device *const device, const enum usart_parity parity) +{ + _usart_set_parity(device->hw, parity); +} + +/** + * \brief Set parity + */ +void _usart_async_set_parity(struct _usart_async_device *const device, const enum usart_parity parity) +{ + _usart_set_parity(device->hw, parity); +} + +/** + * \brief Set stop bits mode + */ +void _usart_sync_set_stop_bits(struct _usart_sync_device *const device, const enum usart_stop_bits stop_bits) +{ + _usart_set_stop_bits(device->hw, stop_bits); +} + +/** + * \brief Set stop bits mode + */ +void _usart_async_set_stop_bits(struct _usart_async_device *const device, const enum usart_stop_bits stop_bits) +{ + _usart_set_stop_bits(device->hw, stop_bits); +} + +/** + * \brief Set character size + */ +void _usart_sync_set_character_size(struct _usart_sync_device *const device, const enum usart_character_size size) +{ + _usart_set_character_size(device->hw, size); +} + +/** + * \brief Set character size + */ +void _usart_async_set_character_size(struct _usart_async_device *const device, const enum usart_character_size size) +{ + _usart_set_character_size(device->hw, size); +} + +/** + * \brief Retrieve SERCOM usart status + */ +uint32_t _usart_sync_get_status(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_read_STATUS_reg(device->hw); +} + +/** + * \brief Retrieve SERCOM usart status + */ +uint32_t _usart_async_get_status(const struct _usart_async_device *const device) +{ + return hri_sercomusart_read_STATUS_reg(device->hw); +} + +/** + * \brief Write a byte to the given SERCOM USART instance + */ +void _usart_sync_write_byte(struct _usart_sync_device *const device, uint8_t data) +{ + hri_sercomusart_write_DATA_reg(device->hw, data); +} + +/** + * \brief Write a byte to the given SERCOM USART instance + */ +void _usart_async_write_byte(struct _usart_async_device *const device, uint8_t data) +{ + hri_sercomusart_write_DATA_reg(device->hw, data); +} + +/** + * \brief Read a byte from the given SERCOM USART instance + */ +uint8_t _usart_sync_read_byte(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_read_DATA_reg(device->hw); +} + +/** + * \brief Check if USART is ready to send next byte + */ +bool _usart_sync_is_ready_to_send(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_get_interrupt_DRE_bit(device->hw); +} + +/** + * \brief Check if USART transmission complete + */ +bool _usart_sync_is_transmit_done(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_get_interrupt_TXC_bit(device->hw); +} + +/** + * \brief Check if USART is ready to send next byte + */ +bool _usart_async_is_byte_sent(const struct _usart_async_device *const device) +{ + return hri_sercomusart_get_interrupt_DRE_bit(device->hw); +} + +/** + * \brief Check if there is data received by USART + */ +bool _usart_sync_is_byte_received(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_get_interrupt_RXC_bit(device->hw); +} + +/** + * \brief Set the state of flow control pins + */ +void _usart_sync_set_flow_control_state(struct _usart_sync_device *const device, + const union usart_flow_control_state state) +{ + (void)device; + (void)state; +} + +/** + * \brief Set the state of flow control pins + */ +void _usart_async_set_flow_control_state(struct _usart_async_device *const device, + const union usart_flow_control_state state) +{ + (void)device; + (void)state; +} + +/** + * \brief Retrieve the state of flow control pins + */ +union usart_flow_control_state _usart_sync_get_flow_control_state(const struct _usart_sync_device *const device) +{ + (void)device; + union usart_flow_control_state state; + + state.value = 0; + state.bit.unavailable = 1; + return state; +} + +/** + * \brief Retrieve the state of flow control pins + */ +union usart_flow_control_state _usart_async_get_flow_control_state(const struct _usart_async_device *const device) +{ + (void)device; + union usart_flow_control_state state; + + state.value = 0; + state.bit.unavailable = 1; + return state; +} + +/** + * \brief Enable data register empty interrupt + */ +void _usart_async_enable_byte_sent_irq(struct _usart_async_device *const device) +{ + hri_sercomusart_set_INTEN_DRE_bit(device->hw); +} + +/** + * \brief Enable transmission complete interrupt + */ +void _usart_async_enable_tx_done_irq(struct _usart_async_device *const device) +{ + hri_sercomusart_set_INTEN_TXC_bit(device->hw); +} + +/** + * \brief Retrieve ordinal number of the given sercom hardware instance + */ +static uint8_t _sercom_get_hardware_index(const void *const hw) +{ +#ifdef _UNIT_TEST_ + return ((uint32_t)hw - (uint32_t)SERCOM0) / sizeof(Sercom); +#endif + if ((uint32_t)SERCOM5 == (uint32_t)hw) { + return 5; + } + + return ((uint32_t)hw - (uint32_t)SERCOM0) >> 10; +} + +/** + * \brief Retrieve ordinal number of the given SERCOM USART hardware instance + */ +uint8_t _usart_sync_get_hardware_index(const struct _usart_sync_device *const device) +{ + return _sercom_get_hardware_index(device->hw); +} + +/** + * \brief Retrieve ordinal number of the given SERCOM USART hardware instance + */ +uint8_t _usart_async_get_hardware_index(const struct _usart_async_device *const device) +{ + return _sercom_get_hardware_index(device->hw); +} + +/** + * \brief Enable/disable USART interrupt + */ +void _usart_async_set_irq_state(struct _usart_async_device *const device, const enum _usart_async_callback_type type, + const bool state) +{ + ASSERT(device); + + if (USART_ASYNC_BYTE_SENT == type || USART_ASYNC_TX_DONE == type) { + hri_sercomusart_write_INTEN_DRE_bit(device->hw, state); + hri_sercomusart_write_INTEN_TXC_bit(device->hw, state); + } else if (USART_ASYNC_RX_DONE == type) { + hri_sercomusart_write_INTEN_RXC_bit(device->hw, state); + } else if (USART_ASYNC_ERROR == type) { + hri_sercomusart_write_INTEN_ERROR_bit(device->hw, state); + } +} + +/** + * \internal Retrieve ordinal number of the given sercom hardware instance + * + * \param[in] hw The pointer to hardware instance + + * \return The ordinal number of the given sercom hardware instance + */ +static uint8_t _get_sercom_index(const void *const hw) +{ + uint8_t sercom_offset = _sercom_get_hardware_index(hw); + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(_usarts); i++) { + if (_usarts[i].number == sercom_offset) { + return i; + } + } + + ASSERT(false); + return 0; +} + +/** + * \brief Init irq param with the given sercom hardware instance + */ +static void _sercom_init_irq_param(const void *const hw, void *dev) +{ +} + +/** + * \internal Initialize SERCOM USART + * + * \param[in] hw The pointer to hardware instance + * + * \return The status of initialization + */ +static int32_t _usart_init(void *const hw) +{ + uint8_t i = _get_sercom_index(hw); + + if (!hri_sercomusart_is_syncing(hw, SERCOM_USART_SYNCBUSY_SWRST)) { + uint32_t mode = _usarts[i].ctrl_a & SERCOM_USART_CTRLA_MODE_Msk; + if (hri_sercomusart_get_CTRLA_reg(hw, SERCOM_USART_CTRLA_ENABLE)) { + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + } + hri_sercomusart_write_CTRLA_reg(hw, SERCOM_USART_CTRLA_SWRST | mode); + } + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); + + hri_sercomusart_write_CTRLA_reg(hw, _usarts[i].ctrl_a); + hri_sercomusart_write_CTRLB_reg(hw, _usarts[i].ctrl_b); + if ((_usarts[i].ctrl_a & SERCOM_USART_CTRLA_SAMPR(0x1)) || (_usarts[i].ctrl_a & SERCOM_USART_CTRLA_SAMPR(0x3))) { + ((Sercom *)hw)->USART.BAUD.FRAC.BAUD = _usarts[i].baud; + ((Sercom *)hw)->USART.BAUD.FRAC.FP = _usarts[i].fractional; + } else { + hri_sercomusart_write_BAUD_reg(hw, _usarts[i].baud); + } + + hri_sercomusart_write_RXPL_reg(hw, _usarts[i].rxpl); + hri_sercomusart_write_DBGCTRL_reg(hw, _usarts[i].debug_ctrl); + + return ERR_NONE; +} + +/** + * \internal De-initialize SERCOM USART + * + * \param[in] hw The pointer to hardware instance + */ +static inline void _usart_deinit(void *const hw) +{ + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + hri_sercomusart_set_CTRLA_SWRST_bit(hw); +} + +/** + * \internal Calculate baud rate register value + * + * \param[in] baud Required baud rate + * \param[in] clock_rate SERCOM clock frequency + * \param[in] samples The number of samples + * \param[in] mode USART mode + * \param[in] fraction A fraction value + * + * \return Calculated baud rate register value + */ +static uint16_t _usart_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction) +{ + if (USART_BAUDRATE_ASYNCH_ARITHMETIC == mode) { + return 65536 - ((uint64_t)65536 * samples * baud) / clock_rate; + } + + if (USART_BAUDRATE_ASYNCH_FRACTIONAL == mode) { + return clock_rate / baud / samples + SERCOM_USART_BAUD_FRACFP_FP(fraction); + } + + if (USART_BAUDRATE_SYNCH == mode) { + return clock_rate / baud / 2 - 1; + } + + return 0; +} + +/** + * \internal Set baud rate + * + * \param[in] device The pointer to USART device instance + * \param[in] baud_rate A baud rate to set + */ +static void _usart_set_baud_rate(void *const hw, const uint32_t baud_rate) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_BAUD_reg(hw, baud_rate); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set data order + * + * \param[in] device The pointer to USART device instance + * \param[in] order A data order to set + */ +static void _usart_set_data_order(void *const hw, const enum usart_data_order order) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLA_DORD_bit(hw, order); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set mode + * + * \param[in] device The pointer to USART device instance + * \param[in] mode A mode to set + */ +static void _usart_set_mode(void *const hw, const enum usart_mode mode) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLA_CMODE_bit(hw, mode); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set parity + * + * \param[in] device The pointer to USART device instance + * \param[in] parity A parity to set + */ +static void _usart_set_parity(void *const hw, const enum usart_parity parity) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + + if (USART_PARITY_NONE != parity) { + hri_sercomusart_set_CTRLA_FORM_bf(hw, 1); + } else { + hri_sercomusart_clear_CTRLA_FORM_bf(hw, 1); + } + + hri_sercomusart_write_CTRLB_PMODE_bit(hw, parity); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set stop bits mode + * + * \param[in] device The pointer to USART device instance + * \param[in] stop_bits A stop bits mode to set + */ +static void _usart_set_stop_bits(void *const hw, const enum usart_stop_bits stop_bits) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLB_SBMODE_bit(hw, stop_bits); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set character size + * + * \param[in] device The pointer to USART device instance + * \param[in] size A character size to set + */ +static void _usart_set_character_size(void *const hw, const enum usart_character_size size) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLB_CHSIZE_bf(hw, size); + CRITICAL_SECTION_LEAVE() + + if (enabled) { + hri_sercomusart_set_CTRLA_ENABLE_bit(hw); + } +} + + /* Sercom I2C implementation */ + +#ifndef CONF_SERCOM_0_I2CM_ENABLE +#define CONF_SERCOM_0_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_I2CM_ENABLE +#define CONF_SERCOM_1_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_I2CM_ENABLE +#define CONF_SERCOM_2_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_I2CM_ENABLE +#define CONF_SERCOM_3_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_I2CM_ENABLE +#define CONF_SERCOM_4_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_I2CM_ENABLE +#define CONF_SERCOM_5_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_I2CM_ENABLE +#define CONF_SERCOM_6_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_I2CM_ENABLE +#define CONF_SERCOM_7_I2CM_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as I2C Master. */ +#define SERCOM_I2CM_AMOUNT \ + (CONF_SERCOM_0_I2CM_ENABLE + CONF_SERCOM_1_I2CM_ENABLE + CONF_SERCOM_2_I2CM_ENABLE + CONF_SERCOM_3_I2CM_ENABLE \ + + CONF_SERCOM_4_I2CM_ENABLE + CONF_SERCOM_5_I2CM_ENABLE + CONF_SERCOM_6_I2CM_ENABLE + CONF_SERCOM_7_I2CM_ENABLE) + +/** + * \brief Macro is used to fill i2cm configuration structure based on + * its number + * + * \param[in] n The number of structures + */ +#define I2CM_CONFIGURATION(n) \ + { \ + (n), \ + (SERCOM_I2CM_CTRLA_MODE_I2C_MASTER) | (CONF_SERCOM_##n##_I2CM_RUNSTDBY << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos) \ + | (CONF_SERCOM_##n##_I2CM_SPEED << SERCOM_I2CM_CTRLA_SPEED_Pos) \ + | (CONF_SERCOM_##n##_I2CM_MEXTTOEN << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos) \ + | (CONF_SERCOM_##n##_I2CM_SEXTTOEN << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos) \ + | (CONF_SERCOM_##n##_I2CM_INACTOUT << SERCOM_I2CM_CTRLA_INACTOUT_Pos) \ + | (CONF_SERCOM_##n##_I2CM_LOWTOUT << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos) \ + | (CONF_SERCOM_##n##_I2CM_SDAHOLD << SERCOM_I2CM_CTRLA_SDAHOLD_Pos), \ + SERCOM_I2CM_CTRLB_SMEN, (uint32_t)(CONF_SERCOM_##n##_I2CM_BAUD_RATE), \ + CONF_SERCOM_##n##_I2CM_DEBUG_STOP_MODE, CONF_SERCOM_##n##_I2CM_TRISE, CONF_GCLK_SERCOM##n##_CORE_FREQUENCY \ + } + +#define ERROR_FLAG (1 << 7) +#define SB_FLAG (1 << 1) +#define MB_FLAG (1 << 0) + +#define CMD_STOP 0x3 +#define I2C_IDLE 0x1 +#define I2C_SM 0x0 +#define I2C_FM 0x1 +#define I2C_HS 0x2 +#define TEN_ADDR_FRAME 0x78 +#define TEN_ADDR_MASK 0x3ff +#define SEVEN_ADDR_MASK 0x7f + +/** + * \brief SERCOM I2CM configuration type + */ +struct i2cm_configuration { + uint8_t number; + hri_sercomi2cm_ctrla_reg_t ctrl_a; + hri_sercomi2cm_ctrlb_reg_t ctrl_b; + hri_sercomi2cm_baud_reg_t baud; + hri_sercomi2cm_dbgctrl_reg_t dbgctrl; + uint16_t trise; + uint32_t clk; /* SERCOM peripheral clock frequency */ +}; + +static inline void _i2c_m_enable_implementation(void *hw); +static int32_t _i2c_m_sync_init_impl(struct _i2c_m_service *const service, void *const hw); + +#if SERCOM_I2CM_AMOUNT < 1 +/** Dummy array to pass compiling. */ +static struct i2cm_configuration _i2cms[1] = {{0}}; +#else +/** + * \brief Array of SERCOM I2CM configurations + */ +static struct i2cm_configuration _i2cms[] = { +#if CONF_SERCOM_0_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(0), +#endif +#if CONF_SERCOM_1_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(1), +#endif +#if CONF_SERCOM_2_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(2), +#endif +#if CONF_SERCOM_3_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(3), +#endif +#if CONF_SERCOM_4_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(4), +#endif +#if CONF_SERCOM_5_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(5), +#endif +#if CONF_SERCOM_6_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(6), +#endif +#if CONF_SERCOM_7_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(7), +#endif +}; +#endif + +/** + * \internal Retrieve ordinal number of the given sercom hardware instance + * + * \param[in] hw The pointer to hardware instance + + * \return The ordinal number of the given sercom hardware instance + */ +static int8_t _get_i2cm_index(const void *const hw) +{ + uint8_t sercom_offset = _sercom_get_hardware_index(hw); + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(_i2cms); i++) { + if (_i2cms[i].number == sercom_offset) { + return i; + } + } + + ASSERT(false); + return -1; +} + +static inline void _sercom_i2c_send_stop(void *const hw) +{ + hri_sercomi2cm_set_CTRLB_CMD_bf(hw, CMD_STOP); +} + +/** + * \brief SERCOM I2CM analyze hardware status and transfer next byte + */ +static inline int32_t _sercom_i2c_sync_analyse_flags(void *const hw, uint32_t flags, struct _i2c_m_msg *const msg) +{ + int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); + uint16_t status = hri_sercomi2cm_read_STATUS_reg(hw); + + if (flags & MB_FLAG) { + /* tx error */ + if (status & SERCOM_I2CM_STATUS_ARBLOST) { + hri_sercomi2cm_clear_interrupt_MB_bit(hw); + msg->flags |= I2C_M_FAIL; + msg->flags &= ~I2C_M_BUSY; + + if (status & SERCOM_I2CM_STATUS_BUSERR) { + return I2C_ERR_BUS; + } + + return I2C_ERR_BAD_ADDRESS; + } else { + if (status & SERCOM_I2CM_STATUS_RXNACK) { + + /* Slave rejects to receive more data */ + if (msg->len > 0) { + msg->flags |= I2C_M_FAIL; + } + + if (msg->flags & I2C_M_STOP) { + _sercom_i2c_send_stop(hw); + } + + msg->flags &= ~I2C_M_BUSY; + + return I2C_NACK; + } + + if (msg->flags & I2C_M_TEN) { + hri_sercomi2cm_write_ADDR_reg(hw, + ((((msg->addr & TEN_ADDR_MASK) >> 8) | TEN_ADDR_FRAME) << 1) | I2C_M_RD + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + msg->flags &= ~I2C_M_TEN; + + return I2C_OK; + } + + if (msg->len == 0) { + if (msg->flags & I2C_M_STOP) { + _sercom_i2c_send_stop(hw); + } + + msg->flags &= ~I2C_M_BUSY; + } else { + hri_sercomi2cm_write_DATA_reg(hw, *msg->buffer); + msg->buffer++; + msg->len--; + } + + return I2C_OK; + } + } else if (flags & SB_FLAG) { + if ((msg->len) && !(status & SERCOM_I2CM_STATUS_RXNACK)) { + msg->len--; + + /* last byte, send nack */ + if ((msg->len == 0 && !sclsm) || (msg->len == 1 && sclsm)) { + hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); + } + + if (msg->len == 0) { + if (msg->flags & I2C_M_STOP) { + hri_sercomi2cm_clear_CTRLB_SMEN_bit(hw); + _sercom_i2c_send_stop(hw); + } + + msg->flags &= ~I2C_M_BUSY; + } + + /* Accessing DATA.DATA auto-triggers I2C bus operations. + * The operation performed depends on the state of + * CTRLB.ACKACT, CTRLB.SMEN + **/ + *msg->buffer++ = hri_sercomi2cm_read_DATA_reg(hw); + } else { + hri_sercomi2cm_clear_interrupt_SB_bit(hw); + return I2C_NACK; + } + + hri_sercomi2cm_clear_interrupt_SB_bit(hw); + } + + return I2C_OK; +} + +/** + * \brief Enable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + _i2c_m_enable_implementation(i2c_dev->hw); + + return ERR_NONE; +} + +/** + * \brief Disable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** + * \brief Set baudrate of master + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] clkrate The clock rate of i2c master, in KHz + * \param[in] baudrate The baud rate desired for i2c master, in KHz + */ +int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate) +{ + uint32_t tmp; + void * hw = i2c_dev->hw; + + if (hri_sercomi2cm_get_CTRLA_ENABLE_bit(hw)) { + return ERR_DENIED; + } + + tmp = _get_i2cm_index(hw); + clkrate = _i2cms[tmp].clk / 1000; + + if (i2c_dev->service.mode == I2C_STANDARD_MODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_FASTMODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_HIGHSPEED_MODE) { + tmp = (clkrate - 2 * baudrate) / (2 * baudrate); + hri_sercomi2cm_write_BAUD_HSBAUD_bf(hw, tmp); + } else { + /* error baudrate */ + return ERR_INVALID_ARG; + } + + return ERR_NONE; +} + +/** + * \brief Retrieve IRQ number for the given hardware instance + */ +static uint8_t _sercom_get_irq_num(const void *const hw) +{ + return SERCOM0_IRQn + _sercom_get_hardware_index(hw); +} + +/** + * \brief Initialize sercom i2c module to use in async mode + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw) +{ + int32_t init_status; + + ASSERT(i2c_dev); + + i2c_dev->hw = hw; + + init_status = _i2c_m_sync_init_impl(&i2c_dev->service, hw); + if (init_status) { + return init_status; + } + + _sercom_init_irq_param(hw, (void *)i2c_dev); + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + + return ERR_NONE; +} + +/** + * \brief Deinitialize sercom i2c module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(i2c_dev->hw); + hri_sercomi2cm_set_CTRLA_SWRST_bit(i2c_dev->hw); + + return ERR_NONE; +} + +/** + * \brief Transfer the slave address to bus, which will start the transfer + * + * \param[in] i2c_dev The pointer to i2c device + */ +static int32_t _sercom_i2c_send_address(struct _i2c_m_async_device *const i2c_dev) +{ + void * hw = i2c_dev->hw; + struct _i2c_m_msg *msg = &i2c_dev->service.msg; + int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); + + ASSERT(i2c_dev); + + if (msg->len == 1 && sclsm) { + hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); + } else { + hri_sercomi2cm_clear_CTRLB_ACKACT_bit(hw); + } + + /* ten bit address */ + if (msg->addr & I2C_M_TEN) { + if (msg->flags & I2C_M_RD) { + msg->flags |= I2C_M_TEN; + } + + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & TEN_ADDR_MASK) << 1) | SERCOM_I2CM_ADDR_TENBITEN + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } else { + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & SEVEN_ADDR_MASK) << 1) | (msg->flags & I2C_M_RD ? I2C_M_RD : 0x0) + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } + + return ERR_NONE; +} + +/** + * \brief Transfer data specified by msg + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] msg The pointer to i2c message + * + * \return Transfer status. + * \retval 0 Transfer success + * \retval <0 Transfer fail, return the error code + */ +int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *i2c_dev, struct _i2c_m_msg *msg) +{ + int ret; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + ASSERT(msg); + + if (msg->len == 0) { + return ERR_NONE; + } + + if (i2c_dev->service.msg.flags & I2C_M_BUSY) { + return ERR_BUSY; + } + + msg->flags |= I2C_M_BUSY; + i2c_dev->service.msg = *msg; + hri_sercomi2cm_set_CTRLB_SMEN_bit(i2c_dev->hw); + + ret = _sercom_i2c_send_address(i2c_dev); + + if (ret) { + i2c_dev->service.msg.flags &= ~I2C_M_BUSY; + + return ret; + } + + return ERR_NONE; +} + +/** + * \brief Set callback to be called in interrupt handler + * + * \param[in] i2c_dev The pointer to master i2c device + * \param[in] type The callback type + * \param[in] func The callback function pointer + */ +int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *const i2c_dev, enum _i2c_m_async_callback_type type, + FUNC_PTR func) +{ + switch (type) { + case I2C_M_ASYNC_DEVICE_ERROR: + i2c_dev->cb.error = (_i2c_error_cb_t)func; + break; + case I2C_M_ASYNC_DEVICE_TX_COMPLETE: + i2c_dev->cb.tx_complete = (_i2c_complete_cb_t)func; + break; + case I2C_M_ASYNC_DEVICE_RX_COMPLETE: + i2c_dev->cb.rx_complete = (_i2c_complete_cb_t)func; + break; + default: + /* error */ + break; + } + + return ERR_NONE; +} + +/** + * \brief Set stop condition on I2C + * + * \param i2c_dev Pointer to master i2c device + * + * \return Operation status + * \retval I2C_OK Operation was successfull + */ +int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + _sercom_i2c_send_stop(hw); + + return I2C_OK; +} + +/** + * \brief Get number of bytes left in transfer buffer + * + * \param i2c_dev Pointer to i2c master device + * + * \return Bytes left in buffer + * \retval =>0 Bytes left in buffer + */ +int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev) +{ + if (i2c_dev->service.msg.flags & I2C_M_BUSY) { + return i2c_dev->service.msg.len; + } + + return 0; +} + +/** + * \brief Initialize sercom i2c module to use in sync mode + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw) +{ + ASSERT(i2c_dev); + + i2c_dev->hw = hw; + + return _i2c_m_sync_init_impl(&i2c_dev->service, hw); +} + +/** + * \brief Deinitialize sercom i2c module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(i2c_dev->hw); + hri_sercomi2cm_set_CTRLA_SWRST_bit(i2c_dev->hw); + + return ERR_NONE; +} + +/** + * \brief Enable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + _i2c_m_enable_implementation(i2c_dev->hw); + + return ERR_NONE; +} + +/** + * \brief Disable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** + * \brief Set baudrate of master + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] clkrate The clock rate of i2c master, in KHz + * \param[in] baudrate The baud rate desired for i2c master, in KHz + */ +int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate) +{ + uint32_t tmp; + void * hw = i2c_dev->hw; + + if (hri_sercomi2cm_get_CTRLA_ENABLE_bit(hw)) { + return ERR_DENIED; + } + + tmp = _get_i2cm_index(hw); + clkrate = _i2cms[tmp].clk / 1000; + + if (i2c_dev->service.mode == I2C_STANDARD_MODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_FASTMODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_HIGHSPEED_MODE) { + tmp = (clkrate - 2 * baudrate) / (2 * baudrate); + hri_sercomi2cm_write_BAUD_HSBAUD_bf(hw, tmp); + } else { + /* error baudrate */ + return ERR_INVALID_ARG; + } + + return ERR_NONE; +} + +/** + * \brief Enable/disable I2C master interrupt + */ +void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type, + const bool state) +{ + if (I2C_M_ASYNC_DEVICE_TX_COMPLETE == type || I2C_M_ASYNC_DEVICE_RX_COMPLETE == type) { + hri_sercomi2cm_write_INTEN_SB_bit(device->hw, state); + hri_sercomi2cm_write_INTEN_MB_bit(device->hw, state); + } else if (I2C_M_ASYNC_DEVICE_ERROR == type) { + hri_sercomi2cm_write_INTEN_ERROR_bit(device->hw, state); + } +} + +/** + * \brief Wait for bus response + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] flags Store the hardware response + * + * \return Bus response status. + * \retval 0 Bus response status OK + * \retval <0 Bus response fail + */ +inline static int32_t _sercom_i2c_sync_wait_bus(struct _i2c_m_sync_device *const i2c_dev, uint32_t *flags) +{ + uint32_t timeout = 65535; + void * hw = i2c_dev->hw; + + do { + *flags = hri_sercomi2cm_read_INTFLAG_reg(hw); + + if (timeout-- == 0) { + return I2C_ERR_BUS; + } + } while (!(*flags & MB_FLAG) && !(*flags & SB_FLAG)); + + return I2C_OK; +} + +/** + * \brief Send the slave address to bus, which will start the transfer + * + * \param[in] i2c_dev The pointer to i2c device + */ +static int32_t _sercom_i2c_sync_send_address(struct _i2c_m_sync_device *const i2c_dev) +{ + void * hw = i2c_dev->hw; + struct _i2c_m_msg *msg = &i2c_dev->service.msg; + int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); + uint32_t flags; + + ASSERT(i2c_dev); + + if (msg->len == 1 && sclsm) { + hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); + } else { + hri_sercomi2cm_clear_CTRLB_ACKACT_bit(hw); + } + + /* ten bit address */ + if (msg->addr & I2C_M_TEN) { + if (msg->flags & I2C_M_RD) { + msg->flags |= I2C_M_TEN; + } + + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & TEN_ADDR_MASK) << 1) | SERCOM_I2CM_ADDR_TENBITEN + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } else { + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & SEVEN_ADDR_MASK) << 1) | (msg->flags & I2C_M_RD ? I2C_M_RD : 0x0) + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } + + _sercom_i2c_sync_wait_bus(i2c_dev, &flags); + return _sercom_i2c_sync_analyse_flags(hw, flags, msg); +} + +/** + * \brief Transfer data specified by msg + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] msg The pointer to i2c message + * + * \return Transfer status. + * \retval 0 Transfer success + * \retval <0 Transfer fail or partial fail, return the error code + */ +int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg) +{ + uint32_t flags; + int ret; + void * hw = i2c_dev->hw; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + ASSERT(msg); + + if (i2c_dev->service.msg.flags & I2C_M_BUSY) { + return I2C_ERR_BUSY; + } + + msg->flags |= I2C_M_BUSY; + i2c_dev->service.msg = *msg; + hri_sercomi2cm_set_CTRLB_SMEN_bit(hw); + + ret = _sercom_i2c_sync_send_address(i2c_dev); + + if (ret) { + i2c_dev->service.msg.flags &= ~I2C_M_BUSY; + + return ret; + } + + while (i2c_dev->service.msg.flags & I2C_M_BUSY) { + ret = _sercom_i2c_sync_wait_bus(i2c_dev, &flags); + + if (ret) { + if (msg->flags & I2C_M_STOP) { + _sercom_i2c_send_stop(hw); + } + + i2c_dev->service.msg.flags &= ~I2C_M_BUSY; + + return ret; + } + + ret = _sercom_i2c_sync_analyse_flags(hw, flags, &i2c_dev->service.msg); + } + + return ret; +} + +int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + _sercom_i2c_send_stop(hw); + + return I2C_OK; +} + +static inline void _i2c_m_enable_implementation(void *const hw) +{ + int timeout = 65535; + + ASSERT(hw); + + /* Enable interrupts */ + hri_sercomi2cm_set_CTRLA_ENABLE_bit(hw); + + while (hri_sercomi2cm_read_STATUS_BUSSTATE_bf(hw) != I2C_IDLE) { + timeout--; + + if (timeout <= 0) { + hri_sercomi2cm_clear_STATUS_reg(hw, SERCOM_I2CM_STATUS_BUSSTATE(I2C_IDLE)); + } + } +} + +static int32_t _i2c_m_sync_init_impl(struct _i2c_m_service *const service, void *const hw) +{ + uint8_t i = _get_i2cm_index(hw); + + if (!hri_sercomi2cm_is_syncing(hw, SERCOM_I2CM_SYNCBUSY_SWRST)) { + uint32_t mode = _i2cms[i].ctrl_a & SERCOM_I2CM_CTRLA_MODE_Msk; + if (hri_sercomi2cm_get_CTRLA_reg(hw, SERCOM_I2CM_CTRLA_ENABLE)) { + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_ENABLE); + } + hri_sercomi2cm_write_CTRLA_reg(hw, SERCOM_I2CM_CTRLA_SWRST | mode); + } + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); + + hri_sercomi2cm_write_CTRLA_reg(hw, _i2cms[i].ctrl_a); + hri_sercomi2cm_write_CTRLB_reg(hw, _i2cms[i].ctrl_b); + hri_sercomi2cm_write_BAUD_reg(hw, _i2cms[i].baud); + + service->mode = (_i2cms[i].ctrl_a & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos; + hri_sercomi2cm_write_ADDR_HS_bit(hw, service->mode < I2C_HS ? 0 : 1); + + service->trise = _i2cms[i].trise; + + return ERR_NONE; +} + + /* SERCOM I2C slave */ + +#ifndef CONF_SERCOM_0_I2CS_ENABLE +#define CONF_SERCOM_0_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_I2CS_ENABLE +#define CONF_SERCOM_1_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_I2CS_ENABLE +#define CONF_SERCOM_2_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_I2CS_ENABLE +#define CONF_SERCOM_3_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_I2CS_ENABLE +#define CONF_SERCOM_4_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_I2CS_ENABLE +#define CONF_SERCOM_5_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_I2CS_ENABLE +#define CONF_SERCOM_6_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_I2CS_ENABLE +#define CONF_SERCOM_7_I2CS_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as I2C Slave. */ +#define SERCOM_I2CS_AMOUNT \ + (CONF_SERCOM_0_I2CS_ENABLE + CONF_SERCOM_1_I2CS_ENABLE + CONF_SERCOM_2_I2CS_ENABLE + CONF_SERCOM_3_I2CS_ENABLE \ + + CONF_SERCOM_4_I2CS_ENABLE + CONF_SERCOM_5_I2CS_ENABLE + CONF_SERCOM_6_I2CS_ENABLE + CONF_SERCOM_7_I2CS_ENABLE) + +/** + * \brief Macro is used to fill I2C slave configuration structure based on + * its number + * + * \param[in] n The number of structures + */ +#define I2CS_CONFIGURATION(n) \ + { \ + n, \ + SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE | (CONF_SERCOM_##n##_I2CS_RUNSTDBY << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos) \ + | SERCOM_I2CS_CTRLA_SDAHOLD(CONF_SERCOM_##n##_I2CS_SDAHOLD) \ + | (CONF_SERCOM_##n##_I2CS_SEXTTOEN << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos) \ + | (CONF_SERCOM_##n##_I2CS_SPEED << SERCOM_I2CS_CTRLA_SPEED_Pos) \ + | (CONF_SERCOM_##n##_I2CS_SCLSM << SERCOM_I2CS_CTRLA_SCLSM_Pos) \ + | (CONF_SERCOM_##n##_I2CS_LOWTOUT << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos), \ + SERCOM_I2CS_CTRLB_SMEN | SERCOM_I2CS_CTRLB_AACKEN | SERCOM_I2CS_CTRLB_AMODE(CONF_SERCOM_##n##_I2CS_AMODE), \ + (CONF_SERCOM_##n##_I2CS_GENCEN << SERCOM_I2CS_ADDR_GENCEN_Pos) \ + | SERCOM_I2CS_ADDR_ADDR(CONF_SERCOM_##n##_I2CS_ADDRESS) \ + | (CONF_SERCOM_##n##_I2CS_TENBITEN << SERCOM_I2CS_ADDR_TENBITEN_Pos) \ + | SERCOM_I2CS_ADDR_ADDRMASK(CONF_SERCOM_##n##_I2CS_ADDRESS_MASK) \ + } + +/** + * \brief Macro to check 10-bit addressing + */ +#define I2CS_7BIT_ADDRESSING_MASK 0x7F + +static int32_t _i2c_s_init(void *const hw); +static int8_t _get_i2c_s_index(const void *const hw); +static inline void _i2c_s_deinit(void *const hw); +static int32_t _i2c_s_set_address(void *const hw, const uint16_t address); + +/** + * \brief SERCOM I2C slave configuration type + */ +struct i2cs_configuration { + uint8_t number; + hri_sercomi2cs_ctrla_reg_t ctrl_a; + hri_sercomi2cs_ctrlb_reg_t ctrl_b; + hri_sercomi2cs_addr_reg_t address; +}; + +#if SERCOM_I2CS_AMOUNT < 1 +/** Dummy array for compiling. */ +static struct i2cs_configuration _i2css[1] = {{0}}; +#else +/** + * \brief Array of SERCOM I2C slave configurations + */ +static struct i2cs_configuration _i2css[] = { +#if CONF_SERCOM_0_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(0), +#endif +#if CONF_SERCOM_1_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(1), +#endif +#if CONF_SERCOM_2_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(2), +#endif +#if CONF_SERCOM_3_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(3), +#endif +#if CONF_SERCOM_4_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(4), +#endif +#if CONF_SERCOM_5_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(5), +#endif +}; +#endif + +/** + * \brief Initialize synchronous I2C slave + */ +int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw) +{ + int32_t status; + + ASSERT(device); + + status = _i2c_s_init(hw); + if (status) { + return status; + } + device->hw = hw; + + return ERR_NONE; +} + +/** + * \brief Initialize asynchronous I2C slave + */ +int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw) +{ + int32_t init_status; + + ASSERT(device); + + init_status = _i2c_s_init(hw); + if (init_status) { + return init_status; + } + + device->hw = hw; + _sercom_init_irq_param(hw, (void *)device); + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + + return ERR_NONE; +} + +/** + * \brief Deinitialize synchronous I2C + */ +int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device) +{ + _i2c_s_deinit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Deinitialize asynchronous I2C + */ +int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device) +{ + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(device->hw)); + _i2c_s_deinit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Enable I2C module + */ +int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device) +{ + hri_sercomi2cs_set_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Enable I2C module + */ +int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device) +{ + hri_sercomi2cs_set_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Disable I2C module + */ +int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device) +{ + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Disable I2C module + */ +int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device) +{ + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Check if 10-bit addressing mode is on + */ +int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_get_ADDR_TENBITEN_bit(device->hw); +} + +/** + * \brief Check if 10-bit addressing mode is on + */ +int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device) +{ + return hri_sercomi2cs_get_ADDR_TENBITEN_bit(device->hw); +} + +/** + * \brief Set I2C slave address + */ +int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address) +{ + return _i2c_s_set_address(device->hw, address); +} + +/** + * \brief Set I2C slave address + */ +int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address) +{ + return _i2c_s_set_address(device->hw, address); +} + +/** + * \brief Write a byte to the given I2C instance + */ +void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data) +{ + hri_sercomi2cs_write_DATA_reg(device->hw, data); +} + +/** + * \brief Write a byte to the given I2C instance + */ +void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data) +{ + hri_sercomi2cs_write_DATA_reg(device->hw, data); +} + +/** + * \brief Read a byte from the given I2C instance + */ +uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_read_DATA_reg(device->hw); +} + +/** + * \brief Check if I2C is ready to send next byt + */ +bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_get_interrupt_DRDY_bit(device->hw); +} + +/** + * \brief Check if there is data received by I2C + */ +bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_get_interrupt_DRDY_bit(device->hw); +} + +/** + * \brief Retrieve I2C slave status + */ +i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_read_STATUS_reg(device->hw); +} + +/** + * \brief Clear the Data Ready interrupt flag + */ +int32_t _i2c_s_sync_clear_data_ready_flag(const struct _i2c_s_sync_device *const device) +{ + hri_sercomi2cs_clear_INTFLAG_DRDY_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Retrieve I2C slave status + */ +i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device) +{ + return hri_sercomi2cs_read_STATUS_reg(device->hw); +} + +/** + * \brief Abort data transmission + */ +int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device) +{ + hri_sercomi2cs_clear_INTEN_DRDY_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Enable/disable I2C slave interrupt + */ +int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type, + const bool state) +{ + ASSERT(device); + + if (I2C_S_DEVICE_TX == type || I2C_S_DEVICE_RX_COMPLETE == type) { + hri_sercomi2cs_write_INTEN_DRDY_bit(device->hw, state); + } else if (I2C_S_DEVICE_ERROR == type) { + hri_sercomi2cs_write_INTEN_ERROR_bit(device->hw, state); + } + + return ERR_NONE; +} + +/** + * \internal Initalize i2c slave hardware + * + * \param[in] p The pointer to hardware instance + * + *\ return status of initialization + */ +static int32_t _i2c_s_init(void *const hw) +{ + int8_t i = _get_i2c_s_index(hw); + if (i == -1) { + return ERR_INVALID_ARG; + } + + if (!hri_sercomi2cs_is_syncing(hw, SERCOM_I2CS_CTRLA_SWRST)) { + uint32_t mode = _i2css[i].ctrl_a & SERCOM_I2CS_CTRLA_MODE_Msk; + if (hri_sercomi2cs_get_CTRLA_reg(hw, SERCOM_I2CS_CTRLA_ENABLE)) { + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_ENABLE); + } + hri_sercomi2cs_write_CTRLA_reg(hw, SERCOM_I2CS_CTRLA_SWRST | mode); + } + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); + + hri_sercomi2cs_write_CTRLA_reg(hw, _i2css[i].ctrl_a); + hri_sercomi2cs_write_CTRLB_reg(hw, _i2css[i].ctrl_b); + hri_sercomi2cs_write_ADDR_reg(hw, _i2css[i].address); + + return ERR_NONE; +} + +/** + * \internal Retrieve ordinal number of the given sercom hardware instance + * + * \param[in] hw The pointer to hardware instance + * + * \return The ordinal number of the given sercom hardware instance + */ +static int8_t _get_i2c_s_index(const void *const hw) +{ + uint8_t sercom_offset = _sercom_get_hardware_index(hw); + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(_i2css); i++) { + if (_i2css[i].number == sercom_offset) { + return i; + } + } + + ASSERT(false); + return -1; +} + +/** + * \internal De-initialize i2c slave + * + * \param[in] hw The pointer to hardware instance + */ +static inline void _i2c_s_deinit(void *const hw) +{ + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); + hri_sercomi2cs_set_CTRLA_SWRST_bit(hw); +} + +/** + * \internal De-initialize i2c slave + * + * \param[in] hw The pointer to hardware instance + * \param[in] address Address to set + */ +static int32_t _i2c_s_set_address(void *const hw, const uint16_t address) +{ + bool enabled; + + enabled = hri_sercomi2cs_get_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); + hri_sercomi2cs_write_ADDR_ADDR_bf(hw, address); + CRITICAL_SECTION_LEAVE() + + if (enabled) { + hri_sercomi2cs_set_CTRLA_ENABLE_bit(hw); + } + + return ERR_NONE; +} + + /* Sercom SPI implementation */ + +#ifndef SERCOM_USART_CTRLA_MODE_SPI_SLAVE +#define SERCOM_USART_CTRLA_MODE_SPI_SLAVE (2 << 2) +#endif + +#define SPI_DEV_IRQ_MODE 0x8000 + +#define _SPI_CS_PORT_EXTRACT(cs) (((cs) >> 0) & 0xFF) +#define _SPI_CS_PIN_EXTRACT(cs) (((cs) >> 8) & 0xFF) + +COMPILER_PACK_SET(1) +/** Initialization configuration of registers. */ +struct sercomspi_regs_cfg { + uint32_t ctrla; + uint32_t ctrlb; + uint32_t addr; + uint8_t baud; + uint8_t dbgctrl; + uint16_t dummy_byte; + uint8_t n; +}; +COMPILER_PACK_RESET() + +/** Build configuration from header macros. */ +#define SERCOMSPI_REGS(n) \ + { \ + (((CONF_SERCOM_##n##_SPI_DORD) << SERCOM_SPI_CTRLA_DORD_Pos) \ + | (CONF_SERCOM_##n##_SPI_CPOL << SERCOM_SPI_CTRLA_CPOL_Pos) \ + | (CONF_SERCOM_##n##_SPI_CPHA << SERCOM_SPI_CTRLA_CPHA_Pos) \ + | (CONF_SERCOM_##n##_SPI_AMODE_EN ? SERCOM_SPI_CTRLA_FORM(2) : SERCOM_SPI_CTRLA_FORM(0)) \ + | SERCOM_SPI_CTRLA_DOPO(CONF_SERCOM_##n##_SPI_TXPO) | SERCOM_SPI_CTRLA_DIPO(CONF_SERCOM_##n##_SPI_RXPO) \ + | (CONF_SERCOM_##n##_SPI_IBON << SERCOM_SPI_CTRLA_IBON_Pos) \ + | (CONF_SERCOM_##n##_SPI_RUNSTDBY << SERCOM_SPI_CTRLA_RUNSTDBY_Pos) \ + | SERCOM_SPI_CTRLA_MODE(CONF_SERCOM_##n##_SPI_MODE)), /* ctrla */ \ + ((CONF_SERCOM_##n##_SPI_RXEN << SERCOM_SPI_CTRLB_RXEN_Pos) \ + | (CONF_SERCOM_##n##_SPI_MSSEN << SERCOM_SPI_CTRLB_MSSEN_Pos) \ + | (CONF_SERCOM_##n##_SPI_SSDE << SERCOM_SPI_CTRLB_SSDE_Pos) \ + | (CONF_SERCOM_##n##_SPI_PLOADEN << SERCOM_SPI_CTRLB_PLOADEN_Pos) \ + | SERCOM_SPI_CTRLB_AMODE(CONF_SERCOM_##n##_SPI_AMODE) \ + | SERCOM_SPI_CTRLB_CHSIZE(CONF_SERCOM_##n##_SPI_CHSIZE)), /* ctrlb */ \ + (SERCOM_SPI_ADDR_ADDR(CONF_SERCOM_##n##_SPI_ADDR) \ + | SERCOM_SPI_ADDR_ADDRMASK(CONF_SERCOM_##n##_SPI_ADDRMASK)), /* addr */ \ + ((uint8_t)CONF_SERCOM_##n##_SPI_BAUD_RATE), /* baud */ \ + (CONF_SERCOM_##n##_SPI_DBGSTOP << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos), /* dbgctrl */ \ + CONF_SERCOM_##n##_SPI_DUMMYBYTE, /* Dummy byte for SPI master mode */ \ + n /* sercom number */ \ + } + +#ifndef CONF_SERCOM_0_SPI_ENABLE +#define CONF_SERCOM_0_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_SPI_ENABLE +#define CONF_SERCOM_1_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_SPI_ENABLE +#define CONF_SERCOM_2_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_SPI_ENABLE +#define CONF_SERCOM_3_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_SPI_ENABLE +#define CONF_SERCOM_4_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_SPI_ENABLE +#define CONF_SERCOM_5_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_SPI_ENABLE +#define CONF_SERCOM_6_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_SPI_ENABLE +#define CONF_SERCOM_7_SPI_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as SPI */ +#define SERCOM_SPI_AMOUNT \ + (CONF_SERCOM_0_SPI_ENABLE + CONF_SERCOM_1_SPI_ENABLE + CONF_SERCOM_2_SPI_ENABLE + CONF_SERCOM_3_SPI_ENABLE \ + + CONF_SERCOM_4_SPI_ENABLE + CONF_SERCOM_5_SPI_ENABLE + CONF_SERCOM_6_SPI_ENABLE + CONF_SERCOM_7_SPI_ENABLE) + +#if SERCOM_SPI_AMOUNT < 1 +/** Dummy array for compiling. */ +static const struct sercomspi_regs_cfg sercomspi_regs[1] = {{0}}; +#else +/** The SERCOM SPI configurations of SERCOM that is used as SPI. */ +static const struct sercomspi_regs_cfg sercomspi_regs[] = { +#if CONF_SERCOM_0_SPI_ENABLE + SERCOMSPI_REGS(0), +#endif +#if CONF_SERCOM_1_SPI_ENABLE + SERCOMSPI_REGS(1), +#endif +#if CONF_SERCOM_2_SPI_ENABLE + SERCOMSPI_REGS(2), +#endif +#if CONF_SERCOM_3_SPI_ENABLE + SERCOMSPI_REGS(3), +#endif +#if CONF_SERCOM_4_SPI_ENABLE + SERCOMSPI_REGS(4), +#endif +#if CONF_SERCOM_5_SPI_ENABLE + SERCOMSPI_REGS(5), +#endif +#if CONF_SERCOM_6_SPI_ENABLE + SERCOMSPI_REGS(6), +#endif +#if CONF_SERCOM_7_SPI_ENABLE + SERCOMSPI_REGS(7), +#endif +}; +#endif + +/** \internal De-initialize SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return De-initialization status + */ +static int32_t _spi_deinit(void *const hw) +{ + hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); + hri_sercomspi_set_CTRLA_SWRST_bit(hw); + + return ERR_NONE; +} + +/** \internal Enable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Enabling status + */ +static int32_t _spi_sync_enable(void *const hw) +{ + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + + hri_sercomspi_set_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** \internal Enable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Enabling status + */ +static int32_t _spi_async_enable(void *const hw) +{ + _spi_sync_enable(hw); + NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + + return ERR_NONE; +} + +/** \internal Disable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Disabling status + */ +static int32_t _spi_sync_disable(void *const hw) +{ + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** \internal Disable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Disabling status + */ +static int32_t _spi_async_disable(void *const hw) +{ + _spi_sync_disable(hw); + hri_sercomspi_clear_INTEN_reg( + hw, SERCOM_SPI_INTFLAG_ERROR | SERCOM_SPI_INTFLAG_RXC | SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE); + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI mode + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] mode The mode to set + * + * \return Setting mode status + */ +static int32_t _spi_set_mode(void *const hw, const enum spi_transfer_mode mode) +{ + uint32_t ctrla; + + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE)) { + return ERR_BUSY; + } + + ctrla = hri_sercomspi_read_CTRLA_reg(hw); + ctrla &= ~(SERCOM_SPI_CTRLA_CPOL | SERCOM_SPI_CTRLA_CPHA); + ctrla |= (mode & 0x3u) << SERCOM_SPI_CTRLA_CPHA_Pos; + hri_sercomspi_write_CTRLA_reg(hw, ctrla); + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI baudrate + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] baud_val The baudrate to set + * + * \return Setting baudrate status + */ +static int32_t _spi_set_baudrate(void *const hw, const uint32_t baud_val) +{ + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + + hri_sercomspi_write_BAUD_reg(hw, baud_val); + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI char size + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] baud_val The baudrate to set + * \param[out] size Stored char size + * + * \return Setting char size status + */ +static int32_t _spi_set_char_size(void *const hw, const enum spi_char_size char_size, uint8_t *const size) +{ + /* Only 8-bit or 9-bit accepted */ + if (!(char_size == SPI_CHAR_SIZE_8 || char_size == SPI_CHAR_SIZE_9)) { + return ERR_INVALID_ARG; + } + + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_CTRLB)) { + return ERR_BUSY; + } + + hri_sercomspi_write_CTRLB_CHSIZE_bf(hw, char_size); + *size = (char_size == SPI_CHAR_SIZE_8) ? 1 : 2; + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI data order + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] baud_val The baudrate to set + * + * \return Setting data order status + */ +static int32_t _spi_set_data_order(void *const hw, const enum spi_data_order dord) +{ + uint32_t ctrla; + + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + + ctrla = hri_sercomspi_read_CTRLA_reg(hw); + + if (dord == SPI_DATA_ORDER_LSB_1ST) { + ctrla |= SERCOM_SPI_CTRLA_DORD; + } else { + ctrla &= ~SERCOM_SPI_CTRLA_DORD; + } + hri_sercomspi_write_CTRLA_reg(hw, ctrla); + + return ERR_NONE; +} + +/** \brief Load SERCOM registers to init for SPI master mode + * The settings will be applied with default master mode, unsupported things + * are ignored. + * \param[in, out] hw Pointer to the hardware register base. + * \param[in] regs Pointer to register configuration values. + */ +static inline void _spi_load_regs_master(void *const hw, const struct sercomspi_regs_cfg *regs) +{ + ASSERT(hw && regs); + hri_sercomspi_write_CTRLA_reg( + hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST)); + hri_sercomspi_write_CTRLB_reg( + hw, + (regs->ctrlb + & ~(SERCOM_SPI_CTRLB_MSSEN | SERCOM_SPI_CTRLB_AMODE_Msk | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN)) + | (SERCOM_SPI_CTRLB_RXEN)); + hri_sercomspi_write_BAUD_reg(hw, regs->baud); + hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl); +} + +/** \brief Load SERCOM registers to init for SPI slave mode + * The settings will be applied with default slave mode, unsupported things + * are ignored. + * \param[in, out] hw Pointer to the hardware register base. + * \param[in] regs Pointer to register configuration values. + */ +static inline void _spi_load_regs_slave(void *const hw, const struct sercomspi_regs_cfg *regs) +{ + ASSERT(hw && regs); + hri_sercomspi_write_CTRLA_reg( + hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST)); + hri_sercomspi_write_CTRLB_reg(hw, + (regs->ctrlb & ~(SERCOM_SPI_CTRLB_MSSEN)) + | (SERCOM_SPI_CTRLB_RXEN | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN)); + hri_sercomspi_write_ADDR_reg(hw, regs->addr); + hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl); + while (hri_sercomspi_is_syncing(hw, 0xFFFFFFFF)) + ; +} + +/** \brief Return the pointer to register settings of specific SERCOM + * \param[in] hw_addr The hardware register base address. + * \return Pointer to register settings of specific SERCOM. + */ +static inline const struct sercomspi_regs_cfg *_spi_get_regs(const uint32_t hw_addr) +{ + uint8_t n = _sercom_get_hardware_index((const void *)hw_addr); + uint8_t i; + + for (i = 0; i < sizeof(sercomspi_regs) / sizeof(struct sercomspi_regs_cfg); i++) { + if (sercomspi_regs[i].n == n) { + return &sercomspi_regs[i]; + } + } + + return NULL; +} + +int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw) +{ + const struct sercomspi_regs_cfg *regs = _spi_get_regs((uint32_t)hw); + + ASSERT(dev && hw); + + if (regs == NULL) { + return ERR_INVALID_ARG; + } + + if (!hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + uint32_t mode = regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk; + if (hri_sercomspi_get_CTRLA_reg(hw, SERCOM_SPI_CTRLA_ENABLE)) { + hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_ENABLE); + } + hri_sercomspi_write_CTRLA_reg(hw, SERCOM_SPI_CTRLA_SWRST | mode); + } + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); + + dev->prvt = hw; + + if ((regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk) == SERCOM_USART_CTRLA_MODE_SPI_SLAVE) { + _spi_load_regs_slave(hw, regs); + } else { + _spi_load_regs_master(hw, regs); + } + + /* Load character size from default hardware configuration */ + dev->char_size = ((regs->ctrlb & SERCOM_SPI_CTRLB_CHSIZE_Msk) == 0) ? 1 : 2; + + dev->dummy_byte = regs->dummy_byte; + + return ERR_NONE; +} + +int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw) +{ + return _spi_m_sync_init(dev, hw); +} + +int32_t _spi_m_async_init(struct _spi_async_dev *dev, void *const hw) +{ + struct _spi_async_dev *spid = dev; + /* Do hardware initialize. */ + int32_t rc = _spi_m_sync_init((struct _spi_m_sync_dev *)dev, hw); + + if (rc < 0) { + return rc; + } + + _sercom_init_irq_param(hw, (void *)dev); + /* Initialize callbacks: must use them */ + spid->callbacks.complete = NULL; + spid->callbacks.rx = NULL; + spid->callbacks.tx = NULL; + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + + return ERR_NONE; +} + +int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw) +{ + return _spi_m_async_init(dev, hw); +} + +int32_t _spi_m_async_deinit(struct _spi_async_dev *dev) +{ + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); + + return _spi_deinit(dev->prvt); +} + +int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev) +{ + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); + + return _spi_deinit(dev->prvt); +} + +int32_t _spi_m_sync_deinit(struct _spi_m_sync_dev *dev) +{ + return _spi_deinit(dev->prvt); +} + +int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev) +{ + return _spi_deinit(dev->prvt); +} + +int32_t _spi_m_sync_enable(struct _spi_m_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_enable(dev->prvt); +} + +int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_enable(dev->prvt); +} + +int32_t _spi_m_async_enable(struct _spi_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_enable(dev->prvt); +} + +int32_t _spi_s_async_enable(struct _spi_s_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_enable(dev->prvt); +} + +int32_t _spi_m_sync_disable(struct _spi_m_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_disable(dev->prvt); +} + +int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_disable(dev->prvt); +} + +int32_t _spi_m_async_disable(struct _spi_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_disable(dev->prvt); +} + +int32_t _spi_s_async_disable(struct _spi_s_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_disable(dev->prvt); +} + +int32_t _spi_m_sync_set_mode(struct _spi_m_sync_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_m_async_set_mode(struct _spi_async_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_s_async_set_mode(struct _spi_s_async_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_calc_baud_val(struct spi_dev *dev, const uint32_t clk, const uint32_t baud) +{ + int32_t rc; + ASSERT(dev); + + /* Not accept 0es */ + if (clk == 0 || baud == 0) { + return ERR_INVALID_ARG; + } + + /* Check baudrate range of current assigned clock */ + if (!(baud <= (clk >> 1) && baud >= (clk >> 8))) { + return ERR_INVALID_ARG; + } + + rc = ((clk >> 1) / baud) - 1; + return rc; +} + +int32_t _spi_m_sync_set_baudrate(struct _spi_m_sync_dev *dev, const uint32_t baud_val) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_baudrate(dev->prvt, baud_val); +} + +int32_t _spi_m_async_set_baudrate(struct _spi_async_dev *dev, const uint32_t baud_val) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_baudrate(dev->prvt, baud_val); +} + +int32_t _spi_m_sync_set_char_size(struct _spi_m_sync_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_m_async_set_char_size(struct _spi_async_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_s_async_set_char_size(struct _spi_s_async_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_m_sync_set_data_order(struct _spi_m_sync_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +int32_t _spi_m_async_set_data_order(struct _spi_async_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +int32_t _spi_s_async_set_data_order(struct _spi_s_async_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +/** Wait until SPI bus idle. */ +static inline void _spi_wait_bus_idle(void *const hw) +{ + while (!(hri_sercomspi_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE))) { + ; + } + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE); +} + +/** Holds run time information for message sync transaction. */ +struct _spi_trans_ctrl { + /** Pointer to transmitting data buffer. */ + uint8_t *txbuf; + /** Pointer to receiving data buffer. */ + uint8_t *rxbuf; + /** Count number of data transmitted. */ + uint32_t txcnt; + /** Count number of data received. */ + uint32_t rxcnt; + /** Data character size. */ + uint8_t char_size; +}; + +/** Check interrupt flag of RXC and update transaction runtime information. */ +static inline bool _spi_rx_check_and_receive(void *const hw, const uint32_t iflag, struct _spi_trans_ctrl *ctrl) +{ + uint32_t data; + + if (!(iflag & SERCOM_SPI_INTFLAG_RXC)) { + return false; + } + + data = hri_sercomspi_read_DATA_reg(hw); + + if (ctrl->rxbuf) { + *ctrl->rxbuf++ = (uint8_t)data; + + if (ctrl->char_size > 1) { + *ctrl->rxbuf++ = (uint8_t)(data >> 8); + } + } + + ctrl->rxcnt++; + + return true; +} + +/** Check interrupt flag of DRE and update transaction runtime information. */ +static inline void _spi_tx_check_and_send(void *const hw, const uint32_t iflag, struct _spi_trans_ctrl *ctrl, + uint16_t dummy) +{ + uint32_t data; + + if (!(SERCOM_SPI_INTFLAG_DRE & iflag)) { + return; + } + + if (ctrl->txbuf) { + data = *ctrl->txbuf++; + + if (ctrl->char_size > 1) { + data |= (*ctrl->txbuf) << 8; + ctrl->txbuf++; + } + } else { + data = dummy; + } + + ctrl->txcnt++; + hri_sercomspi_write_DATA_reg(hw, data); +} + +/** Check interrupt flag of ERROR and update transaction runtime information. */ +static inline int32_t _spi_err_check(const uint32_t iflag, void *const hw) +{ + if (SERCOM_SPI_INTFLAG_ERROR & iflag) { + hri_sercomspi_clear_STATUS_reg(hw, ~0); + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR); + return ERR_OVERFLOW; + } + + return ERR_NONE; +} + +int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg) +{ + void * hw = dev->prvt; + int32_t rc = 0; + struct _spi_trans_ctrl ctrl = {msg->txbuf, msg->rxbuf, 0, 0, dev->char_size}; + + ASSERT(dev && hw); + + /* If settings are not applied (pending), we can not go on */ + if (hri_sercomspi_is_syncing( + hw, (SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE | SERCOM_SPI_SYNCBUSY_CTRLB))) { + return ERR_BUSY; + } + + /* SPI must be enabled to start synchronous transfer */ + if (!hri_sercomspi_get_CTRLA_ENABLE_bit(hw)) { + return ERR_NOT_INITIALIZED; + } + + for (;;) { + uint32_t iflag = hri_sercomspi_read_INTFLAG_reg(hw); + + if (!_spi_rx_check_and_receive(hw, iflag, &ctrl)) { + /* In master mode, do not start next byte before previous byte received + * to make better output waveform */ + if (ctrl.rxcnt >= ctrl.txcnt) { + _spi_tx_check_and_send(hw, iflag, &ctrl, dev->dummy_byte); + } + } + + rc = _spi_err_check(iflag, hw); + + if (rc < 0) { + break; + } + if (ctrl.txcnt >= msg->size && ctrl.rxcnt >= msg->size) { + rc = ctrl.txcnt; + break; + } + } + /* Wait until SPI bus idle */ + _spi_wait_bus_idle(hw); + + return rc; +} + +int32_t _spi_m_async_enable_tx(struct _spi_async_dev *dev, bool state) +{ + void *hw = dev->prvt; + + ASSERT(dev && hw); + + if (state) { + hri_sercomspi_set_INTEN_DRE_bit(hw); + } else { + hri_sercomspi_clear_INTEN_DRE_bit(hw); + } + + return ERR_NONE; +} + +int32_t _spi_s_async_enable_tx(struct _spi_s_async_dev *dev, bool state) +{ + return _spi_m_async_enable_tx(dev, state); +} + +int32_t _spi_m_async_enable_rx(struct _spi_async_dev *dev, bool state) +{ + void *hw = dev->prvt; + + ASSERT(dev); + ASSERT(hw); + + if (state) { + hri_sercomspi_set_INTEN_RXC_bit(hw); + } else { + hri_sercomspi_clear_INTEN_RXC_bit(hw); + } + + return ERR_NONE; +} + +int32_t _spi_s_async_enable_rx(struct _spi_s_async_dev *dev, bool state) +{ + return _spi_m_async_enable_rx(dev, state); +} + +int32_t _spi_m_async_enable_tx_complete(struct _spi_async_dev *dev, bool state) +{ + ASSERT(dev && dev->prvt); + + if (state) { + hri_sercomspi_set_INTEN_TXC_bit(dev->prvt); + } else { + hri_sercomspi_clear_INTEN_TXC_bit(dev->prvt); + } + + return ERR_NONE; +} + +int32_t _spi_s_async_enable_ss_detect(struct _spi_s_async_dev *dev, bool state) +{ + return _spi_m_async_enable_tx_complete(dev, state); +} + +int32_t _spi_m_async_write_one(struct _spi_async_dev *dev, uint16_t data) +{ + ASSERT(dev && dev->prvt); + + hri_sercomspi_write_DATA_reg(dev->prvt, data); + + return ERR_NONE; +} + +int32_t _spi_s_async_write_one(struct _spi_s_async_dev *dev, uint16_t data) +{ + ASSERT(dev && dev->prvt); + + hri_sercomspi_write_DATA_reg(dev->prvt, data); + + return ERR_NONE; +} + +int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data) +{ + ASSERT(dev && dev->prvt); + + hri_sercomspi_write_DATA_reg(dev->prvt, data); + + return ERR_NONE; +} + +uint16_t _spi_m_async_read_one(struct _spi_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomspi_read_DATA_reg(dev->prvt); +} + +uint16_t _spi_s_async_read_one(struct _spi_s_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomspi_read_DATA_reg(dev->prvt); +} + +uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomspi_read_DATA_reg(dev->prvt); +} + +int32_t _spi_m_async_register_callback(struct _spi_async_dev *dev, const enum _spi_async_dev_cb_type cb_type, + const FUNC_PTR func) +{ + typedef void (*func_t)(void); + struct _spi_async_dev *spid = dev; + + ASSERT(dev && (cb_type < SPI_DEV_CB_N)); + + func_t *p_ls = (func_t *)&spid->callbacks; + p_ls[cb_type] = (func_t)func; + + return ERR_NONE; +} + +int32_t _spi_s_async_register_callback(struct _spi_s_async_dev *dev, const enum _spi_s_async_dev_cb_type cb_type, + const FUNC_PTR func) +{ + return _spi_m_async_register_callback(dev, cb_type, func); +} + +bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomi2cm_get_INTFLAG_reg(dev->prvt, SERCOM_SPI_INTFLAG_DRE); +} + +bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomi2cm_get_INTFLAG_reg(dev->prvt, SERCOM_SPI_INTFLAG_RXC); +} + +bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev) +{ + void *hw = dev->prvt; + + ASSERT(dev && hw); + + if (hri_sercomi2cm_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC)) { + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC); + return true; + } + return false; +} + +bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev) +{ + void *hw = dev->prvt; + + ASSERT(dev && hw); + + if (hri_sercomi2cm_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR)) { + hri_sercomspi_clear_STATUS_reg(hw, SERCOM_SPI_STATUS_BUFOVF); + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR); + return true; + } + return false; +} + +/** + * \brief Enable/disable SPI master interrupt + * + * param[in] device The pointer to SPI master device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _spi_m_async_set_irq_state(struct _spi_async_dev *const device, const enum _spi_async_dev_cb_type type, + const bool state) +{ + ASSERT(device); + + if (SPI_DEV_CB_ERROR == type) { + hri_sercomspi_write_INTEN_ERROR_bit(device->prvt, state); + } +} + +/** + * \brief Enable/disable SPI slave interrupt + * + * param[in] device The pointer to SPI slave device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _spi_s_async_set_irq_state(struct _spi_async_dev *const device, const enum _spi_async_dev_cb_type type, + const bool state) +{ + _spi_m_async_set_irq_state(device, type, state); +} diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hpl/systick/hpl_systick.c b/prototype/firmware/I2C_scanner/I2C_scanner/hpl/systick/hpl_systick.c new file mode 100644 index 00000000..3caf6746 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hpl/systick/hpl_systick.c @@ -0,0 +1,103 @@ + +/** + * \file + * + * \brief SysTick related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** + * \brief Initialize system time module + */ +void _system_time_init(void *const hw) +{ + (void)hw; + SysTick->LOAD = (0xFFFFFF << SysTick_LOAD_RELOAD_Pos); + SysTick->CTRL = (1 << SysTick_CTRL_ENABLE_Pos) | (CONF_SYSTICK_TICKINT << SysTick_CTRL_TICKINT_Pos) + | (1 << SysTick_CTRL_CLKSOURCE_Pos); +} +/** + * \brief Initialize delay functionality + */ +void _delay_init(void *const hw) +{ + _system_time_init(hw); +} + +/** + * \brief De-initialize system time module + */ +void _system_time_deinit(void *const hw) +{ + (void)hw; + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; +} + +/** + * \brief Get system time + */ +system_time_t _system_time_get(const void *const hw) +{ + (void)hw; + return (system_time_t)SysTick->VAL; +} + +/** + * \brief Get maximum possible system time + */ +system_time_t _system_time_get_max_time_value(const void *const hw) +{ + (void)hw; + return 0xFFFFFF; +} +/** + * \brief Delay loop to delay n number of cycles + */ +void _delay_cycles(void *const hw, uint32_t cycles) +{ + (void)hw; + uint8_t n = cycles >> 24; + uint32_t buf = cycles; + + while (n--) { + SysTick->LOAD = 0xFFFFFF; + SysTick->VAL = 0xFFFFFF; + while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)) + ; + buf -= 0xFFFFFF; + } + + SysTick->LOAD = buf; + SysTick->VAL = buf; + while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)) + ; +} diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_ac_l21.h b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_ac_l21.h new file mode 100644 index 00000000..e7c6018b --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_ac_l21.h @@ -0,0 +1,1746 @@ +/** + * \file + * + * \brief SAM AC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_AC_COMPONENT_ +#ifndef _HRI_AC_L21_H_INCLUDED_ +#define _HRI_AC_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_AC_CRITICAL_SECTIONS) +#define AC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define AC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define AC_CRITICAL_SECTION_ENTER() +#define AC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_ac_evctrl_reg_t; +typedef uint32_t hri_ac_compctrl_reg_t; +typedef uint32_t hri_ac_syncbusy_reg_t; +typedef uint8_t hri_ac_ctrla_reg_t; +typedef uint8_t hri_ac_ctrlb_reg_t; +typedef uint8_t hri_ac_dbgctrl_reg_t; +typedef uint8_t hri_ac_intenset_reg_t; +typedef uint8_t hri_ac_intflag_reg_t; +typedef uint8_t hri_ac_scaler_reg_t; +typedef uint8_t hri_ac_statusa_reg_t; +typedef uint8_t hri_ac_statusb_reg_t; +typedef uint8_t hri_ac_winctrl_reg_t; + +static inline void hri_ac_wait_for_sync(const void *const hw, hri_ac_syncbusy_reg_t reg) +{ + while (((Ac *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_ac_is_syncing(const void *const hw, hri_ac_syncbusy_reg_t reg) +{ + return ((Ac *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_ac_get_INTFLAG_COMP0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos; +} + +static inline void hri_ac_clear_INTFLAG_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0; +} + +static inline bool hri_ac_get_INTFLAG_COMP1_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos; +} + +static inline void hri_ac_clear_INTFLAG_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1; +} + +static inline bool hri_ac_get_INTFLAG_WIN0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos; +} + +static inline void hri_ac_clear_INTFLAG_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0; +} + +static inline bool hri_ac_get_interrupt_COMP0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos; +} + +static inline void hri_ac_clear_interrupt_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0; +} + +static inline bool hri_ac_get_interrupt_COMP1_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos; +} + +static inline void hri_ac_clear_interrupt_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1; +} + +static inline bool hri_ac_get_interrupt_WIN0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos; +} + +static inline void hri_ac_clear_interrupt_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0; +} + +static inline hri_ac_intflag_reg_t hri_ac_get_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_intflag_reg_t hri_ac_read_INTFLAG_reg(const void *const hw) +{ + return ((Ac *)hw)->INTFLAG.reg; +} + +static inline void hri_ac_clear_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask) +{ + ((Ac *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_ac_set_INTEN_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0; +} + +static inline bool hri_ac_get_INTEN_COMP0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP0) >> AC_INTENSET_COMP0_Pos; +} + +static inline void hri_ac_write_INTEN_COMP0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0; + } else { + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0; + } +} + +static inline void hri_ac_clear_INTEN_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0; +} + +static inline void hri_ac_set_INTEN_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1; +} + +static inline bool hri_ac_get_INTEN_COMP1_bit(const void *const hw) +{ + return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP1) >> AC_INTENSET_COMP1_Pos; +} + +static inline void hri_ac_write_INTEN_COMP1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1; + } else { + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1; + } +} + +static inline void hri_ac_clear_INTEN_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1; +} + +static inline void hri_ac_set_INTEN_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0; +} + +static inline bool hri_ac_get_INTEN_WIN0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_WIN0) >> AC_INTENSET_WIN0_Pos; +} + +static inline void hri_ac_write_INTEN_WIN0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0; + } else { + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0; + } +} + +static inline void hri_ac_clear_INTEN_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0; +} + +static inline void hri_ac_set_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) +{ + ((Ac *)hw)->INTENSET.reg = mask; +} + +static inline hri_ac_intenset_reg_t hri_ac_get_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_intenset_reg_t hri_ac_read_INTEN_reg(const void *const hw) +{ + return ((Ac *)hw)->INTENSET.reg; +} + +static inline void hri_ac_write_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t data) +{ + ((Ac *)hw)->INTENSET.reg = data; + ((Ac *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_ac_clear_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) +{ + ((Ac *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_ac_get_STATUSA_STATE0_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE0) >> AC_STATUSA_STATE0_Pos; +} + +static inline bool hri_ac_get_STATUSA_STATE1_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE1) >> AC_STATUSA_STATE1_Pos; +} + +static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_WSTATE0_bf(const void *const hw, hri_ac_statusa_reg_t mask) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0(mask)) >> AC_STATUSA_WSTATE0_Pos; +} + +static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_WSTATE0_bf(const void *const hw) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0_Msk) >> AC_STATUSA_WSTATE0_Pos; +} + +static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_reg(const void *const hw, hri_ac_statusa_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->STATUSA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_reg(const void *const hw) +{ + return ((Ac *)hw)->STATUSA.reg; +} + +static inline bool hri_ac_get_STATUSB_READY0_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY0) >> AC_STATUSB_READY0_Pos; +} + +static inline bool hri_ac_get_STATUSB_READY1_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY1) >> AC_STATUSB_READY1_Pos; +} + +static inline hri_ac_statusb_reg_t hri_ac_get_STATUSB_reg(const void *const hw, hri_ac_statusb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->STATUSB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_statusb_reg_t hri_ac_read_STATUSB_reg(const void *const hw) +{ + return ((Ac *)hw)->STATUSB.reg; +} + +static inline bool hri_ac_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_SWRST) >> AC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_ENABLE) >> AC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_WINCTRL_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_WINCTRL) >> AC_SYNCBUSY_WINCTRL_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_COMPCTRL0_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL0) >> AC_SYNCBUSY_COMPCTRL0_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_COMPCTRL1_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL1) >> AC_SYNCBUSY_COMPCTRL1_Pos; +} + +static inline hri_ac_syncbusy_reg_t hri_ac_get_SYNCBUSY_reg(const void *const hw, hri_ac_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_syncbusy_reg_t hri_ac_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Ac *)hw)->SYNCBUSY.reg; +} + +static inline void hri_ac_set_CTRLA_SWRST_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg |= AC_CTRLA_SWRST; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp = (tmp & AC_CTRLA_SWRST) >> AC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_ac_set_CTRLA_ENABLE_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg |= AC_CTRLA_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp = (tmp & AC_CTRLA_ENABLE) >> AC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp &= ~AC_CTRLA_ENABLE; + tmp |= value << AC_CTRLA_ENABLE_Pos; + ((Ac *)hw)->CTRLA.reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg &= ~AC_CTRLA_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg ^= AC_CTRLA_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg |= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_ctrla_reg_t hri_ac_get_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg = data; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg &= ~mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg ^= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_ctrla_reg_t hri_ac_read_CTRLA_reg(const void *const hw) +{ + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + return ((Ac *)hw)->CTRLA.reg; +} + +static inline void hri_ac_set_EVCTRL_COMPEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEO0) >> AC_EVCTRL_COMPEO0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEO0; + tmp |= value << AC_EVCTRL_COMPEO0_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_COMPEO1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEO1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEO1) >> AC_EVCTRL_COMPEO1_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEO1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEO1; + tmp |= value << AC_EVCTRL_COMPEO1_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEO1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEO1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_WINEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_WINEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_WINEO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_WINEO0) >> AC_EVCTRL_WINEO0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_WINEO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_WINEO0; + tmp |= value << AC_EVCTRL_WINEO0_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_WINEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_WINEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_WINEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_WINEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_COMPEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEI0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEI0) >> AC_EVCTRL_COMPEI0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEI0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEI0; + tmp |= value << AC_EVCTRL_COMPEI0_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_COMPEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEI1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEI1) >> AC_EVCTRL_COMPEI1_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEI1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEI1; + tmp |= value << AC_EVCTRL_COMPEI1_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_INVEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_INVEI0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_INVEI0) >> AC_EVCTRL_INVEI0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_INVEI0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_INVEI0; + tmp |= value << AC_EVCTRL_INVEI0_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_INVEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_INVEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_INVEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_INVEI1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_INVEI1) >> AC_EVCTRL_INVEI1_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_INVEI1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_INVEI1; + tmp |= value << AC_EVCTRL_INVEI1_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_INVEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_INVEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_evctrl_reg_t hri_ac_get_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_evctrl_reg_t hri_ac_read_EVCTRL_reg(const void *const hw) +{ + return ((Ac *)hw)->EVCTRL.reg; +} + +static inline void hri_ac_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg |= AC_DBGCTRL_DBGRUN; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->DBGCTRL.reg; + tmp = (tmp & AC_DBGCTRL_DBGRUN) >> AC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->DBGCTRL.reg; + tmp &= ~AC_DBGCTRL_DBGRUN; + tmp |= value << AC_DBGCTRL_DBGRUN_Pos; + ((Ac *)hw)->DBGCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg &= ~AC_DBGCTRL_DBGRUN; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg ^= AC_DBGCTRL_DBGRUN; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg |= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_dbgctrl_reg_t hri_ac_get_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg &= ~mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg ^= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_dbgctrl_reg_t hri_ac_read_DBGCTRL_reg(const void *const hw) +{ + return ((Ac *)hw)->DBGCTRL.reg; +} + +static inline void hri_ac_set_WINCTRL_WEN0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WEN0; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_WINCTRL_WEN0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp = (tmp & AC_WINCTRL_WEN0) >> AC_WINCTRL_WEN0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_WINCTRL_WEN0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp &= ~AC_WINCTRL_WEN0; + tmp |= value << AC_WINCTRL_WEN0_Pos; + ((Ac *)hw)->WINCTRL.reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_WINCTRL_WEN0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WEN0; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_WINCTRL_WEN0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WEN0; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WINTSEL0(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp = (tmp & AC_WINCTRL_WINTSEL0(mask)) >> AC_WINCTRL_WINTSEL0_Pos; + return tmp; +} + +static inline void hri_ac_write_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t data) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp &= ~AC_WINCTRL_WINTSEL0_Msk; + tmp |= AC_WINCTRL_WINTSEL0(data); + ((Ac *)hw)->WINCTRL.reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WINTSEL0(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WINTSEL0(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_WINTSEL0_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp = (tmp & AC_WINCTRL_WINTSEL0_Msk) >> AC_WINCTRL_WINTSEL0_Pos; + return tmp; +} + +static inline void hri_ac_set_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg |= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg = data; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg &= ~mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg ^= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_reg(const void *const hw) +{ + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + return ((Ac *)hw)->WINCTRL.reg; +} + +static inline void hri_ac_set_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg |= AC_SCALER_VALUE(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_VALUE_bf(const void *const hw, uint8_t index, + hri_ac_scaler_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp = (tmp & AC_SCALER_VALUE(mask)) >> AC_SCALER_VALUE_Pos; + return tmp; +} + +static inline void hri_ac_write_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp &= ~AC_SCALER_VALUE_Msk; + tmp |= AC_SCALER_VALUE(data); + ((Ac *)hw)->SCALER[index].reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg &= ~AC_SCALER_VALUE(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg ^= AC_SCALER_VALUE(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_VALUE_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp = (tmp & AC_SCALER_VALUE_Msk) >> AC_SCALER_VALUE_Pos; + return tmp; +} + +static inline void hri_ac_set_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg |= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg &= ~mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg ^= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_reg(const void *const hw, uint8_t index) +{ + return ((Ac *)hw)->SCALER[index].reg; +} + +static inline void hri_ac_set_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_ENABLE) >> AC_COMPCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_ENABLE; + tmp |= value << AC_COMPCTRL_ENABLE_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SINGLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SINGLE) >> AC_COMPCTRL_SINGLE_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_SINGLE; + tmp |= value << AC_COMPCTRL_SINGLE_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SINGLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SINGLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_RUNSTDBY; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_RUNSTDBY) >> AC_COMPCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_RUNSTDBY; + tmp |= value << AC_COMPCTRL_RUNSTDBY_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_RUNSTDBY; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_RUNSTDBY; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SWAP; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SWAP) >> AC_COMPCTRL_SWAP_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_SWAP; + tmp |= value << AC_COMPCTRL_SWAP_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SWAP; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SWAP; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_HYSTEN; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_HYSTEN) >> AC_COMPCTRL_HYSTEN_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_HYSTEN; + tmp |= value << AC_COMPCTRL_HYSTEN_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_HYSTEN; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_HYSTEN; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_INTSEL(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_INTSEL(mask)) >> AC_COMPCTRL_INTSEL_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_INTSEL_Msk; + tmp |= AC_COMPCTRL_INTSEL(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_INTSEL(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_INTSEL(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_INTSEL_Msk) >> AC_COMPCTRL_INTSEL_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXNEG(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXNEG(mask)) >> AC_COMPCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_MUXNEG_Msk; + tmp |= AC_COMPCTRL_MUXNEG(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXNEG(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXNEG(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXNEG_Msk) >> AC_COMPCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXPOS(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXPOS(mask)) >> AC_COMPCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_MUXPOS_Msk; + tmp |= AC_COMPCTRL_MUXPOS(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXPOS(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXPOS(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXPOS_Msk) >> AC_COMPCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SPEED(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SPEED(mask)) >> AC_COMPCTRL_SPEED_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_SPEED_Msk; + tmp |= AC_COMPCTRL_SPEED(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SPEED(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SPEED(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SPEED_Msk) >> AC_COMPCTRL_SPEED_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_HYST(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_HYST(mask)) >> AC_COMPCTRL_HYST_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_HYST_Msk; + tmp |= AC_COMPCTRL_HYST(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_HYST(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_HYST(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_HYST_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_HYST_Msk) >> AC_COMPCTRL_HYST_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_FLEN(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_FLEN(mask)) >> AC_COMPCTRL_FLEN_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_FLEN_Msk; + tmp |= AC_COMPCTRL_FLEN(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_FLEN(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_FLEN(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_FLEN_Msk) >> AC_COMPCTRL_FLEN_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_OUT(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_OUT(mask)) >> AC_COMPCTRL_OUT_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_OUT_Msk; + tmp |= AC_COMPCTRL_OUT(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_OUT(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_OUT(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_OUT_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_OUT_Msk) >> AC_COMPCTRL_OUT_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_reg(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg = data; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_reg(const void *const hw, uint8_t index) +{ + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + return ((Ac *)hw)->COMPCTRL[index].reg; +} + +static inline void hri_ac_write_CTRLB_reg(const void *const hw, hri_ac_ctrlb_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLB.reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_AC_L21_H_INCLUDED */ +#endif /* _SAML21_AC_COMPONENT_ */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_adc_l21.h b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_adc_l21.h new file mode 100644 index 00000000..296e2cec --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_adc_l21.h @@ -0,0 +1,2707 @@ +/** + * \file + * + * \brief SAM ADC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_ADC_COMPONENT_ +#ifndef _HRI_ADC_L21_H_INCLUDED_ +#define _HRI_ADC_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_ADC_CRITICAL_SECTIONS) +#define ADC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define ADC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define ADC_CRITICAL_SECTION_ENTER() +#define ADC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_adc_calib_reg_t; +typedef uint16_t hri_adc_ctrlc_reg_t; +typedef uint16_t hri_adc_gaincorr_reg_t; +typedef uint16_t hri_adc_inputctrl_reg_t; +typedef uint16_t hri_adc_offsetcorr_reg_t; +typedef uint16_t hri_adc_result_reg_t; +typedef uint16_t hri_adc_syncbusy_reg_t; +typedef uint16_t hri_adc_winlt_reg_t; +typedef uint16_t hri_adc_winut_reg_t; +typedef uint32_t hri_adc_seqctrl_reg_t; +typedef uint8_t hri_adc_avgctrl_reg_t; +typedef uint8_t hri_adc_ctrla_reg_t; +typedef uint8_t hri_adc_ctrlb_reg_t; +typedef uint8_t hri_adc_dbgctrl_reg_t; +typedef uint8_t hri_adc_evctrl_reg_t; +typedef uint8_t hri_adc_intenset_reg_t; +typedef uint8_t hri_adc_intflag_reg_t; +typedef uint8_t hri_adc_refctrl_reg_t; +typedef uint8_t hri_adc_sampctrl_reg_t; +typedef uint8_t hri_adc_seqstatus_reg_t; +typedef uint8_t hri_adc_swtrig_reg_t; + +static inline void hri_adc_wait_for_sync(const void *const hw, hri_adc_syncbusy_reg_t reg) +{ + while (((Adc *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_adc_is_syncing(const void *const hw, hri_adc_syncbusy_reg_t reg) +{ + return ((Adc *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_adc_get_INTFLAG_RESRDY_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos; +} + +static inline void hri_adc_clear_INTFLAG_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY; +} + +static inline bool hri_adc_get_INTFLAG_OVERRUN_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos; +} + +static inline void hri_adc_clear_INTFLAG_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN; +} + +static inline bool hri_adc_get_INTFLAG_WINMON_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos; +} + +static inline void hri_adc_clear_INTFLAG_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON; +} + +static inline bool hri_adc_get_interrupt_RESRDY_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos; +} + +static inline void hri_adc_clear_interrupt_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY; +} + +static inline bool hri_adc_get_interrupt_OVERRUN_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos; +} + +static inline void hri_adc_clear_interrupt_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN; +} + +static inline bool hri_adc_get_interrupt_WINMON_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos; +} + +static inline void hri_adc_clear_interrupt_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON; +} + +static inline hri_adc_intflag_reg_t hri_adc_get_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_intflag_reg_t hri_adc_read_INTFLAG_reg(const void *const hw) +{ + return ((Adc *)hw)->INTFLAG.reg; +} + +static inline void hri_adc_clear_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask) +{ + ((Adc *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_adc_set_INTEN_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY; +} + +static inline bool hri_adc_get_INTEN_RESRDY_bit(const void *const hw) +{ + return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_RESRDY) >> ADC_INTENSET_RESRDY_Pos; +} + +static inline void hri_adc_write_INTEN_RESRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY; + } else { + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY; + } +} + +static inline void hri_adc_clear_INTEN_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY; +} + +static inline void hri_adc_set_INTEN_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN; +} + +static inline bool hri_adc_get_INTEN_OVERRUN_bit(const void *const hw) +{ + return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_OVERRUN) >> ADC_INTENSET_OVERRUN_Pos; +} + +static inline void hri_adc_write_INTEN_OVERRUN_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN; + } else { + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN; + } +} + +static inline void hri_adc_clear_INTEN_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN; +} + +static inline void hri_adc_set_INTEN_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON; +} + +static inline bool hri_adc_get_INTEN_WINMON_bit(const void *const hw) +{ + return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_WINMON) >> ADC_INTENSET_WINMON_Pos; +} + +static inline void hri_adc_write_INTEN_WINMON_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON; + } else { + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON; + } +} + +static inline void hri_adc_clear_INTEN_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON; +} + +static inline void hri_adc_set_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) +{ + ((Adc *)hw)->INTENSET.reg = mask; +} + +static inline hri_adc_intenset_reg_t hri_adc_get_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_intenset_reg_t hri_adc_read_INTEN_reg(const void *const hw) +{ + return ((Adc *)hw)->INTENSET.reg; +} + +static inline void hri_adc_write_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t data) +{ + ((Adc *)hw)->INTENSET.reg = data; + ((Adc *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_adc_clear_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) +{ + ((Adc *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_adc_get_SEQSTATUS_SEQBUSY_bit(const void *const hw) +{ + return (((Adc *)hw)->SEQSTATUS.reg & ADC_SEQSTATUS_SEQBUSY) >> ADC_SEQSTATUS_SEQBUSY_Pos; +} + +static inline hri_adc_seqstatus_reg_t hri_adc_get_SEQSTATUS_SEQSTATE_bf(const void *const hw, + hri_adc_seqstatus_reg_t mask) +{ + return (((Adc *)hw)->SEQSTATUS.reg & ADC_SEQSTATUS_SEQSTATE(mask)) >> ADC_SEQSTATUS_SEQSTATE_Pos; +} + +static inline hri_adc_seqstatus_reg_t hri_adc_read_SEQSTATUS_SEQSTATE_bf(const void *const hw) +{ + return (((Adc *)hw)->SEQSTATUS.reg & ADC_SEQSTATUS_SEQSTATE_Msk) >> ADC_SEQSTATUS_SEQSTATE_Pos; +} + +static inline hri_adc_seqstatus_reg_t hri_adc_get_SEQSTATUS_reg(const void *const hw, hri_adc_seqstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SEQSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_seqstatus_reg_t hri_adc_read_SEQSTATUS_reg(const void *const hw) +{ + return ((Adc *)hw)->SEQSTATUS.reg; +} + +static inline bool hri_adc_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SWRST) >> ADC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_ENABLE) >> ADC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_INPUTCTRL_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_INPUTCTRL) >> ADC_SYNCBUSY_INPUTCTRL_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_CTRLC_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_CTRLC) >> ADC_SYNCBUSY_CTRLC_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_AVGCTRL_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_AVGCTRL) >> ADC_SYNCBUSY_AVGCTRL_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_SAMPCTRL_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SAMPCTRL) >> ADC_SYNCBUSY_SAMPCTRL_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_WINLT_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_WINLT) >> ADC_SYNCBUSY_WINLT_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_WINUT_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_WINUT) >> ADC_SYNCBUSY_WINUT_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_GAINCORR_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_GAINCORR) >> ADC_SYNCBUSY_GAINCORR_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_OFFSETCORR_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_OFFSETCORR) >> ADC_SYNCBUSY_OFFSETCORR_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_SWTRIG_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SWTRIG) >> ADC_SYNCBUSY_SWTRIG_Pos; +} + +static inline hri_adc_syncbusy_reg_t hri_adc_get_SYNCBUSY_reg(const void *const hw, hri_adc_syncbusy_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_syncbusy_reg_t hri_adc_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Adc *)hw)->SYNCBUSY.reg; +} + +static inline hri_adc_result_reg_t hri_adc_get_RESULT_RESULT_bf(const void *const hw, hri_adc_result_reg_t mask) +{ + return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT(mask)) >> ADC_RESULT_RESULT_Pos; +} + +static inline hri_adc_result_reg_t hri_adc_read_RESULT_RESULT_bf(const void *const hw) +{ + return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT_Msk) >> ADC_RESULT_RESULT_Pos; +} + +static inline hri_adc_result_reg_t hri_adc_get_RESULT_reg(const void *const hw, hri_adc_result_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->RESULT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_result_reg_t hri_adc_read_RESULT_reg(const void *const hw) +{ + return ((Adc *)hw)->RESULT.reg; +} + +static inline void hri_adc_set_CTRLA_SWRST_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_SWRST; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_SWRST) >> ADC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_adc_set_CTRLA_ENABLE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ENABLE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_ENABLE) >> ADC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_ENABLE; + tmp |= value << ADC_CTRLA_ENABLE_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ENABLE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ENABLE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_RUNSTDBY; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_RUNSTDBY) >> ADC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_RUNSTDBY; + tmp |= value << ADC_CTRLA_RUNSTDBY_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_RUNSTDBY; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_RUNSTDBY; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_ONDEMAND_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ONDEMAND; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_ONDEMAND_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_ONDEMAND) >> ADC_CTRLA_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_ONDEMAND_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_ONDEMAND; + tmp |= value << ADC_CTRLA_ONDEMAND_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_ONDEMAND_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ONDEMAND; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_ONDEMAND_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ONDEMAND; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + return ((Adc *)hw)->CTRLA.reg; +} + +static inline void hri_adc_set_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_PRESCALER(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_PRESCALER(mask)) >> ADC_CTRLB_PRESCALER_Pos; + return tmp; +} + +static inline void hri_adc_write_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= ~ADC_CTRLB_PRESCALER_Msk; + tmp |= ADC_CTRLB_PRESCALER(data); + ((Adc *)hw)->CTRLB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_PRESCALER(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_PRESCALER(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_PRESCALER_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_PRESCALER_Msk) >> ADC_CTRLB_PRESCALER_Pos; + return tmp; +} + +static inline void hri_adc_set_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_reg(const void *const hw) +{ + return ((Adc *)hw)->CTRLB.reg; +} + +static inline void hri_adc_set_REFCTRL_REFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFCOMP; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_REFCTRL_REFCOMP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp = (tmp & ADC_REFCTRL_REFCOMP) >> ADC_REFCTRL_REFCOMP_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_REFCTRL_REFCOMP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp &= ~ADC_REFCTRL_REFCOMP; + tmp |= value << ADC_REFCTRL_REFCOMP_Pos; + ((Adc *)hw)->REFCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_REFCTRL_REFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFCOMP; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_REFCTRL_REFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFCOMP; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFSEL(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp = (tmp & ADC_REFCTRL_REFSEL(mask)) >> ADC_REFCTRL_REFSEL_Pos; + return tmp; +} + +static inline void hri_adc_write_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp &= ~ADC_REFCTRL_REFSEL_Msk; + tmp |= ADC_REFCTRL_REFSEL(data); + ((Adc *)hw)->REFCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFSEL(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFSEL(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_REFSEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp = (tmp & ADC_REFCTRL_REFSEL_Msk) >> ADC_REFCTRL_REFSEL_Pos; + return tmp; +} + +static inline void hri_adc_set_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_reg(const void *const hw) +{ + return ((Adc *)hw)->REFCTRL.reg; +} + +static inline void hri_adc_set_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_FLUSHEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_FLUSHEI) >> ADC_EVCTRL_FLUSHEI_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_FLUSHEI_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_FLUSHEI; + tmp |= value << ADC_EVCTRL_FLUSHEI_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_FLUSHEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_FLUSHEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_STARTEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_STARTEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_STARTEI_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_STARTEI) >> ADC_EVCTRL_STARTEI_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_STARTEI_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_STARTEI; + tmp |= value << ADC_EVCTRL_STARTEI_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_STARTEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_STARTEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_STARTEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_STARTEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_FLUSHINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_FLUSHINV) >> ADC_EVCTRL_FLUSHINV_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_FLUSHINV_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_FLUSHINV; + tmp |= value << ADC_EVCTRL_FLUSHINV_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_FLUSHINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_FLUSHINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_STARTINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_STARTINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_STARTINV_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_STARTINV) >> ADC_EVCTRL_STARTINV_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_STARTINV_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_STARTINV; + tmp |= value << ADC_EVCTRL_STARTINV_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_STARTINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_STARTINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_STARTINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_STARTINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_RESRDYEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_RESRDYEO) >> ADC_EVCTRL_RESRDYEO_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_RESRDYEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_RESRDYEO; + tmp |= value << ADC_EVCTRL_RESRDYEO_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_RESRDYEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_RESRDYEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_WINMONEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_WINMONEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_WINMONEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_WINMONEO) >> ADC_EVCTRL_WINMONEO_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_WINMONEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_WINMONEO; + tmp |= value << ADC_EVCTRL_WINMONEO_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_WINMONEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_WINMONEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_WINMONEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_WINMONEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_evctrl_reg_t hri_adc_get_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_evctrl_reg_t hri_adc_read_EVCTRL_reg(const void *const hw) +{ + return ((Adc *)hw)->EVCTRL.reg; +} + +static inline void hri_adc_set_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXPOS(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXPOS_bf(const void *const hw, + hri_adc_inputctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXPOS(mask)) >> ADC_INPUTCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_adc_write_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= ~ADC_INPUTCTRL_MUXPOS_Msk; + tmp |= ADC_INPUTCTRL_MUXPOS(data); + ((Adc *)hw)->INPUTCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXPOS(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXPOS(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXPOS_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXPOS_Msk) >> ADC_INPUTCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_adc_set_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXNEG(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXNEG_bf(const void *const hw, + hri_adc_inputctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXNEG(mask)) >> ADC_INPUTCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_adc_write_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= ~ADC_INPUTCTRL_MUXNEG_Msk; + tmp |= ADC_INPUTCTRL_MUXNEG(data); + ((Adc *)hw)->INPUTCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXNEG(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXNEG(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXNEG_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXNEG_Msk) >> ADC_INPUTCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_adc_set_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->INPUTCTRL.reg; +} + +static inline void hri_adc_set_CTRLC_DIFFMODE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_DIFFMODE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLC_DIFFMODE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_DIFFMODE) >> ADC_CTRLC_DIFFMODE_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLC_DIFFMODE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLC.reg; + tmp &= ~ADC_CTRLC_DIFFMODE; + tmp |= value << ADC_CTRLC_DIFFMODE_Pos; + ((Adc *)hw)->CTRLC.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLC_DIFFMODE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_DIFFMODE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLC_DIFFMODE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_DIFFMODE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLC_LEFTADJ_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_LEFTADJ; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLC_LEFTADJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_LEFTADJ) >> ADC_CTRLC_LEFTADJ_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLC_LEFTADJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLC.reg; + tmp &= ~ADC_CTRLC_LEFTADJ; + tmp |= value << ADC_CTRLC_LEFTADJ_Pos; + ((Adc *)hw)->CTRLC.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLC_LEFTADJ_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_LEFTADJ; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLC_LEFTADJ_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_LEFTADJ; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLC_FREERUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_FREERUN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLC_FREERUN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_FREERUN) >> ADC_CTRLC_FREERUN_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLC_FREERUN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLC.reg; + tmp &= ~ADC_CTRLC_FREERUN; + tmp |= value << ADC_CTRLC_FREERUN_Pos; + ((Adc *)hw)->CTRLC.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLC_FREERUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_FREERUN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLC_FREERUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_FREERUN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLC_CORREN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_CORREN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLC_CORREN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_CORREN) >> ADC_CTRLC_CORREN_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLC_CORREN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLC.reg; + tmp &= ~ADC_CTRLC_CORREN; + tmp |= value << ADC_CTRLC_CORREN_Pos; + ((Adc *)hw)->CTRLC.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLC_CORREN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_CORREN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLC_CORREN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_CORREN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLC_RESSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_RESSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlc_reg_t hri_adc_get_CTRLC_RESSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_RESSEL(mask)) >> ADC_CTRLC_RESSEL_Pos; + return tmp; +} + +static inline void hri_adc_write_CTRLC_RESSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLC.reg; + tmp &= ~ADC_CTRLC_RESSEL_Msk; + tmp |= ADC_CTRLC_RESSEL(data); + ((Adc *)hw)->CTRLC.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLC_RESSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_RESSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLC_RESSEL_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_RESSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlc_reg_t hri_adc_read_CTRLC_RESSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_RESSEL_Msk) >> ADC_CTRLC_RESSEL_Pos; + return tmp; +} + +static inline void hri_adc_set_CTRLC_WINMODE_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg |= ADC_CTRLC_WINMODE(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlc_reg_t hri_adc_get_CTRLC_WINMODE_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_WINMODE(mask)) >> ADC_CTRLC_WINMODE_Pos; + return tmp; +} + +static inline void hri_adc_write_CTRLC_WINMODE_bf(const void *const hw, hri_adc_ctrlc_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLC.reg; + tmp &= ~ADC_CTRLC_WINMODE_Msk; + tmp |= ADC_CTRLC_WINMODE(data); + ((Adc *)hw)->CTRLC.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLC_WINMODE_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg &= ~ADC_CTRLC_WINMODE(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLC_WINMODE_bf(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg ^= ADC_CTRLC_WINMODE(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlc_reg_t hri_adc_read_CTRLC_WINMODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLC.reg; + tmp = (tmp & ADC_CTRLC_WINMODE_Msk) >> ADC_CTRLC_WINMODE_Pos; + return tmp; +} + +static inline void hri_adc_set_CTRLC_reg(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlc_reg_t hri_adc_get_CTRLC_reg(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->CTRLC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_CTRLC_reg(const void *const hw, hri_adc_ctrlc_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLC_reg(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLC_reg(const void *const hw, hri_adc_ctrlc_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLC.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlc_reg_t hri_adc_read_CTRLC_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->CTRLC.reg; +} + +static inline void hri_adc_set_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_SAMPLENUM(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_SAMPLENUM(mask)) >> ADC_AVGCTRL_SAMPLENUM_Pos; + return tmp; +} + +static inline void hri_adc_write_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp &= ~ADC_AVGCTRL_SAMPLENUM_Msk; + tmp |= ADC_AVGCTRL_SAMPLENUM(data); + ((Adc *)hw)->AVGCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_SAMPLENUM(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_SAMPLENUM(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_SAMPLENUM_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_SAMPLENUM_Msk) >> ADC_AVGCTRL_SAMPLENUM_Pos; + return tmp; +} + +static inline void hri_adc_set_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_ADJRES(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_ADJRES(mask)) >> ADC_AVGCTRL_ADJRES_Pos; + return tmp; +} + +static inline void hri_adc_write_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp &= ~ADC_AVGCTRL_ADJRES_Msk; + tmp |= ADC_AVGCTRL_ADJRES(data); + ((Adc *)hw)->AVGCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_ADJRES(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_ADJRES(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_ADJRES_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_ADJRES_Msk) >> ADC_AVGCTRL_ADJRES_Pos; + return tmp; +} + +static inline void hri_adc_set_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->AVGCTRL.reg; +} + +static inline void hri_adc_set_SAMPCTRL_OFFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg |= ADC_SAMPCTRL_OFFCOMP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_SAMPCTRL_OFFCOMP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp = (tmp & ADC_SAMPCTRL_OFFCOMP) >> ADC_SAMPCTRL_OFFCOMP_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_SAMPCTRL_OFFCOMP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp &= ~ADC_SAMPCTRL_OFFCOMP; + tmp |= value << ADC_SAMPCTRL_OFFCOMP_Pos; + ((Adc *)hw)->SAMPCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SAMPCTRL_OFFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg &= ~ADC_SAMPCTRL_OFFCOMP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SAMPCTRL_OFFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg ^= ADC_SAMPCTRL_OFFCOMP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg |= ADC_SAMPCTRL_SAMPLEN(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp = (tmp & ADC_SAMPCTRL_SAMPLEN(mask)) >> ADC_SAMPCTRL_SAMPLEN_Pos; + return tmp; +} + +static inline void hri_adc_write_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp &= ~ADC_SAMPCTRL_SAMPLEN_Msk; + tmp |= ADC_SAMPCTRL_SAMPLEN(data); + ((Adc *)hw)->SAMPCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg &= ~ADC_SAMPCTRL_SAMPLEN(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg ^= ADC_SAMPCTRL_SAMPLEN(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_SAMPLEN_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp = (tmp & ADC_SAMPCTRL_SAMPLEN_Msk) >> ADC_SAMPCTRL_SAMPLEN_Pos; + return tmp; +} + +static inline void hri_adc_set_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->SAMPCTRL.reg; +} + +static inline void hri_adc_set_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg |= ADC_WINLT_WINLT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + tmp = ((Adc *)hw)->WINLT.reg; + tmp = (tmp & ADC_WINLT_WINLT(mask)) >> ADC_WINLT_WINLT_Pos; + return tmp; +} + +static inline void hri_adc_write_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->WINLT.reg; + tmp &= ~ADC_WINLT_WINLT_Msk; + tmp |= ADC_WINLT_WINLT(data); + ((Adc *)hw)->WINLT.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg &= ~ADC_WINLT_WINLT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg ^= ADC_WINLT_WINLT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_WINLT_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + tmp = ((Adc *)hw)->WINLT.reg; + tmp = (tmp & ADC_WINLT_WINLT_Msk) >> ADC_WINLT_WINLT_Pos; + return tmp; +} + +static inline void hri_adc_set_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + tmp = ((Adc *)hw)->WINLT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + return ((Adc *)hw)->WINLT.reg; +} + +static inline void hri_adc_set_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg |= ADC_WINUT_WINUT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_get_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + tmp = ((Adc *)hw)->WINUT.reg; + tmp = (tmp & ADC_WINUT_WINUT(mask)) >> ADC_WINUT_WINUT_Pos; + return tmp; +} + +static inline void hri_adc_write_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->WINUT.reg; + tmp &= ~ADC_WINUT_WINUT_Msk; + tmp |= ADC_WINUT_WINUT(data); + ((Adc *)hw)->WINUT.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg &= ~ADC_WINUT_WINUT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg ^= ADC_WINUT_WINUT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_read_WINUT_WINUT_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + tmp = ((Adc *)hw)->WINUT.reg; + tmp = (tmp & ADC_WINUT_WINUT_Msk) >> ADC_WINUT_WINUT_Pos; + return tmp; +} + +static inline void hri_adc_set_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_get_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + tmp = ((Adc *)hw)->WINUT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_WINUT_reg(const void *const hw, hri_adc_winut_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_read_WINUT_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + return ((Adc *)hw)->WINUT.reg; +} + +static inline void hri_adc_set_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg |= ADC_GAINCORR_GAINCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp = (tmp & ADC_GAINCORR_GAINCORR(mask)) >> ADC_GAINCORR_GAINCORR_Pos; + return tmp; +} + +static inline void hri_adc_write_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp &= ~ADC_GAINCORR_GAINCORR_Msk; + tmp |= ADC_GAINCORR_GAINCORR(data); + ((Adc *)hw)->GAINCORR.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg &= ~ADC_GAINCORR_GAINCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg ^= ADC_GAINCORR_GAINCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_GAINCORR_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp = (tmp & ADC_GAINCORR_GAINCORR_Msk) >> ADC_GAINCORR_GAINCORR_Pos; + return tmp; +} + +static inline void hri_adc_set_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + return ((Adc *)hw)->GAINCORR.reg; +} + +static inline void hri_adc_set_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg |= ADC_OFFSETCORR_OFFSETCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_OFFSETCORR_bf(const void *const hw, + hri_adc_offsetcorr_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR(mask)) >> ADC_OFFSETCORR_OFFSETCORR_Pos; + return tmp; +} + +static inline void hri_adc_write_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp &= ~ADC_OFFSETCORR_OFFSETCORR_Msk; + tmp |= ADC_OFFSETCORR_OFFSETCORR(data); + ((Adc *)hw)->OFFSETCORR.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg &= ~ADC_OFFSETCORR_OFFSETCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg ^= ADC_OFFSETCORR_OFFSETCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_OFFSETCORR_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR_Msk) >> ADC_OFFSETCORR_OFFSETCORR_Pos; + return tmp; +} + +static inline void hri_adc_set_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + return ((Adc *)hw)->OFFSETCORR.reg; +} + +static inline void hri_adc_set_SWTRIG_FLUSH_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_FLUSH; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_SWTRIG_FLUSH_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp = (tmp & ADC_SWTRIG_FLUSH) >> ADC_SWTRIG_FLUSH_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_SWTRIG_FLUSH_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp &= ~ADC_SWTRIG_FLUSH; + tmp |= value << ADC_SWTRIG_FLUSH_Pos; + ((Adc *)hw)->SWTRIG.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SWTRIG_FLUSH_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_FLUSH; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SWTRIG_FLUSH_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_FLUSH; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_SWTRIG_START_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_START; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_SWTRIG_START_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp = (tmp & ADC_SWTRIG_START) >> ADC_SWTRIG_START_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_SWTRIG_START_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp &= ~ADC_SWTRIG_START; + tmp |= value << ADC_SWTRIG_START_Pos; + ((Adc *)hw)->SWTRIG.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SWTRIG_START_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_START; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SWTRIG_START_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_START; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_swtrig_reg_t hri_adc_get_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_swtrig_reg_t hri_adc_read_SWTRIG_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->SWTRIG.reg; +} + +static inline void hri_adc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg |= ADC_DBGCTRL_DBGRUN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->DBGCTRL.reg; + tmp = (tmp & ADC_DBGCTRL_DBGRUN) >> ADC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DBGCTRL.reg; + tmp &= ~ADC_DBGCTRL_DBGRUN; + tmp |= value << ADC_DBGCTRL_DBGRUN_Pos; + ((Adc *)hw)->DBGCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg &= ~ADC_DBGCTRL_DBGRUN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg ^= ADC_DBGCTRL_DBGRUN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_dbgctrl_reg_t hri_adc_get_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_dbgctrl_reg_t hri_adc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Adc *)hw)->DBGCTRL.reg; +} + +static inline void hri_adc_set_SEQCTRL_SEQEN_bf(const void *const hw, hri_adc_seqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SEQCTRL.reg |= ADC_SEQCTRL_SEQEN(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_seqctrl_reg_t hri_adc_get_SEQCTRL_SEQEN_bf(const void *const hw, hri_adc_seqctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Adc *)hw)->SEQCTRL.reg; + tmp = (tmp & ADC_SEQCTRL_SEQEN(mask)) >> ADC_SEQCTRL_SEQEN_Pos; + return tmp; +} + +static inline void hri_adc_write_SEQCTRL_SEQEN_bf(const void *const hw, hri_adc_seqctrl_reg_t data) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->SEQCTRL.reg; + tmp &= ~ADC_SEQCTRL_SEQEN_Msk; + tmp |= ADC_SEQCTRL_SEQEN(data); + ((Adc *)hw)->SEQCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SEQCTRL_SEQEN_bf(const void *const hw, hri_adc_seqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SEQCTRL.reg &= ~ADC_SEQCTRL_SEQEN(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SEQCTRL_SEQEN_bf(const void *const hw, hri_adc_seqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SEQCTRL.reg ^= ADC_SEQCTRL_SEQEN(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_seqctrl_reg_t hri_adc_read_SEQCTRL_SEQEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Adc *)hw)->SEQCTRL.reg; + tmp = (tmp & ADC_SEQCTRL_SEQEN_Msk) >> ADC_SEQCTRL_SEQEN_Pos; + return tmp; +} + +static inline void hri_adc_set_SEQCTRL_reg(const void *const hw, hri_adc_seqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SEQCTRL.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_seqctrl_reg_t hri_adc_get_SEQCTRL_reg(const void *const hw, hri_adc_seqctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Adc *)hw)->SEQCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_SEQCTRL_reg(const void *const hw, hri_adc_seqctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SEQCTRL.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SEQCTRL_reg(const void *const hw, hri_adc_seqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SEQCTRL.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SEQCTRL_reg(const void *const hw, hri_adc_seqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SEQCTRL.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_seqctrl_reg_t hri_adc_read_SEQCTRL_reg(const void *const hw) +{ + return ((Adc *)hw)->SEQCTRL.reg; +} + +static inline void hri_adc_set_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASCOMP(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASCOMP(mask)) >> ADC_CALIB_BIASCOMP_Pos; + return tmp; +} + +static inline void hri_adc_write_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CALIB.reg; + tmp &= ~ADC_CALIB_BIASCOMP_Msk; + tmp |= ADC_CALIB_BIASCOMP(data); + ((Adc *)hw)->CALIB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASCOMP(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASCOMP(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASCOMP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASCOMP_Msk) >> ADC_CALIB_BIASCOMP_Pos; + return tmp; +} + +static inline void hri_adc_set_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASREFBUF(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASREFBUF(mask)) >> ADC_CALIB_BIASREFBUF_Pos; + return tmp; +} + +static inline void hri_adc_write_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CALIB.reg; + tmp &= ~ADC_CALIB_BIASREFBUF_Msk; + tmp |= ADC_CALIB_BIASREFBUF(data); + ((Adc *)hw)->CALIB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASREFBUF(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASREFBUF(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASREFBUF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASREFBUF_Msk) >> ADC_CALIB_BIASREFBUF_Pos; + return tmp; +} + +static inline void hri_adc_set_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_get_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_CALIB_reg(const void *const hw, hri_adc_calib_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_read_CALIB_reg(const void *const hw) +{ + return ((Adc *)hw)->CALIB.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_ADC_L21_H_INCLUDED */ +#endif /* _SAML21_ADC_COMPONENT_ */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_aes_l21.h b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_aes_l21.h new file mode 100644 index 00000000..abb9e333 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_aes_l21.h @@ -0,0 +1,1213 @@ +/** + * \file + * + * \brief SAM AES + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_AES_COMPONENT_ +#ifndef _HRI_AES_L21_H_INCLUDED_ +#define _HRI_AES_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_AES_CRITICAL_SECTIONS) +#define AES_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define AES_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define AES_CRITICAL_SECTION_ENTER() +#define AES_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_aes_ciplen_reg_t; +typedef uint32_t hri_aes_ctrla_reg_t; +typedef uint32_t hri_aes_ghash_reg_t; +typedef uint32_t hri_aes_hashkey_reg_t; +typedef uint32_t hri_aes_indata_reg_t; +typedef uint32_t hri_aes_intvectv_reg_t; +typedef uint32_t hri_aes_keyword_reg_t; +typedef uint32_t hri_aes_randseed_reg_t; +typedef uint8_t hri_aes_ctrlb_reg_t; +typedef uint8_t hri_aes_databufptr_reg_t; +typedef uint8_t hri_aes_dbgctrl_reg_t; +typedef uint8_t hri_aes_intenset_reg_t; +typedef uint8_t hri_aes_intflag_reg_t; + +static inline bool hri_aes_get_INTFLAG_ENCCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_ENCCMP) >> AES_INTFLAG_ENCCMP_Pos; +} + +static inline void hri_aes_clear_INTFLAG_ENCCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_ENCCMP; +} + +static inline bool hri_aes_get_INTFLAG_GFMCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_GFMCMP) >> AES_INTFLAG_GFMCMP_Pos; +} + +static inline void hri_aes_clear_INTFLAG_GFMCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_GFMCMP; +} + +static inline bool hri_aes_get_interrupt_ENCCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_ENCCMP) >> AES_INTFLAG_ENCCMP_Pos; +} + +static inline void hri_aes_clear_interrupt_ENCCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_ENCCMP; +} + +static inline bool hri_aes_get_interrupt_GFMCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_GFMCMP) >> AES_INTFLAG_GFMCMP_Pos; +} + +static inline void hri_aes_clear_interrupt_GFMCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_GFMCMP; +} + +static inline hri_aes_intflag_reg_t hri_aes_get_INTFLAG_reg(const void *const hw, hri_aes_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_aes_intflag_reg_t hri_aes_read_INTFLAG_reg(const void *const hw) +{ + return ((Aes *)hw)->INTFLAG.reg; +} + +static inline void hri_aes_clear_INTFLAG_reg(const void *const hw, hri_aes_intflag_reg_t mask) +{ + ((Aes *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_aes_set_INTEN_ENCCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTENSET.reg = AES_INTENSET_ENCCMP; +} + +static inline bool hri_aes_get_INTEN_ENCCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTENSET.reg & AES_INTENSET_ENCCMP) >> AES_INTENSET_ENCCMP_Pos; +} + +static inline void hri_aes_write_INTEN_ENCCMP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_ENCCMP; + } else { + ((Aes *)hw)->INTENSET.reg = AES_INTENSET_ENCCMP; + } +} + +static inline void hri_aes_clear_INTEN_ENCCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_ENCCMP; +} + +static inline void hri_aes_set_INTEN_GFMCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTENSET.reg = AES_INTENSET_GFMCMP; +} + +static inline bool hri_aes_get_INTEN_GFMCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTENSET.reg & AES_INTENSET_GFMCMP) >> AES_INTENSET_GFMCMP_Pos; +} + +static inline void hri_aes_write_INTEN_GFMCMP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_GFMCMP; + } else { + ((Aes *)hw)->INTENSET.reg = AES_INTENSET_GFMCMP; + } +} + +static inline void hri_aes_clear_INTEN_GFMCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_GFMCMP; +} + +static inline void hri_aes_set_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask) +{ + ((Aes *)hw)->INTENSET.reg = mask; +} + +static inline hri_aes_intenset_reg_t hri_aes_get_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_aes_intenset_reg_t hri_aes_read_INTEN_reg(const void *const hw) +{ + return ((Aes *)hw)->INTENSET.reg; +} + +static inline void hri_aes_write_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t data) +{ + ((Aes *)hw)->INTENSET.reg = data; + ((Aes *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_aes_clear_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask) +{ + ((Aes *)hw)->INTENCLR.reg = mask; +} + +static inline void hri_aes_set_CTRLA_SWRST_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_SWRST; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_SWRST) >> AES_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_aes_set_CTRLA_ENABLE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_ENABLE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_ENABLE) >> AES_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_ENABLE; + tmp |= value << AES_CTRLA_ENABLE_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_ENABLE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_ENABLE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_CIPHER_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CIPHER; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_CIPHER_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_CIPHER) >> AES_CTRLA_CIPHER_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_CIPHER_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_CIPHER; + tmp |= value << AES_CTRLA_CIPHER_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_CIPHER_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CIPHER; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_CIPHER_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CIPHER; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_STARTMODE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_STARTMODE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_STARTMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_STARTMODE) >> AES_CTRLA_STARTMODE_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_STARTMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_STARTMODE; + tmp |= value << AES_CTRLA_STARTMODE_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_STARTMODE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_STARTMODE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_STARTMODE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_STARTMODE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_LOD_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_LOD; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_LOD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_LOD) >> AES_CTRLA_LOD_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_LOD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_LOD; + tmp |= value << AES_CTRLA_LOD_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_LOD_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_LOD; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_LOD_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_LOD; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_KEYGEN_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_KEYGEN; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_KEYGEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_KEYGEN) >> AES_CTRLA_KEYGEN_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_KEYGEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_KEYGEN; + tmp |= value << AES_CTRLA_KEYGEN_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_KEYGEN_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_KEYGEN; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_KEYGEN_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_KEYGEN; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_XORKEY_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_XORKEY; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_XORKEY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_XORKEY) >> AES_CTRLA_XORKEY_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_XORKEY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_XORKEY; + tmp |= value << AES_CTRLA_XORKEY_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_XORKEY_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_XORKEY; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_XORKEY_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_XORKEY; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_AESMODE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_AESMODE(mask)) >> AES_CTRLA_AESMODE_Pos; + return tmp; +} + +static inline void hri_aes_write_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t data) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_AESMODE_Msk; + tmp |= AES_CTRLA_AESMODE(data); + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_AESMODE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_AESMODE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_AESMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_AESMODE_Msk) >> AES_CTRLA_AESMODE_Pos; + return tmp; +} + +static inline void hri_aes_set_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CFBS(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_CFBS(mask)) >> AES_CTRLA_CFBS_Pos; + return tmp; +} + +static inline void hri_aes_write_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t data) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_CFBS_Msk; + tmp |= AES_CTRLA_CFBS(data); + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CFBS(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CFBS(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_CFBS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_CFBS_Msk) >> AES_CTRLA_CFBS_Pos; + return tmp; +} + +static inline void hri_aes_set_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_KEYSIZE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_KEYSIZE(mask)) >> AES_CTRLA_KEYSIZE_Pos; + return tmp; +} + +static inline void hri_aes_write_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t data) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_KEYSIZE_Msk; + tmp |= AES_CTRLA_KEYSIZE(data); + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_KEYSIZE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_KEYSIZE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_KEYSIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_KEYSIZE_Msk) >> AES_CTRLA_KEYSIZE_Pos; + return tmp; +} + +static inline void hri_aes_set_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CTYPE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_CTYPE(mask)) >> AES_CTRLA_CTYPE_Pos; + return tmp; +} + +static inline void hri_aes_write_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t data) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_CTYPE_Msk; + tmp |= AES_CTRLA_CTYPE(data); + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CTYPE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CTYPE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_CTYPE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_CTYPE_Msk) >> AES_CTRLA_CTYPE_Pos; + return tmp; +} + +static inline void hri_aes_set_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_reg(const void *const hw) +{ + return ((Aes *)hw)->CTRLA.reg; +} + +static inline void hri_aes_set_CTRLB_START_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_START; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLB_START_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->CTRLB.reg; + tmp = (tmp & AES_CTRLB_START) >> AES_CTRLB_START_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLB_START_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLB.reg; + tmp &= ~AES_CTRLB_START; + tmp |= value << AES_CTRLB_START_Pos; + ((Aes *)hw)->CTRLB.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLB_START_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_START; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLB_START_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_START; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLB_NEWMSG_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_NEWMSG; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLB_NEWMSG_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->CTRLB.reg; + tmp = (tmp & AES_CTRLB_NEWMSG) >> AES_CTRLB_NEWMSG_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLB_NEWMSG_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLB.reg; + tmp &= ~AES_CTRLB_NEWMSG; + tmp |= value << AES_CTRLB_NEWMSG_Pos; + ((Aes *)hw)->CTRLB.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLB_NEWMSG_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_NEWMSG; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLB_NEWMSG_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_NEWMSG; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLB_EOM_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_EOM; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLB_EOM_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->CTRLB.reg; + tmp = (tmp & AES_CTRLB_EOM) >> AES_CTRLB_EOM_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLB_EOM_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLB.reg; + tmp &= ~AES_CTRLB_EOM; + tmp |= value << AES_CTRLB_EOM_Pos; + ((Aes *)hw)->CTRLB.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLB_EOM_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_EOM; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLB_EOM_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_EOM; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLB_GFMUL_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_GFMUL; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLB_GFMUL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->CTRLB.reg; + tmp = (tmp & AES_CTRLB_GFMUL) >> AES_CTRLB_GFMUL_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLB_GFMUL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLB.reg; + tmp &= ~AES_CTRLB_GFMUL; + tmp |= value << AES_CTRLB_GFMUL_Pos; + ((Aes *)hw)->CTRLB.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLB_GFMUL_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_GFMUL; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLB_GFMUL_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_GFMUL; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrlb_reg_t hri_aes_get_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrlb_reg_t hri_aes_read_CTRLB_reg(const void *const hw) +{ + return ((Aes *)hw)->CTRLB.reg; +} + +static inline void hri_aes_set_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg |= AES_DATABUFPTR_INDATAPTR(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_databufptr_reg_t hri_aes_get_DATABUFPTR_INDATAPTR_bf(const void *const hw, + hri_aes_databufptr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->DATABUFPTR.reg; + tmp = (tmp & AES_DATABUFPTR_INDATAPTR(mask)) >> AES_DATABUFPTR_INDATAPTR_Pos; + return tmp; +} + +static inline void hri_aes_write_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t data) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->DATABUFPTR.reg; + tmp &= ~AES_DATABUFPTR_INDATAPTR_Msk; + tmp |= AES_DATABUFPTR_INDATAPTR(data); + ((Aes *)hw)->DATABUFPTR.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg &= ~AES_DATABUFPTR_INDATAPTR(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg ^= AES_DATABUFPTR_INDATAPTR(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_databufptr_reg_t hri_aes_read_DATABUFPTR_INDATAPTR_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->DATABUFPTR.reg; + tmp = (tmp & AES_DATABUFPTR_INDATAPTR_Msk) >> AES_DATABUFPTR_INDATAPTR_Pos; + return tmp; +} + +static inline void hri_aes_set_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_databufptr_reg_t hri_aes_get_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->DATABUFPTR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_databufptr_reg_t hri_aes_read_DATABUFPTR_reg(const void *const hw) +{ + return ((Aes *)hw)->DATABUFPTR.reg; +} + +static inline void hri_aes_set_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->INDATA.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_indata_reg_t hri_aes_get_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->INDATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_INDATA_reg(const void *const hw, hri_aes_indata_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->INDATA.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->INDATA.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->INDATA.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_indata_reg_t hri_aes_read_INDATA_reg(const void *const hw) +{ + return ((Aes *)hw)->INDATA.reg; +} + +static inline void hri_aes_set_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->HASHKEY[index].reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_hashkey_reg_t hri_aes_get_HASHKEY_reg(const void *const hw, uint8_t index, + hri_aes_hashkey_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->HASHKEY[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->HASHKEY[index].reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->HASHKEY[index].reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->HASHKEY[index].reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_hashkey_reg_t hri_aes_read_HASHKEY_reg(const void *const hw, uint8_t index) +{ + return ((Aes *)hw)->HASHKEY[index].reg; +} + +static inline void hri_aes_set_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->GHASH[index].reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ghash_reg_t hri_aes_get_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->GHASH[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->GHASH[index].reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->GHASH[index].reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->GHASH[index].reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ghash_reg_t hri_aes_read_GHASH_reg(const void *const hw, uint8_t index) +{ + return ((Aes *)hw)->GHASH[index].reg; +} + +static inline void hri_aes_set_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CIPLEN.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ciplen_reg_t hri_aes_get_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CIPLEN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CIPLEN.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CIPLEN.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CIPLEN.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ciplen_reg_t hri_aes_read_CIPLEN_reg(const void *const hw) +{ + return ((Aes *)hw)->CIPLEN.reg; +} + +static inline void hri_aes_set_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->RANDSEED.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_randseed_reg_t hri_aes_get_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->RANDSEED.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->RANDSEED.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->RANDSEED.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->RANDSEED.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_randseed_reg_t hri_aes_read_RANDSEED_reg(const void *const hw) +{ + return ((Aes *)hw)->RANDSEED.reg; +} + +static inline void hri_aes_write_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DBGCTRL.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_write_KEYWORD_reg(const void *const hw, uint8_t index, hri_aes_keyword_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->KEYWORD[index].reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_write_INTVECTV_reg(const void *const hw, uint8_t index, hri_aes_intvectv_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->INTVECTV[index].reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_AES_L21_H_INCLUDED */ +#endif /* _SAML21_AES_COMPONENT_ */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_ccl_l21.h b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_ccl_l21.h new file mode 100644 index 00000000..e88acd39 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_ccl_l21.h @@ -0,0 +1,776 @@ +/** + * \file + * + * \brief SAM CCL + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_CCL_COMPONENT_ +#ifndef _HRI_CCL_L21_H_INCLUDED_ +#define _HRI_CCL_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_CCL_CRITICAL_SECTIONS) +#define CCL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define CCL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define CCL_CRITICAL_SECTION_ENTER() +#define CCL_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_ccl_lutctrl_reg_t; +typedef uint8_t hri_ccl_ctrl_reg_t; +typedef uint8_t hri_ccl_seqctrl_reg_t; + +static inline void hri_ccl_set_CTRL_SWRST_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_SWRST; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_CTRL_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->CTRL.reg; + tmp = (tmp & CCL_CTRL_SWRST) >> CCL_CTRL_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_set_CTRL_ENABLE_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_CTRL_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->CTRL.reg; + tmp = (tmp & CCL_CTRL_ENABLE) >> CCL_CTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_CTRL_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->CTRL.reg; + tmp &= ~CCL_CTRL_ENABLE; + tmp |= value << CCL_CTRL_ENABLE_Pos; + ((Ccl *)hw)->CTRL.reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_CTRL_ENABLE_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg &= ~CCL_CTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_CTRL_ENABLE_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg ^= CCL_CTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_CTRL_RUNSTDBY_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_RUNSTDBY; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_CTRL_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->CTRL.reg; + tmp = (tmp & CCL_CTRL_RUNSTDBY) >> CCL_CTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_CTRL_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->CTRL.reg; + tmp &= ~CCL_CTRL_RUNSTDBY; + tmp |= value << CCL_CTRL_RUNSTDBY_Pos; + ((Ccl *)hw)->CTRL.reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_CTRL_RUNSTDBY_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg &= ~CCL_CTRL_RUNSTDBY; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_CTRL_RUNSTDBY_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg ^= CCL_CTRL_RUNSTDBY; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg |= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_ctrl_reg_t hri_ccl_get_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ccl_write_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t data) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg = data; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg &= ~mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg ^= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_ctrl_reg_t hri_ccl_read_CTRL_reg(const void *const hw) +{ + return ((Ccl *)hw)->CTRL.reg; +} + +static inline void hri_ccl_set_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg |= CCL_SEQCTRL_SEQSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_seqctrl_reg_t hri_ccl_get_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, + hri_ccl_seqctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->SEQCTRL[index].reg; + tmp = (tmp & CCL_SEQCTRL_SEQSEL(mask)) >> CCL_SEQCTRL_SEQSEL_Pos; + return tmp; +} + +static inline void hri_ccl_write_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t data) +{ + uint8_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->SEQCTRL[index].reg; + tmp &= ~CCL_SEQCTRL_SEQSEL_Msk; + tmp |= CCL_SEQCTRL_SEQSEL(data); + ((Ccl *)hw)->SEQCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg &= ~CCL_SEQCTRL_SEQSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg ^= CCL_SEQCTRL_SEQSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_seqctrl_reg_t hri_ccl_read_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->SEQCTRL[index].reg; + tmp = (tmp & CCL_SEQCTRL_SEQSEL_Msk) >> CCL_SEQCTRL_SEQSEL_Pos; + return tmp; +} + +static inline void hri_ccl_set_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg |= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_seqctrl_reg_t hri_ccl_get_SEQCTRL_reg(const void *const hw, uint8_t index, + hri_ccl_seqctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->SEQCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ccl_write_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t data) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg = data; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg &= ~mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg ^= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_seqctrl_reg_t hri_ccl_read_SEQCTRL_reg(const void *const hw, uint8_t index) +{ + return ((Ccl *)hw)->SEQCTRL[index].reg; +} + +static inline void hri_ccl_set_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_ENABLE) >> CCL_LUTCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_ENABLE; + tmp |= value << CCL_LUTCTRL_ENABLE_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_EDGESEL; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_EDGESEL) >> CCL_LUTCTRL_EDGESEL_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_EDGESEL; + tmp |= value << CCL_LUTCTRL_EDGESEL_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_EDGESEL; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_EDGESEL; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INVEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INVEI) >> CCL_LUTCTRL_INVEI_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_INVEI; + tmp |= value << CCL_LUTCTRL_INVEI_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INVEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INVEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_LUTEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_LUTEI) >> CCL_LUTCTRL_LUTEI_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_LUTEI; + tmp |= value << CCL_LUTCTRL_LUTEI_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_LUTEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_LUTEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_LUTEO; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_LUTEO) >> CCL_LUTCTRL_LUTEO_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_LUTEO; + tmp |= value << CCL_LUTCTRL_LUTEO_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_LUTEO; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_LUTEO; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_FILTSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_FILTSEL(mask)) >> CCL_LUTCTRL_FILTSEL_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_FILTSEL_Msk; + tmp |= CCL_LUTCTRL_FILTSEL(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_FILTSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_FILTSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_FILTSEL_Msk) >> CCL_LUTCTRL_FILTSEL_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL0(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL0(mask)) >> CCL_LUTCTRL_INSEL0_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_INSEL0_Msk; + tmp |= CCL_LUTCTRL_INSEL0(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL0(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL0(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL0_Msk) >> CCL_LUTCTRL_INSEL0_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL1(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL1(mask)) >> CCL_LUTCTRL_INSEL1_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_INSEL1_Msk; + tmp |= CCL_LUTCTRL_INSEL1(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL1(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL1(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL1_Msk) >> CCL_LUTCTRL_INSEL1_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL2(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL2(mask)) >> CCL_LUTCTRL_INSEL2_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_INSEL2_Msk; + tmp |= CCL_LUTCTRL_INSEL2(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL2(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL2(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL2_Msk) >> CCL_LUTCTRL_INSEL2_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_TRUTH(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_TRUTH(mask)) >> CCL_LUTCTRL_TRUTH_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_TRUTH_Msk; + tmp |= CCL_LUTCTRL_TRUTH(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_TRUTH(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_TRUTH(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_TRUTH_Msk) >> CCL_LUTCTRL_TRUTH_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_reg(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg = data; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_reg(const void *const hw, uint8_t index) +{ + return ((Ccl *)hw)->LUTCTRL[index].reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_CCL_L21_H_INCLUDED */ +#endif /* _SAML21_CCL_COMPONENT_ */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_dac_l21.h b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_dac_l21.h new file mode 100644 index 00000000..328973df --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_dac_l21.h @@ -0,0 +1,1327 @@ +/** + * \file + * + * \brief SAM DAC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_DAC_COMPONENT_ +#ifndef _HRI_DAC_L21_H_INCLUDED_ +#define _HRI_DAC_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_DAC_CRITICAL_SECTIONS) +#define DAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define DAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define DAC_CRITICAL_SECTION_ENTER() +#define DAC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_dac_dacctrl_reg_t; +typedef uint16_t hri_dac_data_reg_t; +typedef uint16_t hri_dac_databuf_reg_t; +typedef uint32_t hri_dac_syncbusy_reg_t; +typedef uint8_t hri_dac_ctrla_reg_t; +typedef uint8_t hri_dac_ctrlb_reg_t; +typedef uint8_t hri_dac_dbgctrl_reg_t; +typedef uint8_t hri_dac_evctrl_reg_t; +typedef uint8_t hri_dac_intenset_reg_t; +typedef uint8_t hri_dac_intflag_reg_t; +typedef uint8_t hri_dac_status_reg_t; + +static inline void hri_dac_wait_for_sync(const void *const hw, hri_dac_syncbusy_reg_t reg) +{ + while (((Dac *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_dac_is_syncing(const void *const hw, hri_dac_syncbusy_reg_t reg) +{ + return ((Dac *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_dac_get_INTFLAG_UNDERRUN0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN0) >> DAC_INTFLAG_UNDERRUN0_Pos; +} + +static inline void hri_dac_clear_INTFLAG_UNDERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN0; +} + +static inline bool hri_dac_get_INTFLAG_UNDERRUN1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN1) >> DAC_INTFLAG_UNDERRUN1_Pos; +} + +static inline void hri_dac_clear_INTFLAG_UNDERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN1; +} + +static inline bool hri_dac_get_INTFLAG_EMPTY0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY0) >> DAC_INTFLAG_EMPTY0_Pos; +} + +static inline void hri_dac_clear_INTFLAG_EMPTY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY0; +} + +static inline bool hri_dac_get_INTFLAG_EMPTY1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY1) >> DAC_INTFLAG_EMPTY1_Pos; +} + +static inline void hri_dac_clear_INTFLAG_EMPTY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY1; +} + +static inline bool hri_dac_get_interrupt_UNDERRUN0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN0) >> DAC_INTFLAG_UNDERRUN0_Pos; +} + +static inline void hri_dac_clear_interrupt_UNDERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN0; +} + +static inline bool hri_dac_get_interrupt_UNDERRUN1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN1) >> DAC_INTFLAG_UNDERRUN1_Pos; +} + +static inline void hri_dac_clear_interrupt_UNDERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN1; +} + +static inline bool hri_dac_get_interrupt_EMPTY0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY0) >> DAC_INTFLAG_EMPTY0_Pos; +} + +static inline void hri_dac_clear_interrupt_EMPTY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY0; +} + +static inline bool hri_dac_get_interrupt_EMPTY1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY1) >> DAC_INTFLAG_EMPTY1_Pos; +} + +static inline void hri_dac_clear_interrupt_EMPTY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY1; +} + +static inline hri_dac_intflag_reg_t hri_dac_get_INTFLAG_reg(const void *const hw, hri_dac_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_intflag_reg_t hri_dac_read_INTFLAG_reg(const void *const hw) +{ + return ((Dac *)hw)->INTFLAG.reg; +} + +static inline void hri_dac_clear_INTFLAG_reg(const void *const hw, hri_dac_intflag_reg_t mask) +{ + ((Dac *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_dac_set_INTEN_UNDERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN0; +} + +static inline bool hri_dac_get_INTEN_UNDERRUN0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_UNDERRUN0) >> DAC_INTENSET_UNDERRUN0_Pos; +} + +static inline void hri_dac_write_INTEN_UNDERRUN0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN0; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN0; + } +} + +static inline void hri_dac_clear_INTEN_UNDERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN0; +} + +static inline void hri_dac_set_INTEN_UNDERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN1; +} + +static inline bool hri_dac_get_INTEN_UNDERRUN1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_UNDERRUN1) >> DAC_INTENSET_UNDERRUN1_Pos; +} + +static inline void hri_dac_write_INTEN_UNDERRUN1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN1; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN1; + } +} + +static inline void hri_dac_clear_INTEN_UNDERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN1; +} + +static inline void hri_dac_set_INTEN_EMPTY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY0; +} + +static inline bool hri_dac_get_INTEN_EMPTY0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_EMPTY0) >> DAC_INTENSET_EMPTY0_Pos; +} + +static inline void hri_dac_write_INTEN_EMPTY0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY0; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY0; + } +} + +static inline void hri_dac_clear_INTEN_EMPTY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY0; +} + +static inline void hri_dac_set_INTEN_EMPTY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY1; +} + +static inline bool hri_dac_get_INTEN_EMPTY1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_EMPTY1) >> DAC_INTENSET_EMPTY1_Pos; +} + +static inline void hri_dac_write_INTEN_EMPTY1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY1; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY1; + } +} + +static inline void hri_dac_clear_INTEN_EMPTY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY1; +} + +static inline void hri_dac_set_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) +{ + ((Dac *)hw)->INTENSET.reg = mask; +} + +static inline hri_dac_intenset_reg_t hri_dac_get_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_intenset_reg_t hri_dac_read_INTEN_reg(const void *const hw) +{ + return ((Dac *)hw)->INTENSET.reg; +} + +static inline void hri_dac_write_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t data) +{ + ((Dac *)hw)->INTENSET.reg = data; + ((Dac *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_dac_clear_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) +{ + ((Dac *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_dac_get_STATUS_READY0_bit(const void *const hw) +{ + return (((Dac *)hw)->STATUS.reg & DAC_STATUS_READY0) >> DAC_STATUS_READY0_Pos; +} + +static inline bool hri_dac_get_STATUS_READY1_bit(const void *const hw) +{ + return (((Dac *)hw)->STATUS.reg & DAC_STATUS_READY1) >> DAC_STATUS_READY1_Pos; +} + +static inline bool hri_dac_get_STATUS_EOC0_bit(const void *const hw) +{ + return (((Dac *)hw)->STATUS.reg & DAC_STATUS_EOC0) >> DAC_STATUS_EOC0_Pos; +} + +static inline bool hri_dac_get_STATUS_EOC1_bit(const void *const hw) +{ + return (((Dac *)hw)->STATUS.reg & DAC_STATUS_EOC1) >> DAC_STATUS_EOC1_Pos; +} + +static inline hri_dac_status_reg_t hri_dac_get_STATUS_reg(const void *const hw, hri_dac_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_status_reg_t hri_dac_read_STATUS_reg(const void *const hw) +{ + return ((Dac *)hw)->STATUS.reg; +} + +static inline bool hri_dac_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_SWRST) >> DAC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_dac_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_ENABLE) >> DAC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_dac_get_SYNCBUSY_DATA0_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATA0) >> DAC_SYNCBUSY_DATA0_Pos; +} + +static inline bool hri_dac_get_SYNCBUSY_DATA1_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATA1) >> DAC_SYNCBUSY_DATA1_Pos; +} + +static inline bool hri_dac_get_SYNCBUSY_DATABUF0_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATABUF0) >> DAC_SYNCBUSY_DATABUF0_Pos; +} + +static inline bool hri_dac_get_SYNCBUSY_DATABUF1_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATABUF1) >> DAC_SYNCBUSY_DATABUF1_Pos; +} + +static inline hri_dac_syncbusy_reg_t hri_dac_get_SYNCBUSY_reg(const void *const hw, hri_dac_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dac *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_syncbusy_reg_t hri_dac_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Dac *)hw)->SYNCBUSY.reg; +} + +static inline void hri_dac_set_CTRLA_SWRST_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_SWRST; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST); + tmp = ((Dac *)hw)->CTRLA.reg; + tmp = (tmp & DAC_CTRLA_SWRST) >> DAC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_dac_set_CTRLA_ENABLE_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_ENABLE; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + tmp = ((Dac *)hw)->CTRLA.reg; + tmp = (tmp & DAC_CTRLA_ENABLE) >> DAC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->CTRLA.reg; + tmp &= ~DAC_CTRLA_ENABLE; + tmp |= value << DAC_CTRLA_ENABLE_Pos; + ((Dac *)hw)->CTRLA.reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg &= ~DAC_CTRLA_ENABLE; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg ^= DAC_CTRLA_ENABLE; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg |= mask; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrla_reg_t hri_dac_get_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + tmp = ((Dac *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg = data; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg &= ~mask; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg ^= mask; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrla_reg_t hri_dac_read_CTRLA_reg(const void *const hw) +{ + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + return ((Dac *)hw)->CTRLA.reg; +} + +static inline void hri_dac_set_CTRLB_DIFF_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_DIFF; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLB_DIFF_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp = (tmp & DAC_CTRLB_DIFF) >> DAC_CTRLB_DIFF_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_CTRLB_DIFF_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->CTRLB.reg; + tmp &= ~DAC_CTRLB_DIFF; + tmp |= value << DAC_CTRLB_DIFF_Pos; + ((Dac *)hw)->CTRLB.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLB_DIFF_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_DIFF; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLB_DIFF_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_DIFF; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_REFSEL(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrlb_reg_t hri_dac_get_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp = (tmp & DAC_CTRLB_REFSEL(mask)) >> DAC_CTRLB_REFSEL_Pos; + return tmp; +} + +static inline void hri_dac_write_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t data) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->CTRLB.reg; + tmp &= ~DAC_CTRLB_REFSEL_Msk; + tmp |= DAC_CTRLB_REFSEL(data); + ((Dac *)hw)->CTRLB.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_REFSEL(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_REFSEL(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrlb_reg_t hri_dac_read_CTRLB_REFSEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp = (tmp & DAC_CTRLB_REFSEL_Msk) >> DAC_CTRLB_REFSEL_Pos; + return tmp; +} + +static inline void hri_dac_set_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg |= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrlb_reg_t hri_dac_get_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg = data; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg &= ~mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg ^= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrlb_reg_t hri_dac_read_CTRLB_reg(const void *const hw) +{ + return ((Dac *)hw)->CTRLB.reg; +} + +static inline void hri_dac_set_EVCTRL_STARTEI0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_STARTEI0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_STARTEI0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_STARTEI0) >> DAC_EVCTRL_STARTEI0_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_STARTEI0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_STARTEI0; + tmp |= value << DAC_EVCTRL_STARTEI0_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_STARTEI0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_STARTEI0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_STARTEI0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_STARTEI0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_STARTEI1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_STARTEI1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_STARTEI1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_STARTEI1) >> DAC_EVCTRL_STARTEI1_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_STARTEI1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_STARTEI1; + tmp |= value << DAC_EVCTRL_STARTEI1_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_STARTEI1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_STARTEI1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_STARTEI1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_STARTEI1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_EMPTYEO0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_EMPTYEO0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_EMPTYEO0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_EMPTYEO0) >> DAC_EVCTRL_EMPTYEO0_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_EMPTYEO0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_EMPTYEO0; + tmp |= value << DAC_EVCTRL_EMPTYEO0_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_EMPTYEO0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_EMPTYEO0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_EMPTYEO0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_EMPTYEO0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_EMPTYEO1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_EMPTYEO1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_EMPTYEO1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_EMPTYEO1) >> DAC_EVCTRL_EMPTYEO1_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_EMPTYEO1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_EMPTYEO1; + tmp |= value << DAC_EVCTRL_EMPTYEO1_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_EMPTYEO1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_EMPTYEO1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_EMPTYEO1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_EMPTYEO1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_INVEI0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_INVEI0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_INVEI0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_INVEI0) >> DAC_EVCTRL_INVEI0_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_INVEI0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_INVEI0; + tmp |= value << DAC_EVCTRL_INVEI0_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_INVEI0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_INVEI0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_INVEI0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_INVEI0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_INVEI1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_INVEI1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_INVEI1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_INVEI1) >> DAC_EVCTRL_INVEI1_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_INVEI1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_INVEI1; + tmp |= value << DAC_EVCTRL_INVEI1_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_INVEI1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_INVEI1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_INVEI1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_INVEI1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_evctrl_reg_t hri_dac_get_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg = data; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_evctrl_reg_t hri_dac_read_EVCTRL_reg(const void *const hw) +{ + return ((Dac *)hw)->EVCTRL.reg; +} + +static inline void hri_dac_set_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_LEFTADJ; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_LEFTADJ) >> DAC_DACCTRL_LEFTADJ_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index, bool value) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_LEFTADJ; + tmp |= value << DAC_DACCTRL_LEFTADJ_Pos; + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_LEFTADJ; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_LEFTADJ; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_ENABLE; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + uint16_t tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_ENABLE) >> DAC_DACCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_ENABLE; + tmp |= value << DAC_DACCTRL_ENABLE_Pos; + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_ENABLE; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_ENABLE; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_RUNSTDBY; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_RUNSTDBY) >> DAC_DACCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_RUNSTDBY; + tmp |= value << DAC_DACCTRL_RUNSTDBY_Pos; + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_RUNSTDBY; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_RUNSTDBY; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_DITHER; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_DITHER) >> DAC_DACCTRL_DITHER_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_DACCTRL_DITHER_bit(const void *const hw, uint8_t index, bool value) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_DITHER; + tmp |= value << DAC_DACCTRL_DITHER_Pos; + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_DITHER; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_DITHER; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_CCTRL(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, + hri_dac_dacctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_CCTRL(mask)) >> DAC_DACCTRL_CCTRL_Pos; + return tmp; +} + +static inline void hri_dac_write_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_CCTRL_Msk; + tmp |= DAC_DACCTRL_CCTRL(data); + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_CCTRL(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_CCTRL(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_CCTRL_Msk) >> DAC_DACCTRL_CCTRL_Pos; + return tmp; +} + +static inline void hri_dac_set_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_REFRESH(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, + hri_dac_dacctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_REFRESH(mask)) >> DAC_DACCTRL_REFRESH_Pos; + return tmp; +} + +static inline void hri_dac_write_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_REFRESH_Msk; + tmp |= DAC_DACCTRL_REFRESH(data); + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_REFRESH(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_REFRESH(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_REFRESH_Msk) >> DAC_DACCTRL_REFRESH_Pos; + return tmp; +} + +static inline void hri_dac_set_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= mask; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_reg(const void *const hw, uint8_t index, + hri_dac_dacctrl_reg_t mask) +{ + uint16_t tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg = data; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~mask; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= mask; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_reg(const void *const hw, uint8_t index) +{ + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + return ((Dac *)hw)->DACCTRL[index].reg; +} + +static inline void hri_dac_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg |= DAC_DBGCTRL_DBGRUN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->DBGCTRL.reg; + tmp = (tmp & DAC_DBGCTRL_DBGRUN) >> DAC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DBGCTRL.reg; + tmp &= ~DAC_DBGCTRL_DBGRUN; + tmp |= value << DAC_DBGCTRL_DBGRUN_Pos; + ((Dac *)hw)->DBGCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg &= ~DAC_DBGCTRL_DBGRUN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg ^= DAC_DBGCTRL_DBGRUN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg |= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dbgctrl_reg_t hri_dac_get_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg = data; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg &= ~mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg ^= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dbgctrl_reg_t hri_dac_read_DBGCTRL_reg(const void *const hw) +{ + return ((Dac *)hw)->DBGCTRL.reg; +} + +static inline void hri_dac_write_DATA_reg(const void *const hw, uint8_t index, hri_dac_data_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DATA[index].reg = data; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_DATA0 | DAC_SYNCBUSY_DATA1); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_write_DATABUF_reg(const void *const hw, uint8_t index, hri_dac_databuf_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DATABUF[index].reg = data; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_DATABUF0 | DAC_SYNCBUSY_DATABUF1); + DAC_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_DAC_L21_H_INCLUDED */ +#endif /* _SAML21_DAC_COMPONENT_ */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_dmac_l21.h b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_dmac_l21.h new file mode 100644 index 00000000..f3e1a5a9 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_dmac_l21.h @@ -0,0 +1,4559 @@ +/** + * \file + * + * \brief SAM DMAC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_DMAC_COMPONENT_ +#ifndef _HRI_DMAC_L21_H_INCLUDED_ +#define _HRI_DMAC_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_DMAC_CRITICAL_SECTIONS) +#define DMAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define DMAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define DMAC_CRITICAL_SECTION_ENTER() +#define DMAC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_dmac_crcctrl_reg_t; +typedef uint16_t hri_dmac_ctrl_reg_t; +typedef uint16_t hri_dmac_intpend_reg_t; +typedef uint16_t hri_dmacdescriptor_btcnt_reg_t; +typedef uint16_t hri_dmacdescriptor_btctrl_reg_t; +typedef uint32_t hri_dmac_active_reg_t; +typedef uint32_t hri_dmac_baseaddr_reg_t; +typedef uint32_t hri_dmac_busych_reg_t; +typedef uint32_t hri_dmac_chctrlb_reg_t; +typedef uint32_t hri_dmac_crcchksum_reg_t; +typedef uint32_t hri_dmac_crcdatain_reg_t; +typedef uint32_t hri_dmac_intstatus_reg_t; +typedef uint32_t hri_dmac_pendch_reg_t; +typedef uint32_t hri_dmac_prictrl0_reg_t; +typedef uint32_t hri_dmac_swtrigctrl_reg_t; +typedef uint32_t hri_dmac_wrbaddr_reg_t; +typedef uint32_t hri_dmacdescriptor_descaddr_reg_t; +typedef uint32_t hri_dmacdescriptor_dstaddr_reg_t; +typedef uint32_t hri_dmacdescriptor_srcaddr_reg_t; +typedef uint8_t hri_dmac_chctrla_reg_t; +typedef uint8_t hri_dmac_chid_reg_t; +typedef uint8_t hri_dmac_chintenset_reg_t; +typedef uint8_t hri_dmac_chintflag_reg_t; +typedef uint8_t hri_dmac_chstatus_reg_t; +typedef uint8_t hri_dmac_crcstatus_reg_t; +typedef uint8_t hri_dmac_dbgctrl_reg_t; +typedef uint8_t hri_dmac_qosctrl_reg_t; + +static inline bool hri_dmac_get_CHINTFLAG_TERR_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; +} + +static inline void hri_dmac_clear_CHINTFLAG_TERR_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; +} + +static inline bool hri_dmac_get_CHINTFLAG_TCMPL_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; +} + +static inline void hri_dmac_clear_CHINTFLAG_TCMPL_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; +} + +static inline bool hri_dmac_get_CHINTFLAG_SUSP_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; +} + +static inline void hri_dmac_clear_CHINTFLAG_SUSP_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; +} + +static inline bool hri_dmac_get_interrupt_TERR_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; +} + +static inline void hri_dmac_clear_interrupt_TERR_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; +} + +static inline bool hri_dmac_get_interrupt_TCMPL_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; +} + +static inline void hri_dmac_clear_interrupt_TCMPL_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; +} + +static inline bool hri_dmac_get_interrupt_SUSP_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; +} + +static inline void hri_dmac_clear_interrupt_SUSP_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; +} + +static inline hri_dmac_chintflag_reg_t hri_dmac_get_CHINTFLAG_reg(const void *const hw, hri_dmac_chintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_chintflag_reg_t hri_dmac_read_CHINTFLAG_reg(const void *const hw) +{ + return ((Dmac *)hw)->CHINTFLAG.reg; +} + +static inline void hri_dmac_clear_CHINTFLAG_reg(const void *const hw, hri_dmac_chintflag_reg_t mask) +{ + ((Dmac *)hw)->CHINTFLAG.reg = mask; +} + +static inline void hri_dmac_set_CHINTEN_TERR_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR; +} + +static inline bool hri_dmac_get_CHINTEN_TERR_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TERR) >> DMAC_CHINTENSET_TERR_Pos; +} + +static inline void hri_dmac_write_CHINTEN_TERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR; + } else { + ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR; + } +} + +static inline void hri_dmac_clear_CHINTEN_TERR_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR; +} + +static inline void hri_dmac_set_CHINTEN_TCMPL_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; +} + +static inline bool hri_dmac_get_CHINTEN_TCMPL_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TCMPL) >> DMAC_CHINTENSET_TCMPL_Pos; +} + +static inline void hri_dmac_write_CHINTEN_TCMPL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; + } else { + ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; + } +} + +static inline void hri_dmac_clear_CHINTEN_TCMPL_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; +} + +static inline void hri_dmac_set_CHINTEN_SUSP_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP; +} + +static inline bool hri_dmac_get_CHINTEN_SUSP_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_SUSP) >> DMAC_CHINTENSET_SUSP_Pos; +} + +static inline void hri_dmac_write_CHINTEN_SUSP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; + } else { + ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP; + } +} + +static inline void hri_dmac_clear_CHINTEN_SUSP_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; +} + +static inline void hri_dmac_set_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask) +{ + ((Dmac *)hw)->CHINTENSET.reg = mask; +} + +static inline hri_dmac_chintenset_reg_t hri_dmac_get_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_chintenset_reg_t hri_dmac_read_CHINTEN_reg(const void *const hw) +{ + return ((Dmac *)hw)->CHINTENSET.reg; +} + +static inline void hri_dmac_write_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t data) +{ + ((Dmac *)hw)->CHINTENSET.reg = data; + ((Dmac *)hw)->CHINTENCLR.reg = ~data; +} + +static inline void hri_dmac_clear_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask) +{ + ((Dmac *)hw)->CHINTENCLR.reg = mask; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT0_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT0) >> DMAC_INTSTATUS_CHINT0_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT1_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT1) >> DMAC_INTSTATUS_CHINT1_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT2_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT2) >> DMAC_INTSTATUS_CHINT2_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT3_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT3) >> DMAC_INTSTATUS_CHINT3_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT4_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT4) >> DMAC_INTSTATUS_CHINT4_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT5_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT5) >> DMAC_INTSTATUS_CHINT5_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT6_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT6) >> DMAC_INTSTATUS_CHINT6_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT7_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT7) >> DMAC_INTSTATUS_CHINT7_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT8_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT8) >> DMAC_INTSTATUS_CHINT8_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT9_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT9) >> DMAC_INTSTATUS_CHINT9_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT10_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT10) >> DMAC_INTSTATUS_CHINT10_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT11_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT11) >> DMAC_INTSTATUS_CHINT11_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT12_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT12) >> DMAC_INTSTATUS_CHINT12_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT13_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT13) >> DMAC_INTSTATUS_CHINT13_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT14_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT14) >> DMAC_INTSTATUS_CHINT14_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT15_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT15) >> DMAC_INTSTATUS_CHINT15_Pos; +} + +static inline hri_dmac_intstatus_reg_t hri_dmac_get_INTSTATUS_reg(const void *const hw, hri_dmac_intstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->INTSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_intstatus_reg_t hri_dmac_read_INTSTATUS_reg(const void *const hw) +{ + return ((Dmac *)hw)->INTSTATUS.reg; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH0_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH0) >> DMAC_BUSYCH_BUSYCH0_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH1_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH1) >> DMAC_BUSYCH_BUSYCH1_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH2_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH2) >> DMAC_BUSYCH_BUSYCH2_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH3_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH3) >> DMAC_BUSYCH_BUSYCH3_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH4_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH4) >> DMAC_BUSYCH_BUSYCH4_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH5_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH5) >> DMAC_BUSYCH_BUSYCH5_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH6_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH6) >> DMAC_BUSYCH_BUSYCH6_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH7_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH7) >> DMAC_BUSYCH_BUSYCH7_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH8_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH8) >> DMAC_BUSYCH_BUSYCH8_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH9_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH9) >> DMAC_BUSYCH_BUSYCH9_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH10_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH10) >> DMAC_BUSYCH_BUSYCH10_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH11_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH11) >> DMAC_BUSYCH_BUSYCH11_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH12_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH12) >> DMAC_BUSYCH_BUSYCH12_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH13_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH13) >> DMAC_BUSYCH_BUSYCH13_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH14_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH14) >> DMAC_BUSYCH_BUSYCH14_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH15_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH15) >> DMAC_BUSYCH_BUSYCH15_Pos; +} + +static inline hri_dmac_busych_reg_t hri_dmac_get_BUSYCH_reg(const void *const hw, hri_dmac_busych_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BUSYCH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_busych_reg_t hri_dmac_read_BUSYCH_reg(const void *const hw) +{ + return ((Dmac *)hw)->BUSYCH.reg; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH0_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH0) >> DMAC_PENDCH_PENDCH0_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH1_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH1) >> DMAC_PENDCH_PENDCH1_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH2_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH2) >> DMAC_PENDCH_PENDCH2_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH3_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH3) >> DMAC_PENDCH_PENDCH3_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH4_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH4) >> DMAC_PENDCH_PENDCH4_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH5_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH5) >> DMAC_PENDCH_PENDCH5_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH6_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH6) >> DMAC_PENDCH_PENDCH6_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH7_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH7) >> DMAC_PENDCH_PENDCH7_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH8_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH8) >> DMAC_PENDCH_PENDCH8_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH9_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH9) >> DMAC_PENDCH_PENDCH9_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH10_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH10) >> DMAC_PENDCH_PENDCH10_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH11_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH11) >> DMAC_PENDCH_PENDCH11_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH12_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH12) >> DMAC_PENDCH_PENDCH12_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH13_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH13) >> DMAC_PENDCH_PENDCH13_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH14_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH14) >> DMAC_PENDCH_PENDCH14_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH15_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH15) >> DMAC_PENDCH_PENDCH15_Pos; +} + +static inline hri_dmac_pendch_reg_t hri_dmac_get_PENDCH_reg(const void *const hw, hri_dmac_pendch_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PENDCH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_pendch_reg_t hri_dmac_read_PENDCH_reg(const void *const hw) +{ + return ((Dmac *)hw)->PENDCH.reg; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX0_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX0) >> DMAC_ACTIVE_LVLEX0_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX1_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX1) >> DMAC_ACTIVE_LVLEX1_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX2_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX2) >> DMAC_ACTIVE_LVLEX2_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX3_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX3) >> DMAC_ACTIVE_LVLEX3_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_ABUSY_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ABUSY) >> DMAC_ACTIVE_ABUSY_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_ID_bf(const void *const hw, hri_dmac_active_reg_t mask) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID(mask)) >> DMAC_ACTIVE_ID_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_ID_bf(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID_Msk) >> DMAC_ACTIVE_ID_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_BTCNT_bf(const void *const hw, hri_dmac_active_reg_t mask) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT(mask)) >> DMAC_ACTIVE_BTCNT_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_BTCNT_bf(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT_Msk) >> DMAC_ACTIVE_BTCNT_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_reg(const void *const hw, hri_dmac_active_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->ACTIVE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_reg(const void *const hw) +{ + return ((Dmac *)hw)->ACTIVE.reg; +} + +static inline bool hri_dmac_get_CHSTATUS_PEND_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_PEND) >> DMAC_CHSTATUS_PEND_Pos; +} + +static inline bool hri_dmac_get_CHSTATUS_BUSY_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_BUSY) >> DMAC_CHSTATUS_BUSY_Pos; +} + +static inline bool hri_dmac_get_CHSTATUS_FERR_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_FERR) >> DMAC_CHSTATUS_FERR_Pos; +} + +static inline hri_dmac_chstatus_reg_t hri_dmac_get_CHSTATUS_reg(const void *const hw, hri_dmac_chstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_chstatus_reg_t hri_dmac_read_CHSTATUS_reg(const void *const hw) +{ + return ((Dmac *)hw)->CHSTATUS.reg; +} + +static inline void hri_dmac_set_CTRL_SWRST_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_SWRST; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_SWRST) >> DMAC_CTRL_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_set_CTRL_DMAENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_DMAENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_DMAENABLE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_DMAENABLE) >> DMAC_CTRL_DMAENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_DMAENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_DMAENABLE; + tmp |= value << DMAC_CTRL_DMAENABLE_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_DMAENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_DMAENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_DMAENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_DMAENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_CRCENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_CRCENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_CRCENABLE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_CRCENABLE) >> DMAC_CTRL_CRCENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_CRCENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_CRCENABLE; + tmp |= value << DMAC_CTRL_CRCENABLE_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_CRCENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_CRCENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_CRCENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_CRCENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN0) >> DMAC_CTRL_LVLEN0_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN0; + tmp |= value << DMAC_CTRL_LVLEN0_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN1) >> DMAC_CTRL_LVLEN1_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN1; + tmp |= value << DMAC_CTRL_LVLEN1_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN2) >> DMAC_CTRL_LVLEN2_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN2; + tmp |= value << DMAC_CTRL_LVLEN2_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN3) >> DMAC_CTRL_LVLEN3_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN3; + tmp |= value << DMAC_CTRL_LVLEN3_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_ctrl_reg_t hri_dmac_get_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_ctrl_reg_t hri_dmac_read_CTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->CTRL.reg; +} + +static inline void hri_dmac_set_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCBEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, + hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE(mask)) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= ~DMAC_CRCCTRL_CRCBEATSIZE_Msk; + tmp |= DMAC_CRCCTRL_CRCBEATSIZE(data); + ((Dmac *)hw)->CRCCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCBEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCBEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCBEATSIZE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE_Msk) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCPOLY(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCPOLY(mask)) >> DMAC_CRCCTRL_CRCPOLY_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= ~DMAC_CRCCTRL_CRCPOLY_Msk; + tmp |= DMAC_CRCCTRL_CRCPOLY(data); + ((Dmac *)hw)->CRCCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCPOLY(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCPOLY(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCPOLY_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCPOLY_Msk) >> DMAC_CRCCTRL_CRCPOLY_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCSRC(mask)) >> DMAC_CRCCTRL_CRCSRC_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= ~DMAC_CRCCTRL_CRCSRC_Msk; + tmp |= DMAC_CRCCTRL_CRCSRC(data); + ((Dmac *)hw)->CRCCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCSRC_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCSRC_Msk) >> DMAC_CRCCTRL_CRCSRC_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCCTRL.reg; +} + +static inline void hri_dmac_set_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg |= DMAC_CRCDATAIN_CRCDATAIN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_CRCDATAIN_bf(const void *const hw, + hri_dmac_crcdatain_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN(mask)) >> DMAC_CRCDATAIN_CRCDATAIN_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp &= ~DMAC_CRCDATAIN_CRCDATAIN_Msk; + tmp |= DMAC_CRCDATAIN_CRCDATAIN(data); + ((Dmac *)hw)->CRCDATAIN.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg &= ~DMAC_CRCDATAIN_CRCDATAIN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg ^= DMAC_CRCDATAIN_CRCDATAIN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_CRCDATAIN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN_Msk) >> DMAC_CRCDATAIN_CRCDATAIN_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCDATAIN.reg; +} + +static inline void hri_dmac_set_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg |= DMAC_CRCCHKSUM_CRCCHKSUM(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, + hri_dmac_crcchksum_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM(mask)) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp &= ~DMAC_CRCCHKSUM_CRCCHKSUM_Msk; + tmp |= DMAC_CRCCHKSUM_CRCCHKSUM(data); + ((Dmac *)hw)->CRCCHKSUM.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg &= ~DMAC_CRCCHKSUM_CRCCHKSUM(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg ^= DMAC_CRCCHKSUM_CRCCHKSUM(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM_Msk) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCCHKSUM.reg; +} + +static inline void hri_dmac_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg |= DMAC_DBGCTRL_DBGRUN; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->DBGCTRL.reg; + tmp = (tmp & DMAC_DBGCTRL_DBGRUN) >> DMAC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->DBGCTRL.reg; + tmp &= ~DMAC_DBGCTRL_DBGRUN; + tmp |= value << DMAC_DBGCTRL_DBGRUN_Pos; + ((Dmac *)hw)->DBGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg &= ~DMAC_DBGCTRL_DBGRUN; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg ^= DMAC_DBGCTRL_DBGRUN; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_dbgctrl_reg_t hri_dmac_get_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_dbgctrl_reg_t hri_dmac_read_DBGCTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->DBGCTRL.reg; +} + +static inline void hri_dmac_set_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg |= DMAC_QOSCTRL_WRBQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp = (tmp & DMAC_QOSCTRL_WRBQOS(mask)) >> DMAC_QOSCTRL_WRBQOS_Pos; + return tmp; +} + +static inline void hri_dmac_write_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp &= ~DMAC_QOSCTRL_WRBQOS_Msk; + tmp |= DMAC_QOSCTRL_WRBQOS(data); + ((Dmac *)hw)->QOSCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg &= ~DMAC_QOSCTRL_WRBQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg ^= DMAC_QOSCTRL_WRBQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_WRBQOS_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp = (tmp & DMAC_QOSCTRL_WRBQOS_Msk) >> DMAC_QOSCTRL_WRBQOS_Pos; + return tmp; +} + +static inline void hri_dmac_set_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg |= DMAC_QOSCTRL_FQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp = (tmp & DMAC_QOSCTRL_FQOS(mask)) >> DMAC_QOSCTRL_FQOS_Pos; + return tmp; +} + +static inline void hri_dmac_write_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp &= ~DMAC_QOSCTRL_FQOS_Msk; + tmp |= DMAC_QOSCTRL_FQOS(data); + ((Dmac *)hw)->QOSCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg &= ~DMAC_QOSCTRL_FQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg ^= DMAC_QOSCTRL_FQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_FQOS_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp = (tmp & DMAC_QOSCTRL_FQOS_Msk) >> DMAC_QOSCTRL_FQOS_Pos; + return tmp; +} + +static inline void hri_dmac_set_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg |= DMAC_QOSCTRL_DQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp = (tmp & DMAC_QOSCTRL_DQOS(mask)) >> DMAC_QOSCTRL_DQOS_Pos; + return tmp; +} + +static inline void hri_dmac_write_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp &= ~DMAC_QOSCTRL_DQOS_Msk; + tmp |= DMAC_QOSCTRL_DQOS(data); + ((Dmac *)hw)->QOSCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg &= ~DMAC_QOSCTRL_DQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg ^= DMAC_QOSCTRL_DQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_DQOS_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp = (tmp & DMAC_QOSCTRL_DQOS_Msk) >> DMAC_QOSCTRL_DQOS_Pos; + return tmp; +} + +static inline void hri_dmac_set_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->QOSCTRL.reg; +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG0) >> DMAC_SWTRIGCTRL_SWTRIG0_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG0; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG0_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG1) >> DMAC_SWTRIGCTRL_SWTRIG1_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG1; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG1_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG2) >> DMAC_SWTRIGCTRL_SWTRIG2_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG2; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG2_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG3) >> DMAC_SWTRIGCTRL_SWTRIG3_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG3; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG3_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG4; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG4) >> DMAC_SWTRIGCTRL_SWTRIG4_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG4; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG4_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG4; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG4; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG5; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG5) >> DMAC_SWTRIGCTRL_SWTRIG5_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG5; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG5_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG5; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG5; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG6; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG6) >> DMAC_SWTRIGCTRL_SWTRIG6_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG6; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG6_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG6; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG6; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG7; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG7) >> DMAC_SWTRIGCTRL_SWTRIG7_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG7; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG7_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG7; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG7; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG8; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG8) >> DMAC_SWTRIGCTRL_SWTRIG8_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG8; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG8_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG8; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG8; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG9; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG9) >> DMAC_SWTRIGCTRL_SWTRIG9_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG9; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG9_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG9; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG9; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG10; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG10) >> DMAC_SWTRIGCTRL_SWTRIG10_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG10; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG10_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG10; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG10; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG11; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG11) >> DMAC_SWTRIGCTRL_SWTRIG11_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG11; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG11_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG11; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG11; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG12; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG12) >> DMAC_SWTRIGCTRL_SWTRIG12_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG12; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG12_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG12; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG12; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG13; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG13) >> DMAC_SWTRIGCTRL_SWTRIG13_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG13; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG13_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG13; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG13; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG14; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG14) >> DMAC_SWTRIGCTRL_SWTRIG14_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG14; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG14_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG14; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG14; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG15; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG15) >> DMAC_SWTRIGCTRL_SWTRIG15_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG15; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG15_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG15; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG15; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_swtrigctrl_reg_t hri_dmac_get_SWTRIGCTRL_reg(const void *const hw, + hri_dmac_swtrigctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_swtrigctrl_reg_t hri_dmac_read_SWTRIGCTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->SWTRIGCTRL.reg; +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN0) >> DMAC_PRICTRL0_RRLVLEN0_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN0; + tmp |= value << DMAC_PRICTRL0_RRLVLEN0_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN1) >> DMAC_PRICTRL0_RRLVLEN1_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN1; + tmp |= value << DMAC_PRICTRL0_RRLVLEN1_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN2) >> DMAC_PRICTRL0_RRLVLEN2_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN2; + tmp |= value << DMAC_PRICTRL0_RRLVLEN2_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN3) >> DMAC_PRICTRL0_RRLVLEN3_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN3; + tmp |= value << DMAC_PRICTRL0_RRLVLEN3_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI0_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI0(mask)) >> DMAC_PRICTRL0_LVLPRI0_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI0_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI0(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI0_Msk) >> DMAC_PRICTRL0_LVLPRI0_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI1_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI1(mask)) >> DMAC_PRICTRL0_LVLPRI1_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI1_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI1(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI1_Msk) >> DMAC_PRICTRL0_LVLPRI1_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI2_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI2(mask)) >> DMAC_PRICTRL0_LVLPRI2_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI2_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI2(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI2_Msk) >> DMAC_PRICTRL0_LVLPRI2_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI3_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI3(mask)) >> DMAC_PRICTRL0_LVLPRI3_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI3_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI3(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI3_Msk) >> DMAC_PRICTRL0_LVLPRI3_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_reg(const void *const hw) +{ + return ((Dmac *)hw)->PRICTRL0.reg; +} + +static inline void hri_dmac_set_INTPEND_TERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_TERR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_TERR) >> DMAC_INTPEND_TERR_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_TERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_TERR; + tmp |= value << DMAC_INTPEND_TERR_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_TERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_TERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_TCMPL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TCMPL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_TCMPL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_TCMPL) >> DMAC_INTPEND_TCMPL_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_TCMPL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_TCMPL; + tmp |= value << DMAC_INTPEND_TCMPL_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_TCMPL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TCMPL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_TCMPL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TCMPL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_SUSP_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_SUSP; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_SUSP_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_SUSP) >> DMAC_INTPEND_SUSP_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_SUSP_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_SUSP; + tmp |= value << DMAC_INTPEND_SUSP_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_SUSP_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_SUSP; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_SUSP_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_SUSP; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_FERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_FERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_FERR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_FERR) >> DMAC_INTPEND_FERR_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_FERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_FERR; + tmp |= value << DMAC_INTPEND_FERR_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_FERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_FERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_FERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_FERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_BUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_BUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_BUSY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_BUSY) >> DMAC_INTPEND_BUSY_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_BUSY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_BUSY; + tmp |= value << DMAC_INTPEND_BUSY_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_BUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_BUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_BUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_BUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_PEND_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_PEND; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_PEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_PEND) >> DMAC_INTPEND_PEND_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_PEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_PEND; + tmp |= value << DMAC_INTPEND_PEND_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_PEND_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_PEND; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_PEND_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_PEND; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_ID(mask)) >> DMAC_INTPEND_ID_Pos; + return tmp; +} + +static inline void hri_dmac_write_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_ID_Msk; + tmp |= DMAC_INTPEND_ID(data); + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_ID_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_ID_Msk) >> DMAC_INTPEND_ID_Pos; + return tmp; +} + +static inline void hri_dmac_set_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_reg(const void *const hw) +{ + return ((Dmac *)hw)->INTPEND.reg; +} + +static inline void hri_dmac_set_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg |= DMAC_BASEADDR_BASEADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_BASEADDR_bf(const void *const hw, + hri_dmac_baseaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp = (tmp & DMAC_BASEADDR_BASEADDR(mask)) >> DMAC_BASEADDR_BASEADDR_Pos; + return tmp; +} + +static inline void hri_dmac_write_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp &= ~DMAC_BASEADDR_BASEADDR_Msk; + tmp |= DMAC_BASEADDR_BASEADDR(data); + ((Dmac *)hw)->BASEADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg &= ~DMAC_BASEADDR_BASEADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg ^= DMAC_BASEADDR_BASEADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_BASEADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp = (tmp & DMAC_BASEADDR_BASEADDR_Msk) >> DMAC_BASEADDR_BASEADDR_Pos; + return tmp; +} + +static inline void hri_dmac_set_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_reg(const void *const hw) +{ + return ((Dmac *)hw)->BASEADDR.reg; +} + +static inline void hri_dmac_set_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg |= DMAC_WRBADDR_WRBADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp = (tmp & DMAC_WRBADDR_WRBADDR(mask)) >> DMAC_WRBADDR_WRBADDR_Pos; + return tmp; +} + +static inline void hri_dmac_write_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp &= ~DMAC_WRBADDR_WRBADDR_Msk; + tmp |= DMAC_WRBADDR_WRBADDR(data); + ((Dmac *)hw)->WRBADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg &= ~DMAC_WRBADDR_WRBADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg ^= DMAC_WRBADDR_WRBADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_WRBADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp = (tmp & DMAC_WRBADDR_WRBADDR_Msk) >> DMAC_WRBADDR_WRBADDR_Pos; + return tmp; +} + +static inline void hri_dmac_set_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_reg(const void *const hw) +{ + return ((Dmac *)hw)->WRBADDR.reg; +} + +static inline void hri_dmac_set_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHID.reg |= DMAC_CHID_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chid_reg_t hri_dmac_get_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHID.reg; + tmp = (tmp & DMAC_CHID_ID(mask)) >> DMAC_CHID_ID_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHID.reg; + tmp &= ~DMAC_CHID_ID_Msk; + tmp |= DMAC_CHID_ID(data); + ((Dmac *)hw)->CHID.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHID.reg &= ~DMAC_CHID_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHID.reg ^= DMAC_CHID_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chid_reg_t hri_dmac_read_CHID_ID_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHID.reg; + tmp = (tmp & DMAC_CHID_ID_Msk) >> DMAC_CHID_ID_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHID.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chid_reg_t hri_dmac_get_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHID.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CHID_reg(const void *const hw, hri_dmac_chid_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHID.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHID.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHID.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chid_reg_t hri_dmac_read_CHID_reg(const void *const hw) +{ + return ((Dmac *)hw)->CHID.reg; +} + +static inline void hri_dmac_set_CHCTRLA_SWRST_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_SWRST; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_SWRST) >> DMAC_CHCTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_set_CHCTRLA_ENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_ENABLE) >> DMAC_CHCTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CHCTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_ENABLE; + tmp |= value << DMAC_CHCTRLA_ENABLE_Pos; + ((Dmac *)hw)->CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_ENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_ENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CHCTRLA_RUNSTDBY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_RUNSTDBY) >> DMAC_CHCTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CHCTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_RUNSTDBY; + tmp |= value << DMAC_CHCTRLA_RUNSTDBY_Pos; + ((Dmac *)hw)->CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_RUNSTDBY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_RUNSTDBY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_reg(const void *const hw) +{ + return ((Dmac *)hw)->CHCTRLA.reg; +} + +static inline void hri_dmac_set_CHCTRLB_EVIE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLB_EVIE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_EVIE) >> DMAC_CHCTRLB_EVIE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CHCTRLB_EVIE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_EVIE; + tmp |= value << DMAC_CHCTRLB_EVIE_Pos; + ((Dmac *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_EVIE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_EVIE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CHCTRLB_EVOE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLB_EVOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_EVOE) >> DMAC_CHCTRLB_EVOE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CHCTRLB_EVOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_EVOE; + tmp |= value << DMAC_CHCTRLB_EVOE_Pos; + ((Dmac *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_EVOE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_EVOE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_EVACT(mask)) >> DMAC_CHCTRLB_EVACT_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_EVACT_Msk; + tmp |= DMAC_CHCTRLB_EVACT(data); + ((Dmac *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_EVACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_EVACT_Msk) >> DMAC_CHCTRLB_EVACT_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_LVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_LVL(mask)) >> DMAC_CHCTRLB_LVL_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_LVL_Msk; + tmp |= DMAC_CHCTRLB_LVL(data); + ((Dmac *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_LVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_LVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_LVL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_LVL_Msk) >> DMAC_CHCTRLB_LVL_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_TRIGSRC(mask)) >> DMAC_CHCTRLB_TRIGSRC_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_TRIGSRC_Msk; + tmp |= DMAC_CHCTRLB_TRIGSRC(data); + ((Dmac *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_TRIGSRC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_TRIGSRC_Msk) >> DMAC_CHCTRLB_TRIGSRC_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_TRIGACT(mask)) >> DMAC_CHCTRLB_TRIGACT_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_TRIGACT_Msk; + tmp |= DMAC_CHCTRLB_TRIGACT(data); + ((Dmac *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_TRIGACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_TRIGACT_Msk) >> DMAC_CHCTRLB_TRIGACT_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_CMD(mask)) >> DMAC_CHCTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_CMD_Msk; + tmp |= DMAC_CHCTRLB_CMD(data); + ((Dmac *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_CMD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_CMD_Msk) >> DMAC_CHCTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_reg(const void *const hw) +{ + return ((Dmac *)hw)->CHCTRLB.reg; +} + +static inline bool hri_dmac_get_CRCSTATUS_CRCBUSY_bit(const void *const hw) +{ + return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) >> DMAC_CRCSTATUS_CRCBUSY_Pos; +} + +static inline void hri_dmac_clear_CRCSTATUS_CRCBUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCBUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CRCSTATUS_CRCZERO_bit(const void *const hw) +{ + return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCZERO) >> DMAC_CRCSTATUS_CRCZERO_Pos; +} + +static inline void hri_dmac_clear_CRCSTATUS_CRCZERO_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCZERO; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcstatus_reg_t hri_dmac_get_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CRCSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_clear_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCSTATUS.reg = mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcstatus_reg_t hri_dmac_read_CRCSTATUS_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCSTATUS.reg; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_VALID_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_VALID; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_VALID_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_VALID) >> DMAC_BTCTRL_VALID_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_VALID_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_VALID; + tmp |= value << DMAC_BTCTRL_VALID_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_VALID_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_VALID; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_VALID_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_VALID; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_SRCINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_SRCINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_SRCINC) >> DMAC_BTCTRL_SRCINC_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_SRCINC; + tmp |= value << DMAC_BTCTRL_SRCINC_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_SRCINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_SRCINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_SRCINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_SRCINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_DSTINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_DSTINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_DSTINC) >> DMAC_BTCTRL_DSTINC_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_DSTINC; + tmp |= value << DMAC_BTCTRL_DSTINC_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_DSTINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_DSTINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_DSTINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_DSTINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_STEPSEL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSEL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_STEPSEL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_STEPSEL) >> DMAC_BTCTRL_STEPSEL_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_STEPSEL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_STEPSEL; + tmp |= value << DMAC_BTCTRL_STEPSEL_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSEL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSEL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSEL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSEL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_EVOSEL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_EVOSEL(mask)) >> DMAC_BTCTRL_EVOSEL_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_EVOSEL_Msk; + tmp |= DMAC_BTCTRL_EVOSEL(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_EVOSEL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_EVOSEL_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_EVOSEL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_EVOSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_EVOSEL_Msk) >> DMAC_BTCTRL_EVOSEL_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BLOCKACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BLOCKACT(mask)) >> DMAC_BTCTRL_BLOCKACT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_BLOCKACT_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_BLOCKACT_Msk; + tmp |= DMAC_BTCTRL_BLOCKACT(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_BLOCKACT_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BLOCKACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_BLOCKACT_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BLOCKACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BLOCKACT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BLOCKACT_Msk) >> DMAC_BTCTRL_BLOCKACT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BEATSIZE(mask)) >> DMAC_BTCTRL_BEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_BEATSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_BEATSIZE_Msk; + tmp |= DMAC_BTCTRL_BEATSIZE(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_BEATSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_BEATSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BEATSIZE_Msk) >> DMAC_BTCTRL_BEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_STEPSIZE(mask)) >> DMAC_BTCTRL_STEPSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_STEPSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_STEPSIZE_Msk; + tmp |= DMAC_BTCTRL_STEPSIZE(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_STEPSIZE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_STEPSIZE_Msk) >> DMAC_BTCTRL_STEPSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_get_BTCTRL_reg(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->BTCTRL.reg; +} + +static inline void hri_dmacdescriptor_set_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg |= DMAC_BTCNT_BTCNT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_BTCNT_bf(const void *const hw, + hri_dmacdescriptor_btcnt_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp = (tmp & DMAC_BTCNT_BTCNT(mask)) >> DMAC_BTCNT_BTCNT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp &= ~DMAC_BTCNT_BTCNT_Msk; + tmp |= DMAC_BTCNT_BTCNT(data); + ((DmacDescriptor *)hw)->BTCNT.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg &= ~DMAC_BTCNT_BTCNT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg ^= DMAC_BTCNT_BTCNT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_BTCNT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp = (tmp & DMAC_BTCNT_BTCNT_Msk) >> DMAC_BTCNT_BTCNT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_reg(const void *const hw, + hri_dmacdescriptor_btcnt_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->BTCNT.reg; +} + +static inline void hri_dmacdescriptor_set_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg |= DMAC_SRCADDR_SRCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t +hri_dmacdescriptor_get_SRCADDR_SRCADDR_bf(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp = (tmp & DMAC_SRCADDR_SRCADDR(mask)) >> DMAC_SRCADDR_SRCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp &= ~DMAC_SRCADDR_SRCADDR_Msk; + tmp |= DMAC_SRCADDR_SRCADDR(data); + ((DmacDescriptor *)hw)->SRCADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg &= ~DMAC_SRCADDR_SRCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg ^= DMAC_SRCADDR_SRCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_SRCADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp = (tmp & DMAC_SRCADDR_SRCADDR_Msk) >> DMAC_SRCADDR_SRCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_get_SRCADDR_reg(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->SRCADDR.reg; +} + +static inline void hri_dmacdescriptor_set_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg |= DMAC_DSTADDR_DSTADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t +hri_dmacdescriptor_get_DSTADDR_DSTADDR_bf(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp = (tmp & DMAC_DSTADDR_DSTADDR(mask)) >> DMAC_DSTADDR_DSTADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp &= ~DMAC_DSTADDR_DSTADDR_Msk; + tmp |= DMAC_DSTADDR_DSTADDR(data); + ((DmacDescriptor *)hw)->DSTADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg &= ~DMAC_DSTADDR_DSTADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg ^= DMAC_DSTADDR_DSTADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_DSTADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp = (tmp & DMAC_DSTADDR_DSTADDR_Msk) >> DMAC_DSTADDR_DSTADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_get_DSTADDR_reg(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->DSTADDR.reg; +} + +static inline void hri_dmacdescriptor_set_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg |= DMAC_DESCADDR_DESCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t +hri_dmacdescriptor_get_DESCADDR_DESCADDR_bf(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp = (tmp & DMAC_DESCADDR_DESCADDR(mask)) >> DMAC_DESCADDR_DESCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp &= ~DMAC_DESCADDR_DESCADDR_Msk; + tmp |= DMAC_DESCADDR_DESCADDR(data); + ((DmacDescriptor *)hw)->DESCADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg &= ~DMAC_DESCADDR_DESCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg ^= DMAC_DESCADDR_DESCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_DESCADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp = (tmp & DMAC_DESCADDR_DESCADDR_Msk) >> DMAC_DESCADDR_DESCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t +hri_dmacdescriptor_get_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->DESCADDR.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_DMAC_L21_H_INCLUDED */ +#endif /* _SAML21_DMAC_COMPONENT_ */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_dsu_l21.h b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_dsu_l21.h new file mode 100644 index 00000000..d9c66b1c --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_dsu_l21.h @@ -0,0 +1,1163 @@ +/** + * \file + * + * \brief SAM DSU + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_DSU_COMPONENT_ +#ifndef _HRI_DSU_L21_H_INCLUDED_ +#define _HRI_DSU_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_DSU_CRITICAL_SECTIONS) +#define DSU_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define DSU_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define DSU_CRITICAL_SECTION_ENTER() +#define DSU_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_dsu_addr_reg_t; +typedef uint32_t hri_dsu_cid0_reg_t; +typedef uint32_t hri_dsu_cid1_reg_t; +typedef uint32_t hri_dsu_cid2_reg_t; +typedef uint32_t hri_dsu_cid3_reg_t; +typedef uint32_t hri_dsu_data_reg_t; +typedef uint32_t hri_dsu_dcc_reg_t; +typedef uint32_t hri_dsu_dcfg_reg_t; +typedef uint32_t hri_dsu_did_reg_t; +typedef uint32_t hri_dsu_end_reg_t; +typedef uint32_t hri_dsu_entry0_reg_t; +typedef uint32_t hri_dsu_entry1_reg_t; +typedef uint32_t hri_dsu_length_reg_t; +typedef uint32_t hri_dsu_memtype_reg_t; +typedef uint32_t hri_dsu_pid0_reg_t; +typedef uint32_t hri_dsu_pid1_reg_t; +typedef uint32_t hri_dsu_pid2_reg_t; +typedef uint32_t hri_dsu_pid3_reg_t; +typedef uint32_t hri_dsu_pid4_reg_t; +typedef uint32_t hri_dsu_pid5_reg_t; +typedef uint32_t hri_dsu_pid6_reg_t; +typedef uint32_t hri_dsu_pid7_reg_t; +typedef uint8_t hri_dsu_ctrl_reg_t; +typedef uint8_t hri_dsu_statusa_reg_t; +typedef uint8_t hri_dsu_statusb_reg_t; + +static inline bool hri_dsu_get_STATUSB_PROT_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_PROT) >> DSU_STATUSB_PROT_Pos; +} + +static inline bool hri_dsu_get_STATUSB_DBGPRES_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DBGPRES) >> DSU_STATUSB_DBGPRES_Pos; +} + +static inline bool hri_dsu_get_STATUSB_DCCD0_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD0) >> DSU_STATUSB_DCCD0_Pos; +} + +static inline bool hri_dsu_get_STATUSB_DCCD1_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD1) >> DSU_STATUSB_DCCD1_Pos; +} + +static inline bool hri_dsu_get_STATUSB_HPE_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_HPE) >> DSU_STATUSB_HPE_Pos; +} + +static inline hri_dsu_statusb_reg_t hri_dsu_get_STATUSB_reg(const void *const hw, hri_dsu_statusb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dsu *)hw)->STATUSB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_statusb_reg_t hri_dsu_read_STATUSB_reg(const void *const hw) +{ + return ((Dsu *)hw)->STATUSB.reg; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_DEVSEL_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL(mask)) >> DSU_DID_DEVSEL_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_DEVSEL_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL_Msk) >> DSU_DID_DEVSEL_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_REVISION_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION(mask)) >> DSU_DID_REVISION_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_REVISION_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION_Msk) >> DSU_DID_REVISION_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_DIE_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DIE(mask)) >> DSU_DID_DIE_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_DIE_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DIE_Msk) >> DSU_DID_DIE_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_SERIES_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES(mask)) >> DSU_DID_SERIES_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_SERIES_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES_Msk) >> DSU_DID_SERIES_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_FAMILY_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY(mask)) >> DSU_DID_FAMILY_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_FAMILY_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY_Msk) >> DSU_DID_FAMILY_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_PROCESSOR_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR(mask)) >> DSU_DID_PROCESSOR_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_PROCESSOR_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR_Msk) >> DSU_DID_PROCESSOR_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_reg(const void *const hw, hri_dsu_did_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DID.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_reg(const void *const hw) +{ + return ((Dsu *)hw)->DID.reg; +} + +static inline bool hri_dsu_get_ENTRY0_EPRES_bit(const void *const hw) +{ + return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_EPRES) >> DSU_ENTRY0_EPRES_Pos; +} + +static inline bool hri_dsu_get_ENTRY0_FMT_bit(const void *const hw) +{ + return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_FMT) >> DSU_ENTRY0_FMT_Pos; +} + +static inline hri_dsu_entry0_reg_t hri_dsu_get_ENTRY0_ADDOFF_bf(const void *const hw, hri_dsu_entry0_reg_t mask) +{ + return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_ADDOFF(mask)) >> DSU_ENTRY0_ADDOFF_Pos; +} + +static inline hri_dsu_entry0_reg_t hri_dsu_read_ENTRY0_ADDOFF_bf(const void *const hw) +{ + return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_ADDOFF_Msk) >> DSU_ENTRY0_ADDOFF_Pos; +} + +static inline hri_dsu_entry0_reg_t hri_dsu_get_ENTRY0_reg(const void *const hw, hri_dsu_entry0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ENTRY0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_entry0_reg_t hri_dsu_read_ENTRY0_reg(const void *const hw) +{ + return ((Dsu *)hw)->ENTRY0.reg; +} + +static inline hri_dsu_entry1_reg_t hri_dsu_get_ENTRY1_reg(const void *const hw, hri_dsu_entry1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ENTRY1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_entry1_reg_t hri_dsu_read_ENTRY1_reg(const void *const hw) +{ + return ((Dsu *)hw)->ENTRY1.reg; +} + +static inline hri_dsu_end_reg_t hri_dsu_get_END_END_bf(const void *const hw, hri_dsu_end_reg_t mask) +{ + return (((Dsu *)hw)->END.reg & DSU_END_END(mask)) >> DSU_END_END_Pos; +} + +static inline hri_dsu_end_reg_t hri_dsu_read_END_END_bf(const void *const hw) +{ + return (((Dsu *)hw)->END.reg & DSU_END_END_Msk) >> DSU_END_END_Pos; +} + +static inline hri_dsu_end_reg_t hri_dsu_get_END_reg(const void *const hw, hri_dsu_end_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->END.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_end_reg_t hri_dsu_read_END_reg(const void *const hw) +{ + return ((Dsu *)hw)->END.reg; +} + +static inline bool hri_dsu_get_MEMTYPE_SMEMP_bit(const void *const hw) +{ + return (((Dsu *)hw)->MEMTYPE.reg & DSU_MEMTYPE_SMEMP) >> DSU_MEMTYPE_SMEMP_Pos; +} + +static inline hri_dsu_memtype_reg_t hri_dsu_get_MEMTYPE_reg(const void *const hw, hri_dsu_memtype_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MEMTYPE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_memtype_reg_t hri_dsu_read_MEMTYPE_reg(const void *const hw) +{ + return ((Dsu *)hw)->MEMTYPE.reg; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_JEPCC_bf(const void *const hw, hri_dsu_pid4_reg_t mask) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC(mask)) >> DSU_PID4_JEPCC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_JEPCC_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC_Msk) >> DSU_PID4_JEPCC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_FKBC_bf(const void *const hw, hri_dsu_pid4_reg_t mask) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC(mask)) >> DSU_PID4_FKBC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_FKBC_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC_Msk) >> DSU_PID4_FKBC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_reg(const void *const hw, hri_dsu_pid4_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID4.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID4.reg; +} + +static inline hri_dsu_pid5_reg_t hri_dsu_get_PID5_reg(const void *const hw, hri_dsu_pid5_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID5.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid5_reg_t hri_dsu_read_PID5_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID5.reg; +} + +static inline hri_dsu_pid6_reg_t hri_dsu_get_PID6_reg(const void *const hw, hri_dsu_pid6_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID6.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid6_reg_t hri_dsu_read_PID6_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID6.reg; +} + +static inline hri_dsu_pid7_reg_t hri_dsu_get_PID7_reg(const void *const hw, hri_dsu_pid7_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID7.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid7_reg_t hri_dsu_read_PID7_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID7.reg; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_PARTNBL_bf(const void *const hw, hri_dsu_pid0_reg_t mask) +{ + return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL(mask)) >> DSU_PID0_PARTNBL_Pos; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_PARTNBL_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL_Msk) >> DSU_PID0_PARTNBL_Pos; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_reg(const void *const hw, hri_dsu_pid0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID0.reg; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_PARTNBH_bf(const void *const hw, hri_dsu_pid1_reg_t mask) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH(mask)) >> DSU_PID1_PARTNBH_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_PARTNBH_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH_Msk) >> DSU_PID1_PARTNBH_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_JEPIDCL_bf(const void *const hw, hri_dsu_pid1_reg_t mask) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL(mask)) >> DSU_PID1_JEPIDCL_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_JEPIDCL_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL_Msk) >> DSU_PID1_JEPIDCL_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_reg(const void *const hw, hri_dsu_pid1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID1.reg; +} + +static inline bool hri_dsu_get_PID2_JEPU_bit(const void *const hw) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPU) >> DSU_PID2_JEPU_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_JEPIDCH_bf(const void *const hw, hri_dsu_pid2_reg_t mask) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH(mask)) >> DSU_PID2_JEPIDCH_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_JEPIDCH_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH_Msk) >> DSU_PID2_JEPIDCH_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_REVISION_bf(const void *const hw, hri_dsu_pid2_reg_t mask) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION(mask)) >> DSU_PID2_REVISION_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_REVISION_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION_Msk) >> DSU_PID2_REVISION_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_reg(const void *const hw, hri_dsu_pid2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID2.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID2.reg; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_CUSMOD_bf(const void *const hw, hri_dsu_pid3_reg_t mask) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD(mask)) >> DSU_PID3_CUSMOD_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_CUSMOD_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD_Msk) >> DSU_PID3_CUSMOD_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_REVAND_bf(const void *const hw, hri_dsu_pid3_reg_t mask) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND(mask)) >> DSU_PID3_REVAND_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_REVAND_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND_Msk) >> DSU_PID3_REVAND_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_reg(const void *const hw, hri_dsu_pid3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID3.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID3.reg; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_PREAMBLEB0_bf(const void *const hw, hri_dsu_cid0_reg_t mask) +{ + return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0(mask)) >> DSU_CID0_PREAMBLEB0_Pos; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_PREAMBLEB0_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0_Msk) >> DSU_CID0_PREAMBLEB0_Pos; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_reg(const void *const hw, hri_dsu_cid0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID0.reg; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_PREAMBLE_bf(const void *const hw, hri_dsu_cid1_reg_t mask) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE(mask)) >> DSU_CID1_PREAMBLE_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_PREAMBLE_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE_Msk) >> DSU_CID1_PREAMBLE_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_CCLASS_bf(const void *const hw, hri_dsu_cid1_reg_t mask) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS(mask)) >> DSU_CID1_CCLASS_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_CCLASS_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS_Msk) >> DSU_CID1_CCLASS_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_reg(const void *const hw, hri_dsu_cid1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID1.reg; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_PREAMBLEB2_bf(const void *const hw, hri_dsu_cid2_reg_t mask) +{ + return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2(mask)) >> DSU_CID2_PREAMBLEB2_Pos; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_PREAMBLEB2_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2_Msk) >> DSU_CID2_PREAMBLEB2_Pos; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_reg(const void *const hw, hri_dsu_cid2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID2.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID2.reg; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_PREAMBLEB3_bf(const void *const hw, hri_dsu_cid3_reg_t mask) +{ + return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3(mask)) >> DSU_CID3_PREAMBLEB3_Pos; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_PREAMBLEB3_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3_Msk) >> DSU_CID3_PREAMBLEB3_Pos; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_reg(const void *const hw, hri_dsu_cid3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID3.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID3.reg; +} + +static inline void hri_dsu_set_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg |= DSU_ADDR_AMOD(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp = (tmp & DSU_ADDR_AMOD(mask)) >> DSU_ADDR_AMOD_Pos; + return tmp; +} + +static inline void hri_dsu_write_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->ADDR.reg; + tmp &= ~DSU_ADDR_AMOD_Msk; + tmp |= DSU_ADDR_AMOD(data); + ((Dsu *)hw)->ADDR.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_AMOD(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_AMOD(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_AMOD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp = (tmp & DSU_ADDR_AMOD_Msk) >> DSU_ADDR_AMOD_Pos; + return tmp; +} + +static inline void hri_dsu_set_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg |= DSU_ADDR_ADDR(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp = (tmp & DSU_ADDR_ADDR(mask)) >> DSU_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_dsu_write_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->ADDR.reg; + tmp &= ~DSU_ADDR_ADDR_Msk; + tmp |= DSU_ADDR_ADDR(data); + ((Dsu *)hw)->ADDR.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_ADDR(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_ADDR(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp = (tmp & DSU_ADDR_ADDR_Msk) >> DSU_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_dsu_set_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_reg(const void *const hw) +{ + return ((Dsu *)hw)->ADDR.reg; +} + +static inline void hri_dsu_set_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg |= DSU_LENGTH_LENGTH(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp = (tmp & DSU_LENGTH_LENGTH(mask)) >> DSU_LENGTH_LENGTH_Pos; + return tmp; +} + +static inline void hri_dsu_write_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp &= ~DSU_LENGTH_LENGTH_Msk; + tmp |= DSU_LENGTH_LENGTH(data); + ((Dsu *)hw)->LENGTH.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg &= ~DSU_LENGTH_LENGTH(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg ^= DSU_LENGTH_LENGTH(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_LENGTH_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp = (tmp & DSU_LENGTH_LENGTH_Msk) >> DSU_LENGTH_LENGTH_Pos; + return tmp; +} + +static inline void hri_dsu_set_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_reg(const void *const hw) +{ + return ((Dsu *)hw)->LENGTH.reg; +} + +static inline void hri_dsu_set_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg |= DSU_DATA_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_get_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DATA.reg; + tmp = (tmp & DSU_DATA_DATA(mask)) >> DSU_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_write_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->DATA.reg; + tmp &= ~DSU_DATA_DATA_Msk; + tmp |= DSU_DATA_DATA(data); + ((Dsu *)hw)->DATA.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg &= ~DSU_DATA_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg ^= DSU_DATA_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_read_DATA_DATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DATA.reg; + tmp = (tmp & DSU_DATA_DATA_Msk) >> DSU_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_set_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_get_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_DATA_reg(const void *const hw, hri_dsu_data_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_read_DATA_reg(const void *const hw) +{ + return ((Dsu *)hw)->DATA.reg; +} + +static inline void hri_dsu_set_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg |= DSU_DCC_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp = (tmp & DSU_DCC_DATA(mask)) >> DSU_DCC_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_write_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp &= ~DSU_DCC_DATA_Msk; + tmp |= DSU_DCC_DATA(data); + ((Dsu *)hw)->DCC[index].reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg &= ~DSU_DCC_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg ^= DSU_DCC_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_DATA_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp = (tmp & DSU_DCC_DATA_Msk) >> DSU_DCC_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_set_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_reg(const void *const hw, uint8_t index) +{ + return ((Dsu *)hw)->DCC[index].reg; +} + +static inline void hri_dsu_set_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCFG[index].reg |= DSU_DCFG_DCFG(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcfg_reg_t hri_dsu_get_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCFG[index].reg; + tmp = (tmp & DSU_DCFG_DCFG(mask)) >> DSU_DCFG_DCFG_Pos; + return tmp; +} + +static inline void hri_dsu_write_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->DCFG[index].reg; + tmp &= ~DSU_DCFG_DCFG_Msk; + tmp |= DSU_DCFG_DCFG(data); + ((Dsu *)hw)->DCFG[index].reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCFG[index].reg &= ~DSU_DCFG_DCFG(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCFG[index].reg ^= DSU_DCFG_DCFG(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcfg_reg_t hri_dsu_read_DCFG_DCFG_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCFG[index].reg; + tmp = (tmp & DSU_DCFG_DCFG_Msk) >> DSU_DCFG_DCFG_Pos; + return tmp; +} + +static inline void hri_dsu_set_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCFG[index].reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcfg_reg_t hri_dsu_get_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCFG[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCFG[index].reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCFG[index].reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCFG[index].reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcfg_reg_t hri_dsu_read_DCFG_reg(const void *const hw, uint8_t index) +{ + return ((Dsu *)hw)->DCFG[index].reg; +} + +static inline bool hri_dsu_get_STATUSA_DONE_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_DONE) >> DSU_STATUSA_DONE_Pos; +} + +static inline void hri_dsu_clear_STATUSA_DONE_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_DONE; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_CRSTEXT_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_CRSTEXT) >> DSU_STATUSA_CRSTEXT_Pos; +} + +static inline void hri_dsu_clear_STATUSA_CRSTEXT_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_CRSTEXT; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_BERR_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_BERR) >> DSU_STATUSA_BERR_Pos; +} + +static inline void hri_dsu_clear_STATUSA_BERR_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_BERR; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_FAIL_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_FAIL) >> DSU_STATUSA_FAIL_Pos; +} + +static inline void hri_dsu_clear_STATUSA_FAIL_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_FAIL; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_PERR_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_PERR) >> DSU_STATUSA_PERR_Pos; +} + +static inline void hri_dsu_clear_STATUSA_PERR_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_PERR; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_statusa_reg_t hri_dsu_get_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dsu *)hw)->STATUSA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_clear_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_statusa_reg_t hri_dsu_read_STATUSA_reg(const void *const hw) +{ + return ((Dsu *)hw)->STATUSA.reg; +} + +static inline void hri_dsu_write_CTRL_reg(const void *const hw, hri_dsu_ctrl_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CTRL.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_DSU_L21_H_INCLUDED */ +#endif /* _SAML21_DSU_COMPONENT_ */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_eic_l21.h b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_eic_l21.h new file mode 100644 index 00000000..9d2ddeaf --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_eic_l21.h @@ -0,0 +1,1463 @@ +/** + * \file + * + * \brief SAM EIC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_EIC_COMPONENT_ +#ifndef _HRI_EIC_L21_H_INCLUDED_ +#define _HRI_EIC_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_EIC_CRITICAL_SECTIONS) +#define EIC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define EIC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define EIC_CRITICAL_SECTION_ENTER() +#define EIC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_eic_nmiflag_reg_t; +typedef uint32_t hri_eic_asynch_reg_t; +typedef uint32_t hri_eic_config_reg_t; +typedef uint32_t hri_eic_evctrl_reg_t; +typedef uint32_t hri_eic_intenset_reg_t; +typedef uint32_t hri_eic_intflag_reg_t; +typedef uint32_t hri_eic_syncbusy_reg_t; +typedef uint8_t hri_eic_ctrla_reg_t; +typedef uint8_t hri_eic_nmictrl_reg_t; + +static inline void hri_eic_wait_for_sync(const void *const hw, hri_eic_syncbusy_reg_t reg) +{ + while (((Eic *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_eic_is_syncing(const void *const hw, hri_eic_syncbusy_reg_t reg) +{ + return ((Eic *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_eic_get_NMIFLAG_NMI_bit(const void *const hw) +{ + return (((Eic *)hw)->NMIFLAG.reg & EIC_NMIFLAG_NMI) >> EIC_NMIFLAG_NMI_Pos; +} + +static inline void hri_eic_clear_NMIFLAG_NMI_bit(const void *const hw) +{ + ((Eic *)hw)->NMIFLAG.reg = EIC_NMIFLAG_NMI; +} + +static inline hri_eic_nmiflag_reg_t hri_eic_get_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Eic *)hw)->NMIFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_nmiflag_reg_t hri_eic_read_NMIFLAG_reg(const void *const hw) +{ + return ((Eic *)hw)->NMIFLAG.reg; +} + +static inline void hri_eic_clear_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask) +{ + ((Eic *)hw)->NMIFLAG.reg = mask; +} + +static inline hri_eic_intflag_reg_t hri_eic_get_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_intflag_reg_t hri_eic_read_INTFLAG_reg(const void *const hw) +{ + return ((Eic *)hw)->INTFLAG.reg; +} + +static inline void hri_eic_clear_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask) +{ + ((Eic *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_eic_set_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) +{ + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(mask); +} + +static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->INTENSET.reg; + tmp = (tmp & EIC_INTENSET_EXTINT(mask)) >> EIC_INTENSET_EXTINT_Pos; + return tmp; +} + +static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_EXTINT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->INTENSET.reg; + tmp = (tmp & EIC_INTENSET_EXTINT_Msk) >> EIC_INTENSET_EXTINT_Pos; + return tmp; +} + +static inline void hri_eic_write_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t data) +{ + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(data); + ((Eic *)hw)->INTENCLR.reg = ~EIC_INTENSET_EXTINT(data); +} + +static inline void hri_eic_clear_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) +{ + ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT(mask); +} + +static inline void hri_eic_set_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) +{ + ((Eic *)hw)->INTENSET.reg = mask; +} + +static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_reg(const void *const hw) +{ + return ((Eic *)hw)->INTENSET.reg; +} + +static inline void hri_eic_write_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t data) +{ + ((Eic *)hw)->INTENSET.reg = data; + ((Eic *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_eic_clear_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) +{ + ((Eic *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_eic_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_SWRST) >> EIC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_eic_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_ENABLE) >> EIC_SYNCBUSY_ENABLE_Pos; +} + +static inline hri_eic_syncbusy_reg_t hri_eic_get_SYNCBUSY_reg(const void *const hw, hri_eic_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_syncbusy_reg_t hri_eic_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Eic *)hw)->SYNCBUSY.reg; +} + +static inline void hri_eic_set_CTRLA_SWRST_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_SWRST; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp = (tmp & EIC_CTRLA_SWRST) >> EIC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_eic_set_CTRLA_ENABLE_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_ENABLE; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp = (tmp & EIC_CTRLA_ENABLE) >> EIC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp &= ~EIC_CTRLA_ENABLE; + tmp |= value << EIC_CTRLA_ENABLE_Pos; + ((Eic *)hw)->CTRLA.reg = tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_ENABLE; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_ENABLE; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CTRLA_CKSEL_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_CKSEL; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CTRLA_CKSEL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->CTRLA.reg; + tmp = (tmp & EIC_CTRLA_CKSEL) >> EIC_CTRLA_CKSEL_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CTRLA_CKSEL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp &= ~EIC_CTRLA_CKSEL; + tmp |= value << EIC_CTRLA_CKSEL_Pos; + ((Eic *)hw)->CTRLA.reg = tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CTRLA_CKSEL_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_CKSEL; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CTRLA_CKSEL_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_CKSEL; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg |= mask; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_ctrla_reg_t hri_eic_get_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg = data; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg &= ~mask; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg ^= mask; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_ctrla_reg_t hri_eic_read_CTRLA_reg(const void *const hw) +{ + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + return ((Eic *)hw)->CTRLA.reg; +} + +static inline void hri_eic_set_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIFILTEN; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp = (tmp & EIC_NMICTRL_NMIFILTEN) >> EIC_NMICTRL_NMIFILTEN_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_NMICTRL_NMIFILTEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp &= ~EIC_NMICTRL_NMIFILTEN; + tmp |= value << EIC_NMICTRL_NMIFILTEN_Pos; + ((Eic *)hw)->NMICTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIFILTEN; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIFILTEN; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_NMICTRL_NMIASYNCH_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIASYNCH; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_NMICTRL_NMIASYNCH_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp = (tmp & EIC_NMICTRL_NMIASYNCH) >> EIC_NMICTRL_NMIASYNCH_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_NMICTRL_NMIASYNCH_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp &= ~EIC_NMICTRL_NMIASYNCH; + tmp |= value << EIC_NMICTRL_NMIASYNCH_Pos; + ((Eic *)hw)->NMICTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_NMICTRL_NMIASYNCH_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIASYNCH; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_NMICTRL_NMIASYNCH_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIASYNCH; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMISENSE(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp = (tmp & EIC_NMICTRL_NMISENSE(mask)) >> EIC_NMICTRL_NMISENSE_Pos; + return tmp; +} + +static inline void hri_eic_write_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t data) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp &= ~EIC_NMICTRL_NMISENSE_Msk; + tmp |= EIC_NMICTRL_NMISENSE(data); + ((Eic *)hw)->NMICTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMISENSE(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMISENSE(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_NMISENSE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp = (tmp & EIC_NMICTRL_NMISENSE_Msk) >> EIC_NMICTRL_NMISENSE_Pos; + return tmp; +} + +static inline void hri_eic_set_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_reg(const void *const hw) +{ + return ((Eic *)hw)->NMICTRL.reg; +} + +static inline void hri_eic_set_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp = (tmp & EIC_EVCTRL_EXTINTEO(mask)) >> EIC_EVCTRL_EXTINTEO_Pos; + return tmp; +} + +static inline void hri_eic_write_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp &= ~EIC_EVCTRL_EXTINTEO_Msk; + tmp |= EIC_EVCTRL_EXTINTEO(data); + ((Eic *)hw)->EVCTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_EXTINTEO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp = (tmp & EIC_EVCTRL_EXTINTEO_Msk) >> EIC_EVCTRL_EXTINTEO_Pos; + return tmp; +} + +static inline void hri_eic_set_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_reg(const void *const hw) +{ + return ((Eic *)hw)->EVCTRL.reg; +} + +static inline void hri_eic_set_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg |= EIC_ASYNCH_ASYNCH(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->ASYNCH.reg; + tmp = (tmp & EIC_ASYNCH_ASYNCH(mask)) >> EIC_ASYNCH_ASYNCH_Pos; + return tmp; +} + +static inline void hri_eic_write_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->ASYNCH.reg; + tmp &= ~EIC_ASYNCH_ASYNCH_Msk; + tmp |= EIC_ASYNCH_ASYNCH(data); + ((Eic *)hw)->ASYNCH.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg &= ~EIC_ASYNCH_ASYNCH(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg ^= EIC_ASYNCH_ASYNCH(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_ASYNCH_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->ASYNCH.reg; + tmp = (tmp & EIC_ASYNCH_ASYNCH_Msk) >> EIC_ASYNCH_ASYNCH_Pos; + return tmp; +} + +static inline void hri_eic_set_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->ASYNCH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_reg(const void *const hw) +{ + return ((Eic *)hw)->ASYNCH.reg; +} + +static inline void hri_eic_set_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN0) >> EIC_CONFIG_FILTEN0_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN0; + tmp |= value << EIC_CONFIG_FILTEN0_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN1) >> EIC_CONFIG_FILTEN1_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN1; + tmp |= value << EIC_CONFIG_FILTEN1_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN2; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN2) >> EIC_CONFIG_FILTEN2_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN2; + tmp |= value << EIC_CONFIG_FILTEN2_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN2; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN2; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN3; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN3) >> EIC_CONFIG_FILTEN3_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN3; + tmp |= value << EIC_CONFIG_FILTEN3_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN3; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN3; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN4; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN4) >> EIC_CONFIG_FILTEN4_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN4; + tmp |= value << EIC_CONFIG_FILTEN4_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN4; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN4; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN5; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN5) >> EIC_CONFIG_FILTEN5_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN5; + tmp |= value << EIC_CONFIG_FILTEN5_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN5; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN5; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN6; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN6) >> EIC_CONFIG_FILTEN6_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN6; + tmp |= value << EIC_CONFIG_FILTEN6_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN6; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN6; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN7; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN7) >> EIC_CONFIG_FILTEN7_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN7; + tmp |= value << EIC_CONFIG_FILTEN7_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN7; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN7; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE0(mask)) >> EIC_CONFIG_SENSE0_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE0_Msk; + tmp |= EIC_CONFIG_SENSE0(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE0_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE0_Msk) >> EIC_CONFIG_SENSE0_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE1(mask)) >> EIC_CONFIG_SENSE1_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE1_Msk; + tmp |= EIC_CONFIG_SENSE1(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE1_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE1_Msk) >> EIC_CONFIG_SENSE1_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE2(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE2(mask)) >> EIC_CONFIG_SENSE2_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE2_Msk; + tmp |= EIC_CONFIG_SENSE2(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE2(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE2(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE2_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE2_Msk) >> EIC_CONFIG_SENSE2_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE3(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE3(mask)) >> EIC_CONFIG_SENSE3_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE3_Msk; + tmp |= EIC_CONFIG_SENSE3(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE3(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE3(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE3_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE3_Msk) >> EIC_CONFIG_SENSE3_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE4(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE4(mask)) >> EIC_CONFIG_SENSE4_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE4_Msk; + tmp |= EIC_CONFIG_SENSE4(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE4(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE4(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE4_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE4_Msk) >> EIC_CONFIG_SENSE4_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE5(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE5(mask)) >> EIC_CONFIG_SENSE5_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE5_Msk; + tmp |= EIC_CONFIG_SENSE5(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE5(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE5(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE5_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE5_Msk) >> EIC_CONFIG_SENSE5_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE6(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE6(mask)) >> EIC_CONFIG_SENSE6_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE6_Msk; + tmp |= EIC_CONFIG_SENSE6(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE6(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE6(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE6_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE6_Msk) >> EIC_CONFIG_SENSE6_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE7(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE7(mask)) >> EIC_CONFIG_SENSE7_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE7_Msk; + tmp |= EIC_CONFIG_SENSE7(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE7(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE7(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE7_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE7_Msk) >> EIC_CONFIG_SENSE7_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_reg(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_reg(const void *const hw, uint8_t index) +{ + return ((Eic *)hw)->CONFIG[index].reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_EIC_L21_H_INCLUDED */ +#endif /* _SAML21_EIC_COMPONENT_ */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_evsys_l21.h b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_evsys_l21.h new file mode 100644 index 00000000..e05d1e32 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_evsys_l21.h @@ -0,0 +1,1725 @@ +/** + * \file + * + * \brief SAM EVSYS + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_EVSYS_COMPONENT_ +#ifndef _HRI_EVSYS_L21_H_INCLUDED_ +#define _HRI_EVSYS_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_EVSYS_CRITICAL_SECTIONS) +#define EVSYS_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define EVSYS_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define EVSYS_CRITICAL_SECTION_ENTER() +#define EVSYS_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_evsys_channel_reg_t; +typedef uint32_t hri_evsys_chstatus_reg_t; +typedef uint32_t hri_evsys_intenset_reg_t; +typedef uint32_t hri_evsys_intflag_reg_t; +typedef uint32_t hri_evsys_swevt_reg_t; +typedef uint32_t hri_evsys_user_reg_t; +typedef uint8_t hri_evsys_ctrla_reg_t; + +static inline bool hri_evsys_get_INTFLAG_OVR0_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR0) >> EVSYS_INTFLAG_OVR0_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR0; +} + +static inline bool hri_evsys_get_INTFLAG_OVR1_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR1) >> EVSYS_INTFLAG_OVR1_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR1; +} + +static inline bool hri_evsys_get_INTFLAG_OVR2_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR2) >> EVSYS_INTFLAG_OVR2_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR2; +} + +static inline bool hri_evsys_get_INTFLAG_OVR3_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR3) >> EVSYS_INTFLAG_OVR3_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR3; +} + +static inline bool hri_evsys_get_INTFLAG_OVR4_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR4) >> EVSYS_INTFLAG_OVR4_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR4; +} + +static inline bool hri_evsys_get_INTFLAG_OVR5_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR5) >> EVSYS_INTFLAG_OVR5_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR5; +} + +static inline bool hri_evsys_get_INTFLAG_OVR6_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR6) >> EVSYS_INTFLAG_OVR6_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR6; +} + +static inline bool hri_evsys_get_INTFLAG_OVR7_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR7) >> EVSYS_INTFLAG_OVR7_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR7; +} + +static inline bool hri_evsys_get_INTFLAG_OVR8_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR8) >> EVSYS_INTFLAG_OVR8_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR8_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR8; +} + +static inline bool hri_evsys_get_INTFLAG_OVR9_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR9) >> EVSYS_INTFLAG_OVR9_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR9_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR9; +} + +static inline bool hri_evsys_get_INTFLAG_OVR10_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR10) >> EVSYS_INTFLAG_OVR10_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR10_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR10; +} + +static inline bool hri_evsys_get_INTFLAG_OVR11_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR11) >> EVSYS_INTFLAG_OVR11_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR11_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR11; +} + +static inline bool hri_evsys_get_INTFLAG_EVD0_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD0) >> EVSYS_INTFLAG_EVD0_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD0; +} + +static inline bool hri_evsys_get_INTFLAG_EVD1_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD1) >> EVSYS_INTFLAG_EVD1_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD1; +} + +static inline bool hri_evsys_get_INTFLAG_EVD2_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD2) >> EVSYS_INTFLAG_EVD2_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD2; +} + +static inline bool hri_evsys_get_INTFLAG_EVD3_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD3) >> EVSYS_INTFLAG_EVD3_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD3; +} + +static inline bool hri_evsys_get_INTFLAG_EVD4_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD4) >> EVSYS_INTFLAG_EVD4_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD4; +} + +static inline bool hri_evsys_get_INTFLAG_EVD5_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD5) >> EVSYS_INTFLAG_EVD5_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD5; +} + +static inline bool hri_evsys_get_INTFLAG_EVD6_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD6) >> EVSYS_INTFLAG_EVD6_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD6; +} + +static inline bool hri_evsys_get_INTFLAG_EVD7_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD7) >> EVSYS_INTFLAG_EVD7_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD7; +} + +static inline bool hri_evsys_get_INTFLAG_EVD8_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD8) >> EVSYS_INTFLAG_EVD8_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD8_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD8; +} + +static inline bool hri_evsys_get_INTFLAG_EVD9_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD9) >> EVSYS_INTFLAG_EVD9_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD9_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD9; +} + +static inline bool hri_evsys_get_INTFLAG_EVD10_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD10) >> EVSYS_INTFLAG_EVD10_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD10_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD10; +} + +static inline bool hri_evsys_get_INTFLAG_EVD11_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD11) >> EVSYS_INTFLAG_EVD11_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD11_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD11; +} + +static inline bool hri_evsys_get_interrupt_OVR0_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR0) >> EVSYS_INTFLAG_OVR0_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR0; +} + +static inline bool hri_evsys_get_interrupt_OVR1_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR1) >> EVSYS_INTFLAG_OVR1_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR1; +} + +static inline bool hri_evsys_get_interrupt_OVR2_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR2) >> EVSYS_INTFLAG_OVR2_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR2; +} + +static inline bool hri_evsys_get_interrupt_OVR3_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR3) >> EVSYS_INTFLAG_OVR3_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR3; +} + +static inline bool hri_evsys_get_interrupt_OVR4_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR4) >> EVSYS_INTFLAG_OVR4_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR4; +} + +static inline bool hri_evsys_get_interrupt_OVR5_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR5) >> EVSYS_INTFLAG_OVR5_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR5; +} + +static inline bool hri_evsys_get_interrupt_OVR6_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR6) >> EVSYS_INTFLAG_OVR6_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR6; +} + +static inline bool hri_evsys_get_interrupt_OVR7_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR7) >> EVSYS_INTFLAG_OVR7_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR7; +} + +static inline bool hri_evsys_get_interrupt_OVR8_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR8) >> EVSYS_INTFLAG_OVR8_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR8_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR8; +} + +static inline bool hri_evsys_get_interrupt_OVR9_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR9) >> EVSYS_INTFLAG_OVR9_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR9_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR9; +} + +static inline bool hri_evsys_get_interrupt_OVR10_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR10) >> EVSYS_INTFLAG_OVR10_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR10_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR10; +} + +static inline bool hri_evsys_get_interrupt_OVR11_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR11) >> EVSYS_INTFLAG_OVR11_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR11_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR11; +} + +static inline bool hri_evsys_get_interrupt_EVD0_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD0) >> EVSYS_INTFLAG_EVD0_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD0; +} + +static inline bool hri_evsys_get_interrupt_EVD1_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD1) >> EVSYS_INTFLAG_EVD1_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD1; +} + +static inline bool hri_evsys_get_interrupt_EVD2_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD2) >> EVSYS_INTFLAG_EVD2_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD2; +} + +static inline bool hri_evsys_get_interrupt_EVD3_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD3) >> EVSYS_INTFLAG_EVD3_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD3; +} + +static inline bool hri_evsys_get_interrupt_EVD4_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD4) >> EVSYS_INTFLAG_EVD4_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD4; +} + +static inline bool hri_evsys_get_interrupt_EVD5_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD5) >> EVSYS_INTFLAG_EVD5_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD5; +} + +static inline bool hri_evsys_get_interrupt_EVD6_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD6) >> EVSYS_INTFLAG_EVD6_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD6; +} + +static inline bool hri_evsys_get_interrupt_EVD7_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD7) >> EVSYS_INTFLAG_EVD7_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD7; +} + +static inline bool hri_evsys_get_interrupt_EVD8_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD8) >> EVSYS_INTFLAG_EVD8_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD8_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD8; +} + +static inline bool hri_evsys_get_interrupt_EVD9_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD9) >> EVSYS_INTFLAG_EVD9_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD9_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD9; +} + +static inline bool hri_evsys_get_interrupt_EVD10_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD10) >> EVSYS_INTFLAG_EVD10_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD10_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD10; +} + +static inline bool hri_evsys_get_interrupt_EVD11_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD11) >> EVSYS_INTFLAG_EVD11_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD11_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD11; +} + +static inline hri_evsys_intflag_reg_t hri_evsys_get_INTFLAG_reg(const void *const hw, hri_evsys_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_intflag_reg_t hri_evsys_read_INTFLAG_reg(const void *const hw) +{ + return ((Evsys *)hw)->INTFLAG.reg; +} + +static inline void hri_evsys_clear_INTFLAG_reg(const void *const hw, hri_evsys_intflag_reg_t mask) +{ + ((Evsys *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_evsys_set_INTEN_OVR0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR0; +} + +static inline bool hri_evsys_get_INTEN_OVR0_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR0) >> EVSYS_INTENSET_OVR0_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR0; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR0; + } +} + +static inline void hri_evsys_clear_INTEN_OVR0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR0; +} + +static inline void hri_evsys_set_INTEN_OVR1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR1; +} + +static inline bool hri_evsys_get_INTEN_OVR1_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR1) >> EVSYS_INTENSET_OVR1_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR1; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR1; + } +} + +static inline void hri_evsys_clear_INTEN_OVR1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR1; +} + +static inline void hri_evsys_set_INTEN_OVR2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR2; +} + +static inline bool hri_evsys_get_INTEN_OVR2_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR2) >> EVSYS_INTENSET_OVR2_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR2; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR2; + } +} + +static inline void hri_evsys_clear_INTEN_OVR2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR2; +} + +static inline void hri_evsys_set_INTEN_OVR3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR3; +} + +static inline bool hri_evsys_get_INTEN_OVR3_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR3) >> EVSYS_INTENSET_OVR3_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR3; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR3; + } +} + +static inline void hri_evsys_clear_INTEN_OVR3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR3; +} + +static inline void hri_evsys_set_INTEN_OVR4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR4; +} + +static inline bool hri_evsys_get_INTEN_OVR4_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR4) >> EVSYS_INTENSET_OVR4_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR4; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR4; + } +} + +static inline void hri_evsys_clear_INTEN_OVR4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR4; +} + +static inline void hri_evsys_set_INTEN_OVR5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR5; +} + +static inline bool hri_evsys_get_INTEN_OVR5_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR5) >> EVSYS_INTENSET_OVR5_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR5; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR5; + } +} + +static inline void hri_evsys_clear_INTEN_OVR5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR5; +} + +static inline void hri_evsys_set_INTEN_OVR6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR6; +} + +static inline bool hri_evsys_get_INTEN_OVR6_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR6) >> EVSYS_INTENSET_OVR6_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR6; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR6; + } +} + +static inline void hri_evsys_clear_INTEN_OVR6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR6; +} + +static inline void hri_evsys_set_INTEN_OVR7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR7; +} + +static inline bool hri_evsys_get_INTEN_OVR7_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR7) >> EVSYS_INTENSET_OVR7_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR7; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR7; + } +} + +static inline void hri_evsys_clear_INTEN_OVR7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR7; +} + +static inline void hri_evsys_set_INTEN_OVR8_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR8; +} + +static inline bool hri_evsys_get_INTEN_OVR8_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR8) >> EVSYS_INTENSET_OVR8_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR8_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR8; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR8; + } +} + +static inline void hri_evsys_clear_INTEN_OVR8_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR8; +} + +static inline void hri_evsys_set_INTEN_OVR9_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR9; +} + +static inline bool hri_evsys_get_INTEN_OVR9_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR9) >> EVSYS_INTENSET_OVR9_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR9_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR9; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR9; + } +} + +static inline void hri_evsys_clear_INTEN_OVR9_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR9; +} + +static inline void hri_evsys_set_INTEN_OVR10_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR10; +} + +static inline bool hri_evsys_get_INTEN_OVR10_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR10) >> EVSYS_INTENSET_OVR10_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR10_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR10; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR10; + } +} + +static inline void hri_evsys_clear_INTEN_OVR10_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR10; +} + +static inline void hri_evsys_set_INTEN_OVR11_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR11; +} + +static inline bool hri_evsys_get_INTEN_OVR11_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR11) >> EVSYS_INTENSET_OVR11_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR11_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR11; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR11; + } +} + +static inline void hri_evsys_clear_INTEN_OVR11_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR11; +} + +static inline void hri_evsys_set_INTEN_EVD0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD0; +} + +static inline bool hri_evsys_get_INTEN_EVD0_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD0) >> EVSYS_INTENSET_EVD0_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD0; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD0; + } +} + +static inline void hri_evsys_clear_INTEN_EVD0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD0; +} + +static inline void hri_evsys_set_INTEN_EVD1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD1; +} + +static inline bool hri_evsys_get_INTEN_EVD1_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD1) >> EVSYS_INTENSET_EVD1_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD1; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD1; + } +} + +static inline void hri_evsys_clear_INTEN_EVD1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD1; +} + +static inline void hri_evsys_set_INTEN_EVD2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD2; +} + +static inline bool hri_evsys_get_INTEN_EVD2_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD2) >> EVSYS_INTENSET_EVD2_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD2; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD2; + } +} + +static inline void hri_evsys_clear_INTEN_EVD2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD2; +} + +static inline void hri_evsys_set_INTEN_EVD3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD3; +} + +static inline bool hri_evsys_get_INTEN_EVD3_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD3) >> EVSYS_INTENSET_EVD3_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD3; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD3; + } +} + +static inline void hri_evsys_clear_INTEN_EVD3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD3; +} + +static inline void hri_evsys_set_INTEN_EVD4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD4; +} + +static inline bool hri_evsys_get_INTEN_EVD4_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD4) >> EVSYS_INTENSET_EVD4_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD4; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD4; + } +} + +static inline void hri_evsys_clear_INTEN_EVD4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD4; +} + +static inline void hri_evsys_set_INTEN_EVD5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD5; +} + +static inline bool hri_evsys_get_INTEN_EVD5_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD5) >> EVSYS_INTENSET_EVD5_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD5; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD5; + } +} + +static inline void hri_evsys_clear_INTEN_EVD5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD5; +} + +static inline void hri_evsys_set_INTEN_EVD6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD6; +} + +static inline bool hri_evsys_get_INTEN_EVD6_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD6) >> EVSYS_INTENSET_EVD6_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD6; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD6; + } +} + +static inline void hri_evsys_clear_INTEN_EVD6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD6; +} + +static inline void hri_evsys_set_INTEN_EVD7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD7; +} + +static inline bool hri_evsys_get_INTEN_EVD7_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD7) >> EVSYS_INTENSET_EVD7_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD7; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD7; + } +} + +static inline void hri_evsys_clear_INTEN_EVD7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD7; +} + +static inline void hri_evsys_set_INTEN_EVD8_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD8; +} + +static inline bool hri_evsys_get_INTEN_EVD8_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD8) >> EVSYS_INTENSET_EVD8_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD8_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD8; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD8; + } +} + +static inline void hri_evsys_clear_INTEN_EVD8_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD8; +} + +static inline void hri_evsys_set_INTEN_EVD9_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD9; +} + +static inline bool hri_evsys_get_INTEN_EVD9_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD9) >> EVSYS_INTENSET_EVD9_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD9_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD9; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD9; + } +} + +static inline void hri_evsys_clear_INTEN_EVD9_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD9; +} + +static inline void hri_evsys_set_INTEN_EVD10_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD10; +} + +static inline bool hri_evsys_get_INTEN_EVD10_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD10) >> EVSYS_INTENSET_EVD10_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD10_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD10; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD10; + } +} + +static inline void hri_evsys_clear_INTEN_EVD10_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD10; +} + +static inline void hri_evsys_set_INTEN_EVD11_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD11; +} + +static inline bool hri_evsys_get_INTEN_EVD11_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD11) >> EVSYS_INTENSET_EVD11_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD11_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD11; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD11; + } +} + +static inline void hri_evsys_clear_INTEN_EVD11_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD11; +} + +static inline void hri_evsys_set_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t mask) +{ + ((Evsys *)hw)->INTENSET.reg = mask; +} + +static inline hri_evsys_intenset_reg_t hri_evsys_get_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_intenset_reg_t hri_evsys_read_INTEN_reg(const void *const hw) +{ + return ((Evsys *)hw)->INTENSET.reg; +} + +static inline void hri_evsys_write_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t data) +{ + ((Evsys *)hw)->INTENSET.reg = data; + ((Evsys *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_evsys_clear_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t mask) +{ + ((Evsys *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY0_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY0) >> EVSYS_CHSTATUS_USRRDY0_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY1_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY1) >> EVSYS_CHSTATUS_USRRDY1_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY2_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY2) >> EVSYS_CHSTATUS_USRRDY2_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY3_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY3) >> EVSYS_CHSTATUS_USRRDY3_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY4_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY4) >> EVSYS_CHSTATUS_USRRDY4_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY5_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY5) >> EVSYS_CHSTATUS_USRRDY5_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY6_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY6) >> EVSYS_CHSTATUS_USRRDY6_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY7_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY7) >> EVSYS_CHSTATUS_USRRDY7_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY8_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY8) >> EVSYS_CHSTATUS_USRRDY8_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY9_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY9) >> EVSYS_CHSTATUS_USRRDY9_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY10_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY10) >> EVSYS_CHSTATUS_USRRDY10_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY11_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY11) >> EVSYS_CHSTATUS_USRRDY11_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY0_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY0) >> EVSYS_CHSTATUS_CHBUSY0_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY1_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY1) >> EVSYS_CHSTATUS_CHBUSY1_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY2_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY2) >> EVSYS_CHSTATUS_CHBUSY2_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY3_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY3) >> EVSYS_CHSTATUS_CHBUSY3_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY4_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY4) >> EVSYS_CHSTATUS_CHBUSY4_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY5_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY5) >> EVSYS_CHSTATUS_CHBUSY5_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY6_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY6) >> EVSYS_CHSTATUS_CHBUSY6_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY7_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY7) >> EVSYS_CHSTATUS_CHBUSY7_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY8_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY8) >> EVSYS_CHSTATUS_CHBUSY8_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY9_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY9) >> EVSYS_CHSTATUS_CHBUSY9_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY10_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY10) >> EVSYS_CHSTATUS_CHBUSY10_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY11_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY11) >> EVSYS_CHSTATUS_CHBUSY11_Pos; +} + +static inline hri_evsys_chstatus_reg_t hri_evsys_get_CHSTATUS_reg(const void *const hw, hri_evsys_chstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_chstatus_reg_t hri_evsys_read_CHSTATUS_reg(const void *const hw) +{ + return ((Evsys *)hw)->CHSTATUS.reg; +} + +static inline void hri_evsys_set_CTRLA_SWRST_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg |= EVSYS_CTRLA_SWRST; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->CTRLA.reg; + tmp = (tmp & EVSYS_CTRLA_SWRST) >> EVSYS_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_set_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_ctrla_reg_t hri_evsys_get_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsys_write_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_ctrla_reg_t hri_evsys_read_CTRLA_reg(const void *const hw) +{ + return ((Evsys *)hw)->CTRLA.reg; +} + +static inline void hri_evsys_set_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg |= EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp = (tmp & EVSYS_CHANNEL_RUNSTDBY) >> EVSYS_CHANNEL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp &= ~EVSYS_CHANNEL_RUNSTDBY; + tmp |= value << EVSYS_CHANNEL_RUNSTDBY_Pos; + ((Evsys *)hw)->CHANNEL[index].reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg &= ~EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg ^= EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg |= EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp = (tmp & EVSYS_CHANNEL_ONDEMAND) >> EVSYS_CHANNEL_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp &= ~EVSYS_CHANNEL_ONDEMAND; + tmp |= value << EVSYS_CHANNEL_ONDEMAND_Pos; + ((Evsys *)hw)->CHANNEL[index].reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg &= ~EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg ^= EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg |= EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp = (tmp & EVSYS_CHANNEL_EVGEN(mask)) >> EVSYS_CHANNEL_EVGEN_Pos; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp &= ~EVSYS_CHANNEL_EVGEN_Msk; + tmp |= EVSYS_CHANNEL_EVGEN(data); + ((Evsys *)hw)->CHANNEL[index].reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg &= ~EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg ^= EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EVGEN_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp = (tmp & EVSYS_CHANNEL_EVGEN_Msk) >> EVSYS_CHANNEL_EVGEN_Pos; + return tmp; +} + +static inline void hri_evsys_set_CHANNEL_PATH_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg |= EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_PATH_bf(const void *const hw, uint8_t index, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp = (tmp & EVSYS_CHANNEL_PATH(mask)) >> EVSYS_CHANNEL_PATH_Pos; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_PATH_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp &= ~EVSYS_CHANNEL_PATH_Msk; + tmp |= EVSYS_CHANNEL_PATH(data); + ((Evsys *)hw)->CHANNEL[index].reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_PATH_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg &= ~EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_PATH_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg ^= EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_PATH_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp = (tmp & EVSYS_CHANNEL_PATH_Msk) >> EVSYS_CHANNEL_PATH_Pos; + return tmp; +} + +static inline void hri_evsys_set_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg |= EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp = (tmp & EVSYS_CHANNEL_EDGSEL(mask)) >> EVSYS_CHANNEL_EDGSEL_Pos; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp &= ~EVSYS_CHANNEL_EDGSEL_Msk; + tmp |= EVSYS_CHANNEL_EDGSEL(data); + ((Evsys *)hw)->CHANNEL[index].reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg &= ~EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg ^= EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp = (tmp & EVSYS_CHANNEL_EDGSEL_Msk) >> EVSYS_CHANNEL_EDGSEL_Pos; + return tmp; +} + +static inline void hri_evsys_set_CHANNEL_reg(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_reg(const void *const hw, uint8_t index, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_reg(const void *const hw, uint8_t index, hri_evsys_channel_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_reg(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_reg(const void *const hw, uint8_t index, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL[index].reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_reg(const void *const hw, uint8_t index) +{ + return ((Evsys *)hw)->CHANNEL[index].reg; +} + +static inline void hri_evsys_set_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg |= EVSYS_USER_CHANNEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_get_USER_CHANNEL_bf(const void *const hw, uint8_t index, + hri_evsys_user_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->USER[index].reg; + tmp = (tmp & EVSYS_USER_CHANNEL(mask)) >> EVSYS_USER_CHANNEL_Pos; + return tmp; +} + +static inline void hri_evsys_write_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->USER[index].reg; + tmp &= ~EVSYS_USER_CHANNEL_Msk; + tmp |= EVSYS_USER_CHANNEL(data); + ((Evsys *)hw)->USER[index].reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg &= ~EVSYS_USER_CHANNEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg ^= EVSYS_USER_CHANNEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_read_USER_CHANNEL_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->USER[index].reg; + tmp = (tmp & EVSYS_USER_CHANNEL_Msk) >> EVSYS_USER_CHANNEL_Pos; + return tmp; +} + +static inline void hri_evsys_set_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_get_USER_reg(const void *const hw, uint8_t index, + hri_evsys_user_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->USER[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsys_write_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_read_USER_reg(const void *const hw, uint8_t index) +{ + return ((Evsys *)hw)->USER[index].reg; +} + +static inline void hri_evsys_write_SWEVT_reg(const void *const hw, hri_evsys_swevt_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->SWEVT.reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_EVSYS_L21_H_INCLUDED */ +#endif /* _SAML21_EVSYS_COMPONENT_ */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_gclk_l21.h b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_gclk_l21.h new file mode 100644 index 00000000..3b5b1e4b --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_gclk_l21.h @@ -0,0 +1,790 @@ +/** + * \file + * + * \brief SAM GCLK + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_GCLK_COMPONENT_ +#ifndef _HRI_GCLK_L21_H_INCLUDED_ +#define _HRI_GCLK_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_GCLK_CRITICAL_SECTIONS) +#define GCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define GCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define GCLK_CRITICAL_SECTION_ENTER() +#define GCLK_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_gclk_genctrl_reg_t; +typedef uint32_t hri_gclk_pchctrl_reg_t; +typedef uint32_t hri_gclk_syncbusy_reg_t; +typedef uint8_t hri_gclk_ctrla_reg_t; + +static inline void hri_gclk_wait_for_sync(const void *const hw, hri_gclk_syncbusy_reg_t reg) +{ + while (((Gclk *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_gclk_is_syncing(const void *const hw, hri_gclk_syncbusy_reg_t reg) +{ + return ((Gclk *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_gclk_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_SWRST) >> GCLK_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL0_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL0) >> GCLK_SYNCBUSY_GENCTRL0_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL1_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL1) >> GCLK_SYNCBUSY_GENCTRL1_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL2_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL2) >> GCLK_SYNCBUSY_GENCTRL2_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL3_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL3) >> GCLK_SYNCBUSY_GENCTRL3_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL4_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL4) >> GCLK_SYNCBUSY_GENCTRL4_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL5_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL5) >> GCLK_SYNCBUSY_GENCTRL5_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL6_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL6) >> GCLK_SYNCBUSY_GENCTRL6_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL7_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL7) >> GCLK_SYNCBUSY_GENCTRL7_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL8_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL8) >> GCLK_SYNCBUSY_GENCTRL8_Pos; +} + +static inline hri_gclk_syncbusy_reg_t hri_gclk_get_SYNCBUSY_reg(const void *const hw, hri_gclk_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gclk_syncbusy_reg_t hri_gclk_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Gclk *)hw)->SYNCBUSY.reg; +} + +static inline void hri_gclk_set_CTRLA_SWRST_bit(const void *const hw) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg |= GCLK_CTRLA_SWRST; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + tmp = ((Gclk *)hw)->CTRLA.reg; + tmp = (tmp & GCLK_CTRLA_SWRST) >> GCLK_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_set_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg |= mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_ctrla_reg_t hri_gclk_get_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + tmp = ((Gclk *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gclk_write_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t data) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg = data; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg &= ~mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg ^= mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_ctrla_reg_t hri_gclk_read_CTRLA_reg(const void *const hw) +{ + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + return ((Gclk *)hw)->CTRLA.reg; +} + +static inline void hri_gclk_set_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_GENEN; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_GENEN) >> GCLK_GENCTRL_GENEN_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_GENEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_GENEN; + tmp |= value << GCLK_GENCTRL_GENEN_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_GENEN; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_GENEN; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_IDC_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_IDC; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_IDC_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_IDC) >> GCLK_GENCTRL_IDC_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_IDC_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_IDC; + tmp |= value << GCLK_GENCTRL_IDC_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_IDC_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_IDC; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_IDC_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_IDC; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_OOV_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OOV; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_OOV_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_OOV) >> GCLK_GENCTRL_OOV_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_OOV_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_OOV; + tmp |= value << GCLK_GENCTRL_OOV_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_OOV_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OOV; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_OOV_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OOV; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_OE_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OE; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_OE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_OE) >> GCLK_GENCTRL_OE_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_OE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_OE; + tmp |= value << GCLK_GENCTRL_OE_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_OE_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OE; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_OE_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OE; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIVSEL; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_DIVSEL) >> GCLK_GENCTRL_DIVSEL_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_DIVSEL; + tmp |= value << GCLK_GENCTRL_DIVSEL_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIVSEL; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIVSEL; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_RUNSTDBY; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_RUNSTDBY) >> GCLK_GENCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_RUNSTDBY; + tmp |= value << GCLK_GENCTRL_RUNSTDBY_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_RUNSTDBY; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_RUNSTDBY; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_SRC(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_SRC_bf(const void *const hw, uint8_t index, + hri_gclk_genctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_SRC(mask)) >> GCLK_GENCTRL_SRC_Pos; + return tmp; +} + +static inline void hri_gclk_write_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_SRC_Msk; + tmp |= GCLK_GENCTRL_SRC(data); + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_SRC(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_SRC(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_SRC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_SRC_Msk) >> GCLK_GENCTRL_SRC_Pos; + return tmp; +} + +static inline void hri_gclk_set_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIV(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_DIV_bf(const void *const hw, uint8_t index, + hri_gclk_genctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_DIV(mask)) >> GCLK_GENCTRL_DIV_Pos; + return tmp; +} + +static inline void hri_gclk_write_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_DIV_Msk; + tmp |= GCLK_GENCTRL_DIV(data); + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIV(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIV(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_DIV_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_DIV_Msk) >> GCLK_GENCTRL_DIV_Pos; + return tmp; +} + +static inline void hri_gclk_set_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_reg(const void *const hw, uint8_t index, + hri_gclk_genctrl_reg_t mask) +{ + uint32_t tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gclk_write_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg = data; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_reg(const void *const hw, uint8_t index) +{ + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + return ((Gclk *)hw)->GENCTRL[index].reg; +} + +static inline void hri_gclk_set_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_CHEN; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp = (tmp & GCLK_PCHCTRL_CHEN) >> GCLK_PCHCTRL_CHEN_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp &= ~GCLK_PCHCTRL_CHEN; + tmp |= value << GCLK_PCHCTRL_CHEN_Pos; + ((Gclk *)hw)->PCHCTRL[index].reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_CHEN; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_CHEN; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_WRTLOCK; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp = (tmp & GCLK_PCHCTRL_WRTLOCK) >> GCLK_PCHCTRL_WRTLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp &= ~GCLK_PCHCTRL_WRTLOCK; + tmp |= value << GCLK_PCHCTRL_WRTLOCK_Pos; + ((Gclk *)hw)->PCHCTRL[index].reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_WRTLOCK; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_WRTLOCK; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_GEN(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, + hri_gclk_pchctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp = (tmp & GCLK_PCHCTRL_GEN(mask)) >> GCLK_PCHCTRL_GEN_Pos; + return tmp; +} + +static inline void hri_gclk_write_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp &= ~GCLK_PCHCTRL_GEN_Msk; + tmp |= GCLK_PCHCTRL_GEN(data); + ((Gclk *)hw)->PCHCTRL[index].reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_GEN(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_GEN(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_GEN_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp = (tmp & GCLK_PCHCTRL_GEN_Msk) >> GCLK_PCHCTRL_GEN_Pos; + return tmp; +} + +static inline void hri_gclk_set_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg |= mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_reg(const void *const hw, uint8_t index, + hri_gclk_pchctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gclk_write_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg = data; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg &= ~mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg ^= mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_reg(const void *const hw, uint8_t index) +{ + return ((Gclk *)hw)->PCHCTRL[index].reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_GCLK_L21_H_INCLUDED */ +#endif /* _SAML21_GCLK_COMPONENT_ */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_l21b.h b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_l21b.h new file mode 100644 index 00000000..35772521 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_l21b.h @@ -0,0 +1,70 @@ +/** + * \file + * + * \brief SAM L21 HRI top-level header file + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HRI_L21_H_INCLUDED_ +#define _HRI_L21_H_INCLUDED_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#endif /* _HRI_L21_H_INCLUDED_ */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_mclk_l21.h b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_mclk_l21.h new file mode 100644 index 00000000..a503db1b --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_mclk_l21.h @@ -0,0 +1,2916 @@ +/** + * \file + * + * \brief SAM MCLK + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_MCLK_COMPONENT_ +#ifndef _HRI_MCLK_L21_H_INCLUDED_ +#define _HRI_MCLK_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_MCLK_CRITICAL_SECTIONS) +#define MCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define MCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define MCLK_CRITICAL_SECTION_ENTER() +#define MCLK_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_mclk_ahbmask_reg_t; +typedef uint32_t hri_mclk_apbamask_reg_t; +typedef uint32_t hri_mclk_apbbmask_reg_t; +typedef uint32_t hri_mclk_apbcmask_reg_t; +typedef uint32_t hri_mclk_apbdmask_reg_t; +typedef uint32_t hri_mclk_apbemask_reg_t; +typedef uint8_t hri_mclk_bupdiv_reg_t; +typedef uint8_t hri_mclk_cpudiv_reg_t; +typedef uint8_t hri_mclk_ctrla_reg_t; +typedef uint8_t hri_mclk_intenset_reg_t; +typedef uint8_t hri_mclk_intflag_reg_t; +typedef uint8_t hri_mclk_lpdiv_reg_t; + +static inline bool hri_mclk_get_INTFLAG_CKRDY_bit(const void *const hw) +{ + return (((Mclk *)hw)->INTFLAG.reg & MCLK_INTFLAG_CKRDY) >> MCLK_INTFLAG_CKRDY_Pos; +} + +static inline void hri_mclk_clear_INTFLAG_CKRDY_bit(const void *const hw) +{ + ((Mclk *)hw)->INTFLAG.reg = MCLK_INTFLAG_CKRDY; +} + +static inline bool hri_mclk_get_interrupt_CKRDY_bit(const void *const hw) +{ + return (((Mclk *)hw)->INTFLAG.reg & MCLK_INTFLAG_CKRDY) >> MCLK_INTFLAG_CKRDY_Pos; +} + +static inline void hri_mclk_clear_interrupt_CKRDY_bit(const void *const hw) +{ + ((Mclk *)hw)->INTFLAG.reg = MCLK_INTFLAG_CKRDY; +} + +static inline hri_mclk_intflag_reg_t hri_mclk_get_INTFLAG_reg(const void *const hw, hri_mclk_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mclk_intflag_reg_t hri_mclk_read_INTFLAG_reg(const void *const hw) +{ + return ((Mclk *)hw)->INTFLAG.reg; +} + +static inline void hri_mclk_clear_INTFLAG_reg(const void *const hw, hri_mclk_intflag_reg_t mask) +{ + ((Mclk *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_mclk_set_INTEN_CKRDY_bit(const void *const hw) +{ + ((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY; +} + +static inline bool hri_mclk_get_INTEN_CKRDY_bit(const void *const hw) +{ + return (((Mclk *)hw)->INTENSET.reg & MCLK_INTENSET_CKRDY) >> MCLK_INTENSET_CKRDY_Pos; +} + +static inline void hri_mclk_write_INTEN_CKRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY; + } else { + ((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY; + } +} + +static inline void hri_mclk_clear_INTEN_CKRDY_bit(const void *const hw) +{ + ((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY; +} + +static inline void hri_mclk_set_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask) +{ + ((Mclk *)hw)->INTENSET.reg = mask; +} + +static inline hri_mclk_intenset_reg_t hri_mclk_get_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mclk_intenset_reg_t hri_mclk_read_INTEN_reg(const void *const hw) +{ + return ((Mclk *)hw)->INTENSET.reg; +} + +static inline void hri_mclk_write_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t data) +{ + ((Mclk *)hw)->INTENSET.reg = data; + ((Mclk *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_mclk_clear_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask) +{ + ((Mclk *)hw)->INTENCLR.reg = mask; +} + +static inline void hri_mclk_set_CTRLA_reg(const void *const hw, hri_mclk_ctrla_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CTRLA.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_ctrla_reg_t hri_mclk_get_CTRLA_reg(const void *const hw, hri_mclk_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_CTRLA_reg(const void *const hw, hri_mclk_ctrla_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CTRLA.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_CTRLA_reg(const void *const hw, hri_mclk_ctrla_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CTRLA.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_CTRLA_reg(const void *const hw, hri_mclk_ctrla_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CTRLA.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_ctrla_reg_t hri_mclk_read_CTRLA_reg(const void *const hw) +{ + return ((Mclk *)hw)->CTRLA.reg; +} + +static inline void hri_mclk_set_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg |= MCLK_CPUDIV_CPUDIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_cpudiv_reg_t hri_mclk_get_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->CPUDIV.reg; + tmp = (tmp & MCLK_CPUDIV_CPUDIV(mask)) >> MCLK_CPUDIV_CPUDIV_Pos; + return tmp; +} + +static inline void hri_mclk_write_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t data) +{ + uint8_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->CPUDIV.reg; + tmp &= ~MCLK_CPUDIV_CPUDIV_Msk; + tmp |= MCLK_CPUDIV_CPUDIV(data); + ((Mclk *)hw)->CPUDIV.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg &= ~MCLK_CPUDIV_CPUDIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg ^= MCLK_CPUDIV_CPUDIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_cpudiv_reg_t hri_mclk_read_CPUDIV_CPUDIV_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->CPUDIV.reg; + tmp = (tmp & MCLK_CPUDIV_CPUDIV_Msk) >> MCLK_CPUDIV_CPUDIV_Pos; + return tmp; +} + +static inline void hri_mclk_set_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_cpudiv_reg_t hri_mclk_get_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->CPUDIV.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_cpudiv_reg_t hri_mclk_read_CPUDIV_reg(const void *const hw) +{ + return ((Mclk *)hw)->CPUDIV.reg; +} + +static inline void hri_mclk_set_LPDIV_LPDIV_bf(const void *const hw, hri_mclk_lpdiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->LPDIV.reg |= MCLK_LPDIV_LPDIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_lpdiv_reg_t hri_mclk_get_LPDIV_LPDIV_bf(const void *const hw, hri_mclk_lpdiv_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->LPDIV.reg; + tmp = (tmp & MCLK_LPDIV_LPDIV(mask)) >> MCLK_LPDIV_LPDIV_Pos; + return tmp; +} + +static inline void hri_mclk_write_LPDIV_LPDIV_bf(const void *const hw, hri_mclk_lpdiv_reg_t data) +{ + uint8_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->LPDIV.reg; + tmp &= ~MCLK_LPDIV_LPDIV_Msk; + tmp |= MCLK_LPDIV_LPDIV(data); + ((Mclk *)hw)->LPDIV.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_LPDIV_LPDIV_bf(const void *const hw, hri_mclk_lpdiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->LPDIV.reg &= ~MCLK_LPDIV_LPDIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_LPDIV_LPDIV_bf(const void *const hw, hri_mclk_lpdiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->LPDIV.reg ^= MCLK_LPDIV_LPDIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_lpdiv_reg_t hri_mclk_read_LPDIV_LPDIV_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->LPDIV.reg; + tmp = (tmp & MCLK_LPDIV_LPDIV_Msk) >> MCLK_LPDIV_LPDIV_Pos; + return tmp; +} + +static inline void hri_mclk_set_LPDIV_reg(const void *const hw, hri_mclk_lpdiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->LPDIV.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_lpdiv_reg_t hri_mclk_get_LPDIV_reg(const void *const hw, hri_mclk_lpdiv_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->LPDIV.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_LPDIV_reg(const void *const hw, hri_mclk_lpdiv_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->LPDIV.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_LPDIV_reg(const void *const hw, hri_mclk_lpdiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->LPDIV.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_LPDIV_reg(const void *const hw, hri_mclk_lpdiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->LPDIV.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_lpdiv_reg_t hri_mclk_read_LPDIV_reg(const void *const hw) +{ + return ((Mclk *)hw)->LPDIV.reg; +} + +static inline void hri_mclk_set_BUPDIV_BUPDIV_bf(const void *const hw, hri_mclk_bupdiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->BUPDIV.reg |= MCLK_BUPDIV_BUPDIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_bupdiv_reg_t hri_mclk_get_BUPDIV_BUPDIV_bf(const void *const hw, hri_mclk_bupdiv_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->BUPDIV.reg; + tmp = (tmp & MCLK_BUPDIV_BUPDIV(mask)) >> MCLK_BUPDIV_BUPDIV_Pos; + return tmp; +} + +static inline void hri_mclk_write_BUPDIV_BUPDIV_bf(const void *const hw, hri_mclk_bupdiv_reg_t data) +{ + uint8_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->BUPDIV.reg; + tmp &= ~MCLK_BUPDIV_BUPDIV_Msk; + tmp |= MCLK_BUPDIV_BUPDIV(data); + ((Mclk *)hw)->BUPDIV.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_BUPDIV_BUPDIV_bf(const void *const hw, hri_mclk_bupdiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->BUPDIV.reg &= ~MCLK_BUPDIV_BUPDIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_BUPDIV_BUPDIV_bf(const void *const hw, hri_mclk_bupdiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->BUPDIV.reg ^= MCLK_BUPDIV_BUPDIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_bupdiv_reg_t hri_mclk_read_BUPDIV_BUPDIV_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->BUPDIV.reg; + tmp = (tmp & MCLK_BUPDIV_BUPDIV_Msk) >> MCLK_BUPDIV_BUPDIV_Pos; + return tmp; +} + +static inline void hri_mclk_set_BUPDIV_reg(const void *const hw, hri_mclk_bupdiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->BUPDIV.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_bupdiv_reg_t hri_mclk_get_BUPDIV_reg(const void *const hw, hri_mclk_bupdiv_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->BUPDIV.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_BUPDIV_reg(const void *const hw, hri_mclk_bupdiv_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->BUPDIV.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_BUPDIV_reg(const void *const hw, hri_mclk_bupdiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->BUPDIV.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_BUPDIV_reg(const void *const hw, hri_mclk_bupdiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->BUPDIV.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_bupdiv_reg_t hri_mclk_read_BUPDIV_reg(const void *const hw) +{ + return ((Mclk *)hw)->BUPDIV.reg; +} + +static inline void hri_mclk_set_AHBMASK_HPB0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HPB0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HPB0) >> MCLK_AHBMASK_HPB0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HPB0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HPB0; + tmp |= value << MCLK_AHBMASK_HPB0_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HPB0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HPB0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HPB1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HPB1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HPB1) >> MCLK_AHBMASK_HPB1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HPB1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HPB1; + tmp |= value << MCLK_AHBMASK_HPB1_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HPB1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HPB1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HPB2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HPB2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HPB2) >> MCLK_AHBMASK_HPB2_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HPB2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HPB2; + tmp |= value << MCLK_AHBMASK_HPB2_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HPB2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HPB2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HPB3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HPB3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HPB3) >> MCLK_AHBMASK_HPB3_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HPB3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HPB3; + tmp |= value << MCLK_AHBMASK_HPB3_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HPB3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HPB3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HPB4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HPB4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HPB4) >> MCLK_AHBMASK_HPB4_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HPB4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HPB4; + tmp |= value << MCLK_AHBMASK_HPB4_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HPB4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HPB4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_DSU_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_DSU) >> MCLK_AHBMASK_DSU_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_DSU_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_DSU; + tmp |= value << MCLK_AHBMASK_DSU_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_NVMCTRL) >> MCLK_AHBMASK_NVMCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_NVMCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_NVMCTRL; + tmp |= value << MCLK_AHBMASK_NVMCTRL_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HSRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HSRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HSRAM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HSRAM) >> MCLK_AHBMASK_HSRAM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HSRAM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HSRAM; + tmp |= value << MCLK_AHBMASK_HSRAM_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HSRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HSRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HSRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HSRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_LPRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_LPRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_LPRAM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_LPRAM) >> MCLK_AHBMASK_LPRAM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_LPRAM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_LPRAM; + tmp |= value << MCLK_AHBMASK_LPRAM_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_LPRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_LPRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_LPRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_LPRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_DMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_DMAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_DMAC) >> MCLK_AHBMASK_DMAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_DMAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_DMAC; + tmp |= value << MCLK_AHBMASK_DMAC_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_DMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_DMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_USB_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_USB) >> MCLK_AHBMASK_USB_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_USB_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_USB; + tmp |= value << MCLK_AHBMASK_USB_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_PAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_PAC) >> MCLK_AHBMASK_PAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_PAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_PAC; + tmp |= value << MCLK_AHBMASK_PAC_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL_PICACHU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_NVMCTRL_PICACHU) >> MCLK_AHBMASK_NVMCTRL_PICACHU_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_NVMCTRL_PICACHU; + tmp |= value << MCLK_AHBMASK_NVMCTRL_PICACHU_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL_PICACHU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL_PICACHU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_L2HBRIDGES_H_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_L2HBRIDGES_H; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_L2HBRIDGES_H_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_L2HBRIDGES_H) >> MCLK_AHBMASK_L2HBRIDGES_H_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_L2HBRIDGES_H_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_L2HBRIDGES_H; + tmp |= value << MCLK_AHBMASK_L2HBRIDGES_H_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_L2HBRIDGES_H_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_L2HBRIDGES_H; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_L2HBRIDGES_H_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_L2HBRIDGES_H; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_H2LBRIDGES_H_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_H2LBRIDGES_H; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_H2LBRIDGES_H_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_H2LBRIDGES_H) >> MCLK_AHBMASK_H2LBRIDGES_H_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_H2LBRIDGES_H_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_H2LBRIDGES_H; + tmp |= value << MCLK_AHBMASK_H2LBRIDGES_H_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_H2LBRIDGES_H_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_H2LBRIDGES_H; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_H2LBRIDGES_H_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_H2LBRIDGES_H; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HSRAM_AHBSETUPKEEPER_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HSRAM_AHBSETUPKEEPER; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HSRAM_AHBSETUPKEEPER_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HSRAM_AHBSETUPKEEPER) >> MCLK_AHBMASK_HSRAM_AHBSETUPKEEPER_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HSRAM_AHBSETUPKEEPER_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HSRAM_AHBSETUPKEEPER; + tmp |= value << MCLK_AHBMASK_HSRAM_AHBSETUPKEEPER_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HSRAM_AHBSETUPKEEPER_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HSRAM_AHBSETUPKEEPER; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HSRAM_AHBSETUPKEEPER_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HSRAM_AHBSETUPKEEPER; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HSRAM_HMATRIXLP2HMCRAMCHSBRIDGE_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HSRAM_HMATRIXLP2HMCRAMCHSBRIDGE; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HSRAM_HMATRIXLP2HMCRAMCHSBRIDGE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HSRAM_HMATRIXLP2HMCRAMCHSBRIDGE) >> MCLK_AHBMASK_HSRAM_HMATRIXLP2HMCRAMCHSBRIDGE_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HSRAM_HMATRIXLP2HMCRAMCHSBRIDGE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HSRAM_HMATRIXLP2HMCRAMCHSBRIDGE; + tmp |= value << MCLK_AHBMASK_HSRAM_HMATRIXLP2HMCRAMCHSBRIDGE_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HSRAM_HMATRIXLP2HMCRAMCHSBRIDGE_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HSRAM_HMATRIXLP2HMCRAMCHSBRIDGE; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HSRAM_HMATRIXLP2HMCRAMCHSBRIDGE_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HSRAM_HMATRIXLP2HMCRAMCHSBRIDGE; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_ahbmask_reg_t hri_mclk_get_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_ahbmask_reg_t hri_mclk_read_AHBMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->AHBMASK.reg; +} + +static inline void hri_mclk_set_APBAMASK_PM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_PM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_PM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_PM) >> MCLK_APBAMASK_PM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_PM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_PM; + tmp |= value << MCLK_APBAMASK_PM_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_PM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_PM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_PM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_PM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_MCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_MCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_MCLK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_MCLK) >> MCLK_APBAMASK_MCLK_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_MCLK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_MCLK; + tmp |= value << MCLK_APBAMASK_MCLK_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_MCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_MCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_MCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_MCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_RSTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RSTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_RSTC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_RSTC) >> MCLK_APBAMASK_RSTC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_RSTC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_RSTC; + tmp |= value << MCLK_APBAMASK_RSTC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_RSTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_RSTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_RSTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_RSTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_OSCCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_OSCCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_OSCCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_OSCCTRL) >> MCLK_APBAMASK_OSCCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_OSCCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_OSCCTRL; + tmp |= value << MCLK_APBAMASK_OSCCTRL_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_OSCCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_OSCCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_OSCCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_OSCCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_OSC32KCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_OSC32KCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_OSC32KCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_OSC32KCTRL) >> MCLK_APBAMASK_OSC32KCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_OSC32KCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_OSC32KCTRL; + tmp |= value << MCLK_APBAMASK_OSC32KCTRL_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_OSC32KCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_OSC32KCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_OSC32KCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_OSC32KCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_SUPC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SUPC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_SUPC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_SUPC) >> MCLK_APBAMASK_SUPC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_SUPC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_SUPC; + tmp |= value << MCLK_APBAMASK_SUPC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_SUPC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SUPC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_SUPC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SUPC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_GCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_GCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_GCLK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_GCLK) >> MCLK_APBAMASK_GCLK_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_GCLK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_GCLK; + tmp |= value << MCLK_APBAMASK_GCLK_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_GCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_GCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_GCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_GCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_WDT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_WDT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_WDT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_WDT) >> MCLK_APBAMASK_WDT_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_WDT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_WDT; + tmp |= value << MCLK_APBAMASK_WDT_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_WDT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_WDT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_WDT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_WDT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_RTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_RTC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_RTC) >> MCLK_APBAMASK_RTC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_RTC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_RTC; + tmp |= value << MCLK_APBAMASK_RTC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_RTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_RTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_RTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_RTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_EIC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_EIC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_EIC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_EIC) >> MCLK_APBAMASK_EIC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_EIC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_EIC; + tmp |= value << MCLK_APBAMASK_EIC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_EIC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_EIC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_EIC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_EIC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_PORT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_PORT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_PORT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_PORT) >> MCLK_APBAMASK_PORT_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_PORT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_PORT; + tmp |= value << MCLK_APBAMASK_PORT_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_PORT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_PORT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_PORT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_PORT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbamask_reg_t hri_mclk_get_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbamask_reg_t hri_mclk_read_APBAMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->APBAMASK.reg; +} + +static inline void hri_mclk_set_APBBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_USB_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_USB) >> MCLK_APBBMASK_USB_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_USB_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_USB; + tmp |= value << MCLK_APBBMASK_USB_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_DSU_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_DSU) >> MCLK_APBBMASK_DSU_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_DSU_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_DSU; + tmp |= value << MCLK_APBBMASK_DSU_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_NVMCTRL) >> MCLK_APBBMASK_NVMCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_NVMCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_NVMCTRL; + tmp |= value << MCLK_APBBMASK_NVMCTRL_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbbmask_reg_t hri_mclk_get_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbbmask_reg_t hri_mclk_read_APBBMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->APBBMASK.reg; +} + +static inline void hri_mclk_set_APBCMASK_SERCOM0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_SERCOM0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_SERCOM0) >> MCLK_APBCMASK_SERCOM0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_SERCOM0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_SERCOM0; + tmp |= value << MCLK_APBCMASK_SERCOM0_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_SERCOM0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_SERCOM0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_SERCOM1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_SERCOM1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_SERCOM1) >> MCLK_APBCMASK_SERCOM1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_SERCOM1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_SERCOM1; + tmp |= value << MCLK_APBCMASK_SERCOM1_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_SERCOM1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_SERCOM1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_SERCOM2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_SERCOM2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_SERCOM2) >> MCLK_APBCMASK_SERCOM2_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_SERCOM2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_SERCOM2; + tmp |= value << MCLK_APBCMASK_SERCOM2_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_SERCOM2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_SERCOM2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_SERCOM3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_SERCOM3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_SERCOM3) >> MCLK_APBCMASK_SERCOM3_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_SERCOM3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_SERCOM3; + tmp |= value << MCLK_APBCMASK_SERCOM3_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_SERCOM3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_SERCOM3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_SERCOM4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_SERCOM4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_SERCOM4) >> MCLK_APBCMASK_SERCOM4_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_SERCOM4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_SERCOM4; + tmp |= value << MCLK_APBCMASK_SERCOM4_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_SERCOM4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_SERCOM4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TCC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TCC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TCC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TCC0) >> MCLK_APBCMASK_TCC0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TCC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TCC0; + tmp |= value << MCLK_APBCMASK_TCC0_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TCC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TCC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TCC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TCC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TCC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TCC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TCC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TCC1) >> MCLK_APBCMASK_TCC1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TCC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TCC1; + tmp |= value << MCLK_APBCMASK_TCC1_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TCC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TCC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TCC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TCC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TCC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TCC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TCC2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TCC2) >> MCLK_APBCMASK_TCC2_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TCC2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TCC2; + tmp |= value << MCLK_APBCMASK_TCC2_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TCC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TCC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TCC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TCC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TC0) >> MCLK_APBCMASK_TC0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TC0; + tmp |= value << MCLK_APBCMASK_TC0_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TC1) >> MCLK_APBCMASK_TC1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TC1; + tmp |= value << MCLK_APBCMASK_TC1_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TC2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TC2) >> MCLK_APBCMASK_TC2_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TC2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TC2; + tmp |= value << MCLK_APBCMASK_TC2_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TC3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TC3) >> MCLK_APBCMASK_TC3_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TC3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TC3; + tmp |= value << MCLK_APBCMASK_TC3_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_DAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_DAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_DAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_DAC) >> MCLK_APBCMASK_DAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_DAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_DAC; + tmp |= value << MCLK_APBCMASK_DAC_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_DAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_DAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_DAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_DAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_AES_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_AES; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_AES_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_AES) >> MCLK_APBCMASK_AES_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_AES_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_AES; + tmp |= value << MCLK_APBCMASK_AES_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_AES_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_AES; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_AES_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_AES; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TRNG_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TRNG; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TRNG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TRNG) >> MCLK_APBCMASK_TRNG_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TRNG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TRNG; + tmp |= value << MCLK_APBCMASK_TRNG_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TRNG_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TRNG; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TRNG_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TRNG; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbcmask_reg_t hri_mclk_get_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbcmask_reg_t hri_mclk_read_APBCMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->APBCMASK.reg; +} + +static inline void hri_mclk_set_APBDMASK_EVSYS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_EVSYS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_EVSYS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_EVSYS) >> MCLK_APBDMASK_EVSYS_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_EVSYS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_EVSYS; + tmp |= value << MCLK_APBDMASK_EVSYS_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_EVSYS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_EVSYS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_EVSYS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_EVSYS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_SERCOM5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_SERCOM5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_SERCOM5) >> MCLK_APBDMASK_SERCOM5_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_SERCOM5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_SERCOM5; + tmp |= value << MCLK_APBDMASK_SERCOM5_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_SERCOM5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_SERCOM5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_TC4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_TC4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_TC4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_TC4) >> MCLK_APBDMASK_TC4_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_TC4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_TC4; + tmp |= value << MCLK_APBDMASK_TC4_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_TC4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_TC4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_TC4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_TC4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_ADC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_ADC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_ADC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_ADC) >> MCLK_APBDMASK_ADC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_ADC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_ADC; + tmp |= value << MCLK_APBDMASK_ADC_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_ADC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_ADC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_ADC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_ADC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_AC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_AC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_AC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_AC) >> MCLK_APBDMASK_AC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_AC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_AC; + tmp |= value << MCLK_APBDMASK_AC_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_AC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_AC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_AC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_AC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_PTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_PTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_PTC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_PTC) >> MCLK_APBDMASK_PTC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_PTC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_PTC; + tmp |= value << MCLK_APBDMASK_PTC_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_PTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_PTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_PTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_PTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_OPAMP_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_OPAMP; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_OPAMP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_OPAMP) >> MCLK_APBDMASK_OPAMP_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_OPAMP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_OPAMP; + tmp |= value << MCLK_APBDMASK_OPAMP_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_OPAMP_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_OPAMP; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_OPAMP_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_OPAMP; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_CCL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_CCL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_CCL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_CCL) >> MCLK_APBDMASK_CCL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_CCL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_CCL; + tmp |= value << MCLK_APBDMASK_CCL_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_CCL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_CCL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_CCL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_CCL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbdmask_reg_t hri_mclk_get_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbdmask_reg_t hri_mclk_read_APBDMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->APBDMASK.reg; +} + +static inline void hri_mclk_set_APBEMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBEMASK.reg |= MCLK_APBEMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBEMASK_PAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBEMASK.reg; + tmp = (tmp & MCLK_APBEMASK_PAC) >> MCLK_APBEMASK_PAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBEMASK_PAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBEMASK.reg; + tmp &= ~MCLK_APBEMASK_PAC; + tmp |= value << MCLK_APBEMASK_PAC_Pos; + ((Mclk *)hw)->APBEMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBEMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBEMASK.reg &= ~MCLK_APBEMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBEMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBEMASK.reg ^= MCLK_APBEMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBEMASK_reg(const void *const hw, hri_mclk_apbemask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBEMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbemask_reg_t hri_mclk_get_APBEMASK_reg(const void *const hw, hri_mclk_apbemask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBEMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_APBEMASK_reg(const void *const hw, hri_mclk_apbemask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBEMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBEMASK_reg(const void *const hw, hri_mclk_apbemask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBEMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBEMASK_reg(const void *const hw, hri_mclk_apbemask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBEMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbemask_reg_t hri_mclk_read_APBEMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->APBEMASK.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_MCLK_L21_H_INCLUDED */ +#endif /* _SAML21_MCLK_COMPONENT_ */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_mtb_l21.h b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_mtb_l21.h new file mode 100644 index 00000000..7d04b825 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_mtb_l21.h @@ -0,0 +1,551 @@ +/** + * \file + * + * \brief SAM MTB + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_MTB_COMPONENT_ +#ifndef _HRI_MTB_L21_H_INCLUDED_ +#define _HRI_MTB_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_MTB_CRITICAL_SECTIONS) +#define MTB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define MTB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define MTB_CRITICAL_SECTION_ENTER() +#define MTB_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_mtb_authstatus_reg_t; +typedef uint32_t hri_mtb_base_reg_t; +typedef uint32_t hri_mtb_cid0_reg_t; +typedef uint32_t hri_mtb_cid1_reg_t; +typedef uint32_t hri_mtb_cid2_reg_t; +typedef uint32_t hri_mtb_cid3_reg_t; +typedef uint32_t hri_mtb_claimset_reg_t; +typedef uint32_t hri_mtb_devarch_reg_t; +typedef uint32_t hri_mtb_devid_reg_t; +typedef uint32_t hri_mtb_devtype_reg_t; +typedef uint32_t hri_mtb_flow_reg_t; +typedef uint32_t hri_mtb_itctrl_reg_t; +typedef uint32_t hri_mtb_lockaccess_reg_t; +typedef uint32_t hri_mtb_lockstatus_reg_t; +typedef uint32_t hri_mtb_master_reg_t; +typedef uint32_t hri_mtb_pid0_reg_t; +typedef uint32_t hri_mtb_pid1_reg_t; +typedef uint32_t hri_mtb_pid2_reg_t; +typedef uint32_t hri_mtb_pid3_reg_t; +typedef uint32_t hri_mtb_pid4_reg_t; +typedef uint32_t hri_mtb_pid5_reg_t; +typedef uint32_t hri_mtb_pid6_reg_t; +typedef uint32_t hri_mtb_pid7_reg_t; +typedef uint32_t hri_mtb_position_reg_t; + +static inline void hri_mtb_set_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t mask) +{ + ((Mtb *)hw)->CLAIMSET.reg = mask; +} + +static inline hri_mtb_claimset_reg_t hri_mtb_get_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->CLAIMSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_claimset_reg_t hri_mtb_read_CLAIM_reg(const void *const hw) +{ + return ((Mtb *)hw)->CLAIMSET.reg; +} + +static inline void hri_mtb_write_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t data) +{ + ((Mtb *)hw)->CLAIMSET.reg = data; + ((Mtb *)hw)->CLAIMCLR.reg = ~data; +} + +static inline void hri_mtb_clear_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t mask) +{ + ((Mtb *)hw)->CLAIMCLR.reg = mask; +} + +static inline hri_mtb_base_reg_t hri_mtb_get_BASE_reg(const void *const hw, hri_mtb_base_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->BASE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_base_reg_t hri_mtb_read_BASE_reg(const void *const hw) +{ + return ((Mtb *)hw)->BASE.reg; +} + +static inline hri_mtb_lockstatus_reg_t hri_mtb_get_LOCKSTATUS_reg(const void *const hw, hri_mtb_lockstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->LOCKSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_lockstatus_reg_t hri_mtb_read_LOCKSTATUS_reg(const void *const hw) +{ + return ((Mtb *)hw)->LOCKSTATUS.reg; +} + +static inline hri_mtb_authstatus_reg_t hri_mtb_get_AUTHSTATUS_reg(const void *const hw, hri_mtb_authstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->AUTHSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_authstatus_reg_t hri_mtb_read_AUTHSTATUS_reg(const void *const hw) +{ + return ((Mtb *)hw)->AUTHSTATUS.reg; +} + +static inline hri_mtb_devarch_reg_t hri_mtb_get_DEVARCH_reg(const void *const hw, hri_mtb_devarch_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->DEVARCH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_devarch_reg_t hri_mtb_read_DEVARCH_reg(const void *const hw) +{ + return ((Mtb *)hw)->DEVARCH.reg; +} + +static inline hri_mtb_devid_reg_t hri_mtb_get_DEVID_reg(const void *const hw, hri_mtb_devid_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->DEVID.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_devid_reg_t hri_mtb_read_DEVID_reg(const void *const hw) +{ + return ((Mtb *)hw)->DEVID.reg; +} + +static inline hri_mtb_devtype_reg_t hri_mtb_get_DEVTYPE_reg(const void *const hw, hri_mtb_devtype_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->DEVTYPE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_devtype_reg_t hri_mtb_read_DEVTYPE_reg(const void *const hw) +{ + return ((Mtb *)hw)->DEVTYPE.reg; +} + +static inline hri_mtb_pid4_reg_t hri_mtb_get_PID4_reg(const void *const hw, hri_mtb_pid4_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID4.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid4_reg_t hri_mtb_read_PID4_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID4.reg; +} + +static inline hri_mtb_pid5_reg_t hri_mtb_get_PID5_reg(const void *const hw, hri_mtb_pid5_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID5.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid5_reg_t hri_mtb_read_PID5_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID5.reg; +} + +static inline hri_mtb_pid6_reg_t hri_mtb_get_PID6_reg(const void *const hw, hri_mtb_pid6_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID6.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid6_reg_t hri_mtb_read_PID6_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID6.reg; +} + +static inline hri_mtb_pid7_reg_t hri_mtb_get_PID7_reg(const void *const hw, hri_mtb_pid7_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID7.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid7_reg_t hri_mtb_read_PID7_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID7.reg; +} + +static inline hri_mtb_pid0_reg_t hri_mtb_get_PID0_reg(const void *const hw, hri_mtb_pid0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid0_reg_t hri_mtb_read_PID0_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID0.reg; +} + +static inline hri_mtb_pid1_reg_t hri_mtb_get_PID1_reg(const void *const hw, hri_mtb_pid1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid1_reg_t hri_mtb_read_PID1_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID1.reg; +} + +static inline hri_mtb_pid2_reg_t hri_mtb_get_PID2_reg(const void *const hw, hri_mtb_pid2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID2.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid2_reg_t hri_mtb_read_PID2_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID2.reg; +} + +static inline hri_mtb_pid3_reg_t hri_mtb_get_PID3_reg(const void *const hw, hri_mtb_pid3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID3.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid3_reg_t hri_mtb_read_PID3_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID3.reg; +} + +static inline hri_mtb_cid0_reg_t hri_mtb_get_CID0_reg(const void *const hw, hri_mtb_cid0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->CID0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_cid0_reg_t hri_mtb_read_CID0_reg(const void *const hw) +{ + return ((Mtb *)hw)->CID0.reg; +} + +static inline hri_mtb_cid1_reg_t hri_mtb_get_CID1_reg(const void *const hw, hri_mtb_cid1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->CID1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_cid1_reg_t hri_mtb_read_CID1_reg(const void *const hw) +{ + return ((Mtb *)hw)->CID1.reg; +} + +static inline hri_mtb_cid2_reg_t hri_mtb_get_CID2_reg(const void *const hw, hri_mtb_cid2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->CID2.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_cid2_reg_t hri_mtb_read_CID2_reg(const void *const hw) +{ + return ((Mtb *)hw)->CID2.reg; +} + +static inline hri_mtb_cid3_reg_t hri_mtb_get_CID3_reg(const void *const hw, hri_mtb_cid3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->CID3.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_cid3_reg_t hri_mtb_read_CID3_reg(const void *const hw) +{ + return ((Mtb *)hw)->CID3.reg; +} + +static inline void hri_mtb_set_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->POSITION.reg |= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_position_reg_t hri_mtb_get_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->POSITION.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mtb_write_POSITION_reg(const void *const hw, hri_mtb_position_reg_t data) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->POSITION.reg = data; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_clear_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->POSITION.reg &= ~mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_toggle_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->POSITION.reg ^= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_position_reg_t hri_mtb_read_POSITION_reg(const void *const hw) +{ + return ((Mtb *)hw)->POSITION.reg; +} + +static inline void hri_mtb_set_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->MASTER.reg |= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_master_reg_t hri_mtb_get_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->MASTER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mtb_write_MASTER_reg(const void *const hw, hri_mtb_master_reg_t data) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->MASTER.reg = data; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_clear_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->MASTER.reg &= ~mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_toggle_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->MASTER.reg ^= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_master_reg_t hri_mtb_read_MASTER_reg(const void *const hw) +{ + return ((Mtb *)hw)->MASTER.reg; +} + +static inline void hri_mtb_set_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->FLOW.reg |= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_flow_reg_t hri_mtb_get_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->FLOW.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mtb_write_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t data) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->FLOW.reg = data; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_clear_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->FLOW.reg &= ~mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_toggle_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->FLOW.reg ^= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_flow_reg_t hri_mtb_read_FLOW_reg(const void *const hw) +{ + return ((Mtb *)hw)->FLOW.reg; +} + +static inline void hri_mtb_set_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->ITCTRL.reg |= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_itctrl_reg_t hri_mtb_get_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->ITCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mtb_write_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t data) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->ITCTRL.reg = data; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_clear_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->ITCTRL.reg &= ~mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_toggle_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->ITCTRL.reg ^= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_itctrl_reg_t hri_mtb_read_ITCTRL_reg(const void *const hw) +{ + return ((Mtb *)hw)->ITCTRL.reg; +} + +static inline void hri_mtb_set_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->LOCKACCESS.reg |= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_lockaccess_reg_t hri_mtb_get_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->LOCKACCESS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mtb_write_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t data) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->LOCKACCESS.reg = data; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_clear_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->LOCKACCESS.reg &= ~mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_toggle_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->LOCKACCESS.reg ^= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_lockaccess_reg_t hri_mtb_read_LOCKACCESS_reg(const void *const hw) +{ + return ((Mtb *)hw)->LOCKACCESS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_MTB_L21_H_INCLUDED */ +#endif /* _SAML21_MTB_COMPONENT_ */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_nvic_l21.h b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_nvic_l21.h new file mode 100644 index 00000000..0cb5e2cd --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_nvic_l21.h @@ -0,0 +1,269 @@ +/** + * \file + * + * \brief SAM NVIC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_NVIC_COMPONENT_ +#ifndef _HRI_NVIC_L21_H_INCLUDED_ +#define _HRI_NVIC_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_NVIC_CRITICAL_SECTIONS) +#define NVIC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define NVIC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define NVIC_CRITICAL_SECTION_ENTER() +#define NVIC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_nvic_icer_reg_t; +typedef uint32_t hri_nvic_icpr_reg_t; +typedef uint32_t hri_nvic_ipr_reg_t; +typedef uint32_t hri_nvic_iser_reg_t; +typedef uint32_t hri_nvic_ispr_reg_t; + +static inline void hri_nvic_set_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ISER.reg |= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_iser_reg_t hri_nvic_get_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->ISER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvic_write_ISER_reg(const void *const hw, hri_nvic_iser_reg_t data) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ISER.reg = data; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ISER.reg &= ~mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_ISER_reg(const void *const hw, hri_nvic_iser_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ISER.reg ^= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_iser_reg_t hri_nvic_read_ISER_reg(const void *const hw) +{ + return ((Nvic *)hw)->ISER.reg; +} + +static inline void hri_nvic_set_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ICER.reg |= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_icer_reg_t hri_nvic_get_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->ICER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvic_write_ICER_reg(const void *const hw, hri_nvic_icer_reg_t data) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ICER.reg = data; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ICER.reg &= ~mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_ICER_reg(const void *const hw, hri_nvic_icer_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ICER.reg ^= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_icer_reg_t hri_nvic_read_ICER_reg(const void *const hw) +{ + return ((Nvic *)hw)->ICER.reg; +} + +static inline void hri_nvic_set_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ISPR.reg |= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_ispr_reg_t hri_nvic_get_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->ISPR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvic_write_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t data) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ISPR.reg = data; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ISPR.reg &= ~mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_ISPR_reg(const void *const hw, hri_nvic_ispr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ISPR.reg ^= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_ispr_reg_t hri_nvic_read_ISPR_reg(const void *const hw) +{ + return ((Nvic *)hw)->ISPR.reg; +} + +static inline void hri_nvic_set_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ICPR.reg |= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_icpr_reg_t hri_nvic_get_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->ICPR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvic_write_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t data) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ICPR.reg = data; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ICPR.reg &= ~mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_ICPR_reg(const void *const hw, hri_nvic_icpr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->ICPR.reg ^= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_icpr_reg_t hri_nvic_read_ICPR_reg(const void *const hw) +{ + return ((Nvic *)hw)->ICPR.reg; +} + +static inline void hri_nvic_set_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->IPR[index].reg |= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_ipr_reg_t hri_nvic_get_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->IPR[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvic_write_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t data) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->IPR[index].reg = data; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->IPR[index].reg &= ~mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_IPR_reg(const void *const hw, uint8_t index, hri_nvic_ipr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->IPR[index].reg ^= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_ipr_reg_t hri_nvic_read_IPR_reg(const void *const hw, uint8_t index) +{ + return ((Nvic *)hw)->IPR[index].reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_NVIC_L21_H_INCLUDED */ +#endif /* _SAML21_NVIC_COMPONENT_ */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_nvmctrl_l21.h b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_nvmctrl_l21.h new file mode 100644 index 00000000..08e70193 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_nvmctrl_l21.h @@ -0,0 +1,1104 @@ +/** + * \file + * + * \brief SAM NVMCTRL + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_NVMCTRL_COMPONENT_ +#ifndef _HRI_NVMCTRL_L21_H_INCLUDED_ +#define _HRI_NVMCTRL_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_NVMCTRL_CRITICAL_SECTIONS) +#define NVMCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define NVMCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define NVMCTRL_CRITICAL_SECTION_ENTER() +#define NVMCTRL_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_nvmctrl_ctrla_reg_t; +typedef uint16_t hri_nvmctrl_lock_reg_t; +typedef uint16_t hri_nvmctrl_status_reg_t; +typedef uint32_t hri_nvmctrl_addr_reg_t; +typedef uint32_t hri_nvmctrl_ctrlb_reg_t; +typedef uint32_t hri_nvmctrl_param_reg_t; +typedef uint8_t hri_nvmctrl_intenset_reg_t; +typedef uint8_t hri_nvmctrl_intflag_reg_t; + +static inline bool hri_nvmctrl_get_INTFLAG_READY_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_READY) >> NVMCTRL_INTFLAG_READY_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_READY_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_READY; +} + +static inline bool hri_nvmctrl_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ERROR) >> NVMCTRL_INTFLAG_ERROR_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ERROR; +} + +static inline bool hri_nvmctrl_get_interrupt_READY_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_READY) >> NVMCTRL_INTFLAG_READY_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_READY_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_READY; +} + +static inline bool hri_nvmctrl_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ERROR) >> NVMCTRL_INTFLAG_ERROR_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ERROR; +} + +static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_get_INTFLAG_reg(const void *const hw, + hri_nvmctrl_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Nvmctrl *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_read_INTFLAG_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->INTFLAG.reg; +} + +static inline void hri_nvmctrl_clear_INTFLAG_reg(const void *const hw, hri_nvmctrl_intflag_reg_t mask) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_nvmctrl_set_INTEN_READY_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_READY; +} + +static inline bool hri_nvmctrl_get_INTEN_READY_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_READY) >> NVMCTRL_INTENSET_READY_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_READY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_READY; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_READY; + } +} + +static inline void hri_nvmctrl_clear_INTEN_READY_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_READY; +} + +static inline void hri_nvmctrl_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ERROR; +} + +static inline bool hri_nvmctrl_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ERROR) >> NVMCTRL_INTENSET_ERROR_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ERROR; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ERROR; + } +} + +static inline void hri_nvmctrl_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ERROR; +} + +static inline void hri_nvmctrl_set_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask) +{ + ((Nvmctrl *)hw)->INTENSET.reg = mask; +} + +static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_get_INTEN_reg(const void *const hw, + hri_nvmctrl_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Nvmctrl *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_read_INTEN_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->INTENSET.reg; +} + +static inline void hri_nvmctrl_write_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t data) +{ + ((Nvmctrl *)hw)->INTENSET.reg = data; + ((Nvmctrl *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_nvmctrl_clear_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = mask; +} + +static inline void hri_nvmctrl_set_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CMD(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_CMD(mask)) >> NVMCTRL_CTRLA_CMD_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_CMD_Msk; + tmp |= NVMCTRL_CTRLA_CMD(data); + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CMD(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CMD(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_CMD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_CMD_Msk) >> NVMCTRL_CTRLA_CMD_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CMDEX(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_CMDEX(mask)) >> NVMCTRL_CTRLA_CMDEX_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_CMDEX_Msk; + tmp |= NVMCTRL_CTRLA_CMDEX(data); + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CMDEX(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CMDEX(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_CMDEX_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_CMDEX_Msk) >> NVMCTRL_CTRLA_CMDEX_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->CTRLA.reg; +} + +static inline void hri_nvmctrl_set_CTRLB_MANW_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_MANW; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_CTRLB_MANW_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_MANW) >> NVMCTRL_CTRLB_MANW_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_CTRLB_MANW_bit(const void *const hw, bool value) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp &= ~NVMCTRL_CTRLB_MANW; + tmp |= value << NVMCTRL_CTRLB_MANW_Pos; + ((Nvmctrl *)hw)->CTRLB.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLB_MANW_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_MANW; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLB_MANW_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_MANW; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLB_FWUP_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_FWUP; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_CTRLB_FWUP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_FWUP) >> NVMCTRL_CTRLB_FWUP_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_CTRLB_FWUP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp &= ~NVMCTRL_CTRLB_FWUP; + tmp |= value << NVMCTRL_CTRLB_FWUP_Pos; + ((Nvmctrl *)hw)->CTRLB.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLB_FWUP_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_FWUP; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLB_FWUP_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_FWUP; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLB_CACHEDIS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_CACHEDIS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_CTRLB_CACHEDIS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_CACHEDIS) >> NVMCTRL_CTRLB_CACHEDIS_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_CTRLB_CACHEDIS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp &= ~NVMCTRL_CTRLB_CACHEDIS; + tmp |= value << NVMCTRL_CTRLB_CACHEDIS_Pos; + ((Nvmctrl *)hw)->CTRLB.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLB_CACHEDIS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_CACHEDIS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLB_CACHEDIS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_CACHEDIS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_RWS(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_RWS(mask)) >> NVMCTRL_CTRLB_RWS_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp &= ~NVMCTRL_CTRLB_RWS_Msk; + tmp |= NVMCTRL_CTRLB_RWS(data); + ((Nvmctrl *)hw)->CTRLB.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_RWS(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_RWS(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_RWS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_RWS_Msk) >> NVMCTRL_CTRLB_RWS_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_SLEEPPRM(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_SLEEPPRM_bf(const void *const hw, + hri_nvmctrl_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_SLEEPPRM(mask)) >> NVMCTRL_CTRLB_SLEEPPRM_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp &= ~NVMCTRL_CTRLB_SLEEPPRM_Msk; + tmp |= NVMCTRL_CTRLB_SLEEPPRM(data); + ((Nvmctrl *)hw)->CTRLB.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_SLEEPPRM(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_SLEEPPRM(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_SLEEPPRM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_SLEEPPRM_Msk) >> NVMCTRL_CTRLB_SLEEPPRM_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_READMODE(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_READMODE_bf(const void *const hw, + hri_nvmctrl_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_READMODE(mask)) >> NVMCTRL_CTRLB_READMODE_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp &= ~NVMCTRL_CTRLB_READMODE_Msk; + tmp |= NVMCTRL_CTRLB_READMODE(data); + ((Nvmctrl *)hw)->CTRLB.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_READMODE(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_READMODE(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_READMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_READMODE_Msk) >> NVMCTRL_CTRLB_READMODE_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->CTRLB.reg; +} + +static inline void hri_nvmctrl_set_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg |= NVMCTRL_PARAM_NVMP(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp = (tmp & NVMCTRL_PARAM_NVMP(mask)) >> NVMCTRL_PARAM_NVMP_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp &= ~NVMCTRL_PARAM_NVMP_Msk; + tmp |= NVMCTRL_PARAM_NVMP(data); + ((Nvmctrl *)hw)->PARAM.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg &= ~NVMCTRL_PARAM_NVMP(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg ^= NVMCTRL_PARAM_NVMP(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_NVMP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp = (tmp & NVMCTRL_PARAM_NVMP_Msk) >> NVMCTRL_PARAM_NVMP_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg |= NVMCTRL_PARAM_PSZ(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp = (tmp & NVMCTRL_PARAM_PSZ(mask)) >> NVMCTRL_PARAM_PSZ_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp &= ~NVMCTRL_PARAM_PSZ_Msk; + tmp |= NVMCTRL_PARAM_PSZ(data); + ((Nvmctrl *)hw)->PARAM.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg &= ~NVMCTRL_PARAM_PSZ(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg ^= NVMCTRL_PARAM_PSZ(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_PSZ_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp = (tmp & NVMCTRL_PARAM_PSZ_Msk) >> NVMCTRL_PARAM_PSZ_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_PARAM_RWWEEP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg |= NVMCTRL_PARAM_RWWEEP(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_RWWEEP_bf(const void *const hw, + hri_nvmctrl_param_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp = (tmp & NVMCTRL_PARAM_RWWEEP(mask)) >> NVMCTRL_PARAM_RWWEEP_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_PARAM_RWWEEP_bf(const void *const hw, hri_nvmctrl_param_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp &= ~NVMCTRL_PARAM_RWWEEP_Msk; + tmp |= NVMCTRL_PARAM_RWWEEP(data); + ((Nvmctrl *)hw)->PARAM.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_PARAM_RWWEEP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg &= ~NVMCTRL_PARAM_RWWEEP(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_PARAM_RWWEEP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg ^= NVMCTRL_PARAM_RWWEEP(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_RWWEEP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp = (tmp & NVMCTRL_PARAM_RWWEEP_Msk) >> NVMCTRL_PARAM_RWWEEP_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->PARAM.reg; +} + +static inline void hri_nvmctrl_set_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg |= NVMCTRL_ADDR_ADDR(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp = (tmp & NVMCTRL_ADDR_ADDR(mask)) >> NVMCTRL_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp &= ~NVMCTRL_ADDR_ADDR_Msk; + tmp |= NVMCTRL_ADDR_ADDR(data); + ((Nvmctrl *)hw)->ADDR.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg &= ~NVMCTRL_ADDR_ADDR(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg ^= NVMCTRL_ADDR_ADDR(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp = (tmp & NVMCTRL_ADDR_ADDR_Msk) >> NVMCTRL_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->ADDR.reg; +} + +static inline void hri_nvmctrl_set_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->LOCK.reg |= NVMCTRL_LOCK_LOCK(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_get_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->LOCK.reg; + tmp = (tmp & NVMCTRL_LOCK_LOCK(mask)) >> NVMCTRL_LOCK_LOCK_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t data) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->LOCK.reg; + tmp &= ~NVMCTRL_LOCK_LOCK_Msk; + tmp |= NVMCTRL_LOCK_LOCK(data); + ((Nvmctrl *)hw)->LOCK.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->LOCK.reg &= ~NVMCTRL_LOCK_LOCK(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->LOCK.reg ^= NVMCTRL_LOCK_LOCK(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_read_LOCK_LOCK_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->LOCK.reg; + tmp = (tmp & NVMCTRL_LOCK_LOCK_Msk) >> NVMCTRL_LOCK_LOCK_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->LOCK.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_get_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->LOCK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->LOCK.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->LOCK.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->LOCK.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_read_LOCK_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->LOCK.reg; +} + +static inline bool hri_nvmctrl_get_STATUS_PRM_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_PRM) >> NVMCTRL_STATUS_PRM_Pos; +} + +static inline void hri_nvmctrl_clear_STATUS_PRM_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_PRM; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_STATUS_LOAD_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_LOAD) >> NVMCTRL_STATUS_LOAD_Pos; +} + +static inline void hri_nvmctrl_clear_STATUS_LOAD_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_LOAD; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_STATUS_PROGE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_PROGE) >> NVMCTRL_STATUS_PROGE_Pos; +} + +static inline void hri_nvmctrl_clear_STATUS_PROGE_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_PROGE; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_STATUS_LOCKE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_LOCKE) >> NVMCTRL_STATUS_LOCKE_Pos; +} + +static inline void hri_nvmctrl_clear_STATUS_LOCKE_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_LOCKE; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_STATUS_NVME_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_NVME) >> NVMCTRL_STATUS_NVME_Pos; +} + +static inline void hri_nvmctrl_clear_STATUS_NVME_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_NVME; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_STATUS_SB_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_SB) >> NVMCTRL_STATUS_SB_Pos; +} + +static inline void hri_nvmctrl_clear_STATUS_SB_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_SB; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_status_reg_t hri_nvmctrl_get_STATUS_reg(const void *const hw, hri_nvmctrl_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_clear_STATUS_reg(const void *const hw, hri_nvmctrl_status_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->STATUS.reg = mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_status_reg_t hri_nvmctrl_read_STATUS_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->STATUS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_NVMCTRL_L21_H_INCLUDED */ +#endif /* _SAML21_NVMCTRL_COMPONENT_ */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_opamp_l21.h b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_opamp_l21.h new file mode 100644 index 00000000..bb45b322 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_opamp_l21.h @@ -0,0 +1,812 @@ +/** + * \file + * + * \brief SAM OPAMP + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_OPAMP_COMPONENT_ +#ifndef _HRI_OPAMP_L21_H_INCLUDED_ +#define _HRI_OPAMP_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_OPAMP_CRITICAL_SECTIONS) +#define OPAMP_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define OPAMP_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define OPAMP_CRITICAL_SECTION_ENTER() +#define OPAMP_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_opamp_opampctrl_reg_t; +typedef uint8_t hri_opamp_ctrla_reg_t; +typedef uint8_t hri_opamp_status_reg_t; + +static inline bool hri_opamp_get_STATUS_READY0_bit(const void *const hw) +{ + return (((Opamp *)hw)->STATUS.reg & OPAMP_STATUS_READY0) >> OPAMP_STATUS_READY0_Pos; +} + +static inline bool hri_opamp_get_STATUS_READY1_bit(const void *const hw) +{ + return (((Opamp *)hw)->STATUS.reg & OPAMP_STATUS_READY1) >> OPAMP_STATUS_READY1_Pos; +} + +static inline bool hri_opamp_get_STATUS_READY2_bit(const void *const hw) +{ + return (((Opamp *)hw)->STATUS.reg & OPAMP_STATUS_READY2) >> OPAMP_STATUS_READY2_Pos; +} + +static inline hri_opamp_status_reg_t hri_opamp_get_STATUS_reg(const void *const hw, hri_opamp_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Opamp *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_opamp_status_reg_t hri_opamp_read_STATUS_reg(const void *const hw) +{ + return ((Opamp *)hw)->STATUS.reg; +} + +static inline void hri_opamp_set_CTRLA_SWRST_bit(const void *const hw) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->CTRLA.reg |= OPAMP_CTRLA_SWRST; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_opamp_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Opamp *)hw)->CTRLA.reg; + tmp = (tmp & OPAMP_CTRLA_SWRST) >> OPAMP_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_opamp_set_CTRLA_ENABLE_bit(const void *const hw) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->CTRLA.reg |= OPAMP_CTRLA_ENABLE; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_opamp_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Opamp *)hw)->CTRLA.reg; + tmp = (tmp & OPAMP_CTRLA_ENABLE) >> OPAMP_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_opamp_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OPAMP_CRITICAL_SECTION_ENTER(); + tmp = ((Opamp *)hw)->CTRLA.reg; + tmp &= ~OPAMP_CTRLA_ENABLE; + tmp |= value << OPAMP_CTRLA_ENABLE_Pos; + ((Opamp *)hw)->CTRLA.reg = tmp; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->CTRLA.reg &= ~OPAMP_CTRLA_ENABLE; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->CTRLA.reg ^= OPAMP_CTRLA_ENABLE; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_set_CTRLA_LPMUX_bit(const void *const hw) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->CTRLA.reg |= OPAMP_CTRLA_LPMUX; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_opamp_get_CTRLA_LPMUX_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Opamp *)hw)->CTRLA.reg; + tmp = (tmp & OPAMP_CTRLA_LPMUX) >> OPAMP_CTRLA_LPMUX_Pos; + return (bool)tmp; +} + +static inline void hri_opamp_write_CTRLA_LPMUX_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OPAMP_CRITICAL_SECTION_ENTER(); + tmp = ((Opamp *)hw)->CTRLA.reg; + tmp &= ~OPAMP_CTRLA_LPMUX; + tmp |= value << OPAMP_CTRLA_LPMUX_Pos; + ((Opamp *)hw)->CTRLA.reg = tmp; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_clear_CTRLA_LPMUX_bit(const void *const hw) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->CTRLA.reg &= ~OPAMP_CTRLA_LPMUX; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_toggle_CTRLA_LPMUX_bit(const void *const hw) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->CTRLA.reg ^= OPAMP_CTRLA_LPMUX; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_set_CTRLA_reg(const void *const hw, hri_opamp_ctrla_reg_t mask) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->CTRLA.reg |= mask; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_opamp_ctrla_reg_t hri_opamp_get_CTRLA_reg(const void *const hw, hri_opamp_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Opamp *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_opamp_write_CTRLA_reg(const void *const hw, hri_opamp_ctrla_reg_t data) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->CTRLA.reg = data; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_clear_CTRLA_reg(const void *const hw, hri_opamp_ctrla_reg_t mask) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->CTRLA.reg &= ~mask; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_toggle_CTRLA_reg(const void *const hw, hri_opamp_ctrla_reg_t mask) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->CTRLA.reg ^= mask; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_opamp_ctrla_reg_t hri_opamp_read_CTRLA_reg(const void *const hw) +{ + return ((Opamp *)hw)->CTRLA.reg; +} + +static inline void hri_opamp_set_OPAMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg |= OPAMP_OPAMPCTRL_ENABLE; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_opamp_get_OPAMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp = (tmp & OPAMP_OPAMPCTRL_ENABLE) >> OPAMP_OPAMPCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_opamp_write_OPAMPCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OPAMP_CRITICAL_SECTION_ENTER(); + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp &= ~OPAMP_OPAMPCTRL_ENABLE; + tmp |= value << OPAMP_OPAMPCTRL_ENABLE_Pos; + ((Opamp *)hw)->OPAMPCTRL[index].reg = tmp; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_clear_OPAMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg &= ~OPAMP_OPAMPCTRL_ENABLE; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_toggle_OPAMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg ^= OPAMP_OPAMPCTRL_ENABLE; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_set_OPAMPCTRL_ANAOUT_bit(const void *const hw, uint8_t index) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg |= OPAMP_OPAMPCTRL_ANAOUT; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_opamp_get_OPAMPCTRL_ANAOUT_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp = (tmp & OPAMP_OPAMPCTRL_ANAOUT) >> OPAMP_OPAMPCTRL_ANAOUT_Pos; + return (bool)tmp; +} + +static inline void hri_opamp_write_OPAMPCTRL_ANAOUT_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OPAMP_CRITICAL_SECTION_ENTER(); + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp &= ~OPAMP_OPAMPCTRL_ANAOUT; + tmp |= value << OPAMP_OPAMPCTRL_ANAOUT_Pos; + ((Opamp *)hw)->OPAMPCTRL[index].reg = tmp; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_clear_OPAMPCTRL_ANAOUT_bit(const void *const hw, uint8_t index) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg &= ~OPAMP_OPAMPCTRL_ANAOUT; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_toggle_OPAMPCTRL_ANAOUT_bit(const void *const hw, uint8_t index) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg ^= OPAMP_OPAMPCTRL_ANAOUT; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_set_OPAMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg |= OPAMP_OPAMPCTRL_RUNSTDBY; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_opamp_get_OPAMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp = (tmp & OPAMP_OPAMPCTRL_RUNSTDBY) >> OPAMP_OPAMPCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_opamp_write_OPAMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OPAMP_CRITICAL_SECTION_ENTER(); + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp &= ~OPAMP_OPAMPCTRL_RUNSTDBY; + tmp |= value << OPAMP_OPAMPCTRL_RUNSTDBY_Pos; + ((Opamp *)hw)->OPAMPCTRL[index].reg = tmp; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_clear_OPAMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg &= ~OPAMP_OPAMPCTRL_RUNSTDBY; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_toggle_OPAMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg ^= OPAMP_OPAMPCTRL_RUNSTDBY; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_set_OPAMPCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg |= OPAMP_OPAMPCTRL_ONDEMAND; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_opamp_get_OPAMPCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp = (tmp & OPAMP_OPAMPCTRL_ONDEMAND) >> OPAMP_OPAMPCTRL_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_opamp_write_OPAMPCTRL_ONDEMAND_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OPAMP_CRITICAL_SECTION_ENTER(); + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp &= ~OPAMP_OPAMPCTRL_ONDEMAND; + tmp |= value << OPAMP_OPAMPCTRL_ONDEMAND_Pos; + ((Opamp *)hw)->OPAMPCTRL[index].reg = tmp; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_clear_OPAMPCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg &= ~OPAMP_OPAMPCTRL_ONDEMAND; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_toggle_OPAMPCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg ^= OPAMP_OPAMPCTRL_ONDEMAND; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_set_OPAMPCTRL_RES2OUT_bit(const void *const hw, uint8_t index) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg |= OPAMP_OPAMPCTRL_RES2OUT; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_opamp_get_OPAMPCTRL_RES2OUT_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp = (tmp & OPAMP_OPAMPCTRL_RES2OUT) >> OPAMP_OPAMPCTRL_RES2OUT_Pos; + return (bool)tmp; +} + +static inline void hri_opamp_write_OPAMPCTRL_RES2OUT_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OPAMP_CRITICAL_SECTION_ENTER(); + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp &= ~OPAMP_OPAMPCTRL_RES2OUT; + tmp |= value << OPAMP_OPAMPCTRL_RES2OUT_Pos; + ((Opamp *)hw)->OPAMPCTRL[index].reg = tmp; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_clear_OPAMPCTRL_RES2OUT_bit(const void *const hw, uint8_t index) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg &= ~OPAMP_OPAMPCTRL_RES2OUT; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_toggle_OPAMPCTRL_RES2OUT_bit(const void *const hw, uint8_t index) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg ^= OPAMP_OPAMPCTRL_RES2OUT; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_set_OPAMPCTRL_RES2VCC_bit(const void *const hw, uint8_t index) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg |= OPAMP_OPAMPCTRL_RES2VCC; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_opamp_get_OPAMPCTRL_RES2VCC_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp = (tmp & OPAMP_OPAMPCTRL_RES2VCC) >> OPAMP_OPAMPCTRL_RES2VCC_Pos; + return (bool)tmp; +} + +static inline void hri_opamp_write_OPAMPCTRL_RES2VCC_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OPAMP_CRITICAL_SECTION_ENTER(); + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp &= ~OPAMP_OPAMPCTRL_RES2VCC; + tmp |= value << OPAMP_OPAMPCTRL_RES2VCC_Pos; + ((Opamp *)hw)->OPAMPCTRL[index].reg = tmp; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_clear_OPAMPCTRL_RES2VCC_bit(const void *const hw, uint8_t index) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg &= ~OPAMP_OPAMPCTRL_RES2VCC; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_toggle_OPAMPCTRL_RES2VCC_bit(const void *const hw, uint8_t index) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg ^= OPAMP_OPAMPCTRL_RES2VCC; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_set_OPAMPCTRL_RES1EN_bit(const void *const hw, uint8_t index) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg |= OPAMP_OPAMPCTRL_RES1EN; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_opamp_get_OPAMPCTRL_RES1EN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp = (tmp & OPAMP_OPAMPCTRL_RES1EN) >> OPAMP_OPAMPCTRL_RES1EN_Pos; + return (bool)tmp; +} + +static inline void hri_opamp_write_OPAMPCTRL_RES1EN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OPAMP_CRITICAL_SECTION_ENTER(); + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp &= ~OPAMP_OPAMPCTRL_RES1EN; + tmp |= value << OPAMP_OPAMPCTRL_RES1EN_Pos; + ((Opamp *)hw)->OPAMPCTRL[index].reg = tmp; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_clear_OPAMPCTRL_RES1EN_bit(const void *const hw, uint8_t index) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg &= ~OPAMP_OPAMPCTRL_RES1EN; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_toggle_OPAMPCTRL_RES1EN_bit(const void *const hw, uint8_t index) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg ^= OPAMP_OPAMPCTRL_RES1EN; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_set_OPAMPCTRL_BIAS_bf(const void *const hw, uint8_t index, hri_opamp_opampctrl_reg_t mask) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg |= OPAMP_OPAMPCTRL_BIAS(mask); + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_opamp_opampctrl_reg_t hri_opamp_get_OPAMPCTRL_BIAS_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp = (tmp & OPAMP_OPAMPCTRL_BIAS(mask)) >> OPAMP_OPAMPCTRL_BIAS_Pos; + return tmp; +} + +static inline void hri_opamp_write_OPAMPCTRL_BIAS_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t data) +{ + uint32_t tmp; + OPAMP_CRITICAL_SECTION_ENTER(); + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp &= ~OPAMP_OPAMPCTRL_BIAS_Msk; + tmp |= OPAMP_OPAMPCTRL_BIAS(data); + ((Opamp *)hw)->OPAMPCTRL[index].reg = tmp; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_clear_OPAMPCTRL_BIAS_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t mask) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg &= ~OPAMP_OPAMPCTRL_BIAS(mask); + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_toggle_OPAMPCTRL_BIAS_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t mask) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg ^= OPAMP_OPAMPCTRL_BIAS(mask); + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_opamp_opampctrl_reg_t hri_opamp_read_OPAMPCTRL_BIAS_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp = (tmp & OPAMP_OPAMPCTRL_BIAS_Msk) >> OPAMP_OPAMPCTRL_BIAS_Pos; + return tmp; +} + +static inline void hri_opamp_set_OPAMPCTRL_RES1MUX_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t mask) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg |= OPAMP_OPAMPCTRL_RES1MUX(mask); + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_opamp_opampctrl_reg_t hri_opamp_get_OPAMPCTRL_RES1MUX_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp = (tmp & OPAMP_OPAMPCTRL_RES1MUX(mask)) >> OPAMP_OPAMPCTRL_RES1MUX_Pos; + return tmp; +} + +static inline void hri_opamp_write_OPAMPCTRL_RES1MUX_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t data) +{ + uint32_t tmp; + OPAMP_CRITICAL_SECTION_ENTER(); + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp &= ~OPAMP_OPAMPCTRL_RES1MUX_Msk; + tmp |= OPAMP_OPAMPCTRL_RES1MUX(data); + ((Opamp *)hw)->OPAMPCTRL[index].reg = tmp; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_clear_OPAMPCTRL_RES1MUX_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t mask) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg &= ~OPAMP_OPAMPCTRL_RES1MUX(mask); + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_toggle_OPAMPCTRL_RES1MUX_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t mask) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg ^= OPAMP_OPAMPCTRL_RES1MUX(mask); + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_opamp_opampctrl_reg_t hri_opamp_read_OPAMPCTRL_RES1MUX_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp = (tmp & OPAMP_OPAMPCTRL_RES1MUX_Msk) >> OPAMP_OPAMPCTRL_RES1MUX_Pos; + return tmp; +} + +static inline void hri_opamp_set_OPAMPCTRL_POTMUX_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t mask) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg |= OPAMP_OPAMPCTRL_POTMUX(mask); + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_opamp_opampctrl_reg_t hri_opamp_get_OPAMPCTRL_POTMUX_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp = (tmp & OPAMP_OPAMPCTRL_POTMUX(mask)) >> OPAMP_OPAMPCTRL_POTMUX_Pos; + return tmp; +} + +static inline void hri_opamp_write_OPAMPCTRL_POTMUX_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t data) +{ + uint32_t tmp; + OPAMP_CRITICAL_SECTION_ENTER(); + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp &= ~OPAMP_OPAMPCTRL_POTMUX_Msk; + tmp |= OPAMP_OPAMPCTRL_POTMUX(data); + ((Opamp *)hw)->OPAMPCTRL[index].reg = tmp; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_clear_OPAMPCTRL_POTMUX_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t mask) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg &= ~OPAMP_OPAMPCTRL_POTMUX(mask); + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_toggle_OPAMPCTRL_POTMUX_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t mask) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg ^= OPAMP_OPAMPCTRL_POTMUX(mask); + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_opamp_opampctrl_reg_t hri_opamp_read_OPAMPCTRL_POTMUX_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp = (tmp & OPAMP_OPAMPCTRL_POTMUX_Msk) >> OPAMP_OPAMPCTRL_POTMUX_Pos; + return tmp; +} + +static inline void hri_opamp_set_OPAMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t mask) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg |= OPAMP_OPAMPCTRL_MUXPOS(mask); + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_opamp_opampctrl_reg_t hri_opamp_get_OPAMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp = (tmp & OPAMP_OPAMPCTRL_MUXPOS(mask)) >> OPAMP_OPAMPCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_opamp_write_OPAMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t data) +{ + uint32_t tmp; + OPAMP_CRITICAL_SECTION_ENTER(); + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp &= ~OPAMP_OPAMPCTRL_MUXPOS_Msk; + tmp |= OPAMP_OPAMPCTRL_MUXPOS(data); + ((Opamp *)hw)->OPAMPCTRL[index].reg = tmp; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_clear_OPAMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t mask) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg &= ~OPAMP_OPAMPCTRL_MUXPOS(mask); + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_toggle_OPAMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t mask) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg ^= OPAMP_OPAMPCTRL_MUXPOS(mask); + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_opamp_opampctrl_reg_t hri_opamp_read_OPAMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp = (tmp & OPAMP_OPAMPCTRL_MUXPOS_Msk) >> OPAMP_OPAMPCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_opamp_set_OPAMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t mask) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg |= OPAMP_OPAMPCTRL_MUXNEG(mask); + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_opamp_opampctrl_reg_t hri_opamp_get_OPAMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp = (tmp & OPAMP_OPAMPCTRL_MUXNEG(mask)) >> OPAMP_OPAMPCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_opamp_write_OPAMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t data) +{ + uint32_t tmp; + OPAMP_CRITICAL_SECTION_ENTER(); + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp &= ~OPAMP_OPAMPCTRL_MUXNEG_Msk; + tmp |= OPAMP_OPAMPCTRL_MUXNEG(data); + ((Opamp *)hw)->OPAMPCTRL[index].reg = tmp; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_clear_OPAMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t mask) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg &= ~OPAMP_OPAMPCTRL_MUXNEG(mask); + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_toggle_OPAMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t mask) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg ^= OPAMP_OPAMPCTRL_MUXNEG(mask); + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_opamp_opampctrl_reg_t hri_opamp_read_OPAMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp = (tmp & OPAMP_OPAMPCTRL_MUXNEG_Msk) >> OPAMP_OPAMPCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_opamp_set_OPAMPCTRL_reg(const void *const hw, uint8_t index, hri_opamp_opampctrl_reg_t mask) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg |= mask; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_opamp_opampctrl_reg_t hri_opamp_get_OPAMPCTRL_reg(const void *const hw, uint8_t index, + hri_opamp_opampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Opamp *)hw)->OPAMPCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_opamp_write_OPAMPCTRL_reg(const void *const hw, uint8_t index, hri_opamp_opampctrl_reg_t data) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg = data; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_clear_OPAMPCTRL_reg(const void *const hw, uint8_t index, hri_opamp_opampctrl_reg_t mask) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg &= ~mask; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_opamp_toggle_OPAMPCTRL_reg(const void *const hw, uint8_t index, hri_opamp_opampctrl_reg_t mask) +{ + OPAMP_CRITICAL_SECTION_ENTER(); + ((Opamp *)hw)->OPAMPCTRL[index].reg ^= mask; + OPAMP_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_opamp_opampctrl_reg_t hri_opamp_read_OPAMPCTRL_reg(const void *const hw, uint8_t index) +{ + return ((Opamp *)hw)->OPAMPCTRL[index].reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_OPAMP_L21_H_INCLUDED */ +#endif /* _SAML21_OPAMP_COMPONENT_ */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_osc32kctrl_l21.h b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_osc32kctrl_l21.h new file mode 100644 index 00000000..9aa600af --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_osc32kctrl_l21.h @@ -0,0 +1,1200 @@ +/** + * \file + * + * \brief SAM OSC32KCTRL + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_OSC32KCTRL_COMPONENT_ +#ifndef _HRI_OSC32KCTRL_L21_H_INCLUDED_ +#define _HRI_OSC32KCTRL_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_OSC32KCTRL_CRITICAL_SECTIONS) +#define OSC32KCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define OSC32KCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define OSC32KCTRL_CRITICAL_SECTION_ENTER() +#define OSC32KCTRL_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_osc32kctrl_intenset_reg_t; +typedef uint32_t hri_osc32kctrl_intflag_reg_t; +typedef uint32_t hri_osc32kctrl_osc32k_reg_t; +typedef uint32_t hri_osc32kctrl_osculp32k_reg_t; +typedef uint32_t hri_osc32kctrl_rtcctrl_reg_t; +typedef uint32_t hri_osc32kctrl_status_reg_t; +typedef uint32_t hri_osc32kctrl_xosc32k_reg_t; + +static inline bool hri_osc32kctrl_get_INTFLAG_XOSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KRDY) >> OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos; +} + +static inline void hri_osc32kctrl_clear_INTFLAG_XOSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY; +} + +static inline bool hri_osc32kctrl_get_INTFLAG_OSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_OSC32KRDY) >> OSC32KCTRL_INTFLAG_OSC32KRDY_Pos; +} + +static inline void hri_osc32kctrl_clear_INTFLAG_OSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_OSC32KRDY; +} + +static inline bool hri_osc32kctrl_get_interrupt_XOSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KRDY) >> OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos; +} + +static inline void hri_osc32kctrl_clear_interrupt_XOSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY; +} + +static inline bool hri_osc32kctrl_get_interrupt_OSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_OSC32KRDY) >> OSC32KCTRL_INTFLAG_OSC32KRDY_Pos; +} + +static inline void hri_osc32kctrl_clear_interrupt_OSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_OSC32KRDY; +} + +static inline hri_osc32kctrl_intflag_reg_t hri_osc32kctrl_get_INTFLAG_reg(const void *const hw, + hri_osc32kctrl_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_osc32kctrl_intflag_reg_t hri_osc32kctrl_read_INTFLAG_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->INTFLAG.reg; +} + +static inline void hri_osc32kctrl_clear_INTFLAG_reg(const void *const hw, hri_osc32kctrl_intflag_reg_t mask) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_osc32kctrl_set_INTEN_XOSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; +} + +static inline bool hri_osc32kctrl_get_INTEN_XOSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_XOSC32KRDY) >> OSC32KCTRL_INTENSET_XOSC32KRDY_Pos; +} + +static inline void hri_osc32kctrl_write_INTEN_XOSC32KRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; + } else { + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; + } +} + +static inline void hri_osc32kctrl_clear_INTEN_XOSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; +} + +static inline void hri_osc32kctrl_set_INTEN_OSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_OSC32KRDY; +} + +static inline bool hri_osc32kctrl_get_INTEN_OSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_OSC32KRDY) >> OSC32KCTRL_INTENSET_OSC32KRDY_Pos; +} + +static inline void hri_osc32kctrl_write_INTEN_OSC32KRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_OSC32KRDY; + } else { + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_OSC32KRDY; + } +} + +static inline void hri_osc32kctrl_clear_INTEN_OSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_OSC32KRDY; +} + +static inline void hri_osc32kctrl_set_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t mask) +{ + ((Osc32kctrl *)hw)->INTENSET.reg = mask; +} + +static inline hri_osc32kctrl_intenset_reg_t hri_osc32kctrl_get_INTEN_reg(const void *const hw, + hri_osc32kctrl_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_osc32kctrl_intenset_reg_t hri_osc32kctrl_read_INTEN_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->INTENSET.reg; +} + +static inline void hri_osc32kctrl_write_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t data) +{ + ((Osc32kctrl *)hw)->INTENSET.reg = data; + ((Osc32kctrl *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_osc32kctrl_clear_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t mask) +{ + ((Osc32kctrl *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_osc32kctrl_get_STATUS_XOSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KRDY) >> OSC32KCTRL_STATUS_XOSC32KRDY_Pos; +} + +static inline bool hri_osc32kctrl_get_STATUS_OSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_OSC32KRDY) >> OSC32KCTRL_STATUS_OSC32KRDY_Pos; +} + +static inline hri_osc32kctrl_status_reg_t hri_osc32kctrl_get_STATUS_reg(const void *const hw, + hri_osc32kctrl_status_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_osc32kctrl_status_reg_t hri_osc32kctrl_read_STATUS_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->STATUS.reg; +} + +static inline void hri_osc32kctrl_set_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg |= OSC32KCTRL_RTCCTRL_RTCSEL(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_get_RTCCTRL_RTCSEL_bf(const void *const hw, + hri_osc32kctrl_rtcctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; + tmp = (tmp & OSC32KCTRL_RTCCTRL_RTCSEL(mask)) >> OSC32KCTRL_RTCCTRL_RTCSEL_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_write_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t data) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; + tmp &= ~OSC32KCTRL_RTCCTRL_RTCSEL_Msk; + tmp |= OSC32KCTRL_RTCCTRL_RTCSEL(data); + ((Osc32kctrl *)hw)->RTCCTRL.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg &= ~OSC32KCTRL_RTCCTRL_RTCSEL(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg ^= OSC32KCTRL_RTCCTRL_RTCSEL(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_read_RTCCTRL_RTCSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; + tmp = (tmp & OSC32KCTRL_RTCCTRL_RTCSEL_Msk) >> OSC32KCTRL_RTCCTRL_RTCSEL_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_set_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_get_RTCCTRL_reg(const void *const hw, + hri_osc32kctrl_rtcctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_read_RTCCTRL_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->RTCCTRL.reg; +} + +static inline void hri_osc32kctrl_set_XOSC32K_ENABLE_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ENABLE; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_ENABLE) >> OSC32KCTRL_XOSC32K_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_ENABLE; + tmp |= value << OSC32KCTRL_XOSC32K_ENABLE_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_ENABLE_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ENABLE; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_ENABLE_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_ENABLE; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_XTALEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_XTALEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_XTALEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_XTALEN) >> OSC32KCTRL_XOSC32K_XTALEN_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_XTALEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_XTALEN; + tmp |= value << OSC32KCTRL_XOSC32K_XTALEN_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_XTALEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_XTALEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_XTALEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_XTALEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_EN32K_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_EN32K) >> OSC32KCTRL_XOSC32K_EN32K_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_EN32K_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_EN32K; + tmp |= value << OSC32KCTRL_XOSC32K_EN32K_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_EN1K_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_EN1K) >> OSC32KCTRL_XOSC32K_EN1K_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_EN1K_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_EN1K; + tmp |= value << OSC32KCTRL_XOSC32K_EN1K_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_RUNSTDBY; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_RUNSTDBY) >> OSC32KCTRL_XOSC32K_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_RUNSTDBY; + tmp |= value << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_RUNSTDBY; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_RUNSTDBY; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ONDEMAND; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_ONDEMAND) >> OSC32KCTRL_XOSC32K_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_ONDEMAND_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_ONDEMAND; + tmp |= value << OSC32KCTRL_XOSC32K_ONDEMAND_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ONDEMAND; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_ONDEMAND; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_WRTLOCK) >> OSC32KCTRL_XOSC32K_WRTLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_WRTLOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_WRTLOCK; + tmp |= value << OSC32KCTRL_XOSC32K_WRTLOCK_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_STARTUP(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_STARTUP_bf(const void *const hw, + hri_osc32kctrl_xosc32k_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_STARTUP(mask)) >> OSC32KCTRL_XOSC32K_STARTUP_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_STARTUP_Msk; + tmp |= OSC32KCTRL_XOSC32K_STARTUP(data); + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_STARTUP(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_STARTUP(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_STARTUP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_STARTUP_Msk) >> OSC32KCTRL_XOSC32K_STARTUP_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_set_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_reg(const void *const hw, + hri_osc32kctrl_xosc32k_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->XOSC32K.reg; +} + +static inline void hri_osc32kctrl_set_OSC32K_ENABLE_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg |= OSC32KCTRL_OSC32K_ENABLE; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSC32K_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp = (tmp & OSC32KCTRL_OSC32K_ENABLE) >> OSC32KCTRL_OSC32K_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSC32K_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp &= ~OSC32KCTRL_OSC32K_ENABLE; + tmp |= value << OSC32KCTRL_OSC32K_ENABLE_Pos; + ((Osc32kctrl *)hw)->OSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSC32K_ENABLE_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg &= ~OSC32KCTRL_OSC32K_ENABLE; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSC32K_ENABLE_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg ^= OSC32KCTRL_OSC32K_ENABLE; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSC32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg |= OSC32KCTRL_OSC32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSC32K_EN32K_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp = (tmp & OSC32KCTRL_OSC32K_EN32K) >> OSC32KCTRL_OSC32K_EN32K_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSC32K_EN32K_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp &= ~OSC32KCTRL_OSC32K_EN32K; + tmp |= value << OSC32KCTRL_OSC32K_EN32K_Pos; + ((Osc32kctrl *)hw)->OSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSC32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg &= ~OSC32KCTRL_OSC32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSC32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg ^= OSC32KCTRL_OSC32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSC32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg |= OSC32KCTRL_OSC32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSC32K_EN1K_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp = (tmp & OSC32KCTRL_OSC32K_EN1K) >> OSC32KCTRL_OSC32K_EN1K_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSC32K_EN1K_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp &= ~OSC32KCTRL_OSC32K_EN1K; + tmp |= value << OSC32KCTRL_OSC32K_EN1K_Pos; + ((Osc32kctrl *)hw)->OSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSC32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg &= ~OSC32KCTRL_OSC32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSC32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg ^= OSC32KCTRL_OSC32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSC32K_RUNSTDBY_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg |= OSC32KCTRL_OSC32K_RUNSTDBY; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSC32K_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp = (tmp & OSC32KCTRL_OSC32K_RUNSTDBY) >> OSC32KCTRL_OSC32K_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSC32K_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp &= ~OSC32KCTRL_OSC32K_RUNSTDBY; + tmp |= value << OSC32KCTRL_OSC32K_RUNSTDBY_Pos; + ((Osc32kctrl *)hw)->OSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSC32K_RUNSTDBY_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg &= ~OSC32KCTRL_OSC32K_RUNSTDBY; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSC32K_RUNSTDBY_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg ^= OSC32KCTRL_OSC32K_RUNSTDBY; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSC32K_ONDEMAND_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg |= OSC32KCTRL_OSC32K_ONDEMAND; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSC32K_ONDEMAND_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp = (tmp & OSC32KCTRL_OSC32K_ONDEMAND) >> OSC32KCTRL_OSC32K_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSC32K_ONDEMAND_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp &= ~OSC32KCTRL_OSC32K_ONDEMAND; + tmp |= value << OSC32KCTRL_OSC32K_ONDEMAND_Pos; + ((Osc32kctrl *)hw)->OSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSC32K_ONDEMAND_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg &= ~OSC32KCTRL_OSC32K_ONDEMAND; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSC32K_ONDEMAND_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg ^= OSC32KCTRL_OSC32K_ONDEMAND; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSC32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg |= OSC32KCTRL_OSC32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSC32K_WRTLOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp = (tmp & OSC32KCTRL_OSC32K_WRTLOCK) >> OSC32KCTRL_OSC32K_WRTLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSC32K_WRTLOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp &= ~OSC32KCTRL_OSC32K_WRTLOCK; + tmp |= value << OSC32KCTRL_OSC32K_WRTLOCK_Pos; + ((Osc32kctrl *)hw)->OSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSC32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg &= ~OSC32KCTRL_OSC32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSC32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg ^= OSC32KCTRL_OSC32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_osc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg |= OSC32KCTRL_OSC32K_STARTUP(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osc32k_reg_t hri_osc32kctrl_get_OSC32K_STARTUP_bf(const void *const hw, + hri_osc32kctrl_osc32k_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp = (tmp & OSC32KCTRL_OSC32K_STARTUP(mask)) >> OSC32KCTRL_OSC32K_STARTUP_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_write_OSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_osc32k_reg_t data) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp &= ~OSC32KCTRL_OSC32K_STARTUP_Msk; + tmp |= OSC32KCTRL_OSC32K_STARTUP(data); + ((Osc32kctrl *)hw)->OSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_osc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg &= ~OSC32KCTRL_OSC32K_STARTUP(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_osc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg ^= OSC32KCTRL_OSC32K_STARTUP(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osc32k_reg_t hri_osc32kctrl_read_OSC32K_STARTUP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp = (tmp & OSC32KCTRL_OSC32K_STARTUP_Msk) >> OSC32KCTRL_OSC32K_STARTUP_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_set_OSC32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg |= OSC32KCTRL_OSC32K_CALIB(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osc32k_reg_t hri_osc32kctrl_get_OSC32K_CALIB_bf(const void *const hw, + hri_osc32kctrl_osc32k_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp = (tmp & OSC32KCTRL_OSC32K_CALIB(mask)) >> OSC32KCTRL_OSC32K_CALIB_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_write_OSC32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osc32k_reg_t data) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp &= ~OSC32KCTRL_OSC32K_CALIB_Msk; + tmp |= OSC32KCTRL_OSC32K_CALIB(data); + ((Osc32kctrl *)hw)->OSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSC32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg &= ~OSC32KCTRL_OSC32K_CALIB(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSC32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg ^= OSC32KCTRL_OSC32K_CALIB(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osc32k_reg_t hri_osc32kctrl_read_OSC32K_CALIB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp = (tmp & OSC32KCTRL_OSC32K_CALIB_Msk) >> OSC32KCTRL_OSC32K_CALIB_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_set_OSC32K_reg(const void *const hw, hri_osc32kctrl_osc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osc32k_reg_t hri_osc32kctrl_get_OSC32K_reg(const void *const hw, + hri_osc32kctrl_osc32k_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSC32K.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_OSC32K_reg(const void *const hw, hri_osc32kctrl_osc32k_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSC32K_reg(const void *const hw, hri_osc32kctrl_osc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSC32K_reg(const void *const hw, hri_osc32kctrl_osc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSC32K.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osc32k_reg_t hri_osc32kctrl_read_OSC32K_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->OSC32K.reg; +} + +static inline void hri_osc32kctrl_set_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & OSC32KCTRL_OSCULP32K_WRTLOCK) >> OSC32KCTRL_OSCULP32K_WRTLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSCULP32K_WRTLOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp &= ~OSC32KCTRL_OSCULP32K_WRTLOCK; + tmp |= value << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos; + ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_CALIB(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_get_OSCULP32K_CALIB_bf(const void *const hw, + hri_osc32kctrl_osculp32k_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB(mask)) >> OSC32KCTRL_OSCULP32K_CALIB_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_write_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp &= ~OSC32KCTRL_OSCULP32K_CALIB_Msk; + tmp |= OSC32KCTRL_OSCULP32K_CALIB(data); + ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_CALIB(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_CALIB(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_CALIB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB_Msk) >> OSC32KCTRL_OSCULP32K_CALIB_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_set_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_get_OSCULP32K_reg(const void *const hw, + hri_osc32kctrl_osculp32k_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->OSCULP32K.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_OSC32KCTRL_L21_H_INCLUDED */ +#endif /* _SAML21_OSC32KCTRL_COMPONENT_ */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_oscctrl_l21.h b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_oscctrl_l21.h new file mode 100644 index 00000000..e83e1d92 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_oscctrl_l21.h @@ -0,0 +1,3135 @@ +/** + * \file + * + * \brief SAM OSCCTRL + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_OSCCTRL_COMPONENT_ +#ifndef _HRI_OSCCTRL_L21_H_INCLUDED_ +#define _HRI_OSCCTRL_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_OSCCTRL_CRITICAL_SECTIONS) +#define OSCCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define OSCCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define OSCCTRL_CRITICAL_SECTION_ENTER() +#define OSCCTRL_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_oscctrl_dfllctrl_reg_t; +typedef uint16_t hri_oscctrl_xoscctrl_reg_t; +typedef uint32_t hri_oscctrl_dfllmul_reg_t; +typedef uint32_t hri_oscctrl_dfllval_reg_t; +typedef uint32_t hri_oscctrl_dpllctrlb_reg_t; +typedef uint32_t hri_oscctrl_dpllratio_reg_t; +typedef uint32_t hri_oscctrl_intenset_reg_t; +typedef uint32_t hri_oscctrl_intflag_reg_t; +typedef uint32_t hri_oscctrl_status_reg_t; +typedef uint8_t hri_oscctrl_dfllsync_reg_t; +typedef uint8_t hri_oscctrl_dpllctrla_reg_t; +typedef uint8_t hri_oscctrl_dpllpresc_reg_t; +typedef uint8_t hri_oscctrl_dpllstatus_reg_t; +typedef uint8_t hri_oscctrl_dpllsyncbusy_reg_t; +typedef uint8_t hri_oscctrl_osc16mctrl_reg_t; + +static inline void hri_oscctrl_wait_for_sync(const void *const hw, hri_oscctrl_dpllsyncbusy_reg_t reg) +{ + while (((Oscctrl *)hw)->DPLLSYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_oscctrl_is_syncing(const void *const hw, hri_oscctrl_dpllsyncbusy_reg_t reg) +{ + return ((Oscctrl *)hw)->DPLLSYNCBUSY.reg & reg; +} + +static inline bool hri_oscctrl_get_INTFLAG_XOSCRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY) >> OSCCTRL_INTFLAG_XOSCRDY_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_XOSCRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY; +} + +static inline bool hri_oscctrl_get_INTFLAG_OSC16MRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_OSC16MRDY) >> OSCCTRL_INTFLAG_OSC16MRDY_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_OSC16MRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_OSC16MRDY; +} + +static inline bool hri_oscctrl_get_INTFLAG_DFLLRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRDY) >> OSCCTRL_INTFLAG_DFLLRDY_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DFLLRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY; +} + +static inline bool hri_oscctrl_get_INTFLAG_DFLLOOB_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLOOB) >> OSCCTRL_INTFLAG_DFLLOOB_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DFLLOOB_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLOOB; +} + +static inline bool hri_oscctrl_get_INTFLAG_DFLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKF) >> OSCCTRL_INTFLAG_DFLLLCKF_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DFLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKF; +} + +static inline bool hri_oscctrl_get_INTFLAG_DFLLLCKC_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKC) >> OSCCTRL_INTFLAG_DFLLLCKC_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DFLLLCKC_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKC; +} + +static inline bool hri_oscctrl_get_INTFLAG_DFLLRCS_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRCS) >> OSCCTRL_INTFLAG_DFLLRCS_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DFLLRCS_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRCS; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLLLCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLCKR) >> OSCCTRL_INTFLAG_DPLLLCKR_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLLLCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLCKR; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLCKF) >> OSCCTRL_INTFLAG_DPLLLCKF_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLCKF; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLLLTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLTO) >> OSCCTRL_INTFLAG_DPLLLTO_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLLLTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLTO; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLLLDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLDRTO) >> OSCCTRL_INTFLAG_DPLLLDRTO_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLLLDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLDRTO; +} + +static inline bool hri_oscctrl_get_interrupt_XOSCRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY) >> OSCCTRL_INTFLAG_XOSCRDY_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_XOSCRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY; +} + +static inline bool hri_oscctrl_get_interrupt_OSC16MRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_OSC16MRDY) >> OSCCTRL_INTFLAG_OSC16MRDY_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_OSC16MRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_OSC16MRDY; +} + +static inline bool hri_oscctrl_get_interrupt_DFLLRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRDY) >> OSCCTRL_INTFLAG_DFLLRDY_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DFLLRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY; +} + +static inline bool hri_oscctrl_get_interrupt_DFLLOOB_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLOOB) >> OSCCTRL_INTFLAG_DFLLOOB_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DFLLOOB_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLOOB; +} + +static inline bool hri_oscctrl_get_interrupt_DFLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKF) >> OSCCTRL_INTFLAG_DFLLLCKF_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DFLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKF; +} + +static inline bool hri_oscctrl_get_interrupt_DFLLLCKC_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKC) >> OSCCTRL_INTFLAG_DFLLLCKC_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DFLLLCKC_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKC; +} + +static inline bool hri_oscctrl_get_interrupt_DFLLRCS_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRCS) >> OSCCTRL_INTFLAG_DFLLRCS_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DFLLRCS_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRCS; +} + +static inline bool hri_oscctrl_get_interrupt_DPLLLCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLCKR) >> OSCCTRL_INTFLAG_DPLLLCKR_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLLLCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLCKR; +} + +static inline bool hri_oscctrl_get_interrupt_DPLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLCKF) >> OSCCTRL_INTFLAG_DPLLLCKF_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLCKF; +} + +static inline bool hri_oscctrl_get_interrupt_DPLLLTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLTO) >> OSCCTRL_INTFLAG_DPLLLTO_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLLLTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLTO; +} + +static inline bool hri_oscctrl_get_interrupt_DPLLLDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLLLDRTO) >> OSCCTRL_INTFLAG_DPLLLDRTO_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLLLDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLLLDRTO; +} + +static inline hri_oscctrl_intflag_reg_t hri_oscctrl_get_INTFLAG_reg(const void *const hw, + hri_oscctrl_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_intflag_reg_t hri_oscctrl_read_INTFLAG_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->INTFLAG.reg; +} + +static inline void hri_oscctrl_clear_INTFLAG_reg(const void *const hw, hri_oscctrl_intflag_reg_t mask) +{ + ((Oscctrl *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_oscctrl_set_INTEN_XOSCRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY; +} + +static inline bool hri_oscctrl_get_INTEN_XOSCRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCRDY) >> OSCCTRL_INTENSET_XOSCRDY_Pos; +} + +static inline void hri_oscctrl_write_INTEN_XOSCRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY; + } +} + +static inline void hri_oscctrl_clear_INTEN_XOSCRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY; +} + +static inline void hri_oscctrl_set_INTEN_OSC16MRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_OSC16MRDY; +} + +static inline bool hri_oscctrl_get_INTEN_OSC16MRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_OSC16MRDY) >> OSCCTRL_INTENSET_OSC16MRDY_Pos; +} + +static inline void hri_oscctrl_write_INTEN_OSC16MRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_OSC16MRDY; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_OSC16MRDY; + } +} + +static inline void hri_oscctrl_clear_INTEN_OSC16MRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_OSC16MRDY; +} + +static inline void hri_oscctrl_set_INTEN_DFLLRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRDY; +} + +static inline bool hri_oscctrl_get_INTEN_DFLLRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLRDY) >> OSCCTRL_INTENSET_DFLLRDY_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DFLLRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRDY; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRDY; + } +} + +static inline void hri_oscctrl_clear_INTEN_DFLLRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRDY; +} + +static inline void hri_oscctrl_set_INTEN_DFLLOOB_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLOOB; +} + +static inline bool hri_oscctrl_get_INTEN_DFLLOOB_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLOOB) >> OSCCTRL_INTENSET_DFLLOOB_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DFLLOOB_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLOOB; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLOOB; + } +} + +static inline void hri_oscctrl_clear_INTEN_DFLLOOB_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLOOB; +} + +static inline void hri_oscctrl_set_INTEN_DFLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKF; +} + +static inline bool hri_oscctrl_get_INTEN_DFLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLLCKF) >> OSCCTRL_INTENSET_DFLLLCKF_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DFLLLCKF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKF; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKF; + } +} + +static inline void hri_oscctrl_clear_INTEN_DFLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKF; +} + +static inline void hri_oscctrl_set_INTEN_DFLLLCKC_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKC; +} + +static inline bool hri_oscctrl_get_INTEN_DFLLLCKC_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLLCKC) >> OSCCTRL_INTENSET_DFLLLCKC_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DFLLLCKC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKC; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKC; + } +} + +static inline void hri_oscctrl_clear_INTEN_DFLLLCKC_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKC; +} + +static inline void hri_oscctrl_set_INTEN_DFLLRCS_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRCS; +} + +static inline bool hri_oscctrl_get_INTEN_DFLLRCS_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLRCS) >> OSCCTRL_INTENSET_DFLLRCS_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DFLLRCS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRCS; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRCS; + } +} + +static inline void hri_oscctrl_clear_INTEN_DFLLRCS_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRCS; +} + +static inline void hri_oscctrl_set_INTEN_DPLLLCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLCKR; +} + +static inline bool hri_oscctrl_get_INTEN_DPLLLCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLLLCKR) >> OSCCTRL_INTENSET_DPLLLCKR_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLLLCKR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLCKR; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLCKR; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLLLCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLCKR; +} + +static inline void hri_oscctrl_set_INTEN_DPLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLCKF; +} + +static inline bool hri_oscctrl_get_INTEN_DPLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLLLCKF) >> OSCCTRL_INTENSET_DPLLLCKF_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLLLCKF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLCKF; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLCKF; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLCKF; +} + +static inline void hri_oscctrl_set_INTEN_DPLLLTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLTO; +} + +static inline bool hri_oscctrl_get_INTEN_DPLLLTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLLLTO) >> OSCCTRL_INTENSET_DPLLLTO_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLLLTO_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLTO; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLTO; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLLLTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLTO; +} + +static inline void hri_oscctrl_set_INTEN_DPLLLDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLDRTO; +} + +static inline bool hri_oscctrl_get_INTEN_DPLLLDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLLLDRTO) >> OSCCTRL_INTENSET_DPLLLDRTO_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLLLDRTO_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLDRTO; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLLLDRTO; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLLLDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLLLDRTO; +} + +static inline void hri_oscctrl_set_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t mask) +{ + ((Oscctrl *)hw)->INTENSET.reg = mask; +} + +static inline hri_oscctrl_intenset_reg_t hri_oscctrl_get_INTEN_reg(const void *const hw, + hri_oscctrl_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_intenset_reg_t hri_oscctrl_read_INTEN_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->INTENSET.reg; +} + +static inline void hri_oscctrl_write_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t data) +{ + ((Oscctrl *)hw)->INTENSET.reg = data; + ((Oscctrl *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_oscctrl_clear_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t mask) +{ + ((Oscctrl *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_oscctrl_get_STATUS_XOSCRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCRDY) >> OSCCTRL_STATUS_XOSCRDY_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_OSC16MRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_OSC16MRDY) >> OSCCTRL_STATUS_OSC16MRDY_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DFLLRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLRDY) >> OSCCTRL_STATUS_DFLLRDY_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DFLLOOB_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLOOB) >> OSCCTRL_STATUS_DFLLOOB_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DFLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLLCKF) >> OSCCTRL_STATUS_DFLLLCKF_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DFLLLCKC_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLLCKC) >> OSCCTRL_STATUS_DFLLLCKC_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DFLLRCS_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLRCS) >> OSCCTRL_STATUS_DFLLRCS_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLLLCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLLLCKR) >> OSCCTRL_STATUS_DPLLLCKR_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLLLCKF) >> OSCCTRL_STATUS_DPLLLCKF_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLLTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLLTO) >> OSCCTRL_STATUS_DPLLTO_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLLLDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLLLDRTO) >> OSCCTRL_STATUS_DPLLLDRTO_Pos; +} + +static inline hri_oscctrl_status_reg_t hri_oscctrl_get_STATUS_reg(const void *const hw, hri_oscctrl_status_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_status_reg_t hri_oscctrl_read_STATUS_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->STATUS.reg; +} + +static inline bool hri_oscctrl_get_DPLLSYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_ENABLE) >> OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_oscctrl_get_DPLLSYNCBUSY_DPLLRATIO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLRATIO) >> OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos; +} + +static inline bool hri_oscctrl_get_DPLLSYNCBUSY_DPLLPRESC_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLPRESC) >> OSCCTRL_DPLLSYNCBUSY_DPLLPRESC_Pos; +} + +static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrl_get_DPLLSYNCBUSY_reg(const void *const hw, + hri_oscctrl_dpllsyncbusy_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DPLLSYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrl_read_DPLLSYNCBUSY_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DPLLSYNCBUSY.reg; +} + +static inline bool hri_oscctrl_get_DPLLSTATUS_LOCK_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_LOCK) >> OSCCTRL_DPLLSTATUS_LOCK_Pos; +} + +static inline bool hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY) >> OSCCTRL_DPLLSTATUS_CLKRDY_Pos; +} + +static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrl_get_DPLLSTATUS_reg(const void *const hw, + hri_oscctrl_dpllstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DPLLSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrl_read_DPLLSTATUS_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DPLLSTATUS.reg; +} + +static inline void hri_oscctrl_set_XOSCCTRL_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_ENABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_ENABLE) >> OSCCTRL_XOSCCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= ~OSCCTRL_XOSCCTRL_ENABLE; + tmp |= value << OSCCTRL_XOSCCTRL_ENABLE_Pos; + ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_ENABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_ENABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_XTALEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_XTALEN; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_XTALEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_XTALEN) >> OSCCTRL_XOSCCTRL_XTALEN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_XTALEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= ~OSCCTRL_XOSCCTRL_XTALEN; + tmp |= value << OSCCTRL_XOSCCTRL_XTALEN_Pos; + ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_XTALEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_XTALEN; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_XTALEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_XTALEN; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_RUNSTDBY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_RUNSTDBY) >> OSCCTRL_XOSCCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= ~OSCCTRL_XOSCCTRL_RUNSTDBY; + tmp |= value << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos; + ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_ONDEMAND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_ONDEMAND) >> OSCCTRL_XOSCCTRL_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_ONDEMAND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= ~OSCCTRL_XOSCCTRL_ONDEMAND; + tmp |= value << OSCCTRL_XOSCCTRL_ONDEMAND_Pos; + ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_AMPGC_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_AMPGC; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_AMPGC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_AMPGC) >> OSCCTRL_XOSCCTRL_AMPGC_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_AMPGC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= ~OSCCTRL_XOSCCTRL_AMPGC; + tmp |= value << OSCCTRL_XOSCCTRL_AMPGC_Pos; + ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_AMPGC_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_AMPGC; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_AMPGC_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_AMPGC; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_GAIN_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_GAIN(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_GAIN_bf(const void *const hw, + hri_oscctrl_xoscctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_GAIN(mask)) >> OSCCTRL_XOSCCTRL_GAIN_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_GAIN_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t data) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= ~OSCCTRL_XOSCCTRL_GAIN_Msk; + tmp |= OSCCTRL_XOSCCTRL_GAIN(data); + ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_GAIN_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_GAIN(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_GAIN_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_GAIN(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_GAIN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_GAIN_Msk) >> OSCCTRL_XOSCCTRL_GAIN_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_XOSCCTRL_STARTUP_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= OSCCTRL_XOSCCTRL_STARTUP(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_STARTUP_bf(const void *const hw, + hri_oscctrl_xoscctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_STARTUP(mask)) >> OSCCTRL_XOSCCTRL_STARTUP_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_STARTUP_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t data) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= ~OSCCTRL_XOSCCTRL_STARTUP_Msk; + tmp |= OSCCTRL_XOSCCTRL_STARTUP(data); + ((Oscctrl *)hw)->XOSCCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_STARTUP_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~OSCCTRL_XOSCCTRL_STARTUP(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_STARTUP_bf(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= OSCCTRL_XOSCCTRL_STARTUP(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_STARTUP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_STARTUP_Msk) >> OSCCTRL_XOSCCTRL_STARTUP_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_XOSCCTRL_reg(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg |= mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_reg(const void *const hw, + hri_oscctrl_xoscctrl_reg_t mask) +{ + uint16_t tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((Oscctrl *)hw)->XOSCCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_reg(const void *const hw, hri_oscctrl_xoscctrl_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg = data; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_reg(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg &= ~mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_reg(const void *const hw, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL.reg ^= mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_reg(const void *const hw) +{ + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + return ((Oscctrl *)hw)->XOSCCTRL.reg; +} + +static inline void hri_oscctrl_set_OSC16MCTRL_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg |= OSCCTRL_OSC16MCTRL_ENABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_OSC16MCTRL_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg; + tmp = (tmp & OSCCTRL_OSC16MCTRL_ENABLE) >> OSCCTRL_OSC16MCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_OSC16MCTRL_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg; + tmp &= ~OSCCTRL_OSC16MCTRL_ENABLE; + tmp |= value << OSCCTRL_OSC16MCTRL_ENABLE_Pos; + ((Oscctrl *)hw)->OSC16MCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_OSC16MCTRL_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg &= ~OSCCTRL_OSC16MCTRL_ENABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_OSC16MCTRL_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg ^= OSCCTRL_OSC16MCTRL_ENABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_OSC16MCTRL_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg |= OSCCTRL_OSC16MCTRL_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_OSC16MCTRL_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg; + tmp = (tmp & OSCCTRL_OSC16MCTRL_RUNSTDBY) >> OSCCTRL_OSC16MCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_OSC16MCTRL_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg; + tmp &= ~OSCCTRL_OSC16MCTRL_RUNSTDBY; + tmp |= value << OSCCTRL_OSC16MCTRL_RUNSTDBY_Pos; + ((Oscctrl *)hw)->OSC16MCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_OSC16MCTRL_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg &= ~OSCCTRL_OSC16MCTRL_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_OSC16MCTRL_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg ^= OSCCTRL_OSC16MCTRL_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_OSC16MCTRL_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg |= OSCCTRL_OSC16MCTRL_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_OSC16MCTRL_ONDEMAND_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg; + tmp = (tmp & OSCCTRL_OSC16MCTRL_ONDEMAND) >> OSCCTRL_OSC16MCTRL_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_OSC16MCTRL_ONDEMAND_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg; + tmp &= ~OSCCTRL_OSC16MCTRL_ONDEMAND; + tmp |= value << OSCCTRL_OSC16MCTRL_ONDEMAND_Pos; + ((Oscctrl *)hw)->OSC16MCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_OSC16MCTRL_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg &= ~OSCCTRL_OSC16MCTRL_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_OSC16MCTRL_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg ^= OSCCTRL_OSC16MCTRL_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_OSC16MCTRL_FSEL_bf(const void *const hw, hri_oscctrl_osc16mctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg |= OSCCTRL_OSC16MCTRL_FSEL(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_osc16mctrl_reg_t hri_oscctrl_get_OSC16MCTRL_FSEL_bf(const void *const hw, + hri_oscctrl_osc16mctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg; + tmp = (tmp & OSCCTRL_OSC16MCTRL_FSEL(mask)) >> OSCCTRL_OSC16MCTRL_FSEL_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_OSC16MCTRL_FSEL_bf(const void *const hw, hri_oscctrl_osc16mctrl_reg_t data) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg; + tmp &= ~OSCCTRL_OSC16MCTRL_FSEL_Msk; + tmp |= OSCCTRL_OSC16MCTRL_FSEL(data); + ((Oscctrl *)hw)->OSC16MCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_OSC16MCTRL_FSEL_bf(const void *const hw, hri_oscctrl_osc16mctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg &= ~OSCCTRL_OSC16MCTRL_FSEL(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_OSC16MCTRL_FSEL_bf(const void *const hw, hri_oscctrl_osc16mctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg ^= OSCCTRL_OSC16MCTRL_FSEL(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_osc16mctrl_reg_t hri_oscctrl_read_OSC16MCTRL_FSEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg; + tmp = (tmp & OSCCTRL_OSC16MCTRL_FSEL_Msk) >> OSCCTRL_OSC16MCTRL_FSEL_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_OSC16MCTRL_reg(const void *const hw, hri_oscctrl_osc16mctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg |= mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_osc16mctrl_reg_t hri_oscctrl_get_OSC16MCTRL_reg(const void *const hw, + hri_oscctrl_osc16mctrl_reg_t mask) +{ + uint8_t tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((Oscctrl *)hw)->OSC16MCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_OSC16MCTRL_reg(const void *const hw, hri_oscctrl_osc16mctrl_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg = data; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_OSC16MCTRL_reg(const void *const hw, hri_oscctrl_osc16mctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg &= ~mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_OSC16MCTRL_reg(const void *const hw, hri_oscctrl_osc16mctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->OSC16MCTRL.reg ^= mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_osc16mctrl_reg_t hri_oscctrl_read_OSC16MCTRL_reg(const void *const hw) +{ + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + return ((Oscctrl *)hw)->OSC16MCTRL.reg; +} + +static inline void hri_oscctrl_set_DFLLCTRL_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_ENABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRL_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & OSCCTRL_DFLLCTRL_ENABLE) >> OSCCTRL_DFLLCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRL_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp &= ~OSCCTRL_DFLLCTRL_ENABLE; + tmp |= value << OSCCTRL_DFLLCTRL_ENABLE_Pos; + ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRL_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_ENABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRL_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_ENABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRL_MODE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_MODE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRL_MODE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & OSCCTRL_DFLLCTRL_MODE) >> OSCCTRL_DFLLCTRL_MODE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRL_MODE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp &= ~OSCCTRL_DFLLCTRL_MODE; + tmp |= value << OSCCTRL_DFLLCTRL_MODE_Pos; + ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRL_MODE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_MODE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRL_MODE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_MODE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRL_STABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_STABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRL_STABLE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & OSCCTRL_DFLLCTRL_STABLE) >> OSCCTRL_DFLLCTRL_STABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRL_STABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp &= ~OSCCTRL_DFLLCTRL_STABLE; + tmp |= value << OSCCTRL_DFLLCTRL_STABLE_Pos; + ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRL_STABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_STABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRL_STABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_STABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRL_LLAW_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_LLAW; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRL_LLAW_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & OSCCTRL_DFLLCTRL_LLAW) >> OSCCTRL_DFLLCTRL_LLAW_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRL_LLAW_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp &= ~OSCCTRL_DFLLCTRL_LLAW; + tmp |= value << OSCCTRL_DFLLCTRL_LLAW_Pos; + ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRL_LLAW_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_LLAW; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRL_LLAW_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_LLAW; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRL_USBCRM_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_USBCRM; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRL_USBCRM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & OSCCTRL_DFLLCTRL_USBCRM) >> OSCCTRL_DFLLCTRL_USBCRM_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRL_USBCRM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp &= ~OSCCTRL_DFLLCTRL_USBCRM; + tmp |= value << OSCCTRL_DFLLCTRL_USBCRM_Pos; + ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRL_USBCRM_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_USBCRM; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRL_USBCRM_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_USBCRM; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRL_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRL_RUNSTDBY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & OSCCTRL_DFLLCTRL_RUNSTDBY) >> OSCCTRL_DFLLCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRL_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp &= ~OSCCTRL_DFLLCTRL_RUNSTDBY; + tmp |= value << OSCCTRL_DFLLCTRL_RUNSTDBY_Pos; + ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRL_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRL_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRL_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRL_ONDEMAND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & OSCCTRL_DFLLCTRL_ONDEMAND) >> OSCCTRL_DFLLCTRL_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRL_ONDEMAND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp &= ~OSCCTRL_DFLLCTRL_ONDEMAND; + tmp |= value << OSCCTRL_DFLLCTRL_ONDEMAND_Pos; + ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRL_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRL_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRL_CCDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_CCDIS; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRL_CCDIS_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & OSCCTRL_DFLLCTRL_CCDIS) >> OSCCTRL_DFLLCTRL_CCDIS_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRL_CCDIS_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp &= ~OSCCTRL_DFLLCTRL_CCDIS; + tmp |= value << OSCCTRL_DFLLCTRL_CCDIS_Pos; + ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRL_CCDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_CCDIS; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRL_CCDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_CCDIS; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRL_QLDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_QLDIS; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRL_QLDIS_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & OSCCTRL_DFLLCTRL_QLDIS) >> OSCCTRL_DFLLCTRL_QLDIS_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRL_QLDIS_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp &= ~OSCCTRL_DFLLCTRL_QLDIS; + tmp |= value << OSCCTRL_DFLLCTRL_QLDIS_Pos; + ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRL_QLDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_QLDIS; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRL_QLDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_QLDIS; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRL_BPLCKC_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_BPLCKC; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRL_BPLCKC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & OSCCTRL_DFLLCTRL_BPLCKC) >> OSCCTRL_DFLLCTRL_BPLCKC_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRL_BPLCKC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp &= ~OSCCTRL_DFLLCTRL_BPLCKC; + tmp |= value << OSCCTRL_DFLLCTRL_BPLCKC_Pos; + ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRL_BPLCKC_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_BPLCKC; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRL_BPLCKC_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_BPLCKC; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRL_WAITLOCK_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg |= OSCCTRL_DFLLCTRL_WAITLOCK; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRL_WAITLOCK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & OSCCTRL_DFLLCTRL_WAITLOCK) >> OSCCTRL_DFLLCTRL_WAITLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRL_WAITLOCK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp &= ~OSCCTRL_DFLLCTRL_WAITLOCK; + tmp |= value << OSCCTRL_DFLLCTRL_WAITLOCK_Pos; + ((Oscctrl *)hw)->DFLLCTRL.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRL_WAITLOCK_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg &= ~OSCCTRL_DFLLCTRL_WAITLOCK; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRL_WAITLOCK_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg ^= OSCCTRL_DFLLCTRL_WAITLOCK; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRL_reg(const void *const hw, hri_oscctrl_dfllctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg |= mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllctrl_reg_t hri_oscctrl_get_DFLLCTRL_reg(const void *const hw, + hri_oscctrl_dfllctrl_reg_t mask) +{ + uint16_t tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((Oscctrl *)hw)->DFLLCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRL_reg(const void *const hw, hri_oscctrl_dfllctrl_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg = data; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRL_reg(const void *const hw, hri_oscctrl_dfllctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg &= ~mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRL_reg(const void *const hw, hri_oscctrl_dfllctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRL.reg ^= mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllctrl_reg_t hri_oscctrl_read_DFLLCTRL_reg(const void *const hw) +{ + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + return ((Oscctrl *)hw)->DFLLCTRL.reg; +} + +static inline void hri_oscctrl_set_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_FINE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_FINE_bf(const void *const hw, + hri_oscctrl_dfllval_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_FINE(mask)) >> OSCCTRL_DFLLVAL_FINE_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp &= ~OSCCTRL_DFLLVAL_FINE_Msk; + tmp |= OSCCTRL_DFLLVAL_FINE(data); + ((Oscctrl *)hw)->DFLLVAL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_FINE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_FINE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_FINE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_FINE_Msk) >> OSCCTRL_DFLLVAL_FINE_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_COARSE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_COARSE_bf(const void *const hw, + hri_oscctrl_dfllval_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_COARSE(mask)) >> OSCCTRL_DFLLVAL_COARSE_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp &= ~OSCCTRL_DFLLVAL_COARSE_Msk; + tmp |= OSCCTRL_DFLLVAL_COARSE(data); + ((Oscctrl *)hw)->DFLLVAL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_COARSE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_COARSE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_COARSE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_COARSE_Msk) >> OSCCTRL_DFLLVAL_COARSE_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_DIFF(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_DIFF_bf(const void *const hw, + hri_oscctrl_dfllval_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_DIFF(mask)) >> OSCCTRL_DFLLVAL_DIFF_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp &= ~OSCCTRL_DFLLVAL_DIFF_Msk; + tmp |= OSCCTRL_DFLLVAL_DIFF(data); + ((Oscctrl *)hw)->DFLLVAL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_DIFF(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_DIFF(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_DIFF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_DIFF_Msk) >> OSCCTRL_DFLLVAL_DIFF_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_reg(const void *const hw, + hri_oscctrl_dfllval_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DFLLVAL.reg; +} + +static inline void hri_oscctrl_set_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_MUL(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_MUL_bf(const void *const hw, + hri_oscctrl_dfllmul_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_MUL(mask)) >> OSCCTRL_DFLLMUL_MUL_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp &= ~OSCCTRL_DFLLMUL_MUL_Msk; + tmp |= OSCCTRL_DFLLMUL_MUL(data); + ((Oscctrl *)hw)->DFLLMUL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_MUL(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_MUL(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_MUL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_MUL_Msk) >> OSCCTRL_DFLLMUL_MUL_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_FSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_FSTEP_bf(const void *const hw, + hri_oscctrl_dfllmul_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_FSTEP(mask)) >> OSCCTRL_DFLLMUL_FSTEP_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp &= ~OSCCTRL_DFLLMUL_FSTEP_Msk; + tmp |= OSCCTRL_DFLLMUL_FSTEP(data); + ((Oscctrl *)hw)->DFLLMUL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_FSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_FSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_FSTEP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_FSTEP_Msk) >> OSCCTRL_DFLLMUL_FSTEP_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_CSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_CSTEP_bf(const void *const hw, + hri_oscctrl_dfllmul_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_CSTEP(mask)) >> OSCCTRL_DFLLMUL_CSTEP_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp &= ~OSCCTRL_DFLLMUL_CSTEP_Msk; + tmp |= OSCCTRL_DFLLMUL_CSTEP(data); + ((Oscctrl *)hw)->DFLLMUL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_CSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_CSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_CSTEP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_CSTEP_Msk) >> OSCCTRL_DFLLMUL_CSTEP_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_reg(const void *const hw, + hri_oscctrl_dfllmul_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DFLLMUL.reg; +} + +static inline void hri_oscctrl_set_DFLLSYNC_READREQ_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_READREQ; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLSYNC_READREQ_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp = (tmp & OSCCTRL_DFLLSYNC_READREQ) >> OSCCTRL_DFLLSYNC_READREQ_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLSYNC_READREQ_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp &= ~OSCCTRL_DFLLSYNC_READREQ; + tmp |= value << OSCCTRL_DFLLSYNC_READREQ_Pos; + ((Oscctrl *)hw)->DFLLSYNC.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLSYNC_READREQ_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_READREQ; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLSYNC_READREQ_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_READREQ; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllsync_reg_t hri_oscctrl_get_DFLLSYNC_reg(const void *const hw, + hri_oscctrl_dfllsync_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllsync_reg_t hri_oscctrl_read_DFLLSYNC_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DFLLSYNC.reg; +} + +static inline void hri_oscctrl_set_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ENABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_ENABLE) >> OSCCTRL_DPLLCTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_ENABLE; + tmp |= value << OSCCTRL_DPLLCTRLA_ENABLE_Pos; + ((Oscctrl *)hw)->DPLLCTRLA.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ENABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ENABLE; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_RUNSTDBY) >> OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; + tmp |= value << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; + ((Oscctrl *)hw)->DPLLCTRLA.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_ONDEMAND) >> OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLA_ONDEMAND_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; + tmp |= value << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; + ((Oscctrl *)hw)->DPLLCTRLA.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg |= mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrl_get_DPLLCTRLA_reg(const void *const hw, + hri_oscctrl_dpllctrla_reg_t mask) +{ + uint8_t tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((Oscctrl *)hw)->DPLLCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg = data; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg &= ~mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLA.reg ^= mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrl_read_DPLLCTRLA_reg(const void *const hw) +{ + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + return ((Oscctrl *)hw)->DPLLCTRLA.reg; +} + +static inline void hri_oscctrl_set_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDR(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_get_DPLLRATIO_LDR_bf(const void *const hw, + hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDR(mask)) >> OSCCTRL_DPLLRATIO_LDR_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLRATIO.reg; + tmp &= ~OSCCTRL_DPLLRATIO_LDR_Msk; + tmp |= OSCCTRL_DPLLRATIO_LDR(data); + ((Oscctrl *)hw)->DPLLRATIO.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDR(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDR(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_LDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDR_Msk) >> OSCCTRL_DPLLRATIO_LDR_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDRFRAC(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_get_DPLLRATIO_LDRFRAC_bf(const void *const hw, + hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC(mask)) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLRATIO.reg; + tmp &= ~OSCCTRL_DPLLRATIO_LDRFRAC_Msk; + tmp |= OSCCTRL_DPLLRATIO_LDRFRAC(data); + ((Oscctrl *)hw)->DPLLRATIO.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDRFRAC(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDRFRAC(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_LDRFRAC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC_Msk) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg |= mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_get_DPLLRATIO_reg(const void *const hw, + hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + tmp = ((Oscctrl *)hw)->DPLLRATIO.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg = data; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg &= ~mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLRATIO.reg ^= mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_reg(const void *const hw) +{ + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + return ((Oscctrl *)hw)->DPLLRATIO.reg; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_LPEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LPEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLB_LPEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LPEN) >> OSCCTRL_DPLLCTRLB_LPEN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_LPEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_LPEN; + tmp |= value << OSCCTRL_DPLLCTRLB_LPEN_Pos; + ((Oscctrl *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_LPEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LPEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_LPEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LPEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLB_WUF_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLB_WUF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_WUF) >> OSCCTRL_DPLLCTRLB_WUF_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_WUF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_WUF; + tmp |= value << OSCCTRL_DPLLCTRLB_WUF_Pos; + ((Oscctrl *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_WUF_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_WUF_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LBYPASS) >> OSCCTRL_DPLLCTRLB_LBYPASS_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_LBYPASS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_LBYPASS; + tmp |= value << OSCCTRL_DPLLCTRLB_LBYPASS_Pos; + ((Oscctrl *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_FILTER_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER(mask)) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_FILTER_Msk; + tmp |= OSCCTRL_DPLLCTRLB_FILTER(data); + ((Oscctrl *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_FILTER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER_Msk) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_REFCLK_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK(mask)) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_REFCLK_Msk; + tmp |= OSCCTRL_DPLLCTRLB_REFCLK(data); + ((Oscctrl *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_REFCLK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK_Msk) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_LTIME_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME(mask)) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_LTIME_Msk; + tmp |= OSCCTRL_DPLLCTRLB_LTIME(data); + ((Oscctrl *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_LTIME_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME_Msk) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_DIV_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV(mask)) >> OSCCTRL_DPLLCTRLB_DIV_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_DIV_Msk; + tmp |= OSCCTRL_DPLLCTRLB_DIV(data); + ((Oscctrl *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_DIV_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV_Msk) >> OSCCTRL_DPLLCTRLB_DIV_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_reg(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DPLLCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLCTRLB.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DPLLCTRLB.reg; +} + +static inline void hri_oscctrl_set_DPLLPRESC_PRESC_bf(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLPRESC.reg |= OSCCTRL_DPLLPRESC_PRESC(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllpresc_reg_t hri_oscctrl_get_DPLLPRESC_PRESC_bf(const void *const hw, + hri_oscctrl_dpllpresc_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DPLLPRESC.reg; + tmp = (tmp & OSCCTRL_DPLLPRESC_PRESC(mask)) >> OSCCTRL_DPLLPRESC_PRESC_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLPRESC_PRESC_bf(const void *const hw, hri_oscctrl_dpllpresc_reg_t data) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DPLLPRESC.reg; + tmp &= ~OSCCTRL_DPLLPRESC_PRESC_Msk; + tmp |= OSCCTRL_DPLLPRESC_PRESC(data); + ((Oscctrl *)hw)->DPLLPRESC.reg = tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLPRESC_PRESC_bf(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLPRESC.reg &= ~OSCCTRL_DPLLPRESC_PRESC(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLPRESC_PRESC_bf(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLPRESC.reg ^= OSCCTRL_DPLLPRESC_PRESC(mask); + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllpresc_reg_t hri_oscctrl_read_DPLLPRESC_PRESC_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DPLLPRESC.reg; + tmp = (tmp & OSCCTRL_DPLLPRESC_PRESC_Msk) >> OSCCTRL_DPLLPRESC_PRESC_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLPRESC_reg(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLPRESC.reg |= mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllpresc_reg_t hri_oscctrl_get_DPLLPRESC_reg(const void *const hw, + hri_oscctrl_dpllpresc_reg_t mask) +{ + uint8_t tmp; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + tmp = ((Oscctrl *)hw)->DPLLPRESC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLPRESC_reg(const void *const hw, hri_oscctrl_dpllpresc_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLPRESC.reg = data; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLPRESC_reg(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLPRESC.reg &= ~mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLPRESC_reg(const void *const hw, hri_oscctrl_dpllpresc_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DPLLPRESC.reg ^= mask; + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllpresc_reg_t hri_oscctrl_read_DPLLPRESC_reg(const void *const hw) +{ + hri_oscctrl_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + return ((Oscctrl *)hw)->DPLLPRESC.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_OSCCTRL_L21_H_INCLUDED */ +#endif /* _SAML21_OSCCTRL_COMPONENT_ */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_pac_l21.h b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_pac_l21.h new file mode 100644 index 00000000..07997ea6 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_pac_l21.h @@ -0,0 +1,1257 @@ +/** + * \file + * + * \brief SAM PAC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_PAC_COMPONENT_ +#ifndef _HRI_PAC_L21_H_INCLUDED_ +#define _HRI_PAC_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PAC_CRITICAL_SECTIONS) +#define PAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PAC_CRITICAL_SECTION_ENTER() +#define PAC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_pac_intflaga_reg_t; +typedef uint32_t hri_pac_intflagahb_reg_t; +typedef uint32_t hri_pac_intflagb_reg_t; +typedef uint32_t hri_pac_intflagc_reg_t; +typedef uint32_t hri_pac_intflagd_reg_t; +typedef uint32_t hri_pac_intflage_reg_t; +typedef uint32_t hri_pac_statusa_reg_t; +typedef uint32_t hri_pac_statusb_reg_t; +typedef uint32_t hri_pac_statusc_reg_t; +typedef uint32_t hri_pac_statusd_reg_t; +typedef uint32_t hri_pac_statuse_reg_t; +typedef uint32_t hri_pac_wrctrl_reg_t; +typedef uint8_t hri_pac_evctrl_reg_t; +typedef uint8_t hri_pac_intenset_reg_t; + +static inline bool hri_pac_get_INTFLAGAHB_FLASH_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_FLASH) >> PAC_INTFLAGAHB_FLASH_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_FLASH_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_FLASH; +} + +static inline bool hri_pac_get_INTFLAGAHB_HSRAMCM0P_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HSRAMCM0P) >> PAC_INTFLAGAHB_HSRAMCM0P_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HSRAMCM0P_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HSRAMCM0P; +} + +static inline bool hri_pac_get_INTFLAGAHB_HSRAMDSU_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HSRAMDSU) >> PAC_INTFLAGAHB_HSRAMDSU_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HSRAMDSU_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HSRAMDSU; +} + +static inline bool hri_pac_get_INTFLAGAHB_HPB1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB1) >> PAC_INTFLAGAHB_HPB1_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HPB1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB1; +} + +static inline bool hri_pac_get_INTFLAGAHB_H2LBRIDGES_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_H2LBRIDGES) >> PAC_INTFLAGAHB_H2LBRIDGES_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_H2LBRIDGES_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_H2LBRIDGES; +} + +static inline bool hri_pac_get_INTFLAGAHB_HPB0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB0) >> PAC_INTFLAGAHB_HPB0_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HPB0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB0; +} + +static inline bool hri_pac_get_INTFLAGAHB_HPB2_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB2) >> PAC_INTFLAGAHB_HPB2_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HPB2_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB2; +} + +static inline bool hri_pac_get_INTFLAGAHB_HPB3_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB3) >> PAC_INTFLAGAHB_HPB3_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HPB3_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB3; +} + +static inline bool hri_pac_get_INTFLAGAHB_HPB4_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB4) >> PAC_INTFLAGAHB_HPB4_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HPB4_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB4; +} + +static inline bool hri_pac_get_INTFLAGAHB_LPRAMHS_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_LPRAMHS) >> PAC_INTFLAGAHB_LPRAMHS_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_LPRAMHS_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_LPRAMHS; +} + +static inline bool hri_pac_get_INTFLAGAHB_LPRAMPICOP_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_LPRAMPICOP) >> PAC_INTFLAGAHB_LPRAMPICOP_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_LPRAMPICOP_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_LPRAMPICOP; +} + +static inline bool hri_pac_get_INTFLAGAHB_LPRAMDMAC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_LPRAMDMAC) >> PAC_INTFLAGAHB_LPRAMDMAC_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_LPRAMDMAC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_LPRAMDMAC; +} + +static inline bool hri_pac_get_INTFLAGAHB_L2HBRIDGES_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_L2HBRIDGES) >> PAC_INTFLAGAHB_L2HBRIDGES_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_L2HBRIDGES_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_L2HBRIDGES; +} + +static inline bool hri_pac_get_INTFLAGAHB_HSRAMLP_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HSRAMLP) >> PAC_INTFLAGAHB_HSRAMLP_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HSRAMLP_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HSRAMLP; +} + +static inline hri_pac_intflagahb_reg_t hri_pac_get_INTFLAGAHB_reg(const void *const hw, hri_pac_intflagahb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGAHB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflagahb_reg_t hri_pac_read_INTFLAGAHB_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGAHB.reg; +} + +static inline void hri_pac_clear_INTFLAGAHB_reg(const void *const hw, hri_pac_intflagahb_reg_t mask) +{ + ((Pac *)hw)->INTFLAGAHB.reg = mask; +} + +static inline bool hri_pac_get_INTFLAGA_PM_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_PM) >> PAC_INTFLAGA_PM_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_PM_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_PM; +} + +static inline bool hri_pac_get_INTFLAGA_MCLK_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_MCLK) >> PAC_INTFLAGA_MCLK_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_MCLK_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_MCLK; +} + +static inline bool hri_pac_get_INTFLAGA_RSTC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_RSTC) >> PAC_INTFLAGA_RSTC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_RSTC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_RSTC; +} + +static inline bool hri_pac_get_INTFLAGA_OSCCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_OSCCTRL) >> PAC_INTFLAGA_OSCCTRL_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_OSCCTRL_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_OSCCTRL; +} + +static inline bool hri_pac_get_INTFLAGA_OSC32KCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_OSC32KCTRL) >> PAC_INTFLAGA_OSC32KCTRL_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_OSC32KCTRL_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_OSC32KCTRL; +} + +static inline bool hri_pac_get_INTFLAGA_SUPC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SUPC) >> PAC_INTFLAGA_SUPC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_SUPC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SUPC; +} + +static inline bool hri_pac_get_INTFLAGA_GCLK_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_GCLK) >> PAC_INTFLAGA_GCLK_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_GCLK_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_GCLK; +} + +static inline bool hri_pac_get_INTFLAGA_WDT_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_WDT) >> PAC_INTFLAGA_WDT_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_WDT_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_WDT; +} + +static inline bool hri_pac_get_INTFLAGA_RTC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_RTC) >> PAC_INTFLAGA_RTC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_RTC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_RTC; +} + +static inline bool hri_pac_get_INTFLAGA_EIC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_EIC) >> PAC_INTFLAGA_EIC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_EIC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_EIC; +} + +static inline bool hri_pac_get_INTFLAGA_PORT_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_PORT) >> PAC_INTFLAGA_PORT_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_PORT_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_PORT; +} + +static inline hri_pac_intflaga_reg_t hri_pac_get_INTFLAGA_reg(const void *const hw, hri_pac_intflaga_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflaga_reg_t hri_pac_read_INTFLAGA_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGA.reg; +} + +static inline void hri_pac_clear_INTFLAGA_reg(const void *const hw, hri_pac_intflaga_reg_t mask) +{ + ((Pac *)hw)->INTFLAGA.reg = mask; +} + +static inline bool hri_pac_get_INTFLAGB_USB_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_USB) >> PAC_INTFLAGB_USB_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_USB_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_USB; +} + +static inline bool hri_pac_get_INTFLAGB_DSU_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_DSU) >> PAC_INTFLAGB_DSU_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_DSU_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_DSU; +} + +static inline bool hri_pac_get_INTFLAGB_NVMCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_NVMCTRL) >> PAC_INTFLAGB_NVMCTRL_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_NVMCTRL_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_NVMCTRL; +} + +static inline bool hri_pac_get_INTFLAGB_MTB_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_MTB) >> PAC_INTFLAGB_MTB_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_MTB_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_MTB; +} + +static inline hri_pac_intflagb_reg_t hri_pac_get_INTFLAGB_reg(const void *const hw, hri_pac_intflagb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflagb_reg_t hri_pac_read_INTFLAGB_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGB.reg; +} + +static inline void hri_pac_clear_INTFLAGB_reg(const void *const hw, hri_pac_intflagb_reg_t mask) +{ + ((Pac *)hw)->INTFLAGB.reg = mask; +} + +static inline bool hri_pac_get_INTFLAGC_SERCOM0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM0) >> PAC_INTFLAGC_SERCOM0_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_SERCOM0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM0; +} + +static inline bool hri_pac_get_INTFLAGC_SERCOM1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM1) >> PAC_INTFLAGC_SERCOM1_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_SERCOM1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM1; +} + +static inline bool hri_pac_get_INTFLAGC_SERCOM2_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM2) >> PAC_INTFLAGC_SERCOM2_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_SERCOM2_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM2; +} + +static inline bool hri_pac_get_INTFLAGC_SERCOM3_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM3) >> PAC_INTFLAGC_SERCOM3_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_SERCOM3_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM3; +} + +static inline bool hri_pac_get_INTFLAGC_SERCOM4_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_SERCOM4) >> PAC_INTFLAGC_SERCOM4_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_SERCOM4_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_SERCOM4; +} + +static inline bool hri_pac_get_INTFLAGC_TCC0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TCC0) >> PAC_INTFLAGC_TCC0_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TCC0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TCC0; +} + +static inline bool hri_pac_get_INTFLAGC_TCC1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TCC1) >> PAC_INTFLAGC_TCC1_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TCC1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TCC1; +} + +static inline bool hri_pac_get_INTFLAGC_TCC2_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TCC2) >> PAC_INTFLAGC_TCC2_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TCC2_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TCC2; +} + +static inline bool hri_pac_get_INTFLAGC_TC0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC0) >> PAC_INTFLAGC_TC0_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TC0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC0; +} + +static inline bool hri_pac_get_INTFLAGC_TC1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC1) >> PAC_INTFLAGC_TC1_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TC1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC1; +} + +static inline bool hri_pac_get_INTFLAGC_TC2_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC2) >> PAC_INTFLAGC_TC2_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TC2_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC2; +} + +static inline bool hri_pac_get_INTFLAGC_TC3_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC3) >> PAC_INTFLAGC_TC3_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TC3_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC3; +} + +static inline bool hri_pac_get_INTFLAGC_DAC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_DAC) >> PAC_INTFLAGC_DAC_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_DAC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_DAC; +} + +static inline bool hri_pac_get_INTFLAGC_AES_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_AES) >> PAC_INTFLAGC_AES_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_AES_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_AES; +} + +static inline bool hri_pac_get_INTFLAGC_TRNG_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TRNG) >> PAC_INTFLAGC_TRNG_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TRNG_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TRNG; +} + +static inline hri_pac_intflagc_reg_t hri_pac_get_INTFLAGC_reg(const void *const hw, hri_pac_intflagc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGC.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflagc_reg_t hri_pac_read_INTFLAGC_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGC.reg; +} + +static inline void hri_pac_clear_INTFLAGC_reg(const void *const hw, hri_pac_intflagc_reg_t mask) +{ + ((Pac *)hw)->INTFLAGC.reg = mask; +} + +static inline bool hri_pac_get_INTFLAGD_EVSYS_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_EVSYS) >> PAC_INTFLAGD_EVSYS_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_EVSYS_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_EVSYS; +} + +static inline bool hri_pac_get_INTFLAGD_SERCOM5_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM5) >> PAC_INTFLAGD_SERCOM5_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_SERCOM5_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM5; +} + +static inline bool hri_pac_get_INTFLAGD_TC4_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_TC4) >> PAC_INTFLAGD_TC4_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_TC4_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_TC4; +} + +static inline bool hri_pac_get_INTFLAGD_ADC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_ADC) >> PAC_INTFLAGD_ADC_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_ADC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_ADC; +} + +static inline bool hri_pac_get_INTFLAGD_AC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_AC) >> PAC_INTFLAGD_AC_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_AC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_AC; +} + +static inline bool hri_pac_get_INTFLAGD_PTC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_PTC) >> PAC_INTFLAGD_PTC_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_PTC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_PTC; +} + +static inline bool hri_pac_get_INTFLAGD_OPAMP_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_OPAMP) >> PAC_INTFLAGD_OPAMP_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_OPAMP_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_OPAMP; +} + +static inline bool hri_pac_get_INTFLAGD_CCL_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_CCL) >> PAC_INTFLAGD_CCL_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_CCL_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_CCL; +} + +static inline hri_pac_intflagd_reg_t hri_pac_get_INTFLAGD_reg(const void *const hw, hri_pac_intflagd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGD.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflagd_reg_t hri_pac_read_INTFLAGD_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGD.reg; +} + +static inline void hri_pac_clear_INTFLAGD_reg(const void *const hw, hri_pac_intflagd_reg_t mask) +{ + ((Pac *)hw)->INTFLAGD.reg = mask; +} + +static inline bool hri_pac_get_INTFLAGE_PAC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGE.reg & PAC_INTFLAGE_PAC) >> PAC_INTFLAGE_PAC_Pos; +} + +static inline void hri_pac_clear_INTFLAGE_PAC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGE.reg = PAC_INTFLAGE_PAC; +} + +static inline bool hri_pac_get_INTFLAGE_DMAC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGE.reg & PAC_INTFLAGE_DMAC) >> PAC_INTFLAGE_DMAC_Pos; +} + +static inline void hri_pac_clear_INTFLAGE_DMAC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGE.reg = PAC_INTFLAGE_DMAC; +} + +static inline hri_pac_intflage_reg_t hri_pac_get_INTFLAGE_reg(const void *const hw, hri_pac_intflage_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflage_reg_t hri_pac_read_INTFLAGE_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGE.reg; +} + +static inline void hri_pac_clear_INTFLAGE_reg(const void *const hw, hri_pac_intflage_reg_t mask) +{ + ((Pac *)hw)->INTFLAGE.reg = mask; +} + +static inline void hri_pac_set_INTEN_ERR_bit(const void *const hw) +{ + ((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR; +} + +static inline bool hri_pac_get_INTEN_ERR_bit(const void *const hw) +{ + return (((Pac *)hw)->INTENSET.reg & PAC_INTENSET_ERR) >> PAC_INTENSET_ERR_Pos; +} + +static inline void hri_pac_write_INTEN_ERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR; + } else { + ((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR; + } +} + +static inline void hri_pac_clear_INTEN_ERR_bit(const void *const hw) +{ + ((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR; +} + +static inline void hri_pac_set_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) +{ + ((Pac *)hw)->INTENSET.reg = mask; +} + +static inline hri_pac_intenset_reg_t hri_pac_get_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pac *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intenset_reg_t hri_pac_read_INTEN_reg(const void *const hw) +{ + return ((Pac *)hw)->INTENSET.reg; +} + +static inline void hri_pac_write_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t data) +{ + ((Pac *)hw)->INTENSET.reg = data; + ((Pac *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_pac_clear_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) +{ + ((Pac *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_pac_get_STATUSA_PM_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_PM) >> PAC_STATUSA_PM_Pos; +} + +static inline bool hri_pac_get_STATUSA_MCLK_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_MCLK) >> PAC_STATUSA_MCLK_Pos; +} + +static inline bool hri_pac_get_STATUSA_RSTC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_RSTC) >> PAC_STATUSA_RSTC_Pos; +} + +static inline bool hri_pac_get_STATUSA_OSCCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_OSCCTRL) >> PAC_STATUSA_OSCCTRL_Pos; +} + +static inline bool hri_pac_get_STATUSA_OSC32KCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_OSC32KCTRL) >> PAC_STATUSA_OSC32KCTRL_Pos; +} + +static inline bool hri_pac_get_STATUSA_SUPC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SUPC) >> PAC_STATUSA_SUPC_Pos; +} + +static inline bool hri_pac_get_STATUSA_GCLK_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_GCLK) >> PAC_STATUSA_GCLK_Pos; +} + +static inline bool hri_pac_get_STATUSA_WDT_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_WDT) >> PAC_STATUSA_WDT_Pos; +} + +static inline bool hri_pac_get_STATUSA_RTC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_RTC) >> PAC_STATUSA_RTC_Pos; +} + +static inline bool hri_pac_get_STATUSA_EIC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_EIC) >> PAC_STATUSA_EIC_Pos; +} + +static inline bool hri_pac_get_STATUSA_PORT_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_PORT) >> PAC_STATUSA_PORT_Pos; +} + +static inline hri_pac_statusa_reg_t hri_pac_get_STATUSA_reg(const void *const hw, hri_pac_statusa_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->STATUSA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_statusa_reg_t hri_pac_read_STATUSA_reg(const void *const hw) +{ + return ((Pac *)hw)->STATUSA.reg; +} + +static inline bool hri_pac_get_STATUSB_USB_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_USB) >> PAC_STATUSB_USB_Pos; +} + +static inline bool hri_pac_get_STATUSB_DSU_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_DSU) >> PAC_STATUSB_DSU_Pos; +} + +static inline bool hri_pac_get_STATUSB_NVMCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_NVMCTRL) >> PAC_STATUSB_NVMCTRL_Pos; +} + +static inline bool hri_pac_get_STATUSB_MTB_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_MTB) >> PAC_STATUSB_MTB_Pos; +} + +static inline hri_pac_statusb_reg_t hri_pac_get_STATUSB_reg(const void *const hw, hri_pac_statusb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->STATUSB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_statusb_reg_t hri_pac_read_STATUSB_reg(const void *const hw) +{ + return ((Pac *)hw)->STATUSB.reg; +} + +static inline bool hri_pac_get_STATUSC_SERCOM0_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM0) >> PAC_STATUSC_SERCOM0_Pos; +} + +static inline bool hri_pac_get_STATUSC_SERCOM1_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM1) >> PAC_STATUSC_SERCOM1_Pos; +} + +static inline bool hri_pac_get_STATUSC_SERCOM2_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM2) >> PAC_STATUSC_SERCOM2_Pos; +} + +static inline bool hri_pac_get_STATUSC_SERCOM3_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM3) >> PAC_STATUSC_SERCOM3_Pos; +} + +static inline bool hri_pac_get_STATUSC_SERCOM4_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_SERCOM4) >> PAC_STATUSC_SERCOM4_Pos; +} + +static inline bool hri_pac_get_STATUSC_TCC0_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TCC0) >> PAC_STATUSC_TCC0_Pos; +} + +static inline bool hri_pac_get_STATUSC_TCC1_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TCC1) >> PAC_STATUSC_TCC1_Pos; +} + +static inline bool hri_pac_get_STATUSC_TCC2_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TCC2) >> PAC_STATUSC_TCC2_Pos; +} + +static inline bool hri_pac_get_STATUSC_TC0_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC0) >> PAC_STATUSC_TC0_Pos; +} + +static inline bool hri_pac_get_STATUSC_TC1_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC1) >> PAC_STATUSC_TC1_Pos; +} + +static inline bool hri_pac_get_STATUSC_TC2_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC2) >> PAC_STATUSC_TC2_Pos; +} + +static inline bool hri_pac_get_STATUSC_TC3_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC3) >> PAC_STATUSC_TC3_Pos; +} + +static inline bool hri_pac_get_STATUSC_DAC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_DAC) >> PAC_STATUSC_DAC_Pos; +} + +static inline bool hri_pac_get_STATUSC_AES_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_AES) >> PAC_STATUSC_AES_Pos; +} + +static inline bool hri_pac_get_STATUSC_TRNG_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TRNG) >> PAC_STATUSC_TRNG_Pos; +} + +static inline hri_pac_statusc_reg_t hri_pac_get_STATUSC_reg(const void *const hw, hri_pac_statusc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->STATUSC.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_statusc_reg_t hri_pac_read_STATUSC_reg(const void *const hw) +{ + return ((Pac *)hw)->STATUSC.reg; +} + +static inline bool hri_pac_get_STATUSD_EVSYS_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_EVSYS) >> PAC_STATUSD_EVSYS_Pos; +} + +static inline bool hri_pac_get_STATUSD_SERCOM5_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM5) >> PAC_STATUSD_SERCOM5_Pos; +} + +static inline bool hri_pac_get_STATUSD_TC4_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_TC4) >> PAC_STATUSD_TC4_Pos; +} + +static inline bool hri_pac_get_STATUSD_ADC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_ADC) >> PAC_STATUSD_ADC_Pos; +} + +static inline bool hri_pac_get_STATUSD_AC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_AC) >> PAC_STATUSD_AC_Pos; +} + +static inline bool hri_pac_get_STATUSD_PTC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_PTC) >> PAC_STATUSD_PTC_Pos; +} + +static inline bool hri_pac_get_STATUSD_OPAMP_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_OPAMP) >> PAC_STATUSD_OPAMP_Pos; +} + +static inline bool hri_pac_get_STATUSD_CCL_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_CCL) >> PAC_STATUSD_CCL_Pos; +} + +static inline hri_pac_statusd_reg_t hri_pac_get_STATUSD_reg(const void *const hw, hri_pac_statusd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->STATUSD.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_statusd_reg_t hri_pac_read_STATUSD_reg(const void *const hw) +{ + return ((Pac *)hw)->STATUSD.reg; +} + +static inline bool hri_pac_get_STATUSE_PAC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSE.reg & PAC_STATUSE_PAC) >> PAC_STATUSE_PAC_Pos; +} + +static inline bool hri_pac_get_STATUSE_DMAC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSE.reg & PAC_STATUSE_DMAC) >> PAC_STATUSE_DMAC_Pos; +} + +static inline hri_pac_statuse_reg_t hri_pac_get_STATUSE_reg(const void *const hw, hri_pac_statuse_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->STATUSE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_statuse_reg_t hri_pac_read_STATUSE_reg(const void *const hw) +{ + return ((Pac *)hw)->STATUSE.reg; +} + +static inline void hri_pac_set_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg |= PAC_WRCTRL_PERID(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp = (tmp & PAC_WRCTRL_PERID(mask)) >> PAC_WRCTRL_PERID_Pos; + return tmp; +} + +static inline void hri_pac_write_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t data) +{ + uint32_t tmp; + PAC_CRITICAL_SECTION_ENTER(); + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp &= ~PAC_WRCTRL_PERID_Msk; + tmp |= PAC_WRCTRL_PERID(data); + ((Pac *)hw)->WRCTRL.reg = tmp; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg &= ~PAC_WRCTRL_PERID(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg ^= PAC_WRCTRL_PERID(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_PERID_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp = (tmp & PAC_WRCTRL_PERID_Msk) >> PAC_WRCTRL_PERID_Pos; + return tmp; +} + +static inline void hri_pac_set_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg |= PAC_WRCTRL_KEY(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp = (tmp & PAC_WRCTRL_KEY(mask)) >> PAC_WRCTRL_KEY_Pos; + return tmp; +} + +static inline void hri_pac_write_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t data) +{ + uint32_t tmp; + PAC_CRITICAL_SECTION_ENTER(); + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp &= ~PAC_WRCTRL_KEY_Msk; + tmp |= PAC_WRCTRL_KEY(data); + ((Pac *)hw)->WRCTRL.reg = tmp; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg &= ~PAC_WRCTRL_KEY(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg ^= PAC_WRCTRL_KEY(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_KEY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp = (tmp & PAC_WRCTRL_KEY_Msk) >> PAC_WRCTRL_KEY_Pos; + return tmp; +} + +static inline void hri_pac_set_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg |= mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pac_write_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t data) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg = data; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg &= ~mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg ^= mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_reg(const void *const hw) +{ + return ((Pac *)hw)->WRCTRL.reg; +} + +static inline void hri_pac_set_EVCTRL_ERREO_bit(const void *const hw) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg |= PAC_EVCTRL_ERREO; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pac_get_EVCTRL_ERREO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pac *)hw)->EVCTRL.reg; + tmp = (tmp & PAC_EVCTRL_ERREO) >> PAC_EVCTRL_ERREO_Pos; + return (bool)tmp; +} + +static inline void hri_pac_write_EVCTRL_ERREO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + PAC_CRITICAL_SECTION_ENTER(); + tmp = ((Pac *)hw)->EVCTRL.reg; + tmp &= ~PAC_EVCTRL_ERREO; + tmp |= value << PAC_EVCTRL_ERREO_Pos; + ((Pac *)hw)->EVCTRL.reg = tmp; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_EVCTRL_ERREO_bit(const void *const hw) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg &= ~PAC_EVCTRL_ERREO; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_EVCTRL_ERREO_bit(const void *const hw) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg ^= PAC_EVCTRL_ERREO; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_set_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg |= mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_evctrl_reg_t hri_pac_get_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pac *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pac_write_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t data) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg = data; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg &= ~mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg ^= mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_evctrl_reg_t hri_pac_read_EVCTRL_reg(const void *const hw) +{ + return ((Pac *)hw)->EVCTRL.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PAC_L21_H_INCLUDED */ +#endif /* _SAML21_PAC_COMPONENT_ */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_pm_l21.h b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_pm_l21.h new file mode 100644 index 00000000..c36d148a --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_pm_l21.h @@ -0,0 +1,994 @@ +/** + * \file + * + * \brief SAM PM + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_PM_COMPONENT_ +#ifndef _HRI_PM_L21_H_INCLUDED_ +#define _HRI_PM_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PM_CRITICAL_SECTIONS) +#define PM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PM_CRITICAL_SECTION_ENTER() +#define PM_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_pm_stdbycfg_reg_t; +typedef uint8_t hri_pm_ctrla_reg_t; +typedef uint8_t hri_pm_intenset_reg_t; +typedef uint8_t hri_pm_intflag_reg_t; +typedef uint8_t hri_pm_plcfg_reg_t; +typedef uint8_t hri_pm_pwsakdly_reg_t; +typedef uint8_t hri_pm_sleepcfg_reg_t; + +static inline bool hri_pm_get_INTFLAG_PLRDY_bit(const void *const hw) +{ + return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_PLRDY) >> PM_INTFLAG_PLRDY_Pos; +} + +static inline void hri_pm_clear_INTFLAG_PLRDY_bit(const void *const hw) +{ + ((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_PLRDY; +} + +static inline bool hri_pm_get_interrupt_PLRDY_bit(const void *const hw) +{ + return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_PLRDY) >> PM_INTFLAG_PLRDY_Pos; +} + +static inline void hri_pm_clear_interrupt_PLRDY_bit(const void *const hw) +{ + ((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_PLRDY; +} + +static inline hri_pm_intflag_reg_t hri_pm_get_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pm_intflag_reg_t hri_pm_read_INTFLAG_reg(const void *const hw) +{ + return ((Pm *)hw)->INTFLAG.reg; +} + +static inline void hri_pm_clear_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask) +{ + ((Pm *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_pm_set_INTEN_PLRDY_bit(const void *const hw) +{ + ((Pm *)hw)->INTENSET.reg = PM_INTENSET_PLRDY; +} + +static inline bool hri_pm_get_INTEN_PLRDY_bit(const void *const hw) +{ + return (((Pm *)hw)->INTENSET.reg & PM_INTENSET_PLRDY) >> PM_INTENSET_PLRDY_Pos; +} + +static inline void hri_pm_write_INTEN_PLRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pm *)hw)->INTENCLR.reg = PM_INTENSET_PLRDY; + } else { + ((Pm *)hw)->INTENSET.reg = PM_INTENSET_PLRDY; + } +} + +static inline void hri_pm_clear_INTEN_PLRDY_bit(const void *const hw) +{ + ((Pm *)hw)->INTENCLR.reg = PM_INTENSET_PLRDY; +} + +static inline void hri_pm_set_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) +{ + ((Pm *)hw)->INTENSET.reg = mask; +} + +static inline hri_pm_intenset_reg_t hri_pm_get_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pm_intenset_reg_t hri_pm_read_INTEN_reg(const void *const hw) +{ + return ((Pm *)hw)->INTENSET.reg; +} + +static inline void hri_pm_write_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t data) +{ + ((Pm *)hw)->INTENSET.reg = data; + ((Pm *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_pm_clear_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) +{ + ((Pm *)hw)->INTENCLR.reg = mask; +} + +static inline void hri_pm_set_CTRLA_IORET_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg |= PM_CTRLA_IORET; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_CTRLA_IORET_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->CTRLA.reg; + tmp = (tmp & PM_CTRLA_IORET) >> PM_CTRLA_IORET_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_CTRLA_IORET_bit(const void *const hw, bool value) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->CTRLA.reg; + tmp &= ~PM_CTRLA_IORET; + tmp |= value << PM_CTRLA_IORET_Pos; + ((Pm *)hw)->CTRLA.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_CTRLA_IORET_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg &= ~PM_CTRLA_IORET; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_CTRLA_IORET_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg ^= PM_CTRLA_IORET; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_ctrla_reg_t hri_pm_get_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_ctrla_reg_t hri_pm_read_CTRLA_reg(const void *const hw) +{ + return ((Pm *)hw)->CTRLA.reg; +} + +static inline void hri_pm_set_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg |= PM_SLEEPCFG_SLEEPMODE(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->SLEEPCFG.reg; + tmp = (tmp & PM_SLEEPCFG_SLEEPMODE(mask)) >> PM_SLEEPCFG_SLEEPMODE_Pos; + return tmp; +} + +static inline void hri_pm_write_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->SLEEPCFG.reg; + tmp &= ~PM_SLEEPCFG_SLEEPMODE_Msk; + tmp |= PM_SLEEPCFG_SLEEPMODE(data); + ((Pm *)hw)->SLEEPCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg &= ~PM_SLEEPCFG_SLEEPMODE(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg ^= PM_SLEEPCFG_SLEEPMODE(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_SLEEPMODE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->SLEEPCFG.reg; + tmp = (tmp & PM_SLEEPCFG_SLEEPMODE_Msk) >> PM_SLEEPCFG_SLEEPMODE_Pos; + return tmp; +} + +static inline void hri_pm_set_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->SLEEPCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_reg(const void *const hw) +{ + return ((Pm *)hw)->SLEEPCFG.reg; +} + +static inline void hri_pm_set_PLCFG_PLDIS_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PLCFG.reg |= PM_PLCFG_PLDIS; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_PLCFG_PLDIS_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->PLCFG.reg; + tmp = (tmp & PM_PLCFG_PLDIS) >> PM_PLCFG_PLDIS_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_PLCFG_PLDIS_bit(const void *const hw, bool value) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->PLCFG.reg; + tmp &= ~PM_PLCFG_PLDIS; + tmp |= value << PM_PLCFG_PLDIS_Pos; + ((Pm *)hw)->PLCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_PLCFG_PLDIS_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PLCFG.reg &= ~PM_PLCFG_PLDIS; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_PLCFG_PLDIS_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PLCFG.reg ^= PM_PLCFG_PLDIS; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PLCFG.reg |= PM_PLCFG_PLSEL(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_plcfg_reg_t hri_pm_get_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->PLCFG.reg; + tmp = (tmp & PM_PLCFG_PLSEL(mask)) >> PM_PLCFG_PLSEL_Pos; + return tmp; +} + +static inline void hri_pm_write_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->PLCFG.reg; + tmp &= ~PM_PLCFG_PLSEL_Msk; + tmp |= PM_PLCFG_PLSEL(data); + ((Pm *)hw)->PLCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PLCFG.reg &= ~PM_PLCFG_PLSEL(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PLCFG.reg ^= PM_PLCFG_PLSEL(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_plcfg_reg_t hri_pm_read_PLCFG_PLSEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->PLCFG.reg; + tmp = (tmp & PM_PLCFG_PLSEL_Msk) >> PM_PLCFG_PLSEL_Pos; + return tmp; +} + +static inline void hri_pm_set_PLCFG_reg(const void *const hw, hri_pm_plcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PLCFG.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_plcfg_reg_t hri_pm_get_PLCFG_reg(const void *const hw, hri_pm_plcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->PLCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_PLCFG_reg(const void *const hw, hri_pm_plcfg_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PLCFG.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_PLCFG_reg(const void *const hw, hri_pm_plcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PLCFG.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_PLCFG_reg(const void *const hw, hri_pm_plcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PLCFG.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_plcfg_reg_t hri_pm_read_PLCFG_reg(const void *const hw) +{ + return ((Pm *)hw)->PLCFG.reg; +} + +static inline void hri_pm_set_STDBYCFG_DPGPD0_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_DPGPD0; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_STDBYCFG_DPGPD0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_DPGPD0) >> PM_STDBYCFG_DPGPD0_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_STDBYCFG_DPGPD0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp &= ~PM_STDBYCFG_DPGPD0; + tmp |= value << PM_STDBYCFG_DPGPD0_Pos; + ((Pm *)hw)->STDBYCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_STDBYCFG_DPGPD0_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_DPGPD0; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_STDBYCFG_DPGPD0_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_DPGPD0; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_STDBYCFG_DPGPD1_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_DPGPD1; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_STDBYCFG_DPGPD1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_DPGPD1) >> PM_STDBYCFG_DPGPD1_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_STDBYCFG_DPGPD1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp &= ~PM_STDBYCFG_DPGPD1; + tmp |= value << PM_STDBYCFG_DPGPD1_Pos; + ((Pm *)hw)->STDBYCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_STDBYCFG_DPGPD1_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_DPGPD1; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_STDBYCFG_DPGPD1_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_DPGPD1; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_STDBYCFG_PDCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_PDCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_PDCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + uint16_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_PDCFG(mask)) >> PM_STDBYCFG_PDCFG_Pos; + return tmp; +} + +static inline void hri_pm_write_STDBYCFG_PDCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t data) +{ + uint16_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp &= ~PM_STDBYCFG_PDCFG_Msk; + tmp |= PM_STDBYCFG_PDCFG(data); + ((Pm *)hw)->STDBYCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_STDBYCFG_PDCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_PDCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_STDBYCFG_PDCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_PDCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_PDCFG_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_PDCFG_Msk) >> PM_STDBYCFG_PDCFG_Pos; + return tmp; +} + +static inline void hri_pm_set_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_VREGSMOD(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + uint16_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_VREGSMOD(mask)) >> PM_STDBYCFG_VREGSMOD_Pos; + return tmp; +} + +static inline void hri_pm_write_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t data) +{ + uint16_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp &= ~PM_STDBYCFG_VREGSMOD_Msk; + tmp |= PM_STDBYCFG_VREGSMOD(data); + ((Pm *)hw)->STDBYCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_VREGSMOD(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_VREGSMOD(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_VREGSMOD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_VREGSMOD_Msk) >> PM_STDBYCFG_VREGSMOD_Pos; + return tmp; +} + +static inline void hri_pm_set_STDBYCFG_LINKPD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_LINKPD(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_LINKPD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + uint16_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_LINKPD(mask)) >> PM_STDBYCFG_LINKPD_Pos; + return tmp; +} + +static inline void hri_pm_write_STDBYCFG_LINKPD_bf(const void *const hw, hri_pm_stdbycfg_reg_t data) +{ + uint16_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp &= ~PM_STDBYCFG_LINKPD_Msk; + tmp |= PM_STDBYCFG_LINKPD(data); + ((Pm *)hw)->STDBYCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_STDBYCFG_LINKPD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_LINKPD(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_STDBYCFG_LINKPD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_LINKPD(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_LINKPD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_LINKPD_Msk) >> PM_STDBYCFG_LINKPD_Pos; + return tmp; +} + +static inline void hri_pm_set_STDBYCFG_BBIASHS_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_BBIASHS(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_BBIASHS_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + uint16_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_BBIASHS(mask)) >> PM_STDBYCFG_BBIASHS_Pos; + return tmp; +} + +static inline void hri_pm_write_STDBYCFG_BBIASHS_bf(const void *const hw, hri_pm_stdbycfg_reg_t data) +{ + uint16_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp &= ~PM_STDBYCFG_BBIASHS_Msk; + tmp |= PM_STDBYCFG_BBIASHS(data); + ((Pm *)hw)->STDBYCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_STDBYCFG_BBIASHS_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_BBIASHS(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_STDBYCFG_BBIASHS_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_BBIASHS(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_BBIASHS_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_BBIASHS_Msk) >> PM_STDBYCFG_BBIASHS_Pos; + return tmp; +} + +static inline void hri_pm_set_STDBYCFG_BBIASLP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_BBIASLP(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_BBIASLP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + uint16_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_BBIASLP(mask)) >> PM_STDBYCFG_BBIASLP_Pos; + return tmp; +} + +static inline void hri_pm_write_STDBYCFG_BBIASLP_bf(const void *const hw, hri_pm_stdbycfg_reg_t data) +{ + uint16_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp &= ~PM_STDBYCFG_BBIASLP_Msk; + tmp |= PM_STDBYCFG_BBIASLP(data); + ((Pm *)hw)->STDBYCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_STDBYCFG_BBIASLP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_BBIASLP(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_STDBYCFG_BBIASLP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_BBIASLP(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_BBIASLP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_BBIASLP_Msk) >> PM_STDBYCFG_BBIASLP_Pos; + return tmp; +} + +static inline void hri_pm_set_STDBYCFG_BBIASPP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_BBIASPP(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_BBIASPP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + uint16_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_BBIASPP(mask)) >> PM_STDBYCFG_BBIASPP_Pos; + return tmp; +} + +static inline void hri_pm_write_STDBYCFG_BBIASPP_bf(const void *const hw, hri_pm_stdbycfg_reg_t data) +{ + uint16_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp &= ~PM_STDBYCFG_BBIASPP_Msk; + tmp |= PM_STDBYCFG_BBIASPP(data); + ((Pm *)hw)->STDBYCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_STDBYCFG_BBIASPP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_BBIASPP(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_STDBYCFG_BBIASPP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_BBIASPP(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_BBIASPP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_BBIASPP_Msk) >> PM_STDBYCFG_BBIASPP_Pos; + return tmp; +} + +static inline void hri_pm_set_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + uint16_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_reg(const void *const hw) +{ + return ((Pm *)hw)->STDBYCFG.reg; +} + +static inline void hri_pm_set_PWSAKDLY_IGNACK_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg |= PM_PWSAKDLY_IGNACK; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_PWSAKDLY_IGNACK_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->PWSAKDLY.reg; + tmp = (tmp & PM_PWSAKDLY_IGNACK) >> PM_PWSAKDLY_IGNACK_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_PWSAKDLY_IGNACK_bit(const void *const hw, bool value) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->PWSAKDLY.reg; + tmp &= ~PM_PWSAKDLY_IGNACK; + tmp |= value << PM_PWSAKDLY_IGNACK_Pos; + ((Pm *)hw)->PWSAKDLY.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_PWSAKDLY_IGNACK_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg &= ~PM_PWSAKDLY_IGNACK; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_PWSAKDLY_IGNACK_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg ^= PM_PWSAKDLY_IGNACK; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg |= PM_PWSAKDLY_DLYVAL(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_pwsakdly_reg_t hri_pm_get_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->PWSAKDLY.reg; + tmp = (tmp & PM_PWSAKDLY_DLYVAL(mask)) >> PM_PWSAKDLY_DLYVAL_Pos; + return tmp; +} + +static inline void hri_pm_write_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->PWSAKDLY.reg; + tmp &= ~PM_PWSAKDLY_DLYVAL_Msk; + tmp |= PM_PWSAKDLY_DLYVAL(data); + ((Pm *)hw)->PWSAKDLY.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg &= ~PM_PWSAKDLY_DLYVAL(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg ^= PM_PWSAKDLY_DLYVAL(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_pwsakdly_reg_t hri_pm_read_PWSAKDLY_DLYVAL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->PWSAKDLY.reg; + tmp = (tmp & PM_PWSAKDLY_DLYVAL_Msk) >> PM_PWSAKDLY_DLYVAL_Pos; + return tmp; +} + +static inline void hri_pm_set_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_pwsakdly_reg_t hri_pm_get_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->PWSAKDLY.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_pwsakdly_reg_t hri_pm_read_PWSAKDLY_reg(const void *const hw) +{ + return ((Pm *)hw)->PWSAKDLY.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PM_L21_H_INCLUDED */ +#endif /* _SAML21_PM_COMPONENT_ */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_port_l21.h b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_port_l21.h new file mode 100644 index 00000000..374ca612 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_port_l21.h @@ -0,0 +1,2528 @@ +/** + * \file + * + * \brief SAM PORT + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_PORT_COMPONENT_ +#ifndef _HRI_PORT_L21_H_INCLUDED_ +#define _HRI_PORT_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PORT_CRITICAL_SECTIONS) +#define PORT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PORT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PORT_CRITICAL_SECTION_ENTER() +#define PORT_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_port_ctrl_reg_t; +typedef uint32_t hri_port_dir_reg_t; +typedef uint32_t hri_port_evctrl_reg_t; +typedef uint32_t hri_port_in_reg_t; +typedef uint32_t hri_port_out_reg_t; +typedef uint32_t hri_port_wrconfig_reg_t; +typedef uint32_t hri_portgroup_ctrl_reg_t; +typedef uint32_t hri_portgroup_dir_reg_t; +typedef uint32_t hri_portgroup_evctrl_reg_t; +typedef uint32_t hri_portgroup_in_reg_t; +typedef uint32_t hri_portgroup_out_reg_t; +typedef uint32_t hri_portgroup_wrconfig_reg_t; +typedef uint8_t hri_port_pincfg_reg_t; +typedef uint8_t hri_port_pmux_reg_t; +typedef uint8_t hri_portgroup_pincfg_reg_t; +typedef uint8_t hri_portgroup_pmux_reg_t; + +static inline void hri_portgroup_set_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRSET.reg = PORT_DIR_DIR(mask); +} + +static inline hri_port_dir_reg_t hri_portgroup_get_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->DIR.reg; + tmp = (tmp & PORT_DIR_DIR(mask)) >> PORT_DIR_DIR_Pos; + return tmp; +} + +static inline hri_port_dir_reg_t hri_portgroup_read_DIR_DIR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->DIR.reg; + tmp = (tmp & PORT_DIR_DIR_Msk) >> PORT_DIR_DIR_Pos; + return tmp; +} + +static inline void hri_portgroup_write_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t data) +{ + ((PortGroup *)hw)->DIRSET.reg = PORT_DIR_DIR(data); + ((PortGroup *)hw)->DIRCLR.reg = ~PORT_DIR_DIR(data); +} + +static inline void hri_portgroup_clear_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRCLR.reg = PORT_DIR_DIR(mask); +} + +static inline void hri_portgroup_toggle_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRTGL.reg = PORT_DIR_DIR(mask); +} + +static inline void hri_portgroup_set_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRSET.reg = mask; +} + +static inline hri_port_dir_reg_t hri_portgroup_get_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->DIR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_dir_reg_t hri_portgroup_read_DIR_reg(const void *const hw) +{ + return ((PortGroup *)hw)->DIR.reg; +} + +static inline void hri_portgroup_write_DIR_reg(const void *const hw, hri_port_dir_reg_t data) +{ + ((PortGroup *)hw)->DIRSET.reg = data; + ((PortGroup *)hw)->DIRCLR.reg = ~data; +} + +static inline void hri_portgroup_clear_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRCLR.reg = mask; +} + +static inline void hri_portgroup_toggle_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRTGL.reg = mask; +} + +static inline void hri_portgroup_set_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTSET.reg = PORT_OUT_OUT(mask); +} + +static inline hri_port_out_reg_t hri_portgroup_get_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->OUT.reg; + tmp = (tmp & PORT_OUT_OUT(mask)) >> PORT_OUT_OUT_Pos; + return tmp; +} + +static inline hri_port_out_reg_t hri_portgroup_read_OUT_OUT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->OUT.reg; + tmp = (tmp & PORT_OUT_OUT_Msk) >> PORT_OUT_OUT_Pos; + return tmp; +} + +static inline void hri_portgroup_write_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t data) +{ + ((PortGroup *)hw)->OUTSET.reg = PORT_OUT_OUT(data); + ((PortGroup *)hw)->OUTCLR.reg = ~PORT_OUT_OUT(data); +} + +static inline void hri_portgroup_clear_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTCLR.reg = PORT_OUT_OUT(mask); +} + +static inline void hri_portgroup_toggle_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTTGL.reg = PORT_OUT_OUT(mask); +} + +static inline void hri_portgroup_set_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTSET.reg = mask; +} + +static inline hri_port_out_reg_t hri_portgroup_get_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->OUT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_out_reg_t hri_portgroup_read_OUT_reg(const void *const hw) +{ + return ((PortGroup *)hw)->OUT.reg; +} + +static inline void hri_portgroup_write_OUT_reg(const void *const hw, hri_port_out_reg_t data) +{ + ((PortGroup *)hw)->OUTSET.reg = data; + ((PortGroup *)hw)->OUTCLR.reg = ~data; +} + +static inline void hri_portgroup_clear_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTCLR.reg = mask; +} + +static inline void hri_portgroup_toggle_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTTGL.reg = mask; +} + +static inline hri_port_in_reg_t hri_portgroup_get_IN_IN_bf(const void *const hw, hri_port_in_reg_t mask) +{ + return (((PortGroup *)hw)->IN.reg & PORT_IN_IN(mask)) >> PORT_IN_IN_Pos; +} + +static inline hri_port_in_reg_t hri_portgroup_read_IN_IN_bf(const void *const hw) +{ + return (((PortGroup *)hw)->IN.reg & PORT_IN_IN_Msk) >> PORT_IN_IN_Pos; +} + +static inline hri_port_in_reg_t hri_portgroup_get_IN_reg(const void *const hw, hri_port_in_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->IN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_in_reg_t hri_portgroup_read_IN_reg(const void *const hw) +{ + return ((PortGroup *)hw)->IN.reg; +} + +static inline void hri_portgroup_set_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg |= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_portgroup_write_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp &= ~PORT_CTRL_SAMPLING_Msk; + tmp |= PORT_CTRL_SAMPLING(data); + ((PortGroup *)hw)->CTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg &= ~PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg ^= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_SAMPLING_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_portgroup_set_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_portgroup_write_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_reg(const void *const hw) +{ + return ((PortGroup *)hw)->CTRL.reg; +} + +static inline void hri_portgroup_set_EVCTRL_PORTEI0_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_EVCTRL_PORTEI0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI0) >> PORT_EVCTRL_PORTEI0_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PORTEI0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI0; + tmp |= value << PORT_EVCTRL_PORTEI0_Pos; + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PORTEI0_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PORTEI0_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_EVCTRL_PORTEI1_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_EVCTRL_PORTEI1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI1) >> PORT_EVCTRL_PORTEI1_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PORTEI1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI1; + tmp |= value << PORT_EVCTRL_PORTEI1_Pos; + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PORTEI1_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PORTEI1_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_EVCTRL_PORTEI2_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_EVCTRL_PORTEI2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI2) >> PORT_EVCTRL_PORTEI2_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PORTEI2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI2; + tmp |= value << PORT_EVCTRL_PORTEI2_Pos; + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PORTEI2_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PORTEI2_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_EVCTRL_PORTEI3_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_EVCTRL_PORTEI3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI3) >> PORT_EVCTRL_PORTEI3_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PORTEI3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI3; + tmp |= value << PORT_EVCTRL_PORTEI3_Pos; + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PORTEI3_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PORTEI3_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID0(mask)) >> PORT_EVCTRL_PID0_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID0_Msk; + tmp |= PORT_EVCTRL_PID0(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID0_Msk) >> PORT_EVCTRL_PID0_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT0(mask)) >> PORT_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT0_Msk; + tmp |= PORT_EVCTRL_EVACT0(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT0_Msk) >> PORT_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID1(mask)) >> PORT_EVCTRL_PID1_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID1_Msk; + tmp |= PORT_EVCTRL_PID1(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID1_Msk) >> PORT_EVCTRL_PID1_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT1(mask)) >> PORT_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT1_Msk; + tmp |= PORT_EVCTRL_EVACT1(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT1_Msk) >> PORT_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID2(mask)) >> PORT_EVCTRL_PID2_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID2_Msk; + tmp |= PORT_EVCTRL_PID2(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID2_Msk) >> PORT_EVCTRL_PID2_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT2(mask)) >> PORT_EVCTRL_EVACT2_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT2_Msk; + tmp |= PORT_EVCTRL_EVACT2(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT2_Msk) >> PORT_EVCTRL_EVACT2_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID3(mask)) >> PORT_EVCTRL_PID3_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID3_Msk; + tmp |= PORT_EVCTRL_PID3(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID3_Msk) >> PORT_EVCTRL_PID3_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT3(mask)) >> PORT_EVCTRL_EVACT3_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT3_Msk; + tmp |= PORT_EVCTRL_EVACT3(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT3_Msk) >> PORT_EVCTRL_EVACT3_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_reg(const void *const hw) +{ + return ((PortGroup *)hw)->EVCTRL.reg; +} + +static inline void hri_portgroup_set_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXE_bf(const void *const hw, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_portgroup_write_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXE_Msk; + tmp |= PORT_PMUX_PMUXE(data); + ((PortGroup *)hw)->PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXE_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_portgroup_set_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXO_bf(const void *const hw, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_portgroup_write_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXO_Msk; + tmp |= PORT_PMUX_PMUXO(data); + ((PortGroup *)hw)->PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXO_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_portgroup_set_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_reg(const void *const hw, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_portgroup_write_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_reg(const void *const hw, uint8_t index) +{ + return ((PortGroup *)hw)->PMUX[index].reg; +} + +static inline void hri_portgroup_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PMUXEN; + tmp |= value << PORT_PINCFG_PMUXEN_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_INEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_INEN; + tmp |= value << PORT_PINCFG_INEN_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PULLEN; + tmp |= value << PORT_PINCFG_PULLEN_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_DRVSTR; + tmp |= value << PORT_PINCFG_DRVSTR_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_portgroup_get_PINCFG_reg(const void *const hw, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_portgroup_write_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_portgroup_read_PINCFG_reg(const void *const hw, uint8_t index) +{ + return ((PortGroup *)hw)->PINCFG[index].reg; +} + +static inline void hri_portgroup_write_WRCONFIG_reg(const void *const hw, hri_port_wrconfig_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->WRCONFIG.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRSET.reg = PORT_DIR_DIR(mask); +} + +static inline hri_port_dir_reg_t hri_port_get_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, + hri_port_dir_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].DIR.reg; + tmp = (tmp & PORT_DIR_DIR(mask)) >> PORT_DIR_DIR_Pos; + return tmp; +} + +static inline hri_port_dir_reg_t hri_port_read_DIR_DIR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].DIR.reg; + tmp = (tmp & PORT_DIR_DIR_Msk) >> PORT_DIR_DIR_Pos; + return tmp; +} + +static inline void hri_port_write_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t data) +{ + ((Port *)hw)->Group[submodule_index].DIRSET.reg = PORT_DIR_DIR(data); + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~PORT_DIR_DIR(data); +} + +static inline void hri_port_clear_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = PORT_DIR_DIR(mask); +} + +static inline void hri_port_toggle_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRTGL.reg = PORT_DIR_DIR(mask); +} + +static inline void hri_port_set_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRSET.reg = mask; +} + +static inline hri_port_dir_reg_t hri_port_get_DIR_reg(const void *const hw, uint8_t submodule_index, + hri_port_dir_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].DIR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_dir_reg_t hri_port_read_DIR_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].DIR.reg; +} + +static inline void hri_port_write_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t data) +{ + ((Port *)hw)->Group[submodule_index].DIRSET.reg = data; + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~data; +} + +static inline void hri_port_clear_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask; +} + +static inline void hri_port_toggle_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRTGL.reg = mask; +} + +static inline void hri_port_set_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTSET.reg = PORT_OUT_OUT(mask); +} + +static inline hri_port_out_reg_t hri_port_get_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, + hri_port_out_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].OUT.reg; + tmp = (tmp & PORT_OUT_OUT(mask)) >> PORT_OUT_OUT_Pos; + return tmp; +} + +static inline hri_port_out_reg_t hri_port_read_OUT_OUT_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].OUT.reg; + tmp = (tmp & PORT_OUT_OUT_Msk) >> PORT_OUT_OUT_Pos; + return tmp; +} + +static inline void hri_port_write_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t data) +{ + ((Port *)hw)->Group[submodule_index].OUTSET.reg = PORT_OUT_OUT(data); + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = ~PORT_OUT_OUT(data); +} + +static inline void hri_port_clear_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = PORT_OUT_OUT(mask); +} + +static inline void hri_port_toggle_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTTGL.reg = PORT_OUT_OUT(mask); +} + +static inline void hri_port_set_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTSET.reg = mask; +} + +static inline hri_port_out_reg_t hri_port_get_OUT_reg(const void *const hw, uint8_t submodule_index, + hri_port_out_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].OUT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_out_reg_t hri_port_read_OUT_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].OUT.reg; +} + +static inline void hri_port_write_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t data) +{ + ((Port *)hw)->Group[submodule_index].OUTSET.reg = data; + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = ~data; +} + +static inline void hri_port_clear_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask; +} + +static inline void hri_port_toggle_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTTGL.reg = mask; +} + +static inline hri_port_in_reg_t hri_port_get_IN_IN_bf(const void *const hw, uint8_t submodule_index, + hri_port_in_reg_t mask) +{ + return (((Port *)hw)->Group[submodule_index].IN.reg & PORT_IN_IN(mask)) >> PORT_IN_IN_Pos; +} + +static inline hri_port_in_reg_t hri_port_read_IN_IN_bf(const void *const hw, uint8_t submodule_index) +{ + return (((Port *)hw)->Group[submodule_index].IN.reg & PORT_IN_IN_Msk) >> PORT_IN_IN_Pos; +} + +static inline hri_port_in_reg_t hri_port_get_IN_reg(const void *const hw, uint8_t submodule_index, + hri_port_in_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].IN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_in_reg_t hri_port_read_IN_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].IN.reg; +} + +static inline void hri_port_set_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg |= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_get_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_port_write_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp &= ~PORT_CTRL_SAMPLING_Msk; + tmp |= PORT_CTRL_SAMPLING(data); + ((Port *)hw)->Group[submodule_index].CTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg &= ~PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg ^= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_read_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_port_set_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_get_CTRL_reg(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_port_write_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_read_CTRL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].CTRL.reg; +} + +static inline void hri_port_set_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI0) >> PORT_EVCTRL_PORTEI0_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI0; + tmp |= value << PORT_EVCTRL_PORTEI0_Pos; + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI1) >> PORT_EVCTRL_PORTEI1_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI1; + tmp |= value << PORT_EVCTRL_PORTEI1_Pos; + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI2) >> PORT_EVCTRL_PORTEI2_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI2; + tmp |= value << PORT_EVCTRL_PORTEI2_Pos; + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI3) >> PORT_EVCTRL_PORTEI3_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI3; + tmp |= value << PORT_EVCTRL_PORTEI3_Pos; + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID0(mask)) >> PORT_EVCTRL_PID0_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID0_Msk; + tmp |= PORT_EVCTRL_PID0(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID0_Msk) >> PORT_EVCTRL_PID0_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT0(mask)) >> PORT_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT0_Msk; + tmp |= PORT_EVCTRL_EVACT0(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT0_Msk) >> PORT_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID1(mask)) >> PORT_EVCTRL_PID1_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID1_Msk; + tmp |= PORT_EVCTRL_PID1(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID1_Msk) >> PORT_EVCTRL_PID1_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT1(mask)) >> PORT_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT1_Msk; + tmp |= PORT_EVCTRL_EVACT1(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT1_Msk) >> PORT_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID2(mask)) >> PORT_EVCTRL_PID2_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID2_Msk; + tmp |= PORT_EVCTRL_PID2(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID2_Msk) >> PORT_EVCTRL_PID2_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT2(mask)) >> PORT_EVCTRL_EVACT2_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT2_Msk; + tmp |= PORT_EVCTRL_EVACT2(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT2_Msk) >> PORT_EVCTRL_EVACT2_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID3(mask)) >> PORT_EVCTRL_PID3_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID3_Msk; + tmp |= PORT_EVCTRL_PID3(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID3_Msk) >> PORT_EVCTRL_PID3_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT3(mask)) >> PORT_EVCTRL_EVACT3_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT3_Msk; + tmp |= PORT_EVCTRL_EVACT3(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT3_Msk) >> PORT_EVCTRL_EVACT3_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_reg(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_port_write_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].EVCTRL.reg; +} + +static inline void hri_port_set_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, + uint8_t index, hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_port_write_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXE_Msk; + tmp |= PORT_PMUX_PMUXE(data); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, + uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_port_set_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, + uint8_t index, hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_port_write_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXO_Msk; + tmp |= PORT_PMUX_PMUXO(data); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, + uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_port_set_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_get_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_port_write_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_read_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + return ((Port *)hw)->Group[submodule_index].PMUX[index].reg; +} + +static inline void hri_port_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PMUXEN; + tmp |= value << PORT_PINCFG_PMUXEN_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_INEN; + tmp |= value << PORT_PINCFG_INEN_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PULLEN; + tmp |= value << PORT_PINCFG_PULLEN_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_DRVSTR; + tmp |= value << PORT_PINCFG_DRVSTR_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_port_get_PINCFG_reg(const void *const hw, uint8_t submodule_index, + uint8_t index, hri_port_pincfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_port_write_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_port_read_PINCFG_reg(const void *const hw, uint8_t submodule_index, + uint8_t index) +{ + return ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; +} + +static inline void hri_port_write_WRCONFIG_reg(const void *const hw, uint8_t submodule_index, + hri_port_wrconfig_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PORT_L21_H_INCLUDED */ +#endif /* _SAML21_PORT_COMPONENT_ */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_rstc_l21.h b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_rstc_l21.h new file mode 100644 index 00000000..b62222ad --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_rstc_l21.h @@ -0,0 +1,498 @@ +/** + * \file + * + * \brief SAM RSTC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_RSTC_COMPONENT_ +#ifndef _HRI_RSTC_L21_H_INCLUDED_ +#define _HRI_RSTC_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_RSTC_CRITICAL_SECTIONS) +#define RSTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define RSTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define RSTC_CRITICAL_SECTION_ENTER() +#define RSTC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_rstc_wkcause_reg_t; +typedef uint16_t hri_rstc_wken_reg_t; +typedef uint16_t hri_rstc_wkpol_reg_t; +typedef uint8_t hri_rstc_bkupexit_reg_t; +typedef uint8_t hri_rstc_rcause_reg_t; +typedef uint8_t hri_rstc_wkdbconf_reg_t; + +static inline bool hri_rstc_get_RCAUSE_POR_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_POR) >> RSTC_RCAUSE_POR_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_BOD12_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BOD12) >> RSTC_RCAUSE_BOD12_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_BOD33_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BOD33) >> RSTC_RCAUSE_BOD33_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_EXT_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_EXT) >> RSTC_RCAUSE_EXT_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_WDT_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_WDT) >> RSTC_RCAUSE_WDT_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_SYST_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_SYST) >> RSTC_RCAUSE_SYST_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_BACKUP_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BACKUP) >> RSTC_RCAUSE_BACKUP_Pos; +} + +static inline hri_rstc_rcause_reg_t hri_rstc_get_RCAUSE_reg(const void *const hw, hri_rstc_rcause_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rstc *)hw)->RCAUSE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rstc_rcause_reg_t hri_rstc_read_RCAUSE_reg(const void *const hw) +{ + return ((Rstc *)hw)->RCAUSE.reg; +} + +static inline bool hri_rstc_get_BKUPEXIT_EXTWAKE_bit(const void *const hw) +{ + return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_EXTWAKE) >> RSTC_BKUPEXIT_EXTWAKE_Pos; +} + +static inline bool hri_rstc_get_BKUPEXIT_RTC_bit(const void *const hw) +{ + return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_RTC) >> RSTC_BKUPEXIT_RTC_Pos; +} + +static inline bool hri_rstc_get_BKUPEXIT_BBPS_bit(const void *const hw) +{ + return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_BBPS) >> RSTC_BKUPEXIT_BBPS_Pos; +} + +static inline hri_rstc_bkupexit_reg_t hri_rstc_get_BKUPEXIT_reg(const void *const hw, hri_rstc_bkupexit_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rstc *)hw)->BKUPEXIT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rstc_bkupexit_reg_t hri_rstc_read_BKUPEXIT_reg(const void *const hw) +{ + return ((Rstc *)hw)->BKUPEXIT.reg; +} + +static inline void hri_rstc_set_WKDBCONF_WKDBCNT_bf(const void *const hw, hri_rstc_wkdbconf_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKDBCONF.reg |= RSTC_WKDBCONF_WKDBCNT(mask); + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rstc_wkdbconf_reg_t hri_rstc_get_WKDBCONF_WKDBCNT_bf(const void *const hw, + hri_rstc_wkdbconf_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rstc *)hw)->WKDBCONF.reg; + tmp = (tmp & RSTC_WKDBCONF_WKDBCNT(mask)) >> RSTC_WKDBCONF_WKDBCNT_Pos; + return tmp; +} + +static inline void hri_rstc_write_WKDBCONF_WKDBCNT_bf(const void *const hw, hri_rstc_wkdbconf_reg_t data) +{ + uint8_t tmp; + RSTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rstc *)hw)->WKDBCONF.reg; + tmp &= ~RSTC_WKDBCONF_WKDBCNT_Msk; + tmp |= RSTC_WKDBCONF_WKDBCNT(data); + ((Rstc *)hw)->WKDBCONF.reg = tmp; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_clear_WKDBCONF_WKDBCNT_bf(const void *const hw, hri_rstc_wkdbconf_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKDBCONF.reg &= ~RSTC_WKDBCONF_WKDBCNT(mask); + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_toggle_WKDBCONF_WKDBCNT_bf(const void *const hw, hri_rstc_wkdbconf_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKDBCONF.reg ^= RSTC_WKDBCONF_WKDBCNT(mask); + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rstc_wkdbconf_reg_t hri_rstc_read_WKDBCONF_WKDBCNT_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Rstc *)hw)->WKDBCONF.reg; + tmp = (tmp & RSTC_WKDBCONF_WKDBCNT_Msk) >> RSTC_WKDBCONF_WKDBCNT_Pos; + return tmp; +} + +static inline void hri_rstc_set_WKDBCONF_reg(const void *const hw, hri_rstc_wkdbconf_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKDBCONF.reg |= mask; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rstc_wkdbconf_reg_t hri_rstc_get_WKDBCONF_reg(const void *const hw, hri_rstc_wkdbconf_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rstc *)hw)->WKDBCONF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rstc_write_WKDBCONF_reg(const void *const hw, hri_rstc_wkdbconf_reg_t data) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKDBCONF.reg = data; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_clear_WKDBCONF_reg(const void *const hw, hri_rstc_wkdbconf_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKDBCONF.reg &= ~mask; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_toggle_WKDBCONF_reg(const void *const hw, hri_rstc_wkdbconf_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKDBCONF.reg ^= mask; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rstc_wkdbconf_reg_t hri_rstc_read_WKDBCONF_reg(const void *const hw) +{ + return ((Rstc *)hw)->WKDBCONF.reg; +} + +static inline void hri_rstc_set_WKPOL_WKPOL_bf(const void *const hw, hri_rstc_wkpol_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKPOL.reg |= RSTC_WKPOL_WKPOL(mask); + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rstc_wkpol_reg_t hri_rstc_get_WKPOL_WKPOL_bf(const void *const hw, hri_rstc_wkpol_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rstc *)hw)->WKPOL.reg; + tmp = (tmp & RSTC_WKPOL_WKPOL(mask)) >> RSTC_WKPOL_WKPOL_Pos; + return tmp; +} + +static inline void hri_rstc_write_WKPOL_WKPOL_bf(const void *const hw, hri_rstc_wkpol_reg_t data) +{ + uint16_t tmp; + RSTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rstc *)hw)->WKPOL.reg; + tmp &= ~RSTC_WKPOL_WKPOL_Msk; + tmp |= RSTC_WKPOL_WKPOL(data); + ((Rstc *)hw)->WKPOL.reg = tmp; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_clear_WKPOL_WKPOL_bf(const void *const hw, hri_rstc_wkpol_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKPOL.reg &= ~RSTC_WKPOL_WKPOL(mask); + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_toggle_WKPOL_WKPOL_bf(const void *const hw, hri_rstc_wkpol_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKPOL.reg ^= RSTC_WKPOL_WKPOL(mask); + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rstc_wkpol_reg_t hri_rstc_read_WKPOL_WKPOL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rstc *)hw)->WKPOL.reg; + tmp = (tmp & RSTC_WKPOL_WKPOL_Msk) >> RSTC_WKPOL_WKPOL_Pos; + return tmp; +} + +static inline void hri_rstc_set_WKPOL_reg(const void *const hw, hri_rstc_wkpol_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKPOL.reg |= mask; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rstc_wkpol_reg_t hri_rstc_get_WKPOL_reg(const void *const hw, hri_rstc_wkpol_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rstc *)hw)->WKPOL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rstc_write_WKPOL_reg(const void *const hw, hri_rstc_wkpol_reg_t data) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKPOL.reg = data; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_clear_WKPOL_reg(const void *const hw, hri_rstc_wkpol_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKPOL.reg &= ~mask; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_toggle_WKPOL_reg(const void *const hw, hri_rstc_wkpol_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKPOL.reg ^= mask; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rstc_wkpol_reg_t hri_rstc_read_WKPOL_reg(const void *const hw) +{ + return ((Rstc *)hw)->WKPOL.reg; +} + +static inline void hri_rstc_set_WKEN_WKEN_bf(const void *const hw, hri_rstc_wken_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKEN.reg |= RSTC_WKEN_WKEN(mask); + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rstc_wken_reg_t hri_rstc_get_WKEN_WKEN_bf(const void *const hw, hri_rstc_wken_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rstc *)hw)->WKEN.reg; + tmp = (tmp & RSTC_WKEN_WKEN(mask)) >> RSTC_WKEN_WKEN_Pos; + return tmp; +} + +static inline void hri_rstc_write_WKEN_WKEN_bf(const void *const hw, hri_rstc_wken_reg_t data) +{ + uint16_t tmp; + RSTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rstc *)hw)->WKEN.reg; + tmp &= ~RSTC_WKEN_WKEN_Msk; + tmp |= RSTC_WKEN_WKEN(data); + ((Rstc *)hw)->WKEN.reg = tmp; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_clear_WKEN_WKEN_bf(const void *const hw, hri_rstc_wken_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKEN.reg &= ~RSTC_WKEN_WKEN(mask); + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_toggle_WKEN_WKEN_bf(const void *const hw, hri_rstc_wken_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKEN.reg ^= RSTC_WKEN_WKEN(mask); + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rstc_wken_reg_t hri_rstc_read_WKEN_WKEN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rstc *)hw)->WKEN.reg; + tmp = (tmp & RSTC_WKEN_WKEN_Msk) >> RSTC_WKEN_WKEN_Pos; + return tmp; +} + +static inline void hri_rstc_set_WKEN_reg(const void *const hw, hri_rstc_wken_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKEN.reg |= mask; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rstc_wken_reg_t hri_rstc_get_WKEN_reg(const void *const hw, hri_rstc_wken_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rstc *)hw)->WKEN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rstc_write_WKEN_reg(const void *const hw, hri_rstc_wken_reg_t data) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKEN.reg = data; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_clear_WKEN_reg(const void *const hw, hri_rstc_wken_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKEN.reg &= ~mask; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_toggle_WKEN_reg(const void *const hw, hri_rstc_wken_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKEN.reg ^= mask; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rstc_wken_reg_t hri_rstc_read_WKEN_reg(const void *const hw) +{ + return ((Rstc *)hw)->WKEN.reg; +} + +static inline void hri_rstc_set_WKCAUSE_WKCAUSE_bf(const void *const hw, hri_rstc_wkcause_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKCAUSE.reg |= RSTC_WKCAUSE_WKCAUSE(mask); + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rstc_wkcause_reg_t hri_rstc_get_WKCAUSE_WKCAUSE_bf(const void *const hw, hri_rstc_wkcause_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rstc *)hw)->WKCAUSE.reg; + tmp = (tmp & RSTC_WKCAUSE_WKCAUSE(mask)) >> RSTC_WKCAUSE_WKCAUSE_Pos; + return tmp; +} + +static inline void hri_rstc_write_WKCAUSE_WKCAUSE_bf(const void *const hw, hri_rstc_wkcause_reg_t data) +{ + uint16_t tmp; + RSTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rstc *)hw)->WKCAUSE.reg; + tmp &= ~RSTC_WKCAUSE_WKCAUSE_Msk; + tmp |= RSTC_WKCAUSE_WKCAUSE(data); + ((Rstc *)hw)->WKCAUSE.reg = tmp; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_clear_WKCAUSE_WKCAUSE_bf(const void *const hw, hri_rstc_wkcause_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKCAUSE.reg &= ~RSTC_WKCAUSE_WKCAUSE(mask); + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_toggle_WKCAUSE_WKCAUSE_bf(const void *const hw, hri_rstc_wkcause_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKCAUSE.reg ^= RSTC_WKCAUSE_WKCAUSE(mask); + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rstc_wkcause_reg_t hri_rstc_read_WKCAUSE_WKCAUSE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rstc *)hw)->WKCAUSE.reg; + tmp = (tmp & RSTC_WKCAUSE_WKCAUSE_Msk) >> RSTC_WKCAUSE_WKCAUSE_Pos; + return tmp; +} + +static inline void hri_rstc_set_WKCAUSE_reg(const void *const hw, hri_rstc_wkcause_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKCAUSE.reg |= mask; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rstc_wkcause_reg_t hri_rstc_get_WKCAUSE_reg(const void *const hw, hri_rstc_wkcause_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rstc *)hw)->WKCAUSE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rstc_write_WKCAUSE_reg(const void *const hw, hri_rstc_wkcause_reg_t data) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKCAUSE.reg = data; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_clear_WKCAUSE_reg(const void *const hw, hri_rstc_wkcause_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKCAUSE.reg &= ~mask; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rstc_toggle_WKCAUSE_reg(const void *const hw, hri_rstc_wkcause_reg_t mask) +{ + RSTC_CRITICAL_SECTION_ENTER(); + ((Rstc *)hw)->WKCAUSE.reg ^= mask; + RSTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rstc_wkcause_reg_t hri_rstc_read_WKCAUSE_reg(const void *const hw) +{ + return ((Rstc *)hw)->WKCAUSE.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_RSTC_L21_H_INCLUDED */ +#endif /* _SAML21_RSTC_COMPONENT_ */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_rtc_l21.h b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_rtc_l21.h new file mode 100644 index 00000000..85384f7c --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_rtc_l21.h @@ -0,0 +1,6235 @@ +/** + * \file + * + * \brief SAM RTC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_RTC_COMPONENT_ +#ifndef _HRI_RTC_L21_H_INCLUDED_ +#define _HRI_RTC_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_RTC_CRITICAL_SECTIONS) +#define RTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define RTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define RTC_CRITICAL_SECTION_ENTER() +#define RTC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_rtcmode0_ctrla_reg_t; +typedef uint16_t hri_rtcmode0_intenset_reg_t; +typedef uint16_t hri_rtcmode0_intflag_reg_t; +typedef uint16_t hri_rtcmode1_comp_reg_t; +typedef uint16_t hri_rtcmode1_count_reg_t; +typedef uint16_t hri_rtcmode1_ctrla_reg_t; +typedef uint16_t hri_rtcmode1_intenset_reg_t; +typedef uint16_t hri_rtcmode1_intflag_reg_t; +typedef uint16_t hri_rtcmode1_per_reg_t; +typedef uint16_t hri_rtcmode2_ctrla_reg_t; +typedef uint16_t hri_rtcmode2_intenset_reg_t; +typedef uint16_t hri_rtcmode2_intflag_reg_t; +typedef uint32_t hri_rtc_gp_reg_t; +typedef uint32_t hri_rtcalarm_alarm_reg_t; +typedef uint32_t hri_rtcmode0_comp_reg_t; +typedef uint32_t hri_rtcmode0_count_reg_t; +typedef uint32_t hri_rtcmode0_evctrl_reg_t; +typedef uint32_t hri_rtcmode0_syncbusy_reg_t; +typedef uint32_t hri_rtcmode1_evctrl_reg_t; +typedef uint32_t hri_rtcmode1_syncbusy_reg_t; +typedef uint32_t hri_rtcmode2_alarm_reg_t; +typedef uint32_t hri_rtcmode2_clock_reg_t; +typedef uint32_t hri_rtcmode2_evctrl_reg_t; +typedef uint32_t hri_rtcmode2_syncbusy_reg_t; +typedef uint8_t hri_rtc_dbgctrl_reg_t; +typedef uint8_t hri_rtc_freqcorr_reg_t; +typedef uint8_t hri_rtcalarm_mask_reg_t; +typedef uint8_t hri_rtcmode2_mask_reg_t; + +static inline void hri_rtcmode0_wait_for_sync(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg) +{ + while (((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_rtcmode0_is_syncing(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg) +{ + return ((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg; +} + +static inline void hri_rtcmode1_wait_for_sync(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg) +{ + while (((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_rtcmode1_is_syncing(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg) +{ + return ((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg; +} + +static inline void hri_rtcmode2_wait_for_sync(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg) +{ + while (((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_rtcmode2_is_syncing(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg) +{ + return ((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg; +} + +static inline void hri_rtcalarm_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_SECOND_Msk; + tmp |= RTC_MODE2_ALARM_SECOND(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk; + tmp |= RTC_MODE2_ALARM_MINUTE(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_HOUR_Msk; + tmp |= RTC_MODE2_ALARM_HOUR(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_DAY_Msk; + tmp |= RTC_MODE2_ALARM_DAY(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MONTH_Msk; + tmp |= RTC_MODE2_ALARM_MONTH(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_YEAR_Msk; + tmp |= RTC_MODE2_ALARM_YEAR(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_reg(const void *const hw, uint8_t submodule_index) +{ + return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; +} + +static inline void hri_rtcalarm_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t data) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp &= ~RTC_MODE2_MASK_SEL_Msk; + tmp |= RTC_MODE2_MASK_SEL(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_get_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcalarm_write_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_read_MASK_reg(const void *const hw, uint8_t submodule_index) +{ + return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; +} + +static inline void hri_rtcmode2_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_SECOND_Msk; + tmp |= RTC_MODE2_ALARM_SECOND(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk; + tmp |= RTC_MODE2_ALARM_MINUTE(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_HOUR_Msk; + tmp |= RTC_MODE2_ALARM_HOUR(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_DAY_Msk; + tmp |= RTC_MODE2_ALARM_DAY(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MONTH_Msk; + tmp |= RTC_MODE2_ALARM_MONTH(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_YEAR_Msk; + tmp |= RTC_MODE2_ALARM_YEAR(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; +} + +static inline void hri_rtcmode2_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t data) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp &= ~RTC_MODE2_MASK_SEL_Msk; + tmp |= RTC_MODE2_MASK_SEL(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER0) >> RTC_MODE0_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER0; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER1) >> RTC_MODE0_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER1; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER2) >> RTC_MODE0_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER3) >> RTC_MODE0_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER3; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER4) >> RTC_MODE0_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER4; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER5) >> RTC_MODE0_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER5; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER6) >> RTC_MODE0_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER6; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER7) >> RTC_MODE0_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER7; +} + +static inline bool hri_rtcmode0_get_INTFLAG_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode0_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF; +} + +static inline bool hri_rtcmode0_get_interrupt_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER0) >> RTC_MODE0_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER0; +} + +static inline bool hri_rtcmode0_get_interrupt_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER1) >> RTC_MODE0_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER1; +} + +static inline bool hri_rtcmode0_get_interrupt_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER2) >> RTC_MODE0_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2; +} + +static inline bool hri_rtcmode0_get_interrupt_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER3) >> RTC_MODE0_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER3; +} + +static inline bool hri_rtcmode0_get_interrupt_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER4) >> RTC_MODE0_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER4; +} + +static inline bool hri_rtcmode0_get_interrupt_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER5) >> RTC_MODE0_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER5; +} + +static inline bool hri_rtcmode0_get_interrupt_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER6) >> RTC_MODE0_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER6; +} + +static inline bool hri_rtcmode0_get_interrupt_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER7) >> RTC_MODE0_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER7; +} + +static inline bool hri_rtcmode0_get_interrupt_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode0_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF; +} + +static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_get_INTFLAG_reg(const void *const hw, + hri_rtcmode0_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_read_INTFLAG_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.INTFLAG.reg; +} + +static inline void hri_rtcmode0_clear_INTFLAG_reg(const void *const hw, hri_rtcmode0_intflag_reg_t mask) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = mask; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER0) >> RTC_MODE1_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER0; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER1) >> RTC_MODE1_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER1; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER2) >> RTC_MODE1_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER2; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER3) >> RTC_MODE1_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER3; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER4) >> RTC_MODE1_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER4; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER5) >> RTC_MODE1_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER5; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER6) >> RTC_MODE1_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER6; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER7) >> RTC_MODE1_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER7; +} + +static inline bool hri_rtcmode1_get_INTFLAG_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode1_get_INTFLAG_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1; +} + +static inline bool hri_rtcmode1_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF; +} + +static inline bool hri_rtcmode1_get_interrupt_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER0) >> RTC_MODE1_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER0; +} + +static inline bool hri_rtcmode1_get_interrupt_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER1) >> RTC_MODE1_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER1; +} + +static inline bool hri_rtcmode1_get_interrupt_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER2) >> RTC_MODE1_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER2; +} + +static inline bool hri_rtcmode1_get_interrupt_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER3) >> RTC_MODE1_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER3; +} + +static inline bool hri_rtcmode1_get_interrupt_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER4) >> RTC_MODE1_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER4; +} + +static inline bool hri_rtcmode1_get_interrupt_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER5) >> RTC_MODE1_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER5; +} + +static inline bool hri_rtcmode1_get_interrupt_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER6) >> RTC_MODE1_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER6; +} + +static inline bool hri_rtcmode1_get_interrupt_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER7) >> RTC_MODE1_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER7; +} + +static inline bool hri_rtcmode1_get_interrupt_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode1_get_interrupt_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1; +} + +static inline bool hri_rtcmode1_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF; +} + +static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_get_INTFLAG_reg(const void *const hw, + hri_rtcmode1_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_read_INTFLAG_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.INTFLAG.reg; +} + +static inline void hri_rtcmode1_clear_INTFLAG_reg(const void *const hw, hri_rtcmode1_intflag_reg_t mask) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = mask; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER0) >> RTC_MODE2_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER0; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER1) >> RTC_MODE2_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER1; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER2) >> RTC_MODE2_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER2; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER3) >> RTC_MODE2_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER3; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER4) >> RTC_MODE2_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER4; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER5) >> RTC_MODE2_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER5; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER6) >> RTC_MODE2_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER6; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER7) >> RTC_MODE2_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER7; +} + +static inline bool hri_rtcmode2_get_INTFLAG_ALARM0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0; +} + +static inline bool hri_rtcmode2_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF; +} + +static inline bool hri_rtcmode2_get_interrupt_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER0) >> RTC_MODE2_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER0; +} + +static inline bool hri_rtcmode2_get_interrupt_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER1) >> RTC_MODE2_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER1; +} + +static inline bool hri_rtcmode2_get_interrupt_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER2) >> RTC_MODE2_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER2; +} + +static inline bool hri_rtcmode2_get_interrupt_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER3) >> RTC_MODE2_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER3; +} + +static inline bool hri_rtcmode2_get_interrupt_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER4) >> RTC_MODE2_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER4; +} + +static inline bool hri_rtcmode2_get_interrupt_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER5) >> RTC_MODE2_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER5; +} + +static inline bool hri_rtcmode2_get_interrupt_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER6) >> RTC_MODE2_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER6; +} + +static inline bool hri_rtcmode2_get_interrupt_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER7) >> RTC_MODE2_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER7; +} + +static inline bool hri_rtcmode2_get_interrupt_ALARM0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0; +} + +static inline bool hri_rtcmode2_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF; +} + +static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_get_INTFLAG_reg(const void *const hw, + hri_rtcmode2_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_read_INTFLAG_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.INTFLAG.reg; +} + +static inline void hri_rtcmode2_clear_INTFLAG_reg(const void *const hw, hri_rtcmode2_intflag_reg_t mask) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = mask; +} + +static inline void hri_rtcmode0_set_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0; +} + +static inline bool hri_rtcmode0_get_INTEN_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER0) >> RTC_MODE0_INTENSET_PER0_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0; +} + +static inline void hri_rtcmode0_set_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER1; +} + +static inline bool hri_rtcmode0_get_INTEN_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER1) >> RTC_MODE0_INTENSET_PER1_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER1; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER1; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER1; +} + +static inline void hri_rtcmode0_set_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2; +} + +static inline bool hri_rtcmode0_get_INTEN_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER2) >> RTC_MODE0_INTENSET_PER2_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER2; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER2; +} + +static inline void hri_rtcmode0_set_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER3; +} + +static inline bool hri_rtcmode0_get_INTEN_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER3) >> RTC_MODE0_INTENSET_PER3_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER3; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER3; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER3; +} + +static inline void hri_rtcmode0_set_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER4; +} + +static inline bool hri_rtcmode0_get_INTEN_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER4) >> RTC_MODE0_INTENSET_PER4_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER4; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER4; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER4; +} + +static inline void hri_rtcmode0_set_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER5; +} + +static inline bool hri_rtcmode0_get_INTEN_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER5) >> RTC_MODE0_INTENSET_PER5_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER5; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER5; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER5; +} + +static inline void hri_rtcmode0_set_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER6; +} + +static inline bool hri_rtcmode0_get_INTEN_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER6) >> RTC_MODE0_INTENSET_PER6_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER6; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER6; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER6; +} + +static inline void hri_rtcmode0_set_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER7; +} + +static inline bool hri_rtcmode0_get_INTEN_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER7) >> RTC_MODE0_INTENSET_PER7_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER7; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER7; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER7; +} + +static inline void hri_rtcmode0_set_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0; +} + +static inline bool hri_rtcmode0_get_INTEN_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_CMP0) >> RTC_MODE0_INTENSET_CMP0_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_CMP0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0; + } +} + +static inline void hri_rtcmode0_clear_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0; +} + +static inline void hri_rtcmode0_set_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF; +} + +static inline bool hri_rtcmode0_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_OVF) >> RTC_MODE0_INTENSET_OVF_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF; + } +} + +static inline void hri_rtcmode0_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF; +} + +static inline void hri_rtcmode0_set_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = mask; +} + +static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_get_INTEN_reg(const void *const hw, + hri_rtcmode0_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_read_INTEN_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.INTENSET.reg; +} + +static inline void hri_rtcmode0_write_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t data) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = data; + ((Rtc *)hw)->MODE0.INTENCLR.reg = ~data; +} + +static inline void hri_rtcmode0_clear_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = mask; +} + +static inline void hri_rtcmode1_set_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0; +} + +static inline bool hri_rtcmode1_get_INTEN_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER0) >> RTC_MODE1_INTENSET_PER0_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0; +} + +static inline void hri_rtcmode1_set_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER1; +} + +static inline bool hri_rtcmode1_get_INTEN_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER1) >> RTC_MODE1_INTENSET_PER1_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER1; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER1; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER1; +} + +static inline void hri_rtcmode1_set_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER2; +} + +static inline bool hri_rtcmode1_get_INTEN_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER2) >> RTC_MODE1_INTENSET_PER2_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER2; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER2; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER2; +} + +static inline void hri_rtcmode1_set_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER3; +} + +static inline bool hri_rtcmode1_get_INTEN_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER3) >> RTC_MODE1_INTENSET_PER3_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER3; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER3; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER3; +} + +static inline void hri_rtcmode1_set_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER4; +} + +static inline bool hri_rtcmode1_get_INTEN_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER4) >> RTC_MODE1_INTENSET_PER4_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER4; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER4; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER4; +} + +static inline void hri_rtcmode1_set_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER5; +} + +static inline bool hri_rtcmode1_get_INTEN_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER5) >> RTC_MODE1_INTENSET_PER5_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER5; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER5; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER5; +} + +static inline void hri_rtcmode1_set_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER6; +} + +static inline bool hri_rtcmode1_get_INTEN_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER6) >> RTC_MODE1_INTENSET_PER6_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER6; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER6; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER6; +} + +static inline void hri_rtcmode1_set_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER7; +} + +static inline bool hri_rtcmode1_get_INTEN_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER7) >> RTC_MODE1_INTENSET_PER7_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER7; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER7; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER7; +} + +static inline void hri_rtcmode1_set_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0; +} + +static inline bool hri_rtcmode1_get_INTEN_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP0) >> RTC_MODE1_INTENSET_CMP0_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_CMP0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0; + } +} + +static inline void hri_rtcmode1_clear_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0; +} + +static inline void hri_rtcmode1_set_INTEN_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1; +} + +static inline bool hri_rtcmode1_get_INTEN_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP1) >> RTC_MODE1_INTENSET_CMP1_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_CMP1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1; + } +} + +static inline void hri_rtcmode1_clear_INTEN_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1; +} + +static inline void hri_rtcmode1_set_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF; +} + +static inline bool hri_rtcmode1_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_OVF) >> RTC_MODE1_INTENSET_OVF_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF; + } +} + +static inline void hri_rtcmode1_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF; +} + +static inline void hri_rtcmode1_set_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = mask; +} + +static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_get_INTEN_reg(const void *const hw, + hri_rtcmode1_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_read_INTEN_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.INTENSET.reg; +} + +static inline void hri_rtcmode1_write_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t data) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = data; + ((Rtc *)hw)->MODE1.INTENCLR.reg = ~data; +} + +static inline void hri_rtcmode1_clear_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = mask; +} + +static inline void hri_rtcmode2_set_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0; +} + +static inline bool hri_rtcmode2_get_INTEN_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER0) >> RTC_MODE2_INTENSET_PER0_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0; +} + +static inline void hri_rtcmode2_set_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1; +} + +static inline bool hri_rtcmode2_get_INTEN_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER1) >> RTC_MODE2_INTENSET_PER1_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1; +} + +static inline void hri_rtcmode2_set_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2; +} + +static inline bool hri_rtcmode2_get_INTEN_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER2) >> RTC_MODE2_INTENSET_PER2_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2; +} + +static inline void hri_rtcmode2_set_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER3; +} + +static inline bool hri_rtcmode2_get_INTEN_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER3) >> RTC_MODE2_INTENSET_PER3_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER3; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3; +} + +static inline void hri_rtcmode2_set_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER4; +} + +static inline bool hri_rtcmode2_get_INTEN_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER4) >> RTC_MODE2_INTENSET_PER4_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER4; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4; +} + +static inline void hri_rtcmode2_set_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER5; +} + +static inline bool hri_rtcmode2_get_INTEN_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER5) >> RTC_MODE2_INTENSET_PER5_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER5; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER5; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER5; +} + +static inline void hri_rtcmode2_set_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER6; +} + +static inline bool hri_rtcmode2_get_INTEN_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER6) >> RTC_MODE2_INTENSET_PER6_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER6; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER6; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER6; +} + +static inline void hri_rtcmode2_set_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7; +} + +static inline bool hri_rtcmode2_get_INTEN_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER7) >> RTC_MODE2_INTENSET_PER7_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER7; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER7; +} + +static inline void hri_rtcmode2_set_INTEN_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0; +} + +static inline bool hri_rtcmode2_get_INTEN_ALARM0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_ALARM0) >> RTC_MODE2_INTENSET_ALARM0_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_ALARM0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0; + } +} + +static inline void hri_rtcmode2_clear_INTEN_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0; +} + +static inline void hri_rtcmode2_set_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF; +} + +static inline bool hri_rtcmode2_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_OVF) >> RTC_MODE2_INTENSET_OVF_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF; + } +} + +static inline void hri_rtcmode2_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF; +} + +static inline void hri_rtcmode2_set_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = mask; +} + +static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_get_INTEN_reg(const void *const hw, + hri_rtcmode2_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_read_INTEN_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.INTENSET.reg; +} + +static inline void hri_rtcmode2_write_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t data) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = data; + ((Rtc *)hw)->MODE2.INTENCLR.reg = ~data; +} + +static inline void hri_rtcmode2_clear_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = mask; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_SWRST) >> RTC_MODE0_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_ENABLE) >> RTC_MODE0_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_FREQCORR_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_FREQCORR) >> RTC_MODE0_SYNCBUSY_FREQCORR_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COUNT) >> RTC_MODE0_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_COMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COMP0) >> RTC_MODE0_SYNCBUSY_COMP0_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_COUNTSYNC_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COUNTSYNC) >> RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos; +} + +static inline hri_rtcmode0_syncbusy_reg_t hri_rtcmode0_get_SYNCBUSY_reg(const void *const hw, + hri_rtcmode0_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode0_syncbusy_reg_t hri_rtcmode0_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.SYNCBUSY.reg; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_SWRST) >> RTC_MODE1_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_ENABLE) >> RTC_MODE1_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_FREQCORR_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_FREQCORR) >> RTC_MODE1_SYNCBUSY_FREQCORR_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COUNT) >> RTC_MODE1_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_PER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_PER) >> RTC_MODE1_SYNCBUSY_PER_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP0) >> RTC_MODE1_SYNCBUSY_COMP0_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP1) >> RTC_MODE1_SYNCBUSY_COMP1_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COUNTSYNC_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COUNTSYNC) >> RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos; +} + +static inline hri_rtcmode1_syncbusy_reg_t hri_rtcmode1_get_SYNCBUSY_reg(const void *const hw, + hri_rtcmode1_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode1_syncbusy_reg_t hri_rtcmode1_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.SYNCBUSY.reg; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_SWRST) >> RTC_MODE2_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ENABLE) >> RTC_MODE2_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_FREQCORR_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_FREQCORR) >> RTC_MODE2_SYNCBUSY_FREQCORR_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_CLOCK_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_CLOCK) >> RTC_MODE2_SYNCBUSY_CLOCK_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_ALARM0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ALARM0) >> RTC_MODE2_SYNCBUSY_ALARM0_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_MASK0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_MASK0) >> RTC_MODE2_SYNCBUSY_MASK0_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_CLOCKSYNC_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_CLOCKSYNC) >> RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos; +} + +static inline hri_rtcmode2_syncbusy_reg_t hri_rtcmode2_get_SYNCBUSY_reg(const void *const hw, + hri_rtcmode2_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode2_syncbusy_reg_t hri_rtcmode2_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.SYNCBUSY.reg; +} + +static inline void hri_rtcmode0_set_CTRLA_SWRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_SWRST; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_SWRST) >> RTC_MODE0_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_set_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_ENABLE; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_ENABLE) >> RTC_MODE0_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_ENABLE; + tmp |= value << RTC_MODE0_CTRLA_ENABLE_Pos; + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_ENABLE; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_ENABLE; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MATCHCLR; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_MATCHCLR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_MATCHCLR) >> RTC_MODE0_CTRLA_MATCHCLR_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_MATCHCLR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_MATCHCLR; + tmp |= value << RTC_MODE0_CTRLA_MATCHCLR_Pos; + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_MATCHCLR; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_MATCHCLR; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_COUNTSYNC; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_COUNTSYNC) >> RTC_MODE0_CTRLA_COUNTSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_COUNTSYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_COUNTSYNC; + tmp |= value << RTC_MODE0_CTRLA_COUNTSYNC_Pos; + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_COUNTSYNC; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_COUNTSYNC; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MODE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_MODE_bf(const void *const hw, + hri_rtcmode0_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_MODE(mask)) >> RTC_MODE0_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_MODE_Msk; + tmp |= RTC_MODE0_CTRLA_MODE(data); + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_MODE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_MODE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_MODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_MODE_Msk) >> RTC_MODE0_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_PRESCALER(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_PRESCALER_bf(const void *const hw, + hri_rtcmode0_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_PRESCALER(mask)) >> RTC_MODE0_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_PRESCALER_Msk; + tmp |= RTC_MODE0_CTRLA_PRESCALER(data); + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_PRESCALER(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_PRESCALER(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_PRESCALER_Msk) >> RTC_MODE0_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg = data; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_reg(const void *const hw) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + return ((Rtc *)hw)->MODE0.CTRLA.reg; +} + +static inline void hri_rtcmode1_set_CTRLA_SWRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_SWRST; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_SWRST) >> RTC_MODE1_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_set_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_ENABLE; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_ENABLE) >> RTC_MODE1_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_ENABLE; + tmp |= value << RTC_MODE1_CTRLA_ENABLE_Pos; + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_ENABLE; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_ENABLE; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_COUNTSYNC; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_COUNTSYNC) >> RTC_MODE1_CTRLA_COUNTSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_COUNTSYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_COUNTSYNC; + tmp |= value << RTC_MODE1_CTRLA_COUNTSYNC_Pos; + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_COUNTSYNC; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_COUNTSYNC; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_MODE(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_MODE_bf(const void *const hw, + hri_rtcmode1_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_MODE(mask)) >> RTC_MODE1_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_MODE_Msk; + tmp |= RTC_MODE1_CTRLA_MODE(data); + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_MODE(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_MODE(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_MODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_MODE_Msk) >> RTC_MODE1_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_PRESCALER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_PRESCALER_bf(const void *const hw, + hri_rtcmode1_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_PRESCALER(mask)) >> RTC_MODE1_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_PRESCALER_Msk; + tmp |= RTC_MODE1_CTRLA_PRESCALER(data); + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_PRESCALER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_PRESCALER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_PRESCALER_Msk) >> RTC_MODE1_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg = data; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_reg(const void *const hw) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + return ((Rtc *)hw)->MODE1.CTRLA.reg; +} + +static inline void hri_rtcmode2_set_CTRLA_SWRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_SWRST; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_SWRST) >> RTC_MODE2_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_set_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_ENABLE; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_ENABLE) >> RTC_MODE2_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_ENABLE; + tmp |= value << RTC_MODE2_CTRLA_ENABLE_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_ENABLE; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_ENABLE; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_CLKREP_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_CLKREP; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_CLKREP_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_CLKREP) >> RTC_MODE2_CTRLA_CLKREP_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_CLKREP_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_CLKREP; + tmp |= value << RTC_MODE2_CTRLA_CLKREP_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_CLKREP_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_CLKREP; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_CLKREP_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLKREP; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_MATCHCLR; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_MATCHCLR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_MATCHCLR) >> RTC_MODE2_CTRLA_MATCHCLR_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_MATCHCLR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_MATCHCLR; + tmp |= value << RTC_MODE2_CTRLA_MATCHCLR_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_MATCHCLR; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_MATCHCLR; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_CLOCKSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_CLOCKSYNC; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_CLOCKSYNC_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_CLOCKSYNC) >> RTC_MODE2_CTRLA_CLOCKSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_CLOCKSYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_CLOCKSYNC; + tmp |= value << RTC_MODE2_CTRLA_CLOCKSYNC_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_CLOCKSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_CLOCKSYNC; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_CLOCKSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLOCKSYNC; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_MODE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_MODE_bf(const void *const hw, + hri_rtcmode2_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_MODE(mask)) >> RTC_MODE2_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_MODE_Msk; + tmp |= RTC_MODE2_CTRLA_MODE(data); + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_MODE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_MODE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_MODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_MODE_Msk) >> RTC_MODE2_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_PRESCALER(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_PRESCALER_bf(const void *const hw, + hri_rtcmode2_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_PRESCALER(mask)) >> RTC_MODE2_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_PRESCALER_Msk; + tmp |= RTC_MODE2_CTRLA_PRESCALER(data); + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_PRESCALER(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_PRESCALER(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_PRESCALER_Msk) >> RTC_MODE2_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg = data; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_reg(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + return ((Rtc *)hw)->MODE2.CTRLA.reg; +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO0) >> RTC_MODE0_EVCTRL_PEREO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO0; + tmp |= value << RTC_MODE0_EVCTRL_PEREO0_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO1) >> RTC_MODE0_EVCTRL_PEREO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO1; + tmp |= value << RTC_MODE0_EVCTRL_PEREO1_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO2) >> RTC_MODE0_EVCTRL_PEREO2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO2; + tmp |= value << RTC_MODE0_EVCTRL_PEREO2_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO3) >> RTC_MODE0_EVCTRL_PEREO3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO3; + tmp |= value << RTC_MODE0_EVCTRL_PEREO3_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO4) >> RTC_MODE0_EVCTRL_PEREO4_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO4; + tmp |= value << RTC_MODE0_EVCTRL_PEREO4_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO5) >> RTC_MODE0_EVCTRL_PEREO5_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO5; + tmp |= value << RTC_MODE0_EVCTRL_PEREO5_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO6) >> RTC_MODE0_EVCTRL_PEREO6_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO6; + tmp |= value << RTC_MODE0_EVCTRL_PEREO6_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO7) >> RTC_MODE0_EVCTRL_PEREO7_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO7; + tmp |= value << RTC_MODE0_EVCTRL_PEREO7_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_CMPEO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_CMPEO0) >> RTC_MODE0_EVCTRL_CMPEO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_CMPEO0; + tmp |= value << RTC_MODE0_EVCTRL_CMPEO0_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_OVFEO) >> RTC_MODE0_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_OVFEO; + tmp |= value << RTC_MODE0_EVCTRL_OVFEO_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_get_EVCTRL_reg(const void *const hw, + hri_rtcmode0_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_read_EVCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.EVCTRL.reg; +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO0) >> RTC_MODE1_EVCTRL_PEREO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO0; + tmp |= value << RTC_MODE1_EVCTRL_PEREO0_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO1) >> RTC_MODE1_EVCTRL_PEREO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO1; + tmp |= value << RTC_MODE1_EVCTRL_PEREO1_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO2) >> RTC_MODE1_EVCTRL_PEREO2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO2; + tmp |= value << RTC_MODE1_EVCTRL_PEREO2_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO3) >> RTC_MODE1_EVCTRL_PEREO3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO3; + tmp |= value << RTC_MODE1_EVCTRL_PEREO3_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO4) >> RTC_MODE1_EVCTRL_PEREO4_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO4; + tmp |= value << RTC_MODE1_EVCTRL_PEREO4_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO5) >> RTC_MODE1_EVCTRL_PEREO5_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO5; + tmp |= value << RTC_MODE1_EVCTRL_PEREO5_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO6) >> RTC_MODE1_EVCTRL_PEREO6_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO6; + tmp |= value << RTC_MODE1_EVCTRL_PEREO6_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO7) >> RTC_MODE1_EVCTRL_PEREO7_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO7; + tmp |= value << RTC_MODE1_EVCTRL_PEREO7_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_CMPEO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO0) >> RTC_MODE1_EVCTRL_CMPEO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_CMPEO0; + tmp |= value << RTC_MODE1_EVCTRL_CMPEO0_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_CMPEO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO1) >> RTC_MODE1_EVCTRL_CMPEO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_CMPEO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_CMPEO1; + tmp |= value << RTC_MODE1_EVCTRL_CMPEO1_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_OVFEO) >> RTC_MODE1_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_OVFEO; + tmp |= value << RTC_MODE1_EVCTRL_OVFEO_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_get_EVCTRL_reg(const void *const hw, + hri_rtcmode1_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_read_EVCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.EVCTRL.reg; +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO0) >> RTC_MODE2_EVCTRL_PEREO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO0; + tmp |= value << RTC_MODE2_EVCTRL_PEREO0_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO1) >> RTC_MODE2_EVCTRL_PEREO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO1; + tmp |= value << RTC_MODE2_EVCTRL_PEREO1_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO2) >> RTC_MODE2_EVCTRL_PEREO2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO2; + tmp |= value << RTC_MODE2_EVCTRL_PEREO2_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO3) >> RTC_MODE2_EVCTRL_PEREO3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO3; + tmp |= value << RTC_MODE2_EVCTRL_PEREO3_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO4) >> RTC_MODE2_EVCTRL_PEREO4_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO4; + tmp |= value << RTC_MODE2_EVCTRL_PEREO4_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO5) >> RTC_MODE2_EVCTRL_PEREO5_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO5; + tmp |= value << RTC_MODE2_EVCTRL_PEREO5_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO6) >> RTC_MODE2_EVCTRL_PEREO6_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO6; + tmp |= value << RTC_MODE2_EVCTRL_PEREO6_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO7) >> RTC_MODE2_EVCTRL_PEREO7_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO7; + tmp |= value << RTC_MODE2_EVCTRL_PEREO7_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_ALARMEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_ALARMEO0) >> RTC_MODE2_EVCTRL_ALARMEO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_ALARMEO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_ALARMEO0; + tmp |= value << RTC_MODE2_EVCTRL_ALARMEO0_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_ALARMEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_ALARMEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_OVFEO) >> RTC_MODE2_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_OVFEO; + tmp |= value << RTC_MODE2_EVCTRL_OVFEO_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_get_EVCTRL_reg(const void *const hw, + hri_rtcmode2_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_read_EVCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.EVCTRL.reg; +} + +static inline void hri_rtc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg |= RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; + tmp = (tmp & RTC_DBGCTRL_DBGRUN) >> RTC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; + tmp &= ~RTC_DBGCTRL_DBGRUN; + tmp |= value << RTC_DBGCTRL_DBGRUN_Pos; + ((Rtc *)hw)->MODE0.DBGCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg ^= RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_dbgctrl_reg_t hri_rtc_get_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_dbgctrl_reg_t hri_rtc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.DBGCTRL.reg; +} + +static inline void hri_rtc_set_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_SIGN; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_FREQCORR_SIGN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_SIGN) >> RTC_FREQCORR_SIGN_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_FREQCORR_SIGN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp &= ~RTC_FREQCORR_SIGN; + tmp |= value << RTC_FREQCORR_SIGN_Pos; + ((Rtc *)hw)->MODE0.FREQCORR.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_SIGN; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_SIGN; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_VALUE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_freqcorr_reg_t hri_rtc_get_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_VALUE(mask)) >> RTC_FREQCORR_VALUE_Pos; + return tmp; +} + +static inline void hri_rtc_write_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t data) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp &= ~RTC_FREQCORR_VALUE_Msk; + tmp |= RTC_FREQCORR_VALUE(data); + ((Rtc *)hw)->MODE0.FREQCORR.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_VALUE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_VALUE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_freqcorr_reg_t hri_rtc_read_FREQCORR_VALUE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_VALUE_Msk) >> RTC_FREQCORR_VALUE_Pos; + return tmp; +} + +static inline void hri_rtc_set_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg |= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_freqcorr_reg_t hri_rtc_get_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + uint8_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg = data; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg ^= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_freqcorr_reg_t hri_rtc_read_FREQCORR_reg(const void *const hw) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + return ((Rtc *)hw)->MODE0.FREQCORR.reg; +} + +static inline void hri_rtcmode0_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg |= RTC_MODE0_COUNT_COUNT(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_COUNT_bf(const void *const hw, + hri_rtcmode0_count_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp = (tmp & RTC_MODE0_COUNT_COUNT(mask)) >> RTC_MODE0_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp &= ~RTC_MODE0_COUNT_COUNT_Msk; + tmp |= RTC_MODE0_COUNT_COUNT(data); + ((Rtc *)hw)->MODE0.COUNT.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg &= ~RTC_MODE0_COUNT_COUNT(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg ^= RTC_MODE0_COUNT_COUNT(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp = (tmp & RTC_MODE0_COUNT_COUNT_Msk) >> RTC_MODE0_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg |= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg = data; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg &= ~mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg ^= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_reg(const void *const hw) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + return ((Rtc *)hw)->MODE0.COUNT.reg; +} + +static inline void hri_rtcmode1_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg |= RTC_MODE1_COUNT_COUNT(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_COUNT_bf(const void *const hw, + hri_rtcmode1_count_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp = (tmp & RTC_MODE1_COUNT_COUNT(mask)) >> RTC_MODE1_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp &= ~RTC_MODE1_COUNT_COUNT_Msk; + tmp |= RTC_MODE1_COUNT_COUNT(data); + ((Rtc *)hw)->MODE1.COUNT.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg &= ~RTC_MODE1_COUNT_COUNT(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg ^= RTC_MODE1_COUNT_COUNT(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_COUNT_bf(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp = (tmp & RTC_MODE1_COUNT_COUNT_Msk) >> RTC_MODE1_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg |= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg = data; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg &= ~mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg ^= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_reg(const void *const hw) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + return ((Rtc *)hw)->MODE1.COUNT.reg; +} + +static inline void hri_rtcmode2_set_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_SECOND(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_SECOND_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_SECOND(mask)) >> RTC_MODE2_CLOCK_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_SECOND_Msk; + tmp |= RTC_MODE2_CLOCK_SECOND(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_SECOND(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_SECOND(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_SECOND_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_SECOND_Msk) >> RTC_MODE2_CLOCK_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MINUTE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MINUTE_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MINUTE(mask)) >> RTC_MODE2_CLOCK_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_MINUTE_Msk; + tmp |= RTC_MODE2_CLOCK_MINUTE(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MINUTE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MINUTE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MINUTE_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MINUTE_Msk) >> RTC_MODE2_CLOCK_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_HOUR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_HOUR_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_HOUR(mask)) >> RTC_MODE2_CLOCK_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_HOUR_Msk; + tmp |= RTC_MODE2_CLOCK_HOUR(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_HOUR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_HOUR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_HOUR_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_HOUR_Msk) >> RTC_MODE2_CLOCK_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_DAY(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_DAY_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_DAY(mask)) >> RTC_MODE2_CLOCK_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_DAY_Msk; + tmp |= RTC_MODE2_CLOCK_DAY(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_DAY(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_DAY(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_DAY_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_DAY_Msk) >> RTC_MODE2_CLOCK_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MONTH(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MONTH_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MONTH(mask)) >> RTC_MODE2_CLOCK_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_MONTH_Msk; + tmp |= RTC_MODE2_CLOCK_MONTH(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MONTH(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MONTH(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MONTH_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MONTH_Msk) >> RTC_MODE2_CLOCK_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_YEAR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_YEAR_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_YEAR(mask)) >> RTC_MODE2_CLOCK_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_YEAR_Msk; + tmp |= RTC_MODE2_CLOCK_YEAR(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_YEAR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_YEAR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_YEAR_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_YEAR_Msk) >> RTC_MODE2_CLOCK_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg = data; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_reg(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return ((Rtc *)hw)->MODE2.CLOCK.reg; +} + +static inline void hri_rtcmode1_set_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg |= RTC_MODE1_PER_PER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp = (tmp & RTC_MODE1_PER_PER(mask)) >> RTC_MODE1_PER_PER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp &= ~RTC_MODE1_PER_PER_Msk; + tmp |= RTC_MODE1_PER_PER(data); + ((Rtc *)hw)->MODE1.PER.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg &= ~RTC_MODE1_PER_PER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg ^= RTC_MODE1_PER_PER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_PER_bf(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp = (tmp & RTC_MODE1_PER_PER_Msk) >> RTC_MODE1_PER_PER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg |= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg = data; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg &= ~mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg ^= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_reg(const void *const hw) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + return ((Rtc *)hw)->MODE1.PER.reg; +} + +static inline void hri_rtcmode0_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg |= RTC_MODE0_COMP_COMP(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_COMP_bf(const void *const hw, uint8_t index, + hri_rtcmode0_comp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp = (tmp & RTC_MODE0_COMP_COMP(mask)) >> RTC_MODE0_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp &= ~RTC_MODE0_COMP_COMP_Msk; + tmp |= RTC_MODE0_COMP_COMP(data); + ((Rtc *)hw)->MODE0.COMP[index].reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg &= ~RTC_MODE0_COMP_COMP(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg ^= RTC_MODE0_COMP_COMP(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_COMP_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp = (tmp & RTC_MODE0_COMP_COMP_Msk) >> RTC_MODE0_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg |= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_reg(const void *const hw, uint8_t index, + hri_rtcmode0_comp_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg = data; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg &= ~mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg ^= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_reg(const void *const hw, uint8_t index) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0); + return ((Rtc *)hw)->MODE0.COMP[index].reg; +} + +static inline void hri_rtcmode1_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg |= RTC_MODE1_COMP_COMP(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_COMP_bf(const void *const hw, uint8_t index, + hri_rtcmode1_comp_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp = (tmp & RTC_MODE1_COMP_COMP(mask)) >> RTC_MODE1_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp &= ~RTC_MODE1_COMP_COMP_Msk; + tmp |= RTC_MODE1_COMP_COMP(data); + ((Rtc *)hw)->MODE1.COMP[index].reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg &= ~RTC_MODE1_COMP_COMP(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg ^= RTC_MODE1_COMP_COMP(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_COMP_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp = (tmp & RTC_MODE1_COMP_COMP_Msk) >> RTC_MODE1_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg |= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_reg(const void *const hw, uint8_t index, + hri_rtcmode1_comp_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg = data; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg &= ~mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg ^= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_reg(const void *const hw, uint8_t index) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1); + return ((Rtc *)hw)->MODE1.COMP[index].reg; +} + +static inline void hri_rtc_set_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_gp_reg_t hri_rtc_get_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.GP[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_gp_reg_t hri_rtc_read_GP_reg(const void *const hw, uint8_t index) +{ + return ((Rtc *)hw)->MODE0.GP[index].reg; +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_rtcmode2_set_DBGCTRL_DBGRUN_bit(a) hri_rtc_set_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode2_get_DBGCTRL_DBGRUN_bit(a) hri_rtc_get_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode2_write_DBGCTRL_DBGRUN_bit(a, b) hri_rtc_write_DBGCTRL_DBGRUN_bit(a, b) +#define hri_rtcmode2_clear_DBGCTRL_DBGRUN_bit(a) hri_rtc_clear_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode2_toggle_DBGCTRL_DBGRUN_bit(a) hri_rtc_toggle_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode2_set_DBGCTRL_reg(a, b) hri_rtc_set_DBGCTRL_reg(a, b) +#define hri_rtcmode2_get_DBGCTRL_reg(a, b) hri_rtc_get_DBGCTRL_reg(a, b) +#define hri_rtcmode2_write_DBGCTRL_reg(a, b) hri_rtc_write_DBGCTRL_reg(a, b) +#define hri_rtcmode2_clear_DBGCTRL_reg(a, b) hri_rtc_clear_DBGCTRL_reg(a, b) +#define hri_rtcmode2_toggle_DBGCTRL_reg(a, b) hri_rtc_toggle_DBGCTRL_reg(a, b) +#define hri_rtcmode2_read_DBGCTRL_reg(a) hri_rtc_read_DBGCTRL_reg(a) +#define hri_rtcmode2_set_FREQCORR_SIGN_bit(a) hri_rtc_set_FREQCORR_SIGN_bit(a) +#define hri_rtcmode2_get_FREQCORR_SIGN_bit(a) hri_rtc_get_FREQCORR_SIGN_bit(a) +#define hri_rtcmode2_write_FREQCORR_SIGN_bit(a, b) hri_rtc_write_FREQCORR_SIGN_bit(a, b) +#define hri_rtcmode2_clear_FREQCORR_SIGN_bit(a) hri_rtc_clear_FREQCORR_SIGN_bit(a) +#define hri_rtcmode2_toggle_FREQCORR_SIGN_bit(a) hri_rtc_toggle_FREQCORR_SIGN_bit(a) +#define hri_rtcmode2_set_FREQCORR_VALUE_bf(a, b) hri_rtc_set_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode2_get_FREQCORR_VALUE_bf(a, b) hri_rtc_get_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode2_write_FREQCORR_VALUE_bf(a, b) hri_rtc_write_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode2_clear_FREQCORR_VALUE_bf(a, b) hri_rtc_clear_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode2_toggle_FREQCORR_VALUE_bf(a, b) hri_rtc_toggle_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode2_read_FREQCORR_VALUE_bf(a) hri_rtc_read_FREQCORR_VALUE_bf(a) +#define hri_rtcmode2_set_FREQCORR_reg(a, b) hri_rtc_set_FREQCORR_reg(a, b) +#define hri_rtcmode2_get_FREQCORR_reg(a, b) hri_rtc_get_FREQCORR_reg(a, b) +#define hri_rtcmode2_write_FREQCORR_reg(a, b) hri_rtc_write_FREQCORR_reg(a, b) +#define hri_rtcmode2_clear_FREQCORR_reg(a, b) hri_rtc_clear_FREQCORR_reg(a, b) +#define hri_rtcmode2_toggle_FREQCORR_reg(a, b) hri_rtc_toggle_FREQCORR_reg(a, b) +#define hri_rtcmode2_read_FREQCORR_reg(a) hri_rtc_read_FREQCORR_reg(a) +#define hri_rtcmode2_set_GP_reg(a, b, c) hri_rtc_set_GP_reg(a, b, c) +#define hri_rtcmode2_get_GP_reg(a, b, c) hri_rtc_get_GP_reg(a, b, c) +#define hri_rtcmode2_write_GP_reg(a, b, c) hri_rtc_write_GP_reg(a, b, c) +#define hri_rtcmode2_clear_GP_reg(a, b, c) hri_rtc_clear_GP_reg(a, b, c) +#define hri_rtcmode2_toggle_GP_reg(a, b, c) hri_rtc_toggle_GP_reg(a, b, c) +#define hri_rtcmode2_read_GP_reg(a, b) hri_rtc_read_GP_reg(a, b) +#define hri_rtcmode0_set_DBGCTRL_DBGRUN_bit(a) hri_rtc_set_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode0_get_DBGCTRL_DBGRUN_bit(a) hri_rtc_get_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode0_write_DBGCTRL_DBGRUN_bit(a, b) hri_rtc_write_DBGCTRL_DBGRUN_bit(a, b) +#define hri_rtcmode0_clear_DBGCTRL_DBGRUN_bit(a) hri_rtc_clear_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode0_toggle_DBGCTRL_DBGRUN_bit(a) hri_rtc_toggle_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode0_set_DBGCTRL_reg(a, b) hri_rtc_set_DBGCTRL_reg(a, b) +#define hri_rtcmode0_get_DBGCTRL_reg(a, b) hri_rtc_get_DBGCTRL_reg(a, b) +#define hri_rtcmode0_write_DBGCTRL_reg(a, b) hri_rtc_write_DBGCTRL_reg(a, b) +#define hri_rtcmode0_clear_DBGCTRL_reg(a, b) hri_rtc_clear_DBGCTRL_reg(a, b) +#define hri_rtcmode0_toggle_DBGCTRL_reg(a, b) hri_rtc_toggle_DBGCTRL_reg(a, b) +#define hri_rtcmode0_read_DBGCTRL_reg(a) hri_rtc_read_DBGCTRL_reg(a) +#define hri_rtcmode0_set_FREQCORR_SIGN_bit(a) hri_rtc_set_FREQCORR_SIGN_bit(a) +#define hri_rtcmode0_get_FREQCORR_SIGN_bit(a) hri_rtc_get_FREQCORR_SIGN_bit(a) +#define hri_rtcmode0_write_FREQCORR_SIGN_bit(a, b) hri_rtc_write_FREQCORR_SIGN_bit(a, b) +#define hri_rtcmode0_clear_FREQCORR_SIGN_bit(a) hri_rtc_clear_FREQCORR_SIGN_bit(a) +#define hri_rtcmode0_toggle_FREQCORR_SIGN_bit(a) hri_rtc_toggle_FREQCORR_SIGN_bit(a) +#define hri_rtcmode0_set_FREQCORR_VALUE_bf(a, b) hri_rtc_set_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode0_get_FREQCORR_VALUE_bf(a, b) hri_rtc_get_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode0_write_FREQCORR_VALUE_bf(a, b) hri_rtc_write_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode0_clear_FREQCORR_VALUE_bf(a, b) hri_rtc_clear_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode0_toggle_FREQCORR_VALUE_bf(a, b) hri_rtc_toggle_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode0_read_FREQCORR_VALUE_bf(a) hri_rtc_read_FREQCORR_VALUE_bf(a) +#define hri_rtcmode0_set_FREQCORR_reg(a, b) hri_rtc_set_FREQCORR_reg(a, b) +#define hri_rtcmode0_get_FREQCORR_reg(a, b) hri_rtc_get_FREQCORR_reg(a, b) +#define hri_rtcmode0_write_FREQCORR_reg(a, b) hri_rtc_write_FREQCORR_reg(a, b) +#define hri_rtcmode0_clear_FREQCORR_reg(a, b) hri_rtc_clear_FREQCORR_reg(a, b) +#define hri_rtcmode0_toggle_FREQCORR_reg(a, b) hri_rtc_toggle_FREQCORR_reg(a, b) +#define hri_rtcmode0_read_FREQCORR_reg(a) hri_rtc_read_FREQCORR_reg(a) +#define hri_rtcmode0_set_GP_reg(a, b, c) hri_rtc_set_GP_reg(a, b, c) +#define hri_rtcmode0_get_GP_reg(a, b, c) hri_rtc_get_GP_reg(a, b, c) +#define hri_rtcmode0_write_GP_reg(a, b, c) hri_rtc_write_GP_reg(a, b, c) +#define hri_rtcmode0_clear_GP_reg(a, b, c) hri_rtc_clear_GP_reg(a, b, c) +#define hri_rtcmode0_toggle_GP_reg(a, b, c) hri_rtc_toggle_GP_reg(a, b, c) +#define hri_rtcmode0_read_GP_reg(a, b) hri_rtc_read_GP_reg(a, b) +#define hri_rtcmode1_set_DBGCTRL_DBGRUN_bit(a) hri_rtc_set_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode1_get_DBGCTRL_DBGRUN_bit(a) hri_rtc_get_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode1_write_DBGCTRL_DBGRUN_bit(a, b) hri_rtc_write_DBGCTRL_DBGRUN_bit(a, b) +#define hri_rtcmode1_clear_DBGCTRL_DBGRUN_bit(a) hri_rtc_clear_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode1_toggle_DBGCTRL_DBGRUN_bit(a) hri_rtc_toggle_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode1_set_DBGCTRL_reg(a, b) hri_rtc_set_DBGCTRL_reg(a, b) +#define hri_rtcmode1_get_DBGCTRL_reg(a, b) hri_rtc_get_DBGCTRL_reg(a, b) +#define hri_rtcmode1_write_DBGCTRL_reg(a, b) hri_rtc_write_DBGCTRL_reg(a, b) +#define hri_rtcmode1_clear_DBGCTRL_reg(a, b) hri_rtc_clear_DBGCTRL_reg(a, b) +#define hri_rtcmode1_toggle_DBGCTRL_reg(a, b) hri_rtc_toggle_DBGCTRL_reg(a, b) +#define hri_rtcmode1_read_DBGCTRL_reg(a) hri_rtc_read_DBGCTRL_reg(a) +#define hri_rtcmode1_set_FREQCORR_SIGN_bit(a) hri_rtc_set_FREQCORR_SIGN_bit(a) +#define hri_rtcmode1_get_FREQCORR_SIGN_bit(a) hri_rtc_get_FREQCORR_SIGN_bit(a) +#define hri_rtcmode1_write_FREQCORR_SIGN_bit(a, b) hri_rtc_write_FREQCORR_SIGN_bit(a, b) +#define hri_rtcmode1_clear_FREQCORR_SIGN_bit(a) hri_rtc_clear_FREQCORR_SIGN_bit(a) +#define hri_rtcmode1_toggle_FREQCORR_SIGN_bit(a) hri_rtc_toggle_FREQCORR_SIGN_bit(a) +#define hri_rtcmode1_set_FREQCORR_VALUE_bf(a, b) hri_rtc_set_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode1_get_FREQCORR_VALUE_bf(a, b) hri_rtc_get_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode1_write_FREQCORR_VALUE_bf(a, b) hri_rtc_write_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode1_clear_FREQCORR_VALUE_bf(a, b) hri_rtc_clear_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode1_toggle_FREQCORR_VALUE_bf(a, b) hri_rtc_toggle_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode1_read_FREQCORR_VALUE_bf(a) hri_rtc_read_FREQCORR_VALUE_bf(a) +#define hri_rtcmode1_set_FREQCORR_reg(a, b) hri_rtc_set_FREQCORR_reg(a, b) +#define hri_rtcmode1_get_FREQCORR_reg(a, b) hri_rtc_get_FREQCORR_reg(a, b) +#define hri_rtcmode1_write_FREQCORR_reg(a, b) hri_rtc_write_FREQCORR_reg(a, b) +#define hri_rtcmode1_clear_FREQCORR_reg(a, b) hri_rtc_clear_FREQCORR_reg(a, b) +#define hri_rtcmode1_toggle_FREQCORR_reg(a, b) hri_rtc_toggle_FREQCORR_reg(a, b) +#define hri_rtcmode1_read_FREQCORR_reg(a) hri_rtc_read_FREQCORR_reg(a) +#define hri_rtcmode1_set_GP_reg(a, b, c) hri_rtc_set_GP_reg(a, b, c) +#define hri_rtcmode1_get_GP_reg(a, b, c) hri_rtc_get_GP_reg(a, b, c) +#define hri_rtcmode1_write_GP_reg(a, b, c) hri_rtc_write_GP_reg(a, b, c) +#define hri_rtcmode1_clear_GP_reg(a, b, c) hri_rtc_clear_GP_reg(a, b, c) +#define hri_rtcmode1_toggle_GP_reg(a, b, c) hri_rtc_toggle_GP_reg(a, b, c) +#define hri_rtcmode1_read_GP_reg(a, b) hri_rtc_read_GP_reg(a, b) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_RTC_L21_H_INCLUDED */ +#endif /* _SAML21_RTC_COMPONENT_ */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_sercom_l21.h b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_sercom_l21.h new file mode 100644 index 00000000..abc55703 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_sercom_l21.h @@ -0,0 +1,7499 @@ +/** + * \file + * + * \brief SAM SERCOM + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_SERCOM_COMPONENT_ +#ifndef _HRI_SERCOM_L21_H_INCLUDED_ +#define _HRI_SERCOM_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SERCOM_CRITICAL_SECTIONS) +#define SERCOM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SERCOM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SERCOM_CRITICAL_SECTION_ENTER() +#define SERCOM_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_sercomi2cm_status_reg_t; +typedef uint16_t hri_sercomi2cs_status_reg_t; +typedef uint16_t hri_sercomspi_status_reg_t; +typedef uint16_t hri_sercomusart_baud_reg_t; +typedef uint16_t hri_sercomusart_data_reg_t; +typedef uint16_t hri_sercomusart_status_reg_t; +typedef uint32_t hri_sercomi2cm_addr_reg_t; +typedef uint32_t hri_sercomi2cm_baud_reg_t; +typedef uint32_t hri_sercomi2cm_ctrla_reg_t; +typedef uint32_t hri_sercomi2cm_ctrlb_reg_t; +typedef uint32_t hri_sercomi2cm_syncbusy_reg_t; +typedef uint32_t hri_sercomi2cs_addr_reg_t; +typedef uint32_t hri_sercomi2cs_ctrla_reg_t; +typedef uint32_t hri_sercomi2cs_ctrlb_reg_t; +typedef uint32_t hri_sercomi2cs_syncbusy_reg_t; +typedef uint32_t hri_sercomspi_addr_reg_t; +typedef uint32_t hri_sercomspi_ctrla_reg_t; +typedef uint32_t hri_sercomspi_ctrlb_reg_t; +typedef uint32_t hri_sercomspi_data_reg_t; +typedef uint32_t hri_sercomspi_syncbusy_reg_t; +typedef uint32_t hri_sercomusart_ctrla_reg_t; +typedef uint32_t hri_sercomusart_ctrlb_reg_t; +typedef uint32_t hri_sercomusart_syncbusy_reg_t; +typedef uint8_t hri_sercomi2cm_data_reg_t; +typedef uint8_t hri_sercomi2cm_dbgctrl_reg_t; +typedef uint8_t hri_sercomi2cm_intenset_reg_t; +typedef uint8_t hri_sercomi2cm_intflag_reg_t; +typedef uint8_t hri_sercomi2cs_data_reg_t; +typedef uint8_t hri_sercomi2cs_intenset_reg_t; +typedef uint8_t hri_sercomi2cs_intflag_reg_t; +typedef uint8_t hri_sercomspi_baud_reg_t; +typedef uint8_t hri_sercomspi_dbgctrl_reg_t; +typedef uint8_t hri_sercomspi_intenset_reg_t; +typedef uint8_t hri_sercomspi_intflag_reg_t; +typedef uint8_t hri_sercomusart_dbgctrl_reg_t; +typedef uint8_t hri_sercomusart_intenset_reg_t; +typedef uint8_t hri_sercomusart_intflag_reg_t; +typedef uint8_t hri_sercomusart_rxpl_reg_t; + +static inline void hri_sercomi2cm_wait_for_sync(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomi2cm_is_syncing(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg; +} + +static inline void hri_sercomi2cs_wait_for_sync(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomi2cs_is_syncing(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg; +} + +static inline void hri_sercomspi_wait_for_sync(const void *const hw, hri_sercomspi_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->SPI.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomspi_is_syncing(const void *const hw, hri_sercomspi_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg; +} + +static inline void hri_sercomusart_wait_for_sync(const void *const hw, hri_sercomusart_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->USART.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomusart_is_syncing(const void *const hw, hri_sercomusart_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->USART.SYNCBUSY.reg & reg; +} + +static inline bool hri_sercomi2cm_get_INTFLAG_MB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB; +} + +static inline bool hri_sercomi2cm_get_INTFLAG_SB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB; +} + +static inline bool hri_sercomi2cm_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR; +} + +static inline bool hri_sercomi2cm_get_interrupt_MB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos; +} + +static inline void hri_sercomi2cm_clear_interrupt_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB; +} + +static inline bool hri_sercomi2cm_get_interrupt_SB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos; +} + +static inline void hri_sercomi2cm_clear_interrupt_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB; +} + +static inline bool hri_sercomi2cm_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cm_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR; +} + +static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_get_INTFLAG_reg(const void *const hw, + hri_sercomi2cm_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.INTFLAG.reg; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cm_intflag_reg_t mask) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = mask; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_PREC_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_AMATCH_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_DRDY_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR; +} + +static inline bool hri_sercomi2cs_get_interrupt_PREC_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; +} + +static inline bool hri_sercomi2cs_get_interrupt_AMATCH_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; +} + +static inline bool hri_sercomi2cs_get_interrupt_DRDY_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY; +} + +static inline bool hri_sercomi2cs_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR; +} + +static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_get_INTFLAG_reg(const void *const hw, + hri_sercomi2cs_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CS.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.INTFLAG.reg; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cs_intflag_reg_t mask) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = mask; +} + +static inline bool hri_sercomspi_get_INTFLAG_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE; +} + +static inline bool hri_sercomspi_get_INTFLAG_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC; +} + +static inline bool hri_sercomspi_get_INTFLAG_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC; +} + +static inline bool hri_sercomspi_get_INTFLAG_SSL_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL; +} + +static inline bool hri_sercomspi_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR; +} + +static inline bool hri_sercomspi_get_interrupt_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE; +} + +static inline bool hri_sercomspi_get_interrupt_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC; +} + +static inline bool hri_sercomspi_get_interrupt_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC; +} + +static inline bool hri_sercomspi_get_interrupt_SSL_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL; +} + +static inline bool hri_sercomspi_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR; +} + +static inline hri_sercomspi_intflag_reg_t hri_sercomspi_get_INTFLAG_reg(const void *const hw, + hri_sercomspi_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomspi_intflag_reg_t hri_sercomspi_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.INTFLAG.reg; +} + +static inline void hri_sercomspi_clear_INTFLAG_reg(const void *const hw, hri_sercomspi_intflag_reg_t mask) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = mask; +} + +static inline bool hri_sercomusart_get_INTFLAG_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE; +} + +static inline bool hri_sercomusart_get_INTFLAG_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC; +} + +static inline bool hri_sercomusart_get_INTFLAG_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC; +} + +static inline bool hri_sercomusart_get_INTFLAG_RXS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS; +} + +static inline bool hri_sercomusart_get_INTFLAG_CTSIC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC; +} + +static inline bool hri_sercomusart_get_INTFLAG_RXBRK_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK; +} + +static inline bool hri_sercomusart_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR; +} + +static inline bool hri_sercomusart_get_interrupt_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE; +} + +static inline bool hri_sercomusart_get_interrupt_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC; +} + +static inline bool hri_sercomusart_get_interrupt_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC; +} + +static inline bool hri_sercomusart_get_interrupt_RXS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS; +} + +static inline bool hri_sercomusart_get_interrupt_CTSIC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC; +} + +static inline bool hri_sercomusart_get_interrupt_RXBRK_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK; +} + +static inline bool hri_sercomusart_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR; +} + +static inline hri_sercomusart_intflag_reg_t hri_sercomusart_get_INTFLAG_reg(const void *const hw, + hri_sercomusart_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomusart_intflag_reg_t hri_sercomusart_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.INTFLAG.reg; +} + +static inline void hri_sercomusart_clear_INTFLAG_reg(const void *const hw, hri_sercomusart_intflag_reg_t mask) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = mask; +} + +static inline void hri_sercomi2cm_set_INTEN_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB; +} + +static inline bool hri_sercomi2cm_get_INTEN_MB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_MB) >> SERCOM_I2CM_INTENSET_MB_Pos; +} + +static inline void hri_sercomi2cm_write_INTEN_MB_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB; + } else { + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB; + } +} + +static inline void hri_sercomi2cm_clear_INTEN_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB; +} + +static inline void hri_sercomi2cm_set_INTEN_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB; +} + +static inline bool hri_sercomi2cm_get_INTEN_SB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_SB) >> SERCOM_I2CM_INTENSET_SB_Pos; +} + +static inline void hri_sercomi2cm_write_INTEN_SB_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB; + } else { + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB; + } +} + +static inline void hri_sercomi2cm_clear_INTEN_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB; +} + +static inline void hri_sercomi2cm_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR; +} + +static inline bool hri_sercomi2cm_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_ERROR) >> SERCOM_I2CM_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomi2cm_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR; + } else { + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR; + } +} + +static inline void hri_sercomi2cm_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR; +} + +static inline void hri_sercomi2cm_set_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = mask; +} + +static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_get_INTEN_reg(const void *const hw, + hri_sercomi2cm_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.INTENSET.reg; +} + +static inline void hri_sercomi2cm_write_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t data) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = data; + ((Sercom *)hw)->I2CM.INTENCLR.reg = ~data; +} + +static inline void hri_sercomi2cm_clear_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = mask; +} + +static inline void hri_sercomi2cs_set_INTEN_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC; +} + +static inline bool hri_sercomi2cs_get_INTEN_PREC_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_PREC) >> SERCOM_I2CS_INTENSET_PREC_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_PREC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC; +} + +static inline void hri_sercomi2cs_set_INTEN_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH; +} + +static inline bool hri_sercomi2cs_get_INTEN_AMATCH_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_AMATCH) >> SERCOM_I2CS_INTENSET_AMATCH_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_AMATCH_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH; +} + +static inline void hri_sercomi2cs_set_INTEN_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY; +} + +static inline bool hri_sercomi2cs_get_INTEN_DRDY_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_DRDY) >> SERCOM_I2CS_INTENSET_DRDY_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_DRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY; +} + +static inline void hri_sercomi2cs_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR; +} + +static inline bool hri_sercomi2cs_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_ERROR) >> SERCOM_I2CS_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR; +} + +static inline void hri_sercomi2cs_set_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = mask; +} + +static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_get_INTEN_reg(const void *const hw, + hri_sercomi2cs_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CS.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.INTENSET.reg; +} + +static inline void hri_sercomi2cs_write_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t data) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = data; + ((Sercom *)hw)->I2CS.INTENCLR.reg = ~data; +} + +static inline void hri_sercomi2cs_clear_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = mask; +} + +static inline void hri_sercomspi_set_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE; +} + +static inline bool hri_sercomspi_get_INTEN_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_DRE) >> SERCOM_SPI_INTENSET_DRE_Pos; +} + +static inline void hri_sercomspi_write_INTEN_DRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE; + } +} + +static inline void hri_sercomspi_clear_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE; +} + +static inline void hri_sercomspi_set_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC; +} + +static inline bool hri_sercomspi_get_INTEN_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_TXC) >> SERCOM_SPI_INTENSET_TXC_Pos; +} + +static inline void hri_sercomspi_write_INTEN_TXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC; + } +} + +static inline void hri_sercomspi_clear_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC; +} + +static inline void hri_sercomspi_set_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC; +} + +static inline bool hri_sercomspi_get_INTEN_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_RXC) >> SERCOM_SPI_INTENSET_RXC_Pos; +} + +static inline void hri_sercomspi_write_INTEN_RXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC; + } +} + +static inline void hri_sercomspi_clear_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC; +} + +static inline void hri_sercomspi_set_INTEN_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL; +} + +static inline bool hri_sercomspi_get_INTEN_SSL_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_SSL) >> SERCOM_SPI_INTENSET_SSL_Pos; +} + +static inline void hri_sercomspi_write_INTEN_SSL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL; + } +} + +static inline void hri_sercomspi_clear_INTEN_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL; +} + +static inline void hri_sercomspi_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR; +} + +static inline bool hri_sercomspi_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_ERROR) >> SERCOM_SPI_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomspi_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR; + } +} + +static inline void hri_sercomspi_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR; +} + +static inline void hri_sercomspi_set_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = mask; +} + +static inline hri_sercomspi_intenset_reg_t hri_sercomspi_get_INTEN_reg(const void *const hw, + hri_sercomspi_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomspi_intenset_reg_t hri_sercomspi_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.INTENSET.reg; +} + +static inline void hri_sercomspi_write_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t data) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = data; + ((Sercom *)hw)->SPI.INTENCLR.reg = ~data; +} + +static inline void hri_sercomspi_clear_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = mask; +} + +static inline void hri_sercomusart_set_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE; +} + +static inline bool hri_sercomusart_get_INTEN_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_DRE) >> SERCOM_USART_INTENSET_DRE_Pos; +} + +static inline void hri_sercomusart_write_INTEN_DRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE; + } +} + +static inline void hri_sercomusart_clear_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE; +} + +static inline void hri_sercomusart_set_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC; +} + +static inline bool hri_sercomusart_get_INTEN_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_TXC) >> SERCOM_USART_INTENSET_TXC_Pos; +} + +static inline void hri_sercomusart_write_INTEN_TXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC; + } +} + +static inline void hri_sercomusart_clear_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC; +} + +static inline void hri_sercomusart_set_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC; +} + +static inline bool hri_sercomusart_get_INTEN_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXC) >> SERCOM_USART_INTENSET_RXC_Pos; +} + +static inline void hri_sercomusart_write_INTEN_RXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC; + } +} + +static inline void hri_sercomusart_clear_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC; +} + +static inline void hri_sercomusart_set_INTEN_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS; +} + +static inline bool hri_sercomusart_get_INTEN_RXS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXS) >> SERCOM_USART_INTENSET_RXS_Pos; +} + +static inline void hri_sercomusart_write_INTEN_RXS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS; + } +} + +static inline void hri_sercomusart_clear_INTEN_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS; +} + +static inline void hri_sercomusart_set_INTEN_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC; +} + +static inline bool hri_sercomusart_get_INTEN_CTSIC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_CTSIC) >> SERCOM_USART_INTENSET_CTSIC_Pos; +} + +static inline void hri_sercomusart_write_INTEN_CTSIC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC; + } +} + +static inline void hri_sercomusart_clear_INTEN_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC; +} + +static inline void hri_sercomusart_set_INTEN_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK; +} + +static inline bool hri_sercomusart_get_INTEN_RXBRK_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXBRK) >> SERCOM_USART_INTENSET_RXBRK_Pos; +} + +static inline void hri_sercomusart_write_INTEN_RXBRK_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK; + } +} + +static inline void hri_sercomusart_clear_INTEN_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK; +} + +static inline void hri_sercomusart_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR; +} + +static inline bool hri_sercomusart_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_ERROR) >> SERCOM_USART_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomusart_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR; + } +} + +static inline void hri_sercomusart_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR; +} + +static inline void hri_sercomusart_set_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask) +{ + ((Sercom *)hw)->USART.INTENSET.reg = mask; +} + +static inline hri_sercomusart_intenset_reg_t hri_sercomusart_get_INTEN_reg(const void *const hw, + hri_sercomusart_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomusart_intenset_reg_t hri_sercomusart_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.INTENSET.reg; +} + +static inline void hri_sercomusart_write_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t data) +{ + ((Sercom *)hw)->USART.INTENSET.reg = data; + ((Sercom *)hw)->USART.INTENCLR.reg = ~data; +} + +static inline void hri_sercomusart_clear_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = mask; +} + +static inline bool hri_sercomi2cm_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SWRST) >> SERCOM_I2CM_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomi2cm_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_ENABLE) >> SERCOM_I2CM_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_sercomi2cm_get_SYNCBUSY_SYSOP_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SYSOP) >> SERCOM_I2CM_SYNCBUSY_SYSOP_Pos; +} + +static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_get_SYNCBUSY_reg(const void *const hw, + hri_sercomi2cm_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.SYNCBUSY.reg; +} + +static inline bool hri_sercomi2cs_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_SWRST) >> SERCOM_I2CS_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomi2cs_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_ENABLE) >> SERCOM_I2CS_SYNCBUSY_ENABLE_Pos; +} + +static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_get_SYNCBUSY_reg(const void *const hw, + hri_sercomi2cs_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.SYNCBUSY.reg; +} + +static inline bool hri_sercomspi_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_SWRST) >> SERCOM_SPI_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomspi_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_ENABLE) >> SERCOM_SPI_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_sercomspi_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_CTRLB) >> SERCOM_SPI_SYNCBUSY_CTRLB_Pos; +} + +static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_get_SYNCBUSY_reg(const void *const hw, + hri_sercomspi_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.SYNCBUSY.reg; +} + +static inline bool hri_sercomusart_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_SWRST) >> SERCOM_USART_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomusart_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_ENABLE) >> SERCOM_USART_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_sercomusart_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_CTRLB) >> SERCOM_USART_SYNCBUSY_CTRLB_Pos; +} + +static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_get_SYNCBUSY_reg(const void *const hw, + hri_sercomusart_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.SYNCBUSY.reg; +} + +static inline void hri_sercomi2cm_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SWRST; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SWRST) >> SERCOM_I2CM_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_ENABLE) >> SERCOM_I2CM_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_ENABLE; + tmp |= value << SERCOM_I2CM_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_ENABLE; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_RUNSTDBY; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_RUNSTDBY) >> SERCOM_I2CM_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_RUNSTDBY; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_RUNSTDBY; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_PINOUT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_PINOUT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_PINOUT) >> SERCOM_I2CM_CTRLA_PINOUT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_PINOUT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_PINOUT; + tmp |= value << SERCOM_I2CM_CTRLA_PINOUT_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_PINOUT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_PINOUT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_MEXTTOEN) >> SERCOM_I2CM_CTRLA_MEXTTOEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_MEXTTOEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_MEXTTOEN; + tmp |= value << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SEXTTOEN) >> SERCOM_I2CM_CTRLA_SEXTTOEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SEXTTOEN; + tmp |= value << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SCLSM; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_SCLSM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SCLSM) >> SERCOM_I2CM_CTRLA_SCLSM_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SCLSM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SCLSM; + tmp |= value << SERCOM_I2CM_CTRLA_SCLSM_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SCLSM; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SCLSM; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_LOWTOUTEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_LOWTOUTEN) >> SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN; + tmp |= value << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_LOWTOUTEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MODE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_MODE(mask)) >> SERCOM_I2CM_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_MODE_Msk; + tmp |= SERCOM_I2CM_CTRLA_MODE(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MODE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MODE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_MODE_Msk) >> SERCOM_I2CM_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SDAHOLD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SDAHOLD_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SDAHOLD_Msk; + tmp |= SERCOM_I2CM_CTRLA_SDAHOLD(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SDAHOLD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SDAHOLD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SDAHOLD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SPEED(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SPEED_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED(mask)) >> SERCOM_I2CM_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SPEED_Msk; + tmp |= SERCOM_I2CM_CTRLA_SPEED(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SPEED(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SPEED(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SPEED_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_INACTOUT(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_INACTOUT_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT(mask)) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_INACTOUT_Msk; + tmp |= SERCOM_I2CM_CTRLA_INACTOUT(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_INACTOUT(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_INACTOUT(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_INACTOUT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT_Msk) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_reg(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg = data; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + return ((Sercom *)hw)->I2CM.CTRLA.reg; +} + +static inline void hri_sercomi2cs_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SWRST; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SWRST) >> SERCOM_I2CS_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_ENABLE; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_ENABLE) >> SERCOM_I2CS_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_ENABLE; + tmp |= value << SERCOM_I2CS_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_ENABLE; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_ENABLE; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_RUNSTDBY; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_RUNSTDBY) >> SERCOM_I2CS_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_RUNSTDBY; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_RUNSTDBY; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_PINOUT; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_PINOUT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_PINOUT) >> SERCOM_I2CS_CTRLA_PINOUT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_PINOUT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_PINOUT; + tmp |= value << SERCOM_I2CS_CTRLA_PINOUT_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_PINOUT; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_PINOUT; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SEXTTOEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SEXTTOEN) >> SERCOM_I2CS_CTRLA_SEXTTOEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SEXTTOEN; + tmp |= value << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SEXTTOEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SEXTTOEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SCLSM; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_SCLSM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SCLSM) >> SERCOM_I2CS_CTRLA_SCLSM_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SCLSM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SCLSM; + tmp |= value << SERCOM_I2CS_CTRLA_SCLSM_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SCLSM; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SCLSM; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_LOWTOUTEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_LOWTOUTEN) >> SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN; + tmp |= value << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_LOWTOUTEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_MODE(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_MODE(mask)) >> SERCOM_I2CS_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_MODE_Msk; + tmp |= SERCOM_I2CS_CTRLA_MODE(data); + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_MODE(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_MODE(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_MODE_Msk) >> SERCOM_I2CS_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SDAHOLD(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SDAHOLD_bf(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SDAHOLD_Msk; + tmp |= SERCOM_I2CS_CTRLA_SDAHOLD(data); + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SDAHOLD(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SDAHOLD(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SDAHOLD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SPEED(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SPEED_bf(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED(mask)) >> SERCOM_I2CS_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SPEED_Msk; + tmp |= SERCOM_I2CS_CTRLA_SPEED(data); + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SPEED(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SPEED(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SPEED_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED_Msk) >> SERCOM_I2CS_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= mask; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_reg(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg = data; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~mask; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= mask; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_reg(const void *const hw) +{ + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + return ((Sercom *)hw)->I2CS.CTRLA.reg; +} + +static inline void hri_sercomspi_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_SWRST; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_SWRST) >> SERCOM_SPI_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_ENABLE) >> SERCOM_SPI_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_ENABLE; + tmp |= value << SERCOM_SPI_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_ENABLE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_RUNSTDBY; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_RUNSTDBY) >> SERCOM_SPI_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_SPI_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_RUNSTDBY; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_RUNSTDBY; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_IBON; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_IBON_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_IBON) >> SERCOM_SPI_CTRLA_IBON_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_IBON_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_IBON; + tmp |= value << SERCOM_SPI_CTRLA_IBON_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_IBON; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_IBON; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_CPHA_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPHA; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_CPHA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_CPHA) >> SERCOM_SPI_CTRLA_CPHA_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_CPHA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_CPHA; + tmp |= value << SERCOM_SPI_CTRLA_CPHA_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_CPHA_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPHA; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_CPHA_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPHA; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPOL; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_CPOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_CPOL) >> SERCOM_SPI_CTRLA_CPOL_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_CPOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_CPOL; + tmp |= value << SERCOM_SPI_CTRLA_CPOL_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPOL; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPOL; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DORD; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_DORD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DORD) >> SERCOM_SPI_CTRLA_DORD_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_DORD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_DORD; + tmp |= value << SERCOM_SPI_CTRLA_DORD_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DORD; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DORD; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_MODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_MODE(mask)) >> SERCOM_SPI_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_MODE_Msk; + tmp |= SERCOM_SPI_CTRLA_MODE(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_MODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_MODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_MODE_Msk) >> SERCOM_SPI_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DOPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DOPO_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DOPO(mask)) >> SERCOM_SPI_CTRLA_DOPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_DOPO_Msk; + tmp |= SERCOM_SPI_CTRLA_DOPO(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DOPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DOPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DOPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DOPO_Msk) >> SERCOM_SPI_CTRLA_DOPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DIPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DIPO_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DIPO(mask)) >> SERCOM_SPI_CTRLA_DIPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_DIPO_Msk; + tmp |= SERCOM_SPI_CTRLA_DIPO(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DIPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DIPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DIPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DIPO_Msk) >> SERCOM_SPI_CTRLA_DIPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_FORM(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_FORM_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_FORM(mask)) >> SERCOM_SPI_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_FORM_Msk; + tmp |= SERCOM_SPI_CTRLA_FORM(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_FORM(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_FORM(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_FORM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_FORM_Msk) >> SERCOM_SPI_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_reg(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg = data; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_reg(const void *const hw) +{ + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + return ((Sercom *)hw)->SPI.CTRLA.reg; +} + +static inline void hri_sercomusart_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SWRST; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SWRST) >> SERCOM_USART_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_ENABLE) >> SERCOM_USART_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_ENABLE; + tmp |= value << SERCOM_USART_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_ENABLE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RUNSTDBY; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_RUNSTDBY) >> SERCOM_USART_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_USART_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RUNSTDBY; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RUNSTDBY; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_IBON; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_IBON_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_IBON) >> SERCOM_USART_CTRLA_IBON_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_IBON_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_IBON; + tmp |= value << SERCOM_USART_CTRLA_IBON_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_IBON; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_IBON; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_CMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_CMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_CMODE) >> SERCOM_USART_CTRLA_CMODE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_CMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_CMODE; + tmp |= value << SERCOM_USART_CTRLA_CMODE_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_CMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_CMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CPOL; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_CPOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_CPOL) >> SERCOM_USART_CTRLA_CPOL_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_CPOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_CPOL; + tmp |= value << SERCOM_USART_CTRLA_CPOL_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CPOL; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CPOL; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_DORD; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_DORD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_DORD) >> SERCOM_USART_CTRLA_DORD_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_DORD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_DORD; + tmp |= value << SERCOM_USART_CTRLA_DORD_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_DORD; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_DORD; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_MODE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_MODE(mask)) >> SERCOM_USART_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_MODE_Msk; + tmp |= SERCOM_USART_CTRLA_MODE(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_MODE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_MODE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_MODE_Msk) >> SERCOM_USART_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPR(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPR_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPR(mask)) >> SERCOM_USART_CTRLA_SAMPR_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_SAMPR_Msk; + tmp |= SERCOM_USART_CTRLA_SAMPR(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPR(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPR(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPR_Msk) >> SERCOM_USART_CTRLA_SAMPR_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_TXPO_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_TXPO(mask)) >> SERCOM_USART_CTRLA_TXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_TXPO_Msk; + tmp |= SERCOM_USART_CTRLA_TXPO(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_TXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_TXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_TXPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_TXPO_Msk) >> SERCOM_USART_CTRLA_TXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_RXPO_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_RXPO(mask)) >> SERCOM_USART_CTRLA_RXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_RXPO_Msk; + tmp |= SERCOM_USART_CTRLA_RXPO(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_RXPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_RXPO_Msk) >> SERCOM_USART_CTRLA_RXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPA(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPA_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPA(mask)) >> SERCOM_USART_CTRLA_SAMPA_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_SAMPA_Msk; + tmp |= SERCOM_USART_CTRLA_SAMPA(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPA(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPA(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPA_Msk) >> SERCOM_USART_CTRLA_SAMPA_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_FORM(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_FORM_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_FORM(mask)) >> SERCOM_USART_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_FORM_Msk; + tmp |= SERCOM_USART_CTRLA_FORM(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_FORM(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_FORM(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_FORM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_FORM_Msk) >> SERCOM_USART_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_reg(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg = data; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_reg(const void *const hw) +{ + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + return ((Sercom *)hw)->USART.CTRLA.reg; +} + +static inline void hri_sercomi2cm_set_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_SMEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLB_SMEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_SMEN) >> SERCOM_I2CM_CTRLB_SMEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_SMEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_SMEN; + tmp |= value << SERCOM_I2CM_CTRLB_SMEN_Pos; + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_SMEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_SMEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLB_QCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_QCEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLB_QCEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_QCEN) >> SERCOM_I2CM_CTRLB_QCEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_QCEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_QCEN; + tmp |= value << SERCOM_I2CM_CTRLB_QCEN_Pos; + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_QCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_QCEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_QCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_QCEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLB_ACKACT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_ACKACT) >> SERCOM_I2CM_CTRLB_ACKACT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_ACKACT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_ACKACT; + tmp |= value << SERCOM_I2CM_CTRLB_ACKACT_Pos; + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_ACKACT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_CMD_bf(const void *const hw, + hri_sercomi2cm_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_CMD(mask)) >> SERCOM_I2CM_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_CMD_Msk; + tmp |= SERCOM_I2CM_CTRLB_CMD(data); + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_CMD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_CMD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_CMD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_CMD_Msk) >> SERCOM_I2CM_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_reg(const void *const hw, + hri_sercomi2cm_ctrlb_reg_t mask) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg = data; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return ((Sercom *)hw)->I2CM.CTRLB.reg; +} + +static inline void hri_sercomi2cs_set_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_SMEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_SMEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_SMEN) >> SERCOM_I2CS_CTRLB_SMEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_SMEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_SMEN; + tmp |= value << SERCOM_I2CS_CTRLB_SMEN_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_SMEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_SMEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_GCMD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_GCMD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_GCMD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_GCMD) >> SERCOM_I2CS_CTRLB_GCMD_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_GCMD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_GCMD; + tmp |= value << SERCOM_I2CS_CTRLB_GCMD_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_GCMD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_GCMD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_GCMD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_GCMD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_AACKEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AACKEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_AACKEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_AACKEN) >> SERCOM_I2CS_CTRLB_AACKEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_AACKEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_AACKEN; + tmp |= value << SERCOM_I2CS_CTRLB_AACKEN_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_AACKEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AACKEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_AACKEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AACKEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_ACKACT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_ACKACT) >> SERCOM_I2CS_CTRLB_ACKACT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_ACKACT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_ACKACT; + tmp |= value << SERCOM_I2CS_CTRLB_ACKACT_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_ACKACT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AMODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_AMODE_bf(const void *const hw, + hri_sercomi2cs_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE(mask)) >> SERCOM_I2CS_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_AMODE_Msk; + tmp |= SERCOM_I2CS_CTRLB_AMODE(data); + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AMODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AMODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_AMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE_Msk) >> SERCOM_I2CS_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_CMD_bf(const void *const hw, + hri_sercomi2cs_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_CMD(mask)) >> SERCOM_I2CS_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_CMD_Msk; + tmp |= SERCOM_I2CS_CTRLB_CMD(data); + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_CMD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_CMD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_CMD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_CMD_Msk) >> SERCOM_I2CS_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_reg(const void *const hw, + hri_sercomi2cs_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.CTRLB.reg; +} + +static inline void hri_sercomspi_set_CTRLB_PLOADEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_PLOADEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_PLOADEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_PLOADEN) >> SERCOM_SPI_CTRLB_PLOADEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_PLOADEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_PLOADEN; + tmp |= value << SERCOM_SPI_CTRLB_PLOADEN_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_PLOADEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_PLOADEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_PLOADEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_PLOADEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_SSDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_SSDE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_SSDE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_SSDE) >> SERCOM_SPI_CTRLB_SSDE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_SSDE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_SSDE; + tmp |= value << SERCOM_SPI_CTRLB_SSDE_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_SSDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_SSDE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_SSDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_SSDE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_MSSEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_MSSEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_MSSEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_MSSEN) >> SERCOM_SPI_CTRLB_MSSEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_MSSEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_MSSEN; + tmp |= value << SERCOM_SPI_CTRLB_MSSEN_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_MSSEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_MSSEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_MSSEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_MSSEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_RXEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_RXEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_RXEN) >> SERCOM_SPI_CTRLB_RXEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_RXEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_RXEN; + tmp |= value << SERCOM_SPI_CTRLB_RXEN_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_RXEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_RXEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_CHSIZE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_CHSIZE_bf(const void *const hw, + hri_sercomspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE(mask)) >> SERCOM_SPI_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_CHSIZE_Msk; + tmp |= SERCOM_SPI_CTRLB_CHSIZE(data); + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_CHSIZE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_CHSIZE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_CHSIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE_Msk) >> SERCOM_SPI_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_AMODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_AMODE_bf(const void *const hw, + hri_sercomspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_AMODE(mask)) >> SERCOM_SPI_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_AMODE_Msk; + tmp |= SERCOM_SPI_CTRLB_AMODE(data); + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_AMODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_AMODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_AMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_AMODE_Msk) >> SERCOM_SPI_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_reg(const void *const hw, + hri_sercomspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg = data; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_reg(const void *const hw) +{ + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + return ((Sercom *)hw)->SPI.CTRLB.reg; +} + +static inline void hri_sercomusart_set_CTRLB_SBMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SBMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_SBMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_SBMODE) >> SERCOM_USART_CTRLB_SBMODE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_SBMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_SBMODE; + tmp |= value << SERCOM_USART_CTRLB_SBMODE_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_SBMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SBMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_SBMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SBMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_COLDEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_COLDEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_COLDEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_COLDEN) >> SERCOM_USART_CTRLB_COLDEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_COLDEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_COLDEN; + tmp |= value << SERCOM_USART_CTRLB_COLDEN_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_COLDEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_COLDEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_COLDEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_COLDEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_SFDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SFDE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_SFDE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_SFDE) >> SERCOM_USART_CTRLB_SFDE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_SFDE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_SFDE; + tmp |= value << SERCOM_USART_CTRLB_SFDE_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_SFDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SFDE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_SFDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SFDE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_ENC_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_ENC; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_ENC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_ENC) >> SERCOM_USART_CTRLB_ENC_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_ENC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_ENC; + tmp |= value << SERCOM_USART_CTRLB_ENC_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_ENC_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_ENC; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_ENC_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_ENC; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_PMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_PMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_PMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_PMODE) >> SERCOM_USART_CTRLB_PMODE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_PMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_PMODE; + tmp |= value << SERCOM_USART_CTRLB_PMODE_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_PMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_PMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_PMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_PMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_TXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_TXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_TXEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_TXEN) >> SERCOM_USART_CTRLB_TXEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_TXEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_TXEN; + tmp |= value << SERCOM_USART_CTRLB_TXEN_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_TXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_TXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_TXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_TXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_RXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_RXEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_RXEN) >> SERCOM_USART_CTRLB_RXEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_RXEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_RXEN; + tmp |= value << SERCOM_USART_CTRLB_RXEN_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_RXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_RXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_CHSIZE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_CHSIZE_bf(const void *const hw, + hri_sercomusart_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE(mask)) >> SERCOM_USART_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_CHSIZE_Msk; + tmp |= SERCOM_USART_CTRLB_CHSIZE(data); + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_CHSIZE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_CHSIZE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_CHSIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE_Msk) >> SERCOM_USART_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_reg(const void *const hw, + hri_sercomusart_ctrlb_reg_t mask) +{ + uint32_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg = data; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_reg(const void *const hw) +{ + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + return ((Sercom *)hw)->USART.CTRLB.reg; +} + +static inline void hri_sercomi2cm_set_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUD_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUD(mask)) >> SERCOM_I2CM_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_BAUD_Msk; + tmp |= SERCOM_I2CM_BAUD_BAUD(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUD_Msk) >> SERCOM_I2CM_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUDLOW_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW(mask)) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_BAUDLOW_Msk; + tmp |= SERCOM_I2CM_BAUD_BAUDLOW(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUDLOW_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW_Msk) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUD_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD(mask)) >> SERCOM_I2CM_BAUD_HSBAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_HSBAUD_Msk; + tmp |= SERCOM_I2CM_BAUD_HSBAUD(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD_Msk) >> SERCOM_I2CM_BAUD_HSBAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUDLOW_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW(mask)) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_HSBAUDLOW_Msk; + tmp |= SERCOM_I2CM_BAUD_HSBAUDLOW(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUDLOW_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW_Msk) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_reg(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.BAUD.reg; +} + +static inline void hri_sercomspi_set_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg |= SERCOM_SPI_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_BAUD_bf(const void *const hw, + hri_sercomspi_baud_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp = (tmp & SERCOM_SPI_BAUD_BAUD(mask)) >> SERCOM_SPI_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t data) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp &= ~SERCOM_SPI_BAUD_BAUD_Msk; + tmp |= SERCOM_SPI_BAUD_BAUD(data); + ((Sercom *)hw)->SPI.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg &= ~SERCOM_SPI_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg ^= SERCOM_SPI_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_BAUD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp = (tmp & SERCOM_SPI_BAUD_BAUD_Msk) >> SERCOM_SPI_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.BAUD.reg; +} + +static inline void hri_sercomusart_set_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_write_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRAC_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRACFP_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_FP_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP(mask)) >> SERCOM_USART_BAUD_FRAC_FP_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_FP_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP(mask)) >> SERCOM_USART_BAUD_FRACFP_FP_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_FRAC_FP_Msk; + tmp |= SERCOM_USART_BAUD_FRAC_FP(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_write_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_FRACFP_FP_Msk; + tmp |= SERCOM_USART_BAUD_FRACFP_FP(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRAC_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRACFP_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRAC_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRACFP_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_FP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP_Msk) >> SERCOM_USART_BAUD_FRAC_FP_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_FP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP_Msk) >> SERCOM_USART_BAUD_FRACFP_FP_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_USARTFP_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_write_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_USARTFP_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_reg(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.BAUD.reg; +} + +static inline void hri_sercomusart_set_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg |= SERCOM_USART_RXPL_RXPL(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_RXPL_bf(const void *const hw, + hri_sercomusart_rxpl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp = (tmp & SERCOM_USART_RXPL_RXPL(mask)) >> SERCOM_USART_RXPL_RXPL_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t data) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp &= ~SERCOM_USART_RXPL_RXPL_Msk; + tmp |= SERCOM_USART_RXPL_RXPL(data); + ((Sercom *)hw)->USART.RXPL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg &= ~SERCOM_USART_RXPL_RXPL(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg ^= SERCOM_USART_RXPL_RXPL(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_RXPL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp = (tmp & SERCOM_USART_RXPL_RXPL_Msk) >> SERCOM_USART_RXPL_RXPL_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_reg(const void *const hw, + hri_sercomusart_rxpl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.RXPL.reg; +} + +static inline void hri_sercomi2cm_set_ADDR_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LENEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_ADDR_LENEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_LENEN) >> SERCOM_I2CM_ADDR_LENEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_LENEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_LENEN; + tmp |= value << SERCOM_I2CM_ADDR_LENEN_Pos; + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LENEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LENEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_ADDR_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_HS; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_ADDR_HS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_HS) >> SERCOM_I2CM_ADDR_HS_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_HS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_HS; + tmp |= value << SERCOM_I2CM_ADDR_HS_Pos; + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_HS; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_HS; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_TENBITEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_ADDR_TENBITEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_TENBITEN) >> SERCOM_I2CM_ADDR_TENBITEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_TENBITEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_TENBITEN; + tmp |= value << SERCOM_I2CM_ADDR_TENBITEN_Pos; + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_TENBITEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_TENBITEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_ADDR(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_ADDR_bf(const void *const hw, + hri_sercomi2cm_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_ADDR(mask)) >> SERCOM_I2CM_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_ADDR_Msk; + tmp |= SERCOM_I2CM_ADDR_ADDR(data); + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_ADDR(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_ADDR(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_ADDR_Msk) >> SERCOM_I2CM_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LEN(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_LEN_bf(const void *const hw, + hri_sercomi2cm_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_LEN(mask)) >> SERCOM_I2CM_ADDR_LEN_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_LEN_Msk; + tmp |= SERCOM_I2CM_ADDR_LEN(data); + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LEN(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LEN(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_LEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_LEN_Msk) >> SERCOM_I2CM_ADDR_LEN_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_reg(const void *const hw, + hri_sercomi2cm_addr_reg_t mask) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg = data; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return ((Sercom *)hw)->I2CM.ADDR.reg; +} + +static inline void hri_sercomi2cs_set_ADDR_GENCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_GENCEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_ADDR_GENCEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_GENCEN) >> SERCOM_I2CS_ADDR_GENCEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_GENCEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_GENCEN; + tmp |= value << SERCOM_I2CS_ADDR_GENCEN_Pos; + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_GENCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_GENCEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_GENCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_GENCEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_TENBITEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_ADDR_TENBITEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_TENBITEN) >> SERCOM_I2CS_ADDR_TENBITEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_TENBITEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_TENBITEN; + tmp |= value << SERCOM_I2CS_ADDR_TENBITEN_Pos; + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_TENBITEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_TENBITEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDR_bf(const void *const hw, + hri_sercomi2cs_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDR(mask)) >> SERCOM_I2CS_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_ADDR_Msk; + tmp |= SERCOM_I2CS_ADDR_ADDR(data); + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDR_Msk) >> SERCOM_I2CS_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDRMASK_bf(const void *const hw, + hri_sercomi2cs_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK(mask)) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_ADDRMASK_Msk; + tmp |= SERCOM_I2CS_ADDR_ADDRMASK(data); + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDRMASK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK_Msk) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_reg(const void *const hw, + hri_sercomi2cs_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.ADDR.reg; +} + +static inline void hri_sercomspi_set_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDR_bf(const void *const hw, + hri_sercomspi_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDR(mask)) >> SERCOM_SPI_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp &= ~SERCOM_SPI_ADDR_ADDR_Msk; + tmp |= SERCOM_SPI_ADDR_ADDR(data); + ((Sercom *)hw)->SPI.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDR_Msk) >> SERCOM_SPI_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDRMASK_bf(const void *const hw, + hri_sercomspi_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK(mask)) >> SERCOM_SPI_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp &= ~SERCOM_SPI_ADDR_ADDRMASK_Msk; + tmp |= SERCOM_SPI_ADDR_ADDRMASK(data); + ((Sercom *)hw)->SPI.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDRMASK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK_Msk) >> SERCOM_SPI_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.ADDR.reg; +} + +static inline void hri_sercomi2cm_set_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg |= SERCOM_I2CM_DATA_DATA(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_get_DATA_DATA_bf(const void *const hw, + hri_sercomi2cm_data_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.DATA.reg; + tmp = (tmp & SERCOM_I2CM_DATA_DATA(mask)) >> SERCOM_I2CM_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t data) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.DATA.reg; + tmp &= ~SERCOM_I2CM_DATA_DATA_Msk; + tmp |= SERCOM_I2CM_DATA_DATA(data); + ((Sercom *)hw)->I2CM.DATA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg &= ~SERCOM_I2CM_DATA_DATA(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg ^= SERCOM_I2CM_DATA_DATA(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_DATA_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.DATA.reg; + tmp = (tmp & SERCOM_I2CM_DATA_DATA_Msk) >> SERCOM_I2CM_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg |= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_get_DATA_reg(const void *const hw, + hri_sercomi2cm_data_reg_t mask) +{ + uint8_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg = data; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg &= ~mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg ^= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return ((Sercom *)hw)->I2CM.DATA.reg; +} + +static inline void hri_sercomi2cs_set_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg |= SERCOM_I2CS_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_get_DATA_DATA_bf(const void *const hw, + hri_sercomi2cs_data_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CS.DATA.reg; + tmp = (tmp & SERCOM_I2CS_DATA_DATA(mask)) >> SERCOM_I2CS_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t data) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.DATA.reg; + tmp &= ~SERCOM_I2CS_DATA_DATA_Msk; + tmp |= SERCOM_I2CS_DATA_DATA(data); + ((Sercom *)hw)->I2CS.DATA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg &= ~SERCOM_I2CS_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg ^= SERCOM_I2CS_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_DATA_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CS.DATA.reg; + tmp = (tmp & SERCOM_I2CS_DATA_DATA_Msk) >> SERCOM_I2CS_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_get_DATA_reg(const void *const hw, + hri_sercomi2cs_data_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CS.DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.DATA.reg; +} + +static inline void hri_sercomspi_set_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg |= SERCOM_SPI_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_data_reg_t hri_sercomspi_get_DATA_DATA_bf(const void *const hw, + hri_sercomspi_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.DATA.reg; + tmp = (tmp & SERCOM_SPI_DATA_DATA(mask)) >> SERCOM_SPI_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.DATA.reg; + tmp &= ~SERCOM_SPI_DATA_DATA_Msk; + tmp |= SERCOM_SPI_DATA_DATA(data); + ((Sercom *)hw)->SPI.DATA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg &= ~SERCOM_SPI_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg ^= SERCOM_SPI_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_data_reg_t hri_sercomspi_read_DATA_DATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.DATA.reg; + tmp = (tmp & SERCOM_SPI_DATA_DATA_Msk) >> SERCOM_SPI_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_data_reg_t hri_sercomspi_get_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_data_reg_t hri_sercomspi_read_DATA_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.DATA.reg; +} + +static inline void hri_sercomusart_set_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg |= SERCOM_USART_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_data_reg_t hri_sercomusart_get_DATA_DATA_bf(const void *const hw, + hri_sercomusart_data_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.DATA.reg; + tmp = (tmp & SERCOM_USART_DATA_DATA(mask)) >> SERCOM_USART_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.DATA.reg; + tmp &= ~SERCOM_USART_DATA_DATA_Msk; + tmp |= SERCOM_USART_DATA_DATA(data); + ((Sercom *)hw)->USART.DATA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg &= ~SERCOM_USART_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg ^= SERCOM_USART_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_DATA_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.DATA.reg; + tmp = (tmp & SERCOM_USART_DATA_DATA_Msk) >> SERCOM_USART_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_data_reg_t hri_sercomusart_get_DATA_reg(const void *const hw, + hri_sercomusart_data_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.DATA.reg; +} + +static inline void hri_sercomi2cm_set_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg |= SERCOM_I2CM_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; + tmp = (tmp & SERCOM_I2CM_DBGCTRL_DBGSTOP) >> SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; + tmp &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP; + tmp |= value << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos; + ((Sercom *)hw)->I2CM.DBGCTRL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg ^= SERCOM_I2CM_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_get_DBGCTRL_reg(const void *const hw, + hri_sercomi2cm_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_read_DBGCTRL_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.DBGCTRL.reg; +} + +static inline void hri_sercomspi_set_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg |= SERCOM_SPI_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; + tmp = (tmp & SERCOM_SPI_DBGCTRL_DBGSTOP) >> SERCOM_SPI_DBGCTRL_DBGSTOP_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; + tmp &= ~SERCOM_SPI_DBGCTRL_DBGSTOP; + tmp |= value << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos; + ((Sercom *)hw)->SPI.DBGCTRL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg &= ~SERCOM_SPI_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg ^= SERCOM_SPI_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_get_DBGCTRL_reg(const void *const hw, + hri_sercomspi_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_read_DBGCTRL_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.DBGCTRL.reg; +} + +static inline void hri_sercomusart_set_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg |= SERCOM_USART_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; + tmp = (tmp & SERCOM_USART_DBGCTRL_DBGSTOP) >> SERCOM_USART_DBGCTRL_DBGSTOP_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; + tmp &= ~SERCOM_USART_DBGCTRL_DBGSTOP; + tmp |= value << SERCOM_USART_DBGCTRL_DBGSTOP_Pos; + ((Sercom *)hw)->USART.DBGCTRL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg &= ~SERCOM_USART_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg ^= SERCOM_USART_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_get_DBGCTRL_reg(const void *const hw, + hri_sercomusart_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_read_DBGCTRL_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.DBGCTRL.reg; +} + +static inline bool hri_sercomi2cs_get_STATUS_BUSERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_BUSERR) >> SERCOM_I2CS_STATUS_BUSERR_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_COLL_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_COLL) >> SERCOM_I2CS_STATUS_COLL_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_COLL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_COLL; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_RXNACK_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_RXNACK) >> SERCOM_I2CS_STATUS_RXNACK_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_DIR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_DIR) >> SERCOM_I2CS_STATUS_DIR_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_DIR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_DIR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_SR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SR) >> SERCOM_I2CS_STATUS_SR_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_SR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_LOWTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_LOWTOUT) >> SERCOM_I2CS_STATUS_LOWTOUT_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_CLKHOLD_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_CLKHOLD) >> SERCOM_I2CS_STATUS_CLKHOLD_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_SEXTTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SEXTTOUT) >> SERCOM_I2CS_STATUS_SEXTTOUT_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_HS_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_HS) >> SERCOM_I2CS_STATUS_HS_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_HS; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_get_STATUS_reg(const void *const hw, + hri_sercomi2cs_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->I2CS.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_clear_STATUS_reg(const void *const hw, hri_sercomi2cs_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_read_STATUS_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.STATUS.reg; +} + +static inline bool hri_sercomspi_get_STATUS_BUFOVF_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.STATUS.reg & SERCOM_SPI_STATUS_BUFOVF) >> SERCOM_SPI_STATUS_BUFOVF_Pos; +} + +static inline void hri_sercomspi_clear_STATUS_BUFOVF_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.STATUS.reg = SERCOM_SPI_STATUS_BUFOVF; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_status_reg_t hri_sercomspi_get_STATUS_reg(const void *const hw, + hri_sercomspi_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->SPI.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_clear_STATUS_reg(const void *const hw, hri_sercomspi_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.STATUS.reg = mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_status_reg_t hri_sercomspi_read_STATUS_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.STATUS.reg; +} + +static inline bool hri_sercomusart_get_STATUS_PERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_PERR) >> SERCOM_USART_STATUS_PERR_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_PERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_PERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_FERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_FERR) >> SERCOM_USART_STATUS_FERR_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_FERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_FERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_BUFOVF_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_BUFOVF) >> SERCOM_USART_STATUS_BUFOVF_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_BUFOVF_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_BUFOVF; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_CTS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_CTS) >> SERCOM_USART_STATUS_CTS_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_CTS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_CTS; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_ISF_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_ISF) >> SERCOM_USART_STATUS_ISF_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_ISF_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_ISF; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_COLL_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_COLL) >> SERCOM_USART_STATUS_COLL_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_COLL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_COLL; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_status_reg_t hri_sercomusart_get_STATUS_reg(const void *const hw, + hri_sercomusart_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_clear_STATUS_reg(const void *const hw, hri_sercomusart_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_status_reg_t hri_sercomusart_read_STATUS_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.STATUS.reg; +} + +static inline void hri_sercomi2cm_set_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_BUSERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSERR) >> SERCOM_I2CM_STATUS_BUSERR_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_BUSERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_BUSERR; + tmp |= value << SERCOM_I2CM_STATUS_BUSERR_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_ARBLOST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_ARBLOST; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_ARBLOST_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) >> SERCOM_I2CM_STATUS_ARBLOST_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_ARBLOST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_ARBLOST; + tmp |= value << SERCOM_I2CM_STATUS_ARBLOST_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_ARBLOST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_ARBLOST; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_ARBLOST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_ARBLOST; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_RXNACK_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) >> SERCOM_I2CM_STATUS_RXNACK_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_RXNACK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_RXNACK; + tmp |= value << SERCOM_I2CM_STATUS_RXNACK_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_LOWTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LOWTOUT) >> SERCOM_I2CM_STATUS_LOWTOUT_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_LOWTOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_LOWTOUT; + tmp |= value << SERCOM_I2CM_STATUS_LOWTOUT_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_CLKHOLD_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_CLKHOLD) >> SERCOM_I2CM_STATUS_CLKHOLD_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_CLKHOLD_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_CLKHOLD; + tmp |= value << SERCOM_I2CM_STATUS_CLKHOLD_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_MEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_MEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_MEXTTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_MEXTTOUT) >> SERCOM_I2CM_STATUS_MEXTTOUT_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_MEXTTOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_MEXTTOUT; + tmp |= value << SERCOM_I2CM_STATUS_MEXTTOUT_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_MEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_MEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_MEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_MEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_SEXTTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_SEXTTOUT) >> SERCOM_I2CM_STATUS_SEXTTOUT_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_SEXTTOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_SEXTTOUT; + tmp |= value << SERCOM_I2CM_STATUS_SEXTTOUT_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_LENERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LENERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_LENERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LENERR) >> SERCOM_I2CM_STATUS_LENERR_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_LENERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_LENERR; + tmp |= value << SERCOM_I2CM_STATUS_LENERR_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_LENERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LENERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_LENERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LENERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_BUSSTATE_bf(const void *const hw, + hri_sercomi2cm_status_reg_t mask) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(mask)) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos; +} + +static inline void hri_sercomi2cm_set_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSSTATE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_BUSSTATE_bf(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE_Msk) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_BUSSTATE_Msk; + tmp |= SERCOM_I2CM_STATUS_BUSSTATE(data); + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSSTATE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSSTATE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_reg(const void *const hw, + hri_sercomi2cm_status_reg_t mask) +{ + uint16_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_set_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + ((Sercom *)hw)->I2CM.STATUS.reg |= mask; +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return ((Sercom *)hw)->I2CM.STATUS.reg; +} + +static inline void hri_sercomi2cm_write_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t data) +{ + ((Sercom *)hw)->I2CM.STATUS.reg = data; +} + +static inline void hri_sercomi2cm_toggle_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + ((Sercom *)hw)->I2CM.STATUS.reg ^= mask; +} + +static inline void hri_sercomi2cm_clear_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_sercomusart_set_BAUD_FRAC_reg(a, b) hri_sercomusart_set_BAUD_reg(a, b) +#define hri_sercomusart_get_BAUD_FRAC_reg(a, b) hri_sercomusart_get_BAUD_reg(a, b) +#define hri_sercomusart_write_BAUD_FRAC_reg(a, b) hri_sercomusart_write_BAUD_reg(a, b) +#define hri_sercomusart_clear_BAUD_FRAC_reg(a, b) hri_sercomusart_clear_BAUD_reg(a, b) +#define hri_sercomusart_toggle_BAUD_FRAC_reg(a, b) hri_sercomusart_toggle_BAUD_reg(a, b) +#define hri_sercomusart_read_BAUD_FRAC_reg(a) hri_sercomusart_read_BAUD_reg(a) +#define hri_sercomusart_set_BAUD_FRACFP_reg(a, b) hri_sercomusart_set_BAUD_reg(a, b) +#define hri_sercomusart_get_BAUD_FRACFP_reg(a, b) hri_sercomusart_get_BAUD_reg(a, b) +#define hri_sercomusart_write_BAUD_FRACFP_reg(a, b) hri_sercomusart_write_BAUD_reg(a, b) +#define hri_sercomusart_clear_BAUD_FRACFP_reg(a, b) hri_sercomusart_clear_BAUD_reg(a, b) +#define hri_sercomusart_toggle_BAUD_FRACFP_reg(a, b) hri_sercomusart_toggle_BAUD_reg(a, b) +#define hri_sercomusart_read_BAUD_FRACFP_reg(a) hri_sercomusart_read_BAUD_reg(a) +#define hri_sercomusart_set_BAUD_USARTFP_reg(a, b) hri_sercomusart_set_BAUD_reg(a, b) +#define hri_sercomusart_get_BAUD_USARTFP_reg(a, b) hri_sercomusart_get_BAUD_reg(a, b) +#define hri_sercomusart_write_BAUD_USARTFP_reg(a, b) hri_sercomusart_write_BAUD_reg(a, b) +#define hri_sercomusart_clear_BAUD_USARTFP_reg(a, b) hri_sercomusart_clear_BAUD_reg(a, b) +#define hri_sercomusart_toggle_BAUD_USARTFP_reg(a, b) hri_sercomusart_toggle_BAUD_reg(a, b) +#define hri_sercomusart_read_BAUD_USARTFP_reg(a) hri_sercomusart_read_BAUD_reg(a) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SERCOM_L21_H_INCLUDED */ +#endif /* _SAML21_SERCOM_COMPONENT_ */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_supc_l21.h b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_supc_l21.h new file mode 100644 index 00000000..5d569345 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_supc_l21.h @@ -0,0 +1,2492 @@ +/** + * \file + * + * \brief SAM SUPC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_SUPC_COMPONENT_ +#ifndef _HRI_SUPC_L21_H_INCLUDED_ +#define _HRI_SUPC_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SUPC_CRITICAL_SECTIONS) +#define SUPC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SUPC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SUPC_CRITICAL_SECTION_ENTER() +#define SUPC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_supc_bbps_reg_t; +typedef uint32_t hri_supc_bkin_reg_t; +typedef uint32_t hri_supc_bkout_reg_t; +typedef uint32_t hri_supc_bod12_reg_t; +typedef uint32_t hri_supc_bod33_reg_t; +typedef uint32_t hri_supc_intenset_reg_t; +typedef uint32_t hri_supc_intflag_reg_t; +typedef uint32_t hri_supc_status_reg_t; +typedef uint32_t hri_supc_vref_reg_t; +typedef uint32_t hri_supc_vreg_reg_t; + +static inline bool hri_supc_get_INTFLAG_BOD33RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33RDY) >> SUPC_INTFLAG_BOD33RDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_BOD33RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY; +} + +static inline bool hri_supc_get_INTFLAG_BOD33DET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33DET) >> SUPC_INTFLAG_BOD33DET_Pos; +} + +static inline void hri_supc_clear_INTFLAG_BOD33DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33DET; +} + +static inline bool hri_supc_get_INTFLAG_B33SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B33SRDY) >> SUPC_INTFLAG_B33SRDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_B33SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B33SRDY; +} + +static inline bool hri_supc_get_INTFLAG_BOD12RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12RDY) >> SUPC_INTFLAG_BOD12RDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_BOD12RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12RDY; +} + +static inline bool hri_supc_get_INTFLAG_BOD12DET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12DET) >> SUPC_INTFLAG_BOD12DET_Pos; +} + +static inline void hri_supc_clear_INTFLAG_BOD12DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12DET; +} + +static inline bool hri_supc_get_INTFLAG_B12SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B12SRDY) >> SUPC_INTFLAG_B12SRDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_B12SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B12SRDY; +} + +static inline bool hri_supc_get_INTFLAG_VREGRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VREGRDY) >> SUPC_INTFLAG_VREGRDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_VREGRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VREGRDY; +} + +static inline bool hri_supc_get_INTFLAG_APWSRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_APWSRDY) >> SUPC_INTFLAG_APWSRDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_APWSRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_APWSRDY; +} + +static inline bool hri_supc_get_INTFLAG_VCORERDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VCORERDY) >> SUPC_INTFLAG_VCORERDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_VCORERDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VCORERDY; +} + +static inline bool hri_supc_get_interrupt_BOD33RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33RDY) >> SUPC_INTFLAG_BOD33RDY_Pos; +} + +static inline void hri_supc_clear_interrupt_BOD33RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY; +} + +static inline bool hri_supc_get_interrupt_BOD33DET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33DET) >> SUPC_INTFLAG_BOD33DET_Pos; +} + +static inline void hri_supc_clear_interrupt_BOD33DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33DET; +} + +static inline bool hri_supc_get_interrupt_B33SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B33SRDY) >> SUPC_INTFLAG_B33SRDY_Pos; +} + +static inline void hri_supc_clear_interrupt_B33SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B33SRDY; +} + +static inline bool hri_supc_get_interrupt_BOD12RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12RDY) >> SUPC_INTFLAG_BOD12RDY_Pos; +} + +static inline void hri_supc_clear_interrupt_BOD12RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12RDY; +} + +static inline bool hri_supc_get_interrupt_BOD12DET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12DET) >> SUPC_INTFLAG_BOD12DET_Pos; +} + +static inline void hri_supc_clear_interrupt_BOD12DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12DET; +} + +static inline bool hri_supc_get_interrupt_B12SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B12SRDY) >> SUPC_INTFLAG_B12SRDY_Pos; +} + +static inline void hri_supc_clear_interrupt_B12SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B12SRDY; +} + +static inline bool hri_supc_get_interrupt_VREGRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VREGRDY) >> SUPC_INTFLAG_VREGRDY_Pos; +} + +static inline void hri_supc_clear_interrupt_VREGRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VREGRDY; +} + +static inline bool hri_supc_get_interrupt_APWSRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_APWSRDY) >> SUPC_INTFLAG_APWSRDY_Pos; +} + +static inline void hri_supc_clear_interrupt_APWSRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_APWSRDY; +} + +static inline bool hri_supc_get_interrupt_VCORERDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VCORERDY) >> SUPC_INTFLAG_VCORERDY_Pos; +} + +static inline void hri_supc_clear_interrupt_VCORERDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VCORERDY; +} + +static inline hri_supc_intflag_reg_t hri_supc_get_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_supc_intflag_reg_t hri_supc_read_INTFLAG_reg(const void *const hw) +{ + return ((Supc *)hw)->INTFLAG.reg; +} + +static inline void hri_supc_clear_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask) +{ + ((Supc *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_supc_set_INTEN_BOD33RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY; +} + +static inline bool hri_supc_get_INTEN_BOD33RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33RDY) >> SUPC_INTENSET_BOD33RDY_Pos; +} + +static inline void hri_supc_write_INTEN_BOD33RDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY; + } +} + +static inline void hri_supc_clear_INTEN_BOD33RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY; +} + +static inline void hri_supc_set_INTEN_BOD33DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET; +} + +static inline bool hri_supc_get_INTEN_BOD33DET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33DET) >> SUPC_INTENSET_BOD33DET_Pos; +} + +static inline void hri_supc_write_INTEN_BOD33DET_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET; + } +} + +static inline void hri_supc_clear_INTEN_BOD33DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET; +} + +static inline void hri_supc_set_INTEN_B33SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B33SRDY; +} + +static inline bool hri_supc_get_INTEN_B33SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_B33SRDY) >> SUPC_INTENSET_B33SRDY_Pos; +} + +static inline void hri_supc_write_INTEN_B33SRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B33SRDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B33SRDY; + } +} + +static inline void hri_supc_clear_INTEN_B33SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B33SRDY; +} + +static inline void hri_supc_set_INTEN_BOD12RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12RDY; +} + +static inline bool hri_supc_get_INTEN_BOD12RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD12RDY) >> SUPC_INTENSET_BOD12RDY_Pos; +} + +static inline void hri_supc_write_INTEN_BOD12RDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12RDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12RDY; + } +} + +static inline void hri_supc_clear_INTEN_BOD12RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12RDY; +} + +static inline void hri_supc_set_INTEN_BOD12DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12DET; +} + +static inline bool hri_supc_get_INTEN_BOD12DET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD12DET) >> SUPC_INTENSET_BOD12DET_Pos; +} + +static inline void hri_supc_write_INTEN_BOD12DET_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12DET; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12DET; + } +} + +static inline void hri_supc_clear_INTEN_BOD12DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12DET; +} + +static inline void hri_supc_set_INTEN_B12SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B12SRDY; +} + +static inline bool hri_supc_get_INTEN_B12SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_B12SRDY) >> SUPC_INTENSET_B12SRDY_Pos; +} + +static inline void hri_supc_write_INTEN_B12SRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B12SRDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B12SRDY; + } +} + +static inline void hri_supc_clear_INTEN_B12SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B12SRDY; +} + +static inline void hri_supc_set_INTEN_VREGRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VREGRDY; +} + +static inline bool hri_supc_get_INTEN_VREGRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_VREGRDY) >> SUPC_INTENSET_VREGRDY_Pos; +} + +static inline void hri_supc_write_INTEN_VREGRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VREGRDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VREGRDY; + } +} + +static inline void hri_supc_clear_INTEN_VREGRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VREGRDY; +} + +static inline void hri_supc_set_INTEN_APWSRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_APWSRDY; +} + +static inline bool hri_supc_get_INTEN_APWSRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_APWSRDY) >> SUPC_INTENSET_APWSRDY_Pos; +} + +static inline void hri_supc_write_INTEN_APWSRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_APWSRDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_APWSRDY; + } +} + +static inline void hri_supc_clear_INTEN_APWSRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_APWSRDY; +} + +static inline void hri_supc_set_INTEN_VCORERDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VCORERDY; +} + +static inline bool hri_supc_get_INTEN_VCORERDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_VCORERDY) >> SUPC_INTENSET_VCORERDY_Pos; +} + +static inline void hri_supc_write_INTEN_VCORERDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VCORERDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VCORERDY; + } +} + +static inline void hri_supc_clear_INTEN_VCORERDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VCORERDY; +} + +static inline void hri_supc_set_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) +{ + ((Supc *)hw)->INTENSET.reg = mask; +} + +static inline hri_supc_intenset_reg_t hri_supc_get_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_supc_intenset_reg_t hri_supc_read_INTEN_reg(const void *const hw) +{ + return ((Supc *)hw)->INTENSET.reg; +} + +static inline void hri_supc_write_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t data) +{ + ((Supc *)hw)->INTENSET.reg = data; + ((Supc *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_supc_clear_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) +{ + ((Supc *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_supc_get_STATUS_BOD33RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD33RDY) >> SUPC_STATUS_BOD33RDY_Pos; +} + +static inline bool hri_supc_get_STATUS_BOD33DET_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD33DET) >> SUPC_STATUS_BOD33DET_Pos; +} + +static inline bool hri_supc_get_STATUS_B33SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_B33SRDY) >> SUPC_STATUS_B33SRDY_Pos; +} + +static inline bool hri_supc_get_STATUS_BOD12RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD12RDY) >> SUPC_STATUS_BOD12RDY_Pos; +} + +static inline bool hri_supc_get_STATUS_BOD12DET_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD12DET) >> SUPC_STATUS_BOD12DET_Pos; +} + +static inline bool hri_supc_get_STATUS_B12SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_B12SRDY) >> SUPC_STATUS_B12SRDY_Pos; +} + +static inline bool hri_supc_get_STATUS_VREGRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_VREGRDY) >> SUPC_STATUS_VREGRDY_Pos; +} + +static inline bool hri_supc_get_STATUS_APWSRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_APWSRDY) >> SUPC_STATUS_APWSRDY_Pos; +} + +static inline bool hri_supc_get_STATUS_VCORERDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_VCORERDY) >> SUPC_STATUS_VCORERDY_Pos; +} + +static inline bool hri_supc_get_STATUS_BBPS_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BBPS) >> SUPC_STATUS_BBPS_Pos; +} + +static inline hri_supc_status_reg_t hri_supc_get_STATUS_reg(const void *const hw, hri_supc_status_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_supc_status_reg_t hri_supc_read_STATUS_reg(const void *const hw) +{ + return ((Supc *)hw)->STATUS.reg; +} + +static inline hri_supc_bkin_reg_t hri_supc_get_BKIN_BKIN_bf(const void *const hw, hri_supc_bkin_reg_t mask) +{ + return (((Supc *)hw)->BKIN.reg & SUPC_BKIN_BKIN(mask)) >> SUPC_BKIN_BKIN_Pos; +} + +static inline hri_supc_bkin_reg_t hri_supc_read_BKIN_BKIN_bf(const void *const hw) +{ + return (((Supc *)hw)->BKIN.reg & SUPC_BKIN_BKIN_Msk) >> SUPC_BKIN_BKIN_Pos; +} + +static inline hri_supc_bkin_reg_t hri_supc_get_BKIN_reg(const void *const hw, hri_supc_bkin_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKIN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_supc_bkin_reg_t hri_supc_read_BKIN_reg(const void *const hw) +{ + return ((Supc *)hw)->BKIN.reg; +} + +static inline void hri_supc_set_BOD33_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_ENABLE) >> SUPC_BOD33_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_ENABLE; + tmp |= value << SUPC_BOD33_ENABLE_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_HYST_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_HYST; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_HYST_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_HYST) >> SUPC_BOD33_HYST_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_HYST_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_HYST; + tmp |= value << SUPC_BOD33_HYST_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_HYST_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_HYST; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_HYST_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_HYST; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_STDBYCFG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_STDBYCFG) >> SUPC_BOD33_STDBYCFG_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_STDBYCFG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_STDBYCFG; + tmp |= value << SUPC_BOD33_STDBYCFG_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_RUNSTDBY) >> SUPC_BOD33_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_RUNSTDBY; + tmp |= value << SUPC_BOD33_RUNSTDBY_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_RUNBKUP_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNBKUP; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_RUNBKUP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_RUNBKUP) >> SUPC_BOD33_RUNBKUP_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_RUNBKUP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_RUNBKUP; + tmp |= value << SUPC_BOD33_RUNBKUP_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_RUNBKUP_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNBKUP; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_RUNBKUP_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNBKUP; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_ACTCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ACTCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_ACTCFG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_ACTCFG) >> SUPC_BOD33_ACTCFG_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_ACTCFG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_ACTCFG; + tmp |= value << SUPC_BOD33_ACTCFG_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_ACTCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ACTCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_ACTCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ACTCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_VMON_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_VMON; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_VMON_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_VMON) >> SUPC_BOD33_VMON_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_VMON_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_VMON; + tmp |= value << SUPC_BOD33_VMON_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_VMON_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_VMON; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_VMON_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_VMON; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_ACTION(mask)) >> SUPC_BOD33_ACTION_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_ACTION_Msk; + tmp |= SUPC_BOD33_ACTION(data); + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_ACTION_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_ACTION_Msk) >> SUPC_BOD33_ACTION_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_PSEL(mask)) >> SUPC_BOD33_PSEL_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_PSEL_Msk; + tmp |= SUPC_BOD33_PSEL(data); + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_PSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_PSEL_Msk) >> SUPC_BOD33_PSEL_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_LEVEL(mask)) >> SUPC_BOD33_LEVEL_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_LEVEL_Msk; + tmp |= SUPC_BOD33_LEVEL(data); + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_LEVEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_LEVEL_Msk) >> SUPC_BOD33_LEVEL_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD33_BKUPLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_BKUPLEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_BKUPLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_BKUPLEVEL(mask)) >> SUPC_BOD33_BKUPLEVEL_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD33_BKUPLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_BKUPLEVEL_Msk; + tmp |= SUPC_BOD33_BKUPLEVEL(data); + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_BKUPLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_BKUPLEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_BKUPLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_BKUPLEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_BKUPLEVEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_BKUPLEVEL_Msk) >> SUPC_BOD33_BKUPLEVEL_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_reg(const void *const hw) +{ + return ((Supc *)hw)->BOD33.reg; +} + +static inline void hri_supc_set_BOD12_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD12_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_ENABLE) >> SUPC_BOD12_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD12_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD12.reg; + tmp &= ~SUPC_BOD12_ENABLE; + tmp |= value << SUPC_BOD12_ENABLE_Pos; + ((Supc *)hw)->BOD12.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD12_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD12_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD12_HYST_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_HYST; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD12_HYST_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_HYST) >> SUPC_BOD12_HYST_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD12_HYST_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD12.reg; + tmp &= ~SUPC_BOD12_HYST; + tmp |= value << SUPC_BOD12_HYST_Pos; + ((Supc *)hw)->BOD12.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD12_HYST_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_HYST; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD12_HYST_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_HYST; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD12_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD12_STDBYCFG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_STDBYCFG) >> SUPC_BOD12_STDBYCFG_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD12_STDBYCFG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD12.reg; + tmp &= ~SUPC_BOD12_STDBYCFG; + tmp |= value << SUPC_BOD12_STDBYCFG_Pos; + ((Supc *)hw)->BOD12.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD12_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD12_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD12_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD12_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_RUNSTDBY) >> SUPC_BOD12_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD12_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD12.reg; + tmp &= ~SUPC_BOD12_RUNSTDBY; + tmp |= value << SUPC_BOD12_RUNSTDBY_Pos; + ((Supc *)hw)->BOD12.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD12_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD12_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD12_ACTCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_ACTCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD12_ACTCFG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_ACTCFG) >> SUPC_BOD12_ACTCFG_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD12_ACTCFG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD12.reg; + tmp &= ~SUPC_BOD12_ACTCFG; + tmp |= value << SUPC_BOD12_ACTCFG_Pos; + ((Supc *)hw)->BOD12.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD12_ACTCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_ACTCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD12_ACTCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_ACTCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_ACTION(mask)) >> SUPC_BOD12_ACTION_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD12.reg; + tmp &= ~SUPC_BOD12_ACTION_Msk; + tmp |= SUPC_BOD12_ACTION(data); + ((Supc *)hw)->BOD12.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_ACTION_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_ACTION_Msk) >> SUPC_BOD12_ACTION_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_PSEL(mask)) >> SUPC_BOD12_PSEL_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD12.reg; + tmp &= ~SUPC_BOD12_PSEL_Msk; + tmp |= SUPC_BOD12_PSEL(data); + ((Supc *)hw)->BOD12.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_PSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_PSEL_Msk) >> SUPC_BOD12_PSEL_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_LEVEL(mask)) >> SUPC_BOD12_LEVEL_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD12.reg; + tmp &= ~SUPC_BOD12_LEVEL_Msk; + tmp |= SUPC_BOD12_LEVEL(data); + ((Supc *)hw)->BOD12.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_LEVEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_LEVEL_Msk) >> SUPC_BOD12_LEVEL_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_reg(const void *const hw) +{ + return ((Supc *)hw)->BOD12.reg; +} + +static inline void hri_supc_set_VREG_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREG_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_ENABLE) >> SUPC_VREG_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREG_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_ENABLE; + tmp |= value << SUPC_VREG_ENABLE_Pos; + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREG_STDBYPL0_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_STDBYPL0; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREG_STDBYPL0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_STDBYPL0) >> SUPC_VREG_STDBYPL0_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREG_STDBYPL0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_STDBYPL0; + tmp |= value << SUPC_VREG_STDBYPL0_Pos; + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_STDBYPL0_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_STDBYPL0; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_STDBYPL0_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_STDBYPL0; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREG_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREG_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_RUNSTDBY) >> SUPC_VREG_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREG_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_RUNSTDBY; + tmp |= value << SUPC_VREG_RUNSTDBY_Pos; + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREG_LPEFF_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_LPEFF; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREG_LPEFF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_LPEFF) >> SUPC_VREG_LPEFF_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREG_LPEFF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_LPEFF; + tmp |= value << SUPC_VREG_LPEFF_Pos; + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_LPEFF_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_LPEFF; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_LPEFF_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_LPEFF; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREG_SEL_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_SEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_get_VREG_SEL_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_SEL(mask)) >> SUPC_VREG_SEL_Pos; + return tmp; +} + +static inline void hri_supc_write_VREG_SEL_bf(const void *const hw, hri_supc_vreg_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_SEL_Msk; + tmp |= SUPC_VREG_SEL(data); + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_SEL_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_SEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_SEL_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_SEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_read_VREG_SEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_SEL_Msk) >> SUPC_VREG_SEL_Pos; + return tmp; +} + +static inline void hri_supc_set_VREG_VSVSTEP_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_VSVSTEP(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_get_VREG_VSVSTEP_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_VSVSTEP(mask)) >> SUPC_VREG_VSVSTEP_Pos; + return tmp; +} + +static inline void hri_supc_write_VREG_VSVSTEP_bf(const void *const hw, hri_supc_vreg_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_VSVSTEP_Msk; + tmp |= SUPC_VREG_VSVSTEP(data); + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_VSVSTEP_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_VSVSTEP(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_VSVSTEP_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_VSVSTEP(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_read_VREG_VSVSTEP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_VSVSTEP_Msk) >> SUPC_VREG_VSVSTEP_Pos; + return tmp; +} + +static inline void hri_supc_set_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_VSPER(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_get_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_VSPER(mask)) >> SUPC_VREG_VSPER_Pos; + return tmp; +} + +static inline void hri_supc_write_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_VSPER_Msk; + tmp |= SUPC_VREG_VSPER(data); + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_VSPER(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_VSPER(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_read_VREG_VSPER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_VSPER_Msk) >> SUPC_VREG_VSPER_Pos; + return tmp; +} + +static inline void hri_supc_set_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_get_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_VREG_reg(const void *const hw, hri_supc_vreg_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_read_VREG_reg(const void *const hw) +{ + return ((Supc *)hw)->VREG.reg; +} + +static inline void hri_supc_set_VREF_TSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_TSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_TSEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_TSEN) >> SUPC_VREF_TSEN_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_TSEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_TSEN; + tmp |= value << SUPC_VREF_TSEN_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_TSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_TSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_TSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_TSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_VREFOE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_VREFOE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_VREFOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_VREFOE) >> SUPC_VREF_VREFOE_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_VREFOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_VREFOE; + tmp |= value << SUPC_VREF_VREFOE_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_VREFOE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_VREFOE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_VREFOE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_VREFOE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_RUNSTDBY) >> SUPC_VREF_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_RUNSTDBY; + tmp |= value << SUPC_VREF_RUNSTDBY_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_ONDEMAND_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_ONDEMAND; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_ONDEMAND_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_ONDEMAND) >> SUPC_VREF_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_ONDEMAND_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_ONDEMAND; + tmp |= value << SUPC_VREF_ONDEMAND_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_ONDEMAND_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_ONDEMAND; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_ONDEMAND_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_ONDEMAND; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_SEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vref_reg_t hri_supc_get_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_SEL(mask)) >> SUPC_VREF_SEL_Pos; + return tmp; +} + +static inline void hri_supc_write_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_SEL_Msk; + tmp |= SUPC_VREF_SEL(data); + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_SEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_SEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vref_reg_t hri_supc_read_VREF_SEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_SEL_Msk) >> SUPC_VREF_SEL_Pos; + return tmp; +} + +static inline void hri_supc_set_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vref_reg_t hri_supc_get_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_VREF_reg(const void *const hw, hri_supc_vref_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vref_reg_t hri_supc_read_VREF_reg(const void *const hw) +{ + return ((Supc *)hw)->VREF.reg; +} + +static inline void hri_supc_set_BBPS_WAKEEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg |= SUPC_BBPS_WAKEEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BBPS_WAKEEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BBPS.reg; + tmp = (tmp & SUPC_BBPS_WAKEEN) >> SUPC_BBPS_WAKEEN_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BBPS_WAKEEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BBPS.reg; + tmp &= ~SUPC_BBPS_WAKEEN; + tmp |= value << SUPC_BBPS_WAKEEN_Pos; + ((Supc *)hw)->BBPS.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BBPS_WAKEEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_WAKEEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BBPS_WAKEEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_WAKEEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BBPS_PSOKEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg |= SUPC_BBPS_PSOKEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BBPS_PSOKEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BBPS.reg; + tmp = (tmp & SUPC_BBPS_PSOKEN) >> SUPC_BBPS_PSOKEN_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BBPS_PSOKEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BBPS.reg; + tmp &= ~SUPC_BBPS_PSOKEN; + tmp |= value << SUPC_BBPS_PSOKEN_Pos; + ((Supc *)hw)->BBPS.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BBPS_PSOKEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_PSOKEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BBPS_PSOKEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_PSOKEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BBPS_CONF_bf(const void *const hw, hri_supc_bbps_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg |= SUPC_BBPS_CONF(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bbps_reg_t hri_supc_get_BBPS_CONF_bf(const void *const hw, hri_supc_bbps_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BBPS.reg; + tmp = (tmp & SUPC_BBPS_CONF(mask)) >> SUPC_BBPS_CONF_Pos; + return tmp; +} + +static inline void hri_supc_write_BBPS_CONF_bf(const void *const hw, hri_supc_bbps_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BBPS.reg; + tmp &= ~SUPC_BBPS_CONF_Msk; + tmp |= SUPC_BBPS_CONF(data); + ((Supc *)hw)->BBPS.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BBPS_CONF_bf(const void *const hw, hri_supc_bbps_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_CONF(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BBPS_CONF_bf(const void *const hw, hri_supc_bbps_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_CONF(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bbps_reg_t hri_supc_read_BBPS_CONF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BBPS.reg; + tmp = (tmp & SUPC_BBPS_CONF_Msk) >> SUPC_BBPS_CONF_Pos; + return tmp; +} + +static inline void hri_supc_set_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bbps_reg_t hri_supc_get_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BBPS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bbps_reg_t hri_supc_read_BBPS_reg(const void *const hw) +{ + return ((Supc *)hw)->BBPS.reg; +} + +static inline void hri_supc_set_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_EN(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_EN(mask)) >> SUPC_BKOUT_EN_Pos; + return tmp; +} + +static inline void hri_supc_write_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BKOUT.reg; + tmp &= ~SUPC_BKOUT_EN_Msk; + tmp |= SUPC_BKOUT_EN(data); + ((Supc *)hw)->BKOUT.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_EN(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_EN(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_EN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_EN_Msk) >> SUPC_BKOUT_EN_Pos; + return tmp; +} + +static inline void hri_supc_set_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_CLR(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_CLR(mask)) >> SUPC_BKOUT_CLR_Pos; + return tmp; +} + +static inline void hri_supc_write_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BKOUT.reg; + tmp &= ~SUPC_BKOUT_CLR_Msk; + tmp |= SUPC_BKOUT_CLR(data); + ((Supc *)hw)->BKOUT.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_CLR(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_CLR(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_CLR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_CLR_Msk) >> SUPC_BKOUT_CLR_Pos; + return tmp; +} + +static inline void hri_supc_set_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_SET(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_SET(mask)) >> SUPC_BKOUT_SET_Pos; + return tmp; +} + +static inline void hri_supc_write_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BKOUT.reg; + tmp &= ~SUPC_BKOUT_SET_Msk; + tmp |= SUPC_BKOUT_SET(data); + ((Supc *)hw)->BKOUT.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_SET(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_SET(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_SET_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_SET_Msk) >> SUPC_BKOUT_SET_Pos; + return tmp; +} + +static inline void hri_supc_set_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_RTCTGL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_RTCTGL(mask)) >> SUPC_BKOUT_RTCTGL_Pos; + return tmp; +} + +static inline void hri_supc_write_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BKOUT.reg; + tmp &= ~SUPC_BKOUT_RTCTGL_Msk; + tmp |= SUPC_BKOUT_RTCTGL(data); + ((Supc *)hw)->BKOUT.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_RTCTGL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_RTCTGL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_RTCTGL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_RTCTGL_Msk) >> SUPC_BKOUT_RTCTGL_Pos; + return tmp; +} + +static inline void hri_supc_set_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_reg(const void *const hw) +{ + return ((Supc *)hw)->BKOUT.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SUPC_L21_H_INCLUDED */ +#endif /* _SAML21_SUPC_COMPONENT_ */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_systemcontrol_l21.h b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_systemcontrol_l21.h new file mode 100644 index 00000000..619b62f0 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_systemcontrol_l21.h @@ -0,0 +1,498 @@ +/** + * \file + * + * \brief SAM SystemControl + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_SystemControl_COMPONENT_ +#ifndef _HRI_SystemControl_L21_H_INCLUDED_ +#define _HRI_SystemControl_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SystemControl_CRITICAL_SECTIONS) +#define SystemControl_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SystemControl_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SystemControl_CRITICAL_SECTION_ENTER() +#define SystemControl_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_systemcontrol_aircr_reg_t; +typedef uint32_t hri_systemcontrol_ccr_reg_t; +typedef uint32_t hri_systemcontrol_cpuid_reg_t; +typedef uint32_t hri_systemcontrol_dfsr_reg_t; +typedef uint32_t hri_systemcontrol_icsr_reg_t; +typedef uint32_t hri_systemcontrol_scr_reg_t; +typedef uint32_t hri_systemcontrol_shcsr_reg_t; +typedef uint32_t hri_systemcontrol_shpr2_reg_t; +typedef uint32_t hri_systemcontrol_shpr3_reg_t; +typedef uint32_t hri_systemcontrol_vtor_reg_t; + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_REVISION_bf(const void *const hw, + hri_systemcontrol_cpuid_reg_t mask) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_REVISION(mask)) >> 0; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_REVISION_bf(const void *const hw) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_REVISION_Msk) >> 0; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_PARTNO_bf(const void *const hw, + hri_systemcontrol_cpuid_reg_t mask) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_PARTNO(mask)) >> 4; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_PARTNO_bf(const void *const hw) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_PARTNO_Msk) >> 4; +} + +static inline hri_systemcontrol_cpuid_reg_t +hri_systemcontrol_get_CPUID_ARCHITECTURE_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_ARCHITECTURE(mask)) >> 16; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_ARCHITECTURE_bf(const void *const hw) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_ARCHITECTURE_Msk) >> 16; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_VARIANT_bf(const void *const hw, + hri_systemcontrol_cpuid_reg_t mask) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_VARIANT(mask)) >> 20; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_VARIANT_bf(const void *const hw) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_VARIANT_Msk) >> 20; +} + +static inline hri_systemcontrol_cpuid_reg_t +hri_systemcontrol_get_CPUID_IMPLEMENTER_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_IMPLEMENTER(mask)) >> 24; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_IMPLEMENTER_bf(const void *const hw) +{ + return (((Systemcontrol *)hw)->CPUID.reg & SystemControl_CPUID_IMPLEMENTER_Msk) >> 24; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_reg(const void *const hw, + hri_systemcontrol_cpuid_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->CPUID.reg; + tmp &= mask; + return tmp; +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->CPUID.reg; +} + +static inline bool hri_systemcontrol_get_CCR_UNALIGN_TRP_bit(const void *const hw) +{ + return (((Systemcontrol *)hw)->CCR.reg & SystemControl_CCR_UNALIGN_TRP) >> 3; +} + +static inline bool hri_systemcontrol_get_CCR_STKALIGN_bit(const void *const hw) +{ + return (((Systemcontrol *)hw)->CCR.reg & SystemControl_CCR_STKALIGN) >> 9; +} + +static inline hri_systemcontrol_ccr_reg_t hri_systemcontrol_get_CCR_reg(const void *const hw, + hri_systemcontrol_ccr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->CCR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_systemcontrol_ccr_reg_t hri_systemcontrol_read_CCR_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->CCR.reg; +} + +static inline void hri_systemcontrol_set_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->ICSR.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_icsr_reg_t hri_systemcontrol_get_ICSR_reg(const void *const hw, + hri_systemcontrol_icsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->ICSR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->ICSR.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->ICSR.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->ICSR.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_icsr_reg_t hri_systemcontrol_read_ICSR_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->ICSR.reg; +} + +static inline void hri_systemcontrol_set_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->VTOR.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_vtor_reg_t hri_systemcontrol_get_VTOR_reg(const void *const hw, + hri_systemcontrol_vtor_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->VTOR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->VTOR.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->VTOR.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->VTOR.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_vtor_reg_t hri_systemcontrol_read_VTOR_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->VTOR.reg; +} + +static inline void hri_systemcontrol_set_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->AIRCR.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_aircr_reg_t hri_systemcontrol_get_AIRCR_reg(const void *const hw, + hri_systemcontrol_aircr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->AIRCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->AIRCR.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->AIRCR.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->AIRCR.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_aircr_reg_t hri_systemcontrol_read_AIRCR_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->AIRCR.reg; +} + +static inline void hri_systemcontrol_set_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SCR.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_scr_reg_t hri_systemcontrol_get_SCR_reg(const void *const hw, + hri_systemcontrol_scr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->SCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SCR.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SCR.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SCR.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_scr_reg_t hri_systemcontrol_read_SCR_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->SCR.reg; +} + +static inline void hri_systemcontrol_set_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR2.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_shpr2_reg_t hri_systemcontrol_get_SHPR2_reg(const void *const hw, + hri_systemcontrol_shpr2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->SHPR2.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR2.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR2.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR2.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_shpr2_reg_t hri_systemcontrol_read_SHPR2_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->SHPR2.reg; +} + +static inline void hri_systemcontrol_set_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR3.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_get_SHPR3_reg(const void *const hw, + hri_systemcontrol_shpr3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->SHPR3.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR3.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR3.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR3.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_read_SHPR3_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->SHPR3.reg; +} + +static inline void hri_systemcontrol_set_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHCSR.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_shcsr_reg_t hri_systemcontrol_get_SHCSR_reg(const void *const hw, + hri_systemcontrol_shcsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->SHCSR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHCSR.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHCSR.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_SHCSR_reg(const void *const hw, hri_systemcontrol_shcsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHCSR.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_shcsr_reg_t hri_systemcontrol_read_SHCSR_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->SHCSR.reg; +} + +static inline void hri_systemcontrol_set_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->DFSR.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_dfsr_reg_t hri_systemcontrol_get_DFSR_reg(const void *const hw, + hri_systemcontrol_dfsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->DFSR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->DFSR.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->DFSR.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_DFSR_reg(const void *const hw, hri_systemcontrol_dfsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->DFSR.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_dfsr_reg_t hri_systemcontrol_read_DFSR_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->DFSR.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SystemControl_L21_H_INCLUDED */ +#endif /* _SAML21_SystemControl_COMPONENT_ */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_systick_l21.h b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_systick_l21.h new file mode 100644 index 00000000..1dda6dc9 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_systick_l21.h @@ -0,0 +1,219 @@ +/** + * \file + * + * \brief SAM SysTick + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_SysTick_COMPONENT_ +#ifndef _HRI_SysTick_L21_H_INCLUDED_ +#define _HRI_SysTick_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SysTick_CRITICAL_SECTIONS) +#define SysTick_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SysTick_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SysTick_CRITICAL_SECTION_ENTER() +#define SysTick_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_systick_calib_reg_t; +typedef uint32_t hri_systick_csr_reg_t; +typedef uint32_t hri_systick_cvr_reg_t; +typedef uint32_t hri_systick_rvr_reg_t; + +static inline bool hri_systick_get_CALIB_SKEW_bit(const void *const hw) +{ + return (((Systick *)hw)->CALIB.reg & SysTick_CALIB_SKEW) >> 30; +} + +static inline bool hri_systick_get_CALIB_NOREF_bit(const void *const hw) +{ + return (((Systick *)hw)->CALIB.reg & SysTick_CALIB_NOREF) >> 31; +} + +static inline hri_systick_calib_reg_t hri_systick_get_CALIB_TENMS_bf(const void *const hw, hri_systick_calib_reg_t mask) +{ + return (((Systick *)hw)->CALIB.reg & SysTick_CALIB_TENMS(mask)) >> 0; +} + +static inline hri_systick_calib_reg_t hri_systick_read_CALIB_TENMS_bf(const void *const hw) +{ + return (((Systick *)hw)->CALIB.reg & SysTick_CALIB_TENMS_Msk) >> 0; +} + +static inline hri_systick_calib_reg_t hri_systick_get_CALIB_reg(const void *const hw, hri_systick_calib_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systick *)hw)->CALIB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_systick_calib_reg_t hri_systick_read_CALIB_reg(const void *const hw) +{ + return ((Systick *)hw)->CALIB.reg; +} + +static inline void hri_systick_set_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CSR.reg |= mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_csr_reg_t hri_systick_get_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systick *)hw)->CSR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systick_write_CSR_reg(const void *const hw, hri_systick_csr_reg_t data) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CSR.reg = data; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_clear_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CSR.reg &= ~mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_toggle_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CSR.reg ^= mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_csr_reg_t hri_systick_read_CSR_reg(const void *const hw) +{ + return ((Systick *)hw)->CSR.reg; +} + +static inline void hri_systick_set_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->RVR.reg |= mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_rvr_reg_t hri_systick_get_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systick *)hw)->RVR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systick_write_RVR_reg(const void *const hw, hri_systick_rvr_reg_t data) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->RVR.reg = data; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_clear_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->RVR.reg &= ~mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_toggle_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->RVR.reg ^= mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_rvr_reg_t hri_systick_read_RVR_reg(const void *const hw) +{ + return ((Systick *)hw)->RVR.reg; +} + +static inline void hri_systick_set_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CVR.reg |= mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_cvr_reg_t hri_systick_get_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systick *)hw)->CVR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systick_write_CVR_reg(const void *const hw, hri_systick_cvr_reg_t data) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CVR.reg = data; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_clear_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CVR.reg &= ~mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_toggle_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CVR.reg ^= mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_cvr_reg_t hri_systick_read_CVR_reg(const void *const hw) +{ + return ((Systick *)hw)->CVR.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SysTick_L21_H_INCLUDED */ +#endif /* _SAML21_SysTick_COMPONENT_ */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_tc_l21.h b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_tc_l21.h new file mode 100644 index 00000000..3d536905 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_tc_l21.h @@ -0,0 +1,2899 @@ +/** + * \file + * + * \brief SAM TC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_TC_COMPONENT_ +#ifndef _HRI_TC_L21_H_INCLUDED_ +#define _HRI_TC_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_TC_CRITICAL_SECTIONS) +#define TC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define TC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define TC_CRITICAL_SECTION_ENTER() +#define TC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_tc_evctrl_reg_t; +typedef uint16_t hri_tccount16_cc_reg_t; +typedef uint16_t hri_tccount16_ccbuf_reg_t; +typedef uint16_t hri_tccount16_count_reg_t; +typedef uint32_t hri_tc_ctrla_reg_t; +typedef uint32_t hri_tc_syncbusy_reg_t; +typedef uint32_t hri_tccount32_cc_reg_t; +typedef uint32_t hri_tccount32_ccbuf_reg_t; +typedef uint32_t hri_tccount32_count_reg_t; +typedef uint8_t hri_tc_ctrlbset_reg_t; +typedef uint8_t hri_tc_dbgctrl_reg_t; +typedef uint8_t hri_tc_drvctrl_reg_t; +typedef uint8_t hri_tc_intenset_reg_t; +typedef uint8_t hri_tc_intflag_reg_t; +typedef uint8_t hri_tc_status_reg_t; +typedef uint8_t hri_tc_wave_reg_t; +typedef uint8_t hri_tccount8_cc_reg_t; +typedef uint8_t hri_tccount8_ccbuf_reg_t; +typedef uint8_t hri_tccount8_count_reg_t; +typedef uint8_t hri_tccount8_per_reg_t; +typedef uint8_t hri_tccount8_perbuf_reg_t; + +static inline void hri_tc_wait_for_sync(const void *const hw, hri_tc_syncbusy_reg_t reg) +{ + while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_tc_is_syncing(const void *const hw, hri_tc_syncbusy_reg_t reg) +{ + return ((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg; +} + +static inline bool hri_tc_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos; +} + +static inline void hri_tc_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_OVF; +} + +static inline bool hri_tc_get_INTFLAG_ERR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos; +} + +static inline void hri_tc_clear_INTFLAG_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_ERR; +} + +static inline bool hri_tc_get_INTFLAG_MC0_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos; +} + +static inline void hri_tc_clear_INTFLAG_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC0; +} + +static inline bool hri_tc_get_INTFLAG_MC1_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos; +} + +static inline void hri_tc_clear_INTFLAG_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC1; +} + +static inline bool hri_tc_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos; +} + +static inline void hri_tc_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_OVF; +} + +static inline bool hri_tc_get_interrupt_ERR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos; +} + +static inline void hri_tc_clear_interrupt_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_ERR; +} + +static inline bool hri_tc_get_interrupt_MC0_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos; +} + +static inline void hri_tc_clear_interrupt_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC0; +} + +static inline bool hri_tc_get_interrupt_MC1_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos; +} + +static inline void hri_tc_clear_interrupt_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC1; +} + +static inline hri_tc_intflag_reg_t hri_tc_get_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_intflag_reg_t hri_tc_read_INTFLAG_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.INTFLAG.reg; +} + +static inline void hri_tc_clear_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = mask; +} + +static inline void hri_tc_set_CTRLB_DIR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_DIR; +} + +static inline bool hri_tc_get_CTRLB_DIR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_DIR) >> TC_CTRLBSET_DIR_Pos; +} + +static inline void hri_tc_write_CTRLB_DIR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_DIR; + } else { + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_DIR; + } +} + +static inline void hri_tc_clear_CTRLB_DIR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_DIR; +} + +static inline void hri_tc_set_CTRLB_LUPD_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_LUPD; +} + +static inline bool hri_tc_get_CTRLB_LUPD_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_LUPD) >> TC_CTRLBSET_LUPD_Pos; +} + +static inline void hri_tc_write_CTRLB_LUPD_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_LUPD; + } else { + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_LUPD; + } +} + +static inline void hri_tc_clear_CTRLB_LUPD_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_LUPD; +} + +static inline void hri_tc_set_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_ONESHOT; +} + +static inline bool hri_tc_get_CTRLB_ONESHOT_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_ONESHOT) >> TC_CTRLBSET_ONESHOT_Pos; +} + +static inline void hri_tc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT; + } else { + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_ONESHOT; + } +} + +static inline void hri_tc_clear_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT; +} + +static inline void hri_tc_set_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD(mask); +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg; + tmp = (tmp & TC_CTRLBSET_CMD(mask)) >> TC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_CMD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg; + tmp = (tmp & TC_CTRLBSET_CMD_Msk) >> TC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t data) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD(data); + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = ~TC_CTRLBSET_CMD(data); +} + +static inline void hri_tc_clear_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_CMD(mask); +} + +static inline void hri_tc_set_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = mask; +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.CTRLBSET.reg; +} + +static inline void hri_tc_write_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t data) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = data; + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = ~data; +} + +static inline void hri_tc_clear_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = mask; +} + +static inline void hri_tc_set_INTEN_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_OVF; +} + +static inline bool hri_tc_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_OVF) >> TC_INTENSET_OVF_Pos; +} + +static inline void hri_tc_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_OVF; + } else { + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_OVF; + } +} + +static inline void hri_tc_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_OVF; +} + +static inline void hri_tc_set_INTEN_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_ERR; +} + +static inline bool hri_tc_get_INTEN_ERR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_ERR) >> TC_INTENSET_ERR_Pos; +} + +static inline void hri_tc_write_INTEN_ERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_ERR; + } else { + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_ERR; + } +} + +static inline void hri_tc_clear_INTEN_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_ERR; +} + +static inline void hri_tc_set_INTEN_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC0; +} + +static inline bool hri_tc_get_INTEN_MC0_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_MC0) >> TC_INTENSET_MC0_Pos; +} + +static inline void hri_tc_write_INTEN_MC0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC0; + } else { + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC0; + } +} + +static inline void hri_tc_clear_INTEN_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC0; +} + +static inline void hri_tc_set_INTEN_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC1; +} + +static inline bool hri_tc_get_INTEN_MC1_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_MC1) >> TC_INTENSET_MC1_Pos; +} + +static inline void hri_tc_write_INTEN_MC1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC1; + } else { + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC1; + } +} + +static inline void hri_tc_clear_INTEN_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC1; +} + +static inline void hri_tc_set_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = mask; +} + +static inline hri_tc_intenset_reg_t hri_tc_get_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_intenset_reg_t hri_tc_read_INTEN_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.INTENSET.reg; +} + +static inline void hri_tc_write_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t data) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = data; + ((Tc *)hw)->COUNT16.INTENCLR.reg = ~data; +} + +static inline void hri_tc_clear_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = mask; +} + +static inline bool hri_tc_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_SWRST) >> TC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_ENABLE) >> TC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CTRLB) >> TC_SYNCBUSY_CTRLB_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_STATUS_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_STATUS) >> TC_SYNCBUSY_STATUS_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_COUNT) >> TC_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_PER_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_PER) >> TC_SYNCBUSY_PER_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_CC0_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CC0) >> TC_SYNCBUSY_CC0_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_CC1_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CC1) >> TC_SYNCBUSY_CC1_Pos; +} + +static inline hri_tc_syncbusy_reg_t hri_tc_get_SYNCBUSY_reg(const void *const hw, hri_tc_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_syncbusy_reg_t hri_tc_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.SYNCBUSY.reg; +} + +static inline void hri_tc_set_CTRLA_SWRST_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_SWRST; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_SWRST) >> TC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_tc_set_CTRLA_ENABLE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ENABLE; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_ENABLE) >> TC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_ENABLE; + tmp |= value << TC_CTRLA_ENABLE_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ENABLE; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ENABLE; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_RUNSTDBY; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_RUNSTDBY) >> TC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_RUNSTDBY; + tmp |= value << TC_CTRLA_RUNSTDBY_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_RUNSTDBY; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_RUNSTDBY; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_ONDEMAND_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ONDEMAND; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_ONDEMAND_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_ONDEMAND) >> TC_CTRLA_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_ONDEMAND_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_ONDEMAND; + tmp |= value << TC_CTRLA_ONDEMAND_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_ONDEMAND_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ONDEMAND; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_ONDEMAND_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ONDEMAND; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_ALOCK_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ALOCK; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_ALOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_ALOCK) >> TC_CTRLA_ALOCK_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_ALOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_ALOCK; + tmp |= value << TC_CTRLA_ALOCK_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_ALOCK_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ALOCK; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_ALOCK_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ALOCK; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_CAPTEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_CAPTEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_CAPTEN0) >> TC_CTRLA_CAPTEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_CAPTEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_CAPTEN0; + tmp |= value << TC_CTRLA_CAPTEN0_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_CAPTEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_CAPTEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_CAPTEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_CAPTEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_CAPTEN1) >> TC_CTRLA_CAPTEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_CAPTEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_CAPTEN1; + tmp |= value << TC_CTRLA_CAPTEN1_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_CAPTEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_CAPTEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_COPEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_COPEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_COPEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_COPEN0) >> TC_CTRLA_COPEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_COPEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_COPEN0; + tmp |= value << TC_CTRLA_COPEN0_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_COPEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_COPEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_COPEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_COPEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_COPEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_COPEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_COPEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_COPEN1) >> TC_CTRLA_COPEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_COPEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_COPEN1; + tmp |= value << TC_CTRLA_COPEN1_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_COPEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_COPEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_COPEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_COPEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_MODE(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_MODE(mask)) >> TC_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_MODE_Msk; + tmp |= TC_CTRLA_MODE(data); + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_MODE(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_MODE(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_MODE_Msk) >> TC_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_PRESCSYNC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCSYNC(mask)) >> TC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_PRESCSYNC_Msk; + tmp |= TC_CTRLA_PRESCSYNC(data); + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_PRESCSYNC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_PRESCSYNC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCSYNC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCSYNC_Msk) >> TC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_PRESCALER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCALER(mask)) >> TC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_PRESCALER_Msk; + tmp |= TC_CTRLA_PRESCALER(data); + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_PRESCALER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_PRESCALER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCALER_Msk) >> TC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + return ((Tc *)hw)->COUNT16.CTRLA.reg; +} + +static inline void hri_tc_set_EVCTRL_TCINV_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_TCINV; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_TCINV_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_TCINV) >> TC_EVCTRL_TCINV_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_TCINV_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_TCINV; + tmp |= value << TC_EVCTRL_TCINV_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_TCINV_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_TCINV; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_TCINV_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_TCINV; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_TCEI_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_TCEI; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_TCEI_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_TCEI) >> TC_EVCTRL_TCEI_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_TCEI_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_TCEI; + tmp |= value << TC_EVCTRL_TCEI_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_TCEI_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_TCEI; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_TCEI_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_TCEI; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_OVFEO; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_OVFEO) >> TC_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_OVFEO; + tmp |= value << TC_EVCTRL_OVFEO_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_OVFEO; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_OVFEO; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_MCEO0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_MCEO0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_MCEO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_MCEO0) >> TC_EVCTRL_MCEO0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_MCEO0; + tmp |= value << TC_EVCTRL_MCEO0_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_MCEO0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_MCEO0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_MCEO0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_MCEO0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_MCEO1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_MCEO1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_MCEO1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_MCEO1) >> TC_EVCTRL_MCEO1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_MCEO1; + tmp |= value << TC_EVCTRL_MCEO1_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_MCEO1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_MCEO1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_MCEO1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_MCEO1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_EVACT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_EVACT(mask)) >> TC_EVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_tc_write_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_EVACT_Msk; + tmp |= TC_EVCTRL_EVACT(data); + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_EVACT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_EVACT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_EVACT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_EVACT_Msk) >> TC_EVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_tc_set_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.EVCTRL.reg; +} + +static inline void hri_tc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg |= TC_WAVE_WAVEGEN(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wave_reg_t hri_tc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.WAVE.reg; + tmp = (tmp & TC_WAVE_WAVEGEN(mask)) >> TC_WAVE_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.WAVE.reg; + tmp &= ~TC_WAVE_WAVEGEN_Msk; + tmp |= TC_WAVE_WAVEGEN(data); + ((Tc *)hw)->COUNT16.WAVE.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg &= ~TC_WAVE_WAVEGEN(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg ^= TC_WAVE_WAVEGEN(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wave_reg_t hri_tc_read_WAVE_WAVEGEN_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.WAVE.reg; + tmp = (tmp & TC_WAVE_WAVEGEN_Msk) >> TC_WAVE_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tc_set_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wave_reg_t hri_tc_get_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.WAVE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_WAVE_reg(const void *const hw, hri_tc_wave_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wave_reg_t hri_tc_read_WAVE_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.WAVE.reg; +} + +static inline void hri_tc_set_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg |= TC_DRVCTRL_INVEN0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_DRVCTRL_INVEN0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp = (tmp & TC_DRVCTRL_INVEN0) >> TC_DRVCTRL_INVEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp &= ~TC_DRVCTRL_INVEN0; + tmp |= value << TC_DRVCTRL_INVEN0_Pos; + ((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= TC_DRVCTRL_INVEN0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg |= TC_DRVCTRL_INVEN1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_DRVCTRL_INVEN1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp = (tmp & TC_DRVCTRL_INVEN1) >> TC_DRVCTRL_INVEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp &= ~TC_DRVCTRL_INVEN1; + tmp |= value << TC_DRVCTRL_INVEN1_Pos; + ((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= TC_DRVCTRL_INVEN1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_drvctrl_reg_t hri_tc_get_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_drvctrl_reg_t hri_tc_read_DRVCTRL_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.DRVCTRL.reg; +} + +static inline void hri_tc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg |= TC_DBGCTRL_DBGRUN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg; + tmp = (tmp & TC_DBGCTRL_DBGRUN) >> TC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg; + tmp &= ~TC_DBGCTRL_DBGRUN; + tmp |= value << TC_DBGCTRL_DBGRUN_Pos; + ((Tc *)hw)->COUNT16.DBGCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg &= ~TC_DBGCTRL_DBGRUN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg ^= TC_DBGCTRL_DBGRUN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_dbgctrl_reg_t hri_tc_get_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_dbgctrl_reg_t hri_tc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.DBGCTRL.reg; +} + +static inline void hri_tccount8_set_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg |= TC_COUNT8_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_count_reg_t hri_tccount8_get_COUNT_COUNT_bf(const void *const hw, + hri_tccount8_count_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp = (tmp & TC_COUNT8_COUNT_COUNT(mask)) >> TC_COUNT8_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount8_write_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp &= ~TC_COUNT8_COUNT_COUNT_Msk; + tmp |= TC_COUNT8_COUNT_COUNT(data); + ((Tc *)hw)->COUNT8.COUNT.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg &= ~TC_COUNT8_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg ^= TC_COUNT8_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_count_reg_t hri_tccount8_read_COUNT_COUNT_bf(const void *const hw) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp = (tmp & TC_COUNT8_COUNT_COUNT_Msk) >> TC_COUNT8_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount8_set_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_count_reg_t hri_tccount8_get_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_count_reg_t hri_tccount8_read_COUNT_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + return ((Tc *)hw)->COUNT8.COUNT.reg; +} + +static inline void hri_tccount16_set_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg |= TC_COUNT16_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_count_reg_t hri_tccount16_get_COUNT_COUNT_bf(const void *const hw, + hri_tccount16_count_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp = (tmp & TC_COUNT16_COUNT_COUNT(mask)) >> TC_COUNT16_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount16_write_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp &= ~TC_COUNT16_COUNT_COUNT_Msk; + tmp |= TC_COUNT16_COUNT_COUNT(data); + ((Tc *)hw)->COUNT16.COUNT.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg &= ~TC_COUNT16_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg ^= TC_COUNT16_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_count_reg_t hri_tccount16_read_COUNT_COUNT_bf(const void *const hw) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp = (tmp & TC_COUNT16_COUNT_COUNT_Msk) >> TC_COUNT16_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount16_set_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_count_reg_t hri_tccount16_get_COUNT_reg(const void *const hw, + hri_tccount16_count_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount16_write_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_count_reg_t hri_tccount16_read_COUNT_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + return ((Tc *)hw)->COUNT16.COUNT.reg; +} + +static inline void hri_tccount32_set_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg |= TC_COUNT32_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_count_reg_t hri_tccount32_get_COUNT_COUNT_bf(const void *const hw, + hri_tccount32_count_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp = (tmp & TC_COUNT32_COUNT_COUNT(mask)) >> TC_COUNT32_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount32_write_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp &= ~TC_COUNT32_COUNT_COUNT_Msk; + tmp |= TC_COUNT32_COUNT_COUNT(data); + ((Tc *)hw)->COUNT32.COUNT.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg &= ~TC_COUNT32_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg ^= TC_COUNT32_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_count_reg_t hri_tccount32_read_COUNT_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp = (tmp & TC_COUNT32_COUNT_COUNT_Msk) >> TC_COUNT32_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount32_set_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_count_reg_t hri_tccount32_get_COUNT_reg(const void *const hw, + hri_tccount32_count_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount32_write_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_count_reg_t hri_tccount32_read_COUNT_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + return ((Tc *)hw)->COUNT32.COUNT.reg; +} + +static inline void hri_tccount8_set_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg |= TC_COUNT8_PER_PER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_per_reg_t hri_tccount8_get_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp = (tmp & TC_COUNT8_PER_PER(mask)) >> TC_COUNT8_PER_PER_Pos; + return tmp; +} + +static inline void hri_tccount8_write_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp &= ~TC_COUNT8_PER_PER_Msk; + tmp |= TC_COUNT8_PER_PER(data); + ((Tc *)hw)->COUNT8.PER.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg &= ~TC_COUNT8_PER_PER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg ^= TC_COUNT8_PER_PER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_per_reg_t hri_tccount8_read_PER_PER_bf(const void *const hw) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp = (tmp & TC_COUNT8_PER_PER_Msk) >> TC_COUNT8_PER_PER_Pos; + return tmp; +} + +static inline void hri_tccount8_set_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_per_reg_t hri_tccount8_get_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_PER_reg(const void *const hw, hri_tccount8_per_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_per_reg_t hri_tccount8_read_PER_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + return ((Tc *)hw)->COUNT8.PER.reg; +} + +static inline void hri_tccount8_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg |= TC_COUNT8_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_cc_reg_t hri_tccount8_get_CC_CC_bf(const void *const hw, uint8_t index, + hri_tccount8_cc_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp = (tmp & TC_COUNT8_CC_CC(mask)) >> TC_COUNT8_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount8_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp &= ~TC_COUNT8_CC_CC_Msk; + tmp |= TC_COUNT8_CC_CC(data); + ((Tc *)hw)->COUNT8.CC[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg &= ~TC_COUNT8_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg ^= TC_COUNT8_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_cc_reg_t hri_tccount8_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp = (tmp & TC_COUNT8_CC_CC_Msk) >> TC_COUNT8_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount8_set_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_cc_reg_t hri_tccount8_get_CC_reg(const void *const hw, uint8_t index, + hri_tccount8_cc_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_cc_reg_t hri_tccount8_read_CC_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + return ((Tc *)hw)->COUNT8.CC[index].reg; +} + +static inline void hri_tccount16_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg |= TC_COUNT16_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_cc_reg_t hri_tccount16_get_CC_CC_bf(const void *const hw, uint8_t index, + hri_tccount16_cc_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp = (tmp & TC_COUNT16_CC_CC(mask)) >> TC_COUNT16_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount16_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp &= ~TC_COUNT16_CC_CC_Msk; + tmp |= TC_COUNT16_CC_CC(data); + ((Tc *)hw)->COUNT16.CC[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg &= ~TC_COUNT16_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg ^= TC_COUNT16_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_cc_reg_t hri_tccount16_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp = (tmp & TC_COUNT16_CC_CC_Msk) >> TC_COUNT16_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount16_set_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_cc_reg_t hri_tccount16_get_CC_reg(const void *const hw, uint8_t index, + hri_tccount16_cc_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount16_write_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_cc_reg_t hri_tccount16_read_CC_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + return ((Tc *)hw)->COUNT16.CC[index].reg; +} + +static inline void hri_tccount32_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg |= TC_COUNT32_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_cc_reg_t hri_tccount32_get_CC_CC_bf(const void *const hw, uint8_t index, + hri_tccount32_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp = (tmp & TC_COUNT32_CC_CC(mask)) >> TC_COUNT32_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount32_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp &= ~TC_COUNT32_CC_CC_Msk; + tmp |= TC_COUNT32_CC_CC(data); + ((Tc *)hw)->COUNT32.CC[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg &= ~TC_COUNT32_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg ^= TC_COUNT32_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_cc_reg_t hri_tccount32_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp = (tmp & TC_COUNT32_CC_CC_Msk) >> TC_COUNT32_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount32_set_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_cc_reg_t hri_tccount32_get_CC_reg(const void *const hw, uint8_t index, + hri_tccount32_cc_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount32_write_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_cc_reg_t hri_tccount32_read_CC_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + return ((Tc *)hw)->COUNT32.CC[index].reg; +} + +static inline void hri_tccount8_set_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg |= TC_COUNT8_PERBUF_PERBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_perbuf_reg_t hri_tccount8_get_PERBUF_PERBUF_bf(const void *const hw, + hri_tccount8_perbuf_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; + tmp = (tmp & TC_COUNT8_PERBUF_PERBUF(mask)) >> TC_COUNT8_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tccount8_write_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; + tmp &= ~TC_COUNT8_PERBUF_PERBUF_Msk; + tmp |= TC_COUNT8_PERBUF_PERBUF(data); + ((Tc *)hw)->COUNT8.PERBUF.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg &= ~TC_COUNT8_PERBUF_PERBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg ^= TC_COUNT8_PERBUF_PERBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_perbuf_reg_t hri_tccount8_read_PERBUF_PERBUF_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; + tmp = (tmp & TC_COUNT8_PERBUF_PERBUF_Msk) >> TC_COUNT8_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tccount8_set_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_perbuf_reg_t hri_tccount8_get_PERBUF_reg(const void *const hw, + hri_tccount8_perbuf_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_perbuf_reg_t hri_tccount8_read_PERBUF_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT8.PERBUF.reg; +} + +static inline void hri_tccount8_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg |= TC_COUNT8_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_ccbuf_reg_t hri_tccount8_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount8_ccbuf_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; + tmp = (tmp & TC_COUNT8_CCBUF_CCBUF(mask)) >> TC_COUNT8_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount8_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; + tmp &= ~TC_COUNT8_CCBUF_CCBUF_Msk; + tmp |= TC_COUNT8_CCBUF_CCBUF(data); + ((Tc *)hw)->COUNT8.CCBUF[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg &= ~TC_COUNT8_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg ^= TC_COUNT8_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_ccbuf_reg_t hri_tccount8_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; + tmp = (tmp & TC_COUNT8_CCBUF_CCBUF_Msk) >> TC_COUNT8_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount8_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_ccbuf_reg_t hri_tccount8_get_CCBUF_reg(const void *const hw, uint8_t index, + hri_tccount8_ccbuf_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_ccbuf_reg_t hri_tccount8_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT8.CCBUF[index].reg; +} + +static inline void hri_tccount16_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg |= TC_COUNT16_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_ccbuf_reg_t hri_tccount16_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; + tmp = (tmp & TC_COUNT16_CCBUF_CCBUF(mask)) >> TC_COUNT16_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount16_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; + tmp &= ~TC_COUNT16_CCBUF_CCBUF_Msk; + tmp |= TC_COUNT16_CCBUF_CCBUF(data); + ((Tc *)hw)->COUNT16.CCBUF[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg &= ~TC_COUNT16_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg ^= TC_COUNT16_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_ccbuf_reg_t hri_tccount16_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; + tmp = (tmp & TC_COUNT16_CCBUF_CCBUF_Msk) >> TC_COUNT16_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount16_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_ccbuf_reg_t hri_tccount16_get_CCBUF_reg(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount16_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_ccbuf_reg_t hri_tccount16_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT16.CCBUF[index].reg; +} + +static inline void hri_tccount32_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg |= TC_COUNT32_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_ccbuf_reg_t hri_tccount32_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; + tmp = (tmp & TC_COUNT32_CCBUF_CCBUF(mask)) >> TC_COUNT32_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount32_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; + tmp &= ~TC_COUNT32_CCBUF_CCBUF_Msk; + tmp |= TC_COUNT32_CCBUF_CCBUF(data); + ((Tc *)hw)->COUNT32.CCBUF[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg &= ~TC_COUNT32_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg ^= TC_COUNT32_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_ccbuf_reg_t hri_tccount32_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; + tmp = (tmp & TC_COUNT32_CCBUF_CCBUF_Msk) >> TC_COUNT32_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount32_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_ccbuf_reg_t hri_tccount32_get_CCBUF_reg(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount32_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_ccbuf_reg_t hri_tccount32_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT32.CCBUF[index].reg; +} + +static inline bool hri_tc_get_STATUS_STOP_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_STOP) >> TC_STATUS_STOP_Pos; +} + +static inline void hri_tc_clear_STATUS_STOP_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_STOP; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_STATUS_SLAVE_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_SLAVE) >> TC_STATUS_SLAVE_Pos; +} + +static inline void hri_tc_clear_STATUS_SLAVE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_SLAVE; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_STATUS_PERBUFV_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_PERBUFV) >> TC_STATUS_PERBUFV_Pos; +} + +static inline void hri_tc_clear_STATUS_PERBUFV_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_PERBUFV; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_STATUS_CCBUFV0_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_CCBUFV0) >> TC_STATUS_CCBUFV0_Pos; +} + +static inline void hri_tc_clear_STATUS_CCBUFV0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_CCBUFV0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_STATUS_CCBUFV1_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_CCBUFV1) >> TC_STATUS_CCBUFV1_Pos; +} + +static inline void hri_tc_clear_STATUS_CCBUFV1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_CCBUFV1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_status_reg_t hri_tc_get_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT16.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_clear_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_status_reg_t hri_tc_read_STATUS_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT16.STATUS.reg; +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_tc_set_PER_PER_bf(a, b) hri_tccount8_set_PER_PER_bf(a, b) +#define hri_tc_get_PER_PER_bf(a, b) hri_tccount8_get_PER_PER_bf(a, b) +#define hri_tc_write_PER_PER_bf(a, b) hri_tccount8_write_PER_PER_bf(a, b) +#define hri_tc_clear_PER_PER_bf(a, b) hri_tccount8_clear_PER_PER_bf(a, b) +#define hri_tc_toggle_PER_PER_bf(a, b) hri_tccount8_toggle_PER_PER_bf(a, b) +#define hri_tc_read_PER_PER_bf(a) hri_tccount8_read_PER_PER_bf(a) +#define hri_tc_set_PER_reg(a, b) hri_tccount8_set_PER_reg(a, b) +#define hri_tc_get_PER_reg(a, b) hri_tccount8_get_PER_reg(a, b) +#define hri_tc_write_PER_reg(a, b) hri_tccount8_write_PER_reg(a, b) +#define hri_tc_clear_PER_reg(a, b) hri_tccount8_clear_PER_reg(a, b) +#define hri_tc_toggle_PER_reg(a, b) hri_tccount8_toggle_PER_reg(a, b) +#define hri_tc_read_PER_reg(a) hri_tccount8_read_PER_reg(a) +#define hri_tc_set_PERBUF_PERBUF_bf(a, b) hri_tccount8_set_PERBUF_PERBUF_bf(a, b) +#define hri_tc_get_PERBUF_PERBUF_bf(a, b) hri_tccount8_get_PERBUF_PERBUF_bf(a, b) +#define hri_tc_write_PERBUF_PERBUF_bf(a, b) hri_tccount8_write_PERBUF_PERBUF_bf(a, b) +#define hri_tc_clear_PERBUF_PERBUF_bf(a, b) hri_tccount8_clear_PERBUF_PERBUF_bf(a, b) +#define hri_tc_toggle_PERBUF_PERBUF_bf(a, b) hri_tccount8_toggle_PERBUF_PERBUF_bf(a, b) +#define hri_tc_read_PERBUF_PERBUF_bf(a) hri_tccount8_read_PERBUF_PERBUF_bf(a) +#define hri_tc_set_PERBUF_reg(a, b) hri_tccount8_set_PERBUF_reg(a, b) +#define hri_tc_get_PERBUF_reg(a, b) hri_tccount8_get_PERBUF_reg(a, b) +#define hri_tc_write_PERBUF_reg(a, b) hri_tccount8_write_PERBUF_reg(a, b) +#define hri_tc_clear_PERBUF_reg(a, b) hri_tccount8_clear_PERBUF_reg(a, b) +#define hri_tc_toggle_PERBUF_reg(a, b) hri_tccount8_toggle_PERBUF_reg(a, b) +#define hri_tc_read_PERBUF_reg(a) hri_tccount8_read_PERBUF_reg(a) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_TC_L21_H_INCLUDED */ +#endif /* _SAML21_TC_COMPONENT_ */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_tcc_l21.h b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_tcc_l21.h new file mode 100644 index 00000000..b0e61b84 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_tcc_l21.h @@ -0,0 +1,9462 @@ +/** + * \file + * + * \brief SAM TCC + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_TCC_COMPONENT_ +#ifndef _HRI_TCC_L21_H_INCLUDED_ +#define _HRI_TCC_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_TCC_CRITICAL_SECTIONS) +#define TCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define TCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define TCC_CRITICAL_SECTION_ENTER() +#define TCC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_tcc_patt_reg_t; +typedef uint16_t hri_tcc_pattbuf_reg_t; +typedef uint32_t hri_tcc_cc_reg_t; +typedef uint32_t hri_tcc_ccbuf_reg_t; +typedef uint32_t hri_tcc_count_reg_t; +typedef uint32_t hri_tcc_ctrla_reg_t; +typedef uint32_t hri_tcc_drvctrl_reg_t; +typedef uint32_t hri_tcc_evctrl_reg_t; +typedef uint32_t hri_tcc_fctrla_reg_t; +typedef uint32_t hri_tcc_fctrlb_reg_t; +typedef uint32_t hri_tcc_intenset_reg_t; +typedef uint32_t hri_tcc_intflag_reg_t; +typedef uint32_t hri_tcc_per_reg_t; +typedef uint32_t hri_tcc_perbuf_reg_t; +typedef uint32_t hri_tcc_status_reg_t; +typedef uint32_t hri_tcc_syncbusy_reg_t; +typedef uint32_t hri_tcc_wave_reg_t; +typedef uint32_t hri_tcc_wexctrl_reg_t; +typedef uint8_t hri_tcc_ctrlbset_reg_t; +typedef uint8_t hri_tcc_dbgctrl_reg_t; + +static inline void hri_tcc_wait_for_sync(const void *const hw, hri_tcc_syncbusy_reg_t reg) +{ + while (((Tcc *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_tcc_is_syncing(const void *const hw, hri_tcc_syncbusy_reg_t reg) +{ + return ((Tcc *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_tcc_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF; +} + +static inline bool hri_tcc_get_INTFLAG_TRG_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG; +} + +static inline bool hri_tcc_get_INTFLAG_CNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT; +} + +static inline bool hri_tcc_get_INTFLAG_ERR_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR; +} + +static inline bool hri_tcc_get_INTFLAG_UFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_UFS) >> TCC_INTFLAG_UFS_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_UFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_UFS; +} + +static inline bool hri_tcc_get_INTFLAG_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS; +} + +static inline bool hri_tcc_get_INTFLAG_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA; +} + +static inline bool hri_tcc_get_INTFLAG_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB; +} + +static inline bool hri_tcc_get_INTFLAG_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0; +} + +static inline bool hri_tcc_get_INTFLAG_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1; +} + +static inline bool hri_tcc_get_INTFLAG_MC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0; +} + +static inline bool hri_tcc_get_INTFLAG_MC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1; +} + +static inline bool hri_tcc_get_INTFLAG_MC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2; +} + +static inline bool hri_tcc_get_INTFLAG_MC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3; +} + +static inline bool hri_tcc_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos; +} + +static inline void hri_tcc_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF; +} + +static inline bool hri_tcc_get_interrupt_TRG_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos; +} + +static inline void hri_tcc_clear_interrupt_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG; +} + +static inline bool hri_tcc_get_interrupt_CNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos; +} + +static inline void hri_tcc_clear_interrupt_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT; +} + +static inline bool hri_tcc_get_interrupt_ERR_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos; +} + +static inline void hri_tcc_clear_interrupt_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR; +} + +static inline bool hri_tcc_get_interrupt_UFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_UFS) >> TCC_INTFLAG_UFS_Pos; +} + +static inline void hri_tcc_clear_interrupt_UFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_UFS; +} + +static inline bool hri_tcc_get_interrupt_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos; +} + +static inline void hri_tcc_clear_interrupt_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS; +} + +static inline bool hri_tcc_get_interrupt_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA; +} + +static inline bool hri_tcc_get_interrupt_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB; +} + +static inline bool hri_tcc_get_interrupt_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0; +} + +static inline bool hri_tcc_get_interrupt_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1; +} + +static inline bool hri_tcc_get_interrupt_MC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0; +} + +static inline bool hri_tcc_get_interrupt_MC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1; +} + +static inline bool hri_tcc_get_interrupt_MC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2; +} + +static inline bool hri_tcc_get_interrupt_MC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3; +} + +static inline hri_tcc_intflag_reg_t hri_tcc_get_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_intflag_reg_t hri_tcc_read_INTFLAG_reg(const void *const hw) +{ + return ((Tcc *)hw)->INTFLAG.reg; +} + +static inline void hri_tcc_clear_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask) +{ + ((Tcc *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_tcc_set_CTRLB_DIR_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR; +} + +static inline bool hri_tcc_get_CTRLB_DIR_bit(const void *const hw) +{ + return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_DIR) >> TCC_CTRLBSET_DIR_Pos; +} + +static inline void hri_tcc_write_CTRLB_DIR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR; + } else { + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR; + } +} + +static inline void hri_tcc_clear_CTRLB_DIR_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR; +} + +static inline void hri_tcc_set_CTRLB_LUPD_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD; +} + +static inline bool hri_tcc_get_CTRLB_LUPD_bit(const void *const hw) +{ + return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_LUPD) >> TCC_CTRLBSET_LUPD_Pos; +} + +static inline void hri_tcc_write_CTRLB_LUPD_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD; + } else { + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD; + } +} + +static inline void hri_tcc_clear_CTRLB_LUPD_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD; +} + +static inline void hri_tcc_set_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT; +} + +static inline bool hri_tcc_get_CTRLB_ONESHOT_bit(const void *const hw) +{ + return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_ONESHOT) >> TCC_CTRLBSET_ONESHOT_Pos; +} + +static inline void hri_tcc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT; + } else { + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT; + } +} + +static inline void hri_tcc_clear_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT; +} + +static inline void hri_tcc_set_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(mask); +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_IDXCMD(mask)) >> TCC_CTRLBSET_IDXCMD_Pos; + return tmp; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_IDXCMD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_IDXCMD_Msk) >> TCC_CTRLBSET_IDXCMD_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(data); + ((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_IDXCMD(data); +} + +static inline void hri_tcc_clear_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_IDXCMD(mask); +} + +static inline void hri_tcc_set_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(mask); +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_CMD(mask)) >> TCC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_CMD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_CMD_Msk) >> TCC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(data); + ((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_CMD(data); +} + +static inline void hri_tcc_clear_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_CMD(mask); +} + +static inline void hri_tcc_set_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBSET.reg = mask; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_reg(const void *const hw) +{ + return ((Tcc *)hw)->CTRLBSET.reg; +} + +static inline void hri_tcc_write_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t data) +{ + ((Tcc *)hw)->CTRLBSET.reg = data; + ((Tcc *)hw)->CTRLBCLR.reg = ~data; +} + +static inline void hri_tcc_clear_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBCLR.reg = mask; +} + +static inline void hri_tcc_set_INTEN_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF; +} + +static inline bool hri_tcc_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_OVF) >> TCC_INTENSET_OVF_Pos; +} + +static inline void hri_tcc_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF; + } +} + +static inline void hri_tcc_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF; +} + +static inline void hri_tcc_set_INTEN_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG; +} + +static inline bool hri_tcc_get_INTEN_TRG_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_TRG) >> TCC_INTENSET_TRG_Pos; +} + +static inline void hri_tcc_write_INTEN_TRG_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG; + } +} + +static inline void hri_tcc_clear_INTEN_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG; +} + +static inline void hri_tcc_set_INTEN_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT; +} + +static inline bool hri_tcc_get_INTEN_CNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_CNT) >> TCC_INTENSET_CNT_Pos; +} + +static inline void hri_tcc_write_INTEN_CNT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT; + } +} + +static inline void hri_tcc_clear_INTEN_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT; +} + +static inline void hri_tcc_set_INTEN_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR; +} + +static inline bool hri_tcc_get_INTEN_ERR_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_ERR) >> TCC_INTENSET_ERR_Pos; +} + +static inline void hri_tcc_write_INTEN_ERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR; + } +} + +static inline void hri_tcc_clear_INTEN_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR; +} + +static inline void hri_tcc_set_INTEN_UFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_UFS; +} + +static inline bool hri_tcc_get_INTEN_UFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_UFS) >> TCC_INTENSET_UFS_Pos; +} + +static inline void hri_tcc_write_INTEN_UFS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_UFS; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_UFS; + } +} + +static inline void hri_tcc_clear_INTEN_UFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_UFS; +} + +static inline void hri_tcc_set_INTEN_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS; +} + +static inline bool hri_tcc_get_INTEN_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_DFS) >> TCC_INTENSET_DFS_Pos; +} + +static inline void hri_tcc_write_INTEN_DFS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS; + } +} + +static inline void hri_tcc_clear_INTEN_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS; +} + +static inline void hri_tcc_set_INTEN_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA; +} + +static inline bool hri_tcc_get_INTEN_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTA) >> TCC_INTENSET_FAULTA_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULTA_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA; + } +} + +static inline void hri_tcc_clear_INTEN_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA; +} + +static inline void hri_tcc_set_INTEN_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB; +} + +static inline bool hri_tcc_get_INTEN_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTB) >> TCC_INTENSET_FAULTB_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULTB_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB; + } +} + +static inline void hri_tcc_clear_INTEN_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB; +} + +static inline void hri_tcc_set_INTEN_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0; +} + +static inline bool hri_tcc_get_INTEN_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT0) >> TCC_INTENSET_FAULT0_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULT0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0; + } +} + +static inline void hri_tcc_clear_INTEN_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0; +} + +static inline void hri_tcc_set_INTEN_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1; +} + +static inline bool hri_tcc_get_INTEN_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT1) >> TCC_INTENSET_FAULT1_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULT1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1; + } +} + +static inline void hri_tcc_clear_INTEN_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1; +} + +static inline void hri_tcc_set_INTEN_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0; +} + +static inline bool hri_tcc_get_INTEN_MC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC0) >> TCC_INTENSET_MC0_Pos; +} + +static inline void hri_tcc_write_INTEN_MC0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0; + } +} + +static inline void hri_tcc_clear_INTEN_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0; +} + +static inline void hri_tcc_set_INTEN_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1; +} + +static inline bool hri_tcc_get_INTEN_MC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC1) >> TCC_INTENSET_MC1_Pos; +} + +static inline void hri_tcc_write_INTEN_MC1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1; + } +} + +static inline void hri_tcc_clear_INTEN_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1; +} + +static inline void hri_tcc_set_INTEN_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2; +} + +static inline bool hri_tcc_get_INTEN_MC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC2) >> TCC_INTENSET_MC2_Pos; +} + +static inline void hri_tcc_write_INTEN_MC2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2; + } +} + +static inline void hri_tcc_clear_INTEN_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2; +} + +static inline void hri_tcc_set_INTEN_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3; +} + +static inline bool hri_tcc_get_INTEN_MC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC3) >> TCC_INTENSET_MC3_Pos; +} + +static inline void hri_tcc_write_INTEN_MC3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3; + } +} + +static inline void hri_tcc_clear_INTEN_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3; +} + +static inline void hri_tcc_set_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) +{ + ((Tcc *)hw)->INTENSET.reg = mask; +} + +static inline hri_tcc_intenset_reg_t hri_tcc_get_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_intenset_reg_t hri_tcc_read_INTEN_reg(const void *const hw) +{ + return ((Tcc *)hw)->INTENSET.reg; +} + +static inline void hri_tcc_write_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t data) +{ + ((Tcc *)hw)->INTENSET.reg = data; + ((Tcc *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_tcc_clear_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) +{ + ((Tcc *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_tcc_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_SWRST) >> TCC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_ENABLE) >> TCC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) >> TCC_SYNCBUSY_CTRLB_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_STATUS_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_STATUS) >> TCC_SYNCBUSY_STATUS_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_COUNT) >> TCC_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_PATT_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PATT) >> TCC_SYNCBUSY_PATT_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_WAVE_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_WAVE) >> TCC_SYNCBUSY_WAVE_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_PER_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PER) >> TCC_SYNCBUSY_PER_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC0) >> TCC_SYNCBUSY_CC0_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC1) >> TCC_SYNCBUSY_CC1_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC2) >> TCC_SYNCBUSY_CC2_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC3) >> TCC_SYNCBUSY_CC3_Pos; +} + +static inline hri_tcc_syncbusy_reg_t hri_tcc_get_SYNCBUSY_reg(const void *const hw, hri_tcc_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_syncbusy_reg_t hri_tcc_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Tcc *)hw)->SYNCBUSY.reg; +} + +static inline void hri_tcc_set_CTRLA_SWRST_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_SWRST; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_SWRST) >> TCC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_set_CTRLA_ENABLE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ENABLE; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_ENABLE) >> TCC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_ENABLE; + tmp |= value << TCC_CTRLA_ENABLE_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ENABLE; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ENABLE; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RUNSTDBY; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_RUNSTDBY) >> TCC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_RUNSTDBY; + tmp |= value << TCC_CTRLA_RUNSTDBY_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RUNSTDBY; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RUNSTDBY; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_ALOCK_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ALOCK; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_ALOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_ALOCK) >> TCC_CTRLA_ALOCK_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_ALOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_ALOCK; + tmp |= value << TCC_CTRLA_ALOCK_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_ALOCK_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ALOCK; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_ALOCK_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ALOCK; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_MSYNC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_MSYNC; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_MSYNC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_MSYNC) >> TCC_CTRLA_MSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_MSYNC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_MSYNC; + tmp |= value << TCC_CTRLA_MSYNC_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_MSYNC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_MSYNC; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_MSYNC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_MSYNC; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_DMAOS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_DMAOS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_DMAOS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_DMAOS) >> TCC_CTRLA_DMAOS_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_DMAOS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_DMAOS; + tmp |= value << TCC_CTRLA_DMAOS_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_DMAOS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_DMAOS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_DMAOS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_DMAOS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN0) >> TCC_CTRLA_CPTEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN0; + tmp |= value << TCC_CTRLA_CPTEN0_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN1) >> TCC_CTRLA_CPTEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN1; + tmp |= value << TCC_CTRLA_CPTEN1_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN2) >> TCC_CTRLA_CPTEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN2; + tmp |= value << TCC_CTRLA_CPTEN2_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN3) >> TCC_CTRLA_CPTEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN3; + tmp |= value << TCC_CTRLA_CPTEN3_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RESOLUTION(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_RESOLUTION(mask)) >> TCC_CTRLA_RESOLUTION_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_RESOLUTION_Msk; + tmp |= TCC_CTRLA_RESOLUTION(data); + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RESOLUTION(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RESOLUTION(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_RESOLUTION_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_RESOLUTION_Msk) >> TCC_CTRLA_RESOLUTION_Pos; + return tmp; +} + +static inline void hri_tcc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCALER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCALER(mask)) >> TCC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_PRESCALER_Msk; + tmp |= TCC_CTRLA_PRESCALER(data); + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCALER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCALER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCALER_Msk) >> TCC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tcc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCSYNC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCSYNC(mask)) >> TCC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_PRESCSYNC_Msk; + tmp |= TCC_CTRLA_PRESCSYNC(data); + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCSYNC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCSYNC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCSYNC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCSYNC_Msk) >> TCC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + return ((Tcc *)hw)->CTRLA.reg; +} + +static inline void hri_tcc_set_FCTRLA_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLA_KEEP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_KEEP) >> TCC_FCTRLA_KEEP_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLA_KEEP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_KEEP; + tmp |= value << TCC_FCTRLA_KEEP_Pos; + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLA_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLA_QUAL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_QUAL) >> TCC_FCTRLA_QUAL_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLA_QUAL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_QUAL; + tmp |= value << TCC_FCTRLA_QUAL_Pos; + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLA_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLA_RESTART_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_RESTART) >> TCC_FCTRLA_RESTART_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLA_RESTART_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_RESTART; + tmp |= value << TCC_FCTRLA_RESTART_Pos; + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLA_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLA_BLANKPRESC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANKPRESC) >> TCC_FCTRLA_BLANKPRESC_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLA_BLANKPRESC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_BLANKPRESC; + tmp |= value << TCC_FCTRLA_BLANKPRESC_Pos; + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_SRC(mask)) >> TCC_FCTRLA_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_SRC_Msk; + tmp |= TCC_FCTRLA_SRC(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_SRC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_SRC_Msk) >> TCC_FCTRLA_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANK(mask)) >> TCC_FCTRLA_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_BLANK_Msk; + tmp |= TCC_FCTRLA_BLANK(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANK_Msk) >> TCC_FCTRLA_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_HALT(mask)) >> TCC_FCTRLA_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_HALT_Msk; + tmp |= TCC_FCTRLA_HALT(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_HALT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_HALT_Msk) >> TCC_FCTRLA_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CHSEL(mask)) >> TCC_FCTRLA_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_CHSEL_Msk; + tmp |= TCC_FCTRLA_CHSEL(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CHSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CHSEL_Msk) >> TCC_FCTRLA_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CAPTURE(mask)) >> TCC_FCTRLA_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_CAPTURE_Msk; + tmp |= TCC_FCTRLA_CAPTURE(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CAPTURE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CAPTURE_Msk) >> TCC_FCTRLA_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANKVAL(mask)) >> TCC_FCTRLA_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_BLANKVAL_Msk; + tmp |= TCC_FCTRLA_BLANKVAL(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANKVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANKVAL_Msk) >> TCC_FCTRLA_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_FILTERVAL(mask)) >> TCC_FCTRLA_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_FILTERVAL_Msk; + tmp |= TCC_FCTRLA_FILTERVAL(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_FILTERVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_FILTERVAL_Msk) >> TCC_FCTRLA_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_reg(const void *const hw) +{ + return ((Tcc *)hw)->FCTRLA.reg; +} + +static inline void hri_tcc_set_FCTRLB_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLB_KEEP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_KEEP) >> TCC_FCTRLB_KEEP_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLB_KEEP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_KEEP; + tmp |= value << TCC_FCTRLB_KEEP_Pos; + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLB_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLB_QUAL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_QUAL) >> TCC_FCTRLB_QUAL_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLB_QUAL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_QUAL; + tmp |= value << TCC_FCTRLB_QUAL_Pos; + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLB_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLB_RESTART_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_RESTART) >> TCC_FCTRLB_RESTART_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLB_RESTART_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_RESTART; + tmp |= value << TCC_FCTRLB_RESTART_Pos; + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLB_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLB_BLANKPRESC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANKPRESC) >> TCC_FCTRLB_BLANKPRESC_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLB_BLANKPRESC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_BLANKPRESC; + tmp |= value << TCC_FCTRLB_BLANKPRESC_Pos; + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_SRC(mask)) >> TCC_FCTRLB_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_SRC_Msk; + tmp |= TCC_FCTRLB_SRC(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_SRC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_SRC_Msk) >> TCC_FCTRLB_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANK(mask)) >> TCC_FCTRLB_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_BLANK_Msk; + tmp |= TCC_FCTRLB_BLANK(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANK_Msk) >> TCC_FCTRLB_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_HALT(mask)) >> TCC_FCTRLB_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_HALT_Msk; + tmp |= TCC_FCTRLB_HALT(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_HALT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_HALT_Msk) >> TCC_FCTRLB_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CHSEL(mask)) >> TCC_FCTRLB_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_CHSEL_Msk; + tmp |= TCC_FCTRLB_CHSEL(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CHSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CHSEL_Msk) >> TCC_FCTRLB_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CAPTURE(mask)) >> TCC_FCTRLB_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_CAPTURE_Msk; + tmp |= TCC_FCTRLB_CAPTURE(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CAPTURE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CAPTURE_Msk) >> TCC_FCTRLB_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANKVAL(mask)) >> TCC_FCTRLB_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_BLANKVAL_Msk; + tmp |= TCC_FCTRLB_BLANKVAL(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANKVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANKVAL_Msk) >> TCC_FCTRLB_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_FILTERVAL(mask)) >> TCC_FCTRLB_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_FILTERVAL_Msk; + tmp |= TCC_FCTRLB_FILTERVAL(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_FILTERVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_FILTERVAL_Msk) >> TCC_FCTRLB_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_reg(const void *const hw) +{ + return ((Tcc *)hw)->FCTRLB.reg; +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN0) >> TCC_WEXCTRL_DTIEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN0; + tmp |= value << TCC_WEXCTRL_DTIEN0_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN1) >> TCC_WEXCTRL_DTIEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN1; + tmp |= value << TCC_WEXCTRL_DTIEN1_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN2) >> TCC_WEXCTRL_DTIEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN2; + tmp |= value << TCC_WEXCTRL_DTIEN2_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN3) >> TCC_WEXCTRL_DTIEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN3; + tmp |= value << TCC_WEXCTRL_DTIEN3_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_OTMX(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_OTMX(mask)) >> TCC_WEXCTRL_OTMX_Pos; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_OTMX_Msk; + tmp |= TCC_WEXCTRL_OTMX(data); + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_OTMX(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_OTMX(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_OTMX_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_OTMX_Msk) >> TCC_WEXCTRL_OTMX_Pos; + return tmp; +} + +static inline void hri_tcc_set_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTLS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTLS(mask)) >> TCC_WEXCTRL_DTLS_Pos; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTLS_Msk; + tmp |= TCC_WEXCTRL_DTLS(data); + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTLS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTLS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTLS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTLS_Msk) >> TCC_WEXCTRL_DTLS_Pos; + return tmp; +} + +static inline void hri_tcc_set_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTHS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTHS(mask)) >> TCC_WEXCTRL_DTHS_Pos; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTHS_Msk; + tmp |= TCC_WEXCTRL_DTHS(data); + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTHS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTHS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTHS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTHS_Msk) >> TCC_WEXCTRL_DTHS_Pos; + return tmp; +} + +static inline void hri_tcc_set_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->WEXCTRL.reg; +} + +static inline void hri_tcc_set_DRVCTRL_NRE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE0) >> TCC_DRVCTRL_NRE0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE0; + tmp |= value << TCC_DRVCTRL_NRE0_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE1) >> TCC_DRVCTRL_NRE1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE1; + tmp |= value << TCC_DRVCTRL_NRE1_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE2) >> TCC_DRVCTRL_NRE2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE2; + tmp |= value << TCC_DRVCTRL_NRE2_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE3) >> TCC_DRVCTRL_NRE3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE3; + tmp |= value << TCC_DRVCTRL_NRE3_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE4) >> TCC_DRVCTRL_NRE4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE4; + tmp |= value << TCC_DRVCTRL_NRE4_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE5) >> TCC_DRVCTRL_NRE5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE5; + tmp |= value << TCC_DRVCTRL_NRE5_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE6) >> TCC_DRVCTRL_NRE6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE6; + tmp |= value << TCC_DRVCTRL_NRE6_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE7) >> TCC_DRVCTRL_NRE7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE7; + tmp |= value << TCC_DRVCTRL_NRE7_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV0) >> TCC_DRVCTRL_NRV0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV0; + tmp |= value << TCC_DRVCTRL_NRV0_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV1) >> TCC_DRVCTRL_NRV1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV1; + tmp |= value << TCC_DRVCTRL_NRV1_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV2) >> TCC_DRVCTRL_NRV2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV2; + tmp |= value << TCC_DRVCTRL_NRV2_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV3) >> TCC_DRVCTRL_NRV3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV3; + tmp |= value << TCC_DRVCTRL_NRV3_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV4) >> TCC_DRVCTRL_NRV4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV4; + tmp |= value << TCC_DRVCTRL_NRV4_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV5) >> TCC_DRVCTRL_NRV5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV5; + tmp |= value << TCC_DRVCTRL_NRV5_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV6) >> TCC_DRVCTRL_NRV6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV6; + tmp |= value << TCC_DRVCTRL_NRV6_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV7) >> TCC_DRVCTRL_NRV7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV7; + tmp |= value << TCC_DRVCTRL_NRV7_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN0) >> TCC_DRVCTRL_INVEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN0; + tmp |= value << TCC_DRVCTRL_INVEN0_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN1) >> TCC_DRVCTRL_INVEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN1; + tmp |= value << TCC_DRVCTRL_INVEN1_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN2) >> TCC_DRVCTRL_INVEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN2; + tmp |= value << TCC_DRVCTRL_INVEN2_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN3) >> TCC_DRVCTRL_INVEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN3; + tmp |= value << TCC_DRVCTRL_INVEN3_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN4) >> TCC_DRVCTRL_INVEN4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN4; + tmp |= value << TCC_DRVCTRL_INVEN4_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN5) >> TCC_DRVCTRL_INVEN5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN5; + tmp |= value << TCC_DRVCTRL_INVEN5_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN6) >> TCC_DRVCTRL_INVEN6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN6; + tmp |= value << TCC_DRVCTRL_INVEN6_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN7) >> TCC_DRVCTRL_INVEN7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN7; + tmp |= value << TCC_DRVCTRL_INVEN7_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL0(mask)) >> TCC_DRVCTRL_FILTERVAL0_Pos; + return tmp; +} + +static inline void hri_tcc_write_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_FILTERVAL0_Msk; + tmp |= TCC_DRVCTRL_FILTERVAL0(data); + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL0_Msk) >> TCC_DRVCTRL_FILTERVAL0_Pos; + return tmp; +} + +static inline void hri_tcc_set_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL1(mask)) >> TCC_DRVCTRL_FILTERVAL1_Pos; + return tmp; +} + +static inline void hri_tcc_write_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_FILTERVAL1_Msk; + tmp |= TCC_DRVCTRL_FILTERVAL1(data); + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL1_Msk) >> TCC_DRVCTRL_FILTERVAL1_Pos; + return tmp; +} + +static inline void hri_tcc_set_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->DRVCTRL.reg; +} + +static inline void hri_tcc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_DBGRUN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp = (tmp & TCC_DBGCTRL_DBGRUN) >> TCC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp &= ~TCC_DBGCTRL_DBGRUN; + tmp |= value << TCC_DBGCTRL_DBGRUN_Pos; + ((Tcc *)hw)->DBGCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_DBGRUN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_DBGRUN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DBGCTRL_FDDBD_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_FDDBD; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DBGCTRL_FDDBD_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp = (tmp & TCC_DBGCTRL_FDDBD) >> TCC_DBGCTRL_FDDBD_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DBGCTRL_FDDBD_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp &= ~TCC_DBGCTRL_FDDBD; + tmp |= value << TCC_DBGCTRL_FDDBD_Pos; + ((Tcc *)hw)->DBGCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DBGCTRL_FDDBD_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_FDDBD; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DBGCTRL_FDDBD_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_FDDBD; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_dbgctrl_reg_t hri_tcc_get_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_dbgctrl_reg_t hri_tcc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->DBGCTRL.reg; +} + +static inline void hri_tcc_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_OVFEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_OVFEO) >> TCC_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_OVFEO; + tmp |= value << TCC_EVCTRL_OVFEO_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_OVFEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_OVFEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TRGEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TRGEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TRGEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TRGEO) >> TCC_EVCTRL_TRGEO_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TRGEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TRGEO; + tmp |= value << TCC_EVCTRL_TRGEO_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TRGEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TRGEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TRGEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TRGEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_CNTEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_CNTEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_CNTEO) >> TCC_EVCTRL_CNTEO_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_CNTEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_CNTEO; + tmp |= value << TCC_EVCTRL_CNTEO_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_CNTEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_CNTEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCINV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCINV0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCINV0) >> TCC_EVCTRL_TCINV0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCINV0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCINV0; + tmp |= value << TCC_EVCTRL_TCINV0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCINV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCINV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCINV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCINV1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCINV1) >> TCC_EVCTRL_TCINV1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCINV1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCINV1; + tmp |= value << TCC_EVCTRL_TCINV1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCINV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCINV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCEI0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCEI0) >> TCC_EVCTRL_TCEI0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCEI0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCEI0; + tmp |= value << TCC_EVCTRL_TCEI0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCEI1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCEI1) >> TCC_EVCTRL_TCEI1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCEI1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCEI1; + tmp |= value << TCC_EVCTRL_TCEI1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI0) >> TCC_EVCTRL_MCEI0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI0; + tmp |= value << TCC_EVCTRL_MCEI0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI1) >> TCC_EVCTRL_MCEI1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI1; + tmp |= value << TCC_EVCTRL_MCEI1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI2) >> TCC_EVCTRL_MCEI2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI2; + tmp |= value << TCC_EVCTRL_MCEI2_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI3) >> TCC_EVCTRL_MCEI3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI3; + tmp |= value << TCC_EVCTRL_MCEI3_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO0) >> TCC_EVCTRL_MCEO0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO0; + tmp |= value << TCC_EVCTRL_MCEO0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO1) >> TCC_EVCTRL_MCEO1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO1; + tmp |= value << TCC_EVCTRL_MCEO1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO2) >> TCC_EVCTRL_MCEO2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO2; + tmp |= value << TCC_EVCTRL_MCEO2_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO3) >> TCC_EVCTRL_MCEO3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO3; + tmp |= value << TCC_EVCTRL_MCEO3_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT0(mask)) >> TCC_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_EVACT0_Msk; + tmp |= TCC_EVCTRL_EVACT0(data); + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT0_Msk) >> TCC_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_tcc_set_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT1(mask)) >> TCC_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_EVACT1_Msk; + tmp |= TCC_EVCTRL_EVACT1(data); + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT1_Msk) >> TCC_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_tcc_set_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_CNTSEL(mask)) >> TCC_EVCTRL_CNTSEL_Pos; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_CNTSEL_Msk; + tmp |= TCC_EVCTRL_CNTSEL(data); + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_CNTSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_CNTSEL_Msk) >> TCC_EVCTRL_CNTSEL_Pos; + return tmp; +} + +static inline void hri_tcc_set_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->EVCTRL.reg; +} + +static inline void hri_tcc_set_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_COUNT_Msk; + tmp |= TCC_COUNT_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH6_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_COUNT_Msk; + tmp |= TCC_COUNT_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH5_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_COUNT_Msk; + tmp |= TCC_COUNT_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH4_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_COUNT_Msk; + tmp |= TCC_COUNT_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_COUNT_reg(const void *const hw, hri_tcc_count_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + return ((Tcc *)hw)->COUNT.reg; +} + +static inline void hri_tcc_set_PATT_PGE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE0) >> TCC_PATT_PGE0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE0; + tmp |= value << TCC_PATT_PGE0_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE1) >> TCC_PATT_PGE1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE1; + tmp |= value << TCC_PATT_PGE1_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE2) >> TCC_PATT_PGE2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE2; + tmp |= value << TCC_PATT_PGE2_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE3) >> TCC_PATT_PGE3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE3; + tmp |= value << TCC_PATT_PGE3_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE4) >> TCC_PATT_PGE4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE4; + tmp |= value << TCC_PATT_PGE4_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE5) >> TCC_PATT_PGE5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE5; + tmp |= value << TCC_PATT_PGE5_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE6) >> TCC_PATT_PGE6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE6; + tmp |= value << TCC_PATT_PGE6_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE7) >> TCC_PATT_PGE7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE7; + tmp |= value << TCC_PATT_PGE7_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV0) >> TCC_PATT_PGV0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV0; + tmp |= value << TCC_PATT_PGV0_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV1) >> TCC_PATT_PGV1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV1; + tmp |= value << TCC_PATT_PGV1_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV2) >> TCC_PATT_PGV2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV2; + tmp |= value << TCC_PATT_PGV2_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV3) >> TCC_PATT_PGV3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV3; + tmp |= value << TCC_PATT_PGV3_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV4) >> TCC_PATT_PGV4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV4; + tmp |= value << TCC_PATT_PGV4_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV5) >> TCC_PATT_PGV5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV5; + tmp |= value << TCC_PATT_PGV5_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV6) >> TCC_PATT_PGV6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV6; + tmp |= value << TCC_PATT_PGV6_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV7) >> TCC_PATT_PGV7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV7; + tmp |= value << TCC_PATT_PGV7_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_patt_reg_t hri_tcc_get_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + uint16_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PATT_reg(const void *const hw, hri_tcc_patt_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_patt_reg_t hri_tcc_read_PATT_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + return ((Tcc *)hw)->PATT.reg; +} + +static inline void hri_tcc_set_WAVE_CIPEREN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CIPEREN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CIPEREN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CIPEREN) >> TCC_WAVE_CIPEREN_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CIPEREN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CIPEREN; + tmp |= value << TCC_WAVE_CIPEREN_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CIPEREN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CIPEREN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CIPEREN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CIPEREN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN0) >> TCC_WAVE_CICCEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN0; + tmp |= value << TCC_WAVE_CICCEN0_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN1) >> TCC_WAVE_CICCEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN1; + tmp |= value << TCC_WAVE_CICCEN1_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN2) >> TCC_WAVE_CICCEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN2; + tmp |= value << TCC_WAVE_CICCEN2_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN3) >> TCC_WAVE_CICCEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN3; + tmp |= value << TCC_WAVE_CICCEN3_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL0) >> TCC_WAVE_POL0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL0; + tmp |= value << TCC_WAVE_POL0_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL1) >> TCC_WAVE_POL1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL1; + tmp |= value << TCC_WAVE_POL1_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL2) >> TCC_WAVE_POL2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL2; + tmp |= value << TCC_WAVE_POL2_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL3) >> TCC_WAVE_POL3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL3; + tmp |= value << TCC_WAVE_POL3_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP0) >> TCC_WAVE_SWAP0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP0; + tmp |= value << TCC_WAVE_SWAP0_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP1) >> TCC_WAVE_SWAP1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP1; + tmp |= value << TCC_WAVE_SWAP1_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP2) >> TCC_WAVE_SWAP2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP2; + tmp |= value << TCC_WAVE_SWAP2_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP3) >> TCC_WAVE_SWAP3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP3; + tmp |= value << TCC_WAVE_SWAP3_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_WAVEGEN(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_WAVEGEN(mask)) >> TCC_WAVE_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tcc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_WAVEGEN_Msk; + tmp |= TCC_WAVE_WAVEGEN(data); + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_WAVEGEN(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_WAVEGEN(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_WAVEGEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_WAVEGEN_Msk) >> TCC_WAVE_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tcc_set_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_RAMP(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_RAMP(mask)) >> TCC_WAVE_RAMP_Pos; + return tmp; +} + +static inline void hri_tcc_write_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_RAMP_Msk; + tmp |= TCC_WAVE_RAMP(data); + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_RAMP(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_RAMP(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_RAMP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_RAMP_Msk) >> TCC_WAVE_RAMP_Pos; + return tmp; +} + +static inline void hri_tcc_set_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + return ((Tcc *)hw)->WAVE.reg; +} + +static inline void hri_tcc_set_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH4_DITHER(mask)) >> TCC_PER_DITH4_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_DITH4_DITHER_Msk; + tmp |= TCC_PER_DITH4_DITHER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_DITHER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH4_DITHER_Msk) >> TCC_PER_DITH4_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH5_DITHER(mask)) >> TCC_PER_DITH5_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_DITH5_DITHER_Msk; + tmp |= TCC_PER_DITH5_DITHER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_DITHER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH5_DITHER_Msk) >> TCC_PER_DITH5_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH6_DITHER(mask)) >> TCC_PER_DITH6_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_DITH6_DITHER_Msk; + tmp |= TCC_PER_DITH6_DITHER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_DITHER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH6_DITHER_Msk) >> TCC_PER_DITH6_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_PER_Msk; + tmp |= TCC_PER_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_PER_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_PER_Msk; + tmp |= TCC_PER_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_PER_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_PER_Msk; + tmp |= TCC_PER_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_PER_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_PER_Msk; + tmp |= TCC_PER_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_PER_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PER_reg(const void *const hw, hri_tcc_per_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + return ((Tcc *)hw)->PER.reg; +} + +static inline void hri_tcc_set_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, + hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH4_DITHER(mask)) >> TCC_CC_DITH4_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_DITH4_DITHER_Msk; + tmp |= TCC_CC_DITH4_DITHER(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH4_DITHER_Msk) >> TCC_CC_DITH4_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, + hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH5_DITHER(mask)) >> TCC_CC_DITH5_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_DITH5_DITHER_Msk; + tmp |= TCC_CC_DITH5_DITHER(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH5_DITHER_Msk) >> TCC_CC_DITH5_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, + hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH6_DITHER(mask)) >> TCC_CC_DITH6_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_DITH6_DITHER_Msk; + tmp |= TCC_CC_DITH6_DITHER(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH6_DITHER_Msk) >> TCC_CC_DITH6_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_CC_Msk; + tmp |= TCC_CC_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_CC_Msk; + tmp |= TCC_CC_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_CC_Msk; + tmp |= TCC_CC_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_CC_Msk; + tmp |= TCC_CC_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_reg(const void *const hw, uint8_t index) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3); + return ((Tcc *)hw)->CC[index].reg; +} + +static inline void hri_tcc_set_PATTBUF_PGEB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB0) >> TCC_PATTBUF_PGEB0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB0; + tmp |= value << TCC_PATTBUF_PGEB0_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB1) >> TCC_PATTBUF_PGEB1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB1; + tmp |= value << TCC_PATTBUF_PGEB1_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB2) >> TCC_PATTBUF_PGEB2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB2; + tmp |= value << TCC_PATTBUF_PGEB2_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB3) >> TCC_PATTBUF_PGEB3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB3; + tmp |= value << TCC_PATTBUF_PGEB3_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB4) >> TCC_PATTBUF_PGEB4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB4; + tmp |= value << TCC_PATTBUF_PGEB4_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB5) >> TCC_PATTBUF_PGEB5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB5; + tmp |= value << TCC_PATTBUF_PGEB5_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB6) >> TCC_PATTBUF_PGEB6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB6; + tmp |= value << TCC_PATTBUF_PGEB6_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB7) >> TCC_PATTBUF_PGEB7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB7; + tmp |= value << TCC_PATTBUF_PGEB7_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB0) >> TCC_PATTBUF_PGVB0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB0; + tmp |= value << TCC_PATTBUF_PGVB0_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB1) >> TCC_PATTBUF_PGVB1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB1; + tmp |= value << TCC_PATTBUF_PGVB1_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB2) >> TCC_PATTBUF_PGVB2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB2; + tmp |= value << TCC_PATTBUF_PGVB2_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB3) >> TCC_PATTBUF_PGVB3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB3; + tmp |= value << TCC_PATTBUF_PGVB3_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB4) >> TCC_PATTBUF_PGVB4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB4; + tmp |= value << TCC_PATTBUF_PGVB4_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB5) >> TCC_PATTBUF_PGVB5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB5; + tmp |= value << TCC_PATTBUF_PGVB5_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB6) >> TCC_PATTBUF_PGVB6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB6; + tmp |= value << TCC_PATTBUF_PGVB6_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB7) >> TCC_PATTBUF_PGVB7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB7; + tmp |= value << TCC_PATTBUF_PGVB7_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_pattbuf_reg_t hri_tcc_get_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_pattbuf_reg_t hri_tcc_read_PATTBUF_reg(const void *const hw) +{ + return ((Tcc *)hw)->PATTBUF.reg; +} + +static inline void hri_tcc_set_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, + hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH4_DITHERBUF(mask)) >> TCC_PERBUF_DITH4_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_DITH4_DITHERBUF_Msk; + tmp |= TCC_PERBUF_DITH4_DITHERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH4_DITHERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH4_DITHERBUF_Msk) >> TCC_PERBUF_DITH4_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, + hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH5_DITHERBUF(mask)) >> TCC_PERBUF_DITH5_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_DITH5_DITHERBUF_Msk; + tmp |= TCC_PERBUF_DITH5_DITHERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH5_DITHERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH5_DITHERBUF_Msk) >> TCC_PERBUF_DITH5_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, + hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH6_DITHERBUF(mask)) >> TCC_PERBUF_DITH6_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_DITH6_DITHERBUF_Msk; + tmp |= TCC_PERBUF_DITH6_DITHERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH6_DITHERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH6_DITHERBUF_Msk) >> TCC_PERBUF_DITH6_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_PERBUF_Msk; + tmp |= TCC_PERBUF_PERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH6_PERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_PERBUF_Msk; + tmp |= TCC_PERBUF_PERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH5_PERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_PERBUF_Msk; + tmp |= TCC_PERBUF_PERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH4_PERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_PERBUF_Msk; + tmp |= TCC_PERBUF_PERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_PERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_reg(const void *const hw) +{ + return ((Tcc *)hw)->PERBUF.reg; +} + +static inline void hri_tcc_set_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_CCBUF_Msk; + tmp |= TCC_CCBUF_CCBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH5_DITHERBUF(mask)) >> TCC_CCBUF_DITH5_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_DITH5_DITHERBUF_Msk; + tmp |= TCC_CCBUF_DITH5_DITHERBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH5_DITHERBUF_Msk) >> TCC_CCBUF_DITH5_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH6_DITHERBUF(mask)) >> TCC_CCBUF_DITH6_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_DITH6_DITHERBUF_Msk; + tmp |= TCC_CCBUF_DITH6_DITHERBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH6_DITHERBUF_Msk) >> TCC_CCBUF_DITH6_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_CCBUF_Msk; + tmp |= TCC_CCBUF_CCBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_CCBUF_Msk; + tmp |= TCC_CCBUF_CCBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH4_DITHERBUF(mask)) >> TCC_CCBUF_DITH4_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_DITH4_DITHERBUF_Msk; + tmp |= TCC_CCBUF_DITH4_DITHERBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH4_DITHERBUF_Msk) >> TCC_CCBUF_DITH4_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_CCBUF_Msk; + tmp |= TCC_CCBUF_CCBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + return ((Tcc *)hw)->CCBUF[index].reg; +} + +static inline bool hri_tcc_get_STATUS_STOP_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_STOP) >> TCC_STATUS_STOP_Pos; +} + +static inline void hri_tcc_clear_STATUS_STOP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_STOP; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_IDX_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_IDX) >> TCC_STATUS_IDX_Pos; +} + +static inline void hri_tcc_clear_STATUS_IDX_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_IDX; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_UFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_UFS) >> TCC_STATUS_UFS_Pos; +} + +static inline void hri_tcc_clear_STATUS_UFS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_UFS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_DFS) >> TCC_STATUS_DFS_Pos; +} + +static inline void hri_tcc_clear_STATUS_DFS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_DFS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_SLAVE_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_SLAVE) >> TCC_STATUS_SLAVE_Pos; +} + +static inline void hri_tcc_clear_STATUS_SLAVE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_SLAVE; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_PATTBUFV_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PATTBUFV) >> TCC_STATUS_PATTBUFV_Pos; +} + +static inline void hri_tcc_clear_STATUS_PATTBUFV_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_PATTBUFV; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_PERBUFV_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PERBUFV) >> TCC_STATUS_PERBUFV_Pos; +} + +static inline void hri_tcc_clear_STATUS_PERBUFV_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_PERBUFV; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTAIN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTAIN) >> TCC_STATUS_FAULTAIN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTAIN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTAIN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTBIN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTBIN) >> TCC_STATUS_FAULTBIN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTBIN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTBIN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT0IN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0IN) >> TCC_STATUS_FAULT0IN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT0IN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0IN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT1IN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1IN) >> TCC_STATUS_FAULT1IN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT1IN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1IN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTA) >> TCC_STATUS_FAULTA_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTA_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTA; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTB) >> TCC_STATUS_FAULTB_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTB_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTB; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0) >> TCC_STATUS_FAULT0_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1) >> TCC_STATUS_FAULT1_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV0_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV0) >> TCC_STATUS_CCBUFV0_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV1_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV1) >> TCC_STATUS_CCBUFV1_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV2_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV2) >> TCC_STATUS_CCBUFV2_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV3_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV3) >> TCC_STATUS_CCBUFV3_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP0_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP0) >> TCC_STATUS_CMP0_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP1_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP1) >> TCC_STATUS_CMP1_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP2_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP2) >> TCC_STATUS_CMP2_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP3_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP3) >> TCC_STATUS_CMP3_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_status_reg_t hri_tcc_get_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_clear_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_status_reg_t hri_tcc_read_STATUS_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + return ((Tcc *)hw)->STATUS.reg; +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_tcc_set_COUNT_DITH4_reg(a, b) hri_tcc_set_COUNT_reg(a, b) +#define hri_tcc_get_COUNT_DITH4_reg(a, b) hri_tcc_get_COUNT_reg(a, b) +#define hri_tcc_write_COUNT_DITH4_reg(a, b) hri_tcc_write_COUNT_reg(a, b) +#define hri_tcc_clear_COUNT_DITH4_reg(a, b) hri_tcc_clear_COUNT_reg(a, b) +#define hri_tcc_toggle_COUNT_DITH4_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b) +#define hri_tcc_read_COUNT_DITH4_reg(a) hri_tcc_read_COUNT_reg(a) +#define hri_tcc_set_COUNT_DITH5_reg(a, b) hri_tcc_set_COUNT_reg(a, b) +#define hri_tcc_get_COUNT_DITH5_reg(a, b) hri_tcc_get_COUNT_reg(a, b) +#define hri_tcc_write_COUNT_DITH5_reg(a, b) hri_tcc_write_COUNT_reg(a, b) +#define hri_tcc_clear_COUNT_DITH5_reg(a, b) hri_tcc_clear_COUNT_reg(a, b) +#define hri_tcc_toggle_COUNT_DITH5_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b) +#define hri_tcc_read_COUNT_DITH5_reg(a) hri_tcc_read_COUNT_reg(a) +#define hri_tcc_set_COUNT_DITH6_reg(a, b) hri_tcc_set_COUNT_reg(a, b) +#define hri_tcc_get_COUNT_DITH6_reg(a, b) hri_tcc_get_COUNT_reg(a, b) +#define hri_tcc_write_COUNT_DITH6_reg(a, b) hri_tcc_write_COUNT_reg(a, b) +#define hri_tcc_clear_COUNT_DITH6_reg(a, b) hri_tcc_clear_COUNT_reg(a, b) +#define hri_tcc_toggle_COUNT_DITH6_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b) +#define hri_tcc_read_COUNT_DITH6_reg(a) hri_tcc_read_COUNT_reg(a) +#define hri_tcc_set_PER_DITH4_reg(a, b) hri_tcc_set_PER_reg(a, b) +#define hri_tcc_get_PER_DITH4_reg(a, b) hri_tcc_get_PER_reg(a, b) +#define hri_tcc_write_PER_DITH4_reg(a, b) hri_tcc_write_PER_reg(a, b) +#define hri_tcc_clear_PER_DITH4_reg(a, b) hri_tcc_clear_PER_reg(a, b) +#define hri_tcc_toggle_PER_DITH4_reg(a, b) hri_tcc_toggle_PER_reg(a, b) +#define hri_tcc_read_PER_DITH4_reg(a) hri_tcc_read_PER_reg(a) +#define hri_tcc_set_PER_DITH5_reg(a, b) hri_tcc_set_PER_reg(a, b) +#define hri_tcc_get_PER_DITH5_reg(a, b) hri_tcc_get_PER_reg(a, b) +#define hri_tcc_write_PER_DITH5_reg(a, b) hri_tcc_write_PER_reg(a, b) +#define hri_tcc_clear_PER_DITH5_reg(a, b) hri_tcc_clear_PER_reg(a, b) +#define hri_tcc_toggle_PER_DITH5_reg(a, b) hri_tcc_toggle_PER_reg(a, b) +#define hri_tcc_read_PER_DITH5_reg(a) hri_tcc_read_PER_reg(a) +#define hri_tcc_set_PER_DITH6_reg(a, b) hri_tcc_set_PER_reg(a, b) +#define hri_tcc_get_PER_DITH6_reg(a, b) hri_tcc_get_PER_reg(a, b) +#define hri_tcc_write_PER_DITH6_reg(a, b) hri_tcc_write_PER_reg(a, b) +#define hri_tcc_clear_PER_DITH6_reg(a, b) hri_tcc_clear_PER_reg(a, b) +#define hri_tcc_toggle_PER_DITH6_reg(a, b) hri_tcc_toggle_PER_reg(a, b) +#define hri_tcc_read_PER_DITH6_reg(a) hri_tcc_read_PER_reg(a) +#define hri_tcc_set_CC_DITH4_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c) +#define hri_tcc_get_CC_DITH4_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c) +#define hri_tcc_write_CC_DITH4_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c) +#define hri_tcc_clear_CC_DITH4_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c) +#define hri_tcc_toggle_CC_DITH4_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c) +#define hri_tcc_read_CC_DITH4_reg(a, b) hri_tcc_read_CC_reg(a, b) +#define hri_tcc_set_CC_DITH5_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c) +#define hri_tcc_get_CC_DITH5_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c) +#define hri_tcc_write_CC_DITH5_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c) +#define hri_tcc_clear_CC_DITH5_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c) +#define hri_tcc_toggle_CC_DITH5_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c) +#define hri_tcc_read_CC_DITH5_reg(a, b) hri_tcc_read_CC_reg(a, b) +#define hri_tcc_set_CC_DITH6_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c) +#define hri_tcc_get_CC_DITH6_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c) +#define hri_tcc_write_CC_DITH6_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c) +#define hri_tcc_clear_CC_DITH6_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c) +#define hri_tcc_toggle_CC_DITH6_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c) +#define hri_tcc_read_CC_DITH6_reg(a, b) hri_tcc_read_CC_reg(a, b) +#define hri_tcc_set_PERBUF_DITH4_reg(a, b) hri_tcc_set_PERBUF_reg(a, b) +#define hri_tcc_get_PERBUF_DITH4_reg(a, b) hri_tcc_get_PERBUF_reg(a, b) +#define hri_tcc_write_PERBUF_DITH4_reg(a, b) hri_tcc_write_PERBUF_reg(a, b) +#define hri_tcc_clear_PERBUF_DITH4_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b) +#define hri_tcc_toggle_PERBUF_DITH4_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b) +#define hri_tcc_read_PERBUF_DITH4_reg(a) hri_tcc_read_PERBUF_reg(a) +#define hri_tcc_set_PERBUF_DITH5_reg(a, b) hri_tcc_set_PERBUF_reg(a, b) +#define hri_tcc_get_PERBUF_DITH5_reg(a, b) hri_tcc_get_PERBUF_reg(a, b) +#define hri_tcc_write_PERBUF_DITH5_reg(a, b) hri_tcc_write_PERBUF_reg(a, b) +#define hri_tcc_clear_PERBUF_DITH5_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b) +#define hri_tcc_toggle_PERBUF_DITH5_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b) +#define hri_tcc_read_PERBUF_DITH5_reg(a) hri_tcc_read_PERBUF_reg(a) +#define hri_tcc_set_PERBUF_DITH6_reg(a, b) hri_tcc_set_PERBUF_reg(a, b) +#define hri_tcc_get_PERBUF_DITH6_reg(a, b) hri_tcc_get_PERBUF_reg(a, b) +#define hri_tcc_write_PERBUF_DITH6_reg(a, b) hri_tcc_write_PERBUF_reg(a, b) +#define hri_tcc_clear_PERBUF_DITH6_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b) +#define hri_tcc_toggle_PERBUF_DITH6_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b) +#define hri_tcc_read_PERBUF_DITH6_reg(a) hri_tcc_read_PERBUF_reg(a) +#define hri_tcc_set_CCBUF_DITH4_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c) +#define hri_tcc_get_CCBUF_DITH4_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c) +#define hri_tcc_write_CCBUF_DITH4_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c) +#define hri_tcc_clear_CCBUF_DITH4_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c) +#define hri_tcc_toggle_CCBUF_DITH4_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c) +#define hri_tcc_read_CCBUF_DITH4_reg(a, b) hri_tcc_read_CCBUF_reg(a, b) +#define hri_tcc_set_CCBUF_DITH5_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c) +#define hri_tcc_get_CCBUF_DITH5_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c) +#define hri_tcc_write_CCBUF_DITH5_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c) +#define hri_tcc_clear_CCBUF_DITH5_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c) +#define hri_tcc_toggle_CCBUF_DITH5_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c) +#define hri_tcc_read_CCBUF_DITH5_reg(a, b) hri_tcc_read_CCBUF_reg(a, b) +#define hri_tcc_set_CCBUF_DITH6_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c) +#define hri_tcc_get_CCBUF_DITH6_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c) +#define hri_tcc_write_CCBUF_DITH6_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c) +#define hri_tcc_clear_CCBUF_DITH6_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c) +#define hri_tcc_toggle_CCBUF_DITH6_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c) +#define hri_tcc_read_CCBUF_DITH6_reg(a, b) hri_tcc_read_CCBUF_reg(a, b) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_TCC_L21_H_INCLUDED */ +#endif /* _SAML21_TCC_COMPONENT_ */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_trng_l21.h b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_trng_l21.h new file mode 100644 index 00000000..ad4476d1 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_trng_l21.h @@ -0,0 +1,380 @@ +/** + * \file + * + * \brief SAM TRNG + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_TRNG_COMPONENT_ +#ifndef _HRI_TRNG_L21_H_INCLUDED_ +#define _HRI_TRNG_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_TRNG_CRITICAL_SECTIONS) +#define TRNG_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define TRNG_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define TRNG_CRITICAL_SECTION_ENTER() +#define TRNG_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_trng_data_reg_t; +typedef uint8_t hri_trng_ctrla_reg_t; +typedef uint8_t hri_trng_evctrl_reg_t; +typedef uint8_t hri_trng_intenset_reg_t; +typedef uint8_t hri_trng_intflag_reg_t; + +static inline bool hri_trng_get_INTFLAG_DATARDY_bit(const void *const hw) +{ + return (((Trng *)hw)->INTFLAG.reg & TRNG_INTFLAG_DATARDY) >> TRNG_INTFLAG_DATARDY_Pos; +} + +static inline void hri_trng_clear_INTFLAG_DATARDY_bit(const void *const hw) +{ + ((Trng *)hw)->INTFLAG.reg = TRNG_INTFLAG_DATARDY; +} + +static inline bool hri_trng_get_interrupt_DATARDY_bit(const void *const hw) +{ + return (((Trng *)hw)->INTFLAG.reg & TRNG_INTFLAG_DATARDY) >> TRNG_INTFLAG_DATARDY_Pos; +} + +static inline void hri_trng_clear_interrupt_DATARDY_bit(const void *const hw) +{ + ((Trng *)hw)->INTFLAG.reg = TRNG_INTFLAG_DATARDY; +} + +static inline hri_trng_intflag_reg_t hri_trng_get_INTFLAG_reg(const void *const hw, hri_trng_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_trng_intflag_reg_t hri_trng_read_INTFLAG_reg(const void *const hw) +{ + return ((Trng *)hw)->INTFLAG.reg; +} + +static inline void hri_trng_clear_INTFLAG_reg(const void *const hw, hri_trng_intflag_reg_t mask) +{ + ((Trng *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_trng_set_INTEN_DATARDY_bit(const void *const hw) +{ + ((Trng *)hw)->INTENSET.reg = TRNG_INTENSET_DATARDY; +} + +static inline bool hri_trng_get_INTEN_DATARDY_bit(const void *const hw) +{ + return (((Trng *)hw)->INTENSET.reg & TRNG_INTENSET_DATARDY) >> TRNG_INTENSET_DATARDY_Pos; +} + +static inline void hri_trng_write_INTEN_DATARDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Trng *)hw)->INTENCLR.reg = TRNG_INTENSET_DATARDY; + } else { + ((Trng *)hw)->INTENSET.reg = TRNG_INTENSET_DATARDY; + } +} + +static inline void hri_trng_clear_INTEN_DATARDY_bit(const void *const hw) +{ + ((Trng *)hw)->INTENCLR.reg = TRNG_INTENSET_DATARDY; +} + +static inline void hri_trng_set_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask) +{ + ((Trng *)hw)->INTENSET.reg = mask; +} + +static inline hri_trng_intenset_reg_t hri_trng_get_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_trng_intenset_reg_t hri_trng_read_INTEN_reg(const void *const hw) +{ + return ((Trng *)hw)->INTENSET.reg; +} + +static inline void hri_trng_write_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t data) +{ + ((Trng *)hw)->INTENSET.reg = data; + ((Trng *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_trng_clear_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask) +{ + ((Trng *)hw)->INTENCLR.reg = mask; +} + +static inline hri_trng_data_reg_t hri_trng_get_DATA_DATA_bf(const void *const hw, hri_trng_data_reg_t mask) +{ + return (((Trng *)hw)->DATA.reg & TRNG_DATA_DATA(mask)) >> TRNG_DATA_DATA_Pos; +} + +static inline hri_trng_data_reg_t hri_trng_read_DATA_DATA_bf(const void *const hw) +{ + return (((Trng *)hw)->DATA.reg & TRNG_DATA_DATA_Msk) >> TRNG_DATA_DATA_Pos; +} + +static inline hri_trng_data_reg_t hri_trng_get_DATA_reg(const void *const hw, hri_trng_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Trng *)hw)->DATA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_trng_data_reg_t hri_trng_read_DATA_reg(const void *const hw) +{ + return ((Trng *)hw)->DATA.reg; +} + +static inline void hri_trng_set_CTRLA_ENABLE_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg |= TRNG_CTRLA_ENABLE; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_trng_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->CTRLA.reg; + tmp = (tmp & TRNG_CTRLA_ENABLE) >> TRNG_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_trng_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TRNG_CRITICAL_SECTION_ENTER(); + tmp = ((Trng *)hw)->CTRLA.reg; + tmp &= ~TRNG_CTRLA_ENABLE; + tmp |= value << TRNG_CTRLA_ENABLE_Pos; + ((Trng *)hw)->CTRLA.reg = tmp; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg &= ~TRNG_CTRLA_ENABLE; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg ^= TRNG_CTRLA_ENABLE; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg |= TRNG_CTRLA_RUNSTDBY; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_trng_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->CTRLA.reg; + tmp = (tmp & TRNG_CTRLA_RUNSTDBY) >> TRNG_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_trng_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TRNG_CRITICAL_SECTION_ENTER(); + tmp = ((Trng *)hw)->CTRLA.reg; + tmp &= ~TRNG_CTRLA_RUNSTDBY; + tmp |= value << TRNG_CTRLA_RUNSTDBY_Pos; + ((Trng *)hw)->CTRLA.reg = tmp; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg &= ~TRNG_CTRLA_RUNSTDBY; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg ^= TRNG_CTRLA_RUNSTDBY; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_set_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg |= mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_trng_ctrla_reg_t hri_trng_get_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_trng_write_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t data) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg = data; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_clear_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg &= ~mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_toggle_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg ^= mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_trng_ctrla_reg_t hri_trng_read_CTRLA_reg(const void *const hw) +{ + return ((Trng *)hw)->CTRLA.reg; +} + +static inline void hri_trng_set_EVCTRL_DATARDYEO_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg |= TRNG_EVCTRL_DATARDYEO; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_trng_get_EVCTRL_DATARDYEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->EVCTRL.reg; + tmp = (tmp & TRNG_EVCTRL_DATARDYEO) >> TRNG_EVCTRL_DATARDYEO_Pos; + return (bool)tmp; +} + +static inline void hri_trng_write_EVCTRL_DATARDYEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TRNG_CRITICAL_SECTION_ENTER(); + tmp = ((Trng *)hw)->EVCTRL.reg; + tmp &= ~TRNG_EVCTRL_DATARDYEO; + tmp |= value << TRNG_EVCTRL_DATARDYEO_Pos; + ((Trng *)hw)->EVCTRL.reg = tmp; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_clear_EVCTRL_DATARDYEO_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg &= ~TRNG_EVCTRL_DATARDYEO; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_toggle_EVCTRL_DATARDYEO_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg ^= TRNG_EVCTRL_DATARDYEO; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_set_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg |= mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_trng_evctrl_reg_t hri_trng_get_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_trng_write_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t data) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg = data; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_clear_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg &= ~mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_toggle_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg ^= mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_trng_evctrl_reg_t hri_trng_read_EVCTRL_reg(const void *const hw) +{ + return ((Trng *)hw)->EVCTRL.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_TRNG_L21_H_INCLUDED */ +#endif /* _SAML21_TRNG_COMPONENT_ */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_usb_l21.h b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_usb_l21.h new file mode 100644 index 00000000..40d2a846 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_usb_l21.h @@ -0,0 +1,9335 @@ +/** + * \file + * + * \brief SAM USB + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_USB_COMPONENT_ +#ifndef _HRI_USB_L21_H_INCLUDED_ +#define _HRI_USB_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_USB_CRITICAL_SECTIONS) +#define USB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define USB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define USB_CRITICAL_SECTION_ENTER() +#define USB_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_usb_padcal_reg_t; +typedef uint16_t hri_usbdesc_bank_ctrl_pipe_reg_t; +typedef uint16_t hri_usbdesc_bank_extreg_reg_t; +typedef uint16_t hri_usbdesc_bank_status_pipe_reg_t; +typedef uint16_t hri_usbdescriptordevice_extreg_reg_t; +typedef uint16_t hri_usbdescriptorhost_ctrl_pipe_reg_t; +typedef uint16_t hri_usbdescriptorhost_extreg_reg_t; +typedef uint16_t hri_usbdescriptorhost_status_pipe_reg_t; +typedef uint16_t hri_usbdevice_ctrlb_reg_t; +typedef uint16_t hri_usbdevice_epintsmry_reg_t; +typedef uint16_t hri_usbdevice_fnum_reg_t; +typedef uint16_t hri_usbdevice_intenset_reg_t; +typedef uint16_t hri_usbdevice_intflag_reg_t; +typedef uint16_t hri_usbhost_ctrlb_reg_t; +typedef uint16_t hri_usbhost_fnum_reg_t; +typedef uint16_t hri_usbhost_intenset_reg_t; +typedef uint16_t hri_usbhost_intflag_reg_t; +typedef uint16_t hri_usbhost_pintsmry_reg_t; +typedef uint32_t hri_usb_descadd_reg_t; +typedef uint32_t hri_usbdesc_bank_addr_reg_t; +typedef uint32_t hri_usbdesc_bank_pcksize_reg_t; +typedef uint32_t hri_usbdescriptordevice_addr_reg_t; +typedef uint32_t hri_usbdescriptordevice_pcksize_reg_t; +typedef uint32_t hri_usbdescriptorhost_addr_reg_t; +typedef uint32_t hri_usbdescriptorhost_pcksize_reg_t; +typedef uint8_t hri_usb_ctrla_reg_t; +typedef uint8_t hri_usb_fsmstatus_reg_t; +typedef uint8_t hri_usb_qosctrl_reg_t; +typedef uint8_t hri_usb_syncbusy_reg_t; +typedef uint8_t hri_usbdesc_bank_status_bk_reg_t; +typedef uint8_t hri_usbdescriptordevice_status_bk_reg_t; +typedef uint8_t hri_usbdescriptorhost_status_bk_reg_t; +typedef uint8_t hri_usbdevice_dadd_reg_t; +typedef uint8_t hri_usbdevice_epcfg_reg_t; +typedef uint8_t hri_usbdevice_epintenset_reg_t; +typedef uint8_t hri_usbdevice_epintflag_reg_t; +typedef uint8_t hri_usbdevice_epstatus_reg_t; +typedef uint8_t hri_usbdevice_status_reg_t; +typedef uint8_t hri_usbendpoint_epcfg_reg_t; +typedef uint8_t hri_usbendpoint_epintenset_reg_t; +typedef uint8_t hri_usbendpoint_epintflag_reg_t; +typedef uint8_t hri_usbendpoint_epstatus_reg_t; +typedef uint8_t hri_usbhost_binterval_reg_t; +typedef uint8_t hri_usbhost_flenhigh_reg_t; +typedef uint8_t hri_usbhost_hsofc_reg_t; +typedef uint8_t hri_usbhost_pcfg_reg_t; +typedef uint8_t hri_usbhost_pintenset_reg_t; +typedef uint8_t hri_usbhost_pintflag_reg_t; +typedef uint8_t hri_usbhost_pstatus_reg_t; +typedef uint8_t hri_usbhost_status_reg_t; +typedef uint8_t hri_usbpipe_binterval_reg_t; +typedef uint8_t hri_usbpipe_pcfg_reg_t; +typedef uint8_t hri_usbpipe_pintenset_reg_t; +typedef uint8_t hri_usbpipe_pintflag_reg_t; +typedef uint8_t hri_usbpipe_pstatus_reg_t; + +static inline void hri_usb_wait_for_sync(const void *const hw, hri_usb_syncbusy_reg_t reg) +{ + while (((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_usb_is_syncing(const void *const hw, hri_usb_syncbusy_reg_t reg) +{ + return ((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg; +} + +static inline bool hri_usbpipe_get_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) + >> USB_HOST_PINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; +} + +static inline bool hri_usbpipe_get_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) + >> USB_HOST_PINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; +} + +static inline bool hri_usbpipe_get_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) + >> USB_HOST_PINTFLAG_TRFAIL_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; +} + +static inline bool hri_usbpipe_get_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) + >> USB_HOST_PINTFLAG_PERR_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; +} + +static inline bool hri_usbpipe_get_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) + >> USB_HOST_PINTFLAG_TXSTP_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; +} + +static inline bool hri_usbpipe_get_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) + >> USB_HOST_PINTFLAG_STALL_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; +} + +static inline bool hri_usbpipe_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) + >> USB_HOST_PINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; +} + +static inline bool hri_usbpipe_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) + >> USB_HOST_PINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; +} + +static inline bool hri_usbpipe_get_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) + >> USB_HOST_PINTFLAG_TRFAIL_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; +} + +static inline bool hri_usbpipe_get_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) + >> USB_HOST_PINTFLAG_PERR_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; +} + +static inline bool hri_usbpipe_get_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) + >> USB_HOST_PINTFLAG_TXSTP_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; +} + +static inline bool hri_usbpipe_get_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) + >> USB_HOST_PINTFLAG_STALL_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; +} + +static inline hri_usbpipe_pintflag_reg_t hri_usbpipe_get_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbpipe_pintflag_reg_t hri_usbpipe_read_PINTFLAG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg; +} + +static inline void hri_usbpipe_clear_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintflag_reg_t mask) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = mask; +} + +static inline void hri_usbpipe_set_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; +} + +static inline bool hri_usbpipe_get_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_DTGL) + >> USB_HOST_PSTATUS_DTGL_Pos; +} + +static inline void hri_usbpipe_write_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; + } +} + +static inline void hri_usbpipe_clear_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; +} + +static inline void hri_usbpipe_set_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; +} + +static inline bool hri_usbpipe_get_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_CURBK) + >> USB_HOST_PSTATUS_CURBK_Pos; +} + +static inline void hri_usbpipe_write_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; + } +} + +static inline void hri_usbpipe_clear_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; +} + +static inline void hri_usbpipe_set_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; +} + +static inline bool hri_usbpipe_get_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_PFREEZE) + >> USB_HOST_PSTATUS_PFREEZE_Pos; +} + +static inline void hri_usbpipe_write_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; + } +} + +static inline void hri_usbpipe_clear_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; +} + +static inline void hri_usbpipe_set_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; +} + +static inline bool hri_usbpipe_get_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK0RDY) + >> USB_HOST_PSTATUS_BK0RDY_Pos; +} + +static inline void hri_usbpipe_write_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; + } +} + +static inline void hri_usbpipe_clear_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; +} + +static inline void hri_usbpipe_set_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; +} + +static inline bool hri_usbpipe_get_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK1RDY) + >> USB_HOST_PSTATUS_BK1RDY_Pos; +} + +static inline void hri_usbpipe_write_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; + } +} + +static inline void hri_usbpipe_clear_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; +} + +static inline void hri_usbpipe_set_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pstatus_reg_t mask) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = mask; +} + +static inline hri_usbpipe_pstatus_reg_t hri_usbpipe_get_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbpipe_pstatus_reg_t hri_usbpipe_read_PSTATUS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg; +} + +static inline void hri_usbpipe_write_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pstatus_reg_t data) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = data; + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = ~data; +} + +static inline void hri_usbpipe_clear_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pstatus_reg_t mask) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = mask; +} + +static inline void hri_usbpipe_set_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; +} + +static inline bool hri_usbpipe_get_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT0) + >> USB_HOST_PINTENSET_TRCPT0_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; + } +} + +static inline void hri_usbpipe_clear_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; +} + +static inline void hri_usbpipe_set_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; +} + +static inline bool hri_usbpipe_get_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT1) + >> USB_HOST_PINTENSET_TRCPT1_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; + } +} + +static inline void hri_usbpipe_clear_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; +} + +static inline void hri_usbpipe_set_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; +} + +static inline bool hri_usbpipe_get_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRFAIL) + >> USB_HOST_PINTENSET_TRFAIL_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; + } +} + +static inline void hri_usbpipe_clear_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; +} + +static inline void hri_usbpipe_set_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; +} + +static inline bool hri_usbpipe_get_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_PERR) + >> USB_HOST_PINTENSET_PERR_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; + } +} + +static inline void hri_usbpipe_clear_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; +} + +static inline void hri_usbpipe_set_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; +} + +static inline bool hri_usbpipe_get_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TXSTP) + >> USB_HOST_PINTENSET_TXSTP_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; + } +} + +static inline void hri_usbpipe_clear_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; +} + +static inline void hri_usbpipe_set_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; +} + +static inline bool hri_usbpipe_get_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_STALL) + >> USB_HOST_PINTENSET_STALL_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; + } +} + +static inline void hri_usbpipe_clear_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; +} + +static inline void hri_usbpipe_set_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintenset_reg_t mask) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = mask; +} + +static inline hri_usbpipe_pintenset_reg_t hri_usbpipe_get_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbpipe_pintenset_reg_t hri_usbpipe_read_PINTEN_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg; +} + +static inline void hri_usbpipe_write_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintenset_reg_t data) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = data; + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = ~data; +} + +static inline void hri_usbpipe_clear_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintenset_reg_t mask) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = mask; +} + +static inline void hri_usbpipe_set_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbpipe_get_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_BK) >> USB_HOST_PCFG_BK_Pos; + return (bool)tmp; +} + +static inline void hri_usbpipe_write_PCFG_BK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_BK; + tmp |= value << USB_HOST_PCFG_BK_Pos; + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_set_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTOKEN(mask)) >> USB_HOST_PCFG_PTOKEN_Pos; + return tmp; +} + +static inline void hri_usbpipe_write_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_PTOKEN_Msk; + tmp |= USB_HOST_PCFG_PTOKEN(data); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTOKEN_Msk) >> USB_HOST_PCFG_PTOKEN_Pos; + return tmp; +} + +static inline void hri_usbpipe_set_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTYPE(mask)) >> USB_HOST_PCFG_PTYPE_Pos; + return tmp; +} + +static inline void hri_usbpipe_write_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_PTYPE_Msk; + tmp |= USB_HOST_PCFG_PTYPE(data); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTYPE_Msk) >> USB_HOST_PCFG_PTYPE_Pos; + return tmp; +} + +static inline void hri_usbpipe_set_PCFG_reg(const void *const hw, uint8_t submodule_index, hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbpipe_write_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; +} + +static inline void hri_usbpipe_set_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg |= USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_binterval_reg_t hri_usbpipe_get_BINTERVAL_BITINTERVAL_bf(const void *const hw, + uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; + tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL(mask)) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; + return tmp; +} + +static inline void hri_usbpipe_write_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; + tmp &= ~USB_HOST_BINTERVAL_BITINTERVAL_Msk; + tmp |= USB_HOST_BINTERVAL_BITINTERVAL(data); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg &= ~USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg ^= USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_binterval_reg_t hri_usbpipe_read_BINTERVAL_BITINTERVAL_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; + tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL_Msk) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; + return tmp; +} + +static inline void hri_usbpipe_set_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_binterval_reg_t hri_usbpipe_get_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbpipe_write_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_binterval_reg_t hri_usbpipe_read_BINTERVAL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; +} + +static inline bool hri_usbhost_get_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) + >> USB_HOST_PINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; +} + +static inline bool hri_usbhost_get_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) + >> USB_HOST_PINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; +} + +static inline bool hri_usbhost_get_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) + >> USB_HOST_PINTFLAG_TRFAIL_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; +} + +static inline bool hri_usbhost_get_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) + >> USB_HOST_PINTFLAG_PERR_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; +} + +static inline bool hri_usbhost_get_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) + >> USB_HOST_PINTFLAG_TXSTP_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; +} + +static inline bool hri_usbhost_get_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) + >> USB_HOST_PINTFLAG_STALL_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; +} + +static inline bool hri_usbhost_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) + >> USB_HOST_PINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbhost_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; +} + +static inline bool hri_usbhost_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) + >> USB_HOST_PINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbhost_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; +} + +static inline bool hri_usbhost_get_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) + >> USB_HOST_PINTFLAG_TRFAIL_Pos; +} + +static inline void hri_usbhost_clear_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; +} + +static inline bool hri_usbhost_get_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) + >> USB_HOST_PINTFLAG_PERR_Pos; +} + +static inline void hri_usbhost_clear_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; +} + +static inline bool hri_usbhost_get_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) + >> USB_HOST_PINTFLAG_TXSTP_Pos; +} + +static inline void hri_usbhost_clear_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; +} + +static inline bool hri_usbhost_get_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) + >> USB_HOST_PINTFLAG_STALL_Pos; +} + +static inline void hri_usbhost_clear_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; +} + +static inline hri_usbhost_pintflag_reg_t hri_usbhost_get_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_pintflag_reg_t hri_usbhost_read_PINTFLAG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg; +} + +static inline void hri_usbhost_clear_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintflag_reg_t mask) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = mask; +} + +static inline void hri_usbhost_set_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; +} + +static inline bool hri_usbhost_get_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_DTGL) + >> USB_HOST_PSTATUS_DTGL_Pos; +} + +static inline void hri_usbhost_write_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; + } +} + +static inline void hri_usbhost_clear_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; +} + +static inline void hri_usbhost_set_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; +} + +static inline bool hri_usbhost_get_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_CURBK) + >> USB_HOST_PSTATUS_CURBK_Pos; +} + +static inline void hri_usbhost_write_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; + } +} + +static inline void hri_usbhost_clear_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; +} + +static inline void hri_usbhost_set_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; +} + +static inline bool hri_usbhost_get_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_PFREEZE) + >> USB_HOST_PSTATUS_PFREEZE_Pos; +} + +static inline void hri_usbhost_write_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; + } +} + +static inline void hri_usbhost_clear_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; +} + +static inline void hri_usbhost_set_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; +} + +static inline bool hri_usbhost_get_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK0RDY) + >> USB_HOST_PSTATUS_BK0RDY_Pos; +} + +static inline void hri_usbhost_write_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; + } +} + +static inline void hri_usbhost_clear_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; +} + +static inline void hri_usbhost_set_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; +} + +static inline bool hri_usbhost_get_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK1RDY) + >> USB_HOST_PSTATUS_BK1RDY_Pos; +} + +static inline void hri_usbhost_write_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; + } +} + +static inline void hri_usbhost_clear_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; +} + +static inline void hri_usbhost_set_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pstatus_reg_t mask) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = mask; +} + +static inline hri_usbhost_pstatus_reg_t hri_usbhost_get_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_pstatus_reg_t hri_usbhost_read_PSTATUS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg; +} + +static inline void hri_usbhost_write_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pstatus_reg_t data) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = data; + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = ~data; +} + +static inline void hri_usbhost_clear_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pstatus_reg_t mask) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = mask; +} + +static inline void hri_usbhost_set_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; +} + +static inline bool hri_usbhost_get_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT0) + >> USB_HOST_PINTENSET_TRCPT0_Pos; +} + +static inline void hri_usbhost_write_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; + } +} + +static inline void hri_usbhost_clear_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; +} + +static inline void hri_usbhost_set_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; +} + +static inline bool hri_usbhost_get_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT1) + >> USB_HOST_PINTENSET_TRCPT1_Pos; +} + +static inline void hri_usbhost_write_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; + } +} + +static inline void hri_usbhost_clear_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; +} + +static inline void hri_usbhost_set_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; +} + +static inline bool hri_usbhost_get_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRFAIL) + >> USB_HOST_PINTENSET_TRFAIL_Pos; +} + +static inline void hri_usbhost_write_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; + } +} + +static inline void hri_usbhost_clear_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; +} + +static inline void hri_usbhost_set_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; +} + +static inline bool hri_usbhost_get_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_PERR) + >> USB_HOST_PINTENSET_PERR_Pos; +} + +static inline void hri_usbhost_write_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; + } +} + +static inline void hri_usbhost_clear_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; +} + +static inline void hri_usbhost_set_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; +} + +static inline bool hri_usbhost_get_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TXSTP) + >> USB_HOST_PINTENSET_TXSTP_Pos; +} + +static inline void hri_usbhost_write_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; + } +} + +static inline void hri_usbhost_clear_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; +} + +static inline void hri_usbhost_set_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; +} + +static inline bool hri_usbhost_get_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_STALL) + >> USB_HOST_PINTENSET_STALL_Pos; +} + +static inline void hri_usbhost_write_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; + } +} + +static inline void hri_usbhost_clear_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; +} + +static inline void hri_usbhost_set_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintenset_reg_t mask) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = mask; +} + +static inline hri_usbhost_pintenset_reg_t hri_usbhost_get_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_pintenset_reg_t hri_usbhost_read_PINTEN_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg; +} + +static inline void hri_usbhost_write_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintenset_reg_t data) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = data; + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = ~data; +} + +static inline void hri_usbhost_clear_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintenset_reg_t mask) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = mask; +} + +static inline void hri_usbhost_set_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_BK) >> USB_HOST_PCFG_BK_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_PCFG_BK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_BK; + tmp |= value << USB_HOST_PCFG_BK_Pos; + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTOKEN(mask)) >> USB_HOST_PCFG_PTOKEN_Pos; + return tmp; +} + +static inline void hri_usbhost_write_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_PTOKEN_Msk; + tmp |= USB_HOST_PCFG_PTOKEN(data); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTOKEN_Msk) >> USB_HOST_PCFG_PTOKEN_Pos; + return tmp; +} + +static inline void hri_usbhost_set_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTYPE(mask)) >> USB_HOST_PCFG_PTYPE_Pos; + return tmp; +} + +static inline void hri_usbhost_write_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_PTYPE_Msk; + tmp |= USB_HOST_PCFG_PTYPE(data); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTYPE_Msk) >> USB_HOST_PCFG_PTYPE_Pos; + return tmp; +} + +static inline void hri_usbhost_set_PCFG_reg(const void *const hw, uint8_t submodule_index, hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; +} + +static inline void hri_usbhost_set_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg |= USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_binterval_reg_t hri_usbhost_get_BINTERVAL_BITINTERVAL_bf(const void *const hw, + uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; + tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL(mask)) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; + return tmp; +} + +static inline void hri_usbhost_write_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; + tmp &= ~USB_HOST_BINTERVAL_BITINTERVAL_Msk; + tmp |= USB_HOST_BINTERVAL_BITINTERVAL(data); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg &= ~USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg ^= USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_binterval_reg_t hri_usbhost_read_BINTERVAL_BITINTERVAL_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; + tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL_Msk) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; + return tmp; +} + +static inline void hri_usbhost_set_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_binterval_reg_t hri_usbhost_get_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_binterval_reg_t hri_usbhost_read_BINTERVAL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; +} + +static inline void hri_usbhostdescbank_set_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg |= USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_get_ADDR_ADDR_bf(const void *const hw, + hri_usbdesc_bank_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->ADDR.reg; + tmp = (tmp & USB_HOST_ADDR_ADDR(mask)) >> USB_HOST_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->ADDR.reg; + tmp &= ~USB_HOST_ADDR_ADDR_Msk; + tmp |= USB_HOST_ADDR_ADDR(data); + ((UsbHostDescBank *)hw)->ADDR.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg &= ~USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg ^= USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->ADDR.reg; + tmp = (tmp & USB_HOST_ADDR_ADDR_Msk) >> USB_HOST_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_get_ADDR_reg(const void *const hw, + hri_usbdesc_bank_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_write_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_read_ADDR_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->ADDR.reg; +} + +static inline void hri_usbhostdescbank_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_AUTO_ZLP) >> USB_HOST_PCKSIZE_AUTO_ZLP_Pos; + return (bool)tmp; +} + +static inline void hri_usbhostdescbank_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_AUTO_ZLP; + tmp |= value << USB_HOST_PCKSIZE_AUTO_ZLP_Pos; + ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbhostdescbank_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT(mask)) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_BYTE_COUNT_Msk; + tmp |= USB_HOST_PCKSIZE_BYTE_COUNT(data); + ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT_Msk) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbhostdescbank_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk; + tmp |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(data); + ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbhostdescbank_get_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_SIZE(mask)) >> USB_HOST_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_SIZE_Msk; + tmp |= USB_HOST_PCKSIZE_SIZE(data); + ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_SIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_SIZE_Msk) >> USB_HOST_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_get_PCKSIZE_reg(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_write_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->PCKSIZE.reg; +} + +static inline void hri_usbhostdescbank_set_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg |= USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_get_EXTREG_SUBPID_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_SUBPID(mask)) >> USB_HOST_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp &= ~USB_HOST_EXTREG_SUBPID_Msk; + tmp |= USB_HOST_EXTREG_SUBPID(data); + ((UsbHostDescBank *)hw)->EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg &= ~USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg ^= USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_SUBPID_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_SUBPID_Msk) >> USB_HOST_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg |= USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t +hri_usbhostdescbank_get_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_VARIABLE(mask)) >> USB_HOST_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp &= ~USB_HOST_EXTREG_VARIABLE_Msk; + tmp |= USB_HOST_EXTREG_VARIABLE(data); + ((UsbHostDescBank *)hw)->EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg &= ~USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg ^= USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_VARIABLE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_VARIABLE_Msk) >> USB_HOST_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_get_EXTREG_reg(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_write_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->EXTREG.reg; +} + +static inline void hri_usbhostdescbank_set_CTRL_PIPE_PDADDR_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t +hri_usbhostdescbank_get_CTRL_PIPE_PDADDR_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR(mask)) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_CTRL_PIPE_PDADDR_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PDADDR_Msk; + tmp |= USB_HOST_CTRL_PIPE_PDADDR(data); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PDADDR_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PDADDR_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PDADDR_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR_Msk) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_CTRL_PIPE_PEPNUM_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t +hri_usbhostdescbank_get_CTRL_PIPE_PEPNUM_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM(mask)) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_CTRL_PIPE_PEPNUM_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PEPNUM_Msk; + tmp |= USB_HOST_CTRL_PIPE_PEPNUM(data); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PEPNUM_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PEPNUM_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PEPNUM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM_Msk) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_CTRL_PIPE_PERMAX_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t +hri_usbhostdescbank_get_CTRL_PIPE_PERMAX_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX(mask)) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_CTRL_PIPE_PERMAX_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PERMAX_Msk; + tmp |= USB_HOST_CTRL_PIPE_PERMAX(data); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PERMAX_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PERMAX_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PERMAX_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX_Msk) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t +hri_usbhostdescbank_get_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_write_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; +} + +static inline bool hri_usbhostdescbank_get_STATUS_BK_CRCERR_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_BK.reg & USB_HOST_STATUS_BK_CRCERR) >> USB_HOST_STATUS_BK_CRCERR_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_BK_CRCERR_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_BK.reg = USB_HOST_STATUS_BK_CRCERR; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_STATUS_BK_ERRORFLOW_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_BK.reg & USB_HOST_STATUS_BK_ERRORFLOW) >> USB_HOST_STATUS_BK_ERRORFLOW_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_BK.reg = USB_HOST_STATUS_BK_ERRORFLOW; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_bk_reg_t +hri_usbhostdescbank_get_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHostDescBank *)hw)->STATUS_BK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_clear_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_BK.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_bk_reg_t hri_usbhostdescbank_read_STATUS_BK_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->STATUS_BK.reg; +} + +static inline bool hri_usbhostdescbank_get_STATUS_PIPE_DTGLER_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DTGLER) >> USB_HOST_STATUS_PIPE_DTGLER_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_DTGLER_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DTGLER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_STATUS_PIPE_DAPIDER_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DAPIDER) + >> USB_HOST_STATUS_PIPE_DAPIDER_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_DAPIDER_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DAPIDER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_STATUS_PIPE_PIDER_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_PIDER) >> USB_HOST_STATUS_PIPE_PIDER_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_PIDER_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_PIDER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_STATUS_PIPE_TOUTER_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_TOUTER) >> USB_HOST_STATUS_PIPE_TOUTER_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_TOUTER_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_TOUTER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_STATUS_PIPE_CRC16ER_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_CRC16ER) + >> USB_HOST_STATUS_PIPE_CRC16ER_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_CRC16ER_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_CRC16ER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_pipe_reg_t +hri_usbhostdescbank_get_STATUS_PIPE_ERCNT_bf(const void *const hw, hri_usbdesc_bank_status_pipe_reg_t mask) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT(mask)) + >> USB_HOST_STATUS_PIPE_ERCNT_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_ERCNT_bf(const void *const hw, + hri_usbdesc_bank_status_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_ERCNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_pipe_reg_t hri_usbhostdescbank_read_STATUS_PIPE_ERCNT_bf(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT_Msk) + >> USB_HOST_STATUS_PIPE_ERCNT_Pos; +} + +static inline hri_usbdesc_bank_status_pipe_reg_t +hri_usbhostdescbank_get_STATUS_PIPE_reg(const void *const hw, hri_usbdesc_bank_status_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->STATUS_PIPE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_reg(const void *const hw, + hri_usbdesc_bank_status_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_pipe_reg_t hri_usbhostdescbank_read_STATUS_PIPE_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->STATUS_PIPE.reg; +} + +static inline void hri_usbhostdescriptor_set_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg |= USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_addr_reg_t +hri_usbhostdescriptor_get_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; + tmp = (tmp & USB_HOST_ADDR_ADDR(mask)) >> USB_HOST_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; + tmp &= ~USB_HOST_ADDR_ADDR_Msk; + tmp |= USB_HOST_ADDR_ADDR(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg &= ~USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg ^= USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_addr_reg_t hri_usbhostdescriptor_read_ADDR_ADDR_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; + tmp = (tmp & USB_HOST_ADDR_ADDR_Msk) >> USB_HOST_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_addr_reg_t +hri_usbhostdescriptor_get_ADDR_reg(const void *const hw, uint8_t submodule_index, hri_usbdescriptorhost_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_addr_reg_t hri_usbhostdescriptor_read_ADDR_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; +} + +static inline void hri_usbhostdescriptor_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_AUTO_ZLP) >> USB_HOST_PCKSIZE_AUTO_ZLP_Pos; + return (bool)tmp; +} + +static inline void hri_usbhostdescriptor_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_AUTO_ZLP; + tmp |= value << USB_HOST_PCKSIZE_AUTO_ZLP_Pos; + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t +hri_usbhostdescriptor_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT(mask)) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_BYTE_COUNT_Msk; + tmp |= USB_HOST_PCKSIZE_BYTE_COUNT(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t +hri_usbhostdescriptor_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT_Msk) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t +hri_usbhostdescriptor_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk; + tmp |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t +hri_usbhostdescriptor_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t +hri_usbhostdescriptor_get_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_SIZE(mask)) >> USB_HOST_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_SIZE_Msk; + tmp |= USB_HOST_PCKSIZE_SIZE(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t hri_usbhostdescriptor_read_PCKSIZE_SIZE_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_SIZE_Msk) >> USB_HOST_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t +hri_usbhostdescriptor_get_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t hri_usbhostdescriptor_read_PCKSIZE_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; +} + +static inline void hri_usbhostdescriptor_set_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_extreg_reg_t +hri_usbhostdescriptor_get_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_SUBPID(mask)) >> USB_HOST_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp &= ~USB_HOST_EXTREG_SUBPID_Msk; + tmp |= USB_HOST_EXTREG_SUBPID(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_SUBPID_bf(const void *const hw, + uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_SUBPID_Msk) >> USB_HOST_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_extreg_reg_t +hri_usbhostdescriptor_get_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_VARIABLE(mask)) >> USB_HOST_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp &= ~USB_HOST_EXTREG_VARIABLE_Msk; + tmp |= USB_HOST_EXTREG_VARIABLE(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_VARIABLE_bf(const void *const hw, + uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_VARIABLE_Msk) >> USB_HOST_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_extreg_reg_t +hri_usbhostdescriptor_get_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; +} + +static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t +hri_usbhostdescriptor_get_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR(mask)) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PDADDR_Msk; + tmp |= USB_HOST_CTRL_PIPE_PDADDR(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t +hri_usbhostdescriptor_read_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR_Msk) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t +hri_usbhostdescriptor_get_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM(mask)) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PEPNUM_Msk; + tmp |= USB_HOST_CTRL_PIPE_PEPNUM(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t +hri_usbhostdescriptor_read_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM_Msk) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t +hri_usbhostdescriptor_get_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX(mask)) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PERMAX_Msk; + tmp |= USB_HOST_CTRL_PIPE_PERMAX(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t +hri_usbhostdescriptor_read_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX_Msk) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t +hri_usbhostdescriptor_get_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t hri_usbhostdescriptor_read_CTRL_PIPE_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; +} + +static inline bool hri_usbhostdescriptor_get_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg & USB_HOST_STATUS_BK_CRCERR) + >> USB_HOST_STATUS_BK_CRCERR_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = USB_HOST_STATUS_BK_CRCERR; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg & USB_HOST_STATUS_BK_ERRORFLOW) + >> USB_HOST_STATUS_BK_ERRORFLOW_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = USB_HOST_STATUS_BK_ERRORFLOW; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_status_bk_reg_t +hri_usbhostdescriptor_get_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_status_bk_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_status_bk_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_status_bk_reg_t hri_usbhostdescriptor_read_STATUS_BK_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg; +} + +static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_DTGLER_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DTGLER) + >> USB_HOST_STATUS_PIPE_DTGLER_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_DTGLER_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DTGLER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_DAPIDER_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DAPIDER) + >> USB_HOST_STATUS_PIPE_DAPIDER_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_DAPIDER_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DAPIDER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_PIDER_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_PIDER) + >> USB_HOST_STATUS_PIPE_PIDER_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_PIDER_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_PIDER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_TOUTER_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_TOUTER) + >> USB_HOST_STATUS_PIPE_TOUTER_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_TOUTER_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_TOUTER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_CRC16ER_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_CRC16ER) + >> USB_HOST_STATUS_PIPE_CRC16ER_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_CRC16ER_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_CRC16ER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_status_pipe_reg_t +hri_usbhostdescriptor_get_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_status_pipe_reg_t mask) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT(mask)) + >> USB_HOST_STATUS_PIPE_ERCNT_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_status_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_ERCNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_status_pipe_reg_t +hri_usbhostdescriptor_read_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT_Msk) + >> USB_HOST_STATUS_PIPE_ERCNT_Pos; +} + +static inline hri_usbdescriptorhost_status_pipe_reg_t +hri_usbhostdescriptor_get_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_status_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_status_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_status_pipe_reg_t +hri_usbhostdescriptor_read_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) + >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) + >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) + >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) + >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) + >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) + >> USB_DEVICE_EPINTFLAG_STALL0_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) + >> USB_DEVICE_EPINTFLAG_STALL1_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; +} + +static inline bool hri_usbendpoint_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) + >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; +} + +static inline bool hri_usbendpoint_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) + >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; +} + +static inline bool hri_usbendpoint_get_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) + >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; +} + +static inline bool hri_usbendpoint_get_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) + >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; +} + +static inline bool hri_usbendpoint_get_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) + >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; +} + +static inline bool hri_usbendpoint_get_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) + >> USB_DEVICE_EPINTFLAG_STALL0_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; +} + +static inline bool hri_usbendpoint_get_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) + >> USB_DEVICE_EPINTFLAG_STALL1_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; +} + +static inline hri_usbendpoint_epintflag_reg_t +hri_usbendpoint_get_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbendpoint_epintflag_reg_t hri_usbendpoint_read_EPINTFLAG_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epintflag_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = mask; +} + +static inline void hri_usbendpoint_set_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLOUT) + >> USB_DEVICE_EPSTATUS_DTGLOUT_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; +} + +static inline void hri_usbendpoint_set_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLIN) + >> USB_DEVICE_EPSTATUS_DTGLIN_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; +} + +static inline void hri_usbendpoint_set_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_CURBK) + >> USB_DEVICE_EPSTATUS_CURBK_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; +} + +static inline void hri_usbendpoint_set_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ0) + >> USB_DEVICE_EPSTATUS_STALLRQ0_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; +} + +static inline void hri_usbendpoint_set_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ1) + >> USB_DEVICE_EPSTATUS_STALLRQ1_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; +} + +static inline void hri_usbendpoint_set_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK0RDY) + >> USB_DEVICE_EPSTATUS_BK0RDY_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; +} + +static inline void hri_usbendpoint_set_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK1RDY) + >> USB_DEVICE_EPSTATUS_BK1RDY_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; +} + +static inline void hri_usbendpoint_set_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epstatus_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = mask; +} + +static inline hri_usbendpoint_epstatus_reg_t +hri_usbendpoint_get_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbendpoint_epstatus_reg_t hri_usbendpoint_read_EPSTATUS_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg; +} + +static inline void hri_usbendpoint_write_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epstatus_reg_t data) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = data; + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = ~data; +} + +static inline void hri_usbendpoint_clear_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epstatus_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = mask; +} + +static inline void hri_usbendpoint_set_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; +} + +static inline bool hri_usbendpoint_get_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT0) + >> USB_DEVICE_EPINTENSET_TRCPT0_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; +} + +static inline void hri_usbendpoint_set_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; +} + +static inline bool hri_usbendpoint_get_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT1) + >> USB_DEVICE_EPINTENSET_TRCPT1_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; +} + +static inline void hri_usbendpoint_set_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; +} + +static inline bool hri_usbendpoint_get_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL0) + >> USB_DEVICE_EPINTENSET_TRFAIL0_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; +} + +static inline void hri_usbendpoint_set_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; +} + +static inline bool hri_usbendpoint_get_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL1) + >> USB_DEVICE_EPINTENSET_TRFAIL1_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; +} + +static inline void hri_usbendpoint_set_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; +} + +static inline bool hri_usbendpoint_get_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_RXSTP) + >> USB_DEVICE_EPINTENSET_RXSTP_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; +} + +static inline void hri_usbendpoint_set_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; +} + +static inline bool hri_usbendpoint_get_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL0) + >> USB_DEVICE_EPINTENSET_STALL0_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; +} + +static inline void hri_usbendpoint_set_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; +} + +static inline bool hri_usbendpoint_get_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL1) + >> USB_DEVICE_EPINTENSET_STALL1_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; +} + +static inline void hri_usbendpoint_set_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epintenset_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = mask; +} + +static inline hri_usbendpoint_epintenset_reg_t +hri_usbendpoint_get_EPINTEN_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbendpoint_epintenset_reg_t hri_usbendpoint_read_EPINTEN_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg; +} + +static inline void hri_usbendpoint_write_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epintenset_reg_t data) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = data; + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = ~data; +} + +static inline void hri_usbendpoint_clear_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epintenset_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = mask; +} + +static inline void hri_usbendpoint_set_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbendpoint_get_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_NYETDIS) >> USB_DEVICE_EPCFG_NYETDIS_Pos; + return (bool)tmp; +} + +static inline void hri_usbendpoint_write_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_NYETDIS; + tmp |= value << USB_DEVICE_EPCFG_NYETDIS_Pos; + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_clear_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_toggle_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_set_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t +hri_usbendpoint_get_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0(mask)) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; + return tmp; +} + +static inline void hri_usbendpoint_write_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk; + tmp |= USB_DEVICE_EPCFG_EPTYPE0(data); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_clear_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_toggle_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_EPTYPE0_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0_Msk) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; + return tmp; +} + +static inline void hri_usbendpoint_set_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t +hri_usbendpoint_get_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1(mask)) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; + return tmp; +} + +static inline void hri_usbendpoint_write_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk; + tmp |= USB_DEVICE_EPCFG_EPTYPE1(data); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_clear_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_toggle_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_EPTYPE1_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1_Msk) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; + return tmp; +} + +static inline void hri_usbendpoint_set_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_get_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbendpoint_write_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_clear_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_toggle_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) + >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) + >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) + >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) + >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) + >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) + >> USB_DEVICE_EPINTFLAG_STALL0_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) + >> USB_DEVICE_EPINTFLAG_STALL1_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; +} + +static inline bool hri_usbdevice_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) + >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; +} + +static inline bool hri_usbdevice_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) + >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; +} + +static inline bool hri_usbdevice_get_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) + >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; +} + +static inline bool hri_usbdevice_get_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) + >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; +} + +static inline bool hri_usbdevice_get_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) + >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; +} + +static inline bool hri_usbdevice_get_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) + >> USB_DEVICE_EPINTFLAG_STALL0_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; +} + +static inline bool hri_usbdevice_get_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) + >> USB_DEVICE_EPINTFLAG_STALL1_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; +} + +static inline hri_usbdevice_epintflag_reg_t +hri_usbdevice_get_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, hri_usbdevice_epintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_epintflag_reg_t hri_usbdevice_read_EPINTFLAG_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epintflag_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = mask; +} + +static inline void hri_usbdevice_set_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; +} + +static inline bool hri_usbdevice_get_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLOUT) + >> USB_DEVICE_EPSTATUS_DTGLOUT_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; +} + +static inline void hri_usbdevice_set_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; +} + +static inline bool hri_usbdevice_get_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLIN) + >> USB_DEVICE_EPSTATUS_DTGLIN_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; +} + +static inline void hri_usbdevice_set_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; +} + +static inline bool hri_usbdevice_get_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_CURBK) + >> USB_DEVICE_EPSTATUS_CURBK_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; +} + +static inline void hri_usbdevice_set_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; +} + +static inline bool hri_usbdevice_get_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ0) + >> USB_DEVICE_EPSTATUS_STALLRQ0_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; +} + +static inline void hri_usbdevice_set_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; +} + +static inline bool hri_usbdevice_get_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ1) + >> USB_DEVICE_EPSTATUS_STALLRQ1_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; +} + +static inline void hri_usbdevice_set_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; +} + +static inline bool hri_usbdevice_get_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK0RDY) + >> USB_DEVICE_EPSTATUS_BK0RDY_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; +} + +static inline void hri_usbdevice_set_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; +} + +static inline bool hri_usbdevice_get_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK1RDY) + >> USB_DEVICE_EPSTATUS_BK1RDY_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; +} + +static inline void hri_usbdevice_set_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epstatus_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = mask; +} + +static inline hri_usbdevice_epstatus_reg_t hri_usbdevice_get_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_epstatus_reg_t hri_usbdevice_read_EPSTATUS_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg; +} + +static inline void hri_usbdevice_write_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epstatus_reg_t data) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = data; + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = ~data; +} + +static inline void hri_usbdevice_clear_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epstatus_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = mask; +} + +static inline void hri_usbdevice_set_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; +} + +static inline bool hri_usbdevice_get_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT0) + >> USB_DEVICE_EPINTENSET_TRCPT0_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; +} + +static inline void hri_usbdevice_set_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; +} + +static inline bool hri_usbdevice_get_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT1) + >> USB_DEVICE_EPINTENSET_TRCPT1_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; +} + +static inline void hri_usbdevice_set_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; +} + +static inline bool hri_usbdevice_get_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL0) + >> USB_DEVICE_EPINTENSET_TRFAIL0_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; +} + +static inline void hri_usbdevice_set_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; +} + +static inline bool hri_usbdevice_get_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL1) + >> USB_DEVICE_EPINTENSET_TRFAIL1_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; +} + +static inline void hri_usbdevice_set_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; +} + +static inline bool hri_usbdevice_get_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_RXSTP) + >> USB_DEVICE_EPINTENSET_RXSTP_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; +} + +static inline void hri_usbdevice_set_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; +} + +static inline bool hri_usbdevice_get_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL0) + >> USB_DEVICE_EPINTENSET_STALL0_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; +} + +static inline void hri_usbdevice_set_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; +} + +static inline bool hri_usbdevice_get_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL1) + >> USB_DEVICE_EPINTENSET_STALL1_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; +} + +static inline void hri_usbdevice_set_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epintenset_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = mask; +} + +static inline hri_usbdevice_epintenset_reg_t +hri_usbdevice_get_EPINTEN_reg(const void *const hw, uint8_t submodule_index, hri_usbdevice_epintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_epintenset_reg_t hri_usbdevice_read_EPINTEN_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg; +} + +static inline void hri_usbdevice_write_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epintenset_reg_t data) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = data; + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = ~data; +} + +static inline void hri_usbdevice_clear_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epintenset_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = mask; +} + +static inline void hri_usbdevice_set_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_NYETDIS) >> USB_DEVICE_EPCFG_NYETDIS_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_NYETDIS; + tmp |= value << USB_DEVICE_EPCFG_NYETDIS_Pos; + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t +hri_usbdevice_get_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, hri_usbdevice_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0(mask)) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk; + tmp |= USB_DEVICE_EPCFG_EPTYPE0(data); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_EPTYPE0_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0_Msk) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t +hri_usbdevice_get_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, hri_usbdevice_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1(mask)) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk; + tmp |= USB_DEVICE_EPCFG_EPTYPE1(data); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_EPTYPE1_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1_Msk) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_get_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevice_write_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; +} + +static inline bool hri_usbdevice_get_INTFLAG_SUSPEND_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SUSPEND) >> USB_DEVICE_INTFLAG_SUSPEND_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_SUSPEND_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SUSPEND; +} + +static inline bool hri_usbdevice_get_INTFLAG_MSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_MSOF) >> USB_DEVICE_INTFLAG_MSOF_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_MSOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MSOF; +} + +static inline bool hri_usbdevice_get_INTFLAG_SOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SOF) >> USB_DEVICE_INTFLAG_SOF_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_SOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF; +} + +static inline bool hri_usbdevice_get_INTFLAG_EORST_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORST) >> USB_DEVICE_INTFLAG_EORST_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_EORST_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST; +} + +static inline bool hri_usbdevice_get_INTFLAG_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_WAKEUP) >> USB_DEVICE_INTFLAG_WAKEUP_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP; +} + +static inline bool hri_usbdevice_get_INTFLAG_EORSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORSM) >> USB_DEVICE_INTFLAG_EORSM_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_EORSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORSM; +} + +static inline bool hri_usbdevice_get_INTFLAG_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_UPRSM) >> USB_DEVICE_INTFLAG_UPRSM_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_UPRSM; +} + +static inline bool hri_usbdevice_get_INTFLAG_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_RAMACER) >> USB_DEVICE_INTFLAG_RAMACER_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_RAMACER; +} + +static inline bool hri_usbdevice_get_INTFLAG_LPMNYET_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMNYET) >> USB_DEVICE_INTFLAG_LPMNYET_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_LPMNYET_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMNYET; +} + +static inline bool hri_usbdevice_get_INTFLAG_LPMSUSP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMSUSP) >> USB_DEVICE_INTFLAG_LPMSUSP_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_LPMSUSP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMSUSP; +} + +static inline bool hri_usbdevice_get_interrupt_SUSPEND_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SUSPEND) >> USB_DEVICE_INTFLAG_SUSPEND_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_SUSPEND_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SUSPEND; +} + +static inline bool hri_usbdevice_get_interrupt_MSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_MSOF) >> USB_DEVICE_INTFLAG_MSOF_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_MSOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MSOF; +} + +static inline bool hri_usbdevice_get_interrupt_SOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SOF) >> USB_DEVICE_INTFLAG_SOF_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_SOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF; +} + +static inline bool hri_usbdevice_get_interrupt_EORST_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORST) >> USB_DEVICE_INTFLAG_EORST_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_EORST_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST; +} + +static inline bool hri_usbdevice_get_interrupt_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_WAKEUP) >> USB_DEVICE_INTFLAG_WAKEUP_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP; +} + +static inline bool hri_usbdevice_get_interrupt_EORSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORSM) >> USB_DEVICE_INTFLAG_EORSM_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_EORSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORSM; +} + +static inline bool hri_usbdevice_get_interrupt_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_UPRSM) >> USB_DEVICE_INTFLAG_UPRSM_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_UPRSM; +} + +static inline bool hri_usbdevice_get_interrupt_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_RAMACER) >> USB_DEVICE_INTFLAG_RAMACER_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_RAMACER; +} + +static inline bool hri_usbdevice_get_interrupt_LPMNYET_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMNYET) >> USB_DEVICE_INTFLAG_LPMNYET_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_LPMNYET_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMNYET; +} + +static inline bool hri_usbdevice_get_interrupt_LPMSUSP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMSUSP) >> USB_DEVICE_INTFLAG_LPMSUSP_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_LPMSUSP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMSUSP; +} + +static inline hri_usbdevice_intflag_reg_t hri_usbdevice_get_INTFLAG_reg(const void *const hw, + hri_usbdevice_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_intflag_reg_t hri_usbdevice_read_INTFLAG_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.INTFLAG.reg; +} + +static inline void hri_usbdevice_clear_INTFLAG_reg(const void *const hw, hri_usbdevice_intflag_reg_t mask) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = mask; +} + +static inline bool hri_usbhost_get_INTFLAG_HSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_HSOF) >> USB_HOST_INTFLAG_HSOF_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_HSOF_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_HSOF; +} + +static inline bool hri_usbhost_get_INTFLAG_RST_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RST) >> USB_HOST_INTFLAG_RST_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_RST_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST; +} + +static inline bool hri_usbhost_get_INTFLAG_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_WAKEUP) >> USB_HOST_INTFLAG_WAKEUP_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_WAKEUP; +} + +static inline bool hri_usbhost_get_INTFLAG_DNRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DNRSM) >> USB_HOST_INTFLAG_DNRSM_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_DNRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DNRSM; +} + +static inline bool hri_usbhost_get_INTFLAG_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_UPRSM) >> USB_HOST_INTFLAG_UPRSM_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_UPRSM; +} + +static inline bool hri_usbhost_get_INTFLAG_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RAMACER) >> USB_HOST_INTFLAG_RAMACER_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RAMACER; +} + +static inline bool hri_usbhost_get_INTFLAG_DCONN_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DCONN) >> USB_HOST_INTFLAG_DCONN_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_DCONN_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DCONN; +} + +static inline bool hri_usbhost_get_INTFLAG_DDISC_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DDISC) >> USB_HOST_INTFLAG_DDISC_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_DDISC_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DDISC; +} + +static inline bool hri_usbhost_get_interrupt_HSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_HSOF) >> USB_HOST_INTFLAG_HSOF_Pos; +} + +static inline void hri_usbhost_clear_interrupt_HSOF_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_HSOF; +} + +static inline bool hri_usbhost_get_interrupt_RST_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RST) >> USB_HOST_INTFLAG_RST_Pos; +} + +static inline void hri_usbhost_clear_interrupt_RST_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST; +} + +static inline bool hri_usbhost_get_interrupt_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_WAKEUP) >> USB_HOST_INTFLAG_WAKEUP_Pos; +} + +static inline void hri_usbhost_clear_interrupt_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_WAKEUP; +} + +static inline bool hri_usbhost_get_interrupt_DNRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DNRSM) >> USB_HOST_INTFLAG_DNRSM_Pos; +} + +static inline void hri_usbhost_clear_interrupt_DNRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DNRSM; +} + +static inline bool hri_usbhost_get_interrupt_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_UPRSM) >> USB_HOST_INTFLAG_UPRSM_Pos; +} + +static inline void hri_usbhost_clear_interrupt_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_UPRSM; +} + +static inline bool hri_usbhost_get_interrupt_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RAMACER) >> USB_HOST_INTFLAG_RAMACER_Pos; +} + +static inline void hri_usbhost_clear_interrupt_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RAMACER; +} + +static inline bool hri_usbhost_get_interrupt_DCONN_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DCONN) >> USB_HOST_INTFLAG_DCONN_Pos; +} + +static inline void hri_usbhost_clear_interrupt_DCONN_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DCONN; +} + +static inline bool hri_usbhost_get_interrupt_DDISC_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DDISC) >> USB_HOST_INTFLAG_DDISC_Pos; +} + +static inline void hri_usbhost_clear_interrupt_DDISC_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DDISC; +} + +static inline hri_usbhost_intflag_reg_t hri_usbhost_get_INTFLAG_reg(const void *const hw, + hri_usbhost_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_intflag_reg_t hri_usbhost_read_INTFLAG_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.INTFLAG.reg; +} + +static inline void hri_usbhost_clear_INTFLAG_reg(const void *const hw, hri_usbhost_intflag_reg_t mask) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = mask; +} + +static inline void hri_usbdevice_set_INTEN_SUSPEND_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND; +} + +static inline bool hri_usbdevice_get_INTEN_SUSPEND_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_SUSPEND) >> USB_DEVICE_INTENSET_SUSPEND_Pos; +} + +static inline void hri_usbdevice_write_INTEN_SUSPEND_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SUSPEND; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND; + } +} + +static inline void hri_usbdevice_clear_INTEN_SUSPEND_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SUSPEND; +} + +static inline void hri_usbdevice_set_INTEN_MSOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_MSOF; +} + +static inline bool hri_usbdevice_get_INTEN_MSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_MSOF) >> USB_DEVICE_INTENSET_MSOF_Pos; +} + +static inline void hri_usbdevice_write_INTEN_MSOF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_MSOF; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_MSOF; + } +} + +static inline void hri_usbdevice_clear_INTEN_MSOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_MSOF; +} + +static inline void hri_usbdevice_set_INTEN_SOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SOF; +} + +static inline bool hri_usbdevice_get_INTEN_SOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_SOF) >> USB_DEVICE_INTENSET_SOF_Pos; +} + +static inline void hri_usbdevice_write_INTEN_SOF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SOF; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SOF; + } +} + +static inline void hri_usbdevice_clear_INTEN_SOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SOF; +} + +static inline void hri_usbdevice_set_INTEN_EORST_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORST; +} + +static inline bool hri_usbdevice_get_INTEN_EORST_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_EORST) >> USB_DEVICE_INTENSET_EORST_Pos; +} + +static inline void hri_usbdevice_write_INTEN_EORST_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORST; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORST; + } +} + +static inline void hri_usbdevice_clear_INTEN_EORST_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORST; +} + +static inline void hri_usbdevice_set_INTEN_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_WAKEUP; +} + +static inline bool hri_usbdevice_get_INTEN_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_WAKEUP) >> USB_DEVICE_INTENSET_WAKEUP_Pos; +} + +static inline void hri_usbdevice_write_INTEN_WAKEUP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_WAKEUP; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_WAKEUP; + } +} + +static inline void hri_usbdevice_clear_INTEN_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_WAKEUP; +} + +static inline void hri_usbdevice_set_INTEN_EORSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORSM; +} + +static inline bool hri_usbdevice_get_INTEN_EORSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_EORSM) >> USB_DEVICE_INTENSET_EORSM_Pos; +} + +static inline void hri_usbdevice_write_INTEN_EORSM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORSM; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORSM; + } +} + +static inline void hri_usbdevice_clear_INTEN_EORSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORSM; +} + +static inline void hri_usbdevice_set_INTEN_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_UPRSM; +} + +static inline bool hri_usbdevice_get_INTEN_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_UPRSM) >> USB_DEVICE_INTENSET_UPRSM_Pos; +} + +static inline void hri_usbdevice_write_INTEN_UPRSM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_UPRSM; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_UPRSM; + } +} + +static inline void hri_usbdevice_clear_INTEN_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_UPRSM; +} + +static inline void hri_usbdevice_set_INTEN_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_RAMACER; +} + +static inline bool hri_usbdevice_get_INTEN_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_RAMACER) >> USB_DEVICE_INTENSET_RAMACER_Pos; +} + +static inline void hri_usbdevice_write_INTEN_RAMACER_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_RAMACER; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_RAMACER; + } +} + +static inline void hri_usbdevice_clear_INTEN_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_RAMACER; +} + +static inline void hri_usbdevice_set_INTEN_LPMNYET_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMNYET; +} + +static inline bool hri_usbdevice_get_INTEN_LPMNYET_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_LPMNYET) >> USB_DEVICE_INTENSET_LPMNYET_Pos; +} + +static inline void hri_usbdevice_write_INTEN_LPMNYET_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMNYET; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMNYET; + } +} + +static inline void hri_usbdevice_clear_INTEN_LPMNYET_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMNYET; +} + +static inline void hri_usbdevice_set_INTEN_LPMSUSP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMSUSP; +} + +static inline bool hri_usbdevice_get_INTEN_LPMSUSP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_LPMSUSP) >> USB_DEVICE_INTENSET_LPMSUSP_Pos; +} + +static inline void hri_usbdevice_write_INTEN_LPMSUSP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMSUSP; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMSUSP; + } +} + +static inline void hri_usbdevice_clear_INTEN_LPMSUSP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMSUSP; +} + +static inline void hri_usbdevice_set_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t mask) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = mask; +} + +static inline hri_usbdevice_intenset_reg_t hri_usbdevice_get_INTEN_reg(const void *const hw, + hri_usbdevice_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_intenset_reg_t hri_usbdevice_read_INTEN_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.INTENSET.reg; +} + +static inline void hri_usbdevice_write_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t data) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = data; + ((Usb *)hw)->DEVICE.INTENCLR.reg = ~data; +} + +static inline void hri_usbdevice_clear_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t mask) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = mask; +} + +static inline void hri_usbhost_set_INTEN_HSOF_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_HSOF; +} + +static inline bool hri_usbhost_get_INTEN_HSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_HSOF) >> USB_HOST_INTENSET_HSOF_Pos; +} + +static inline void hri_usbhost_write_INTEN_HSOF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_HSOF; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_HSOF; + } +} + +static inline void hri_usbhost_clear_INTEN_HSOF_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_HSOF; +} + +static inline void hri_usbhost_set_INTEN_RST_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RST; +} + +static inline bool hri_usbhost_get_INTEN_RST_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_RST) >> USB_HOST_INTENSET_RST_Pos; +} + +static inline void hri_usbhost_write_INTEN_RST_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RST; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RST; + } +} + +static inline void hri_usbhost_clear_INTEN_RST_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RST; +} + +static inline void hri_usbhost_set_INTEN_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP; +} + +static inline bool hri_usbhost_get_INTEN_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_WAKEUP) >> USB_HOST_INTENSET_WAKEUP_Pos; +} + +static inline void hri_usbhost_write_INTEN_WAKEUP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_WAKEUP; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP; + } +} + +static inline void hri_usbhost_clear_INTEN_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_WAKEUP; +} + +static inline void hri_usbhost_set_INTEN_DNRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DNRSM; +} + +static inline bool hri_usbhost_get_INTEN_DNRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DNRSM) >> USB_HOST_INTENSET_DNRSM_Pos; +} + +static inline void hri_usbhost_write_INTEN_DNRSM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DNRSM; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DNRSM; + } +} + +static inline void hri_usbhost_clear_INTEN_DNRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DNRSM; +} + +static inline void hri_usbhost_set_INTEN_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_UPRSM; +} + +static inline bool hri_usbhost_get_INTEN_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_UPRSM) >> USB_HOST_INTENSET_UPRSM_Pos; +} + +static inline void hri_usbhost_write_INTEN_UPRSM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_UPRSM; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_UPRSM; + } +} + +static inline void hri_usbhost_clear_INTEN_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_UPRSM; +} + +static inline void hri_usbhost_set_INTEN_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RAMACER; +} + +static inline bool hri_usbhost_get_INTEN_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_RAMACER) >> USB_HOST_INTENSET_RAMACER_Pos; +} + +static inline void hri_usbhost_write_INTEN_RAMACER_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RAMACER; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RAMACER; + } +} + +static inline void hri_usbhost_clear_INTEN_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RAMACER; +} + +static inline void hri_usbhost_set_INTEN_DCONN_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN; +} + +static inline bool hri_usbhost_get_INTEN_DCONN_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DCONN) >> USB_HOST_INTENSET_DCONN_Pos; +} + +static inline void hri_usbhost_write_INTEN_DCONN_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DCONN; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN; + } +} + +static inline void hri_usbhost_clear_INTEN_DCONN_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DCONN; +} + +static inline void hri_usbhost_set_INTEN_DDISC_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC; +} + +static inline bool hri_usbhost_get_INTEN_DDISC_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DDISC) >> USB_HOST_INTENSET_DDISC_Pos; +} + +static inline void hri_usbhost_write_INTEN_DDISC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DDISC; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC; + } +} + +static inline void hri_usbhost_clear_INTEN_DDISC_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DDISC; +} + +static inline void hri_usbhost_set_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t mask) +{ + ((Usb *)hw)->HOST.INTENSET.reg = mask; +} + +static inline hri_usbhost_intenset_reg_t hri_usbhost_get_INTEN_reg(const void *const hw, + hri_usbhost_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_intenset_reg_t hri_usbhost_read_INTEN_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.INTENSET.reg; +} + +static inline void hri_usbhost_write_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t data) +{ + ((Usb *)hw)->HOST.INTENSET.reg = data; + ((Usb *)hw)->HOST.INTENCLR.reg = ~data; +} + +static inline void hri_usbhost_clear_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t mask) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = mask; +} + +static inline bool hri_usb_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.SYNCBUSY.reg & USB_SYNCBUSY_SWRST) >> USB_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_usb_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.SYNCBUSY.reg & USB_SYNCBUSY_ENABLE) >> USB_SYNCBUSY_ENABLE_Pos; +} + +static inline hri_usb_syncbusy_reg_t hri_usb_get_SYNCBUSY_reg(const void *const hw, hri_usb_syncbusy_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usb_syncbusy_reg_t hri_usb_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.SYNCBUSY.reg; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_SPEED_bf(const void *const hw, + hri_usbdevice_status_reg_t mask) +{ + return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED(mask)) >> USB_DEVICE_STATUS_SPEED_Pos; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_SPEED_bf(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED_Msk) >> USB_DEVICE_STATUS_SPEED_Pos; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_LINESTATE_bf(const void *const hw, + hri_usbdevice_status_reg_t mask) +{ + return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_LINESTATE(mask)) >> USB_DEVICE_STATUS_LINESTATE_Pos; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_LINESTATE_bf(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_LINESTATE_Msk) >> USB_DEVICE_STATUS_LINESTATE_Pos; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_reg(const void *const hw, + hri_usbdevice_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.STATUS.reg; +} + +static inline hri_usb_fsmstatus_reg_t hri_usb_get_FSMSTATUS_FSMSTATE_bf(const void *const hw, + hri_usb_fsmstatus_reg_t mask) +{ + return (((Usb *)hw)->HOST.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE(mask)) >> USB_FSMSTATUS_FSMSTATE_Pos; +} + +static inline hri_usb_fsmstatus_reg_t hri_usb_read_FSMSTATUS_FSMSTATE_bf(const void *const hw) +{ + return (((Usb *)hw)->HOST.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE_Msk) >> USB_FSMSTATUS_FSMSTATE_Pos; +} + +static inline hri_usb_fsmstatus_reg_t hri_usb_get_FSMSTATUS_reg(const void *const hw, hri_usb_fsmstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.FSMSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usb_fsmstatus_reg_t hri_usb_read_FSMSTATUS_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.FSMSTATUS.reg; +} + +static inline bool hri_usbdevice_get_FNUM_FNCERR_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNCERR) >> USB_DEVICE_FNUM_FNCERR_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_MFNUM_bf(const void *const hw, + hri_usbdevice_fnum_reg_t mask) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_MFNUM(mask)) >> USB_DEVICE_FNUM_MFNUM_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_MFNUM_bf(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_MFNUM_Msk) >> USB_DEVICE_FNUM_MFNUM_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_FNUM_bf(const void *const hw, + hri_usbdevice_fnum_reg_t mask) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNUM(mask)) >> USB_DEVICE_FNUM_FNUM_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_FNUM_bf(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNUM_Msk) >> USB_DEVICE_FNUM_FNUM_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_reg(const void *const hw, hri_usbdevice_fnum_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.FNUM.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.FNUM.reg; +} + +static inline hri_usbhost_flenhigh_reg_t hri_usbhost_get_FLENHIGH_FLENHIGH_bf(const void *const hw, + hri_usbhost_flenhigh_reg_t mask) +{ + return (((Usb *)hw)->HOST.FLENHIGH.reg & USB_HOST_FLENHIGH_FLENHIGH(mask)) >> USB_HOST_FLENHIGH_FLENHIGH_Pos; +} + +static inline hri_usbhost_flenhigh_reg_t hri_usbhost_read_FLENHIGH_FLENHIGH_bf(const void *const hw) +{ + return (((Usb *)hw)->HOST.FLENHIGH.reg & USB_HOST_FLENHIGH_FLENHIGH_Msk) >> USB_HOST_FLENHIGH_FLENHIGH_Pos; +} + +static inline hri_usbhost_flenhigh_reg_t hri_usbhost_get_FLENHIGH_reg(const void *const hw, + hri_usbhost_flenhigh_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.FLENHIGH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_flenhigh_reg_t hri_usbhost_read_FLENHIGH_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.FLENHIGH.reg; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT0_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT0) >> USB_DEVICE_EPINTSMRY_EPINT0_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT1_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT1) >> USB_DEVICE_EPINTSMRY_EPINT1_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT2_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT2) >> USB_DEVICE_EPINTSMRY_EPINT2_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT3_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT3) >> USB_DEVICE_EPINTSMRY_EPINT3_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT4_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT4) >> USB_DEVICE_EPINTSMRY_EPINT4_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT5_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT5) >> USB_DEVICE_EPINTSMRY_EPINT5_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT6_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT6) >> USB_DEVICE_EPINTSMRY_EPINT6_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT7_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT7) >> USB_DEVICE_EPINTSMRY_EPINT7_Pos; +} + +static inline hri_usbdevice_epintsmry_reg_t hri_usbdevice_get_EPINTSMRY_reg(const void *const hw, + hri_usbdevice_epintsmry_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.EPINTSMRY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_epintsmry_reg_t hri_usbdevice_read_EPINTSMRY_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.EPINTSMRY.reg; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT0_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT0) >> USB_HOST_PINTSMRY_EPINT0_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT1_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT1) >> USB_HOST_PINTSMRY_EPINT1_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT2_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT2) >> USB_HOST_PINTSMRY_EPINT2_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT3_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT3) >> USB_HOST_PINTSMRY_EPINT3_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT4_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT4) >> USB_HOST_PINTSMRY_EPINT4_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT5_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT5) >> USB_HOST_PINTSMRY_EPINT5_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT6_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT6) >> USB_HOST_PINTSMRY_EPINT6_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT7_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT7) >> USB_HOST_PINTSMRY_EPINT7_Pos; +} + +static inline hri_usbhost_pintsmry_reg_t hri_usbhost_get_PINTSMRY_reg(const void *const hw, + hri_usbhost_pintsmry_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PINTSMRY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_pintsmry_reg_t hri_usbhost_read_PINTSMRY_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.PINTSMRY.reg; +} + +static inline void hri_usb_set_CTRLA_SWRST_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_SWRST; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usb_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp = (tmp & USB_CTRLA_SWRST) >> USB_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_usb_set_CTRLA_ENABLE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_ENABLE; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usb_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp = (tmp & USB_CTRLA_ENABLE) >> USB_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_usb_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp &= ~USB_CTRLA_ENABLE; + tmp |= value << USB_CTRLA_ENABLE_Pos; + ((Usb *)hw)->HOST.CTRLA.reg = tmp; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_ENABLE; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_ENABLE; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_RUNSTDBY; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usb_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp = (tmp & USB_CTRLA_RUNSTDBY) >> USB_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_usb_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp &= ~USB_CTRLA_RUNSTDBY; + tmp |= value << USB_CTRLA_RUNSTDBY_Pos; + ((Usb *)hw)->HOST.CTRLA.reg = tmp; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_RUNSTDBY; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_RUNSTDBY; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_set_CTRLA_MODE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_MODE; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usb_get_CTRLA_MODE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp = (tmp & USB_CTRLA_MODE) >> USB_CTRLA_MODE_Pos; + return (bool)tmp; +} + +static inline void hri_usb_write_CTRLA_MODE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp &= ~USB_CTRLA_MODE; + tmp |= value << USB_CTRLA_MODE_Pos; + ((Usb *)hw)->HOST.CTRLA.reg = tmp; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_CTRLA_MODE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_MODE; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_CTRLA_MODE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_MODE; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_set_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg |= mask; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_ctrla_reg_t hri_usb_get_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usb_write_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg = data; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg &= ~mask; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg ^= mask; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_ctrla_reg_t hri_usb_read_CTRLA_reg(const void *const hw) +{ + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + return ((Usb *)hw)->HOST.CTRLA.reg; +} + +static inline void hri_usb_set_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg |= USB_QOSCTRL_CQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_CQOS(mask)) >> USB_QOSCTRL_CQOS_Pos; + return tmp; +} + +static inline void hri_usb_write_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp &= ~USB_QOSCTRL_CQOS_Msk; + tmp |= USB_QOSCTRL_CQOS(data); + ((Usb *)hw)->HOST.QOSCTRL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg &= ~USB_QOSCTRL_CQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg ^= USB_QOSCTRL_CQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_CQOS_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_CQOS_Msk) >> USB_QOSCTRL_CQOS_Pos; + return tmp; +} + +static inline void hri_usb_set_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg |= USB_QOSCTRL_DQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_DQOS(mask)) >> USB_QOSCTRL_DQOS_Pos; + return tmp; +} + +static inline void hri_usb_write_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp &= ~USB_QOSCTRL_DQOS_Msk; + tmp |= USB_QOSCTRL_DQOS(data); + ((Usb *)hw)->HOST.QOSCTRL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg &= ~USB_QOSCTRL_DQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg ^= USB_QOSCTRL_DQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_DQOS_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_DQOS_Msk) >> USB_QOSCTRL_DQOS_Pos; + return tmp; +} + +static inline void hri_usb_set_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usb_write_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.QOSCTRL.reg; +} + +static inline void hri_usbdevice_set_CTRLB_DETACH_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_DETACH; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_DETACH_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_DETACH) >> USB_DEVICE_CTRLB_DETACH_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_DETACH_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_DETACH; + tmp |= value << USB_DEVICE_CTRLB_DETACH_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_DETACH_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_DETACH; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_DETACH_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_DETACH; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_UPRSM_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_UPRSM; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_UPRSM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_UPRSM) >> USB_DEVICE_CTRLB_UPRSM_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_UPRSM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_UPRSM; + tmp |= value << USB_DEVICE_CTRLB_UPRSM_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_UPRSM_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_UPRSM; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_UPRSM_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_UPRSM; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_NREPLY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_NREPLY; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_NREPLY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_NREPLY) >> USB_DEVICE_CTRLB_NREPLY_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_NREPLY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_NREPLY; + tmp |= value << USB_DEVICE_CTRLB_NREPLY_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_NREPLY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_NREPLY; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_NREPLY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_NREPLY; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_TSTJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_TSTJ) >> USB_DEVICE_CTRLB_TSTJ_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_TSTJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_TSTJ; + tmp |= value << USB_DEVICE_CTRLB_TSTJ_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_TSTK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_TSTK) >> USB_DEVICE_CTRLB_TSTK_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_TSTK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_TSTK; + tmp |= value << USB_DEVICE_CTRLB_TSTK_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_TSTPCKT_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTPCKT; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_TSTPCKT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_TSTPCKT) >> USB_DEVICE_CTRLB_TSTPCKT_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_TSTPCKT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_TSTPCKT; + tmp |= value << USB_DEVICE_CTRLB_TSTPCKT_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_TSTPCKT_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTPCKT; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_TSTPCKT_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTPCKT; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_OPMODE2_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_OPMODE2; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_OPMODE2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_OPMODE2) >> USB_DEVICE_CTRLB_OPMODE2_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_OPMODE2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_OPMODE2; + tmp |= value << USB_DEVICE_CTRLB_OPMODE2_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_OPMODE2_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_OPMODE2; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_OPMODE2_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_OPMODE2; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_GNAK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_GNAK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_GNAK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_GNAK) >> USB_DEVICE_CTRLB_GNAK_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_GNAK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_GNAK; + tmp |= value << USB_DEVICE_CTRLB_GNAK_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_GNAK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_GNAK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_GNAK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_GNAK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_SPDCONF_bf(const void *const hw, + hri_usbdevice_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_SPDCONF(mask)) >> USB_DEVICE_CTRLB_SPDCONF_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_SPDCONF_Msk; + tmp |= USB_DEVICE_CTRLB_SPDCONF(data); + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_SPDCONF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_SPDCONF_Msk) >> USB_DEVICE_CTRLB_SPDCONF_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_LPMHDSK(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_LPMHDSK_bf(const void *const hw, + hri_usbdevice_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_LPMHDSK(mask)) >> USB_DEVICE_CTRLB_LPMHDSK_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_LPMHDSK_Msk; + tmp |= USB_DEVICE_CTRLB_LPMHDSK(data); + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_LPMHDSK(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_LPMHDSK(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_LPMHDSK_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_LPMHDSK_Msk) >> USB_DEVICE_CTRLB_LPMHDSK_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_reg(const void *const hw, + hri_usbdevice_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevice_write_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.CTRLB.reg; +} + +static inline void hri_usbhost_set_CTRLB_RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_RESUME_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_RESUME) >> USB_HOST_CTRLB_RESUME_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_RESUME_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_RESUME; + tmp |= value << USB_HOST_CTRLB_RESUME_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_AUTORESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_AUTORESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_AUTORESUME_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_AUTORESUME) >> USB_HOST_CTRLB_AUTORESUME_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_AUTORESUME_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_AUTORESUME; + tmp |= value << USB_HOST_CTRLB_AUTORESUME_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_AUTORESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_AUTORESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_AUTORESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_AUTORESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_TSTJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_TSTJ) >> USB_HOST_CTRLB_TSTJ_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_TSTJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_TSTJ; + tmp |= value << USB_HOST_CTRLB_TSTJ_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_TSTK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_TSTK) >> USB_HOST_CTRLB_TSTK_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_TSTK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_TSTK; + tmp |= value << USB_HOST_CTRLB_TSTK_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_SOFE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_SOFE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_SOFE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_SOFE) >> USB_HOST_CTRLB_SOFE_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_SOFE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_SOFE; + tmp |= value << USB_HOST_CTRLB_SOFE_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_SOFE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_SOFE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_SOFE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_SOFE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_BUSRESET_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_BUSRESET; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_BUSRESET_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_BUSRESET) >> USB_HOST_CTRLB_BUSRESET_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_BUSRESET_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_BUSRESET; + tmp |= value << USB_HOST_CTRLB_BUSRESET_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_BUSRESET_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_BUSRESET; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_BUSRESET_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_BUSRESET; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_VBUSOK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_VBUSOK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_VBUSOK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_VBUSOK) >> USB_HOST_CTRLB_VBUSOK_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_VBUSOK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_VBUSOK; + tmp |= value << USB_HOST_CTRLB_VBUSOK_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_VBUSOK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_VBUSOK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_VBUSOK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_VBUSOK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_L1RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_L1RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_L1RESUME_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_L1RESUME) >> USB_HOST_CTRLB_L1RESUME_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_L1RESUME_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_L1RESUME; + tmp |= value << USB_HOST_CTRLB_L1RESUME_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_L1RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_L1RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_L1RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_L1RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_ctrlb_reg_t hri_usbhost_get_CTRLB_SPDCONF_bf(const void *const hw, + hri_usbhost_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_SPDCONF(mask)) >> USB_HOST_CTRLB_SPDCONF_Pos; + return tmp; +} + +static inline void hri_usbhost_write_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_SPDCONF_Msk; + tmp |= USB_HOST_CTRLB_SPDCONF(data); + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_ctrlb_reg_t hri_usbhost_read_CTRLB_SPDCONF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_SPDCONF_Msk) >> USB_HOST_CTRLB_SPDCONF_Pos; + return tmp; +} + +static inline void hri_usbhost_set_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_ctrlb_reg_t hri_usbhost_get_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_ctrlb_reg_t hri_usbhost_read_CTRLB_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.CTRLB.reg; +} + +static inline void hri_usbdevice_set_DADD_ADDEN_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg |= USB_DEVICE_DADD_ADDEN; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_DADD_ADDEN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp = (tmp & USB_DEVICE_DADD_ADDEN) >> USB_DEVICE_DADD_ADDEN_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_DADD_ADDEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp &= ~USB_DEVICE_DADD_ADDEN; + tmp |= value << USB_DEVICE_DADD_ADDEN_Pos; + ((Usb *)hw)->DEVICE.DADD.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_DADD_ADDEN_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg &= ~USB_DEVICE_DADD_ADDEN; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_DADD_ADDEN_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg ^= USB_DEVICE_DADD_ADDEN; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg |= USB_DEVICE_DADD_DADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_dadd_reg_t hri_usbdevice_get_DADD_DADD_bf(const void *const hw, + hri_usbdevice_dadd_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp = (tmp & USB_DEVICE_DADD_DADD(mask)) >> USB_DEVICE_DADD_DADD_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp &= ~USB_DEVICE_DADD_DADD_Msk; + tmp |= USB_DEVICE_DADD_DADD(data); + ((Usb *)hw)->DEVICE.DADD.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg &= ~USB_DEVICE_DADD_DADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg ^= USB_DEVICE_DADD_DADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_dadd_reg_t hri_usbdevice_read_DADD_DADD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp = (tmp & USB_DEVICE_DADD_DADD_Msk) >> USB_DEVICE_DADD_DADD_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_dadd_reg_t hri_usbdevice_get_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevice_write_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_dadd_reg_t hri_usbdevice_read_DADD_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.DADD.reg; +} + +static inline void hri_usbhost_set_HSOFC_FLENCE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg |= USB_HOST_HSOFC_FLENCE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_HSOFC_FLENCE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp = (tmp & USB_HOST_HSOFC_FLENCE) >> USB_HOST_HSOFC_FLENCE_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_HSOFC_FLENCE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp &= ~USB_HOST_HSOFC_FLENCE; + tmp |= value << USB_HOST_HSOFC_FLENCE_Pos; + ((Usb *)hw)->HOST.HSOFC.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_HSOFC_FLENCE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg &= ~USB_HOST_HSOFC_FLENCE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_HSOFC_FLENCE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg ^= USB_HOST_HSOFC_FLENCE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg |= USB_HOST_HSOFC_FLENC(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_hsofc_reg_t hri_usbhost_get_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp = (tmp & USB_HOST_HSOFC_FLENC(mask)) >> USB_HOST_HSOFC_FLENC_Pos; + return tmp; +} + +static inline void hri_usbhost_write_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp &= ~USB_HOST_HSOFC_FLENC_Msk; + tmp |= USB_HOST_HSOFC_FLENC(data); + ((Usb *)hw)->HOST.HSOFC.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg &= ~USB_HOST_HSOFC_FLENC(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg ^= USB_HOST_HSOFC_FLENC(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_hsofc_reg_t hri_usbhost_read_HSOFC_FLENC_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp = (tmp & USB_HOST_HSOFC_FLENC_Msk) >> USB_HOST_HSOFC_FLENC_Pos; + return tmp; +} + +static inline void hri_usbhost_set_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_hsofc_reg_t hri_usbhost_get_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_hsofc_reg_t hri_usbhost_read_HSOFC_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.HSOFC.reg; +} + +static inline void hri_usbhost_set_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg |= USB_HOST_FNUM_MFNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp = (tmp & USB_HOST_FNUM_MFNUM(mask)) >> USB_HOST_FNUM_MFNUM_Pos; + return tmp; +} + +static inline void hri_usbhost_write_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp &= ~USB_HOST_FNUM_MFNUM_Msk; + tmp |= USB_HOST_FNUM_MFNUM(data); + ((Usb *)hw)->HOST.FNUM.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg &= ~USB_HOST_FNUM_MFNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg ^= USB_HOST_FNUM_MFNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_MFNUM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp = (tmp & USB_HOST_FNUM_MFNUM_Msk) >> USB_HOST_FNUM_MFNUM_Pos; + return tmp; +} + +static inline void hri_usbhost_set_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg |= USB_HOST_FNUM_FNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp = (tmp & USB_HOST_FNUM_FNUM(mask)) >> USB_HOST_FNUM_FNUM_Pos; + return tmp; +} + +static inline void hri_usbhost_write_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp &= ~USB_HOST_FNUM_FNUM_Msk; + tmp |= USB_HOST_FNUM_FNUM(data); + ((Usb *)hw)->HOST.FNUM.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg &= ~USB_HOST_FNUM_FNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg ^= USB_HOST_FNUM_FNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_FNUM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp = (tmp & USB_HOST_FNUM_FNUM_Msk) >> USB_HOST_FNUM_FNUM_Pos; + return tmp; +} + +static inline void hri_usbhost_set_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.FNUM.reg; +} + +static inline void hri_usb_set_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg |= USB_DESCADD_DESCADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_descadd_reg_t hri_usb_get_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usb *)hw)->HOST.DESCADD.reg; + tmp = (tmp & USB_DESCADD_DESCADD(mask)) >> USB_DESCADD_DESCADD_Pos; + return tmp; +} + +static inline void hri_usb_write_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.DESCADD.reg; + tmp &= ~USB_DESCADD_DESCADD_Msk; + tmp |= USB_DESCADD_DESCADD(data); + ((Usb *)hw)->HOST.DESCADD.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg &= ~USB_DESCADD_DESCADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg ^= USB_DESCADD_DESCADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_descadd_reg_t hri_usb_read_DESCADD_DESCADD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usb *)hw)->HOST.DESCADD.reg; + tmp = (tmp & USB_DESCADD_DESCADD_Msk) >> USB_DESCADD_DESCADD_Pos; + return tmp; +} + +static inline void hri_usb_set_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_descadd_reg_t hri_usb_get_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usb *)hw)->HOST.DESCADD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usb_write_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_descadd_reg_t hri_usb_read_DESCADD_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.DESCADD.reg; +} + +static inline void hri_usb_set_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRANSP(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSP(mask)) >> USB_PADCAL_TRANSP_Pos; + return tmp; +} + +static inline void hri_usb_write_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp &= ~USB_PADCAL_TRANSP_Msk; + tmp |= USB_PADCAL_TRANSP(data); + ((Usb *)hw)->HOST.PADCAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRANSP(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRANSP(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRANSP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSP_Msk) >> USB_PADCAL_TRANSP_Pos; + return tmp; +} + +static inline void hri_usb_set_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRANSN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSN(mask)) >> USB_PADCAL_TRANSN_Pos; + return tmp; +} + +static inline void hri_usb_write_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp &= ~USB_PADCAL_TRANSN_Msk; + tmp |= USB_PADCAL_TRANSN(data); + ((Usb *)hw)->HOST.PADCAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRANSN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRANSN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRANSN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSN_Msk) >> USB_PADCAL_TRANSN_Pos; + return tmp; +} + +static inline void hri_usb_set_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRIM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRIM(mask)) >> USB_PADCAL_TRIM_Pos; + return tmp; +} + +static inline void hri_usb_write_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp &= ~USB_PADCAL_TRIM_Msk; + tmp |= USB_PADCAL_TRIM(data); + ((Usb *)hw)->HOST.PADCAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRIM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRIM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRIM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRIM_Msk) >> USB_PADCAL_TRIM_Pos; + return tmp; +} + +static inline void hri_usb_set_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usb_write_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.PADCAL.reg; +} + +static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_SPEED_bf(const void *const hw, + hri_usbhost_status_reg_t mask) +{ + return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_SPEED(mask)) >> USB_HOST_STATUS_SPEED_Pos; +} + +static inline void hri_usbhost_clear_STATUS_SPEED_bf(const void *const hw, hri_usbhost_status_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.STATUS.reg = USB_HOST_STATUS_SPEED(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_SPEED_bf(const void *const hw) +{ + return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_SPEED_Msk) >> USB_HOST_STATUS_SPEED_Pos; +} + +static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_LINESTATE_bf(const void *const hw, + hri_usbhost_status_reg_t mask) +{ + return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_LINESTATE(mask)) >> USB_HOST_STATUS_LINESTATE_Pos; +} + +static inline void hri_usbhost_clear_STATUS_LINESTATE_bf(const void *const hw, hri_usbhost_status_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.STATUS.reg = USB_HOST_STATUS_LINESTATE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_LINESTATE_bf(const void *const hw) +{ + return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_LINESTATE_Msk) >> USB_HOST_STATUS_LINESTATE_Pos; +} + +static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_reg(const void *const hw, hri_usbhost_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_clear_STATUS_reg(const void *const hw, hri_usbhost_status_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.STATUS.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.STATUS.reg; +} + +static inline void hri_usbdevicedescbank_set_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg |= USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_get_ADDR_ADDR_bf(const void *const hw, + hri_usbdesc_bank_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; + tmp = (tmp & USB_DEVICE_ADDR_ADDR(mask)) >> USB_DEVICE_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; + tmp &= ~USB_DEVICE_ADDR_ADDR_Msk; + tmp |= USB_DEVICE_ADDR_ADDR(data); + ((UsbDeviceDescBank *)hw)->ADDR.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg &= ~USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg ^= USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; + tmp = (tmp & USB_DEVICE_ADDR_ADDR_Msk) >> USB_DEVICE_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_get_ADDR_reg(const void *const hw, + hri_usbdesc_bank_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_read_ADDR_reg(const void *const hw) +{ + return ((UsbDeviceDescBank *)hw)->ADDR.reg; +} + +static inline void hri_usbdevicedescbank_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevicedescbank_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_AUTO_ZLP) >> USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevicedescbank_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; + tmp |= value << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbdevicedescbank_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT(mask)) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk; + tmp |= USB_DEVICE_PCKSIZE_BYTE_COUNT(data); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbdevicedescbank_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk; + tmp |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(data); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbdevicedescbank_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbdevicedescbank_get_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE(mask)) >> USB_DEVICE_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_PCKSIZE_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_SIZE_Msk; + tmp |= USB_DEVICE_PCKSIZE_SIZE(data); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_PCKSIZE_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_PCKSIZE_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_SIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE_Msk) >> USB_DEVICE_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_get_PCKSIZE_reg(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_reg(const void *const hw) +{ + return ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; +} + +static inline void hri_usbdevicedescbank_set_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg |= USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t +hri_usbdevicedescbank_get_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_SUBPID(mask)) >> USB_DEVICE_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_EXTREG_SUBPID_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp &= ~USB_DEVICE_EXTREG_SUBPID_Msk; + tmp |= USB_DEVICE_EXTREG_SUBPID(data); + ((UsbDeviceDescBank *)hw)->EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_EXTREG_SUBPID_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_EXTREG_SUBPID_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg ^= USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_SUBPID_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_SUBPID_Msk) >> USB_DEVICE_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg |= USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t +hri_usbdevicedescbank_get_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE(mask)) >> USB_DEVICE_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp &= ~USB_DEVICE_EXTREG_VARIABLE_Msk; + tmp |= USB_DEVICE_EXTREG_VARIABLE(data); + ((UsbDeviceDescBank *)hw)->EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg ^= USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_VARIABLE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE_Msk) >> USB_DEVICE_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_get_EXTREG_reg(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_reg(const void *const hw) +{ + return ((UsbDeviceDescBank *)hw)->EXTREG.reg; +} + +static inline bool hri_usbdevicedescbank_get_STATUS_BK_CRCERR_bit(const void *const hw) +{ + return (((UsbDeviceDescBank *)hw)->STATUS_BK.reg & USB_DEVICE_STATUS_BK_CRCERR) >> USB_DEVICE_STATUS_BK_CRCERR_Pos; +} + +static inline void hri_usbdevicedescbank_clear_STATUS_BK_CRCERR_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->STATUS_BK.reg = USB_DEVICE_STATUS_BK_CRCERR; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevicedescbank_get_STATUS_BK_ERRORFLOW_bit(const void *const hw) +{ + return (((UsbDeviceDescBank *)hw)->STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW) + >> USB_DEVICE_STATUS_BK_ERRORFLOW_Pos; +} + +static inline void hri_usbdevicedescbank_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->STATUS_BK.reg = USB_DEVICE_STATUS_BK_ERRORFLOW; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_bk_reg_t +hri_usbdevicedescbank_get_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->STATUS_BK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescbank_clear_STATUS_BK_reg(const void *const hw, + hri_usbdesc_bank_status_bk_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->STATUS_BK.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_bk_reg_t hri_usbdevicedescbank_read_STATUS_BK_reg(const void *const hw) +{ + return ((UsbDeviceDescBank *)hw)->STATUS_BK.reg; +} + +static inline void hri_usbdevicedescriptor_set_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg |= USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_addr_reg_t +hri_usbdevicedescriptor_get_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; + tmp = (tmp & USB_DEVICE_ADDR_ADDR(mask)) >> USB_DEVICE_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; + tmp &= ~USB_DEVICE_ADDR_ADDR_Msk; + tmp |= USB_DEVICE_ADDR_ADDR(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg &= ~USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg ^= USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_addr_reg_t hri_usbdevicedescriptor_read_ADDR_ADDR_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; + tmp = (tmp & USB_DEVICE_ADDR_ADDR_Msk) >> USB_DEVICE_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_addr_reg_t +hri_usbdevicedescriptor_get_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_addr_reg_t hri_usbdevicedescriptor_read_ADDR_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevicedescriptor_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_AUTO_ZLP) >> USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevicedescriptor_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; + tmp |= value << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT(mask)) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk; + tmp |= USB_DEVICE_PCKSIZE_BYTE_COUNT(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg + |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void +hri_usbdevicedescriptor_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk; + tmp |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void +hri_usbdevicedescriptor_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg + &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void +hri_usbdevicedescriptor_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg + ^= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_get_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE(mask)) >> USB_DEVICE_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_SIZE_Msk; + tmp |= USB_DEVICE_PCKSIZE_SIZE(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_read_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE_Msk) >> USB_DEVICE_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_get_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t hri_usbdevicedescriptor_read_PCKSIZE_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; +} + +static inline void hri_usbdevicedescriptor_set_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_extreg_reg_t +hri_usbdevicedescriptor_get_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_SUBPID(mask)) >> USB_DEVICE_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp &= ~USB_DEVICE_EXTREG_SUBPID_Msk; + tmp |= USB_DEVICE_EXTREG_SUBPID(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_extreg_reg_t +hri_usbdevicedescriptor_read_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_SUBPID_Msk) >> USB_DEVICE_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_extreg_reg_t +hri_usbdevicedescriptor_get_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE(mask)) >> USB_DEVICE_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp &= ~USB_DEVICE_EXTREG_VARIABLE_Msk; + tmp |= USB_DEVICE_EXTREG_VARIABLE(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_extreg_reg_t +hri_usbdevicedescriptor_read_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE_Msk) >> USB_DEVICE_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_extreg_reg_t +hri_usbdevicedescriptor_get_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_extreg_reg_t hri_usbdevicedescriptor_read_EXTREG_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; +} + +static inline bool hri_usbdevicedescriptor_get_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg & USB_DEVICE_STATUS_BK_CRCERR) + >> USB_DEVICE_STATUS_BK_CRCERR_Pos; +} + +static inline void hri_usbdevicedescriptor_clear_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = USB_DEVICE_STATUS_BK_CRCERR; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevicedescriptor_get_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW) + >> USB_DEVICE_STATUS_BK_ERRORFLOW_Pos; +} + +static inline void hri_usbdevicedescriptor_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = USB_DEVICE_STATUS_BK_ERRORFLOW; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_status_bk_reg_t +hri_usbdevicedescriptor_get_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_status_bk_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescriptor_clear_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_status_bk_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_status_bk_reg_t +hri_usbdevicedescriptor_read_STATUS_BK_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg; +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_usbdevice_wait_for_sync(a, b) hri_usb_wait_for_sync(a, b) +#define hri_usbdevice_is_syncing(a, b) hri_usb_is_syncing(a, b) +#define hri_usbhost_wait_for_sync(a, b) hri_usb_wait_for_sync(a, b) +#define hri_usbhost_is_syncing(a, b) hri_usb_is_syncing(a, b) +#define hri_usbhost_get_SYNCBUSY_SWRST_bit(a) hri_usb_get_SYNCBUSY_SWRST_bit(a) +#define hri_usbhost_get_SYNCBUSY_ENABLE_bit(a) hri_usb_get_SYNCBUSY_ENABLE_bit(a) +#define hri_usbhost_get_SYNCBUSY_reg(a, b) hri_usb_get_SYNCBUSY_reg(a, b) +#define hri_usbhost_read_SYNCBUSY_reg(a) hri_usb_read_SYNCBUSY_reg(a) +#define hri_usbhost_get_FSMSTATUS_FSMSTATE_bf(a, b) hri_usb_get_FSMSTATUS_FSMSTATE_bf(a, b) +#define hri_usbhost_read_FSMSTATUS_FSMSTATE_bf(a) hri_usb_read_FSMSTATUS_FSMSTATE_bf(a) +#define hri_usbhost_get_FSMSTATUS_reg(a, b) hri_usb_get_FSMSTATUS_reg(a, b) +#define hri_usbhost_read_FSMSTATUS_reg(a) hri_usb_read_FSMSTATUS_reg(a) +#define hri_usbhost_set_CTRLA_SWRST_bit(a) hri_usb_set_CTRLA_SWRST_bit(a) +#define hri_usbhost_get_CTRLA_SWRST_bit(a) hri_usb_get_CTRLA_SWRST_bit(a) +#define hri_usbhost_set_CTRLA_ENABLE_bit(a) hri_usb_set_CTRLA_ENABLE_bit(a) +#define hri_usbhost_get_CTRLA_ENABLE_bit(a) hri_usb_get_CTRLA_ENABLE_bit(a) +#define hri_usbhost_write_CTRLA_ENABLE_bit(a, b) hri_usb_write_CTRLA_ENABLE_bit(a, b) +#define hri_usbhost_clear_CTRLA_ENABLE_bit(a) hri_usb_clear_CTRLA_ENABLE_bit(a) +#define hri_usbhost_toggle_CTRLA_ENABLE_bit(a) hri_usb_toggle_CTRLA_ENABLE_bit(a) +#define hri_usbhost_set_CTRLA_RUNSTDBY_bit(a) hri_usb_set_CTRLA_RUNSTDBY_bit(a) +#define hri_usbhost_get_CTRLA_RUNSTDBY_bit(a) hri_usb_get_CTRLA_RUNSTDBY_bit(a) +#define hri_usbhost_write_CTRLA_RUNSTDBY_bit(a, b) hri_usb_write_CTRLA_RUNSTDBY_bit(a, b) +#define hri_usbhost_clear_CTRLA_RUNSTDBY_bit(a) hri_usb_clear_CTRLA_RUNSTDBY_bit(a) +#define hri_usbhost_toggle_CTRLA_RUNSTDBY_bit(a) hri_usb_toggle_CTRLA_RUNSTDBY_bit(a) +#define hri_usbhost_set_CTRLA_MODE_bit(a) hri_usb_set_CTRLA_MODE_bit(a) +#define hri_usbhost_get_CTRLA_MODE_bit(a) hri_usb_get_CTRLA_MODE_bit(a) +#define hri_usbhost_write_CTRLA_MODE_bit(a, b) hri_usb_write_CTRLA_MODE_bit(a, b) +#define hri_usbhost_clear_CTRLA_MODE_bit(a) hri_usb_clear_CTRLA_MODE_bit(a) +#define hri_usbhost_toggle_CTRLA_MODE_bit(a) hri_usb_toggle_CTRLA_MODE_bit(a) +#define hri_usbhost_set_CTRLA_reg(a, b) hri_usb_set_CTRLA_reg(a, b) +#define hri_usbhost_get_CTRLA_reg(a, b) hri_usb_get_CTRLA_reg(a, b) +#define hri_usbhost_write_CTRLA_reg(a, b) hri_usb_write_CTRLA_reg(a, b) +#define hri_usbhost_clear_CTRLA_reg(a, b) hri_usb_clear_CTRLA_reg(a, b) +#define hri_usbhost_toggle_CTRLA_reg(a, b) hri_usb_toggle_CTRLA_reg(a, b) +#define hri_usbhost_read_CTRLA_reg(a) hri_usb_read_CTRLA_reg(a) +#define hri_usbhost_set_QOSCTRL_CQOS_bf(a, b) hri_usb_set_QOSCTRL_CQOS_bf(a, b) +#define hri_usbhost_get_QOSCTRL_CQOS_bf(a, b) hri_usb_get_QOSCTRL_CQOS_bf(a, b) +#define hri_usbhost_write_QOSCTRL_CQOS_bf(a, b) hri_usb_write_QOSCTRL_CQOS_bf(a, b) +#define hri_usbhost_clear_QOSCTRL_CQOS_bf(a, b) hri_usb_clear_QOSCTRL_CQOS_bf(a, b) +#define hri_usbhost_toggle_QOSCTRL_CQOS_bf(a, b) hri_usb_toggle_QOSCTRL_CQOS_bf(a, b) +#define hri_usbhost_read_QOSCTRL_CQOS_bf(a) hri_usb_read_QOSCTRL_CQOS_bf(a) +#define hri_usbhost_set_QOSCTRL_DQOS_bf(a, b) hri_usb_set_QOSCTRL_DQOS_bf(a, b) +#define hri_usbhost_get_QOSCTRL_DQOS_bf(a, b) hri_usb_get_QOSCTRL_DQOS_bf(a, b) +#define hri_usbhost_write_QOSCTRL_DQOS_bf(a, b) hri_usb_write_QOSCTRL_DQOS_bf(a, b) +#define hri_usbhost_clear_QOSCTRL_DQOS_bf(a, b) hri_usb_clear_QOSCTRL_DQOS_bf(a, b) +#define hri_usbhost_toggle_QOSCTRL_DQOS_bf(a, b) hri_usb_toggle_QOSCTRL_DQOS_bf(a, b) +#define hri_usbhost_read_QOSCTRL_DQOS_bf(a) hri_usb_read_QOSCTRL_DQOS_bf(a) +#define hri_usbhost_set_QOSCTRL_reg(a, b) hri_usb_set_QOSCTRL_reg(a, b) +#define hri_usbhost_get_QOSCTRL_reg(a, b) hri_usb_get_QOSCTRL_reg(a, b) +#define hri_usbhost_write_QOSCTRL_reg(a, b) hri_usb_write_QOSCTRL_reg(a, b) +#define hri_usbhost_clear_QOSCTRL_reg(a, b) hri_usb_clear_QOSCTRL_reg(a, b) +#define hri_usbhost_toggle_QOSCTRL_reg(a, b) hri_usb_toggle_QOSCTRL_reg(a, b) +#define hri_usbhost_read_QOSCTRL_reg(a) hri_usb_read_QOSCTRL_reg(a) +#define hri_usbhost_set_DESCADD_DESCADD_bf(a, b) hri_usb_set_DESCADD_DESCADD_bf(a, b) +#define hri_usbhost_get_DESCADD_DESCADD_bf(a, b) hri_usb_get_DESCADD_DESCADD_bf(a, b) +#define hri_usbhost_write_DESCADD_DESCADD_bf(a, b) hri_usb_write_DESCADD_DESCADD_bf(a, b) +#define hri_usbhost_clear_DESCADD_DESCADD_bf(a, b) hri_usb_clear_DESCADD_DESCADD_bf(a, b) +#define hri_usbhost_toggle_DESCADD_DESCADD_bf(a, b) hri_usb_toggle_DESCADD_DESCADD_bf(a, b) +#define hri_usbhost_read_DESCADD_DESCADD_bf(a) hri_usb_read_DESCADD_DESCADD_bf(a) +#define hri_usbhost_set_DESCADD_reg(a, b) hri_usb_set_DESCADD_reg(a, b) +#define hri_usbhost_get_DESCADD_reg(a, b) hri_usb_get_DESCADD_reg(a, b) +#define hri_usbhost_write_DESCADD_reg(a, b) hri_usb_write_DESCADD_reg(a, b) +#define hri_usbhost_clear_DESCADD_reg(a, b) hri_usb_clear_DESCADD_reg(a, b) +#define hri_usbhost_toggle_DESCADD_reg(a, b) hri_usb_toggle_DESCADD_reg(a, b) +#define hri_usbhost_read_DESCADD_reg(a) hri_usb_read_DESCADD_reg(a) +#define hri_usbhost_set_PADCAL_TRANSP_bf(a, b) hri_usb_set_PADCAL_TRANSP_bf(a, b) +#define hri_usbhost_get_PADCAL_TRANSP_bf(a, b) hri_usb_get_PADCAL_TRANSP_bf(a, b) +#define hri_usbhost_write_PADCAL_TRANSP_bf(a, b) hri_usb_write_PADCAL_TRANSP_bf(a, b) +#define hri_usbhost_clear_PADCAL_TRANSP_bf(a, b) hri_usb_clear_PADCAL_TRANSP_bf(a, b) +#define hri_usbhost_toggle_PADCAL_TRANSP_bf(a, b) hri_usb_toggle_PADCAL_TRANSP_bf(a, b) +#define hri_usbhost_read_PADCAL_TRANSP_bf(a) hri_usb_read_PADCAL_TRANSP_bf(a) +#define hri_usbhost_set_PADCAL_TRANSN_bf(a, b) hri_usb_set_PADCAL_TRANSN_bf(a, b) +#define hri_usbhost_get_PADCAL_TRANSN_bf(a, b) hri_usb_get_PADCAL_TRANSN_bf(a, b) +#define hri_usbhost_write_PADCAL_TRANSN_bf(a, b) hri_usb_write_PADCAL_TRANSN_bf(a, b) +#define hri_usbhost_clear_PADCAL_TRANSN_bf(a, b) hri_usb_clear_PADCAL_TRANSN_bf(a, b) +#define hri_usbhost_toggle_PADCAL_TRANSN_bf(a, b) hri_usb_toggle_PADCAL_TRANSN_bf(a, b) +#define hri_usbhost_read_PADCAL_TRANSN_bf(a) hri_usb_read_PADCAL_TRANSN_bf(a) +#define hri_usbhost_set_PADCAL_TRIM_bf(a, b) hri_usb_set_PADCAL_TRIM_bf(a, b) +#define hri_usbhost_get_PADCAL_TRIM_bf(a, b) hri_usb_get_PADCAL_TRIM_bf(a, b) +#define hri_usbhost_write_PADCAL_TRIM_bf(a, b) hri_usb_write_PADCAL_TRIM_bf(a, b) +#define hri_usbhost_clear_PADCAL_TRIM_bf(a, b) hri_usb_clear_PADCAL_TRIM_bf(a, b) +#define hri_usbhost_toggle_PADCAL_TRIM_bf(a, b) hri_usb_toggle_PADCAL_TRIM_bf(a, b) +#define hri_usbhost_read_PADCAL_TRIM_bf(a) hri_usb_read_PADCAL_TRIM_bf(a) +#define hri_usbhost_set_PADCAL_reg(a, b) hri_usb_set_PADCAL_reg(a, b) +#define hri_usbhost_get_PADCAL_reg(a, b) hri_usb_get_PADCAL_reg(a, b) +#define hri_usbhost_write_PADCAL_reg(a, b) hri_usb_write_PADCAL_reg(a, b) +#define hri_usbhost_clear_PADCAL_reg(a, b) hri_usb_clear_PADCAL_reg(a, b) +#define hri_usbhost_toggle_PADCAL_reg(a, b) hri_usb_toggle_PADCAL_reg(a, b) +#define hri_usbhost_read_PADCAL_reg(a) hri_usb_read_PADCAL_reg(a) +#define hri_usbdevice_get_SYNCBUSY_SWRST_bit(a) hri_usb_get_SYNCBUSY_SWRST_bit(a) +#define hri_usbdevice_get_SYNCBUSY_ENABLE_bit(a) hri_usb_get_SYNCBUSY_ENABLE_bit(a) +#define hri_usbdevice_get_SYNCBUSY_reg(a, b) hri_usb_get_SYNCBUSY_reg(a, b) +#define hri_usbdevice_read_SYNCBUSY_reg(a) hri_usb_read_SYNCBUSY_reg(a) +#define hri_usbdevice_get_FSMSTATUS_FSMSTATE_bf(a, b) hri_usb_get_FSMSTATUS_FSMSTATE_bf(a, b) +#define hri_usbdevice_read_FSMSTATUS_FSMSTATE_bf(a) hri_usb_read_FSMSTATUS_FSMSTATE_bf(a) +#define hri_usbdevice_get_FSMSTATUS_reg(a, b) hri_usb_get_FSMSTATUS_reg(a, b) +#define hri_usbdevice_read_FSMSTATUS_reg(a) hri_usb_read_FSMSTATUS_reg(a) +#define hri_usbdevice_set_CTRLA_SWRST_bit(a) hri_usb_set_CTRLA_SWRST_bit(a) +#define hri_usbdevice_get_CTRLA_SWRST_bit(a) hri_usb_get_CTRLA_SWRST_bit(a) +#define hri_usbdevice_set_CTRLA_ENABLE_bit(a) hri_usb_set_CTRLA_ENABLE_bit(a) +#define hri_usbdevice_get_CTRLA_ENABLE_bit(a) hri_usb_get_CTRLA_ENABLE_bit(a) +#define hri_usbdevice_write_CTRLA_ENABLE_bit(a, b) hri_usb_write_CTRLA_ENABLE_bit(a, b) +#define hri_usbdevice_clear_CTRLA_ENABLE_bit(a) hri_usb_clear_CTRLA_ENABLE_bit(a) +#define hri_usbdevice_toggle_CTRLA_ENABLE_bit(a) hri_usb_toggle_CTRLA_ENABLE_bit(a) +#define hri_usbdevice_set_CTRLA_RUNSTDBY_bit(a) hri_usb_set_CTRLA_RUNSTDBY_bit(a) +#define hri_usbdevice_get_CTRLA_RUNSTDBY_bit(a) hri_usb_get_CTRLA_RUNSTDBY_bit(a) +#define hri_usbdevice_write_CTRLA_RUNSTDBY_bit(a, b) hri_usb_write_CTRLA_RUNSTDBY_bit(a, b) +#define hri_usbdevice_clear_CTRLA_RUNSTDBY_bit(a) hri_usb_clear_CTRLA_RUNSTDBY_bit(a) +#define hri_usbdevice_toggle_CTRLA_RUNSTDBY_bit(a) hri_usb_toggle_CTRLA_RUNSTDBY_bit(a) +#define hri_usbdevice_set_CTRLA_MODE_bit(a) hri_usb_set_CTRLA_MODE_bit(a) +#define hri_usbdevice_get_CTRLA_MODE_bit(a) hri_usb_get_CTRLA_MODE_bit(a) +#define hri_usbdevice_write_CTRLA_MODE_bit(a, b) hri_usb_write_CTRLA_MODE_bit(a, b) +#define hri_usbdevice_clear_CTRLA_MODE_bit(a) hri_usb_clear_CTRLA_MODE_bit(a) +#define hri_usbdevice_toggle_CTRLA_MODE_bit(a) hri_usb_toggle_CTRLA_MODE_bit(a) +#define hri_usbdevice_set_CTRLA_reg(a, b) hri_usb_set_CTRLA_reg(a, b) +#define hri_usbdevice_get_CTRLA_reg(a, b) hri_usb_get_CTRLA_reg(a, b) +#define hri_usbdevice_write_CTRLA_reg(a, b) hri_usb_write_CTRLA_reg(a, b) +#define hri_usbdevice_clear_CTRLA_reg(a, b) hri_usb_clear_CTRLA_reg(a, b) +#define hri_usbdevice_toggle_CTRLA_reg(a, b) hri_usb_toggle_CTRLA_reg(a, b) +#define hri_usbdevice_read_CTRLA_reg(a) hri_usb_read_CTRLA_reg(a) +#define hri_usbdevice_set_QOSCTRL_CQOS_bf(a, b) hri_usb_set_QOSCTRL_CQOS_bf(a, b) +#define hri_usbdevice_get_QOSCTRL_CQOS_bf(a, b) hri_usb_get_QOSCTRL_CQOS_bf(a, b) +#define hri_usbdevice_write_QOSCTRL_CQOS_bf(a, b) hri_usb_write_QOSCTRL_CQOS_bf(a, b) +#define hri_usbdevice_clear_QOSCTRL_CQOS_bf(a, b) hri_usb_clear_QOSCTRL_CQOS_bf(a, b) +#define hri_usbdevice_toggle_QOSCTRL_CQOS_bf(a, b) hri_usb_toggle_QOSCTRL_CQOS_bf(a, b) +#define hri_usbdevice_read_QOSCTRL_CQOS_bf(a) hri_usb_read_QOSCTRL_CQOS_bf(a) +#define hri_usbdevice_set_QOSCTRL_DQOS_bf(a, b) hri_usb_set_QOSCTRL_DQOS_bf(a, b) +#define hri_usbdevice_get_QOSCTRL_DQOS_bf(a, b) hri_usb_get_QOSCTRL_DQOS_bf(a, b) +#define hri_usbdevice_write_QOSCTRL_DQOS_bf(a, b) hri_usb_write_QOSCTRL_DQOS_bf(a, b) +#define hri_usbdevice_clear_QOSCTRL_DQOS_bf(a, b) hri_usb_clear_QOSCTRL_DQOS_bf(a, b) +#define hri_usbdevice_toggle_QOSCTRL_DQOS_bf(a, b) hri_usb_toggle_QOSCTRL_DQOS_bf(a, b) +#define hri_usbdevice_read_QOSCTRL_DQOS_bf(a) hri_usb_read_QOSCTRL_DQOS_bf(a) +#define hri_usbdevice_set_QOSCTRL_reg(a, b) hri_usb_set_QOSCTRL_reg(a, b) +#define hri_usbdevice_get_QOSCTRL_reg(a, b) hri_usb_get_QOSCTRL_reg(a, b) +#define hri_usbdevice_write_QOSCTRL_reg(a, b) hri_usb_write_QOSCTRL_reg(a, b) +#define hri_usbdevice_clear_QOSCTRL_reg(a, b) hri_usb_clear_QOSCTRL_reg(a, b) +#define hri_usbdevice_toggle_QOSCTRL_reg(a, b) hri_usb_toggle_QOSCTRL_reg(a, b) +#define hri_usbdevice_read_QOSCTRL_reg(a) hri_usb_read_QOSCTRL_reg(a) +#define hri_usbdevice_set_DESCADD_DESCADD_bf(a, b) hri_usb_set_DESCADD_DESCADD_bf(a, b) +#define hri_usbdevice_get_DESCADD_DESCADD_bf(a, b) hri_usb_get_DESCADD_DESCADD_bf(a, b) +#define hri_usbdevice_write_DESCADD_DESCADD_bf(a, b) hri_usb_write_DESCADD_DESCADD_bf(a, b) +#define hri_usbdevice_clear_DESCADD_DESCADD_bf(a, b) hri_usb_clear_DESCADD_DESCADD_bf(a, b) +#define hri_usbdevice_toggle_DESCADD_DESCADD_bf(a, b) hri_usb_toggle_DESCADD_DESCADD_bf(a, b) +#define hri_usbdevice_read_DESCADD_DESCADD_bf(a) hri_usb_read_DESCADD_DESCADD_bf(a) +#define hri_usbdevice_set_DESCADD_reg(a, b) hri_usb_set_DESCADD_reg(a, b) +#define hri_usbdevice_get_DESCADD_reg(a, b) hri_usb_get_DESCADD_reg(a, b) +#define hri_usbdevice_write_DESCADD_reg(a, b) hri_usb_write_DESCADD_reg(a, b) +#define hri_usbdevice_clear_DESCADD_reg(a, b) hri_usb_clear_DESCADD_reg(a, b) +#define hri_usbdevice_toggle_DESCADD_reg(a, b) hri_usb_toggle_DESCADD_reg(a, b) +#define hri_usbdevice_read_DESCADD_reg(a) hri_usb_read_DESCADD_reg(a) +#define hri_usbdevice_set_PADCAL_TRANSP_bf(a, b) hri_usb_set_PADCAL_TRANSP_bf(a, b) +#define hri_usbdevice_get_PADCAL_TRANSP_bf(a, b) hri_usb_get_PADCAL_TRANSP_bf(a, b) +#define hri_usbdevice_write_PADCAL_TRANSP_bf(a, b) hri_usb_write_PADCAL_TRANSP_bf(a, b) +#define hri_usbdevice_clear_PADCAL_TRANSP_bf(a, b) hri_usb_clear_PADCAL_TRANSP_bf(a, b) +#define hri_usbdevice_toggle_PADCAL_TRANSP_bf(a, b) hri_usb_toggle_PADCAL_TRANSP_bf(a, b) +#define hri_usbdevice_read_PADCAL_TRANSP_bf(a) hri_usb_read_PADCAL_TRANSP_bf(a) +#define hri_usbdevice_set_PADCAL_TRANSN_bf(a, b) hri_usb_set_PADCAL_TRANSN_bf(a, b) +#define hri_usbdevice_get_PADCAL_TRANSN_bf(a, b) hri_usb_get_PADCAL_TRANSN_bf(a, b) +#define hri_usbdevice_write_PADCAL_TRANSN_bf(a, b) hri_usb_write_PADCAL_TRANSN_bf(a, b) +#define hri_usbdevice_clear_PADCAL_TRANSN_bf(a, b) hri_usb_clear_PADCAL_TRANSN_bf(a, b) +#define hri_usbdevice_toggle_PADCAL_TRANSN_bf(a, b) hri_usb_toggle_PADCAL_TRANSN_bf(a, b) +#define hri_usbdevice_read_PADCAL_TRANSN_bf(a) hri_usb_read_PADCAL_TRANSN_bf(a) +#define hri_usbdevice_set_PADCAL_TRIM_bf(a, b) hri_usb_set_PADCAL_TRIM_bf(a, b) +#define hri_usbdevice_get_PADCAL_TRIM_bf(a, b) hri_usb_get_PADCAL_TRIM_bf(a, b) +#define hri_usbdevice_write_PADCAL_TRIM_bf(a, b) hri_usb_write_PADCAL_TRIM_bf(a, b) +#define hri_usbdevice_clear_PADCAL_TRIM_bf(a, b) hri_usb_clear_PADCAL_TRIM_bf(a, b) +#define hri_usbdevice_toggle_PADCAL_TRIM_bf(a, b) hri_usb_toggle_PADCAL_TRIM_bf(a, b) +#define hri_usbdevice_read_PADCAL_TRIM_bf(a) hri_usb_read_PADCAL_TRIM_bf(a) +#define hri_usbdevice_set_PADCAL_reg(a, b) hri_usb_set_PADCAL_reg(a, b) +#define hri_usbdevice_get_PADCAL_reg(a, b) hri_usb_get_PADCAL_reg(a, b) +#define hri_usbdevice_write_PADCAL_reg(a, b) hri_usb_write_PADCAL_reg(a, b) +#define hri_usbdevice_clear_PADCAL_reg(a, b) hri_usb_clear_PADCAL_reg(a, b) +#define hri_usbdevice_toggle_PADCAL_reg(a, b) hri_usb_toggle_PADCAL_reg(a, b) +#define hri_usbdevice_read_PADCAL_reg(a) hri_usb_read_PADCAL_reg(a) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_USB_L21_H_INCLUDED */ +#endif /* _SAML21_USB_COMPONENT_ */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_wdt_l21.h b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_wdt_l21.h new file mode 100644 index 00000000..f4148c3f --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/hri/hri_wdt_l21.h @@ -0,0 +1,617 @@ +/** + * \file + * + * \brief SAM WDT + * + * Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAML21_WDT_COMPONENT_ +#ifndef _HRI_WDT_L21_H_INCLUDED_ +#define _HRI_WDT_L21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_WDT_CRITICAL_SECTIONS) +#define WDT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define WDT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define WDT_CRITICAL_SECTION_ENTER() +#define WDT_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_wdt_syncbusy_reg_t; +typedef uint8_t hri_wdt_clear_reg_t; +typedef uint8_t hri_wdt_config_reg_t; +typedef uint8_t hri_wdt_ctrla_reg_t; +typedef uint8_t hri_wdt_ewctrl_reg_t; +typedef uint8_t hri_wdt_intenset_reg_t; +typedef uint8_t hri_wdt_intflag_reg_t; + +static inline void hri_wdt_wait_for_sync(const void *const hw, hri_wdt_syncbusy_reg_t reg) +{ + while (((Wdt *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_wdt_is_syncing(const void *const hw, hri_wdt_syncbusy_reg_t reg) +{ + return ((Wdt *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_wdt_get_INTFLAG_EW_bit(const void *const hw) +{ + return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos; +} + +static inline void hri_wdt_clear_INTFLAG_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW; +} + +static inline bool hri_wdt_get_interrupt_EW_bit(const void *const hw) +{ + return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos; +} + +static inline void hri_wdt_clear_interrupt_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW; +} + +static inline hri_wdt_intflag_reg_t hri_wdt_get_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_wdt_intflag_reg_t hri_wdt_read_INTFLAG_reg(const void *const hw) +{ + return ((Wdt *)hw)->INTFLAG.reg; +} + +static inline void hri_wdt_clear_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask) +{ + ((Wdt *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_wdt_set_INTEN_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW; +} + +static inline bool hri_wdt_get_INTEN_EW_bit(const void *const hw) +{ + return (((Wdt *)hw)->INTENSET.reg & WDT_INTENSET_EW) >> WDT_INTENSET_EW_Pos; +} + +static inline void hri_wdt_write_INTEN_EW_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW; + } else { + ((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW; + } +} + +static inline void hri_wdt_clear_INTEN_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW; +} + +static inline void hri_wdt_set_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) +{ + ((Wdt *)hw)->INTENSET.reg = mask; +} + +static inline hri_wdt_intenset_reg_t hri_wdt_get_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_wdt_intenset_reg_t hri_wdt_read_INTEN_reg(const void *const hw) +{ + return ((Wdt *)hw)->INTENSET.reg; +} + +static inline void hri_wdt_write_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t data) +{ + ((Wdt *)hw)->INTENSET.reg = data; + ((Wdt *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_wdt_clear_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) +{ + ((Wdt *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_wdt_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ENABLE) >> WDT_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_wdt_get_SYNCBUSY_WEN_bit(const void *const hw) +{ + return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_WEN) >> WDT_SYNCBUSY_WEN_Pos; +} + +static inline bool hri_wdt_get_SYNCBUSY_ALWAYSON_bit(const void *const hw) +{ + return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ALWAYSON) >> WDT_SYNCBUSY_ALWAYSON_Pos; +} + +static inline bool hri_wdt_get_SYNCBUSY_CLEAR_bit(const void *const hw) +{ + return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_CLEAR) >> WDT_SYNCBUSY_CLEAR_Pos; +} + +static inline hri_wdt_syncbusy_reg_t hri_wdt_get_SYNCBUSY_reg(const void *const hw, hri_wdt_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Wdt *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_wdt_syncbusy_reg_t hri_wdt_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Wdt *)hw)->SYNCBUSY.reg; +} + +static inline void hri_wdt_set_CTRLA_ENABLE_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ENABLE; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_wdt_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp = (tmp & WDT_CTRLA_ENABLE) >> WDT_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_wdt_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp &= ~WDT_CTRLA_ENABLE; + tmp |= value << WDT_CTRLA_ENABLE_Pos; + ((Wdt *)hw)->CTRLA.reg = tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ENABLE; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ENABLE; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_set_CTRLA_WEN_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_WEN; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_wdt_get_CTRLA_WEN_bit(const void *const hw) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp = (tmp & WDT_CTRLA_WEN) >> WDT_CTRLA_WEN_Pos; + return (bool)tmp; +} + +static inline void hri_wdt_write_CTRLA_WEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp &= ~WDT_CTRLA_WEN; + tmp |= value << WDT_CTRLA_WEN_Pos; + ((Wdt *)hw)->CTRLA.reg = tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRLA_WEN_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_WEN; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRLA_WEN_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_WEN; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_set_CTRLA_ALWAYSON_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ALWAYSON; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_wdt_get_CTRLA_ALWAYSON_bit(const void *const hw) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp = (tmp & WDT_CTRLA_ALWAYSON) >> WDT_CTRLA_ALWAYSON_Pos; + return (bool)tmp; +} + +static inline void hri_wdt_write_CTRLA_ALWAYSON_bit(const void *const hw, bool value) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp &= ~WDT_CTRLA_ALWAYSON; + tmp |= value << WDT_CTRLA_ALWAYSON_Pos; + ((Wdt *)hw)->CTRLA.reg = tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRLA_ALWAYSON_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ALWAYSON; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRLA_ALWAYSON_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ALWAYSON; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_set_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg |= mask; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ctrla_reg_t hri_wdt_get_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_wdt_write_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg = data; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg &= ~mask; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg ^= mask; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ctrla_reg_t hri_wdt_read_CTRLA_reg(const void *const hw) +{ + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + return ((Wdt *)hw)->CTRLA.reg; +} + +static inline void hri_wdt_set_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_PER(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_PER(mask)) >> WDT_CONFIG_PER_Pos; + return tmp; +} + +static inline void hri_wdt_write_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t data) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp &= ~WDT_CONFIG_PER_Msk; + tmp |= WDT_CONFIG_PER(data); + ((Wdt *)hw)->CONFIG.reg = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_PER(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_PER(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_PER_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_PER_Msk) >> WDT_CONFIG_PER_Pos; + return tmp; +} + +static inline void hri_wdt_set_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_WINDOW(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_WINDOW(mask)) >> WDT_CONFIG_WINDOW_Pos; + return tmp; +} + +static inline void hri_wdt_write_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t data) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp &= ~WDT_CONFIG_WINDOW_Msk; + tmp |= WDT_CONFIG_WINDOW(data); + ((Wdt *)hw)->CONFIG.reg = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_WINDOW(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_WINDOW(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_WINDOW_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_WINDOW_Msk) >> WDT_CONFIG_WINDOW_Pos; + return tmp; +} + +static inline void hri_wdt_set_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg |= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_wdt_write_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg = data; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg &= ~mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg ^= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_reg(const void *const hw) +{ + return ((Wdt *)hw)->CONFIG.reg; +} + +static inline void hri_wdt_set_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg |= WDT_EWCTRL_EWOFFSET(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp = (tmp & WDT_EWCTRL_EWOFFSET(mask)) >> WDT_EWCTRL_EWOFFSET_Pos; + return tmp; +} + +static inline void hri_wdt_write_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t data) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp &= ~WDT_EWCTRL_EWOFFSET_Msk; + tmp |= WDT_EWCTRL_EWOFFSET(data); + ((Wdt *)hw)->EWCTRL.reg = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg &= ~WDT_EWCTRL_EWOFFSET(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg ^= WDT_EWCTRL_EWOFFSET(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_EWOFFSET_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp = (tmp & WDT_EWCTRL_EWOFFSET_Msk) >> WDT_EWCTRL_EWOFFSET_Pos; + return tmp; +} + +static inline void hri_wdt_set_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg |= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_wdt_write_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg = data; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg &= ~mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg ^= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_reg(const void *const hw) +{ + return ((Wdt *)hw)->EWCTRL.reg; +} + +static inline void hri_wdt_write_CLEAR_reg(const void *const hw, hri_wdt_clear_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CLEAR.reg = data; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_CLEAR); + WDT_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_WDT_L21_H_INCLUDED */ +#endif /* _SAML21_WDT_COMPONENT_ */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/main.c b/prototype/firmware/I2C_scanner/I2C_scanner/main.c new file mode 100644 index 00000000..f7da63b1 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/main.c @@ -0,0 +1,65 @@ +/* Discover devices on the I2C Bus */ + +#include + +int main(void) +{ + /* Initializes MCU, drivers and middleware */ + atmel_start_init(); + + /* Initialise UART for stdio*/ + + + usart_sync_enable(&TARGET_IO); + stdio_io_init(&TARGET_IO.io); + + + /* Write Header */ + printf("\r\nI2C Scanner\r\n\n"); + + /* Initialise I2C */ + + struct io_descriptor *I2C_io; + struct _i2c_m_msg msg; + uint8_t reg; + + i2c_m_sync_get_io_descriptor(&I2C_0, &I2C_io); + i2c_m_sync_enable(&I2C_0); + + msg.len = 1; + msg.flags = I2C_M_STOP; + msg.buffer = ® + + + + while (1) { + uint8_t address; + int16_t nDevices; + int32_t error; + + printf("Scanning...\r\n"); + nDevices = 0; + for(address = 8; address < 120; address++ ) + { + msg.addr = address; + + error = i2c_m_sync_transfer(&I2C_0, &msg); + if (error == 0) + { + printf("I2C device found at 0x%x\r\n", address); + + + nDevices++; + } + + } + if (nDevices == 0) + printf("No devices found !\r\n"); + else + printf("done\r\n\n"); + + delay_ms(5000); // wait 5 seconds for next scan + + + } +} diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/stdio_redirect/gcc/read.c b/prototype/firmware/I2C_scanner/I2C_scanner/stdio_redirect/gcc/read.c new file mode 100644 index 00000000..90e46183 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/stdio_redirect/gcc/read.c @@ -0,0 +1,53 @@ +/** + * \file + * + * \brief STDIO redirection + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +int __attribute__((weak)) _read(int file, char *ptr, int len); /* Remove GCC compiler warning */ + +int __attribute__((weak)) _read(int file, char *ptr, int len) +{ + int n = 0; + + if (file != 0) { + return -1; + } + + n = stdio_io_read((uint8_t *)ptr, len); + if (n < 0) { + return -1; + } + + return n; +} diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/stdio_redirect/gcc/write.c b/prototype/firmware/I2C_scanner/I2C_scanner/stdio_redirect/gcc/write.c new file mode 100644 index 00000000..44fa815a --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/stdio_redirect/gcc/write.c @@ -0,0 +1,53 @@ +/** + * \file + * + * \brief STDIO redirection + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +int __attribute__((weak)) _write(int file, char *ptr, int len); /* Remove GCC compiler warning */ + +int __attribute__((weak)) _write(int file, char *ptr, int len) +{ + int n = 0; + + if ((file != 1) && (file != 2) && (file != 3)) { + return -1; + } + + n = stdio_io_write((const uint8_t *)ptr, len); + if (n < 0) { + return -1; + } + + return n; +} diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/stdio_redirect/stdio_io.c b/prototype/firmware/I2C_scanner/I2C_scanner/stdio_redirect/stdio_io.c new file mode 100644 index 00000000..7659f3d2 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/stdio_redirect/stdio_io.c @@ -0,0 +1,74 @@ +/** + * \file + * + * \brief STDIO redirection terminal + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** IO descriptor for STDIO access. */ +static struct io_descriptor *stdio_io = NULL; + +void stdio_io_init(struct io_descriptor *io) +{ +#if defined(__GNUC__) + /* Specify that stdout and stdin should not be buffered. */ + setbuf(stdout, NULL); + setbuf(stdin, NULL); + /* Note: Already the case in IAR's Normal DLIB default configuration + * and AVR GCC library: + * - printf() emits one character at a time. + * - getchar() requests only 1 byte to exit. + */ +#endif + stdio_io = io; +} + +void stdio_io_set_io(struct io_descriptor *io) +{ + stdio_io = io; +} + +int32_t stdio_io_read(uint8_t *buf, const int32_t len) +{ + if (stdio_io == NULL) { + return 0; + } + return io_read(stdio_io, buf, len); +} + +int32_t stdio_io_write(const uint8_t *buf, const int32_t len) +{ + if (stdio_io == NULL) { + return 0; + } + return io_write(stdio_io, buf, len); +} diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/stdio_redirect/stdio_io.h b/prototype/firmware/I2C_scanner/I2C_scanner/stdio_redirect/stdio_io.h new file mode 100644 index 00000000..973adad0 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/stdio_redirect/stdio_io.h @@ -0,0 +1,81 @@ +/** + * \file + * + * \brief STDIO redirection terminal + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _STDIO_IO_H_INCLUDED +#define _STDIO_IO_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** + * \brief Initialize STDIO access + * \param[in] io Pointer to IO descriptor, + * NULL to discard R/W without any error. + */ +void stdio_io_init(struct io_descriptor *io); + +/** + * \brief Change IO descriptor for terminal to R/W data + * \param[in] io Pointer to IO descriptor, + * NULL to discard R/W without any error. + */ +void stdio_io_set_io(struct io_descriptor *io); + +/** + * \brief Read through specified terminal + * \param[out] buf Pointer to buffer to place read data + * \param[in] len Data length in number of bytes + * \return status + * \retval >=0 number of bytes read + * \retval <0 error + */ +int32_t stdio_io_read(uint8_t *buf, const int32_t len); + +/** + * \brief Write through specified terminal + * \param[in] buf Pointer to buffer to place data to write + * \param[in] len Data length in number of bytes + * \return status + * \retval >=0 number of bytes read + * \retval <0 error + */ +int32_t stdio_io_write(const uint8_t *buf, const int32_t len); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* _STDIO_IO_H_INCLUDED */ diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/stdio_start.c b/prototype/firmware/I2C_scanner/I2C_scanner/stdio_start.c new file mode 100644 index 00000000..db8d3625 --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/stdio_start.c @@ -0,0 +1,23 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file or main.c + * to avoid loosing it when reconfiguring. + */ + +#include "atmel_start.h" +#include "stdio_start.h" + +void STDIO_REDIRECT_0_example(void) +{ + /* Print welcome message */ + printf("\r\nHello ATMEL World!\r\n"); +} + +void stdio_redirect_init(void) +{ + + usart_sync_enable(&TARGET_IO); + stdio_io_init(&TARGET_IO.io); +} diff --git a/prototype/firmware/I2C_scanner/I2C_scanner/stdio_start.h b/prototype/firmware/I2C_scanner/I2C_scanner/stdio_start.h new file mode 100644 index 00000000..bee5325b --- /dev/null +++ b/prototype/firmware/I2C_scanner/I2C_scanner/stdio_start.h @@ -0,0 +1,31 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file or main.c + * to avoid loosing it when reconfiguring. + */ +#ifndef STDIO_MAIN_H +#define STDIO_MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include + +#include +#include + +void STDIO_REDIRECT_0_example(void); + +/** + * \brief Initialize STDIO Redirect + */ +void stdio_redirect_init(void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STDIO_MAIN_H */ diff --git a/prototype/firmware/RFM98W/.vs/RFM95W/v14/.atsuo b/prototype/firmware/RFM98W/.vs/RFM95W/v14/.atsuo new file mode 100644 index 00000000..cc340ea6 Binary files /dev/null and b/prototype/firmware/RFM98W/.vs/RFM95W/v14/.atsuo differ diff --git a/prototype/firmware/RFM98W/.vs/RFM98W/v14/.atsuo b/prototype/firmware/RFM98W/.vs/RFM98W/v14/.atsuo new file mode 100644 index 00000000..9a43e882 Binary files /dev/null and b/prototype/firmware/RFM98W/.vs/RFM98W/v14/.atsuo differ diff --git a/prototype/firmware/RFM98W/RFM98W.atsln b/prototype/firmware/RFM98W/RFM98W.atsln new file mode 100644 index 00000000..2adc581d --- /dev/null +++ b/prototype/firmware/RFM98W/RFM98W.atsln @@ -0,0 +1,22 @@ + +Microsoft Visual Studio Solution File, Format Version 12.00 +# Atmel Studio Solution File, Format Version 11.00 +VisualStudioVersion = 14.0.23107.0 +MinimumVisualStudioVersion = 10.0.40219.1 +Project("{54F91283-7BC4-4236-8FF9-10F437C3AD48}") = "RFM98W", "RFM98W\RFM98W.cproj", "{DCE6C7E3-EE26-4D79-826B-08594B9AD897}" +EndProject +Global + GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug|ARM = Debug|ARM + Release|ARM = Release|ARM + EndGlobalSection + GlobalSection(ProjectConfigurationPlatforms) = postSolution + {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|ARM.ActiveCfg = Debug|ARM + {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|ARM.Build.0 = Debug|ARM + {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|ARM.ActiveCfg = Release|ARM + {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|ARM.Build.0 = Release|ARM + EndGlobalSection + GlobalSection(SolutionProperties) = preSolution + HideSolutionNode = FALSE + EndGlobalSection +EndGlobal diff --git a/prototype/firmware/RFM98W/RFM98W/.atmel-start-backup/RFM95W_1.zip b/prototype/firmware/RFM98W/RFM98W/.atmel-start-backup/RFM95W_1.zip new file mode 100644 index 00000000..b23c4623 Binary files /dev/null and b/prototype/firmware/RFM98W/RFM98W/.atmel-start-backup/RFM95W_1.zip differ diff --git a/prototype/firmware/RFM98W/RFM98W/.atmel-start-backup/RFM95W_2.zip b/prototype/firmware/RFM98W/RFM98W/.atmel-start-backup/RFM95W_2.zip new file mode 100644 index 00000000..c560419d Binary files /dev/null and b/prototype/firmware/RFM98W/RFM98W/.atmel-start-backup/RFM95W_2.zip differ diff --git a/prototype/firmware/RFM98W/RFM98W/.atmel-start-backup/RFM98W_8.zip b/prototype/firmware/RFM98W/RFM98W/.atmel-start-backup/RFM98W_8.zip new file mode 100644 index 00000000..a87e8d0c Binary files /dev/null and b/prototype/firmware/RFM98W/RFM98W/.atmel-start-backup/RFM98W_8.zip differ diff --git a/prototype/firmware/RFM98W/RFM98W/.atmelstart/AtmelStart.env_conf b/prototype/firmware/RFM98W/RFM98W/.atmelstart/AtmelStart.env_conf new file mode 100644 index 00000000..ecbeeb71 --- /dev/null +++ b/prototype/firmware/RFM98W/RFM98W/.atmelstart/AtmelStart.env_conf @@ -0,0 +1,6 @@ + + + + + + diff --git a/prototype/firmware/RFM98W/RFM98W/.atmelstart/AtmelStart.gpdsc b/prototype/firmware/RFM98W/RFM98W/.atmelstart/AtmelStart.gpdsc new file mode 100644 index 00000000..05073413 --- /dev/null +++ b/prototype/firmware/RFM98W/RFM98W/.atmelstart/AtmelStart.gpdsc @@ -0,0 +1,208 @@ + + Atmel + My Project + Project generated by Atmel Start + http://start.atmel.com/ + + Initial version + + + Configuration Files generated by Atmel Start + + + + Atmel Start +