diff --git a/Bootloader/Adapters/Inc/flash_adapter.h b/Bootloader/Adapters/Inc/flash_adapter.h index 64c1a08..d02fa80 100644 --- a/Bootloader/Adapters/Inc/flash_adapter.h +++ b/Bootloader/Adapters/Inc/flash_adapter.h @@ -40,9 +40,10 @@ #ifdef EXTERNAL_FLASH // Selecting where will firmware go -// TODO: add support for external flash chip -#define FIRMWARE_FLASH_SIZE_LIMIT (100000U) -#define PACKET_SIZE 256U //TODO: this time size is 256 and 64 byte package can fit in, Check in the future. +#define ENABLE_SSBL + +#define FIRMWARE_FLASH_SIZE_LIMIT (100000U) +#define PACKET_SIZE (256U) #else #define FIRMWARE_FLASH_SIZE_LIMIT (FLASH_SIZE - 0x8000u) //!< Max available flash size for firmware. Flash bank size - FW start address @@ -68,9 +69,11 @@ #define MAGIC_KEY_ADDRESS_FLASH (0x08020200UL) //!< Flash address in internal flash for communication between bootloader and firmware #define MAGIC_KEY_ADDRESS_RAM (0x20070000UL) //!< Flash address in ram for communication between bootloader and firmware #elif defined(STM32N6xx) -#define FLASH_FIRMWARE_ADDRESS (0x08020000UL) //!< Flash address where firmware will be written -#define FLASH_BOOTLOADER_ADDRESS (0x08000000UL) //!< Flash address where bootloader will be written +#define FLASH_FIRMWARE_ADDRESS (0x70200400UL) //!< Flash address where firmware will be written +#define FLASH_BOOTLOADER_ADDRESS (0x70100400UL) //!< Flash address where bootloader (SSBL) will be written #define RAM_FIRMWARE_ADDRESS (0x34000000UL) //!< RAM address where firmware will be written +#define FLASH_ADDRESS_BASE (0x70000000UL) //!< Address where the external flash starts +#define FLASH_ADDRESS_OFFSET (0x400UL) //!< For compatibility with the STM32 SigningTool header #else // UnitTest #define FLASH_FIRMWARE_ADDRESS (0x08020000UL) //!< Flash address where firmware will be written #define FLASH_BOOTLOADER_ADDRESS (0x08000000UL) //!< Flash address where bootloader will be written @@ -92,5 +95,8 @@ bool FlashAdapter_setReadProtection(bool enable); /* proprietary code readout protection */ bool FlashAdapter_setPCROP(bool enable, uint32_t protect_address_start, uint32_t protect_address_end); +#ifdef EXTERNAL_FLASH +void FlashAdapter_init(void); +#endif #endif /* BOOTLOADER_INC_FLASH_ADAPTER_H_ */ diff --git a/Bootloader/Adapters/Src/flash_adapter.c b/Bootloader/Adapters/Src/flash_adapter.c index d2b7848..7887d1b 100644 --- a/Bootloader/Adapters/Src/flash_adapter.c +++ b/Bootloader/Adapters/Src/flash_adapter.c @@ -58,28 +58,111 @@ HAL_StatusTypeDef ActivateProtection(FLASH_OBProgramInitTypeDef* ob_struct, uint #endif #ifdef EXTERNAL_FLASH + +#define MX25UM51245G_SECTOR_SIZE 0xFFF + +#include "extmem_manager.h" +#include "stm32_sfdp_driver_api.h" + +extern BOOTStatus_TypeDef MapMemory(void); + +extern EXTMEM_DefinitionTypeDef extmem_list_config[1]; + +XSPI_HandleTypeDef hxspi2; + +void +FlashAdapter_init(void) { + XSPIM_CfgTypeDef sXspiManagerCfg = {0}; + + /* XSPI2 parameter configuration*/ + hxspi2.Instance = XSPI2; + hxspi2.Init.FifoThresholdByte = 4; + hxspi2.Init.MemoryMode = HAL_XSPI_SINGLE_MEM; + hxspi2.Init.MemoryType = HAL_XSPI_MEMTYPE_MACRONIX; + hxspi2.Init.MemorySize = HAL_XSPI_SIZE_1GB; + hxspi2.Init.ChipSelectHighTimeCycle = 1; + hxspi2.Init.FreeRunningClock = HAL_XSPI_FREERUNCLK_DISABLE; + hxspi2.Init.ClockMode = HAL_XSPI_CLOCK_MODE_0; + hxspi2.Init.WrapSize = HAL_XSPI_WRAP_NOT_SUPPORTED; + hxspi2.Init.ClockPrescaler = 0; + hxspi2.Init.SampleShifting = HAL_XSPI_SAMPLE_SHIFT_NONE; + hxspi2.Init.DelayHoldQuarterCycle = HAL_XSPI_DHQC_ENABLE; + hxspi2.Init.ChipSelectBoundary = HAL_XSPI_BONDARYOF_NONE; + hxspi2.Init.MaxTran = 0; + hxspi2.Init.Refresh = 0; + hxspi2.Init.MemorySelect = HAL_XSPI_CSSEL_NCS1; + if (HAL_XSPI_Init(&hxspi2) != HAL_OK) { + Error_Handler(); + } + sXspiManagerCfg.nCSOverride = HAL_XSPI_CSSEL_OVR_NCS1; + sXspiManagerCfg.IOPort = HAL_XSPIM_IOPORT_2; + sXspiManagerCfg.Req2AckTime = 1; + if (HAL_XSPIM_Config(&hxspi2, &sXspiManagerCfg, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { + Error_Handler(); + } + + MX_EXTMEM_MANAGER_Init(); + MapMemory(); +} + bool FlashAdapter_erase(uint32_t firmware_size, uint32_t flash_address) { - //return W25q_dynamicErase(firmware_size, flash_address); - return true; + + bool success = false; + + uint32_t address = (flash_address - FLASH_ADDRESS_BASE - FLASH_ADDRESS_OFFSET); + + EXTMEM_DRIVER_NOR_SFDP_Disable_MemoryMappedMode(&(extmem_list_config->NorSfdpObject)); + + EXTMEM_StatusTypeDef retr = EXTMEM_EraseSector(EXTMEMORY_1, address, firmware_size + FLASH_ADDRESS_OFFSET); + + if (EXTMEM_OK == retr) { + success = true; + } + + EXTMEM_DRIVER_NOR_SFDP_Enable_MemoryMappedMode(&(extmem_list_config->NorSfdpObject)); + + return success; } bool FlashAdapter_blockErase(uint32_t address) { - //return W25q_blockErase64k(address); - return true; + return false; } bool FlashAdapter_program(uint32_t address, uint8_t* buffer, uint32_t length) { - //return W25q_quadPageProgram(address, buffer, length); - return true; + + bool success = false; + EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef ret = EXTMEM_DRIVER_NOR_SFDP_OK; + + address -= FLASH_ADDRESS_BASE; + + ret = EXTMEM_DRIVER_NOR_SFDP_Disable_MemoryMappedMode(&(extmem_list_config->NorSfdpObject)); + + if (EXTMEM_DRIVER_NOR_SFDP_OK == ret) { + ret = EXTMEM_DRIVER_NOR_SFDP_Write(&(extmem_list_config->NorSfdpObject), address, buffer, length); + + if (EXTMEM_DRIVER_NOR_SFDP_OK == ret) { + EXTMEM_DRIVER_NOR_SFDP_Enable_MemoryMappedMode(&(extmem_list_config->NorSfdpObject)); + } + } + + if (EXTMEM_DRIVER_NOR_SFDP_OK == ret) { + success = true; + } + + return success; } bool FlashAdapter_readBytes(uint32_t address, uint8_t* buffer, uint32_t length) { - //return W25q_readBytes(address, buffer, length); - return true; + + bool success = true; + // cppcheck-suppress misra-c2012-11.6; address is received as uint32_t + (void*)memcpy((void*)buffer, (void*)address, length); + + return success; } bool diff --git a/Bootloader/Adapters/Src/gpio_adapter.c b/Bootloader/Adapters/Src/gpio_adapter.c index a481be1..e842fa2 100644 --- a/Bootloader/Adapters/Src/gpio_adapter.c +++ b/Bootloader/Adapters/Src/gpio_adapter.c @@ -47,6 +47,7 @@ GpioAdapter_init(void) { __HAL_RCC_GPIOF_CLK_ENABLE(); #if defined(STM32N657xx) __HAL_RCC_GPIOG_CLK_ENABLE(); + __HAL_RCC_GPION_CLK_ENABLE(); #endif #if defined(LED1_Pin) && defined(LED1_Port) && defined(LED_OFF) diff --git a/Bootloader/Inc/signature.h b/Bootloader/Inc/signature.h index 9295bbb..88c5853 100644 --- a/Bootloader/Inc/signature.h +++ b/Bootloader/Inc/signature.h @@ -49,11 +49,12 @@ typedef struct signature { //! Enumeration for different signatures typedef enum signatureType_ENUM { - signatureType_FIRMWARE_FLASH = 0x00, //!< New firmware for FLASH - signatureType_FIRMWARE_RAM = 0x01, //!< Firmware for RAM - signatureType_BOOTLOADER_FLASH = 0x02, //!< New bootloader for FLASH - signatureType_BOOTLOADER_RAM = 0x03, //!< Bootloader for RAM - signatureType_UNKNOWN = 0xFF, //!< Not existing or unknown signature + signatureType_FIRMWARE_FLASH = 0x00, //!< New firmware for FLASH + signatureType_FIRMWARE_RAM = 0x01, //!< Firmware for RAM + signatureType_BOOTLOADER_INT_FLASH = 0x02, //!< New bootloader for Internal FLASH + signatureType_BOOTLOADER_RAM = 0x03, //!< Bootloader for RAM + signatureType_BOOTLOADER_EXT_FLASH = 0x04, //!< New bootloader for External FLASH + signatureType_UNKNOWN = 0xFF, //!< Not existing or unknown signature } signatureType_E; signatureType_E Signature_verification(const signature_S* signature); diff --git a/Bootloader/STM32/ExtMemManager/extmem_manager.c b/Bootloader/STM32/ExtMemManager/extmem_manager.c new file mode 100644 index 0000000..c52121c --- /dev/null +++ b/Bootloader/STM32/ExtMemManager/extmem_manager.c @@ -0,0 +1,77 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : extmem_manager.c + * @version : 1.0.0 + * @brief : This file implements the extmem configuration + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "extmem_manager.h" +#include + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN PV */ +/* Private variables ---------------------------------------------------------*/ + +/* USER CODE END PV */ + +/* USER CODE BEGIN PFP */ +/* Private function prototypes -----------------------------------------------*/ + +/* USER CODE END PFP */ + +/* + * -- Insert your variables declaration here -- + */ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* + * -- Insert your external function declaration here -- + */ +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/** + * Init External memory manager + * @retval None + */ +void +MX_EXTMEM_MANAGER_Init(void) { + + /* USER CODE BEGIN MX_EXTMEM_Init_PreTreatment */ + + /* USER CODE END MX_EXTMEM_Init_PreTreatment */ + + /* Initialization of the memory parameters */ + memset(extmem_list_config, 0x0, sizeof(extmem_list_config)); + + /* EXTMEMORY_1 */ + extmem_list_config[0].MemType = EXTMEM_NOR_SFDP; + extmem_list_config[0].Handle = (void*)&hxspi2; + extmem_list_config[0].ConfigType = EXTMEM_LINK_CONFIG_8LINES; + + EXTMEM_Init(EXTMEMORY_1, HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_XSPI2)); + + /* USER CODE BEGIN MX_EXTMEM_Init_PostTreatment */ + + /* USER CODE END MX_EXTMEM_Init_PostTreatment */ +} diff --git a/Bootloader/STM32/ExtMemManager/extmem_manager.h b/Bootloader/STM32/ExtMemManager/extmem_manager.h new file mode 100644 index 0000000..dbedded --- /dev/null +++ b/Bootloader/STM32/ExtMemManager/extmem_manager.h @@ -0,0 +1,67 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : extmem_manager.h + * @version : 1.0.0 + * @brief : Header for secure_manager_api.c file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MX_EXTMEM__H__ +#define __MX_EXTMEM__H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_extmem_conf.h" + +/* USER CODE BEGIN INCLUDE */ + +/* USER CODE END INCLUDE */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* + * -- Insert your variables declaration here -- + */ +/* USER CODE BEGIN VARIABLES */ + +/* USER CODE END VARIABLES */ + +void MX_EXTMEM_MANAGER_Init(void); + +/* + * -- Insert functions declaration here -- + */ +/* USER CODE BEGIN FD */ + +/* USER CODE END FD */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MX_EXTMEM__H__ */ + diff --git a/Bootloader/STM32/ExtMemManager/stm32_extmem_conf.h b/Bootloader/STM32/ExtMemManager/stm32_extmem_conf.h new file mode 100644 index 0000000..6673752 --- /dev/null +++ b/Bootloader/STM32/ExtMemManager/stm32_extmem_conf.h @@ -0,0 +1,121 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : stm32_extmem_conf.h + * @version : 1.0.0 + * @brief : Header for extmem.c file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_EXTMEM_CONF__H__ +#define __STM32_EXTMEM_CONF__H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + +/* + @brief management of the driver layer enable +*/ + +#define EXTMEM_DRIVER_NOR_SFDP 1 +#define EXTMEM_DRIVER_PSRAM 0 +#define EXTMEM_DRIVER_SDCARD 0 +#define EXTMEM_DRIVER_USER 0 + +/* + @brief management of the sal layer enable +*/ +#define EXTMEM_SAL_XSPI 1 +#define EXTMEM_SAL_SD 0 + +/* Includes ------------------------------------------------------------------*/ +#include "stm32n6xx_hal.h" + +#include "stm32_extmem_type.h" +#include "boot/stm32_boot_lrun.h" + +/* USER CODE BEGIN INCLUDE */ + +/* USER CODE END INCLUDE */ +/* Private variables ---------------------------------------------------------*/ +extern XSPI_HandleTypeDef hxspi2; + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTMEM_CONF_Exported_constants EXTMEM_CONF exported constants + * @{ + */ +enum { + EXTMEMORY_1 = 0 /*!< ID=0 for the first memory */ +}; + +/* + @brief management of the boot layer +*/ + +#define EXTMEM_LRUN_SOURCE EXTMEMORY_1 +#define EXTMEM_LRUN_SOURCE_ADDRESS 0x00100000u +#define EXTMEM_LRUN_SOURCE_SIZE 0x10000u +#define EXTMEM_LRUN_DESTINATION_INTERNAL 1 +#define EXTMEM_LRUN_DESTINATION_ADDRESS 0x34000000u + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Exported configuration --------------------------------------------------------*/ +/** @defgroup EXTMEM_CONF_Exported_configuration EXTMEM_CONF exported configuration definition + * @{ + */ + +extern EXTMEM_DefinitionTypeDef extmem_list_config[1]; +#if defined(EXTMEM_C) +EXTMEM_DefinitionTypeDef extmem_list_config[1]; +#endif /* EXTMEM_C */ + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* + * -- Insert your variables declaration here -- + */ +/* USER CODE BEGIN VARIABLES */ + +/* USER CODE END VARIABLES */ + +/* + * -- Insert functions declaration here -- + */ +/* USER CODE BEGIN FD */ + +/* USER CODE END FD */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32_EXTMEM_CONF__H__ */ diff --git a/Bootloader/STM32/Inc/stm32n6xx_hal_conf.h b/Bootloader/STM32/Inc/stm32n6xx_hal_conf.h index 4ee99f5..8993cbe 100644 --- a/Bootloader/STM32/Inc/stm32n6xx_hal_conf.h +++ b/Bootloader/STM32/Inc/stm32n6xx_hal_conf.h @@ -80,7 +80,7 @@ extern "C" { #define HAL_UART_MODULE_ENABLED /*#define HAL_USART_MODULE_ENABLED */ /*#define HAL_WWDG_MODULE_ENABLED */ -/*#define HAL_XSPI_MODULE_ENABLED */ +#define HAL_XSPI_MODULE_ENABLED /*#define HAL_CACHEAXI_MODULE_ENABLED */ /*#define HAL_MDIOS_MODULE_ENABLED */ /*#define HAL_GPU2D_MODULE_ENABLED */ diff --git a/Bootloader/STM32/Src/stm32n6xx_hal_msp.c b/Bootloader/STM32/Src/stm32n6xx_hal_msp.c index f279ab3..d0b7d92 100644 --- a/Bootloader/STM32/Src/stm32n6xx_hal_msp.c +++ b/Bootloader/STM32/Src/stm32n6xx_hal_msp.c @@ -80,6 +80,92 @@ HAL_MspInit(void) { /* USER CODE END MspInit 1 */ } +void +HAL_XSPI_MspInit(XSPI_HandleTypeDef* hxspi) { + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + if (hxspi->Instance == XSPI2) { + /* USER CODE BEGIN XSPI2_MspInit 0 */ + + /* USER CODE END XSPI2_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_XSPI2; + PeriphClkInitStruct.Xspi2ClockSelection = RCC_XSPI2CLKSOURCE_IC3; + PeriphClkInitStruct.ICSelection[RCC_IC3].ClockSelection = RCC_ICCLKSOURCE_PLL1; + PeriphClkInitStruct.ICSelection[RCC_IC3].ClockDivider = 48; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + Error_Handler(); + } + + /* Peripheral clock enable */ + __HAL_RCC_XSPIM_CLK_ENABLE(); + __HAL_RCC_XSPI2_CLK_ENABLE(); + + __HAL_RCC_GPION_CLK_ENABLE(); + /**XSPI2 GPIO Configuration + PN4 ------> XSPIM_P2_IO2 + PN6 ------> XSPIM_P2_CLK + PN8 ------> XSPIM_P2_IO4 + PN0 ------> XSPIM_P2_DQS0 + PN3 ------> XSPIM_P2_IO1 + PN5 ------> XSPIM_P2_IO3 + PN1 ------> XSPIM_P2_NCS1 + PN9 ------> XSPIM_P2_IO5 + PN2 ------> XSPIM_P2_IO0 + PN10 ------> XSPIM_P2_IO6 + PN11 ------> XSPIM_P2_IO7 + */ + GPIO_InitStruct.Pin = GPIO_PIN_4 | GPIO_PIN_6 | GPIO_PIN_8 | GPIO_PIN_0 + | GPIO_PIN_3 | GPIO_PIN_5 | GPIO_PIN_1 | GPIO_PIN_9 + | GPIO_PIN_2 | GPIO_PIN_10 | GPIO_PIN_11; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF9_XSPIM_P2; + HAL_GPIO_Init(GPION, &GPIO_InitStruct); + + /* USER CODE BEGIN XSPI2_MspInit 1 */ + + /* USER CODE END XSPI2_MspInit 1 */ + + } +} + +void +HAL_XSPI_MspDeInit(XSPI_HandleTypeDef* hxspi) { + if (hxspi->Instance == XSPI2) { + /* USER CODE BEGIN XSPI2_MspDeInit 0 */ + + /* USER CODE END XSPI2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_XSPIM_CLK_DISABLE(); + __HAL_RCC_XSPI2_CLK_DISABLE(); + + /**XSPI2 GPIO Configuration + PN4 ------> XSPIM_P2_IO2 + PN6 ------> XSPIM_P2_CLK + PN8 ------> XSPIM_P2_IO4 + PN0 ------> XSPIM_P2_DQS0 + PN3 ------> XSPIM_P2_IO1 + PN5 ------> XSPIM_P2_IO3 + PN1 ------> XSPIM_P2_NCS1 + PN9 ------> XSPIM_P2_IO5 + PN2 ------> XSPIM_P2_IO0 + PN10 ------> XSPIM_P2_IO6 + PN11 ------> XSPIM_P2_IO7 + */ + HAL_GPIO_DeInit(GPION, GPIO_PIN_4 | GPIO_PIN_6 | GPIO_PIN_8 | GPIO_PIN_0 + | GPIO_PIN_3 | GPIO_PIN_5 | GPIO_PIN_1 | GPIO_PIN_9 + | GPIO_PIN_2 | GPIO_PIN_10 | GPIO_PIN_11); + + /* USER CODE BEGIN XSPI2_MspDeInit 1 */ + + /* USER CODE END XSPI2_MspDeInit 1 */ + } +} + /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ diff --git a/Bootloader/Src/binary_update.c b/Bootloader/Src/binary_update.c index c538d5b..0272fc2 100644 --- a/Bootloader/Src/binary_update.c +++ b/Bootloader/Src/binary_update.c @@ -58,7 +58,8 @@ BinaryUpdate_handleDetectedBinary(signatureType_E detected_binary) { s_address = FLASH_FIRMWARE_ADDRESS; break; - case signatureType_BOOTLOADER_FLASH: + case signatureType_BOOTLOADER_INT_FLASH: + case signatureType_BOOTLOADER_EXT_FLASH: s_address = FLASH_BOOTLOADER_ADDRESS; break; @@ -91,7 +92,11 @@ BinaryUpdate_handleBootInfo(void) { break; default: +#if defined(ENABLE_SSBL) + boot_info.jump_address = FLASH_BOOTLOADER_ADDRESS; +#else boot_info.jump_address = FLASH_FIRMWARE_ADDRESS; +#endif boot_info.skip_bl_loop = false; break; } @@ -126,13 +131,20 @@ BinaryUpdate_erase(uint32_t firmware_size) { case signatureType_FIRMWARE_FLASH: success = FlashAdapter_erase(firmware_size, s_address); break; - case signatureType_BOOTLOADER_FLASH: + case signatureType_BOOTLOADER_INT_FLASH: if (boot_info.jump_address == RAM_FIRMWARE_ADDRESS) { //Only allowed to erase if RAM version is running success = FlashAdapter_erase(firmware_size, s_address); } break; + case signatureType_BOOTLOADER_EXT_FLASH: + if (boot_info.jump_address == FLASH_BOOTLOADER_ADDRESS) { + //Only allowed to erase if RAM version is running + success = FlashAdapter_erase(firmware_size, s_address); + } + break; + case signatureType_FIRMWARE_RAM: case signatureType_BOOTLOADER_RAM: break; @@ -187,7 +199,8 @@ BinaryUpdate_write(uint8_t* write_buffer, const uint32_t packet_length) { switch (s_detected_binary) { case signatureType_FIRMWARE_FLASH: - case signatureType_BOOTLOADER_FLASH: + case signatureType_BOOTLOADER_INT_FLASH: + case signatureType_BOOTLOADER_EXT_FLASH: case signatureType_UNKNOWN: success = BinaryUpdate_writeToFlash(data, data_length); break; @@ -230,11 +243,16 @@ BinaryUpdate_finish(void) { boot_info.skip_bl_loop = false; break; - case signatureType_BOOTLOADER_FLASH: + case signatureType_BOOTLOADER_INT_FLASH: boot_info.jump_address = FLASH_FIRMWARE_ADDRESS; boot_info.skip_bl_loop = false; break; + case signatureType_BOOTLOADER_EXT_FLASH: + boot_info.jump_address = FLASH_BOOTLOADER_ADDRESS; + boot_info.skip_bl_loop = false; + break; + case signatureType_BOOTLOADER_RAM: boot_info.jump_address = RAM_FIRMWARE_ADDRESS; boot_info.skip_bl_loop = true; diff --git a/Bootloader/Src/main.c b/Bootloader/Src/main.c index 5c2593d..cd6c90f 100644 --- a/Bootloader/Src/main.c +++ b/Bootloader/Src/main.c @@ -59,6 +59,10 @@ main(void) { BinaryUpdate_handleBootInfo(); bool enter_bootloader_loop = false; +#ifdef EXTERNAL_FLASH + FlashAdapter_init(); +#endif + #ifdef SECURED if (!FlashAdapter_isFlashRDPProtected()) { @@ -119,9 +123,7 @@ main(void) { GpioAdapter_led1Off(); -#if defined(STM32N657xx) - JumpToAddress(); -#else +#if !defined(STM32N657xx) SystemAdapter_reset(); #endif diff --git a/Bootloader/Src/signature.c b/Bootloader/Src/signature.c index bb2a874..738833c 100644 --- a/Bootloader/Src/signature.c +++ b/Bootloader/Src/signature.c @@ -38,7 +38,11 @@ static const uint64_t signature_magic_key = 0xDEC0DE5528101987; //!< First 8 __attribute__ ((section(".bl_flash_signature"))) signature_S bl_flash_signature = { .magic_key = signature_magic_key, - .type = signatureType_BOOTLOADER_FLASH +#if defined (EXTERNAL_FLASH) + .type = signatureType_BOOTLOADER_EXT_FLASH +#else + .type = signatureType_BOOTLOADER_INT_FLASH +#endif }; __attribute__ ((section(".bl_ram_signature"))) signature_S bl_ram_signature = { @@ -60,12 +64,15 @@ Signature_verification(const signature_S* signature) { case signatureType_FIRMWARE_RAM: detected_binary = signatureType_FIRMWARE_RAM; break; - case signatureType_BOOTLOADER_FLASH: - detected_binary = signatureType_BOOTLOADER_FLASH; + case signatureType_BOOTLOADER_INT_FLASH: + detected_binary = signatureType_BOOTLOADER_INT_FLASH; break; case signatureType_BOOTLOADER_RAM: detected_binary = signatureType_BOOTLOADER_RAM; break; + case signatureType_BOOTLOADER_EXT_FLASH: + detected_binary = signatureType_BOOTLOADER_EXT_FLASH; + break; default: detected_binary = signatureType_UNKNOWN; break; diff --git a/Drivers/STM32N6xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/Drivers/STM32N6xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 5073def..96e424b 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/Drivers/STM32N6xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -472,9 +472,9 @@ extern "C" { #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD -#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) +#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5) #define PAGESIZE FLASH_PAGE_SIZE -#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 */ +#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 && STM32H5 */ #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD @@ -538,6 +538,10 @@ extern "C" { #define FLASH_FLAG_WDW FLASH_FLAG_WBNE #define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL #endif /* STM32H7 */ +#if defined(STM32H7RS) +#define FLASH_OPTKEY1 FLASH_OPT_KEY1 +#define FLASH_OPTKEY2 FLASH_OPT_KEY2 +#endif /* STM32H7RS */ #if defined(STM32U5) #define OB_USER_nRST_STOP OB_USER_NRST_STOP #define OB_USER_nRST_STDBY OB_USER_NRST_STDBY @@ -560,6 +564,9 @@ extern "C" { #define OB_nBOOT0_RESET OB_NBOOT0_RESET #define OB_nBOOT0_SET OB_NBOOT0_SET #endif /* STM32U0 */ +#if defined(STM32H5) +#define FLASH_ECC_AREA_EDATA FLASH_ECC_AREA_EDATA_BANK1 +#endif /* STM32H5 */ /** * @} @@ -1299,22 +1306,22 @@ extern "C" { #define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL #endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ -#if defined(STM32F7) +#if defined(STM32F7) || defined(STM32WB) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK -#endif /* STM32F7 */ +#endif /* STM32F7 || STM32WB */ #if defined(STM32H7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_X #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT #endif /* STM32H7 */ -#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) +#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) || defined(STM32WB) #define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 #define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 #define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 #define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP -#endif /* STM32F7 || STM32H7 || STM32L0 */ +#endif /* STM32F7 || STM32H7 || STM32L0 || STM32WB */ /** * @} @@ -3948,7 +3955,7 @@ extern "C" { #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ defined (STM32WBA) || defined (STM32H5) || \ - defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) || defined (STM32U0) + defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif diff --git a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal.h b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal.h index 2d45c16..adacc1b 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal.h +++ b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal.h @@ -78,10 +78,10 @@ extern HAL_TickFreqTypeDef uwTickFreq; /** * @brief STM32N6xx HAL Driver version number */ -#define __STM32N6xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32N6xx_HAL_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */ -#define __STM32N6xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ -#define __STM32N6xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define __STM32N6xx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */ +#define __STM32N6xx_HAL_VERSION_SUB1 (0x02UL) /*!< [23:16] sub1 version */ +#define __STM32N6xx_HAL_VERSION_SUB2 (0x00UL) /*!< [15:8] sub2 version */ +#define __STM32N6xx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */ #define __STM32N6xx_HAL_VERSION ((__STM32N6xx_HAL_VERSION_MAIN << 24U) \ |(__STM32N6xx_HAL_VERSION_SUB1 << 16U) \ |(__STM32N6xx_HAL_VERSION_SUB2 << 8U ) \ diff --git a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_adc.h b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_adc.h index f88fafe..3e9b767 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_adc.h +++ b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_adc.h @@ -1689,8 +1689,7 @@ __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\ * @brief Helper macro to calculate the voltage (unit: mVolt) * corresponding to a ADC conversion data (unit: digital value). * @note Analog reference voltage (Vref+) must be either known from - * user board environment or can be calculated using ADC measurement - * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * user board environment. * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) * (unit: digital value). @@ -1713,8 +1712,7 @@ __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ * corresponding to a ADC conversion data (unit: digital value) * in differential ended mode. * @note Analog reference voltage (Vref+) must be either known from - * user board environment or can be calculated using ADC measurement - * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * user board environment. * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) * (unit: digital value). @@ -1732,36 +1730,6 @@ __LL_ADC_CALC_DIFF_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ (__ADC_DATA__),\ (__ADC_RESOLUTION__)) -/** - * @brief Helper macro to calculate analog reference voltage (Vref+) - * (unit: mVolt) from ADC conversion data of internal voltage - * reference VrefInt. - * @note Computation is using VrefInt calibration value - * stored in system memory for each device during production. - * @note This voltage depends on user board environment: voltage level - * connected to pin Vref+. - * On devices with small package, the pin Vref+ is not present - * and internally bonded to pin Vdda. - * @note On this STM32 series, calibration data of internal voltage reference - * VrefInt corresponds to a resolution of 12 bits, - * this is the recommended ADC resolution to convert voltage of - * internal voltage reference VrefInt. - * Otherwise, this macro performs the processing to scale - * ADC conversion data to 12 bits. - * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) - * of internal voltage reference VrefInt (unit: digital value). - * @param __ADC_RESOLUTION__ This parameter can be one of the following values: - * @arg @ref ADC_RESOLUTION_12B - * @arg @ref ADC_RESOLUTION_10B - * @arg @ref ADC_RESOLUTION_8B - * @arg @ref ADC_RESOLUTION_6B - * @retval Analog reference voltage (unit: mV) - */ -#define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ - __ADC_RESOLUTION__) \ -__LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\ - (__ADC_RESOLUTION__)) - /** * @} diff --git a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_bsec.h b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_bsec.h index f9a0897..d331e28 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_bsec.h +++ b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_bsec.h @@ -159,10 +159,10 @@ typedef struct /** @defgroup BSEC_Lifecycle_State BSEC Device lifecycle state * @{ */ -#define HAL_BSEC_OPEN_STATE (0x16U << BSEC_SR_NVSTATE_Pos) /*!< BSEC is in open state */ -#define HAL_BSEC_CLOSED_STATE (0x0DU << BSEC_SR_NVSTATE_Pos) /*!< BSEC is in closed state */ -#define HAL_BSEC_INVALID_STATE (0x07U << BSEC_SR_NVSTATE_Pos) /*!< BSEC is in invalid state */ -#define HAL_BSEC_INVALID_STATE_WITH_TAMPER (0x23U << BSEC_SR_NVSTATE_Pos) /*!< BSEC is in invalid state with an active confirmed tamper triggered */ +#define HAL_BSEC_OPEN_STATE (0x16UL << BSEC_SR_NVSTATE_Pos) /*!< BSEC is in open state */ +#define HAL_BSEC_CLOSED_STATE (0x0DUL << BSEC_SR_NVSTATE_Pos) /*!< BSEC is in closed state */ +#define HAL_BSEC_INVALID_STATE (0x07UL << BSEC_SR_NVSTATE_Pos) /*!< BSEC is in invalid state */ +#define HAL_BSEC_INVALID_STATE_WITH_TAMPER (0x23UL << BSEC_SR_NVSTATE_Pos) /*!< BSEC is in invalid state with an active confirmed tamper triggered */ /** * @} */ diff --git a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_conf_template.h b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_conf_template.h index 1a5559f..6e83db2 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_conf_template.h +++ b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_conf_template.h @@ -34,59 +34,60 @@ * @brief This is the list of modules to be used in the HAL driver */ #define HAL_MODULE_ENABLED -/*#define HAL_ADC_MODULE_ENABLED */ -/*#define HAL_BSEC_MODULE_ENABLED */ -/*#define HAL_CRC_MODULE_ENABLED */ -/*#define HAL_CRYP_MODULE_ENABLED */ -/*#define HAL_DCMI_MODULE_ENABLED */ +/*#define HAL_ADC_MODULE_ENABLED */ +/*#define HAL_BSEC_MODULE_ENABLED */ +/*#define HAL_CRC_MODULE_ENABLED */ +/*#define HAL_CRYP_MODULE_ENABLED */ +/*#define HAL_DCMI_MODULE_ENABLED */ /*#define HAL_DCMIPP_MODULE_ENABLED */ -/*#define HAL_DMA2D_MODULE_ENABLED */ -/*#define HAL_DTS_MODULE_ENABLED */ -/*#define HAL_ETH_MODULE_ENABLED */ -/*#define HAL_EXTI_MODULE_ENABLED */ -/*#define HAL_FDCAN_MODULE_ENABLED */ +/*#define HAL_DMA2D_MODULE_ENABLED */ +/*#define HAL_DTS_MODULE_ENABLED */ +/*#define HAL_ETH_MODULE_ENABLED */ +/*#define HAL_EXTI_MODULE_ENABLED */ +/*#define HAL_FDCAN_MODULE_ENABLED */ /*#define HAL_GFXMMU_MODULE_ENABLED */ /*#define HAL_GFXTIM_MODULE_ENABLED */ -/*#define HAL_HASH_MODULE_ENABLED */ -/*#define HAL_HCD_MODULE_ENABLED */ -/*#define HAL_I2C_MODULE_ENABLED */ -/*#define HAL_I2S_MODULE_ENABLED */ -/*#define HAL_I3C_MODULE_ENABLED */ +/*#define HAL_HASH_MODULE_ENABLED */ +/*#define HAL_HCD_MODULE_ENABLED */ +/*#define HAL_I2C_MODULE_ENABLED */ +/*#define HAL_I2S_MODULE_ENABLED */ +/*#define HAL_I3C_MODULE_ENABLED */ /*#define HAL_ICACHE_MODULE_ENABLED */ -/*#define HAL_IRDA_MODULE_ENABLED */ -/*#define HAL_IWDG_MODULE_ENABLED */ -/*#define HAL_JPEG_MODULE_ENABLED */ -/*#define HAL_LPTIM_MODULE_ENABLED */ -/*#define HAL_LTDC_MODULE_ENABLED */ -/*#define HAL_MCE_MODULE_ENABLED */ -/*#define HAL_MDF_MODULE_ENABLED */ -/*#define HAL_MMC_MODULE_ENABLED */ -/*#define HAL_NAND_MODULE_ENABLED */ -/*#define HAL_NOR_MODULE_ENABLED */ -/*#define HAL_PCD_MODULE_ENABLED */ -/*#define HAL_PKA_MODULE_ENABLED */ -/*#define HAL_PSSI_MODULE_ENABLED */ +/*#define HAL_IRDA_MODULE_ENABLED */ +/*#define HAL_IWDG_MODULE_ENABLED */ +/*#define HAL_JPEG_MODULE_ENABLED */ +/*#define HAL_LPTIM_MODULE_ENABLED */ +/*#define HAL_LTDC_MODULE_ENABLED */ +/*#define HAL_MCE_MODULE_ENABLED */ +/*#define HAL_MDF_MODULE_ENABLED */ +/*#define HAL_MMC_MODULE_ENABLED */ +/*#define HAL_NAND_MODULE_ENABLED */ +/*#define HAL_NOR_MODULE_ENABLED */ +/*#define HAL_PCD_MODULE_ENABLED */ +/*#define HAL_PKA_MODULE_ENABLED */ +/*#define HAL_PSSI_MODULE_ENABLED */ /*#define HAL_RAMCFG_MODULE_ENABLED */ -/*#define HAL_RIF_MODULE_ENABLED */ -/*#define HAL_RNG_MODULE_ENABLED */ -/*#define HAL_RTC_MODULE_ENABLED */ -/*#define HAL_SAI_MODULE_ENABLED */ -/*#define HAL_SD_MODULE_ENABLED */ -/*#define HAL_SDRAM_MODULE_ENABLED */ -/*#define HAL_SMARTCARD_MODULE_ENABLED */ -/*#define HAL_SMBUS_MODULE_ENABLED */ -/*#define HAL_SPDIFRX_MODULE_ENABLED */ -/*#define HAL_SPI_MODULE_ENABLED */ -/*#define HAL_SRAM_MODULE_ENABLED */ -/*#define HAL_TIM_MODULE_ENABLED */ -/*#define HAL_UART_MODULE_ENABLED */ -/*#define HAL_USART_MODULE_ENABLED */ -/*#define HAL_WWDG_MODULE_ENABLED */ -/*#define HAL_XSPI_MODULE_ENABLED */ -/*#define HAL_CACHEAXI_MODULE_ENABLED */ -/*#define HAL_MDIOS_MODULE_ENABLED */ -/*#define HAL_GPU2D_MODULE_ENABLED */ -/*#define HAL_CACHEAXI_MODULE_ENABLED */ +/*#define HAL_RIF_MODULE_ENABLED */ +/*#define HAL_RNG_MODULE_ENABLED */ +/*#define HAL_RTC_MODULE_ENABLED */ +/*#define HAL_SAI_MODULE_ENABLED */ +/*#define HAL_SD_MODULE_ENABLED */ +/*#define HAL_SDIO_MODULE_ENABLED */ +/*#define HAL_SDRAM_MODULE_ENABLED */ +/*#define HAL_SMARTCARD_MODULE_ENABLED*/ +/*#define HAL_SMBUS_MODULE_ENABLED */ +/*#define HAL_SPDIFRX_MODULE_ENABLED */ +/*#define HAL_SPI_MODULE_ENABLED */ +/*#define HAL_SRAM_MODULE_ENABLED */ +/*#define HAL_TIM_MODULE_ENABLED */ +/*#define HAL_UART_MODULE_ENABLED */ +/*#define HAL_USART_MODULE_ENABLED */ +/*#define HAL_WWDG_MODULE_ENABLED */ +/*#define HAL_XSPI_MODULE_ENABLED */ +/*#define HAL_CACHEAXI_MODULE_ENABLED */ +/*#define HAL_MDIOS_MODULE_ENABLED */ +/*#define HAL_GPU2D_MODULE_ENABLED */ +/*#define HAL_CACHEAXI_MODULE_ENABLED */ #define HAL_GPIO_MODULE_ENABLED #define HAL_EXTI_MODULE_ENABLED #define HAL_DMA_MODULE_ENABLED @@ -206,6 +207,7 @@ #define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ #define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ #define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SDIO_REGISTER_CALLBACKS 0U /* SDIO register callback disabled */ #define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ #define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ #define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ @@ -230,6 +232,10 @@ #define USE_SD_TRANSCEIVER 0U +/* ################## SDIO peripheral configuration ########################## */ +#define USE_SDIO_TRANSCEIVER 1U +#define SDIO_MAX_IO_NUMBER 7U /*!< SDIO device support maximum IO number */ + /* Includes ------------------------------------------------------------------*/ /** * @brief Include module's header file @@ -426,6 +432,10 @@ #include "stm32n6xx_hal_sd.h" #endif /* HAL_SD_MODULE_ENABLED */ +#ifdef HAL_SDIO_MODULE_ENABLED +#include "stm32n6xx_hal_sdio.h" +#endif /* HAL_SDIO_MODULE_ENABLED */ + #ifdef HAL_SDRAM_MODULE_ENABLED #include "stm32n6xx_hal_sdram.h" #endif /* HAL_SDRAM_MODULE_ENABLED */ diff --git a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_cortex.h b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_cortex.h index b4fb881..1663d50 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_cortex.h +++ b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_cortex.h @@ -51,14 +51,16 @@ typedef struct This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ uint8_t Number; /*!< Specifies the number of the region to protect. This parameter can be a value of @ref CORTEX_MPU_Region_Number */ - uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ - uint32_t LimitAddress; /*!< Specifies the limit address of the region to protect. */ uint8_t AttributesIndex; /*!< Specifies the memory attributes index. This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */ + uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ + uint32_t LimitAddress; /*!< Specifies the limit address of the region to protect. */ uint8_t AccessPermission; /*!< Specifies the region access permission type. This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ uint8_t DisableExec; /*!< Specifies the instruction access status. This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ + uint8_t DisablePrivExec; /*!< Specifies if privileged software can execute instructions from this region. + This parameter can be a value of @ref CORTEX_MPU_Priv_Instruction_Access */ uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ } MPU_Region_InitTypeDef; @@ -75,7 +77,7 @@ typedef struct This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */ uint8_t Attributes; /*!< Specifies the memory attributes vue. - This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */ + This parameter can be a value of @ref CORTEX_MPU_Attributes */ } MPU_Attributes_InitTypeDef; /** @@ -148,6 +150,15 @@ typedef struct * @} */ +/** @defgroup CORTEX_MPU_Priv_Instruction_Access CORTEX MPU Privileged Instruction Access + * @{ + */ +#define MPU_PRIV_INSTRUCTION_ACCESS_ENABLE 0U +#define MPU_PRIV_INSTRUCTION_ACCESS_DISABLE 1U +/** + * @} + */ + /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable * @{ */ @@ -352,6 +363,9 @@ void HAL_MPU_ConfigMemoryAttributes_NS(const MPU_Attributes_InitTypeDef *pMPU_At #define IS_MPU_INSTRUCTION_ACCESS(__STATE__) (((__STATE__) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ ((__STATE__) == MPU_INSTRUCTION_ACCESS_DISABLE)) +#define IS_MPU_PRIV_INSTRUCTION_ACCESS(__STATE__) (((__STATE__) == MPU_PRIV_INSTRUCTION_ACCESS_ENABLE) || \ + ((__STATE__) == MPU_PRIV_INSTRUCTION_ACCESS_DISABLE)) + #define IS_MPU_ACCESS_SHAREABLE(__STATE__) (((__STATE__) == MPU_ACCESS_OUTER_SHAREABLE) || \ ((__STATE__) == MPU_ACCESS_INNER_SHAREABLE) || \ ((__STATE__) == MPU_ACCESS_NOT_SHAREABLE)) diff --git a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_cryp.h b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_cryp.h index fb771aa..c550040 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_cryp.h +++ b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_cryp.h @@ -736,7 +736,7 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp); HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp); void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp); void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp); -HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf); +HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, const CRYP_ConfigTypeDef *pConf); HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf); #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, diff --git a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_dcmipp.h b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_dcmipp.h index 7083d87..5ccf865 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_dcmipp.h +++ b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_dcmipp.h @@ -194,13 +194,13 @@ typedef struct typedef struct { uint32_t VStart; /*!< Configures the DCMIPP Crop Vertical Start - This parameter can be one value between 0 and 4095 */ + This parameter can be one value between 0 and 4094 */ uint32_t HStart; /*!< Configures the DCMIPP Crop Horizontal Start - This parameter can be one value between 0 and 4095 */ + This parameter can be one value between 0 and 4094 */ uint32_t VSize; /*!< Configures the DCMIPP Crop Vertical Size - This parameter can be one value between 0 and 4095 */ + This parameter can be one value between 0 and 4094 */ uint32_t HSize; /*!< Configures the DCMIPP Crop Horizontal Size - This parameter can be one value between 1 and 4095 */ + This parameter can be one value between 1 and 4094 */ uint32_t PipeArea; /*!< Configures the DCMIPP Crop Area for the pipe0 This parameter can be one value of @ref DCMIPP_Crop_Area */ } DCMIPP_CropConfTypeDef; @@ -208,13 +208,13 @@ typedef struct typedef struct { uint32_t VStart; /*!< Configures the DCMIPP Statistic Extraction Vertical Start - This parameter can be one value between 0 and 4095 */ + This parameter can be one value between 0 and 4094 */ uint32_t HStart; /*!< Configures the DCMIPP Statistic Extraction Horizontal Start - This parameter can be one value between 0 and 4095 */ + This parameter can be one value between 0 and 4094 */ uint32_t VSize; /*!< Configures the DCMIPP Statistic Extraction Vertical Size - This parameter can be one value between 0 and 4095 */ + This parameter can be one value between 0 and 4094 */ uint32_t HSize; /*!< Configures the DCMIPP Statistic Extraction Horizontal Size - This parameter can be one value between 0 and 4095 */ + This parameter can be one value between 0 and 4094 */ } DCMIPP_StatisticExtractionAreaConfTypeDef; typedef struct @@ -321,23 +321,23 @@ typedef struct typedef struct { uint32_t VStart; /*!< Configures the DCMIPP Region Of Interest Vertical Start - This parameter can be one value between 0 and 4095 */ + This parameter can be one value between 0 and 4094 */ uint32_t HStart; /*!< Configures the DCMIPP Region Of Interest Horizontal Start - This parameter can be one value between 0 and 4095 */ + This parameter can be one value between 0 and 4094 */ uint32_t VSize; /*!< Configures the DCMIPP Region Of Interest Vertical Size - This parameter can be one value between 0 and 4095 */ + This parameter can be one value between 0 and 4094 */ uint32_t HSize; /*!< Configures the DCMIPP Region Of Interest Horizontal Size - This parameter can be one value between 0 and 4095 */ + This parameter can be one value between 0 and 4094 */ uint32_t LineSizeWidth; /*!< Configures the DCMIPP Region Of Interest Line Size Width This parameter can be a value from @ref DCMIPP_Region_Of_Interest_Line_Width */ uint32_t RegionOfInterest; /*!< Configures the DCMIPP Region Of Interest This parameter can be a value from @ref DCMIPP_Region_Of_Interest */ uint8_t ColorLineRed; /*!< Configures the DCMIPP Region Of Interest Line Color : Red Component - This parameter can be one value between 0 and 4095 */ + This parameter can be one value between 0 and 3 */ uint8_t ColorLineGreen; /*!< Configures the DCMIPP Region Of Interest Line Color : Green Component - This parameter can be one value between 0 and 4095 */ + This parameter can be one value between 0 and 3 */ uint8_t ColorLineBlue; /*!< Configures the DCMIPP Region Of Interest Line Color : Blue Component - This parameter can be one value between 0 and 4095 */ + This parameter can be one value between 0 and 3 */ } DCMIPP_RegionOfInterestConfTypeDef; /** @@ -359,17 +359,17 @@ typedef struct typedef struct { uint32_t VSize; /*!< Configures the DCMIPP Downsize Vertical Size - This parameter can be one value between 0 and 4095 */ + This parameter can be one value between 0 and 4094 */ uint32_t HSize; /*!< Configures the DCMIPP Downsize Horizontal Size - This parameter can be one value between 0 and 4095 */ + This parameter can be one value between 0 and 4094 */ uint32_t VRatio; /*!< Configures the DCMIPP Downsize Vertical Ratio - This parameter can be one value between 0 and 4095 */ + This parameter can be one value between 0 and 4094 */ uint32_t HRatio; /*!< Configures the DCMIPP Downsize Horizontal Ratio - This parameter can be one value between 0 and 4095 */ + This parameter can be one value between 0 and 4094 */ uint32_t VDivFactor; /*!< Configures the DCMIPP Downsize Vertical Division Factor - This parameter can be one value between 0 and 4095 */ + This parameter can be one value between 0 and 4094 */ uint32_t HDivFactor; /*!< Configures the DCMIPP Downsize Horizontal Division Factor - This parameter can be one value between 0 and 4095 */ + This parameter can be one value between 0 and 4094 */ } DCMIPP_DownsizeTypeDef; typedef struct @@ -667,15 +667,15 @@ typedef void (*pDCMIPP_PIPE_CallbackTypeDef)(DCMIPP_HandleTypeDef *hdcmipp, uint /** @defgroup DCMIPP_DataTypeMode DCMIPP DCMIPP Data Type Mode * @{ */ -#define DCMIPP_DTMODE_DTIDA (0U << DCMIPP_P0FSCR_DTMODE_Pos) /*!< Only flow DTIDA from the selected VC +#define DCMIPP_DTMODE_DTIDA (0UL << DCMIPP_P0FSCR_DTMODE_Pos) /*!< Only flow DTIDA from the selected VC is forwarded in the pipe */ -#define DCMIPP_DTMODE_DTIDA_OR_DTIDB (1U << DCMIPP_P0FSCR_DTMODE_Pos) /*!< Flows DTIDA and/or DTIDB from the +#define DCMIPP_DTMODE_DTIDA_OR_DTIDB (1UL << DCMIPP_P0FSCR_DTMODE_Pos) /*!< Flows DTIDA and/or DTIDB from the selected VC are forwarded in the pipe */ -#define DCMIPP_DTMODE_ALL_EXCEPT_DTIA_DTIB (2U << DCMIPP_P0FSCR_DTMODE_Pos) /*!< All data types from the selected VC +#define DCMIPP_DTMODE_ALL_EXCEPT_DTIA_DTIB (2UL << DCMIPP_P0FSCR_DTMODE_Pos) /*!< All data types from the selected VC (except the DTIDA or DTIDB) are forwarded in the pipe, only for Pipe0 */ -#define DCMIPP_DTMODE_ALL (3U << DCMIPP_P0FSCR_DTMODE_Pos) /*!< All data types of the selected virtual +#define DCMIPP_DTMODE_ALL (3UL << DCMIPP_P0FSCR_DTMODE_Pos) /*!< All data types of the selected virtual channel VC are forwarded in the pipe, only for Pipe0 */ /** @@ -728,8 +728,8 @@ typedef void (*pDCMIPP_PIPE_CallbackTypeDef)(DCMIPP_HandleTypeDef *hdcmipp, uint /** @defgroup DCMIPP_CSI_Number_Of_Lanes DCMIPP CSI Number Of Lanes * @{ */ -#define DCMIPP_CSI_ONE_DATA_LANE (1U << CSI_LMCFGR_LANENB_Pos) /*!< DCMIPP CSI One Data Lane */ -#define DCMIPP_CSI_TWO_DATA_LANES (2U << CSI_LMCFGR_LANENB_Pos) /*!< DCMIPP CSI 2 Data Lanes */ +#define DCMIPP_CSI_ONE_DATA_LANE (1UL << CSI_LMCFGR_LANENB_Pos) /*!< DCMIPP CSI One Data Lane */ +#define DCMIPP_CSI_TWO_DATA_LANES (2UL << CSI_LMCFGR_LANENB_Pos) /*!< DCMIPP CSI 2 Data Lanes */ /** * @} */ @@ -747,8 +747,8 @@ typedef void (*pDCMIPP_PIPE_CallbackTypeDef)(DCMIPP_HandleTypeDef *hdcmipp, uint /** @defgroup DCMIPP_CSI_DataLane DCMIPP CSI Data Lane * @{ */ -#define DCMIPP_CSI_DATA_LANE0 1U /*!< DCMIPP CSI Data Lane 0 */ -#define DCMIPP_CSI_DATA_LANE1 2U /*!< DCMIPP CSI Data Lane 1 */ +#define DCMIPP_CSI_DATA_LANE0 1UL /*!< DCMIPP CSI Data Lane 0 */ +#define DCMIPP_CSI_DATA_LANE1 2UL /*!< DCMIPP CSI Data Lane 1 */ /** * @} */ @@ -877,18 +877,18 @@ typedef void (*pDCMIPP_PIPE_CallbackTypeDef)(DCMIPP_HandleTypeDef *hdcmipp, uint * @{ */ #define DCMIPP_FORMAT_BYTE 0U /*!< DCMIPP Format BYTE */ -#define DCMIPP_FORMAT_YUV422 (0x1EU << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format YUV422 */ -#define DCMIPP_FORMAT_RGB565 (0x22U << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format RGB565 */ -#define DCMIPP_FORMAT_RGB666 (0x23U << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format RGB666 */ -#define DCMIPP_FORMAT_RGB888 (0x24U << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format RGB888 */ -#define DCMIPP_FORMAT_RAW8 (0x2AU << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format RAW8 */ -#define DCMIPP_FORMAT_RAW10 (0x2BU << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format RAW10 */ -#define DCMIPP_FORMAT_RAW12 (0x2CU << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format RAW12 */ -#define DCMIPP_FORMAT_RAW14 (0x2DU << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format RAW14 */ -#define DCMIPP_FORMAT_MONOCHROME_8B (0x4AU << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format 8-bits */ -#define DCMIPP_FORMAT_MONOCHROME_10B (0x4BU << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format 10-bits */ -#define DCMIPP_FORMAT_MONOCHROME_12B (0x4CU << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format 12-bits */ -#define DCMIPP_FORMAT_MONOCHROME_14B (0x4DU << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format 14-bits */ +#define DCMIPP_FORMAT_YUV422 (0x1EUL << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format YUV422 */ +#define DCMIPP_FORMAT_RGB565 (0x22UL << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format RGB565 */ +#define DCMIPP_FORMAT_RGB666 (0x23UL << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format RGB666 */ +#define DCMIPP_FORMAT_RGB888 (0x24UL << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format RGB888 */ +#define DCMIPP_FORMAT_RAW8 (0x2AUL << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format RAW8 */ +#define DCMIPP_FORMAT_RAW10 (0x2BUL << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format RAW10 */ +#define DCMIPP_FORMAT_RAW12 (0x2CUL << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format RAW12 */ +#define DCMIPP_FORMAT_RAW14 (0x2DUL << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format RAW14 */ +#define DCMIPP_FORMAT_MONOCHROME_8B (0x4AUL << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format 8-bits */ +#define DCMIPP_FORMAT_MONOCHROME_10B (0x4BUL << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format 10-bits */ +#define DCMIPP_FORMAT_MONOCHROME_12B (0x4CUL << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format 12-bits */ +#define DCMIPP_FORMAT_MONOCHROME_14B (0x4DUL << DCMIPP_PRCR_FORMAT_Pos) /*!< DCMIPP Format 14-bits */ /** * @} */ @@ -896,11 +896,11 @@ typedef void (*pDCMIPP_PIPE_CallbackTypeDef)(DCMIPP_HandleTypeDef *hdcmipp, uint /** @defgroup DCMIPP_Extended_Data_Mode DCMIPP Extended Data Mode * @{ */ -#define DCMIPP_INTERFACE_8BITS 0U /*!< Interface captures 8bits on every pixel clock */ -#define DCMIPP_INTERFACE_10BITS (1U << DCMIPP_PRCR_EDM_Pos) /*!< Interface captures 10bits on every pixel clock */ -#define DCMIPP_INTERFACE_12BITS (2U << DCMIPP_PRCR_EDM_Pos) /*!< Interface captures 12bits on every pixel clock */ -#define DCMIPP_INTERFACE_14BITS (3U << DCMIPP_PRCR_EDM_Pos) /*!< Interface captures 14bits on every pixel clock */ -#define DCMIPP_INTERFACE_16BITS (4U << DCMIPP_PRCR_EDM_Pos) /*!< Interface captures 16bits on every pixel clock */ +#define DCMIPP_INTERFACE_8BITS 0UL /*!< Interface captures 8bits on every pixel clock */ +#define DCMIPP_INTERFACE_10BITS (1UL << DCMIPP_PRCR_EDM_Pos) /*!< Interface captures 10bits on every pixel clock */ +#define DCMIPP_INTERFACE_12BITS (2UL << DCMIPP_PRCR_EDM_Pos) /*!< Interface captures 12bits on every pixel clock */ +#define DCMIPP_INTERFACE_14BITS (3UL << DCMIPP_PRCR_EDM_Pos) /*!< Interface captures 14bits on every pixel clock */ +#define DCMIPP_INTERFACE_16BITS (4UL << DCMIPP_PRCR_EDM_Pos) /*!< Interface captures 16bits on every pixel clock */ /** * @} */ @@ -971,17 +971,17 @@ typedef void (*pDCMIPP_PIPE_CallbackTypeDef)(DCMIPP_HandleTypeDef *hdcmipp, uint /** @defgroup DCMIPP_Line_Select_Mode DCMIPP Line Select Mode * @{ */ -#define DCMIPP_LSM_ALL 0U /*!< Interface captures all received lines */ -#define DCMIPP_LSM_ALTERNATE_2 (1U << DCMIPP_P0PPCR_LSM_Pos ) /*!< Interface captures one line out of two */ +#define DCMIPP_LSM_ALL 0UL /*!< Interface captures all received lines */ +#define DCMIPP_LSM_ALTERNATE_2 (1UL << DCMIPP_P0PPCR_LSM_Pos ) /*!< Interface captures one line out of two */ /** * @} */ /** @defgroup DCMIPP_Line_Start_Mode DCMIPP Line Start Mode * @{ */ -#define DCMIPP_OELS_ODD 0U /*!< Interface captures first line from the frame start, +#define DCMIPP_OELS_ODD 0UL /*!< Interface captures first line from the frame start, second one is dropped */ -#define DCMIPP_OELS_EVEN (1U << DCMIPP_P0PPCR_OELS_Pos) /*!< Interface captures second line from the frame +#define DCMIPP_OELS_EVEN (1UL << DCMIPP_P0PPCR_OELS_Pos) /*!< Interface captures second line from the frame start, first one is dropped */ /** * @} @@ -996,19 +996,19 @@ typedef void (*pDCMIPP_PIPE_CallbackTypeDef)(DCMIPP_HandleTypeDef *hdcmipp, uint /** @defgroup DCMIPP_Byte_Select_Mode DCMIPP Byte Select Mode * @{ */ -#define DCMIPP_BSM_ALL 0U /*!< Interface captures all received data */ -#define DCMIPP_BSM_DATA_OUT_2 (1U << DCMIPP_P0PPCR_BSM_Pos) /*!< Interface captures 1 data out of 2 */ -#define DCMIPP_BSM_BYTE_OUT_4 (2U << DCMIPP_P0PPCR_BSM_Pos) /*!< Interface captures 1 byte out of 4 */ -#define DCMIPP_BSM_2BYTE_OUT_4 (3U << DCMIPP_P0PPCR_BSM_Pos) /*!< Interface captures 2 byte out of 4 */ +#define DCMIPP_BSM_ALL 0UL /*!< Interface captures all received data */ +#define DCMIPP_BSM_DATA_OUT_2 (1UL << DCMIPP_P0PPCR_BSM_Pos) /*!< Interface captures 1 data out of 2 */ +#define DCMIPP_BSM_BYTE_OUT_4 (2UL << DCMIPP_P0PPCR_BSM_Pos) /*!< Interface captures 1 byte out of 4 */ +#define DCMIPP_BSM_2BYTE_OUT_4 (3UL << DCMIPP_P0PPCR_BSM_Pos) /*!< Interface captures 2 byte out of 4 */ /** * @} */ /** @defgroup DCMIPP_Byte_Start_Mode DCMIPP Byte Start Mode * @{ */ -#define DCMIPP_OEBS_ODD 0U /*!< Interface captures first data (byte or double byte) +#define DCMIPP_OEBS_ODD 0UL /*!< Interface captures first data (byte or double byte) from the frame/line start,second one being dropped */ -#define DCMIPP_OEBS_EVEN (1U << DCMIPP_P0PPCR_OEBS_Pos) /*!< Interface captures second data (byte or double byte) +#define DCMIPP_OEBS_EVEN (1UL << DCMIPP_P0PPCR_OEBS_Pos) /*!< Interface captures second data (byte or double byte) from the frame/line start, first one is dropped */ /** * @} @@ -1028,28 +1028,28 @@ typedef void (*pDCMIPP_PIPE_CallbackTypeDef)(DCMIPP_HandleTypeDef *hdcmipp, uint /** @defgroup DCMIPP_LineMult DCMIPP Line Mult * @{ */ -#define DCMIPP_MULTILINE_1_LINE 0U /*!< Event after every 1 line */ -#define DCMIPP_MULTILINE_2_LINES (1U << DCMIPP_P0PPCR_LINEMULT_Pos) /*!< Event after every 2 lines */ -#define DCMIPP_MULTILINE_4_LINES (2U << DCMIPP_P0PPCR_LINEMULT_Pos) /*!< Event after every 4 lines */ -#define DCMIPP_MULTILINE_8_LINES (3U << DCMIPP_P0PPCR_LINEMULT_Pos) /*!< Event after every 8 lines */ -#define DCMIPP_MULTILINE_16_LINES (4U << DCMIPP_P0PPCR_LINEMULT_Pos) /*!< Event after every 16 lines */ -#define DCMIPP_MULTILINE_32_LINES (5U << DCMIPP_P0PPCR_LINEMULT_Pos) /*!< Event after every 32 lines */ -#define DCMIPP_MULTILINE_64_LINES (6U << DCMIPP_P0PPCR_LINEMULT_Pos) /*!< Event after every 64 lines */ -#define DCMIPP_MULTILINE_128_LINES (7U << DCMIPP_P0PPCR_LINEMULT_Pos) /*!< Event after every 128 lines */ +#define DCMIPP_MULTILINE_1_LINE 0UL /*!< Event after every 1 line */ +#define DCMIPP_MULTILINE_2_LINES (1UL << DCMIPP_P0PPCR_LINEMULT_Pos) /*!< Event after every 2 lines */ +#define DCMIPP_MULTILINE_4_LINES (2UL << DCMIPP_P0PPCR_LINEMULT_Pos) /*!< Event after every 4 lines */ +#define DCMIPP_MULTILINE_8_LINES (3UL << DCMIPP_P0PPCR_LINEMULT_Pos) /*!< Event after every 8 lines */ +#define DCMIPP_MULTILINE_16_LINES (4UL << DCMIPP_P0PPCR_LINEMULT_Pos) /*!< Event after every 16 lines */ +#define DCMIPP_MULTILINE_32_LINES (5UL << DCMIPP_P0PPCR_LINEMULT_Pos) /*!< Event after every 32 lines */ +#define DCMIPP_MULTILINE_64_LINES (6UL << DCMIPP_P0PPCR_LINEMULT_Pos) /*!< Event after every 64 lines */ +#define DCMIPP_MULTILINE_128_LINES (7UL << DCMIPP_P0PPCR_LINEMULT_Pos) /*!< Event after every 128 lines */ /** * @} */ /** @defgroup DCMIPP_LineWrapAddress DCMIPP line Wrap Address * @{ */ -#define DCMIPP_WRAP_ADDRESS_1_LINE (0U << DCMIPP_P1PPCR_LMAWM_Pos) /*!< Wraps address after 1 line */ -#define DCMIPP_WRAP_ADDRESS_2_LINES (1U << DCMIPP_P1PPCR_LMAWM_Pos) /*!< Wraps address after 2 lines */ -#define DCMIPP_WRAP_ADDRESS_4_LINES (2U << DCMIPP_P1PPCR_LMAWM_Pos) /*!< Wraps address after 4 lines */ -#define DCMIPP_WRAP_ADDRESS_8_LINES (3U << DCMIPP_P1PPCR_LMAWM_Pos) /*!< Wraps address after 8 lines */ -#define DCMIPP_WRAP_ADDRESS_16_LINES (4U << DCMIPP_P1PPCR_LMAWM_Pos) /*!< Wraps address after 16 lines */ -#define DCMIPP_WRAP_ADDRESS_32_LINES (5U << DCMIPP_P1PPCR_LMAWM_Pos) /*!< Wraps address after 32 lines */ -#define DCMIPP_WRAP_ADDRESS_64_LINES (6U << DCMIPP_P1PPCR_LMAWM_Pos) /*!< Wraps address after 64 lines */ -#define DCMIPP_WRAP_ADDRESS_128_LINES (7U << DCMIPP_P1PPCR_LMAWM_Pos) /*!< Wraps address after 128 lines */ +#define DCMIPP_WRAP_ADDRESS_1_LINE (0UL << DCMIPP_P1PPCR_LMAWM_Pos) /*!< Wraps address after 1 line */ +#define DCMIPP_WRAP_ADDRESS_2_LINES (1UL << DCMIPP_P1PPCR_LMAWM_Pos) /*!< Wraps address after 2 lines */ +#define DCMIPP_WRAP_ADDRESS_4_LINES (2UL << DCMIPP_P1PPCR_LMAWM_Pos) /*!< Wraps address after 4 lines */ +#define DCMIPP_WRAP_ADDRESS_8_LINES (3UL << DCMIPP_P1PPCR_LMAWM_Pos) /*!< Wraps address after 8 lines */ +#define DCMIPP_WRAP_ADDRESS_16_LINES (4UL << DCMIPP_P1PPCR_LMAWM_Pos) /*!< Wraps address after 16 lines */ +#define DCMIPP_WRAP_ADDRESS_32_LINES (5UL << DCMIPP_P1PPCR_LMAWM_Pos) /*!< Wraps address after 32 lines */ +#define DCMIPP_WRAP_ADDRESS_64_LINES (6UL << DCMIPP_P1PPCR_LMAWM_Pos) /*!< Wraps address after 64 lines */ +#define DCMIPP_WRAP_ADDRESS_128_LINES (7UL << DCMIPP_P1PPCR_LMAWM_Pos) /*!< Wraps address after 128 lines */ /** * @} */ @@ -1088,10 +1088,11 @@ typedef void (*pDCMIPP_PIPE_CallbackTypeDef)(DCMIPP_HandleTypeDef *hdcmipp, uint #define DCMIPP_PIXEL_PACKER_FORMAT_MONO_Y8_G8_1 (4U << DCMIPP_P1PPCR_FORMAT_Pos) /*!< Monochrome Y8 or G8 */ #define DCMIPP_PIXEL_PACKER_FORMAT_YUV444_1 (5U << DCMIPP_P1PPCR_FORMAT_Pos) /*!< YUV444 1-buffer 32bpp A=0xff) */ -#define DCMIPP_PIXEL_PACKER_FORMAT_YUV422_1 (6U << DCMIPP_P1PPCR_FORMAT_Pos) /*!< YUV422 1-buffer 16bpp */ +#define DCMIPP_PIXEL_PACKER_FORMAT_YUV422_1 (6U << DCMIPP_P1PPCR_FORMAT_Pos) /*!< YUV422 1-buffer 16bpp YUYV*/ #define DCMIPP_PIXEL_PACKER_FORMAT_YUV422_2 (7U << DCMIPP_P1PPCR_FORMAT_Pos) /*!< YUV422 2-buffer 16bpp */ #define DCMIPP_PIXEL_PACKER_FORMAT_YUV420_2 (8U << DCMIPP_P1PPCR_FORMAT_Pos) /*!< YUV420 2-buffer 12bpp */ #define DCMIPP_PIXEL_PACKER_FORMAT_YUV420_3 (9U << DCMIPP_P1PPCR_FORMAT_Pos) /*!< YUV420 3-buffer 12bpp */ +#define DCMIPP_PIXEL_PACKER_FORMAT_YUV422_1_UYVY (0xAU << DCMIPP_P1PPCR_FORMAT_Pos) /*!< YUV422 1-buffer 16bpp UYVY*/ /** * @} */ @@ -2207,7 +2208,8 @@ uint32_t HAL_DCMIPP_GetError(const DCMIPP_HandleTypeDef *hdcmipp); ((FORMAT) == DCMIPP_PIXEL_PACKER_FORMAT_YUV422_1) ||\ ((FORMAT) == DCMIPP_PIXEL_PACKER_FORMAT_YUV422_2) ||\ ((FORMAT) == DCMIPP_PIXEL_PACKER_FORMAT_YUV420_2) ||\ - ((FORMAT) == DCMIPP_PIXEL_PACKER_FORMAT_YUV420_3)) + ((FORMAT) == DCMIPP_PIXEL_PACKER_FORMAT_YUV420_3) ||\ + ((FORMAT) == DCMIPP_PIXEL_PACKER_FORMAT_YUV422_1_UYVY)) #define IS_DCMIPP_PIXEL_PIPE_PITCH(PITCH) ((((PITCH) & 0xFU) == 0U) && ((PITCH) <= 0x7FFFU)) diff --git a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_def.h b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_def.h index 95a5317..9564a3b 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_def.h +++ b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_def.h @@ -196,9 +196,9 @@ typedef enum #define __NON_CACHEABLE_SECTION_END ((uint32_t) __sfe(".noncacheable")) #elif defined(__ARMCC_VERSION) extern uint32_t Image$$RW_NONCACHEABLEBUFFER$$Base; -extern uint32_t Image$$RW_NONCACHEABLEBUFFER$$Length; -#define __NON_CACHEABLE_SECTION_BEGIN Image$$RW_NONCACHEABLEBUFFER$$Base -#define __NON_CACHEABLE_SECTION_END (__NON_CACHEABLE_SECTION_BEGIN + Image$$RW_NONCACHEABLEBUFFER$$Length) +extern uint32_t Image$$RW_NONCACHEABLEBUFFER$$Limit; +#define __NON_CACHEABLE_SECTION_BEGIN ((uint32_t) &Image$$RW_NONCACHEABLEBUFFER$$Base) +#define __NON_CACHEABLE_SECTION_END ((uint32_t) &Image$$RW_NONCACHEABLEBUFFER$$Limit-1) #elif defined(__GNUC__) extern uint32_t __snoncacheable; extern uint32_t __enoncacheable; diff --git a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_dma_ex.h b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_dma_ex.h index 2067c9f..fc0c66e 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_dma_ex.h +++ b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_dma_ex.h @@ -770,8 +770,8 @@ typedef struct #define NODE_CDAR_DEFAULT_OFFSET (0x0004U) /* CDAR default offset */ #define NODE_CTR3_DEFAULT_OFFSET (0x0005U) /* CTR3 2D addressing default offset */ #define NODE_CBR2_DEFAULT_OFFSET (0x0006U) /* CBR2 2D addressing default offset */ -#define NODE_CLLR_2D_DEFAULT_OFFSET (0x0007U) /* CLLR 2D addressing default offset */ -#define NODE_CLLR_LINEAR_DEFAULT_OFFSET (0x0005U) /* CLLR linear addressing default offset */ +#define NODE_CLLR_2D_DEFAULT_OFFSET (0x007UL) /* CLLR 2D addressing default offset */ +#define NODE_CLLR_LINEAR_DEFAULT_OFFSET (0x005UL) /* CLLR linear addressing default offset */ #define DMA_BURST_ADDR_OFFSET_MIN (-8192L) /* DMA burst minimum address offset */ #define DMA_BURST_ADDR_OFFSET_MAX (8192L) /* DMA burst maximum address offset */ diff --git a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_eth.h b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_eth.h index d81e87a..02be36a 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_eth.h +++ b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_eth.h @@ -1708,11 +1708,14 @@ typedef enum */ #define ETH_DMA_CH0_IDX (0U) #define ETH_DMA_CH1_IDX (1U) + /** * @} */ - +/** + * @} + */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup ETH_Exported_Macros ETH Exported Macros @@ -2090,10 +2093,6 @@ uint32_t HAL_ETH_GetTxBuffersNumber(const ETH_HandleTypeDef *heth); * @} */ -/** - * @} - */ - #endif /* ETH1 */ #ifdef __cplusplus diff --git a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_eth_ex.h b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_eth_ex.h index cf3e521..ab58c22 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_eth_ex.h +++ b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_eth_ex.h @@ -572,7 +572,7 @@ typedef struct #define ETH_RX_QUEUE_PRIO_6 0x00000040U /*!< Rx VLAN User Tag Priority 6 */ #define ETH_RX_QUEUE_PRIO_7 0x00000080U /*!< Rx VLAN User Tag Priority 7 */ /** - * + * @} */ /** @defgroup ETHEx_Preemption_Packet ETHEx Preemption Packet @@ -725,10 +725,6 @@ HAL_StatusTypeDef HAL_ETHEx_SetFPEConfig(ETH_HandleTypeDef *heth, ETH_FPEConfig * @} */ -/** - * @} - */ - #endif /* ETH1 */ #ifdef __cplusplus diff --git a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_exti.h b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_exti.h index 7fb168f..5edda62 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_exti.h +++ b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_exti.h @@ -238,27 +238,27 @@ typedef struct /** * @brief EXTI Event presence definition */ -#define EXTI_EVENT_PRESENCE_SHIFT 28U +#define EXTI_EVENT_PRESENCE_SHIFT 28UL #define EXTI_EVENT (0x01UL << EXTI_EVENT_PRESENCE_SHIFT) #define EXTI_EVENT_PRESENCE_MASK (EXTI_EVENT) /** * @brief EXTI Line property definition */ -#define EXTI_PROPERTY_SHIFT 24U -#define EXTI_DIRECT (0x01U << EXTI_PROPERTY_SHIFT) -#define EXTI_CONFIG (0x02U << EXTI_PROPERTY_SHIFT) -#define EXTI_GPIO ((0x04U << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) -#define EXTI_RESERVED (0x08U << EXTI_PROPERTY_SHIFT) +#define EXTI_PROPERTY_SHIFT 24UL +#define EXTI_DIRECT (0x01UL << EXTI_PROPERTY_SHIFT) +#define EXTI_CONFIG (0x02UL << EXTI_PROPERTY_SHIFT) +#define EXTI_GPIO ((0x04UL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) +#define EXTI_RESERVED (0x08UL << EXTI_PROPERTY_SHIFT) #define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO) /** * @brief EXTI Register and bit usage */ -#define EXTI_REG_SHIFT 16U -#define EXTI_REG1 (0x00U << EXTI_REG_SHIFT) -#define EXTI_REG2 (0x01U << EXTI_REG_SHIFT) -#define EXTI_REG3 (0x02U << EXTI_REG_SHIFT) +#define EXTI_REG_SHIFT 16UL +#define EXTI_REG1 (0x00UL << EXTI_REG_SHIFT) +#define EXTI_REG2 (0x01UL << EXTI_REG_SHIFT) +#define EXTI_REG3 (0x02UL << EXTI_REG_SHIFT) #define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2 | EXTI_REG3) #define EXTI_PIN_MASK 0x0000001FU diff --git a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_gfxtim.h b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_gfxtim.h index f5a39fa..8c7e5ea 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_gfxtim.h +++ b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_gfxtim.h @@ -523,18 +523,18 @@ typedef struct /** @defgroup GFXTIM_WatchdogClockSrc GFXTIM Watchdog clock source * @{ */ -#define GFXTIM_WATCHDOG_CLK_SRC_LINE_CLK (0U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Line Clock */ -#define GFXTIM_WATCHDOG_CLK_SRC_FRAME_CLK (1U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Frame Clock */ -#define GFXTIM_WATCHDOG_CLK_SRC_HSYNC_RISING (2U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< HSYNC rising edge */ -#define GFXTIM_WATCHDOG_CLK_SRC_HSYNC_FALLING (3U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< HSYNC falling edge */ -#define GFXTIM_WATCHDOG_CLK_SRC_VSYNC_RISING (4U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< VSYNC rising edge */ -#define GFXTIM_WATCHDOG_CLK_SRC_VSYNC_FALLING (5U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< VSYNC falling edge */ -#define GFXTIM_WATCHDOG_CLK_SRC_TE_RISING (6U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Tearing Effect rising edge */ -#define GFXTIM_WATCHDOG_CLK_SRC_TE_FALLING (7U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Tearing Effect falling edge */ -#define GFXTIM_WATCHDOG_CLK_SRC_EVENT_1 (8U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Event Generator 1 output */ -#define GFXTIM_WATCHDOG_CLK_SRC_EVENT_2 (9U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Event Generator 2 output */ -#define GFXTIM_WATCHDOG_CLK_SRC_EVENT_3 (10U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Event Generator 3 output */ -#define GFXTIM_WATCHDOG_CLK_SRC_EVENT_4 (11U << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Event Generator 4 output */ +#define GFXTIM_WATCHDOG_CLK_SRC_LINE_CLK (0UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Line Clock */ +#define GFXTIM_WATCHDOG_CLK_SRC_FRAME_CLK (1UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Frame Clock */ +#define GFXTIM_WATCHDOG_CLK_SRC_HSYNC_RISING (2UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< HSYNC rising edge */ +#define GFXTIM_WATCHDOG_CLK_SRC_HSYNC_FALLING (3UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< HSYNC falling edge */ +#define GFXTIM_WATCHDOG_CLK_SRC_VSYNC_RISING (4UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< VSYNC rising edge */ +#define GFXTIM_WATCHDOG_CLK_SRC_VSYNC_FALLING (5UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< VSYNC falling edge */ +#define GFXTIM_WATCHDOG_CLK_SRC_TE_RISING (6UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Tearing Effect rising edge */ +#define GFXTIM_WATCHDOG_CLK_SRC_TE_FALLING (7UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Tearing Effect falling edge */ +#define GFXTIM_WATCHDOG_CLK_SRC_EVENT_1 (8UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Event Generator 1 output */ +#define GFXTIM_WATCHDOG_CLK_SRC_EVENT_2 (9UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Event Generator 2 output */ +#define GFXTIM_WATCHDOG_CLK_SRC_EVENT_3 (10UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Event Generator 3 output */ +#define GFXTIM_WATCHDOG_CLK_SRC_EVENT_4 (11UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< Event Generator 4 output */ /** * @} */ diff --git a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_gpio_ex.h b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_gpio_ex.h index 03f97dc..2e314e1 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_gpio_ex.h +++ b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_gpio_ex.h @@ -113,6 +113,7 @@ extern "C" { #define GPIO_AF5_SPI4 ((uint8_t)0x05) /*!< SPI4 Alternate Function mapping */ #define GPIO_AF5_SPI5 ((uint8_t)0x05) /*!< SPI5 Alternate Function mapping */ #define GPIO_AF5_SPI6 ((uint8_t)0x05) /*!< SPI6 Alternate Function mapping */ +#define GPIO_AF5_SYS ((uint8_t)0x05) /*!< AUDIOCLK Alternate Function mapping */ /** * @brief AF 6 selection diff --git a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_hash.h b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_hash.h index 217338b..4255a1e 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_hash.h +++ b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_hash.h @@ -396,7 +396,7 @@ HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash); void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash); void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash); HAL_StatusTypeDef HAL_HASH_GetConfig(HASH_HandleTypeDef *hhash, HASH_ConfigTypeDef *pConf); -HAL_StatusTypeDef HAL_HASH_SetConfig(HASH_HandleTypeDef *hhash, HASH_ConfigTypeDef *pConf); +HAL_StatusTypeDef HAL_HASH_SetConfig(HASH_HandleTypeDef *hhash, const HASH_ConfigTypeDef *pConf); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) diff --git a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_hcd.h b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_hcd.h index 6811070..9725f4d 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_hcd.h +++ b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_hcd.h @@ -103,6 +103,9 @@ typedef struct /** @defgroup HCD_Exported_Constants HCD Exported Constants * @{ */ +#ifndef HAL_HCD_CHANNEL_NAK_COUNT +#define HAL_HCD_CHANNEL_NAK_COUNT 2U +#endif /* HAL_HCD_CHANNEL_NAK_COUNT */ /** @defgroup HCD_Speed HCD Speed * @{ @@ -193,6 +196,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t speed, uint8_t ep_type, uint16_t mps); HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num); +HAL_StatusTypeDef HAL_HCD_HC_Activate(HCD_HandleTypeDef *hhcd, uint8_t ch_num); void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd); void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd); diff --git a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_ltdc.h b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_ltdc.h index 67245ff..0451d71 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_ltdc.h +++ b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_ltdc.h @@ -538,10 +538,10 @@ typedef void (*pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef *hltdc); /*!< pointer /** @defgroup LTDC_ARGB_SIZE LTDC ARGB pixel size in bytes * @{ */ -#define LTDC_ARGB_PIXEL_SIZE_1_BYTE 0U /*!Instance->IASR, MCE_IASR_IAEF) - /** * @brief Clear MCE peripheral illegal/configuration access flag * @param __HANDLE__ pointer to an MCE_HandleTypeDef structure that contains diff --git a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_pssi.h b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_pssi.h index e690667..f5e552c 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_pssi.h +++ b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_pssi.h @@ -200,14 +200,14 @@ typedef enum /** @defgroup ControlSignal_Configuration ControlSignal Configuration * @{ */ -#define HAL_PSSI_DE_RDY_DISABLE (0x0U << PSSI_CR_DERDYCFG_Pos) /*!< Neither DE nor RDY are enabled */ -#define HAL_PSSI_RDY_ENABLE (0x1U << PSSI_CR_DERDYCFG_Pos) /*!< Only RDY enabled */ -#define HAL_PSSI_DE_ENABLE (0x2U << PSSI_CR_DERDYCFG_Pos) /*!< Only DE enabled */ -#define HAL_PSSI_DE_RDY_ALT_ENABLE (0x3U << PSSI_CR_DERDYCFG_Pos) /*!< Both RDY and DE alternate functions enabled */ -#define HAL_PSSI_MAP_RDY_BIDIR_ENABLE (0x4U << PSSI_CR_DERDYCFG_Pos) /*!< Bi-directional on RDY pin */ -#define HAL_PSSI_RDY_MAP_ENABLE (0x5U << PSSI_CR_DERDYCFG_Pos) /*!< Only RDY enabled, mapped to DE pin */ -#define HAL_PSSI_DE_MAP_ENABLE (0x6U << PSSI_CR_DERDYCFG_Pos) /*!< Only DE enabled, mapped to RDY pin */ -#define HAL_PSSI_MAP_DE_BIDIR_ENABLE (0x7U << PSSI_CR_DERDYCFG_Pos) /*!< Bi-directional on DE pin */ +#define HAL_PSSI_DE_RDY_DISABLE (0x0UL << PSSI_CR_DERDYCFG_Pos) /*!< Neither DE nor RDY are enabled */ +#define HAL_PSSI_RDY_ENABLE (0x1UL << PSSI_CR_DERDYCFG_Pos) /*!< Only RDY enabled */ +#define HAL_PSSI_DE_ENABLE (0x2UL << PSSI_CR_DERDYCFG_Pos) /*!< Only DE enabled */ +#define HAL_PSSI_DE_RDY_ALT_ENABLE (0x3UL << PSSI_CR_DERDYCFG_Pos) /*!< Both RDY and DE alternate functions enabled */ +#define HAL_PSSI_MAP_RDY_BIDIR_ENABLE (0x4UL << PSSI_CR_DERDYCFG_Pos) /*!< Bi-directional on RDY pin */ +#define HAL_PSSI_RDY_MAP_ENABLE (0x5UL << PSSI_CR_DERDYCFG_Pos) /*!< Only RDY enabled, mapped to DE pin */ +#define HAL_PSSI_DE_MAP_ENABLE (0x6UL << PSSI_CR_DERDYCFG_Pos) /*!< Only DE enabled, mapped to RDY pin */ +#define HAL_PSSI_MAP_DE_BIDIR_ENABLE (0x7UL << PSSI_CR_DERDYCFG_Pos) /*!< Bi-directional on DE pin */ /** * @} diff --git a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_rcc.h b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_rcc.h index fa2a51a..b89223e 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_rcc.h +++ b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_rcc.h @@ -455,73 +455,73 @@ typedef struct /** @defgroup RCC_RTC_Clock_Source RTC Clock Source * @{ */ -#define RCC_RTCCLKSOURCE_DISABLE 0U /*!< No clock used as RTC clock */ -#define RCC_RTCCLKSOURCE_LSE RCC_CCIPR7_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ -#define RCC_RTCCLKSOURCE_LSI RCC_CCIPR7_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV1 ((0x00U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 1 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV2 ((0x01U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 2 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV3 ((0x02U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 3 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV4 ((0x03U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 4 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV5 ((0x04U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 5 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV6 ((0x05U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 6 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV7 ((0x06U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 7 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV8 ((0x07U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 8 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV9 ((0x08U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 9 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV10 ((0x09U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 10 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV11 ((0x0AU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 11 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV12 ((0x0BU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 12 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV13 ((0x0CU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 13 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV14 ((0x0DU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 14 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV15 ((0x0EU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 15 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV16 ((0x0FU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 16 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV17 ((0x10U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 17 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV18 ((0x11U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 18 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV19 ((0x12U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 19 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV20 ((0x13U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 20 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV21 ((0x14U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 21 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV22 ((0x15U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 22 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV23 ((0x16U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 23 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV24 ((0x17U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 24 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV25 ((0x18U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 25 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV26 ((0x19U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 26 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV27 ((0x1AU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 27 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV28 ((0x1BU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 28 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV29 ((0x1CU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 29 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV30 ((0x1DU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 30 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV31 ((0x1EU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 31 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV32 ((0x1FU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 32 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV33 ((0x20U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 33 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV34 ((0x21U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 34 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV35 ((0x22U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 35 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV36 ((0x23U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 36 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV37 ((0x24U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 37 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV38 ((0x25U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 38 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV39 ((0x26U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 39 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV40 ((0x27U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 40 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV41 ((0x28U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 41 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV42 ((0x29U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 42 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV43 ((0x2AU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 43 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV44 ((0x2BU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 44 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV45 ((0x2CU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 45 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV46 ((0x2DU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 46 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV47 ((0x2EU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 47 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV48 ((0x2FU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 48 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV49 ((0x30U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 49 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV50 ((0x31U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 50 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV51 ((0x32U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 51 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV52 ((0x33U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 52 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV53 ((0x34U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 53 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV54 ((0x35U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 54 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV55 ((0x36U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 55 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV56 ((0x37U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 56 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV57 ((0x38U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 57 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV58 ((0x39U << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 58 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV59 ((0x3AU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 59 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV60 ((0x3BU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 60 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV61 ((0x3CU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 61 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV62 ((0x3DU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 62 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV63 ((0x3EU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 63 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV64 ((0x3FU << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 64 used as RTC clock */ +#define RCC_RTCCLKSOURCE_DISABLE 0UL /*!< No clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_LSE RCC_CCIPR7_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_LSI RCC_CCIPR7_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV1 ((0x00UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 1 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV2 ((0x01UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 2 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV3 ((0x02UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 3 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV4 ((0x03UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 4 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV5 ((0x04UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 5 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV6 ((0x05UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 6 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV7 ((0x06UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 7 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV8 ((0x07UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 8 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV9 ((0x08UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 9 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV10 ((0x09UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 10 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV11 ((0x0AUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 11 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV12 ((0x0BUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 12 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV13 ((0x0CUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 13 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV14 ((0x0DUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 14 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV15 ((0x0EUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 15 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV16 ((0x0FUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 16 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV17 ((0x10UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 17 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV18 ((0x11UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 18 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV19 ((0x12UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 19 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV20 ((0x13UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 20 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV21 ((0x14UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 21 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV22 ((0x15UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 22 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV23 ((0x16UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 23 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV24 ((0x17UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 24 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV25 ((0x18UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 25 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV26 ((0x19UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 26 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV27 ((0x1AUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 27 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV28 ((0x1BUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 28 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV29 ((0x1CUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 29 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV30 ((0x1DUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 30 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV31 ((0x1EUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 31 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV32 ((0x1FUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 32 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV33 ((0x20UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 33 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV34 ((0x21UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 34 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV35 ((0x22UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 35 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV36 ((0x23UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 36 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV37 ((0x24UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 37 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV38 ((0x25UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 38 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV39 ((0x26UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 39 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV40 ((0x27UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 40 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV41 ((0x28UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 41 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV42 ((0x29UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 42 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV43 ((0x2AUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 43 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV44 ((0x2BUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 44 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV45 ((0x2CUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 45 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV46 ((0x2DUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 46 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV47 ((0x2EUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 47 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV48 ((0x2FUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 48 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV49 ((0x30UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 49 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV50 ((0x31UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 50 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV51 ((0x32UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 51 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV52 ((0x33UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 52 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV53 ((0x34UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 53 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV54 ((0x35UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 54 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV55 ((0x36UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 55 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV56 ((0x37UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 56 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV57 ((0x38UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 57 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV58 ((0x39UL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 58 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV59 ((0x3AUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 59 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV60 ((0x3BUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 60 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV61 ((0x3CUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 61 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV62 ((0x3DUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 62 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV63 ((0x3EUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 63 used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV64 ((0x3FUL << RCC_CCIPR7_RTCPRE_Pos) | RCC_CCIPR7_RTCSEL) /*!< HSE oscillator clock divided by 64 used as RTC clock */ /** * @} */ @@ -4319,6 +4319,8 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t R void HAL_RCC_EnableCSS(void); uint32_t HAL_RCC_GetCpuClockFreq(void); uint32_t HAL_RCC_GetSysClockFreq(void); +uint32_t HAL_RCC_GetNPUClockFreq(void); +uint32_t HAL_RCC_GetNPURAMSClockFreq(void); uint32_t HAL_RCC_GetHCLKFreq(void); uint32_t HAL_RCC_GetPCLK1Freq(void); uint32_t HAL_RCC_GetPCLK2Freq(void); diff --git a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_rcc_ex.h b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_rcc_ex.h index 785ddb8..de90bd3 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_rcc_ex.h +++ b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_rcc_ex.h @@ -2591,6 +2591,7 @@ uint32_t HAL_RCCEx_GetPLL1CLKFreq(void); uint32_t HAL_RCCEx_GetPLL2CLKFreq(void); uint32_t HAL_RCCEx_GetPLL3CLKFreq(void); uint32_t HAL_RCCEx_GetPLL4CLKFreq(void); +uint32_t HAL_RCCEx_GetTIMGFreq(void); /** * @} */ diff --git a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_rif.h b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_rif.h index 210dd18..0992221 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_rif.h +++ b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_rif.h @@ -110,6 +110,8 @@ extern "C" { #define RIF_RISC_PERIPH_INDEX_USART10 (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC24_Pos) #define RIF_RISC_PERIPH_INDEX_LPUART1 (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC25_Pos) #define RIF_RISC_PERIPH_INDEX_FDCAN1 (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC26_Pos) +#define RIF_RISC_PERIPH_INDEX_FDCAN2 (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC26_Pos) +#define RIF_RISC_PERIPH_INDEX_FDCAN3 (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC26_Pos) #define RIF_RISC_PERIPH_INDEX_TIM1 (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC27_Pos) #define RIF_RISC_PERIPH_INDEX_TIM2 (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC28_Pos) #define RIF_RISC_PERIPH_INDEX_TIM3 (RIF_PERIPH_REG0 | RIFSC_RISC_SECCFGRx_SEC29_Pos) @@ -546,7 +548,7 @@ typedef struct */ /* Private constants ---------------------------------------------------------*/ -/** @defgroup RCC_Private_Constants RCC Private Constants +/** @defgroup RIF_Private_Constants RIF Private Constants * @{ */ @@ -556,9 +558,8 @@ typedef struct /* Composition definition for Peripheral identifier parameter (PeriphId) used in * RIF RISC and IAC related functions. * Bitmap Definition - * bits[31:28] Field "register". Define the register index a peripheral belongs to. - * bits[4:0] Field "bit position". Define the bit position within the - * register dedicated to the peripheral, value from 0 to 31. + * bits[31:28] define the register index a peripheral belongs to, value from 0 to 5. + * bits[4:0] define the bit position within the register, value from 0 to 31. */ #define RIF_PERIPH_REG_SHIFT 28U #define RIF_PERIPH_REG 0xF0000000U @@ -576,8 +577,8 @@ typedef struct /** @defgroup RIF_MASK RIF register masks * @{ */ -#define RIF_CID_MASK 0x000000FFU -#define RIF_ATTRIBUTE_MASK 0x00000003U +#define RIF_CID_MASK 0x000000FFUL +#define RIF_ATTRIBUTE_MASK 0x00000003UL #define RISAF_READ_WRITE_MASK (RISAF_READ_ENABLE | RISAF_WRITE_ENABLE) /** * @} diff --git a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_rng.h b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_rng.h index fa72d71..ca50e45 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_rng.h +++ b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_rng.h @@ -178,6 +178,7 @@ typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t #define HAL_RNG_ERROR_BUSY 0x00000004U /*!< Busy error */ #define HAL_RNG_ERROR_SEED 0x00000008U /*!< Seed error */ #define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */ +#define HAL_RNG_ERROR_RECOVERSEED 0x00000020U /*!< Recover Seed error */ /** * @} */ diff --git a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_sdio.h b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_sdio.h index 384ea98..0234fef 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_sdio.h +++ b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_sdio.h @@ -27,7 +27,7 @@ extern "C" { /* Includes ----------------------------------------------------------------------------------------------------------*/ #include "stm32n6xx_ll_sdmmc.h" -/** @addtogroup STM32U5xx_HAL_Driver +/** @addtogroup STM32N6xx_HAL_Driver * @{ */ #if defined (SDMMC1) || defined (SDMMC2) @@ -187,11 +187,6 @@ typedef enum * @{ */ typedef void (*pSDIO_CallbackTypeDef)(SDIO_HandleTypeDef *hsdio); -#if (USE_SDIO_TRANSCEIVER != 0U) -typedef void (*pSDIO_TransceiverCallbackTypeDef)(SDIO_HandleTypeDef *hsdio, FlagStatus status); -#endif /* USE_SDIO_TRANSCEIVER */ - -typedef HAL_StatusTypeDef(*pSDIO_IdentifyCardCallbackTypeDef)(SDIO_HandleTypeDef *hsdio); /** * @} */ @@ -351,7 +346,6 @@ typedef void (*HAL_SDIO_IOFunction_CallbackTypeDef)(SDIO_HandleTypeDef *hsdio, u * @brief Enable the SDIO device interrupt. * @param __HANDLE__ SDIO Handle. * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled. - * This parameter can be one or a combination of @ref SDMMC_LL_Interrupt_sources. * @retval None */ #define __HAL_SDIO_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) @@ -360,7 +354,6 @@ typedef void (*HAL_SDIO_IOFunction_CallbackTypeDef)(SDIO_HandleTypeDef *hsdio, u * @brief Disable the SDIO device interrupt. * @param __HANDLE__ SDIO Handle. * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled. - * This parameter can be one or a combination of @ref SDMMC_LL_Interrupt_sources. * @retval None */ #define __HAL_SDIO_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) @@ -369,7 +362,6 @@ typedef void (*HAL_SDIO_IOFunction_CallbackTypeDef)(SDIO_HandleTypeDef *hsdio, u * @brief Check whether the specified SDIO flag is set or not. * @param __HANDLE__ SDIO Handle. * @param __FLAG__ specifies the flag to check. - * This parameter can be one of @ref SDMMC_LL_Flags. * @retval The new state of SDIO FLAG (SET or RESET). */ #define __HAL_SDIO_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__)) @@ -378,7 +370,6 @@ typedef void (*HAL_SDIO_IOFunction_CallbackTypeDef)(SDIO_HandleTypeDef *hsdio, u * @brief Clear the SDIO's pending flags. * @param __HANDLE__ SDIO Handle. * @param __FLAG__ specifies the flag to clear. - * This parameter can be one or a combination of @ref SDMMC_LL_Flags. * @retval None */ #define __HAL_SDIO_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__)) @@ -387,7 +378,6 @@ typedef void (*HAL_SDIO_IOFunction_CallbackTypeDef)(SDIO_HandleTypeDef *hsdio, u * @brief Check whether the specified SDIO interrupt has occurred or not. * @param __HANDLE__ SDIO Handle. * @param __INTERRUPT__ specifies the SDMMC interrupt source to check. - * This parameter can be one of @ref SDMMC_LL_Interrupt_sources. * @retval The new state of SDIO IT (SET or RESET). */ #define __HAL_SDIO_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__)) @@ -439,19 +429,21 @@ HAL_StatusTypeDef HAL_SDIO_GetCardFBRRegister(SDIO_HandleTypeDef *hsdio, HAL_SDI /** @defgroup SDIO_Exported_Functions_Group3 Process functions * @{ */ -HAL_StatusTypeDef HAL_SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, HAL_SDIO_DirectCmd_TypeDef *Argument, uint8_t *pData); -HAL_StatusTypeDef HAL_SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, HAL_SDIO_DirectCmd_TypeDef *Argument, uint8_t Data); +HAL_StatusTypeDef HAL_SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_DirectCmd_TypeDef *Argument, + uint8_t *pData); +HAL_StatusTypeDef HAL_SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_DirectCmd_TypeDef *Argument, + uint8_t Data); -HAL_StatusTypeDef HAL_SDIO_ReadExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, +HAL_StatusTypeDef HAL_SDIO_ReadExtended(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_ExtendedCmd_TypeDef *Argument, uint8_t *pData, uint32_t Size_byte, uint32_t Timeout_Ms); -HAL_StatusTypeDef HAL_SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, +HAL_StatusTypeDef HAL_SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_ExtendedCmd_TypeDef *Argument, uint8_t *pData, uint32_t Size_byte, uint32_t Timeout_Ms); -HAL_StatusTypeDef HAL_SDIO_ReadExtended_DMA(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, +HAL_StatusTypeDef HAL_SDIO_ReadExtended_DMA(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_ExtendedCmd_TypeDef *Argument, uint8_t *pData, uint32_t Size_byte); -HAL_StatusTypeDef HAL_SDIO_WriteExtended_DMA(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, +HAL_StatusTypeDef HAL_SDIO_WriteExtended_DMA(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_ExtendedCmd_TypeDef *Argument, uint8_t *pData, uint32_t Size_byte); /** * @} diff --git a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_smartcard.h b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_smartcard.h index 98b87bb..e612a9b 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_smartcard.h +++ b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_smartcard.h @@ -713,13 +713,13 @@ typedef void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsmartcard) */ #define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ SMARTCARD_CR_POS) == 1U)?\ - ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\ + ((__HANDLE__)->Instance->CR1 &= ~ (1UL <<\ ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ SMARTCARD_CR_POS) == 2U)?\ - ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\ + ((__HANDLE__)->Instance->CR2 &= ~ (1UL <<\ ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\ + ((__HANDLE__)->Instance->CR3 &= ~ (1UL <<\ ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Check whether the specified SmartCard interrupt has occurred or not. diff --git a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_uart.h b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_uart.h index 97c47f3..4db4c20 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_uart.h +++ b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_uart.h @@ -47,12 +47,10 @@ typedef struct { uint32_t BaudRate; /*!< This member configures the UART communication baud rate. The baud rate register is computed using the following formula: - LPUART: - ======= + @note For LPUART : Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) - where lpuart_ker_ck_pres is the UART input clock divided by a prescaler - UART: - ===== + where lpuart_ker_ck_pres is the UART input clock divided by a prescaler. + @note For UART : - If oversampling is 16 or in LIN mode, Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate))) - If oversampling is 8, diff --git a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_usart.h b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_usart.h index eee6274..6feb9cb 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_usart.h +++ b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_usart.h @@ -537,10 +537,10 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin */ #define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)\ (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ - ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR1 |= (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ - ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK)))) + ((__HANDLE__)->Instance->CR2 |= (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1UL << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Disable the specified USART interrupt. * @param __HANDLE__ specifies the USART Handle. @@ -562,10 +562,10 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin */ #define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)\ (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ - ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR1 &= ~ (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ - ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK)))) + ((__HANDLE__)->Instance->CR2 &= ~ (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1UL << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Check whether the specified USART interrupt has occurred or not. * @param __HANDLE__ specifies the USART Handle. diff --git a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_xspi.h b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_xspi.h index 21b0fbb..e0297c0 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_xspi.h +++ b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_hal_xspi.h @@ -74,8 +74,7 @@ typedef struct uint32_t SampleShifting; /*!< It allows to delay to 1/2 cycle the data sampling in order to take in account external signal delays. This parameter can be a value of @ref XSPI_SampleShifting */ - uint32_t DelayHoldQuarterCycle; /*!< It allows to hold to 1/4 cycle the data. - This parameter can be a value of @ref XSPI_DelayHoldQuarterCycle */ + uint32_t DelayHoldQuarterCycle; /*!< This parameter is deprecated and is not used on STM32N6xx devices */ uint32_t ChipSelectBoundary; /*!< It enables the transaction boundary feature and defines the boundary of bytes to release the chip select. This parameter can be a value of @ref XSPI_ChipSelectBoundary */ @@ -458,6 +457,7 @@ typedef struct */ /** @defgroup XSPI_DelayHoldQuarterCycle XSPI Delay Hold Quarter Cycle + * @note These constants are deprecated and are not expected to be used anymore. * @{ */ #define HAL_XSPI_DHQC_DISABLE (0x00000000U) /*!< No Delay */ @@ -801,21 +801,21 @@ typedef struct * @} */ -/** @defgroup XSPIM_MemorySelect_Override XSPIM Memory Select Override +/** @defgroup XSPI_MaxCal XSPI Calibration Maximal Value * @{ */ -#define HAL_XSPI_CSSEL_OVR_DISABLED (0x00000000U) -#define HAL_XSPI_CSSEL_OVR_NCS1 (0x00000010U) /*!< The chip select signal from XSPI is sent to NCS1 */ -#define HAL_XSPI_CSSEL_OVR_NCS2 (0x00000070U) /*!< The chip select signal from XSPI is sent to NCS2 */ +#define HAL_XSPI_MAXCAL_NOT_REACHED (0x00000000U) /*!< Memory-clock perido inside the range of DLL master */ +#define HAL_XSPI_MAXCAL_REACHED ((uint32_t)XSPI_CALFCR_CALMAX) /*!< Memory-clock period outside the range of DLL master (max delay values used) */ /** * @} */ -/** @defgroup XSPI_MaxCal XSPI Calibration Maximal Value +/** @defgroup XSPIM_MemorySelect_Override XSPIM Memory Select Override * @{ */ -#define HAL_XSPI_MAXCAL_NOT_REACHED (0x00000000U) /*!< Memory-clock perido inside the range of DLL master */ -#define HAL_XSPI_MAXCAL_REACHED ((uint32_t)XSPI_CALFCR_CALMAX) /*!< Memory-clock period outside the range of DLL master (max delay values used) */ +#define HAL_XSPI_CSSEL_OVR_DISABLED (0x00000000U) +#define HAL_XSPI_CSSEL_OVR_NCS1 (0x00000010U) /*!< The chip select signal from XSPI is sent to NCS1 */ +#define HAL_XSPI_CSSEL_OVR_NCS2 (0x00000070U) /*!< The chip select signal from XSPI is sent to NCS2 */ /** * @} */ @@ -952,29 +952,29 @@ void HAL_XSPI_MspDeInit(XSPI_HandleTypeDef *hxspi); void HAL_XSPI_IRQHandler(XSPI_HandleTypeDef *hxspi); /* XSPI command configuration functions */ -HAL_StatusTypeDef HAL_XSPI_Command(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pCmd, +HAL_StatusTypeDef HAL_XSPI_Command(XSPI_HandleTypeDef *hxspi, const XSPI_RegularCmdTypeDef *pCmd, uint32_t Timeout); -HAL_StatusTypeDef HAL_XSPI_Command_IT(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pCmd); -HAL_StatusTypeDef HAL_XSPI_HyperbusCfg(XSPI_HandleTypeDef *hxspi, XSPI_HyperbusCfgTypeDef *const pCfg, +HAL_StatusTypeDef HAL_XSPI_Command_IT(XSPI_HandleTypeDef *hxspi, const XSPI_RegularCmdTypeDef *pCmd); +HAL_StatusTypeDef HAL_XSPI_HyperbusCfg(XSPI_HandleTypeDef *hxspi, const XSPI_HyperbusCfgTypeDef *pCfg, uint32_t Timeout); -HAL_StatusTypeDef HAL_XSPI_HyperbusCmd(XSPI_HandleTypeDef *hxspi, XSPI_HyperbusCmdTypeDef *const pCmd, +HAL_StatusTypeDef HAL_XSPI_HyperbusCmd(XSPI_HandleTypeDef *hxspi, const XSPI_HyperbusCmdTypeDef *pCmd, uint32_t Timeout); /* XSPI indirect mode functions */ HAL_StatusTypeDef HAL_XSPI_Transmit(XSPI_HandleTypeDef *hxspi, const uint8_t *pData, uint32_t Timeout); -HAL_StatusTypeDef HAL_XSPI_Receive(XSPI_HandleTypeDef *hxspi, uint8_t *const pData, uint32_t Timeout); +HAL_StatusTypeDef HAL_XSPI_Receive(XSPI_HandleTypeDef *hxspi, uint8_t *pData, uint32_t Timeout); HAL_StatusTypeDef HAL_XSPI_Transmit_IT(XSPI_HandleTypeDef *hxspi, const uint8_t *pData); -HAL_StatusTypeDef HAL_XSPI_Receive_IT(XSPI_HandleTypeDef *hxspi, uint8_t *const pData); +HAL_StatusTypeDef HAL_XSPI_Receive_IT(XSPI_HandleTypeDef *hxspi, uint8_t *pData); HAL_StatusTypeDef HAL_XSPI_Transmit_DMA(XSPI_HandleTypeDef *hxspi, const uint8_t *pData); -HAL_StatusTypeDef HAL_XSPI_Receive_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *const pData); +HAL_StatusTypeDef HAL_XSPI_Receive_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *pData); /* XSPI status flag polling mode functions */ -HAL_StatusTypeDef HAL_XSPI_AutoPolling(XSPI_HandleTypeDef *hxspi, XSPI_AutoPollingTypeDef *const pCfg, +HAL_StatusTypeDef HAL_XSPI_AutoPolling(XSPI_HandleTypeDef *hxspi, const XSPI_AutoPollingTypeDef *pCfg, uint32_t Timeout); -HAL_StatusTypeDef HAL_XSPI_AutoPolling_IT(XSPI_HandleTypeDef *hxspi, XSPI_AutoPollingTypeDef *const pCfg); +HAL_StatusTypeDef HAL_XSPI_AutoPolling_IT(XSPI_HandleTypeDef *hxspi, const XSPI_AutoPollingTypeDef *pCfg); /* XSPI memory-mapped mode functions */ -HAL_StatusTypeDef HAL_XSPI_MemoryMapped(XSPI_HandleTypeDef *hxspi, XSPI_MemoryMappedTypeDef *const pCfg); +HAL_StatusTypeDef HAL_XSPI_MemoryMapped(XSPI_HandleTypeDef *hxspi, const XSPI_MemoryMappedTypeDef *pCfg); /* Callback functions in non-blocking modes ***********************************/ void HAL_XSPI_ErrorCallback(XSPI_HandleTypeDef *hxspi); @@ -1028,7 +1028,7 @@ uint32_t HAL_XSPI_GetState(const XSPI_HandleTypeDef *hxspi); /** @addtogroup XSPI_Exported_Functions_Group4 IO Manager configuration function * @{ */ -HAL_StatusTypeDef HAL_XSPIM_Config(XSPI_HandleTypeDef *const hxspi, XSPIM_CfgTypeDef *const pCfg, uint32_t Timeout); +HAL_StatusTypeDef HAL_XSPIM_Config(XSPI_HandleTypeDef *hxspi, const XSPIM_CfgTypeDef *pCfg, uint32_t Timeout); /** * @} @@ -1038,8 +1038,8 @@ HAL_StatusTypeDef HAL_XSPIM_Config(XSPI_HandleTypeDef *const hxspi, XSPIM_Cf /** @addtogroup XSPI_Exported_Functions_Group6 High-speed interface and calibration functions * @{ */ -HAL_StatusTypeDef HAL_XSPI_GetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSCalTypeDef *const pCfg); -HAL_StatusTypeDef HAL_XSPI_SetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSCalTypeDef *const pCfg); +HAL_StatusTypeDef HAL_XSPI_GetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSCalTypeDef *pCfg); +HAL_StatusTypeDef HAL_XSPI_SetDelayValue(XSPI_HandleTypeDef *hxspi, const XSPI_HSCalTypeDef *pCfg); /** * @} @@ -1272,6 +1272,10 @@ HAL_StatusTypeDef HAL_XSPI_SetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSC #define IS_XSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) +#define IS_XSPI_PROG_DATA(SET_DATA, REQ_DATA) ((SET_DATA) == (REQ_DATA)) + +#define IS_XSPI_PROG_ADDR(SET_ADDR, REQ_ADDR) ((SET_ADDR) == (REQ_ADDR)) + #define IS_XSPIM_IO_PORT(PORT) (((PORT) == HAL_XSPIM_IOPORT_1) || \ ((PORT) == HAL_XSPIM_IOPORT_2)) diff --git a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_adc.h b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_adc.h index abfa8a4..c8453ae 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_adc.h +++ b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_adc.h @@ -2715,8 +2715,7 @@ static const uint8_t ADC_CHANNEL_DIFF_LUT[2][20] = * @brief Helper macro to calculate the voltage (unit: mVolt) * corresponding to a ADC conversion data (unit: digital value). * @note Analog reference voltage (Vref+) must be either known from - * user board environment or can be calculated using ADC measurement - * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * user board environment. * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) * (unit: digital value). @@ -2742,8 +2741,7 @@ static const uint8_t ADC_CHANNEL_DIFF_LUT[2][20] = * middle code in. Converted voltage can be positive or negative * depending on differential input voltages. * @note Analog reference voltage (Vref+) must be either known from - * user board environment or can be calculated using ADC measurement - * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * user board environment. * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) * @param __ADC_DATA__ ADC conversion data (unit: digital value). * @param __ADC_RESOLUTION__ This parameter can be one of the following values: diff --git a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_cortex.h b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_cortex.h index c0ec0a6..7f5dcea 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_cortex.h +++ b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_cortex.h @@ -1005,13 +1005,13 @@ __STATIC_INLINE void LL_MPU_ConfigAttributes(uint32_t AttIndex, uint32_t Attrib if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4) { /* Modify Attr field of MPU_MAIR0 accordingly */ - MODIFY_REG(MPU->MAIR0, (0xFFU << (AttIndex * 8U)), (Attributes << (AttIndex * 8U))); + MODIFY_REG(MPU->MAIR0, (0xFFUL << (AttIndex * 8U)), (Attributes << (AttIndex * 8U))); } /* When selected index is in range [4;7] */ else { /* Modify Attr field of MPU_MAIR1 accordingly */ - MODIFY_REG(MPU->MAIR1, (0xFFU << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U))); + MODIFY_REG(MPU->MAIR1, (0xFFUL << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U))); } } @@ -1038,13 +1038,13 @@ __STATIC_INLINE void LL_MPU_ConfigAttributes_NS(uint32_t AttIndex, uint32_t Att if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4) { /* Modify Attr field of MPU_MAIR0_NS accordingly */ - MODIFY_REG(MPU_NS->MAIR0, (0xFFU << (AttIndex * 8U)), (Attributes << (AttIndex * 8U))); + MODIFY_REG(MPU_NS->MAIR0, (0xFFUL << (AttIndex * 8U)), (Attributes << (AttIndex * 8U))); } /* When selected index is in range [4;7] */ else { /* Modify Attr field of MPU_MAIR1_NS accordingly */ - MODIFY_REG(MPU_NS->MAIR1, (0xFFU << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U))); + MODIFY_REG(MPU_NS->MAIR1, (0xFFUL << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U))); } } #endif /* MPU_NS */ diff --git a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_dma.h b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_dma.h index 78e78c9..fb75d15 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_dma.h +++ b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_dma.h @@ -649,7 +649,7 @@ typedef struct */ #endif /* USE_FULL_LL_DRIVER */ -/** @defgroup DMA_LL_EC_CID Priority Level +/** @defgroup DMA_LL_EC_CID Static Isolation CID * @{ */ #define LL_DMA_CHANNEL_STATIC_CID_0 (0U<CCMR1, CCMode << LL_LPTIM_SHIFT_TAB_CCxSEL[Channel]); + MODIFY_REG(LPTIMx->CCMR1, LPTIM_CCMR1_CC1SEL << LL_LPTIM_SHIFT_TAB_CCxSEL[Channel], + CCMode << LL_LPTIM_SHIFT_TAB_CCxSEL[Channel]); } /** diff --git a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_lpuart.h b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_lpuart.h index 86469ba..7e30e35 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_lpuart.h +++ b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_lpuart.h @@ -56,6 +56,10 @@ static const uint16_t LPUART_PRESCALER_TAB[] = (uint16_t)32, (uint16_t)64, (uint16_t)128, + (uint16_t)256, + (uint16_t)256, + (uint16_t)256, + (uint16_t)256, (uint16_t)256 }; /** diff --git a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_rcc.h b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_rcc.h index 657089d..7bf4299 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_rcc.h +++ b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_rcc.h @@ -149,11 +149,11 @@ typedef struct * @{ */ #if !defined (HSE_VALUE) -#define HSE_VALUE 48000000U /*!< Value of the HSE oscillator in Hz */ /* N6 FPGA was 30 MHz */ +#define HSE_VALUE 48000000U /*!< Value of the HSE oscillator in Hz */ #endif /* HSE_VALUE */ #if !defined (HSI_VALUE) -#define HSI_VALUE 64000000U /*!< Value of the HSI oscillator in Hz */ /* N6 FPGA was 48 MHz */ +#define HSI_VALUE 64000000U /*!< Value of the HSI oscillator in Hz */ #endif /* HSI_VALUE */ #if !defined (MSI_VALUE) @@ -161,7 +161,7 @@ typedef struct #endif /* MSI_VALUE */ #if !defined (LSE_VALUE) -#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ /* N6 FPGA was 32 KHz*/ +#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ #endif /* LSE_VALUE */ #if !defined (LSI_VALUE) @@ -718,7 +718,7 @@ typedef struct #define LL_RCC_I2C2_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C2SEL, RCC_CCIPR4_I2C2SEL_Pos,\ RCC_CCIPR4_I2C2SEL_2 | RCC_CCIPR4_I2C2SEL_0) -#define LL_RCC_I2C3_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos, 0U) +#define LL_RCC_I2C3_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos, 0UL) #define LL_RCC_I2C3_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos,\ RCC_CCIPR4_I2C3SEL_0) #define LL_RCC_I2C3_CLKSOURCE_IC10 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos,\ @@ -730,7 +730,7 @@ typedef struct #define LL_RCC_I2C3_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos,\ RCC_CCIPR4_I2C3SEL_2| RCC_CCIPR4_I2C3SEL_0) -#define LL_RCC_I2C4_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C4SEL, RCC_CCIPR4_I2C4SEL_Pos, 0U) +#define LL_RCC_I2C4_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C4SEL, RCC_CCIPR4_I2C4SEL_Pos, 0UL) #define LL_RCC_I2C4_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C4SEL, RCC_CCIPR4_I2C4SEL_Pos,\ RCC_CCIPR4_I2C4SEL_0) #define LL_RCC_I2C4_CLKSOURCE_IC10 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C4SEL, RCC_CCIPR4_I2C4SEL_Pos,\ @@ -748,7 +748,7 @@ typedef struct /** @defgroup RCC_LL_EC_I3C_CLKSOURCE Peripheral I3C clock source selection * @{ */ -#define LL_RCC_I3C1_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos, 0U) +#define LL_RCC_I3C1_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos, 0UL) #define LL_RCC_I3C1_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos,\ RCC_CCIPR4_I3C1SEL_0) #define LL_RCC_I3C1_CLKSOURCE_IC10 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos,\ @@ -760,7 +760,7 @@ typedef struct #define LL_RCC_I3C1_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos,\ RCC_CCIPR4_I3C1SEL_2| RCC_CCIPR4_I3C1SEL_0) -#define LL_RCC_I3C2_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos, 0U) +#define LL_RCC_I3C2_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos, 0UL) #define LL_RCC_I3C2_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos,\ RCC_CCIPR4_I3C2SEL_0) #define LL_RCC_I3C2_CLKSOURCE_IC10 LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos,\ @@ -778,7 +778,7 @@ typedef struct /** @defgroup RCC_LL_EC_LPTIM_CLKSOURCE Peripheral LPTIM clock source selection * @{ */ -#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM1SEL, RCC_CCIPR12_LPTIM1SEL_Pos, 0U) +#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM1SEL, RCC_CCIPR12_LPTIM1SEL_Pos, 0UL) #define LL_RCC_LPTIM1_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM1SEL, RCC_CCIPR12_LPTIM1SEL_Pos, RCC_CCIPR12_LPTIM1SEL_0) #define LL_RCC_LPTIM1_CLKSOURCE_IC15 LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM1SEL, RCC_CCIPR12_LPTIM1SEL_Pos, RCC_CCIPR12_LPTIM1SEL_1) #define LL_RCC_LPTIM1_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM1SEL, RCC_CCIPR12_LPTIM1SEL_Pos, RCC_CCIPR12_LPTIM1SEL_1 |\ @@ -787,7 +787,7 @@ typedef struct #define LL_RCC_LPTIM1_CLKSOURCE_TIMG LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM1SEL, RCC_CCIPR12_LPTIM1SEL_Pos, RCC_CCIPR12_LPTIM1SEL_2 |\ RCC_CCIPR12_LPTIM1SEL_0) -#define LL_RCC_LPTIM2_CLKSOURCE_PCLK4 LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM2SEL, RCC_CCIPR12_LPTIM2SEL_Pos, 0U) +#define LL_RCC_LPTIM2_CLKSOURCE_PCLK4 LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM2SEL, RCC_CCIPR12_LPTIM2SEL_Pos, 0UL) #define LL_RCC_LPTIM2_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM2SEL, RCC_CCIPR12_LPTIM2SEL_Pos, RCC_CCIPR12_LPTIM2SEL_0) #define LL_RCC_LPTIM2_CLKSOURCE_IC15 LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM2SEL, RCC_CCIPR12_LPTIM2SEL_Pos, RCC_CCIPR12_LPTIM2SEL_1) #define LL_RCC_LPTIM2_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM2SEL, RCC_CCIPR12_LPTIM2SEL_Pos, RCC_CCIPR12_LPTIM2SEL_1 |\ @@ -796,7 +796,7 @@ typedef struct #define LL_RCC_LPTIM2_CLKSOURCE_TIMG LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM2SEL, RCC_CCIPR12_LPTIM2SEL_Pos, RCC_CCIPR12_LPTIM2SEL_2 |\ RCC_CCIPR12_LPTIM2SEL_0) -#define LL_RCC_LPTIM3_CLKSOURCE_PCLK4 LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM3SEL, RCC_CCIPR12_LPTIM3SEL_Pos, 0U) +#define LL_RCC_LPTIM3_CLKSOURCE_PCLK4 LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM3SEL, RCC_CCIPR12_LPTIM3SEL_Pos, 0UL) #define LL_RCC_LPTIM3_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM3SEL, RCC_CCIPR12_LPTIM3SEL_Pos, RCC_CCIPR12_LPTIM3SEL_0) #define LL_RCC_LPTIM3_CLKSOURCE_IC15 LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM3SEL, RCC_CCIPR12_LPTIM3SEL_Pos, RCC_CCIPR12_LPTIM3SEL_1) #define LL_RCC_LPTIM3_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM3SEL, RCC_CCIPR12_LPTIM3SEL_Pos, RCC_CCIPR12_LPTIM3SEL_1 |\ @@ -805,7 +805,7 @@ typedef struct #define LL_RCC_LPTIM3_CLKSOURCE_TIMG LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM3SEL, RCC_CCIPR12_LPTIM3SEL_Pos, RCC_CCIPR12_LPTIM3SEL_2 |\ RCC_CCIPR12_LPTIM3SEL_0) -#define LL_RCC_LPTIM4_CLKSOURCE_PCLK4 LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM4SEL, RCC_CCIPR12_LPTIM4SEL_Pos, 0U) +#define LL_RCC_LPTIM4_CLKSOURCE_PCLK4 LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM4SEL, RCC_CCIPR12_LPTIM4SEL_Pos, 0UL) #define LL_RCC_LPTIM4_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM4SEL, RCC_CCIPR12_LPTIM4SEL_Pos, RCC_CCIPR12_LPTIM4SEL_0) #define LL_RCC_LPTIM4_CLKSOURCE_IC15 LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM4SEL, RCC_CCIPR12_LPTIM4SEL_Pos, RCC_CCIPR12_LPTIM4SEL_1) #define LL_RCC_LPTIM4_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM4SEL, RCC_CCIPR12_LPTIM4SEL_Pos, RCC_CCIPR12_LPTIM4SEL_1 |\ @@ -814,7 +814,7 @@ typedef struct #define LL_RCC_LPTIM4_CLKSOURCE_TIMG LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM4SEL, RCC_CCIPR12_LPTIM4SEL_Pos, RCC_CCIPR12_LPTIM4SEL_2 |\ RCC_CCIPR12_LPTIM4SEL_0) -#define LL_RCC_LPTIM5_CLKSOURCE_PCLK4 LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM5SEL, RCC_CCIPR12_LPTIM5SEL_Pos, 0U) +#define LL_RCC_LPTIM5_CLKSOURCE_PCLK4 LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM5SEL, RCC_CCIPR12_LPTIM5SEL_Pos, 0UL) #define LL_RCC_LPTIM5_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM5SEL, RCC_CCIPR12_LPTIM5SEL_Pos, RCC_CCIPR12_LPTIM5SEL_0) #define LL_RCC_LPTIM5_CLKSOURCE_IC15 LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM5SEL, RCC_CCIPR12_LPTIM5SEL_Pos, RCC_CCIPR12_LPTIM5SEL_1) #define LL_RCC_LPTIM5_CLKSOURCE_LSE LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM5SEL, RCC_CCIPR12_LPTIM5SEL_Pos, RCC_CCIPR12_LPTIM5SEL_1 |\ @@ -869,13 +869,13 @@ typedef struct /** @defgroup RCC_LL_EC_OTGPHY_CLKSOURCE Peripheral OTGPHY clock source selection * @{ */ -#define LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2 LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY1SEL, RCC_CCIPR6_OTGPHY1SEL_Pos, 0U) +#define LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2 LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY1SEL, RCC_CCIPR6_OTGPHY1SEL_Pos, 0UL) #define LL_RCC_OTGPHY1_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY1SEL, RCC_CCIPR6_OTGPHY1SEL_Pos, RCC_CCIPR6_OTGPHY1SEL_0) #define LL_RCC_OTGPHY1_CLKSOURCE_IC15 LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY1SEL, RCC_CCIPR6_OTGPHY1SEL_Pos, RCC_CCIPR6_OTGPHY1SEL_1) #define LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2_OSC LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY1SEL, RCC_CCIPR6_OTGPHY1SEL_Pos, RCC_CCIPR6_OTGPHY1SEL_1 |\ RCC_CCIPR6_OTGPHY1SEL_0) -#define LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2 LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY2SEL, RCC_CCIPR6_OTGPHY2SEL_Pos, 0U) +#define LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2 LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY2SEL, RCC_CCIPR6_OTGPHY2SEL_Pos, 0UL) #define LL_RCC_OTGPHY2_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY2SEL, RCC_CCIPR6_OTGPHY2SEL_Pos, RCC_CCIPR6_OTGPHY2SEL_0) #define LL_RCC_OTGPHY2_CLKSOURCE_IC15 LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY2SEL, RCC_CCIPR6_OTGPHY2SEL_Pos, RCC_CCIPR6_OTGPHY2SEL_1) #define LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2_OSC LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY2SEL, RCC_CCIPR6_OTGPHY2SEL_Pos, RCC_CCIPR6_OTGPHY2SEL_1 |\ @@ -887,10 +887,10 @@ typedef struct /** @defgroup RCC_LL_EC_OTGPHYCKREF_CLKSOURCE Peripheral OTGPHYCKREF clock source selection * @{ */ -#define LL_RCC_OTGPHY1CKREF_CLKSOURCE_OTGPHY1 LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY1CKREFSEL, RCC_CCIPR6_OTGPHY1CKREFSEL_Pos, 0U) +#define LL_RCC_OTGPHY1CKREF_CLKSOURCE_OTGPHY1 LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY1CKREFSEL, RCC_CCIPR6_OTGPHY1CKREFSEL_Pos, 0UL) #define LL_RCC_OTGPHY1CKREF_CLKSOURCE_HSE_DIV_2_OSC LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY1CKREFSEL, RCC_CCIPR6_OTGPHY1CKREFSEL_Pos, RCC_CCIPR6_OTGPHY1CKREFSEL) -#define LL_RCC_OTGPHY2CKREF_CLKSOURCE_OTGPHY2 LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY2CKREFSEL, RCC_CCIPR6_OTGPHY2CKREFSEL_Pos, 0U) +#define LL_RCC_OTGPHY2CKREF_CLKSOURCE_OTGPHY2 LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY2CKREFSEL, RCC_CCIPR6_OTGPHY2CKREFSEL_Pos, 0UL) #define LL_RCC_OTGPHY2CKREF_CLKSOURCE_HSE_DIV_2_OSC LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY2CKREFSEL, RCC_CCIPR6_OTGPHY2CKREFSEL_Pos, RCC_CCIPR6_OTGPHY2CKREFSEL) /** * @} @@ -921,7 +921,7 @@ typedef struct /** @defgroup RCC_LL_EC_SAI_CLKSOURCE Peripheral SAI clock source selection * @{ */ -#define LL_RCC_SAI1_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI1SEL, RCC_CCIPR7_SAI1SEL_Pos, 0U) +#define LL_RCC_SAI1_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI1SEL, RCC_CCIPR7_SAI1SEL_Pos, 0UL) #define LL_RCC_SAI1_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI1SEL, RCC_CCIPR7_SAI1SEL_Pos, RCC_CCIPR7_SAI1SEL_0) #define LL_RCC_SAI1_CLKSOURCE_IC7 LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI1SEL, RCC_CCIPR7_SAI1SEL_Pos, RCC_CCIPR7_SAI1SEL_1) #define LL_RCC_SAI1_CLKSOURCE_IC8 LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI1SEL, RCC_CCIPR7_SAI1SEL_Pos, RCC_CCIPR7_SAI1SEL_1 |\ @@ -934,7 +934,7 @@ typedef struct #define LL_RCC_SAI1_CLKSOURCE_SPDIFRX1 LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI1SEL, RCC_CCIPR7_SAI1SEL_Pos, RCC_CCIPR7_SAI1SEL_2 |\ RCC_CCIPR7_SAI1SEL_1 | RCC_CCIPR7_SAI1SEL_0) -#define LL_RCC_SAI2_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI2SEL, RCC_CCIPR7_SAI2SEL_Pos, 0U) +#define LL_RCC_SAI2_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI2SEL, RCC_CCIPR7_SAI2SEL_Pos, 0UL) #define LL_RCC_SAI2_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI2SEL, RCC_CCIPR7_SAI2SEL_Pos, RCC_CCIPR7_SAI2SEL_0) #define LL_RCC_SAI2_CLKSOURCE_IC7 LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI2SEL, RCC_CCIPR7_SAI2SEL_Pos, RCC_CCIPR7_SAI2SEL_1) #define LL_RCC_SAI2_CLKSOURCE_IC8 LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI2SEL, RCC_CCIPR7_SAI2SEL_Pos, RCC_CCIPR7_SAI2SEL_1 |\ @@ -953,13 +953,13 @@ typedef struct /** @defgroup RCC_LL_EC_SDMMC_CLKSOURCE Peripheral SDMMC clock source selection * @{ */ -#define LL_RCC_SDMMC1_CLKSOURCE_HCLK LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC1SEL, RCC_CCIPR8_SDMMC1SEL_Pos, 0U) +#define LL_RCC_SDMMC1_CLKSOURCE_HCLK LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC1SEL, RCC_CCIPR8_SDMMC1SEL_Pos, 0UL) #define LL_RCC_SDMMC1_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC1SEL, RCC_CCIPR8_SDMMC1SEL_Pos, RCC_CCIPR8_SDMMC1SEL_0) #define LL_RCC_SDMMC1_CLKSOURCE_IC4 LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC1SEL, RCC_CCIPR8_SDMMC1SEL_Pos, RCC_CCIPR8_SDMMC1SEL_1) #define LL_RCC_SDMMC1_CLKSOURCE_IC5 LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC1SEL, RCC_CCIPR8_SDMMC1SEL_Pos, RCC_CCIPR8_SDMMC1SEL_1 |\ RCC_CCIPR8_SDMMC1SEL_0) -#define LL_RCC_SDMMC2_CLKSOURCE_HCLK LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC2SEL, RCC_CCIPR8_SDMMC2SEL_Pos, 0U) +#define LL_RCC_SDMMC2_CLKSOURCE_HCLK LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC2SEL, RCC_CCIPR8_SDMMC2SEL_Pos, 0UL) #define LL_RCC_SDMMC2_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC2SEL, RCC_CCIPR8_SDMMC2SEL_Pos, RCC_CCIPR8_SDMMC2SEL_0) #define LL_RCC_SDMMC2_CLKSOURCE_IC4 LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC2SEL, RCC_CCIPR8_SDMMC2SEL_Pos, RCC_CCIPR8_SDMMC2SEL_1) #define LL_RCC_SDMMC2_CLKSOURCE_IC5 LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC2SEL, RCC_CCIPR8_SDMMC2SEL_Pos, RCC_CCIPR8_SDMMC2SEL_1 |\ @@ -985,7 +985,7 @@ typedef struct /** @defgroup RCC_LL_EC_SPI_CLKSOURCE Peripheral SPI clock source selection * @{ */ -#define LL_RCC_SPI1_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI1SEL, RCC_CCIPR9_SPI1SEL_Pos, 0U) +#define LL_RCC_SPI1_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI1SEL, RCC_CCIPR9_SPI1SEL_Pos, 0UL) #define LL_RCC_SPI1_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI1SEL, RCC_CCIPR9_SPI1SEL_Pos, RCC_CCIPR9_SPI1SEL_0) #define LL_RCC_SPI1_CLKSOURCE_IC8 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI1SEL, RCC_CCIPR9_SPI1SEL_Pos, RCC_CCIPR9_SPI1SEL_1) #define LL_RCC_SPI1_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI1SEL, RCC_CCIPR9_SPI1SEL_Pos, RCC_CCIPR9_SPI1SEL_1 |\ @@ -996,7 +996,7 @@ typedef struct #define LL_RCC_SPI1_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI1SEL, RCC_CCIPR9_SPI1SEL_Pos, RCC_CCIPR9_SPI1SEL_2 |\ RCC_CCIPR9_SPI1SEL_1) -#define LL_RCC_SPI2_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI2SEL, RCC_CCIPR9_SPI2SEL_Pos, 0U) +#define LL_RCC_SPI2_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI2SEL, RCC_CCIPR9_SPI2SEL_Pos, 0UL) #define LL_RCC_SPI2_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI2SEL, RCC_CCIPR9_SPI2SEL_Pos, RCC_CCIPR9_SPI2SEL_0) #define LL_RCC_SPI2_CLKSOURCE_IC8 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI2SEL, RCC_CCIPR9_SPI2SEL_Pos, RCC_CCIPR9_SPI2SEL_1) #define LL_RCC_SPI2_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI2SEL, RCC_CCIPR9_SPI2SEL_Pos, RCC_CCIPR9_SPI2SEL_1 |\ @@ -1007,7 +1007,7 @@ typedef struct #define LL_RCC_SPI2_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI2SEL, RCC_CCIPR9_SPI2SEL_Pos, RCC_CCIPR9_SPI2SEL_2 |\ RCC_CCIPR9_SPI2SEL_1) -#define LL_RCC_SPI3_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI3SEL, RCC_CCIPR9_SPI3SEL_Pos, 0U) +#define LL_RCC_SPI3_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI3SEL, RCC_CCIPR9_SPI3SEL_Pos, 0UL) #define LL_RCC_SPI3_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI3SEL, RCC_CCIPR9_SPI3SEL_Pos, RCC_CCIPR9_SPI3SEL_0) #define LL_RCC_SPI3_CLKSOURCE_IC8 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI3SEL, RCC_CCIPR9_SPI3SEL_Pos, RCC_CCIPR9_SPI3SEL_1) #define LL_RCC_SPI3_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI3SEL, RCC_CCIPR9_SPI3SEL_Pos, RCC_CCIPR9_SPI3SEL_1 |\ @@ -1018,7 +1018,7 @@ typedef struct #define LL_RCC_SPI3_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI3SEL, RCC_CCIPR9_SPI3SEL_Pos, RCC_CCIPR9_SPI3SEL_2 |\ RCC_CCIPR9_SPI3SEL_1) -#define LL_RCC_SPI4_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI4SEL, RCC_CCIPR9_SPI4SEL_Pos, 0U) +#define LL_RCC_SPI4_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI4SEL, RCC_CCIPR9_SPI4SEL_Pos, 0UL) #define LL_RCC_SPI4_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI4SEL, RCC_CCIPR9_SPI4SEL_Pos, RCC_CCIPR9_SPI4SEL_0) #define LL_RCC_SPI4_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI4SEL, RCC_CCIPR9_SPI4SEL_Pos, RCC_CCIPR9_SPI4SEL_1) #define LL_RCC_SPI4_CLKSOURCE_IC14 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI4SEL, RCC_CCIPR9_SPI4SEL_Pos, RCC_CCIPR9_SPI4SEL_1 |\ @@ -1029,7 +1029,7 @@ typedef struct #define LL_RCC_SPI4_CLKSOURCE_HSE LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI4SEL, RCC_CCIPR9_SPI4SEL_Pos, RCC_CCIPR9_SPI4SEL_2 |\ RCC_CCIPR9_SPI4SEL_1) -#define LL_RCC_SPI5_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI5SEL, RCC_CCIPR9_SPI5SEL_Pos, 0U) +#define LL_RCC_SPI5_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI5SEL, RCC_CCIPR9_SPI5SEL_Pos, 0UL) #define LL_RCC_SPI5_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI5SEL, RCC_CCIPR9_SPI5SEL_Pos, RCC_CCIPR9_SPI5SEL_0) #define LL_RCC_SPI5_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI5SEL, RCC_CCIPR9_SPI5SEL_Pos, RCC_CCIPR9_SPI5SEL_1) #define LL_RCC_SPI5_CLKSOURCE_IC14 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI5SEL, RCC_CCIPR9_SPI5SEL_Pos, RCC_CCIPR9_SPI5SEL_1 |\ @@ -1040,7 +1040,7 @@ typedef struct #define LL_RCC_SPI5_CLKSOURCE_HSE LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI5SEL, RCC_CCIPR9_SPI5SEL_Pos, RCC_CCIPR9_SPI5SEL_2 |\ RCC_CCIPR9_SPI5SEL_1) -#define LL_RCC_SPI6_CLKSOURCE_PCLK4 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI6SEL, RCC_CCIPR9_SPI6SEL_Pos, 0U) +#define LL_RCC_SPI6_CLKSOURCE_PCLK4 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI6SEL, RCC_CCIPR9_SPI6SEL_Pos, 0UL) #define LL_RCC_SPI6_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI6SEL, RCC_CCIPR9_SPI6SEL_Pos, RCC_CCIPR9_SPI6SEL_0) #define LL_RCC_SPI6_CLKSOURCE_IC8 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI6SEL, RCC_CCIPR9_SPI6SEL_Pos, RCC_CCIPR9_SPI6SEL_1) #define LL_RCC_SPI6_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI6SEL, RCC_CCIPR9_SPI6SEL_Pos, RCC_CCIPR9_SPI6SEL_1 |\ @@ -1057,7 +1057,7 @@ typedef struct /** @defgroup RCC_LL_EC_UART_CLKSOURCE Peripheral UART clock source selection * @{ */ -#define LL_RCC_UART4_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART4SEL, RCC_CCIPR13_UART4SEL_Pos, 0U) +#define LL_RCC_UART4_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART4SEL, RCC_CCIPR13_UART4SEL_Pos, 0UL) #define LL_RCC_UART4_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART4SEL, RCC_CCIPR13_UART4SEL_Pos, RCC_CCIPR13_UART4SEL_0) #define LL_RCC_UART4_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART4SEL, RCC_CCIPR13_UART4SEL_Pos, RCC_CCIPR13_UART4SEL_1) #define LL_RCC_UART4_CLKSOURCE_IC14 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART4SEL, RCC_CCIPR13_UART4SEL_Pos, RCC_CCIPR13_UART4SEL_1 |\ @@ -1068,7 +1068,7 @@ typedef struct #define LL_RCC_UART4_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART4SEL, RCC_CCIPR13_UART4SEL_Pos, RCC_CCIPR13_UART4SEL_2 |\ RCC_CCIPR13_UART4SEL_1) -#define LL_RCC_UART5_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART5SEL, RCC_CCIPR13_UART5SEL_Pos, 0U) +#define LL_RCC_UART5_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART5SEL, RCC_CCIPR13_UART5SEL_Pos, 0UL) #define LL_RCC_UART5_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART5SEL, RCC_CCIPR13_UART5SEL_Pos, RCC_CCIPR13_UART5SEL_0) #define LL_RCC_UART5_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART5SEL, RCC_CCIPR13_UART5SEL_Pos, RCC_CCIPR13_UART5SEL_1) #define LL_RCC_UART5_CLKSOURCE_IC14 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART5SEL, RCC_CCIPR13_UART5SEL_Pos, RCC_CCIPR13_UART5SEL_1 |\ @@ -1079,7 +1079,7 @@ typedef struct #define LL_RCC_UART5_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART5SEL, RCC_CCIPR13_UART5SEL_Pos, RCC_CCIPR13_UART5SEL_2 |\ RCC_CCIPR13_UART5SEL_1) -#define LL_RCC_UART7_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART7SEL, RCC_CCIPR13_UART7SEL_Pos, 0U) +#define LL_RCC_UART7_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART7SEL, RCC_CCIPR13_UART7SEL_Pos, 0UL) #define LL_RCC_UART7_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART7SEL, RCC_CCIPR13_UART7SEL_Pos, RCC_CCIPR13_UART7SEL_0) #define LL_RCC_UART7_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART7SEL, RCC_CCIPR13_UART7SEL_Pos, RCC_CCIPR13_UART7SEL_1) #define LL_RCC_UART7_CLKSOURCE_IC14 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART7SEL, RCC_CCIPR13_UART7SEL_Pos, RCC_CCIPR13_UART7SEL_1 |\ @@ -1090,7 +1090,7 @@ typedef struct #define LL_RCC_UART7_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART7SEL, RCC_CCIPR13_UART7SEL_Pos, RCC_CCIPR13_UART7SEL_2 |\ RCC_CCIPR13_UART7SEL_1) -#define LL_RCC_UART8_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART8SEL, RCC_CCIPR13_UART8SEL_Pos, 0U) +#define LL_RCC_UART8_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART8SEL, RCC_CCIPR13_UART8SEL_Pos, 0UL) #define LL_RCC_UART8_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART8SEL, RCC_CCIPR13_UART8SEL_Pos, RCC_CCIPR13_UART8SEL_0) #define LL_RCC_UART8_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART8SEL, RCC_CCIPR13_UART8SEL_Pos, RCC_CCIPR13_UART8SEL_1) #define LL_RCC_UART8_CLKSOURCE_IC14 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART8SEL, RCC_CCIPR13_UART8SEL_Pos, RCC_CCIPR13_UART8SEL_1 |\ @@ -1101,7 +1101,7 @@ typedef struct #define LL_RCC_UART8_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART8SEL, RCC_CCIPR13_UART8SEL_Pos, RCC_CCIPR13_UART8SEL_2 |\ RCC_CCIPR13_UART8SEL_1) -#define LL_RCC_UART9_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_UART9SEL, RCC_CCIPR14_UART9SEL_Pos, 0U) +#define LL_RCC_UART9_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_UART9SEL, RCC_CCIPR14_UART9SEL_Pos, 0UL) #define LL_RCC_UART9_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_UART9SEL, RCC_CCIPR14_UART9SEL_Pos, RCC_CCIPR14_UART9SEL_0) #define LL_RCC_UART9_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_UART9SEL, RCC_CCIPR14_UART9SEL_Pos, RCC_CCIPR14_UART9SEL_1) #define LL_RCC_UART9_CLKSOURCE_IC14 LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_UART9SEL, RCC_CCIPR14_UART9SEL_Pos, RCC_CCIPR14_UART9SEL_1 |\ @@ -1118,7 +1118,7 @@ typedef struct /** @defgroup RCC_LL_EC_USART_CLKSOURCE Peripheral USART clock source selection * @{ */ -#define LL_RCC_USART1_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART1SEL, RCC_CCIPR13_USART1SEL_Pos, 0U) +#define LL_RCC_USART1_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART1SEL, RCC_CCIPR13_USART1SEL_Pos, 0UL) #define LL_RCC_USART1_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART1SEL, RCC_CCIPR13_USART1SEL_Pos, RCC_CCIPR13_USART1SEL_0) #define LL_RCC_USART1_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART1SEL, RCC_CCIPR13_USART1SEL_Pos, RCC_CCIPR13_USART1SEL_1) #define LL_RCC_USART1_CLKSOURCE_IC14 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART1SEL, RCC_CCIPR13_USART1SEL_Pos, RCC_CCIPR13_USART1SEL_1 |\ @@ -1129,7 +1129,7 @@ typedef struct #define LL_RCC_USART1_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART1SEL, RCC_CCIPR13_USART1SEL_Pos, RCC_CCIPR13_USART1SEL_2 |\ RCC_CCIPR13_USART1SEL_1) -#define LL_RCC_USART2_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART2SEL, RCC_CCIPR13_USART2SEL_Pos, 0U) +#define LL_RCC_USART2_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART2SEL, RCC_CCIPR13_USART2SEL_Pos, 0UL) #define LL_RCC_USART2_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART2SEL, RCC_CCIPR13_USART2SEL_Pos, RCC_CCIPR13_USART2SEL_0) #define LL_RCC_USART2_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART2SEL, RCC_CCIPR13_USART2SEL_Pos, RCC_CCIPR13_USART2SEL_1) #define LL_RCC_USART2_CLKSOURCE_IC14 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART2SEL, RCC_CCIPR13_USART2SEL_Pos, RCC_CCIPR13_USART2SEL_1 |\ @@ -1140,7 +1140,7 @@ typedef struct #define LL_RCC_USART2_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART2SEL, RCC_CCIPR13_USART2SEL_Pos, RCC_CCIPR13_USART2SEL_2 |\ RCC_CCIPR13_USART2SEL_1) -#define LL_RCC_USART3_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART3SEL, RCC_CCIPR13_USART3SEL_Pos, 0U) +#define LL_RCC_USART3_CLKSOURCE_PCLK1 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART3SEL, RCC_CCIPR13_USART3SEL_Pos, 0UL) #define LL_RCC_USART3_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART3SEL, RCC_CCIPR13_USART3SEL_Pos, RCC_CCIPR13_USART3SEL_0) #define LL_RCC_USART3_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART3SEL, RCC_CCIPR13_USART3SEL_Pos, RCC_CCIPR13_USART3SEL_1) #define LL_RCC_USART3_CLKSOURCE_IC14 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART3SEL, RCC_CCIPR13_USART3SEL_Pos, RCC_CCIPR13_USART3SEL_1 |\ @@ -1151,7 +1151,7 @@ typedef struct #define LL_RCC_USART3_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART3SEL, RCC_CCIPR13_USART3SEL_Pos, RCC_CCIPR13_USART3SEL_2 |\ RCC_CCIPR13_USART3SEL_1) -#define LL_RCC_USART6_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART6SEL, RCC_CCIPR13_USART6SEL_Pos, 0U) +#define LL_RCC_USART6_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART6SEL, RCC_CCIPR13_USART6SEL_Pos, 0UL) #define LL_RCC_USART6_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART6SEL, RCC_CCIPR13_USART6SEL_Pos, RCC_CCIPR13_USART6SEL_0) #define LL_RCC_USART6_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART6SEL, RCC_CCIPR13_USART6SEL_Pos, RCC_CCIPR13_USART6SEL_1) #define LL_RCC_USART6_CLKSOURCE_IC14 LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART6SEL, RCC_CCIPR13_USART6SEL_Pos, RCC_CCIPR13_USART6SEL_1 |\ @@ -1162,7 +1162,7 @@ typedef struct #define LL_RCC_USART6_CLKSOURCE_HSI LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART6SEL, RCC_CCIPR13_USART6SEL_Pos, RCC_CCIPR13_USART6SEL_2 |\ RCC_CCIPR13_USART6SEL_1) -#define LL_RCC_USART10_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_USART10SEL, RCC_CCIPR14_USART10SEL_Pos, 0U) +#define LL_RCC_USART10_CLKSOURCE_PCLK2 LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_USART10SEL, RCC_CCIPR14_USART10SEL_Pos, 0UL) #define LL_RCC_USART10_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_USART10SEL, RCC_CCIPR14_USART10SEL_Pos, RCC_CCIPR14_USART10SEL_0) #define LL_RCC_USART10_CLKSOURCE_IC9 LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_USART10SEL, RCC_CCIPR14_USART10SEL_Pos, RCC_CCIPR14_USART10SEL_1) #define LL_RCC_USART10_CLKSOURCE_IC14 LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_USART10SEL, RCC_CCIPR14_USART10SEL_Pos, RCC_CCIPR14_USART10SEL_1 |\ @@ -1179,19 +1179,19 @@ typedef struct /** @defgroup RCC_LL_EC_XSPI_CLKSOURCE Peripheral XSPI clock source selection * @{ */ -#define LL_RCC_XSPI1_CLKSOURCE_HCLK LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI1SEL, RCC_CCIPR6_XSPI1SEL_Pos, 0U) +#define LL_RCC_XSPI1_CLKSOURCE_HCLK LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI1SEL, RCC_CCIPR6_XSPI1SEL_Pos, 0UL) #define LL_RCC_XSPI1_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI1SEL, RCC_CCIPR6_XSPI1SEL_Pos, RCC_CCIPR6_XSPI1SEL_0) #define LL_RCC_XSPI1_CLKSOURCE_IC3 LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI1SEL, RCC_CCIPR6_XSPI1SEL_Pos, RCC_CCIPR6_XSPI1SEL_1) #define LL_RCC_XSPI1_CLKSOURCE_IC4 LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI1SEL, RCC_CCIPR6_XSPI1SEL_Pos, RCC_CCIPR6_XSPI1SEL_1 |\ RCC_CCIPR6_XSPI1SEL_0) -#define LL_RCC_XSPI2_CLKSOURCE_HCLK LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI2SEL, RCC_CCIPR6_XSPI2SEL_Pos, 0U) +#define LL_RCC_XSPI2_CLKSOURCE_HCLK LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI2SEL, RCC_CCIPR6_XSPI2SEL_Pos, 0UL) #define LL_RCC_XSPI2_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI2SEL, RCC_CCIPR6_XSPI2SEL_Pos, RCC_CCIPR6_XSPI2SEL_0) #define LL_RCC_XSPI2_CLKSOURCE_IC3 LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI2SEL, RCC_CCIPR6_XSPI2SEL_Pos, RCC_CCIPR6_XSPI2SEL_1) #define LL_RCC_XSPI2_CLKSOURCE_IC4 LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI2SEL, RCC_CCIPR6_XSPI2SEL_Pos, RCC_CCIPR6_XSPI2SEL_1 |\ RCC_CCIPR6_XSPI2SEL_0) -#define LL_RCC_XSPI3_CLKSOURCE_HCLK LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI3SEL, RCC_CCIPR6_XSPI3SEL_Pos, 0U) +#define LL_RCC_XSPI3_CLKSOURCE_HCLK LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI3SEL, RCC_CCIPR6_XSPI3SEL_Pos, 0UL) #define LL_RCC_XSPI3_CLKSOURCE_CLKP LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI3SEL, RCC_CCIPR6_XSPI3SEL_Pos, RCC_CCIPR6_XSPI3SEL_0) #define LL_RCC_XSPI3_CLKSOURCE_IC3 LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI3SEL, RCC_CCIPR6_XSPI3SEL_Pos, RCC_CCIPR6_XSPI3SEL_1) #define LL_RCC_XSPI3_CLKSOURCE_IC4 LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI3SEL, RCC_CCIPR6_XSPI3SEL_Pos, RCC_CCIPR6_XSPI3SEL_1 |\ @@ -1291,10 +1291,10 @@ typedef struct /** @defgroup RCC_LL_EC_I2C Peripheral I2C get clock source * @{ */ -#define LL_RCC_I2C1_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C1SEL, RCC_CCIPR4_I2C1SEL_Pos, 0U) -#define LL_RCC_I2C2_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C2SEL, RCC_CCIPR4_I2C2SEL_Pos, 0U) -#define LL_RCC_I2C3_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos, 0U) -#define LL_RCC_I2C4_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C4SEL, RCC_CCIPR4_I2C4SEL_Pos, 0U) +#define LL_RCC_I2C1_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C1SEL, RCC_CCIPR4_I2C1SEL_Pos, 0UL) +#define LL_RCC_I2C2_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C2SEL, RCC_CCIPR4_I2C2SEL_Pos, 0UL) +#define LL_RCC_I2C3_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C3SEL, RCC_CCIPR4_I2C3SEL_Pos, 0UL) +#define LL_RCC_I2C4_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I2C4SEL, RCC_CCIPR4_I2C4SEL_Pos, 0UL) /** * @} */ @@ -1302,8 +1302,8 @@ typedef struct /** @defgroup RCC_LL_EC_I3C Peripheral I3C get clock source * @{ */ -#define LL_RCC_I3C1_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos, 0U) -#define LL_RCC_I3C2_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos, 0U) +#define LL_RCC_I3C1_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C1SEL, RCC_CCIPR4_I3C1SEL_Pos, 0UL) +#define LL_RCC_I3C2_CLKSOURCE LL_CLKSOURCE(CCIPR4_OFFSET, RCC_CCIPR4_I3C2SEL, RCC_CCIPR4_I3C2SEL_Pos, 0UL) /** * @} */ @@ -1311,11 +1311,11 @@ typedef struct /** @defgroup RCC_LL_EC_LPTIM Peripheral LPTIM get clock source * @{ */ -#define LL_RCC_LPTIM1_CLKSOURCE LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM1SEL, RCC_CCIPR12_LPTIM1SEL_Pos, 0U) -#define LL_RCC_LPTIM2_CLKSOURCE LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM2SEL, RCC_CCIPR12_LPTIM2SEL_Pos, 0U) -#define LL_RCC_LPTIM3_CLKSOURCE LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM3SEL, RCC_CCIPR12_LPTIM3SEL_Pos, 0U) -#define LL_RCC_LPTIM4_CLKSOURCE LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM4SEL, RCC_CCIPR12_LPTIM4SEL_Pos, 0U) -#define LL_RCC_LPTIM5_CLKSOURCE LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM5SEL, RCC_CCIPR12_LPTIM5SEL_Pos, 0U) +#define LL_RCC_LPTIM1_CLKSOURCE LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM1SEL, RCC_CCIPR12_LPTIM1SEL_Pos, 0UL) +#define LL_RCC_LPTIM2_CLKSOURCE LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM2SEL, RCC_CCIPR12_LPTIM2SEL_Pos, 0UL) +#define LL_RCC_LPTIM3_CLKSOURCE LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM3SEL, RCC_CCIPR12_LPTIM3SEL_Pos, 0UL) +#define LL_RCC_LPTIM4_CLKSOURCE LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM4SEL, RCC_CCIPR12_LPTIM4SEL_Pos, 0UL) +#define LL_RCC_LPTIM5_CLKSOURCE LL_CLKSOURCE(CCIPR12_OFFSET, RCC_CCIPR12_LPTIM5SEL, RCC_CCIPR12_LPTIM5SEL_Pos, 0UL) /** * @} */ @@ -1347,8 +1347,8 @@ typedef struct /** @defgroup RCC_LL_EC_OTGPHY Peripheral OTGPHY get clock source * @{ */ -#define LL_RCC_OTGPHY1_CLKSOURCE LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY1SEL, RCC_CCIPR6_OTGPHY1SEL_Pos, 0U) -#define LL_RCC_OTGPHY2_CLKSOURCE LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY2SEL, RCC_CCIPR6_OTGPHY2SEL_Pos, 0U) +#define LL_RCC_OTGPHY1_CLKSOURCE LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY1SEL, RCC_CCIPR6_OTGPHY1SEL_Pos, 0UL) +#define LL_RCC_OTGPHY2_CLKSOURCE LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY2SEL, RCC_CCIPR6_OTGPHY2SEL_Pos, 0UL) /** * @} */ @@ -1356,8 +1356,8 @@ typedef struct /** @defgroup RCC_LL_EC_OTGPHYCKREF Peripheral OTGPHYCKREF get clock source * @{ */ -#define LL_RCC_OTGPHY1CKREF_CLKSOURCE LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY1CKREFSEL, RCC_CCIPR6_OTGPHY1CKREFSEL_Pos, 0U) -#define LL_RCC_OTGPHY2CKREF_CLKSOURCE LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY2CKREFSEL, RCC_CCIPR6_OTGPHY2CKREFSEL_Pos, 0U) +#define LL_RCC_OTGPHY1CKREF_CLKSOURCE LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY1CKREFSEL, RCC_CCIPR6_OTGPHY1CKREFSEL_Pos, 0UL) +#define LL_RCC_OTGPHY2CKREF_CLKSOURCE LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_OTGPHY2CKREFSEL, RCC_CCIPR6_OTGPHY2CKREFSEL_Pos, 0UL) /** * @} */ @@ -1373,8 +1373,8 @@ typedef struct /** @defgroup RCC_LL_EC_SAI Peripheral SAI get clock source * @{ */ -#define LL_RCC_SAI1_CLKSOURCE LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI1SEL, RCC_CCIPR7_SAI1SEL_Pos, 0U) -#define LL_RCC_SAI2_CLKSOURCE LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI2SEL, RCC_CCIPR7_SAI2SEL_Pos, 0U) +#define LL_RCC_SAI1_CLKSOURCE LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI1SEL, RCC_CCIPR7_SAI1SEL_Pos, 0UL) +#define LL_RCC_SAI2_CLKSOURCE LL_CLKSOURCE(CCIPR7_OFFSET, RCC_CCIPR7_SAI2SEL, RCC_CCIPR7_SAI2SEL_Pos, 0UL) /** * @} */ @@ -1382,8 +1382,8 @@ typedef struct /** @defgroup RCC_LL_EC_SDMMC Peripheral SDMMC get clock source * @{ */ -#define LL_RCC_SDMMC1_CLKSOURCE LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC1SEL, RCC_CCIPR8_SDMMC1SEL_Pos, 0U) -#define LL_RCC_SDMMC2_CLKSOURCE LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC2SEL, RCC_CCIPR8_SDMMC2SEL_Pos, 0U) +#define LL_RCC_SDMMC1_CLKSOURCE LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC1SEL, RCC_CCIPR8_SDMMC1SEL_Pos, 0UL) +#define LL_RCC_SDMMC2_CLKSOURCE LL_CLKSOURCE(CCIPR8_OFFSET, RCC_CCIPR8_SDMMC2SEL, RCC_CCIPR8_SDMMC2SEL_Pos, 0UL) /** * @} */ @@ -1399,12 +1399,12 @@ typedef struct /** @defgroup RCC_LL_EC_SPI Peripheral SPI get clock source * @{ */ -#define LL_RCC_SPI1_CLKSOURCE LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI1SEL, RCC_CCIPR9_SPI1SEL_Pos, 0U) -#define LL_RCC_SPI2_CLKSOURCE LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI2SEL, RCC_CCIPR9_SPI2SEL_Pos, 0U) -#define LL_RCC_SPI3_CLKSOURCE LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI3SEL, RCC_CCIPR9_SPI3SEL_Pos, 0U) -#define LL_RCC_SPI4_CLKSOURCE LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI4SEL, RCC_CCIPR9_SPI4SEL_Pos, 0U) -#define LL_RCC_SPI5_CLKSOURCE LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI5SEL, RCC_CCIPR9_SPI5SEL_Pos, 0U) -#define LL_RCC_SPI6_CLKSOURCE LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI6SEL, RCC_CCIPR9_SPI6SEL_Pos, 0U) +#define LL_RCC_SPI1_CLKSOURCE LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI1SEL, RCC_CCIPR9_SPI1SEL_Pos, 0UL) +#define LL_RCC_SPI2_CLKSOURCE LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI2SEL, RCC_CCIPR9_SPI2SEL_Pos, 0UL) +#define LL_RCC_SPI3_CLKSOURCE LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI3SEL, RCC_CCIPR9_SPI3SEL_Pos, 0UL) +#define LL_RCC_SPI4_CLKSOURCE LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI4SEL, RCC_CCIPR9_SPI4SEL_Pos, 0UL) +#define LL_RCC_SPI5_CLKSOURCE LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI5SEL, RCC_CCIPR9_SPI5SEL_Pos, 0UL) +#define LL_RCC_SPI6_CLKSOURCE LL_CLKSOURCE(CCIPR9_OFFSET, RCC_CCIPR9_SPI6SEL, RCC_CCIPR9_SPI6SEL_Pos, 0UL) /** * @} */ @@ -1412,11 +1412,11 @@ typedef struct /** @defgroup RCC_LL_EC_UART Peripheral UART get clock source * @{ */ -#define LL_RCC_UART4_CLKSOURCE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART4SEL, RCC_CCIPR13_UART4SEL_Pos, 0U) -#define LL_RCC_UART5_CLKSOURCE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART5SEL, RCC_CCIPR13_UART5SEL_Pos, 0U) -#define LL_RCC_UART7_CLKSOURCE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART7SEL, RCC_CCIPR13_UART7SEL_Pos, 0U) -#define LL_RCC_UART8_CLKSOURCE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART8SEL, RCC_CCIPR13_UART8SEL_Pos, 0U) -#define LL_RCC_UART9_CLKSOURCE LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_UART9SEL, RCC_CCIPR14_UART9SEL_Pos, 0U) +#define LL_RCC_UART4_CLKSOURCE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART4SEL, RCC_CCIPR13_UART4SEL_Pos, 0UL) +#define LL_RCC_UART5_CLKSOURCE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART5SEL, RCC_CCIPR13_UART5SEL_Pos, 0UL) +#define LL_RCC_UART7_CLKSOURCE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART7SEL, RCC_CCIPR13_UART7SEL_Pos, 0UL) +#define LL_RCC_UART8_CLKSOURCE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_UART8SEL, RCC_CCIPR13_UART8SEL_Pos, 0UL) +#define LL_RCC_UART9_CLKSOURCE LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_UART9SEL, RCC_CCIPR14_UART9SEL_Pos, 0UL) /** * @} */ @@ -1424,11 +1424,11 @@ typedef struct /** @defgroup RCC_LL_EC_USART Peripheral USART get clock source * @{ */ -#define LL_RCC_USART1_CLKSOURCE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART1SEL, RCC_CCIPR13_USART1SEL_Pos, 0U) -#define LL_RCC_USART2_CLKSOURCE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART2SEL, RCC_CCIPR13_USART2SEL_Pos, 0U) -#define LL_RCC_USART3_CLKSOURCE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART3SEL, RCC_CCIPR13_USART3SEL_Pos, 0U) -#define LL_RCC_USART6_CLKSOURCE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART6SEL, RCC_CCIPR13_USART6SEL_Pos, 0U) -#define LL_RCC_USART10_CLKSOURCE LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_USART10SEL, RCC_CCIPR14_USART10SEL_Pos, 0U) +#define LL_RCC_USART1_CLKSOURCE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART1SEL, RCC_CCIPR13_USART1SEL_Pos, 0UL) +#define LL_RCC_USART2_CLKSOURCE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART2SEL, RCC_CCIPR13_USART2SEL_Pos, 0UL) +#define LL_RCC_USART3_CLKSOURCE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART3SEL, RCC_CCIPR13_USART3SEL_Pos, 0UL) +#define LL_RCC_USART6_CLKSOURCE LL_CLKSOURCE(CCIPR13_OFFSET, RCC_CCIPR13_USART6SEL, RCC_CCIPR13_USART6SEL_Pos, 0UL) +#define LL_RCC_USART10_CLKSOURCE LL_CLKSOURCE(CCIPR14_OFFSET, RCC_CCIPR14_USART10SEL, RCC_CCIPR14_USART10SEL_Pos, 0UL) /** * @} */ @@ -1436,9 +1436,9 @@ typedef struct /** @defgroup RCC_LL_EC_XSPI Peripheral XSPI get clock source * @{ */ -#define LL_RCC_XSPI1_CLKSOURCE LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI1SEL, RCC_CCIPR6_XSPI1SEL_Pos, 0U) -#define LL_RCC_XSPI2_CLKSOURCE LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI2SEL, RCC_CCIPR6_XSPI2SEL_Pos, 0U) -#define LL_RCC_XSPI3_CLKSOURCE LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI3SEL, RCC_CCIPR6_XSPI3SEL_Pos, 0U) +#define LL_RCC_XSPI1_CLKSOURCE LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI1SEL, RCC_CCIPR6_XSPI1SEL_Pos, 0UL) +#define LL_RCC_XSPI2_CLKSOURCE LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI2SEL, RCC_CCIPR6_XSPI2SEL_Pos, 0UL) +#define LL_RCC_XSPI3_CLKSOURCE LL_CLKSOURCE(CCIPR6_OFFSET, RCC_CCIPR6_XSPI3SEL, RCC_CCIPR6_XSPI3SEL_Pos, 0UL) /** * @} */ @@ -1596,6 +1596,18 @@ typedef struct #define LL_RCC_CALC_PCLK5_FREQ(__HCLKFREQ__, __APB5PRESCALER__) ((__HCLKFREQ__) >> (((__APB5PRESCALER__) &\ RCC_CFGR2_PPRE5) >> RCC_CFGR2_PPRE5_Pos)) +/** + * @brief Helper macro to calculate the TIMG frequency (timer group1 and group2) + * @param __SYSCLKFREQ__ SYSCLK frequency. + * @param __TIMPRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_TIM_PRESCALER_1 + * @arg @ref LL_RCC_TIM_PRESCALER_2 + * @arg @ref LL_RCC_TIM_PRESCALER_4 + * @arg @ref LL_RCC_TIM_PRESCALER_8 + * @retval TIMG clock frequency (in Hz) + */ +#define LL_RCC_CALC_TIMG_FREQ(__SYSCLKFREQ__, __TIMPRESCALER__) ((__SYSCLKFREQ__) >> (__TIMPRESCALER__)) + /** * @} */ diff --git a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_usart.h b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_usart.h index 055a1ec..87583d7 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_usart.h +++ b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_usart.h @@ -57,6 +57,10 @@ static const uint32_t USART_PRESCALER_TAB[] = 32UL, 64UL, 128UL, + 256UL, + 256UL, + 256UL, + 256UL, 256UL }; /** diff --git a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_usb.h b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_usb.h index d749337..a6f0f03 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_usb.h +++ b/Drivers/STM32N6xx_HAL_Driver/Inc/stm32n6xx_ll_usb.h @@ -56,6 +56,7 @@ typedef enum USB_DRD_MODE = 2 } USB_ModeTypeDef; +#if defined (HAL_HCD_MODULE_ENABLED) /** * @brief URB States definition */ @@ -66,7 +67,8 @@ typedef enum URB_NOTREADY, URB_NYET, URB_ERROR, - URB_STALL + URB_STALL, + URB_NAK_WAIT } USB_URBStateTypeDef; /** @@ -85,6 +87,7 @@ typedef enum HC_BBLERR, HC_DATATGLERR } USB_HCStateTypeDef; +#endif /* defined (HAL_HCD_MODULE_ENABLED) */ /** @@ -128,6 +131,7 @@ typedef struct } USB_CfgTypeDef; +#if defined (HAL_PCD_MODULE_ENABLED) typedef struct { uint8_t num; /*!< Endpoint number @@ -167,7 +171,9 @@ typedef struct uint32_t xfer_size; /*!< requested transfer size */ } USB_EPTypeDef; +#endif /* defined (HAL_PCD_MODULE_ENABLED) */ +#if defined (HAL_HCD_MODULE_ENABLED) typedef struct { uint8_t dev_addr; /*!< USB device address. @@ -182,6 +188,9 @@ typedef struct uint8_t ep_is_in; /*!< Endpoint direction This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + uint8_t ch_dir; /*!< channel direction + This parameter store the physical channel direction IN/OUT/BIDIR */ + uint8_t speed; /*!< USB Host Channel speed. This parameter can be any value of @ref HCD_Device_Speed: (HCD_DEVICE_SPEED_xxx) */ @@ -220,6 +229,8 @@ typedef struct uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */ + uint32_t NakCnt; /*!< Host channel NAK count. */ + uint32_t ErrCnt; /*!< Host channel error count. */ uint32_t NyetErrCnt; /*!< Complete Split NYET Host channel error count. */ @@ -229,13 +240,20 @@ typedef struct USB_HCStateTypeDef state; /*!< Host Channel state. This parameter can be any value of @ref USB_HCStateTypeDef */ } USB_HCTypeDef; +#endif /* defined (HAL_HCD_MODULE_ENABLED) */ typedef USB_ModeTypeDef USB_OTG_ModeTypeDef; typedef USB_CfgTypeDef USB_OTG_CfgTypeDef; + +#if defined (HAL_PCD_MODULE_ENABLED) typedef USB_EPTypeDef USB_OTG_EPTypeDef; +#endif /* defined (HAL_PCD_MODULE_ENABLED) */ + +#if defined (HAL_HCD_MODULE_ENABLED) typedef USB_URBStateTypeDef USB_OTG_URBStateTypeDef; typedef USB_HCStateTypeDef USB_OTG_HCStateTypeDef; typedef USB_HCTypeDef USB_OTG_HCTypeDef; +#endif /* defined (HAL_HCD_MODULE_ENABLED) */ /* Exported constants --------------------------------------------------------*/ @@ -308,9 +326,9 @@ typedef USB_HCTypeDef USB_OTG_HCTypeDef; /** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency * @{ */ -#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1) -#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1) -#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1) +#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0UL << 1) +#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1UL << 1) +#define DSTS_ENUMSPD_FS_PHY_48MHZ (3UL << 1) /** * @} */ @@ -451,6 +469,12 @@ typedef USB_HCTypeDef USB_OTG_HCTypeDef; #define TEST_PACKET 4U #define TEST_FORCE_EN 5U +#define USB_OTG_GAHBCFG_HBSTLEN_SINGLE (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) +#define USB_OTG_GAHBCFG_HBSTLEN_INCR (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) +#define USB_OTG_GAHBCFG_HBSTLEN_INCR4 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) +#define USB_OTG_GAHBCFG_HBSTLEN_INCR8 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) +#define USB_OTG_GAHBCFG_HBSTLEN_INCR16 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) + #define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE) #define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE) @@ -504,18 +528,23 @@ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTy HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed); HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num); + +#if defined (HAL_PCD_MODULE_ENABLED) HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma); +HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +#endif /* defined (HAL_PCD_MODULE_ENABLED) */ + HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma); void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len); -HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); + HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address); HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx); @@ -531,13 +560,17 @@ uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, u uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx); uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt); +HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq); HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); -HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq); HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state); uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx); uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx); +HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num); +HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx); + +#if defined (HAL_HCD_MODULE_ENABLED) HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, uint8_t epnum, uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps); @@ -546,8 +579,9 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num); -HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num); -HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_HC_Activate(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, uint8_t ch_dir); +#endif /* defined (HAL_HCD_MODULE_ENABLED) */ + HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx); #endif /* defined (USB1_OTG_HS) || defined (USB2_OTG_HS) */ @@ -573,5 +607,4 @@ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx); } #endif /* __cplusplus */ - #endif /* STM32N6xx_LL_USB_H */ diff --git a/Drivers/STM32N6xx_HAL_Driver/LICENSE.txt b/Drivers/STM32N6xx_HAL_Driver/LICENSE.txt new file mode 100644 index 0000000..3edc4d1 --- /dev/null +++ b/Drivers/STM32N6xx_HAL_Driver/LICENSE.txt @@ -0,0 +1,6 @@ +This software component is provided to you as part of a software package and +applicable license terms are in the Package_license file. If you received this +software component outside of a package or without applicable license terms, +the terms of the BSD-3-Clause license shall apply. +You may obtain a copy of the BSD-3-Clause at: +https://opensource.org/licenses/BSD-3-Clause diff --git a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_cortex.c b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_cortex.c index 7ab3f18..5f81d8b 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_cortex.c +++ b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_cortex.c @@ -729,6 +729,7 @@ static void MPU_ConfigRegion(MPU_Type *MPUx, const MPU_Region_InitTypeDef *pMPU_ /* Check the parameters */ assert_param(IS_MPU_INSTRUCTION_ACCESS(pMPU_RegionInit->DisableExec)); + assert_param(IS_MPU_PRIV_INSTRUCTION_ACCESS(pMPU_RegionInit->DisablePrivExec)); assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(pMPU_RegionInit->AccessPermission)); assert_param(IS_MPU_ACCESS_SHAREABLE(pMPU_RegionInit->IsShareable)); assert_param(IS_MPU_ATTRIBUTES_NUMBER(pMPU_RegionInit->AttributesIndex)); @@ -739,6 +740,7 @@ static void MPU_ConfigRegion(MPU_Type *MPUx, const MPU_Region_InitTypeDef *pMPU_ ((uint32_t)pMPU_RegionInit->DisableExec << MPU_RBAR_XN_Pos)); MPUx->RLAR = (((uint32_t)pMPU_RegionInit->LimitAddress & 0xFFFFFFE0UL) | + ((uint32_t)pMPU_RegionInit->DisablePrivExec << MPU_RLAR_PXN_Pos) | ((uint32_t)pMPU_RegionInit->AttributesIndex << MPU_RLAR_AttrIndx_Pos) | ((uint32_t)pMPU_RegionInit->Enable << MPU_RLAR_EN_Pos)); } diff --git a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_cryp.c b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_cryp.c index 85209f9..b817320 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_cryp.c +++ b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_cryp.c @@ -657,7 +657,7 @@ HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp) * the configuration information for CRYP module * @retval HAL status */ -HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf) +HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, const CRYP_ConfigTypeDef *pConf) { /* Check the CRYP handle allocation */ if ((hcryp == NULL) || (pConf == NULL)) @@ -806,7 +806,7 @@ HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD pConf->HeaderWidthUnit = hcryp->Init.HeaderWidthUnit; pConf->KeyMode = hcryp->Init.KeyMode; pConf->KeySelect = hcryp->Init.KeySelect; - hcryp->Init.KeyProtection = pConf->KeyProtection; + pConf->KeyProtection = hcryp->Init.KeyProtection; pConf->KeyIVConfigSkip = hcryp->Init.KeyIVConfigSkip; /* Process Unlocked */ @@ -3686,7 +3686,8 @@ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uin static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) { - uint32_t temp[4]; /* Temporary CrypOutBuff */ + + uint32_t temp[4] = {0};/* Temporary CrypOutBuff */ #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) uint16_t incount; /* Temporary CrypInCount Value */ uint16_t outcount; /* Temporary CrypOutCount Value */ @@ -3737,6 +3738,7 @@ static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) if (((((CRYP_TypeDef *)(hcryp->Instance))->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < ((hcryp->Size) / 4U))) { + /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ for (i = 0U; i < 4U; i++) @@ -3792,6 +3794,7 @@ static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/ + for (i = 0U; i < 4U; i++) { temp[i] = ((SAES_TypeDef *)(hcryp->Instance))->DOUTR; @@ -3817,7 +3820,8 @@ static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) */ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) { - uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t temp[4] = {0};/* Temporary CrypOutBuff */ + #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) uint16_t incount; /* Temporary CrypInCount Value */ uint16_t outcount; /* Temporary CrypOutCount Value */ @@ -4131,7 +4135,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t uint32_t tickstart; uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U; uint32_t npblb ; - uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t temp[4] = {0};/* Temporary CrypOutBuff */ uint32_t index ; uint32_t lastwordsize ; uint32_t outcount; /* Temporary CrypOutCount Value */ @@ -4984,7 +4988,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp) uint32_t index; uint32_t npblb; uint32_t lastwordsize = 0U; - uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t temp[4] = {0};/* Temporary CrypOutBuff */ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ uint32_t mode; uint32_t Timeout = CRYP_GENERAL_TIMEOUT; @@ -5340,7 +5344,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U; uint32_t npblb ; uint32_t lastwordsize ; - uint32_t temp[4] ; /* Temporary CrypOutBuff */ + uint32_t temp[4] = {0};/* Temporary CrypOutBuff */ uint32_t index ; uint32_t outcount; /* Temporary CrypOutCount Value */ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ @@ -6173,7 +6177,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) uint32_t index; uint32_t npblb; uint32_t lastwordsize = 0U; - uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t temp[4] = {0};/* Temporary CrypOutBuff */ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ uint32_t mode; #if !defined(USE_HAL_CRYP_ONLY) || (USE_HAL_CRYP_ONLY == 1) @@ -6525,7 +6529,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) { uint32_t loopcounter; - uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t temp[4] = {0};/* Temporary CrypOutBuff */ uint32_t lastwordsize; uint32_t npblb; uint32_t mode; diff --git a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_dma.c b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_dma.c index 3217e5b..0ea4dae 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_dma.c +++ b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_dma.c @@ -328,6 +328,17 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *const hdma) /* Allocate lock resource */ __HAL_UNLOCK(hdma); + /* Initialize the callbacks */ + if (hdma->State == HAL_DMA_STATE_RESET) + { + /* Clean all callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + hdma->XferSuspendCallback = NULL; + } + /* Update the DMA channel state */ hdma->State = HAL_DMA_STATE_BUSY; @@ -1606,7 +1617,6 @@ HAL_StatusTypeDef HAL_DMA_GetIsolationAttributes(DMA_HandleTypeDef const *const return HAL_OK; } - #if defined (CPU_IN_SECURE_STATE) /** * @brief Lock the DMA channel security and privilege attribute(s). diff --git a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_dma_ex.c b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_dma_ex.c index 71c1057..50deac5 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_dma_ex.c +++ b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_dma_ex.c @@ -3546,7 +3546,7 @@ HAL_StatusTypeDef HAL_DMAEx_Suspend(DMA_HandleTypeDef *const hdma) } /** - * @brief Suspend any ongoing DMA channel transfer in polling mode (Non-blocking mode). + * @brief Suspend any ongoing DMA channel transfer in interrupt mode (Non-blocking mode). * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the * specified DMA Channel. * @retval HAL status. diff --git a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_dts.c b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_dts.c index 55ef60c..f1af26c 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_dts.c +++ b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_dts.c @@ -279,7 +279,7 @@ HAL_StatusTypeDef HAL_DTS_Init(DTS_HandleTypeDef *hdts) /* So CLK_SYNTH_HI and CLK_SYNTH_LO have to be set to 0 on TSCCLKSYNTHR register */ /* in order to have TS clock frequency at 4MHz. */ hdts->Instance->TSCCLKSYNTHR = (DTS_TSCCLKSYNTHR_CLK_SYNTH_EN | - (1U << DTS_TSCCLKSYNTHR_CLK_SYNTH_HOLD_Pos)); + (1UL << DTS_TSCCLKSYNTHR_CLK_SYNTH_HOLD_Pos)); /* Program typical power-up delay for all sensors */ status = DTS_ProgramSdaRegister(hdts, DTS_SENSOR_ALL, DTS_SDATS_TIMERR_REG, DTS_SDA_POWER_UP_DELAY); diff --git a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_eth.c b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_eth.c index 609118b..2d22ffb 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_eth.c +++ b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_eth.c @@ -83,6 +83,7 @@ (##) HAL_ETH_PTP_GetTime(): Get Seconds and Nanoseconds for the Ethernet PTP registers (##) HAL_ETH_PTP_SetTime(): Set Seconds and Nanoseconds for the Ethernet PTP registers (##) HAL_ETH_PTP_AddTimeOffset(): Add Seconds and Nanoseconds offset for the Ethernet PTP registers + (##) HAL_ETH_PTP_AddendUpdate(): Update the Addend register (##) HAL_ETH_PTP_InsertTxTimestamp(): Insert Timestamp in transmission (##) HAL_ETH_PTP_GetTxTimestamp(): Get transmission timestamp (##) HAL_ETH_PTP_GetRxTimestamp(): Get reception timestamp @@ -268,6 +269,11 @@ static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth); #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth); #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + +#ifdef HAL_ETH_USE_PTP +static HAL_StatusTypeDef HAL_ETH_PTP_AddendUpdate(ETH_HandleTypeDef *heth, int32_t timeoffset); +#endif /* HAL_ETH_USE_PTP */ + /** * @} */ @@ -1737,6 +1743,7 @@ HAL_StatusTypeDef HAL_ETH_PTP_GetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef * HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpdateTypeDef ptpoffsettype, ETH_TimeTypeDef *timeoffset) { + int32_t addendtime ; if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED) { if (ptpoffsettype == HAL_ETH_PTP_NEGATIVE_UPDATE) @@ -1754,6 +1761,11 @@ HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpda /* Set nanoSeconds update */ heth->Instance->MACSTNUR = ETH_MACSTSUR_VALUE - timeoffset->NanoSeconds + 1U; } + + /* adjust negative addend register */ + addendtime = - timeoffset->NanoSeconds; + HAL_ETH_PTP_AddendUpdate(heth, addendtime); + } else { @@ -1761,6 +1773,11 @@ HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpda heth->Instance->MACSTSUR = timeoffset->Seconds; /* Set nanoSeconds update */ heth->Instance->MACSTNUR = timeoffset->NanoSeconds; + + /* adjust positive addend register */ + addendtime = timeoffset->NanoSeconds; + HAL_ETH_PTP_AddendUpdate(heth, addendtime); + } SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSUPDT); @@ -1775,6 +1792,40 @@ HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpda } } +/** + * @brief Update the Addend register + * @param heth: Pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param timeoffset: The value of the time offset to be added to + * the addend register in Nanoseconds + * @retval HAL status + */ +static HAL_StatusTypeDef HAL_ETH_PTP_AddendUpdate(ETH_HandleTypeDef *heth, int32_t timeoffset) +{ + uint32_t tmpreg; + if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED) + { + /* update the addend register */ + + tmpreg = READ_REG(heth->Instance->MACTSAR); + tmpreg += timeoffset ; + WRITE_REG(heth->Instance->MACTSAR, tmpreg); + + SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSADDREG); + while ((heth->Instance->MACTSCR & ETH_MACTSCR_TSADDREG) != 0) + { + + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Return function status */ + return HAL_ERROR; + } +} /** * @brief Insert Timestamp in transmission. * @param heth: pointer to a ETH_HandleTypeDef structure that contains diff --git a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_hash.c b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_hash.c index ca3e8be..2269810 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_hash.c +++ b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_hash.c @@ -301,7 +301,7 @@ HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash) * the configuration information for HASH module * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SetConfig(HASH_HandleTypeDef *hhash, HASH_ConfigTypeDef *pConf) +HAL_StatusTypeDef HAL_HASH_SetConfig(HASH_HandleTypeDef *hhash, const HASH_ConfigTypeDef *pConf) { uint32_t cr_value; @@ -1864,11 +1864,10 @@ HAL_StatusTypeDef HAL_HASH_HMAC_Start_IT(HASH_HandleTypeDef *hhash, const uint8_ { return HAL_BUSY; } - + status = HASH_WriteData_IT(hhash); /* Enable the specified HASH interrupt*/ __HAL_HASH_ENABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI); - status = HASH_WriteData_IT(hhash); /* Return function status */ return status; @@ -1945,10 +1944,10 @@ HAL_StatusTypeDef HAL_HASH_HMAC_Accumulate_IT(HASH_HandleTypeDef *hhash, const u /* Set the phase */ hhash->Phase = HAL_HASH_PHASE_PROCESS; } + status = HASH_WriteData_IT(hhash); /* Enable the specified HASH interrupt*/ __HAL_HASH_ENABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI); - status = HASH_WriteData_IT(hhash); } else { @@ -1995,10 +1994,10 @@ HAL_StatusTypeDef HAL_HASH_HMAC_AccumulateLast_IT(HASH_HandleTypeDef *hhash, con hhash->Size = Size; /* Set multi buffers accumulation flag */ hhash->Accumulation = 0U; + status = HASH_WriteData_IT(hhash); /* Enable the specified HASH interrupt*/ __HAL_HASH_ENABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI); - status = HASH_WriteData_IT(hhash); } else { @@ -2248,7 +2247,7 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash) } /* If Peripheral ready to accept new data */ - if ((itflag & HASH_FLAG_DINIS) == HASH_FLAG_DINIS) + if (((itflag & HASH_FLAG_DINIS) == HASH_FLAG_DINIS) && ((itflag & HASH_FLAG_DCIS) != HASH_FLAG_DCIS)) { if ((itsource & HASH_IT_DINI) == HASH_IT_DINI) { diff --git a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_hcd.c b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_hcd.c index b0c17e8..939894a 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_hcd.c +++ b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_hcd.c @@ -1227,6 +1227,24 @@ HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_nu return HAL_OK; } + + +/** @brief Activate a host channel. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_Activate(HCD_HandleTypeDef *hhcd, uint8_t ch_num) +{ + HAL_StatusTypeDef status = HAL_OK; + + __HAL_LOCK(hhcd); + (void)USB_HC_Activate(hhcd->Instance, (uint8_t)ch_num, hhcd->hc[ch_num].ch_dir); + __HAL_UNLOCK(hhcd); + + return status; +} /** * @} */ @@ -1350,6 +1368,8 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); + hhcd->hc[chnum].NakCnt = 0U; + if (hhcd->hc[chnum].do_ssplit == 1U) { hhcd->hc[chnum].do_csplit = 1U; @@ -1362,6 +1382,14 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH); + tmpreg = USBx_HC(chnum)->HCCHAR; + + if ((tmpreg & USB_OTG_HCCHAR_CHDIS) != 0U) + { + /* Halt received while channel disable still in progress */ + return; + } + if (hhcd->hc[chnum].state == HC_XFRC) { hhcd->hc[chnum].state = HC_HALTED; @@ -1376,19 +1404,38 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) (hhcd->hc[chnum].state == HC_DATATGLERR)) { hhcd->hc[chnum].state = HC_HALTED; - hhcd->hc[chnum].ErrCnt++; - if (hhcd->hc[chnum].ErrCnt > 2U) + + if (hhcd->Init.dma_enable == 0U) { - hhcd->hc[chnum].ErrCnt = 0U; + hhcd->hc[chnum].ErrCnt++; - if (hhcd->hc[chnum].do_ssplit == 1U) + if (hhcd->hc[chnum].ErrCnt > 2U) { - hhcd->hc[chnum].do_csplit = 0U; - hhcd->hc[chnum].ep_ss_schedule = 0U; - __HAL_HCD_CLEAR_HC_CSPLT(chnum); + hhcd->hc[chnum].ErrCnt = 0U; + + if (hhcd->hc[chnum].do_ssplit == 1U) + { + hhcd->hc[chnum].do_csplit = 0U; + hhcd->hc[chnum].ep_ss_schedule = 0U; + __HAL_HCD_CLEAR_HC_CSPLT(chnum); + } + + hhcd->hc[chnum].urb_state = URB_ERROR; } + else + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; - hhcd->hc[chnum].urb_state = URB_ERROR; + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { + /* re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + } + } } else { @@ -1479,11 +1526,24 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) { - /* re-activate the channel */ - tmpreg = USBx_HC(chnum)->HCCHAR; - tmpreg &= ~USB_OTG_HCCHAR_CHDIS; - tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(chnum)->HCCHAR = tmpreg; +#if defined (USE_HAL_HCD_IN_NAK_AUTO_ACTIVATE_DISABLE) && (USE_HAL_HCD_IN_NAK_AUTO_ACTIVATE_DISABLE == 1) + hhcd->hc[chnum].NakCnt++; + + if (hhcd->hc[chnum].NakCnt >= HAL_HCD_CHANNEL_NAK_COUNT) + { + hhcd->hc[chnum].state = HC_IDLE; + hhcd->hc[chnum].urb_state = URB_NAK_WAIT; + hhcd->hc[chnum].NakCnt = 0U; + } + else +#endif /* defined (USE_HAL_HCD_IN_NAK_AUTO_ACTIVATE_DISABLE) && (USE_HAL_HCD_IN_NAK_AUTO_ACTIVATE_DISABLE == 1) */ + { + /* re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + } } } else if (hhcd->hc[chnum].state == HC_BBLERR) diff --git a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_ltdc.c b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_ltdc.c index 0805258..dce1ae2 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_ltdc.c +++ b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_ltdc.c @@ -1238,7 +1238,7 @@ HAL_StatusTypeDef HAL_LTDC_ConfigGammaCorrection(LTDC_HandleTypeDef *hltdc, uint hltdc->Instance->GCCR = RGBComponent | ((uint32_t) GammaAdress[gammasegment] << LTDC_GCCR_ADDR_Pos) | ((uint32_t) GammaLUT[gammasegment + gammaindex] << LTDC_GCCR_COMP_Pos); } - hltdc->Instance->GCCR = RGBComponent | (0xFFU << LTDC_GCCR_COMP_Pos) | LTDC_GCCR_ADDR; + hltdc->Instance->GCCR = RGBComponent | (0xFFUL << LTDC_GCCR_COMP_Pos) | LTDC_GCCR_ADDR; /* Change the LTDC state*/ hltdc->State = HAL_LTDC_STATE_READY; diff --git a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_mdios.c b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_mdios.c index be42e28..5a806c2 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_mdios.c +++ b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_mdios.c @@ -712,8 +712,12 @@ HAL_StatusTypeDef HAL_MDIOS_EnableEvents(MDIOS_HandleTypeDef *hmdios) */ void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios) { + uint32_t itsource = READ_REG(hmdios->Instance->CR); + uint32_t itflag = READ_REG(hmdios->Instance->SR); + uint32_t exti_flag = READ_REG(EXTI->IMR2); + /* Write Register Interrupt enabled ? */ - if (__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_WRITE) != (uint32_t)RESET) + if ((itsource & MDIOS_IT_WRITE) != 0U) { /* Write register flag */ if (HAL_MDIOS_GetWrittenRegAddress(hmdios) != (uint32_t)RESET) @@ -732,7 +736,7 @@ void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios) } /* Read Register Interrupt enabled ? */ - if (__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_READ) != (uint32_t)RESET) + if ((itsource & MDIOS_IT_READ) != 0U) { /* Read register flag */ if (HAL_MDIOS_GetReadRegAddress(hmdios) != (uint32_t)RESET) @@ -751,10 +755,10 @@ void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios) } /* Error Interrupt enabled ? */ - if (__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_ERROR) != (uint32_t)RESET) + if ((itsource & MDIOS_IT_ERROR) != 0U) { /* All Errors Flag */ - if (__HAL_MDIOS_GET_ERROR_FLAG(hmdios, MDIOS_ALL_ERRORS_FLAG) != (uint32_t)RESET) + if ((itflag & MDIOS_ALL_ERRORS_FLAG) != 0U) { hmdios->ErrorCode |= HAL_MDIOS_ERROR_DATA; @@ -772,7 +776,7 @@ void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios) hmdios->ErrorCode = HAL_MDIOS_ERROR_NONE; } /* check MDIOS WAKEUP exti flag */ - if (__HAL_MDIOS_WAKEUP_EXTI_GET_FLAG(MDIOS_WAKEUP_EXTI_LINE) != (uint32_t)RESET) + if ((exti_flag & MDIOS_WAKEUP_EXTI_LINE) != 0U) { /* Clear MDIOS WAKEUP Exti pending bit */ __HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG(MDIOS_WAKEUP_EXTI_LINE); diff --git a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_mmc.c b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_mmc.c index 6eefd7d..777abcd 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_mmc.c +++ b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_mmc.c @@ -3382,7 +3382,7 @@ HAL_StatusTypeDef HAL_MMC_SleepDevice(MMC_HandleTypeDef *hmmc) { /* Send CMD5 CMD_MMC_SLEEP_AWAKE with RCA and SLEEP as argument */ errorstate = SDMMC_CmdSleepMmc(hmmc->Instance, - ((hmmc->MmcCard.RelCardAdd << 16U) | (0x1U << 15U))); + ((hmmc->MmcCard.RelCardAdd << 16UL) | (0x1UL << 15UL))); if (errorstate == HAL_MMC_ERROR_NONE) { /* Wait that the device is ready by checking the D0 line */ @@ -4093,7 +4093,7 @@ static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state) } else { - Init.ClockDiv = sdmmc_clk / (2U * MMC_HIGH_SPEED_FREQ); + Init.ClockDiv = (sdmmc_clk / (2U * MMC_HIGH_SPEED_FREQ)) + 1U; } (void)SDMMC_Init(hmmc->Instance, Init); diff --git a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_pcd.c b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_pcd.c index 0642830..32e8fe0 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_pcd.c +++ b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_pcd.c @@ -1398,8 +1398,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { if (hpcd->OUT_ep[epnum].is_iso_incomplete == 1U) { - /* Abort current transaction and disable the EP */ - (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)epnum); + /* disable the EP */ + USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK); + USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS); } } } @@ -1433,7 +1434,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) && ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) && - (((RegVal & (0x1U << 16)) >> 16U) == (hpcd->FrameNumber & 0x1U))) + (((RegVal & (0x1UL << 16)) >> 16U) == (hpcd->FrameNumber & 0x1U))) { hpcd->OUT_ep[epnum].is_iso_incomplete = 1U; @@ -2062,6 +2063,7 @@ HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t tes case TEST_SE0_NAK: case TEST_PACKET: case TEST_FORCE_EN: + USBx_DEVICE->DCTL &= ~(0x7UL << 4); USBx_DEVICE->DCTL |= (uint32_t)testmode << 4; break; diff --git a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_rcc.c b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_rcc.c index 3dc8b5d..ceb49ed 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_rcc.c +++ b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_rcc.c @@ -120,12 +120,15 @@ #define RCC_MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() #define RCC_MCO2_GPIO_PORT GPIOC #define RCC_MCO2_PIN GPIO_PIN_9 + +#define RCC_GET_MSI_FREQUENCY() (HAL_IS_BIT_SET(RCC->MSICFGR, RCC_MSICFGR_MSIFREQSEL) ? (MSI_VALUE << 2U) : MSI_VALUE) /** * @} */ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ +static uint32_t RCC_GetSysClockFreq(uint32_t icx_source, uint32_t icx_divider); static HAL_StatusTypeDef RCC_PLL_Config(uint32_t PLLnumber, const RCC_PLLInitTypeDef *pPLLInit); static HAL_StatusTypeDef RCC_PLL_Enable(uint32_t PLLnumber); static uint32_t RCC_PLL_IsNewConfig(uint32_t PLLnumber, const RCC_PLLInitTypeDef *pPLLInit); @@ -345,6 +348,8 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) * first and then HSE On or HSE Bypass. * @note This function does not protect the MCOxSEL, the PERSEL and the PPPSEL glitch-free muxes * (Mux selection cannot be changed if selected input clock is inactive). + * @note This function activates HSE but does not wait for the startup time defined in the datasheet. + * This must be ensured by the application when the HSE is selected as PLL source. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *pRCC_OscInitStruct) @@ -1357,14 +1362,7 @@ uint32_t HAL_RCC_GetCpuClockFreq(void) break; case LL_RCC_CPU_CLKSOURCE_STATUS_MSI: - if (LL_RCC_MSI_GetFrequency() == LL_RCC_MSI_FREQ_4MHZ) - { - frequency = MSI_VALUE; - } - else - { - frequency = 16000000UL; - } + frequency = RCC_GET_MSI_FREQUENCY(); break; case LL_RCC_CPU_CLKSOURCE_STATUS_HSE: @@ -1434,71 +1432,89 @@ uint32_t HAL_RCC_GetCpuClockFreq(void) * baud rate for the communication peripherals or configure other parameters. * * @note Each time SYSCLK changes, this function must be called by the user application - * to update the SYSCLK value. Otherwise, any configuration based on this function + * to update the SYSCLK bus value. Otherwise, any configuration based on this function * will be incorrect. * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { - uint32_t frequency = 0U; - uint32_t ic_divider; - - /* Get SYSCLK source -------------------------------------------------------*/ - switch (LL_RCC_GetSysClkSource()) - { - /* No check on Ready: Won't be selected by hardware if not */ - case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: - frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos); - break; - - case LL_RCC_SYS_CLKSOURCE_STATUS_MSI: - if (LL_RCC_MSI_GetFrequency() == LL_RCC_MSI_FREQ_4MHZ) - { - frequency = MSI_VALUE; - } - else - { - frequency = 16000000UL; - } - break; - - case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: - frequency = HSE_VALUE; - break; - - case LL_RCC_SYS_CLKSOURCE_STATUS_IC2_IC6_IC11: - ic_divider = LL_RCC_IC2_GetDivider(); - switch (LL_RCC_IC2_GetSource()) - { - case LL_RCC_ICCLKSOURCE_PLL1: - frequency = HAL_RCCEx_GetPLL1CLKFreq(); - frequency = frequency / ic_divider; - break; - case LL_RCC_ICCLKSOURCE_PLL2: - frequency = HAL_RCCEx_GetPLL2CLKFreq(); - frequency = frequency / ic_divider; - break; - case LL_RCC_ICCLKSOURCE_PLL3: - frequency = HAL_RCCEx_GetPLL3CLKFreq(); - frequency = frequency / ic_divider; - break; - case LL_RCC_ICCLKSOURCE_PLL4: - frequency = HAL_RCCEx_GetPLL4CLKFreq(); - frequency = frequency / ic_divider; - break; - default: - /* Unexpected case */ - break; - } - break; + return RCC_GetSysClockFreq(LL_RCC_IC2_GetSource(), LL_RCC_IC2_GetDivider()); +} - default: - /* Unexpected case */ - break; - } +/** + * @brief Returns the NPU clock (sysc_ck) frequency + * + * @note The NPU clock frequency computed by this function may be not the real frequency in the chip. + * It is calculated based on the predefined constant and the selected clock source: + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**) + * @note If SYSCLK source is MSI, function returns values based on MSI_VALUE(*) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***) + * @note If SYSCLK source is IC6, function returns values based on HSI_VALUE(*), + * MSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. + * @note (*) HSI_VALUE is a constant defined in stm32n6xx_hal_conf.h file (default value + * 64 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (**) MSI_VALUE is a constant defined in stm32n6xx_hal_conf.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (***) HSE_VALUE is a constant defined in stm32n6xx_hal_conf.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @note This function can be used by the user application. + * + * @note Each time SYSCLK changes, this function must be called by the user application + * to update the NPU clock value. Otherwise, any configuration based on this function + * will be incorrect. + * + * @retval NPU clock frequency + */ +uint32_t HAL_RCC_GetNPUClockFreq(void) +{ + return RCC_GetSysClockFreq(LL_RCC_IC6_GetSource(), LL_RCC_IC6_GetDivider()); +} - return frequency; +/** + * @brief Returns the NPU RAMS clock (sysd_ck) frequency + * + * @note The NPU RAMS rams clock frequency computed by this function may be not the real frequency in the chip. + * It is calculated based on the predefined constant and the selected clock source: + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**) + * @note If SYSCLK source is MSI, function returns values based on MSI_VALUE(*) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***) + * @note If SYSCLK source is IC11, function returns values based on HSI_VALUE(*), + * MSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. + * @note (*) HSI_VALUE is a constant defined in stm32n6xx_hal_conf.h file (default value + * 64 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (**) MSI_VALUE is a constant defined in stm32n6xx_hal_conf.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (***) HSE_VALUE is a constant defined in stm32n6xx_hal_conf.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @note This function can be used by the user application to compute the + * baud rate for the communication peripherals or configure other parameters. + * + * @note Each time SYSCLK changes, this function must be called by the user application + * to update the NPU RAMS clock value. Otherwise, any configuration based on this function + * will be incorrect. + * + * @retval NPU RAMS clock frequency + */ +uint32_t HAL_RCC_GetNPURAMSClockFreq(void) +{ + return RCC_GetSysClockFreq(LL_RCC_IC11_GetSource(), LL_RCC_IC11_GetDivider()); } /** @@ -2012,6 +2028,66 @@ HAL_StatusTypeDef HAL_RCC_GetConfigAttributes(uint32_t Item, uint32_t *pAttribut /** @defgroup RCC_Private_functions RCC Private Functions * @{ */ +/** + * @brief Returns the SYSCLK frequency divided, if icx is selected, by icx_divider. + * @param icx_source The intermediate clock source + * @param icx_divider The intermediate clock divider + * + * @retval SYSCLK frequency + */ +static uint32_t RCC_GetSysClockFreq(uint32_t icx_source, uint32_t icx_divider) +{ + uint32_t frequency = 0U; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (LL_RCC_GetSysClkSource()) + { + /* No check on Ready: Won't be selected by hardware if not */ + case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: + frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos); + break; + + case LL_RCC_SYS_CLKSOURCE_STATUS_MSI: + frequency = RCC_GET_MSI_FREQUENCY(); + break; + + case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: + frequency = HSE_VALUE; + break; + + case LL_RCC_SYS_CLKSOURCE_STATUS_IC2_IC6_IC11: + switch (icx_source) + { + case LL_RCC_ICCLKSOURCE_PLL1: + frequency = HAL_RCCEx_GetPLL1CLKFreq(); + frequency = frequency / icx_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL2: + frequency = HAL_RCCEx_GetPLL2CLKFreq(); + frequency = frequency / icx_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL3: + frequency = HAL_RCCEx_GetPLL3CLKFreq(); + frequency = frequency / icx_divider; + break; + case LL_RCC_ICCLKSOURCE_PLL4: + frequency = HAL_RCCEx_GetPLL4CLKFreq(); + frequency = frequency / icx_divider; + break; + default: + /* Unexpected case */ + break; + } + break; + + default: + /* Unexpected case */ + break; + } + + return frequency; +} + /** * @brief Configure the requested PLL * @param PLLnumber PLL number to configure diff --git a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_rcc_ex.c b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_rcc_ex.c index 525b58c..6128c8b 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_rcc_ex.c +++ b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_rcc_ex.c @@ -36,17 +36,6 @@ /* Private typedef -----------------------------------------------------------*/ /* Private defines -----------------------------------------------------------*/ -/** @defgroup RCCEx_Private_Constants RCCEx Private Constants - * @{ - */ -#if defined(USE_FPGA) -/* ***** FPGA values ******/ -#define RCC_PLL_SOURCE_FREQ 32000000UL /* PLL source forced to 32MHz */ -#endif /* USE_FPGA */ -/** - * @} - */ - /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -2589,7 +2578,7 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) * @arg RCC_PERIPHCLK_XSPI1 : XSPI1 peripheral clock * @arg RCC_PERIPHCLK_XSPI2 : XSPI2 peripheral clock * @arg RCC_PERIPHCLK_XSPI3 : XSPI3 peripheral clock - * @retval Frequency in KHz + * @retval Frequency in Hz */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk) { @@ -2838,11 +2827,6 @@ uint32_t HAL_RCCEx_GetPLL1CLKFreq(void) if (pllinputfreq != RCC_PERIPH_FREQUENCY_NO) { -#if defined(USE_FPGA) - /**** FPGA PLL input forced to 32MHz *****/ - pllinputfreq = RCC_PLL_SOURCE_FREQ; - /*****************************************/ -#endif /* USE_FPGA */ divm = LL_RCC_PLL1_GetM(); if (divm != 0U) @@ -2886,11 +2870,7 @@ uint32_t HAL_RCCEx_GetPLL2CLKFreq(void) if (pllinputfreq != RCC_PERIPH_FREQUENCY_NO) { -#if defined(USE_FPGA) - /**** FPGA PLL input forced to 32MHz *****/ - pllinputfreq = RCC_PLL_SOURCE_FREQ; - /*****************************************/ -#endif /* USE_FPGA */ + divm = LL_RCC_PLL2_GetM(); if (divm != 0U) @@ -2934,11 +2914,6 @@ uint32_t HAL_RCCEx_GetPLL3CLKFreq(void) if (pllinputfreq != RCC_PERIPH_FREQUENCY_NO) { -#if defined(USE_FPGA) - /**** FPGA PLL input forced to 32MHz *****/ - pllinputfreq = RCC_PLL_SOURCE_FREQ; - /*****************************************/ -#endif /* USE_FPGA */ divm = LL_RCC_PLL3_GetM(); if (divm != 0U) @@ -2982,11 +2957,7 @@ uint32_t HAL_RCCEx_GetPLL4CLKFreq(void) if (pllinputfreq != RCC_PERIPH_FREQUENCY_NO) { -#if defined(USE_FPGA) - /**** FPGA PLL input forced to 32MHz *****/ - pllinputfreq = RCC_PLL_SOURCE_FREQ; - /*****************************************/ -#endif /* USE_FPGA */ + divm = LL_RCC_PLL4_GetM(); if (divm != 0U) @@ -3009,6 +2980,15 @@ uint32_t HAL_RCCEx_GetPLL4CLKFreq(void) return plloutputfreq; } +/** + * @brief Return the Timer group frequency. + * @retval Timer group frequency in Hz + */ +uint32_t HAL_RCCEx_GetTIMGFreq(void) +{ + return LL_RCC_CALC_TIMG_FREQ(HAL_RCC_GetSysClockFreq(), LL_RCC_GetTIMPrescaler()); +} + /** * @} */ @@ -3478,7 +3458,7 @@ static uint32_t RCCEx_GetADCCLKFreq(uint32_t ADCxSource) break; case LL_RCC_ADC_CLKSOURCE_TIMG: - adc_frequency = HAL_RCC_GetSysClockFreq() / (1UL << LL_RCC_GetTIMPrescaler()); + adc_frequency = LL_RCC_CALC_TIMG_FREQ(HAL_RCC_GetSysClockFreq(), LL_RCC_GetTIMPrescaler()); break; default: @@ -3588,7 +3568,7 @@ static uint32_t RCCEx_GetADFCLKFreq(uint32_t ADFxSource) break; case LL_RCC_ADF1_CLKSOURCE_TIMG: - adf_frequency = HAL_RCC_GetSysClockFreq() / (1UL << LL_RCC_GetTIMPrescaler()); + adf_frequency = LL_RCC_CALC_TIMG_FREQ(HAL_RCC_GetSysClockFreq(), LL_RCC_GetTIMPrescaler()); break; default: @@ -4510,7 +4490,7 @@ static uint32_t RCCEx_GetLPTIMCLKFreq(uint32_t LPTIMxSource) case LL_RCC_LPTIM3_CLKSOURCE_TIMG: case LL_RCC_LPTIM4_CLKSOURCE_TIMG: case LL_RCC_LPTIM5_CLKSOURCE_TIMG: - lptim_frequency = HAL_RCC_GetSysClockFreq() / (1UL << LL_RCC_GetTIMPrescaler()); + lptim_frequency = LL_RCC_CALC_TIMG_FREQ(HAL_RCC_GetSysClockFreq(), LL_RCC_GetTIMPrescaler()); break; default: @@ -4795,7 +4775,7 @@ static uint32_t RCCEx_GetMDFCLKFreq(uint32_t MDFxSource) break; case LL_RCC_MDF1_CLKSOURCE_TIMG: - adf_frequency = HAL_RCC_GetSysClockFreq() / (1UL << LL_RCC_GetTIMPrescaler()); + adf_frequency = LL_RCC_CALC_TIMG_FREQ(HAL_RCC_GetSysClockFreq(), LL_RCC_GetTIMPrescaler()); break; default: diff --git a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_rif.c b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_rif.c index 32e173f..036d13c 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_rif.c +++ b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_rif.c @@ -358,6 +358,8 @@ uint32_t HAL_RIF_RISC_GetLock(void) * @brief Configure the Security and Privilege of a designated slave peripheral. * @param PeriphId specifies the index of the bus slave. * This parameter can be one of @ref RIF_PERIPHERAL_INDEX + * bits[31:28] define the register index a peripheral belongs to, value from 0 to 5 + * bits[4:0] define the bit position within the register, value from 0 to 31 * @param SecPriv specifies the security and privilege attributes of the peripheral. * This parameter can be one or a combination of @ref RIF_SEC_PRIV * @retval None @@ -370,12 +372,12 @@ void HAL_RIF_RISC_SetSlaveSecureAttributes(uint32_t PeriphId, uint32_t SecPriv) assert_param(IS_RIF_SEC_PRIV_ATTRIBUTE(SecPriv)); sec_reg_val = RIFSC->RISC_SECCFGRx[PeriphId >> RIF_PERIPH_REG_SHIFT]; - sec_reg_val &= (~(1U << (PeriphId & RIF_PERIPH_BIT_POSITION))); + sec_reg_val &= (~(1UL << (PeriphId & RIF_PERIPH_BIT_POSITION))); sec_reg_val |= ((SecPriv & RIF_ATTRIBUTE_SEC) << (PeriphId & RIF_PERIPH_BIT_POSITION)); RIFSC->RISC_SECCFGRx[PeriphId >> RIF_PERIPH_REG_SHIFT] = sec_reg_val; sec_reg_val = RIFSC->RISC_PRIVCFGRx[PeriphId >> RIF_PERIPH_REG_SHIFT]; - sec_reg_val &= (~(1U << (PeriphId & RIF_PERIPH_BIT_POSITION))); + sec_reg_val &= (~(1UL << (PeriphId & RIF_PERIPH_BIT_POSITION))); sec_reg_val |= (((SecPriv & RIF_ATTRIBUTE_PRIV) >> 1U) << (PeriphId & RIF_PERIPH_BIT_POSITION)); RIFSC->RISC_PRIVCFGRx[PeriphId >> RIF_PERIPH_REG_SHIFT] = sec_reg_val; } @@ -384,6 +386,8 @@ void HAL_RIF_RISC_SetSlaveSecureAttributes(uint32_t PeriphId, uint32_t SecPriv) * @brief Get the Security and Privilege configuration of a designated slave peripheral. * @param PeriphId specifies the index of the bus slave. * This parameter can be one of @ref RIF_PERIPHERAL_INDEX + * bits[31:28] define the register index a peripheral belongs to, value from 0 to 5 + * bits[4:0] define the bit position within the register, value from 0 to 31 * @retval can be a combination of @ref RIF_SEC_PRIV */ uint32_t HAL_RIF_RISC_GetSlaveSecureAttributes(uint32_t PeriphId) @@ -408,6 +412,8 @@ uint32_t HAL_RIF_RISC_GetSlaveSecureAttributes(uint32_t PeriphId) * @note This API is protected by the Trusted Domain compilation directive. * @param PeriphId specifies the index of the bus slave. * This parameter can be one of @ref RIF_PERIPHERAL_INDEX + * bits[31:28] define the register index a peripheral belongs to, value from 0 to 5 + * bits[4:0] define the bit position within the register, value from 0 to 31 * @retval None */ void HAL_RIF_RISC_SlaveConfigLock(uint32_t PeriphId) @@ -426,6 +432,8 @@ void HAL_RIF_RISC_SlaveConfigLock(uint32_t PeriphId) * @brief Get the Isolation and Security configuration lock status. * @param PeriphId specifies the index of the bus slave. * This parameter can be one of @ref RIF_PERIPHERAL_INDEX + * bits[31:28] define the register index a peripheral belongs to, value from 0 to 5 + * bits[4:0] define the bit position within the register, value from 0 to 31 * @retval 1 if the Isolation and Security configuration is locked, else 0 */ uint32_t HAL_RIF_RISC_GetSlaveConfigLock(uint32_t PeriphId) @@ -995,6 +1003,8 @@ void HAL_RIF_RISAF_GetIllegalAccess(RISAF_TypeDef *RISAFx, RISAF_IllegalAccess_t * @note This API is protected by the TrustZone Enabled compilation directive. * @param PeriphId specifies the index of the bus slave. * This parameter can be one of @ref RIF_PERIPHERAL_INDEX + * bits[31:28] define the register index a peripheral belongs to, value from 0 to 5 + * bits[4:0] define the bit position within the register, value from 0 to 31 * @retval None */ void HAL_RIF_IAC_EnableIT(uint32_t PeriphId) @@ -1014,6 +1024,8 @@ void HAL_RIF_IAC_EnableIT(uint32_t PeriphId) * @note This API is protected by the Trusted Domain compilation directive. * @param PeriphId specifies the index of the bus slave. * This parameter can be one of @ref RIF_PERIPHERAL_INDEX + * bits[31:28] define the register index a peripheral belongs to, value from 0 to 5 + * bits[4:0] define the bit position within the register, value from 0 to 31 * @retval None */ void HAL_RIF_IAC_DisableIT(uint32_t PeriphId) @@ -1032,6 +1044,8 @@ void HAL_RIF_IAC_DisableIT(uint32_t PeriphId) * @note This API is protected by the Trusted Domain compilation directive. * @param PeriphId specifies the index of the bus slave. * This parameter can be one of @ref RIF_PERIPHERAL_INDEX + * bits[31:28] define the register index a peripheral belongs to, value from 0 to 5 + * bits[4:0] define the bit position within the register, value from 0 to 31 * @retval Detection flag value */ uint32_t HAL_RIF_IAC_GetFlag(uint32_t PeriphId) @@ -1055,6 +1069,8 @@ uint32_t HAL_RIF_IAC_GetFlag(uint32_t PeriphId) * @note This API is protected by the Trusted Domain compilation directive. * @param PeriphId specifies the index of the bus slave. * This parameter can be one of @ref RIF_PERIPHERAL_INDEX + * bits[31:28] define the register index a peripheral belongs to, value from 0 to 5 + * bits[4:0] define the bit position within the register, value from 0 to 31 * @retval None */ void HAL_RIF_IAC_ClearFlag(uint32_t PeriphId) @@ -1104,6 +1120,8 @@ void HAL_RIF_IRQHandler(void) * @note This API is protected by the TrustZone Enabled compilation directive. * @param PeriphId specifies the index of the bus slave. * This parameter can be one of @ref RIF_PERIPHERAL_INDEX + * bits[31:28] define the register index a peripheral belongs to, value from 0 to 5 + * bits[4:0] define the bit position within the register, value from 0 to 31 * @retval None */ __weak void HAL_RIF_ILA_Callback(uint32_t PeriphId) diff --git a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_rng.c b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_rng.c index 1d769f4..cb270cb 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_rng.c +++ b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_rng.c @@ -641,6 +641,8 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t status = RNG_RecoverSeedError(hrng); if (status == HAL_ERROR) { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_RECOVERSEED; return status; } } diff --git a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_rng_ex.c b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_rng_ex.c index 1d64276..b8ba80b 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_rng_ex.c +++ b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_rng_ex.c @@ -306,6 +306,11 @@ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng) /* sequence to fully recover from a seed error */ status = RNG_RecoverSeedError(hrng); + if (status == HAL_ERROR) + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_RECOVERSEED; + } } else { diff --git a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_sai_ex.c b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_sai_ex.c index 3bdb9e3..5158d2b 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_sai_ex.c +++ b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_sai_ex.c @@ -39,7 +39,7 @@ /** @defgroup SAIEx_Private_Defines SAIEx Extended Private Defines * @{ */ -#define SAI_PDM_DELAY_MASK 0x77U +#define SAI_PDM_DELAY_MASK 0x77UL #define SAI_PDM_DELAY_OFFSET 8U #define SAI_PDM_RIGHT_DELAY_OFFSET 4U /** diff --git a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_sdio.c b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_sdio.c index 6b2fa3c..7ac560b 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_sdio.c +++ b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_sdio.c @@ -256,18 +256,18 @@ #define IS_SDIO_FUNCTION(FN) (((FN) >= HAL_SDIO_FUNCTION_1) && ((FN) <= HAL_SDIO_FUNCTION_7)) -#define IS_SDIO_SUPPORTED_BLOCK_SIZE(BLOCKSIZE) (((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_1BYTE) || \ - ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_2BYTE) || \ - ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_4BYTE) || \ - ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_8BYTE) || \ - ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_16BYTE) || \ - ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_32BYTE) || \ - ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_64BYTE) || \ - ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_128BYTE) || \ - ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_256BYTE) || \ - ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) || \ - ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_1024BYTE) || \ - ((BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_2048BYTE)) +#define IS_SDIO_SUPPORTED_BLOCK_SIZE(SDIO_BLOCKSIZE) (((SDIO_BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_1BYTE) || \ + ((SDIO_BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_2BYTE) || \ + ((SDIO_BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_4BYTE) || \ + ((SDIO_BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_8BYTE) || \ + ((SDIO_BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_16BYTE) || \ + ((SDIO_BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_32BYTE) || \ + ((SDIO_BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_64BYTE) || \ + ((SDIO_BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_128BYTE) || \ + ((SDIO_BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_256BYTE) || \ + ((SDIO_BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_512BYTE) || \ + ((SDIO_BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_1024BYTE) || \ + ((SDIO_BLOCKSIZE) == HAL_SDIO_DATA_BLOCK_SIZE_2048BYTE)) /* Private functions -------------------------------------------------------------------------------------------------*/ /** @defgroup SDIO_Private_Functions SDIO Private Functions @@ -277,10 +277,10 @@ static HAL_StatusTypeDef SDIO_InitCard(SDIO_HandleTypeDef *hsdio); static HAL_StatusTypeDef SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, uint32_t addr, uint32_t raw, uint32_t function_nbr, uint8_t *pData); static HAL_StatusTypeDef SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, uint32_t addr, uint32_t raw, uint32_t function_nbr, - uint8_t *pData); + const uint8_t *pData); static HAL_StatusTypeDef SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *cmd_arg, uint8_t *pData, uint16_t Size_byte); -static uint8_t SDIO_Convert_Block_Size(SDIO_HandleTypeDef *hsdio, uint32_t block_size); +static uint8_t SDIO_Convert_Block_Size(const SDIO_HandleTypeDef *hsdio, uint32_t block_size); static HAL_StatusTypeDef SDIO_IOFunction_IRQHandler(SDIO_HandleTypeDef *hsdio); /** * @} @@ -362,7 +362,18 @@ HAL_StatusTypeDef HAL_SDIO_Init(SDIO_HandleTypeDef *hsdio) Init.BusWide = SDMMC_BUS_WIDE_1B; Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; - sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC); + if (hsdio->Instance == SDMMC1) + { + sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC1); + } + else if (hsdio->Instance == SDMMC2) + { + sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC2); + } + else + { + sdmmc_clk = 0; + } if (sdmmc_clk == 0U) { hsdio->ErrorCode = SDMMC_ERROR_INVALID_PARAMETER; @@ -558,7 +569,16 @@ HAL_StatusTypeDef HAL_SDIO_ConfigFrequency(SDIO_HandleTypeDef *hsdio, uint32_t C if (hsdio->State == HAL_SDIO_STATE_READY) { - ClockDiv = (HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC)) / (2U * ClockSpeed); + if (hsdio->Instance == SDMMC1) + { + ClockDiv = (HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC1)) / (2U * ClockSpeed); + } +#if defined(SDMMC2) + if (hsdio->Instance == SDMMC2) + { + ClockDiv = (HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC2)) / (2U * ClockSpeed); + } +#endif /* SDMMC2 */ MODIFY_REG(hsdio->Instance->CLKCR, SDMMC_CLKCR_CLKDIV, ClockDiv); } else @@ -805,7 +825,8 @@ HAL_StatusTypeDef HAL_SDIO_GetCardFBRRegister(SDIO_HandleTypeDef *hsdio, HAL_SDI * @param pData: pointer to the buffer that will contain the received data. * @retval HAL status */ -HAL_StatusTypeDef HAL_SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, HAL_SDIO_DirectCmd_TypeDef *Argument, uint8_t *pData) +HAL_StatusTypeDef HAL_SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_DirectCmd_TypeDef *Argument, + uint8_t *pData) { uint32_t cmd; uint32_t errorstate; @@ -870,7 +891,8 @@ HAL_StatusTypeDef HAL_SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, HAL_SDIO_Direct * @param Data: pointer to the buffer that will contain the received data. * @retval HAL status */ -HAL_StatusTypeDef HAL_SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, HAL_SDIO_DirectCmd_TypeDef *Argument, uint8_t Data) +HAL_StatusTypeDef HAL_SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_DirectCmd_TypeDef *Argument, + uint8_t Data) { uint32_t cmd; uint32_t errorstate; @@ -934,7 +956,7 @@ HAL_StatusTypeDef HAL_SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, HAL_SDIO_Direc * @param Timeout_Ms: Specify timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_SDIO_ReadExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, +HAL_StatusTypeDef HAL_SDIO_ReadExtended(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_ExtendedCmd_TypeDef *Argument, uint8_t *pData, uint32_t Size_byte, uint32_t Timeout_Ms) { uint32_t cmd; @@ -1032,10 +1054,10 @@ HAL_StatusTypeDef HAL_SDIO_ReadExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_Exte while (!__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) { - if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= 32U)) + if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= SDMMC_FIFO_SIZE)) { /* Read data from SDMMC Rx FIFO */ - for (regCount = 0U; regCount < 8U; regCount++) + for (regCount = 0U; regCount < (SDMMC_FIFO_SIZE / 4U); regCount++) { data = SDMMC_ReadFIFO(hsdio->Instance); *tempbuff = (uint8_t)(data & 0xFFU); @@ -1047,11 +1069,11 @@ HAL_StatusTypeDef HAL_SDIO_ReadExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_Exte *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); tempbuff++; } - dataremaining -= 32U; + dataremaining -= SDMMC_FIFO_SIZE; } - else if (dataremaining < 32U) + else if (dataremaining < SDMMC_FIFO_SIZE) { - while ((dataremaining > 0U) && !(__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_RXFIFOE))) + while (!(__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_RXFIFOE)) && (dataremaining > 0U)) { data = SDMMC_ReadFIFO(hsdio->Instance); for (byteCount = 0U; byteCount < 4U; byteCount++) @@ -1143,7 +1165,7 @@ HAL_StatusTypeDef HAL_SDIO_ReadExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_Exte * @param Timeout_Ms: Specify timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, +HAL_StatusTypeDef HAL_SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_ExtendedCmd_TypeDef *Argument, uint8_t *pData, uint32_t Size_byte, uint32_t Timeout_Ms) { uint32_t cmd; @@ -1236,19 +1258,20 @@ HAL_StatusTypeDef HAL_SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_Ext SDMMC_FLAG_DATAEND)) { - if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U)) + if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= SDMMC_FIFO_SIZE)) { /* Read data from SDMMC Rx FIFO */ - for (regCount = 0U; regCount < 8U; regCount++) + for (regCount = 0U; regCount < (SDMMC_FIFO_SIZE / 4U); regCount++) { hsdio->Instance->FIFO = *u32tempbuff; u32tempbuff++; } - dataremaining -= 32U; + dataremaining -= SDMMC_FIFO_SIZE; } - else if ((dataremaining < 32U) && (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXFIFOHE | SDMMC_FLAG_TXFIFOE))) + else if ((__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXFIFOHE | SDMMC_FLAG_TXFIFOE)) && + (dataremaining < SDMMC_FIFO_SIZE)) { - uint8_t *u8buff = (uint8_t *)u32tempbuff; + const uint8_t *u8buff = (uint8_t *)u32tempbuff; while (dataremaining > 0U) { data = 0U; @@ -1335,7 +1358,7 @@ HAL_StatusTypeDef HAL_SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_Ext * @param Size_byte: Block size to write. * @retval HAL status */ -HAL_StatusTypeDef HAL_SDIO_ReadExtended_DMA(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, +HAL_StatusTypeDef HAL_SDIO_ReadExtended_DMA(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_ExtendedCmd_TypeDef *Argument, uint8_t *pData, uint32_t Size_byte) { SDMMC_DataInitTypeDef config; @@ -1467,7 +1490,7 @@ HAL_StatusTypeDef HAL_SDIO_ReadExtended_DMA(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ * @param Size_byte: Block size to write. * @retval HAL status */ -HAL_StatusTypeDef HAL_SDIO_WriteExtended_DMA(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, +HAL_StatusTypeDef HAL_SDIO_WriteExtended_DMA(SDIO_HandleTypeDef *hsdio, const HAL_SDIO_ExtendedCmd_TypeDef *Argument, uint8_t *pData, uint32_t Size_byte) { uint32_t cmd; @@ -2606,7 +2629,7 @@ static HAL_StatusTypeDef SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, uint32_t add * @retval HAL status */ static HAL_StatusTypeDef SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, uint32_t addr, uint32_t raw, - uint32_t function_nbr, uint8_t *pData) + uint32_t function_nbr, const uint8_t *pData) { uint32_t errorstate; uint32_t cmd; @@ -2719,18 +2742,20 @@ static HAL_StatusTypeDef SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ while (!__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) { - if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U)) + if (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXFIFOHE) && + (dataremaining >= SDMMC_FIFO_SIZE)) { - for (regCount = 8U; regCount > 0U; regCount--) + for (regCount = SDMMC_FIFO_SIZE / 4U; regCount > 0U; regCount--) { SDMMCx->FIFO = *u32tempbuff; u32tempbuff++; } - dataremaining -= 32U; + dataremaining -= SDMMC_FIFO_SIZE; } - else if ((dataremaining < 32U) && (__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXFIFOHE | SDMMC_FLAG_TXFIFOE))) + else if ((__HAL_SDIO_GET_FLAG(hsdio, SDMMC_FLAG_TXFIFOHE | SDMMC_FLAG_TXFIFOE)) && + (dataremaining < SDMMC_FIFO_SIZE)) { - uint8_t *u8buff = (uint8_t *)u32tempbuff; + const uint8_t *u8buff = (uint8_t *)u32tempbuff; while (dataremaining > 0U) { data = 0U; @@ -2801,7 +2826,7 @@ static HAL_StatusTypeDef SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ * @param block_size: block size in bytes * @retval block size as DBLOCKSIZE[3:0] bits format */ -static uint8_t SDIO_Convert_Block_Size(SDIO_HandleTypeDef *hsdio, uint32_t block_size) +static uint8_t SDIO_Convert_Block_Size(const SDIO_HandleTypeDef *hsdio, uint32_t block_size) { UNUSED(hsdio); diff --git a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_tim.c b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_tim.c index 8c47784..af7fd52 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_tim.c +++ b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_tim.c @@ -7253,8 +7253,6 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); - TIMx->CR1 = tmpcr1; - /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; @@ -7267,16 +7265,15 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure TIMx->RCR = Structure->RepetitionCounter; } + /* Disable Update Event (UEV) with Update Generation (UG) + by changing Update Request Source (URS) to avoid Update flag (UIF) */ + SET_BIT(TIMx->CR1, TIM_CR1_URS); + /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; - /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ - if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) - { - /* Clear the update flag */ - CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); - } + TIMx->CR1 = tmpcr1; } /** diff --git a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_timebase_tim_template.c b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_timebase_tim_template.c index 8982932..1c11778 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_timebase_tim_template.c +++ b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_timebase_tim_template.c @@ -1,6 +1,6 @@ /** ****************************************************************************** - * @file stm32wbaxx_hal_timebase_tim_template.c + * @file stm32n6xx_hal_timebase_tim_template.c * @author MCD Application Team * @brief HAL time base based on the hardware TIM. * @@ -70,30 +70,15 @@ void TimeBase_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); */ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { - RCC_ClkInitTypeDef clkconfig; uint32_t uwTimclock; - uint32_t uwAPB1Prescaler; uint32_t uwPrescalerValue; HAL_StatusTypeDef Status; /* Enable TIM2 clock */ __HAL_RCC_TIM2_CLK_ENABLE(); - /* Get clock configuration */ - HAL_RCC_GetClockConfig(&clkconfig); - - /* Get APB1 prescaler */ - uwAPB1Prescaler = clkconfig.APB1CLKDivider; - /* Compute TIM2 clock */ - if (uwAPB1Prescaler == RCC_HCLK_DIV1) - { - uwTimclock = HAL_RCC_GetPCLK1Freq(); - } - else - { - uwTimclock = 2UL * HAL_RCC_GetPCLK1Freq(); - } + uwTimclock = HAL_RCCEx_GetTIMGFreq(); /* Compute the prescaler value to have TIM2 counter clock equal to TIM_CNT_FREQ */ uwPrescalerValue = (uint32_t)((uwTimclock / TIM_CNT_FREQ) - 1U); diff --git a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_uart.c b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_uart.c index afe1ae9..364d8dc 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_uart.c +++ b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_uart.c @@ -1024,75 +1024,79 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) =============================================================================== ##### IO operation functions ##### =============================================================================== + [..] This subsection provides a set of functions allowing to manage the UART asynchronous and Half duplex data transfers. - (#) There are two mode of transfer: - (+) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (+) Non-Blocking mode: The communication is performed using Interrupts - or DMA, These API's return the HAL status. - The end of the data processing will be indicated through the - dedicated UART IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks - will be executed respectively at the end of the transmit or Receive process - The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) Non-Blocking mode: The communication is performed using Interrupts + or DMA, These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process + The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected (#) Blocking mode API's are : - (+) HAL_UART_Transmit() - (+) HAL_UART_Receive() + (++) HAL_UART_Transmit() + (++) HAL_UART_Receive() (#) Non-Blocking mode API's with Interrupt are : - (+) HAL_UART_Transmit_IT() - (+) HAL_UART_Receive_IT() - (+) HAL_UART_IRQHandler() + (++) HAL_UART_Transmit_IT() + (++) HAL_UART_Receive_IT() + (++) HAL_UART_IRQHandler() (#) Non-Blocking mode API's with DMA are : - (+) HAL_UART_Transmit_DMA() - (+) HAL_UART_Receive_DMA() - (+) HAL_UART_DMAPause() - (+) HAL_UART_DMAResume() - (+) HAL_UART_DMAStop() + (++) HAL_UART_Transmit_DMA() + (++) HAL_UART_Receive_DMA() + (++) HAL_UART_DMAPause() + (++) HAL_UART_DMAResume() + (++) HAL_UART_DMAStop() (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: - (+) HAL_UART_TxHalfCpltCallback() - (+) HAL_UART_TxCpltCallback() - (+) HAL_UART_RxHalfCpltCallback() - (+) HAL_UART_RxCpltCallback() - (+) HAL_UART_ErrorCallback() + (++) HAL_UART_TxHalfCpltCallback() + (++) HAL_UART_TxCpltCallback() + (++) HAL_UART_RxHalfCpltCallback() + (++) HAL_UART_RxCpltCallback() + (++) HAL_UART_ErrorCallback() (#) Non-Blocking mode transfers could be aborted using Abort API's : - (+) HAL_UART_Abort() - (+) HAL_UART_AbortTransmit() - (+) HAL_UART_AbortReceive() - (+) HAL_UART_Abort_IT() - (+) HAL_UART_AbortTransmit_IT() - (+) HAL_UART_AbortReceive_IT() + (++) HAL_UART_Abort() + (++) HAL_UART_AbortTransmit() + (++) HAL_UART_AbortReceive() + (++) HAL_UART_Abort_IT() + (++) HAL_UART_AbortTransmit_IT() + (++) HAL_UART_AbortReceive_IT() (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided: - (+) HAL_UART_AbortCpltCallback() - (+) HAL_UART_AbortTransmitCpltCallback() - (+) HAL_UART_AbortReceiveCpltCallback() + (++) HAL_UART_AbortCpltCallback() + (++) HAL_UART_AbortTransmitCpltCallback() + (++) HAL_UART_AbortReceiveCpltCallback() (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced reception services: - (+) HAL_UARTEx_RxEventCallback() + (++) HAL_UARTEx_RxEventCallback() + + (#) Wakeup from Stop mode Callback: + (++) HAL_UARTEx_WakeupCallback() (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : - (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error - in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user - to identify error type, and HAL_UART_ErrorCallback() user callback is executed. - Transfer is kept ongoing on UART side. - If user wants to abort it, Abort services should be called by user. - (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. - This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() - user callback is executed. + (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error + in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user + to identify error type, and HAL_UART_ErrorCallback() user callback is executed. + Transfer is kept ongoing on UART side. + If user wants to abort it, Abort services should be called by user. + (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() + user callback is executed. -@- In the Half duplex communication, it is forbidden to run the transmit and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. @@ -3804,12 +3808,24 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { + huart->RxXferCount = 0; + + /* Check current nb of data still to be received on DMA side. + DMA Normal mode, remaining nb of data will be 0 + DMA Circular mode, remaining nb of data is reset to RxXferSize */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma); + if (nb_remaining_rx_data < huart->RxXferSize) + { + /* Update nb of remaining data */ + huart->RxXferCount = nb_remaining_rx_data; + } + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, huart->RxXferSize); + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } else @@ -3842,12 +3858,22 @@ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { + huart->RxXferCount = huart->RxXferSize / 2U; + + /* Check current nb of data still to be received on DMA side. */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma); + if (nb_remaining_rx_data <= huart->RxXferSize) + { + /* Update nb of remaining data */ + huart->RxXferCount = nb_remaining_rx_data; + } + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, huart->RxXferSize / 2U); + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U); + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } else diff --git a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_uart_ex.c b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_uart_ex.c index f6b608e..a1ed651 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_uart_ex.c +++ b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_uart_ex.c @@ -24,7 +24,7 @@ ============================================================================== ##### UART peripheral extended features ##### ============================================================================== - + [..] (#) Declare a UART_HandleTypeDef handle structure. (#) For the UART RS485 Driver Enable mode, initialize the UART registers @@ -253,15 +253,13 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, =============================================================================== ##### IO operation functions ##### =============================================================================== + [..] This subsection provides a set of Wakeup and FIFO mode related callback functions. - (#) Wakeup from Stop mode Callback: - (+) HAL_UARTEx_WakeupCallback() - + (++) HAL_UARTEx_WakeupCallback() (#) TX/RX Fifos Callbacks: - (+) HAL_UARTEx_RxFifoFullCallback() - (+) HAL_UARTEx_TxFifoEmptyCallback() - + (++) HAL_UARTEx_RxFifoFullCallback() + (++) HAL_UARTEx_TxFifoEmptyCallback() @endverbatim * @{ */ @@ -341,19 +339,19 @@ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) (#) Compared to standard reception services which only consider number of received data elements as reception completion criteria, these functions also consider additional events as triggers for updating reception status to caller : - (+) Detection of inactivity period (RX line has not been active for a given period). - (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state) + (++) Detection of inactivity period (RX line has not been active for a given period). + (+++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state) for 1 frame time, after last received byte. - (++) RX inactivity detected by RTO, i.e. line has been in idle state + (+++) RX inactivity detected by RTO, i.e. line has been in idle state for a programmable time, after last received byte. - (+) Detection that a specific character has been received. + (++) Detection that a specific character has been received. - (#) There are two mode of transfer: - (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received, + (#) There are two modes of transfer: + (++) Blocking mode: The reception is performed in polling mode, until either expected number of data is received, or till IDLE event occurs. Reception is handled only during function execution. When function exits, no data reception could occur. HAL status and number of actually received data elements, are returned by function after finishing transfer. - (+) Non-Blocking mode: The reception is performed using Interrupts or DMA. + (++) Non-Blocking mode: The reception is performed using Interrupts or DMA. These API's return the HAL status. The end of the data processing will be indicated through the dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. @@ -361,13 +359,13 @@ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected. (#) Blocking mode API: - (+) HAL_UARTEx_ReceiveToIdle() + (++) HAL_UARTEx_ReceiveToIdle() (#) Non-Blocking mode API with Interrupt: - (+) HAL_UARTEx_ReceiveToIdle_IT() + (++) HAL_UARTEx_ReceiveToIdle_IT() (#) Non-Blocking mode API with DMA: - (+) HAL_UARTEx_ReceiveToIdle_DMA() + (++) HAL_UARTEx_ReceiveToIdle_DMA() @endverbatim * @{ @@ -944,17 +942,15 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_ * Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead * to Rx Event callback execution. * @note This function is expected to be called within the user implementation of Rx Event Callback, - * in order to provide the accurate value : - * In Interrupt Mode : - * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) - * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of - * received data is lower than expected one) - * In DMA Mode : - * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) - * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received - * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of - * received data is lower than expected one). - * In DMA mode, RxEvent callback could be called several times; + * in order to provide the accurate value. + * @note In Interrupt Mode: + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received). + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed. + * @note In DMA Mode: + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received). + * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received. + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed. + * @note In DMA mode, RxEvent callback could be called several times; * When DMA is configured in Normal Mode, HT event does not stop Reception process; * When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process; * @param huart UART handle. diff --git a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_xspi.c b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_xspi.c index a7fad61..4f9b595 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_xspi.c +++ b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_xspi.c @@ -302,8 +302,8 @@ static void XSPI_DMAError(DMA_HandleTypeDef *hdma); static void XSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef XSPI_WaitFlagStateUntilTimeout(XSPI_HandleTypeDef *hxspi, uint32_t Flag, FlagStatus State, uint32_t Tickstart, uint32_t Timeout); -static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pCmd); -static void XSPIM_GetConfig(uint8_t instance_nb, XSPIM_CfgTypeDef *const pCfg); +static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, const XSPI_RegularCmdTypeDef *pCmd); +static void XSPIM_GetConfig(uint8_t instance_nb, XSPIM_CfgTypeDef *pCfg); /** @endcond */ @@ -359,7 +359,6 @@ HAL_StatusTypeDef HAL_XSPI_Init(XSPI_HandleTypeDef *hxspi) assert_param(IS_XSPI_WRAP_SIZE(hxspi->Init.WrapSize)); assert_param(IS_XSPI_CLK_PRESCALER(hxspi->Init.ClockPrescaler)); assert_param(IS_XSPI_SAMPLE_SHIFTING(hxspi->Init.SampleShifting)); - assert_param(IS_XSPI_DHQC(hxspi->Init.DelayHoldQuarterCycle)); assert_param(IS_XSPI_CS_BOUND(hxspi->Init.ChipSelectBoundary)); assert_param(IS_XSPI_FIFO_THRESHOLD_BYTE(hxspi->Init.FifoThresholdByte)); assert_param(IS_XSPI_MAXTRAN(hxspi->Init.MaxTran)); @@ -444,9 +443,8 @@ HAL_StatusTypeDef HAL_XSPI_Init(XSPI_HandleTypeDef *hxspi) MODIFY_REG(hxspi->Instance->CR, (XSPI_CR_DMM | XSPI_CR_CSSEL), (hxspi->Init.MemoryMode | hxspi->Init.MemorySelect)); - /* Configure sample shifting and delay hold quarter cycle */ - MODIFY_REG(hxspi->Instance->TCR, (XSPI_TCR_SSHIFT | XSPI_TCR_DHQC), - (hxspi->Init.SampleShifting | hxspi->Init.DelayHoldQuarterCycle)); + /* Configure sample shifting */ + MODIFY_REG(hxspi->Instance->TCR, (XSPI_TCR_SSHIFT), hxspi->Init.SampleShifting); /* Enable XSPI */ HAL_XSPI_ENABLE(hxspi); @@ -820,7 +818,7 @@ void HAL_XSPI_IRQHandler(XSPI_HandleTypeDef *hxspi) * @param Timeout : Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_XSPI_Command(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pCmd, uint32_t Timeout) +HAL_StatusTypeDef HAL_XSPI_Command(XSPI_HandleTypeDef *hxspi, const XSPI_RegularCmdTypeDef *pCmd, uint32_t Timeout) { HAL_StatusTypeDef status; uint32_t state; @@ -893,9 +891,10 @@ HAL_StatusTypeDef HAL_XSPI_Command(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTyp if (pCmd->DataMode == HAL_XSPI_DATA_NONE) { /* When there is no data phase, the transfer start as soon as the configuration is done - so wait until TC flag is set to go back in idle state */ - status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_TC, SET, tickstart, Timeout); + so wait until BUSY flag is reset to go back in idle state. */ + status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, Timeout); + /* Clear TC flag */ HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); } else @@ -955,7 +954,7 @@ HAL_StatusTypeDef HAL_XSPI_Command(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTyp * @note This function is used only in Indirect Read or Write Modes * @retval HAL status */ -HAL_StatusTypeDef HAL_XSPI_Command_IT(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pCmd) +HAL_StatusTypeDef HAL_XSPI_Command_IT(XSPI_HandleTypeDef *hxspi, const XSPI_RegularCmdTypeDef *pCmd) { HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); @@ -1044,7 +1043,7 @@ HAL_StatusTypeDef HAL_XSPI_Command_IT(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmd * @param Timeout : Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_XSPI_HyperbusCfg(XSPI_HandleTypeDef *hxspi, XSPI_HyperbusCfgTypeDef *const pCfg, +HAL_StatusTypeDef HAL_XSPI_HyperbusCfg(XSPI_HandleTypeDef *hxspi, const XSPI_HyperbusCfgTypeDef *pCfg, uint32_t Timeout) { HAL_StatusTypeDef status; @@ -1095,7 +1094,7 @@ HAL_StatusTypeDef HAL_XSPI_HyperbusCfg(XSPI_HandleTypeDef *hxspi, XSPI_HyperbusC * @param Timeout : Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_XSPI_HyperbusCmd(XSPI_HandleTypeDef *hxspi, XSPI_HyperbusCmdTypeDef *const pCmd, +HAL_StatusTypeDef HAL_XSPI_HyperbusCmd(XSPI_HandleTypeDef *hxspi, const XSPI_HyperbusCmdTypeDef *pCmd, uint32_t Timeout) { HAL_StatusTypeDef status; @@ -1234,7 +1233,7 @@ HAL_StatusTypeDef HAL_XSPI_Transmit(XSPI_HandleTypeDef *hxspi, const uint8_t *pD * @note This function is used only in Indirect Read Mode * @retval HAL status */ -HAL_StatusTypeDef HAL_XSPI_Receive(XSPI_HandleTypeDef *hxspi, uint8_t *const pData, uint32_t Timeout) +HAL_StatusTypeDef HAL_XSPI_Receive(XSPI_HandleTypeDef *hxspi, uint8_t *pData, uint32_t Timeout) { HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); @@ -1373,7 +1372,7 @@ HAL_StatusTypeDef HAL_XSPI_Transmit_IT(XSPI_HandleTypeDef *hxspi, const uint8_t * @note This function is used only in Indirect Read Mode * @retval HAL status */ -HAL_StatusTypeDef HAL_XSPI_Receive_IT(XSPI_HandleTypeDef *hxspi, uint8_t *const pData) +HAL_StatusTypeDef HAL_XSPI_Receive_IT(XSPI_HandleTypeDef *hxspi, uint8_t *pData) { HAL_StatusTypeDef status = HAL_OK; uint32_t addr_reg = hxspi->Instance->AR; @@ -1628,7 +1627,7 @@ HAL_StatusTypeDef HAL_XSPI_Transmit_DMA(XSPI_HandleTypeDef *hxspi, const uint8_t * of data and the fifo threshold should be aligned on word * @retval HAL status */ -HAL_StatusTypeDef HAL_XSPI_Receive_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *const pData) +HAL_StatusTypeDef HAL_XSPI_Receive_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *pData) { HAL_StatusTypeDef status = HAL_OK; uint32_t data_size = hxspi->Instance->DLR + 1U; @@ -1828,7 +1827,7 @@ HAL_StatusTypeDef HAL_XSPI_Receive_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *const * @note This function is used only in Automatic Polling Mode * @retval HAL status */ -HAL_StatusTypeDef HAL_XSPI_AutoPolling(XSPI_HandleTypeDef *hxspi, XSPI_AutoPollingTypeDef *const pCfg, +HAL_StatusTypeDef HAL_XSPI_AutoPolling(XSPI_HandleTypeDef *hxspi, const XSPI_AutoPollingTypeDef *pCfg, uint32_t Timeout) { HAL_StatusTypeDef status; @@ -1909,7 +1908,7 @@ HAL_StatusTypeDef HAL_XSPI_AutoPolling(XSPI_HandleTypeDef *hxspi, XSPI_AutoPolli * @note This function is used only in Automatic Polling Mode * @retval HAL status */ -HAL_StatusTypeDef HAL_XSPI_AutoPolling_IT(XSPI_HandleTypeDef *hxspi, XSPI_AutoPollingTypeDef *const pCfg) +HAL_StatusTypeDef HAL_XSPI_AutoPolling_IT(XSPI_HandleTypeDef *hxspi, const XSPI_AutoPollingTypeDef *pCfg) { HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); @@ -1982,7 +1981,7 @@ HAL_StatusTypeDef HAL_XSPI_AutoPolling_IT(XSPI_HandleTypeDef *hxspi, XSPI_AutoPo * @note This function is used only in Memory mapped Mode * @retval HAL status */ -HAL_StatusTypeDef HAL_XSPI_MemoryMapped(XSPI_HandleTypeDef *hxspi, XSPI_MemoryMappedTypeDef *const pCfg) +HAL_StatusTypeDef HAL_XSPI_MemoryMapped(XSPI_HandleTypeDef *hxspi, const XSPI_MemoryMappedTypeDef *pCfg) { HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); @@ -2782,7 +2781,7 @@ uint32_t HAL_XSPI_GetState(const XSPI_HandleTypeDef *hxspi) * @param Timeout : Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_XSPIM_Config(XSPI_HandleTypeDef *const hxspi, XSPIM_CfgTypeDef *const pCfg, uint32_t Timeout) +HAL_StatusTypeDef HAL_XSPIM_Config(XSPI_HandleTypeDef *hxspi, const XSPIM_CfgTypeDef *pCfg, uint32_t Timeout) { HAL_StatusTypeDef status = HAL_OK; uint8_t index; @@ -2948,7 +2947,7 @@ HAL_StatusTypeDef HAL_XSPIM_Config(XSPI_HandleTypeDef *const hxspi, XSPIM_CfgTyp * @param pCfg : Current delay values corresponding to the DelayValueType field. * @retval HAL status */ -HAL_StatusTypeDef HAL_XSPI_GetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSCalTypeDef *const pCfg) +HAL_StatusTypeDef HAL_XSPI_GetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSCalTypeDef *pCfg) { HAL_StatusTypeDef status = HAL_OK; __IO uint32_t reg = 0; @@ -3000,7 +2999,7 @@ HAL_StatusTypeDef HAL_XSPI_GetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSCalTy * @param pCfg : Configuration of delay value specified in DelayValueType field. * @retval HAL status */ -HAL_StatusTypeDef HAL_XSPI_SetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSCalTypeDef *const pCfg) +HAL_StatusTypeDef HAL_XSPI_SetDelayValue(XSPI_HandleTypeDef *hxspi, const XSPI_HSCalTypeDef *pCfg) { HAL_StatusTypeDef status = HAL_OK; @@ -3219,7 +3218,7 @@ static HAL_StatusTypeDef XSPI_WaitFlagStateUntilTimeout(XSPI_HandleTypeDef *hxsp * @param pCmd : structure that contains the command configuration information * @retval HAL status */ -static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *pCmd) +static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, const XSPI_RegularCmdTypeDef *pCmd) { HAL_StatusTypeDef status = HAL_OK; __IO uint32_t *ccr_reg; @@ -3328,9 +3327,8 @@ static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, XSPI_RegularC (pCmd->InstructionMode | pCmd->InstructionDTRMode | pCmd->InstructionWidth | pCmd->AddressMode | pCmd->AddressDTRMode | pCmd->AddressWidth)); - /* The DHQC bit is linked with DDTR bit which should be activated */ - if ((hxspi->Init.DelayHoldQuarterCycle == HAL_XSPI_DHQC_ENABLE) && - (pCmd->InstructionDTRMode == HAL_XSPI_INSTRUCTION_DTR_ENABLE)) + /* DDTR bit should be activated */ + if (pCmd->InstructionDTRMode == HAL_XSPI_INSTRUCTION_DTR_ENABLE) { MODIFY_REG((*ccr_reg), XSPI_CCR_DDTR, HAL_XSPI_DATA_DTR_ENABLE); } @@ -3340,6 +3338,12 @@ static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, XSPI_RegularC /* Configure the AR register with the address value */ hxspi->Instance->AR = pCmd->Address; + + if (pCmd->OperationType == HAL_XSPI_OPTYPE_COMMON_CFG) + { + /* Verify if programmed address fit with requirement of Reference Manual 28.5 chapter */ + assert_param(IS_XSPI_PROG_ADDR(hxspi->Instance->AR, pCmd->Address)); + } } else { @@ -3361,9 +3365,8 @@ static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, XSPI_RegularC MODIFY_REG((*ccr_reg), (XSPI_CCR_IMODE | XSPI_CCR_IDTR | XSPI_CCR_ISIZE), (pCmd->InstructionMode | pCmd->InstructionDTRMode | pCmd->InstructionWidth)); - /* The DHQC bit is linked with DDTR bit which should be activated */ - if ((hxspi->Init.DelayHoldQuarterCycle == HAL_XSPI_DHQC_ENABLE) && - (pCmd->InstructionDTRMode == HAL_XSPI_INSTRUCTION_DTR_ENABLE)) + /* DDTR bit should be activated */ + if (pCmd->InstructionDTRMode == HAL_XSPI_INSTRUCTION_DTR_ENABLE) { MODIFY_REG((*ccr_reg), XSPI_CCR_DDTR, HAL_XSPI_DATA_DTR_ENABLE); } @@ -3399,6 +3402,12 @@ static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, XSPI_RegularC /* Configure the AR register with the instruction value */ hxspi->Instance->AR = pCmd->Address; + + if (pCmd->OperationType == HAL_XSPI_OPTYPE_COMMON_CFG) + { + /* Verify if programmed address fit with requirement of Reference Manual 28.5 chapter */ + assert_param(IS_XSPI_PROG_ADDR(hxspi->Instance->AR, pCmd->Address)); + } } else { @@ -3408,6 +3417,18 @@ static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, XSPI_RegularC } } + if (pCmd->DataMode != HAL_XSPI_DATA_NONE) + { + if (pCmd->OperationType == HAL_XSPI_OPTYPE_COMMON_CFG) + { + /* Configure the DLR register with the number of data */ + hxspi->Instance->DLR = (pCmd->DataLength - 1U); + + /* Verify if programmed data fit with requirement of Reference Manual 28.5 chapter */ + assert_param(IS_XSPI_PROG_DATA(hxspi->Instance->DLR, (pCmd->DataLength - 1U))); + } + } + return status; } @@ -3417,7 +3438,7 @@ static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, XSPI_RegularC * @param pCfg : configuration of the IO Manager for the instance * @retval HAL status */ -static void XSPIM_GetConfig(uint8_t instance_nb, XSPIM_CfgTypeDef *const pCfg) +static void XSPIM_GetConfig(uint8_t instance_nb, XSPIM_CfgTypeDef *pCfg) { uint32_t mux; uint32_t mode; diff --git a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_ll_fmc.c b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_ll_fmc.c index c1e8035..8fb760e 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_ll_fmc.c +++ b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_ll_fmc.c @@ -345,7 +345,7 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_CFGR_CCLKEN)) { - tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos)); + tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FUL) << FMC_BTRx_CLKDIV_Pos)); tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos); MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr); } diff --git a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_ll_rcc.c b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_ll_rcc.c index 44850dd..3a9e360 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_ll_rcc.c +++ b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_ll_rcc.c @@ -38,18 +38,6 @@ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ -/** @addtogroup RCC_LL_Private_Constants - * @{ - */ -#if defined(USE_FPGA) -/* ***** FPGA values ******/ -#define FREF_FREQ 32000000UL /* FREF forced to 32MHz */ -#define PLL_SOURCE_FREQ 32000000UL /* PLL source forced to 32MHz */ -#endif /* USE_FPGA */ -/** - * @} - */ - /* Private macros ------------------------------------------------------------*/ /** @addtogroup RCC_LL_Private_Macros * @{ @@ -527,10 +515,6 @@ uint32_t LL_RCC_GetPLL1ClockFreq(void) if (pllinputfreq != LL_RCC_PERIPH_FREQUENCY_NO) { -#if defined(USE_FPGA) - /**** FPGA PLL input forced to 32MHz *****/ - pllinputfreq = PLL_SOURCE_FREQ; -#endif /* USE_FPGA */ /* INTEGER mode only - others TO DO */ divm = LL_RCC_PLL1_GetM(); @@ -601,10 +585,6 @@ uint32_t LL_RCC_GetPLL2ClockFreq(void) if (pllinputfreq != LL_RCC_PERIPH_FREQUENCY_NO) { -#if defined(USE_FPGA) - /**** FPGA PLL input forced to 32MHz *****/ - pllinputfreq = PLL_SOURCE_FREQ; -#endif /* USE_FPGA */ /* INTEGER mode only - others TO DO */ divm = LL_RCC_PLL2_GetM(); @@ -675,10 +655,6 @@ uint32_t LL_RCC_GetPLL3ClockFreq(void) if (pllinputfreq != LL_RCC_PERIPH_FREQUENCY_NO) { -#if defined(USE_FPGA) - /**** FPGA PLL input forced to 32MHz *****/ - pllinputfreq = PLL_SOURCE_FREQ; -#endif /* USE_FPGA */ /* INTEGER mode only - others TO DO */ divm = LL_RCC_PLL3_GetM(); @@ -749,10 +725,6 @@ uint32_t LL_RCC_GetPLL4ClockFreq(void) if (pllinputfreq != LL_RCC_PERIPH_FREQUENCY_NO) { -#if defined(USE_FPGA) - /**** FPGA PLL input forced to 32MHz *****/ - pllinputfreq = PLL_SOURCE_FREQ; -#endif /* USE_FPGA */ /* INTEGER mode only - others TO DO */ divm = LL_RCC_PLL4_GetM(); diff --git a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_ll_usb.c b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_ll_usb.c index b03daa3..d91a0b3 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_ll_usb.c +++ b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_ll_usb.c @@ -100,7 +100,8 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c if (cfg.dma_enable == 1U) { - USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2; + USBx->GAHBCFG &= ~(USB_OTG_GAHBCFG_HBSTLEN); + USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_INCR4; USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN; } @@ -545,6 +546,7 @@ uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx) return speed; } +#if defined (HAL_PCD_MODULE_ENABLED) /** * @brief Activate and configure an endpoint * @param USBx Selected device @@ -730,7 +732,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef if (ep->xfer_len == 0U) { USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1UL << 19)); USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); } else @@ -750,7 +752,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef ep->xfer_len = ep->maxpacket; } - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1UL << 19)); } else { @@ -776,7 +778,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef if (ep->type == EP_TYPE_ISOC) { - if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) + if ((USBx_DEVICE->DSTS & (1UL << 8)) == 0U) { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; } @@ -804,7 +806,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef } else { - if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) + if ((USBx_DEVICE->DSTS & (1UL << 8)) == 0U) { USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; } @@ -837,14 +839,14 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef ep->xfer_size = ep->maxpacket; USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size); - USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1UL << 19)); } else { if (ep->xfer_len == 0U) { USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); - USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1UL << 19)); } else { @@ -866,7 +868,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef if (ep->type == EP_TYPE_ISOC) { - if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) + if ((USBx_DEVICE->DSTS & (1UL << 8)) == 0U) { USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; } @@ -889,11 +891,13 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef * @param ep pointer to endpoint structure * @retval HAL status */ -HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { __IO uint32_t count = 0U; HAL_StatusTypeDef ret = HAL_OK; uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t dma_enable = (USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) >> 0x5U; + uint32_t RegVal; /* IN endpoint */ if (ep->is_in == 1U) @@ -908,37 +912,145 @@ HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTy { count++; - if (count > 10000U) + if (count > 0xF0000U) { ret = HAL_ERROR; break; } - } while (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA); + } while (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA); } } else /* OUT endpoint */ { - if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + USBx->GINTMSK &= ~USB_OTG_GINTMSK_GONAKEFFM; + + if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == 0U) { - USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK); - USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS); + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SGONAK; + } + if (dma_enable == 0U) + { do { count++; - if (count > 10000U) + if (count > 0xF0000U) { ret = HAL_ERROR; break; } - } while (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA); + } while (((USBx->GINTSTS & USB_OTG_GINTSTS_RXFLVL) & USB_OTG_GINTSTS_RXFLVL) != USB_OTG_GINTSTS_RXFLVL); + + /* POP the RX status register to generate the NAK Effective interrupt */ + RegVal = USBx->GRXSTSP; + UNUSED(RegVal); } + + /* Wait for Global NAK effective to be set */ + count = 0U; + + do + { + count++; + + if (count > 0xF0000U) + { + ret = HAL_ERROR; + break; + } + } while (((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) + & USB_OTG_GINTSTS_BOUTNAKEFF) != USB_OTG_GINTSTS_BOUTNAKEFF); + + USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK); + USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS); + + /* Wait for EP disable to take effect */ + count = 0U; + + do + { + count++; + + if (count > 0xF0000U) + { + ret = HAL_ERROR; + break; + } + } while (((USBx_OUTEP(ep->num)->DOEPINT & USB_OTG_DOEPINT_EPDISD) + & USB_OTG_DOEPINT_EPDISD) != USB_OTG_DOEPINT_EPDISD); + + /* Clear OUT EP disable interrupt */ + USBx_OUTEP(ep->num)->DOEPINT |= USB_OTG_DOEPINT_EPDISD; + + /* Clear Global OUT NAK */ + USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK; } return ret; } +/** + * @brief USB_EPSetStall : set a stall condition over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) + { + if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U)) + { + USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); + } + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; + } + else + { + if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U)) + { + USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); + } + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; + } + + return HAL_OK; +} + +/** + * @brief USB_EPClearStall : Clear a stall condition over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) + { + USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; + if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ + } + } + else + { + USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; + if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ + } + } + return HAL_OK; +} +#endif /* defined (HAL_PCD_MODULE_ENABLED) */ /** * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated @@ -1020,67 +1132,6 @@ void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t return ((void *)pDest); } -/** - * @brief USB_EPSetStall : set a stall condition over an EP - * @param USBx Selected device - * @param ep pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t epnum = (uint32_t)ep->num; - - if (ep->is_in == 1U) - { - if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U)) - { - USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); - } - USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; - } - else - { - if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U)) - { - USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); - } - USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; - } - - return HAL_OK; -} - -/** - * @brief USB_EPClearStall : Clear a stall condition over an EP - * @param USBx Selected device - * @param ep pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t epnum = (uint32_t)ep->num; - - if (ep->is_in == 1U) - { - USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; - if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) - { - USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ - } - } - else - { - USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; - if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) - { - USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ - } - } - return HAL_OK; -} - /** * @brief USB_StopDevice : Stop the usb device mode * @param USBx Selected device @@ -1291,8 +1342,8 @@ void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) * @param USBx Selected device * @retval return core mode : Host or Device * This parameter can be one of these values: - * 0 : Host - * 1 : Device + * 1 : Host + * 0 : Device */ uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx) { @@ -1340,7 +1391,7 @@ HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dm } USBx_OUTEP(0U)->DOEPTSIZ = 0U; - USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1UL << 19)); USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U); USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; @@ -1374,8 +1425,15 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + count = 10U; + + /* few cycles before setting core reset */ + while (count > 0U) + { + count--; + } + /* Core Soft Reset */ - count = 0U; USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; do @@ -1462,8 +1520,8 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c USBx->GINTSTS = CLEAR_INTERRUPT_MASK; /* set Rx FIFO size */ USBx->GRXFSIZ = 0x200U; - USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x100U << 16) & USB_OTG_NPTXFD) | 0x200U); - USBx->HPTXFSIZ = (uint32_t)(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U); + USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x100UL << 16) & USB_OTG_NPTXFD) | 0x200U); + USBx->HPTXFSIZ = (uint32_t)(((0xE0UL << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U); /* Enable the common interrupts */ if (cfg.dma_enable == 0U) @@ -1568,13 +1626,13 @@ HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state } /** - * @brief Return Host Core speed + * @brief Return Host Port speed * @param USBx Selected device - * @retval speed : Host speed + * @retval speed : Host port device speed * This parameter can be one of these values: - * @arg HCD_SPEED_HIGH: High speed mode - * @arg HCD_SPEED_FULL: Full speed mode - * @arg HCD_SPEED_LOW: Low speed mode + * @arg HCD_DEVICE_SPEED_HIGH: High speed mode + * @arg HCD_DEVICE_SPEED_FULL: Full speed mode + * @arg HCD_DEVICE_SPEED_LOW: Low speed mode */ uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx) { @@ -1597,6 +1655,7 @@ uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx) return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM); } +#if defined (HAL_HCD_MODULE_ENABLED) /** * @brief Initialize a host channel * @param USBx Selected device @@ -1705,7 +1764,7 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, /* Program the HCCHAR register */ if ((epnum & 0x80U) == 0x80U) { - HCcharEpDir = (0x1U << 15) & USB_OTG_HCCHAR_EPDIR; + HCcharEpDir = (0x1UL << 15) & USB_OTG_HCCHAR_EPDIR; } else { @@ -1717,7 +1776,7 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, /* LS device plugged to HUB */ if ((speed == HPRT0_PRTSPD_LOW_SPEED) && (HostCoreSpeed != HPRT0_PRTSPD_LOW_SPEED)) { - HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV; + HCcharLowSpeed = (0x1UL << 17) & USB_OTG_HCCHAR_LSDEV; } else { @@ -2046,7 +2105,7 @@ HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U) { - if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U) + if ((USBx->HNPTXSTS & (0xFFUL << 16)) == 0U) { USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; @@ -2074,7 +2133,7 @@ HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) { USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; - if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U) + if ((USBx_HOST->HPTXSTS & (0xFFUL << 16)) == 0U) { USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; @@ -2097,6 +2156,34 @@ HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) return HAL_OK; } +/** + * @brief Activate a host channel + * @param USBx Selected device + * @param ch_num Host Channel number + * This parameter can be a value from 1 to 15 + * @param ch_dir Host Channel direction + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_Activate(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, uint8_t ch_dir) +{ + UNUSED(ch_dir); + + __IO uint32_t tmpreg; + uint32_t USBx_BASE = (uint32_t)USBx; + + /* activate the channel */ + tmpreg = USBx_HC(ch_num)->HCCHAR; + + if ((tmpreg & USB_OTG_HCCHAR_CHDIS) == 0U) + { + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(ch_num)->HCCHAR = tmpreg; + } + + return HAL_OK; +} +#endif /* defined (HAL_HCD_MODULE_ENABLED) */ + /** * @brief Initiate Do Ping protocol * @param USBx Selected device diff --git a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_ll_utils.c b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_ll_utils.c index 4cc0a6b..c127722 100644 --- a/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_ll_utils.c +++ b/Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_ll_utils.c @@ -295,7 +295,7 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSI(const LL_UTILS_PLLInitTypeDef *pUTILS_P UTILS_ConfigureIC(pUTILS_ICInitStruct); /* Enable PLL and switch CPU/system clock to PLL */ - status = UTILS_EnablePLL1AndSwitchSystem(pllfreq, pUTILS_ClkInitStruct); + status = UTILS_EnablePLL1AndSwitchSystem(pllfreq / pUTILS_ICInitStruct->IC1Divider, pUTILS_ClkInitStruct); } else { @@ -380,7 +380,7 @@ ErrorStatus LL_PLL_ConfigSystemClock_MSI(const LL_UTILS_PLLInitTypeDef *pUTILS_P UTILS_ConfigureIC(pUTILS_ICInitStruct); /* Enable PLL and switch system clock to PLL */ - status = UTILS_EnablePLL1AndSwitchSystem(pllfreq, pUTILS_ClkInitStruct); + status = UTILS_EnablePLL1AndSwitchSystem(pllfreq / pUTILS_ICInitStruct->IC1Divider, pUTILS_ClkInitStruct); } else { @@ -484,7 +484,7 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypa UTILS_ConfigureIC(pUTILS_ICInitStruct); /* Enable PLL and switch system clock to PLL */ - status = UTILS_EnablePLL1AndSwitchSystem(pllfreq, pUTILS_ClkInitStruct); + status = UTILS_EnablePLL1AndSwitchSystem(pllfreq / pUTILS_ICInitStruct->IC1Divider, pUTILS_ClkInitStruct); } else { diff --git a/Linker/STM32N6xx_EXT_FLASH.ld b/Linker/STM32N6xx_EXT_FLASH.ld new file mode 100644 index 0000000..1e732c8 --- /dev/null +++ b/Linker/STM32N6xx_EXT_FLASH.ld @@ -0,0 +1,211 @@ +/* +****************************************************************************** +** +** @file : STM32N657XX_AXISRAM2_fsbl.ld +** +** @author : GPM Application Team +** +** @brief : Linker script for STM32N657XX Device from STM32N6 series +** 512 KBytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2023 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x1600; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + ROM (xrw) : ORIGIN = 0x70100400, LENGTH = 255K + RAM (xrw) : ORIGIN = 0x341C0000, LENGTH = 256K +} + +/* Sections */ +SECTIONS +{ + + .restart_info (NOLOAD) : + { + . = ALIGN(4); + KEEP(*(.restart_info)) + . = ALIGN(4); + } >RAM + + /* The startup code into "RAM" Ram type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >ROM + + /* The program code and other data into "RAM" Ram type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >ROM + + /* Constant data into "RAM" Ram type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >ROM + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >ROM + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >ROM + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >ROM + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >ROM + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >ROM + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> ROM + + .noncacheable : + { + . = ALIGN(8); + __snoncacheable = .;/* create symbol for start of section */ + KEEP(*(.noncacheable)) + . = ALIGN(8); + __enoncacheable = .; /* create symbol for end of section */ + } > RAM + + + .gnu.sgstubs : + { + . = ALIGN(4); + *(.gnu.sgstubs*) /* Secure Gateway stubs */ + . = ALIGN(4); + } >ROM + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/Linker/STM32N6xx_EXT_FLASH_SIGNATURE.ld b/Linker/STM32N6xx_EXT_FLASH_SIGNATURE.ld new file mode 100644 index 0000000..ae55f2a --- /dev/null +++ b/Linker/STM32N6xx_EXT_FLASH_SIGNATURE.ld @@ -0,0 +1,216 @@ +/* +****************************************************************************** +** +** @file : STM32N657XX_AXISRAM2_fsbl.ld +** +** @author : GPM Application Team +** +** @brief : Linker script for STM32N657XX Device from STM32N6 series +** 512 KBytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2023 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ +_sstack = _estack - _Min_Stack_Size; + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x1600; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + SIGNATURE (rx) : ORIGIN = 0x701003C0, LENGTH = 64 /* Never written to the FLASH, it is for binary signature. */ + ROM (xrw) : ORIGIN = 0x70100400, LENGTH = 255K + RAM (xrw) : ORIGIN = 0x341C0000, LENGTH = 256K +} + +/* Sections */ +SECTIONS +{ + .bl_flash_signature : ALIGN(4) + { + KEEP(*(.bl_flash_signature)) + } >SIGNATURE + + .restart_info (NOLOAD) : + { + . = ALIGN(4); + KEEP(*(.restart_info)) + . = ALIGN(4); + } >RAM + + /* The startup code into "RAM" Ram type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >ROM + + /* The program code and other data into "RAM" Ram type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >ROM + + /* Constant data into "RAM" Ram type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >ROM + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >ROM + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >ROM + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >ROM + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >ROM + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >ROM + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> ROM + + .noncacheable : + { + . = ALIGN(8); + __snoncacheable = .;/* create symbol for start of section */ + KEEP(*(.noncacheable)) + . = ALIGN(8); + __enoncacheable = .; /* create symbol for end of section */ + } > RAM + + + .gnu.sgstubs : + { + . = ALIGN(4); + *(.gnu.sgstubs*) /* Secure Gateway stubs */ + . = ALIGN(4); + } >ROM + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/Makefile b/Makefile index ed81be5..75e4935 100644 --- a/Makefile +++ b/Makefile @@ -150,7 +150,10 @@ nucleo_h755zi: nucleo_h755zi_ram: ${MAKE} stm32h7xx_ram BOARD=NUCLEO_H755ZI BOARD_FILE_NAME=$@ - + +nucleo_n657x0_q_ext: + ${MAKE} stm32n6xx_ext BOARD=NUCLEO_N657X0_Q BOARD_FILE_NAME=$@ + nucleo_n657x0_q_ram: ${MAKE} stm32n6xx_ram BOARD=NUCLEO_N657X0_Q BOARD_FILE_NAME=$@ @@ -177,12 +180,15 @@ stm32l4xx: $(MAKEFILE_LIST) stm32h7xx: $(MAKEFILE_LIST) ${MAKE} -f Makefile.stm32h7xx LDSCRIPT=STM32H7xx.ld FLASH=INTERNAL_FLASH MCU_FILE_NAME=$@ + +stm32h7xx_ext: $(MAKEFILE_LIST) + ${MAKE} -f Makefile.stm32h7xx LDSCRIPT=STM32H7xx.ld FLASH=EXTERNAL_FLASH MCU_FILE_NAME=$@ stm32h7xx_ram: $(MAKEFILE_LIST) ${MAKE} -f Makefile.stm32h7xx LDSCRIPT=STM32H7xx_RAM.ld FLASH=INTERNAL_FLASH MCU_FILE_NAME=$@ - -stm32h7xx_ext: $(MAKEFILE_LIST) - ${MAKE} -f Makefile.stm32h7xx LDSCRIPT=STM32H7xx.ld FLASH=EXTERNAL_FLASH MCU_FILE_NAME=$@ + +stm32n6xx_ext: $(MAKEFILE_LIST) + ${MAKE} -f Makefile.stm32n6xx LDSCRIPT=STM32N6xx_EXT_FLASH.ld FLASH=EXTERNAL_FLASH MCU_FILE_NAME=$@ stm32n6xx_ram: $(MAKEFILE_LIST) ${MAKE} -f Makefile.stm32n6xx LDSCRIPT=STM32N6xx_RAM.ld FLASH=EXTERNAL_FLASH MCU_FILE_NAME=$@ diff --git a/Makefile.common b/Makefile.common index f90c558..f3253bc 100644 --- a/Makefile.common +++ b/Makefile.common @@ -40,6 +40,21 @@ else -IBootloader/STM32/UsbDevice/HS endif +ifeq ($(FLASH),EXTERNAL_FLASH) + C_SOURCES += \ + Bootloader/STM32/ExtMemManager/extmem_manager.c \ + Middlewares/ST/STM32_ExtMem_Manager/boot/stm32_boot_lrun.c \ + Middlewares/ST/STM32_ExtMem_Manager/nor_sfdp/stm32_sfdp_data.c \ + Middlewares/ST/STM32_ExtMem_Manager/nor_sfdp/stm32_sfdp_driver.c \ + Middlewares/ST/STM32_ExtMem_Manager/sal/stm32_sal_xspi.c \ + Middlewares/ST/STM32_ExtMem_Manager/stm32_extmem.c + + C_INCLUDES += \ + -IBootloader/STM32/ExtMemManager \ + -IMiddlewares/ST/STM32_ExtMem_Manager \ + -IMiddlewares/ST/STM32_ExtMem_Manager/nor_sfdp +endif + # compile gcc flags ASFLAGS = $(MCU) $(AS_DEFS) $(AS_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections diff --git a/Makefile.stm32n6xx b/Makefile.stm32n6xx index 7ab22b4..be1ed62 100644 --- a/Makefile.stm32n6xx +++ b/Makefile.stm32n6xx @@ -24,7 +24,8 @@ Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_ll_usb.c \ Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_usart.c \ Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_usart_ex.c \ Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_uart_ex.c \ -Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_uart.c +Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_uart.c \ +Drivers/STM32N6xx_HAL_Driver/Src/stm32n6xx_hal_xspi.c \ # ASM sources ASM_SOURCES = \ diff --git a/Middlewares/ST/STM32_ExtMem_Manager/LICENSE.txt b/Middlewares/ST/STM32_ExtMem_Manager/LICENSE.txt new file mode 100644 index 0000000..e66295c --- /dev/null +++ b/Middlewares/ST/STM32_ExtMem_Manager/LICENSE.txt @@ -0,0 +1,86 @@ +This software component is provided to you as part of a software package and +applicable license terms are in the Package_license file. If you received this +software component outside of a package or without applicable license terms, +the terms of the SLA0044 license shall apply and are fully reproduced below: + +SLA0044 Rev5/February 2018 + +Software license agreement + +ULTIMATE LIBERTY SOFTWARE LICENSE AGREEMENT + +BY INSTALLING, COPYING, DOWNLOADING, ACCESSING OR OTHERWISE USING THIS SOFTWARE +OR ANY PART THEREOF (AND THE RELATED DOCUMENTATION) FROM STMICROELECTRONICS +INTERNATIONAL N.V, SWISS BRANCH AND/OR ITS AFFILIATED COMPANIES +(STMICROELECTRONICS), THE RECIPIENT, ON BEHALF OF HIMSELF OR HERSELF, OR ON +BEHALF OF ANY ENTITY BY WHICH SUCH RECIPIENT IS EMPLOYED AND/OR ENGAGED AGREES +TO BE BOUND BY THIS SOFTWARE LICENSE AGREEMENT. + +Under STMicroelectronics’ intellectual property rights, the redistribution, +reproduction and use in source and binary forms of the software or any part +thereof, with or without modification, are permitted provided that the following +conditions are met: + +1. Redistribution of source code (modified or not) must retain any copyright +notice, this list of conditions and the disclaimer set forth below as items 10 +and 11. + +2. Redistributions in binary form, except as embedded into microcontroller or +microprocessor device manufactured by or for STMicroelectronics or a software +update for such device, must reproduce any copyright notice provided with the +binary code, this list of conditions, and the disclaimer set forth below as +items 10 and 11, in documentation and/or other materials provided with the +distribution. + +3. Neither the name of STMicroelectronics nor the names of other contributors to +this software may be used to endorse or promote products derived from this +software or part thereof without specific written permission. + +4. This software or any part thereof, including modifications and/or derivative +works of this software, must be used and execute solely and exclusively on or in +combination with a microcontroller or microprocessor device manufactured by or +for STMicroelectronics. + +5. No use, reproduction or redistribution of this software partially or totally +may be done in any manner that would subject this software to any Open Source +Terms. “Open Source Terms” shall mean any open source license which requires as +part of distribution of software that the source code of such software is +distributed therewith or otherwise made available, or open source license that +substantially complies with the Open Source definition specified at +www.opensource.org and any other comparable open source license such as for +example GNU General Public License (GPL), Eclipse Public License (EPL), Apache +Software License, BSD license or MIT license. + +6. STMicroelectronics has no obligation to provide any maintenance, support or +updates for the software. + +7. The software is and will remain the exclusive property of STMicroelectronics +and its licensors. The recipient will not take any action that jeopardizes +STMicroelectronics and its licensors' proprietary rights or acquire any rights +in the software, except the limited rights specified hereunder. + +8. The recipient shall comply with all applicable laws and regulations affecting +the use of the software or any part thereof including any applicable export +control law or regulation. + +9. Redistribution and use of this software or any part thereof other than as +permitted under this license is void and will automatically terminate your +rights under this license. + +10. THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS, WHICH ARE +DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT SHALL +STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +11. EXCEPT AS EXPRESSLY PERMITTED HEREUNDER, NO LICENSE OR OTHER RIGHTS, WHETHER +EXPRESS OR IMPLIED, ARE GRANTED UNDER ANY PATENT OR OTHER INTELLECTUAL PROPERTY +RIGHTS OF STMICROELECTRONICS OR ANY THIRD PARTY. + diff --git a/Middlewares/ST/STM32_ExtMem_Manager/boot/stm32_boot_lrun.c b/Middlewares/ST/STM32_ExtMem_Manager/boot/stm32_boot_lrun.c new file mode 100644 index 0000000..d28390e --- /dev/null +++ b/Middlewares/ST/STM32_ExtMem_Manager/boot/stm32_boot_lrun.c @@ -0,0 +1,275 @@ +/** + ****************************************************************************** + * @file stm32_boot_lrun.c + * @author MCD Application Team + * @brief this file manages the boot in the mode load and run. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_boot_lrun.h" + +/** @defgroup BOOT + * @{ + */ + +/** @defgroup BOOT_LRUN + * @{ + */ + +/* Private typedefs ----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ + +/* offset of the vector table from the start of the image. Should be set in extmem_conf.h if needed */ +#ifndef EXTMEM_HEADER_OFFSET +#define EXTMEM_HEADER_OFFSET 0 +#endif +#if defined(EXTMEM_LRUN_TS_ENABLE_NS) && (!defined(EXTMEM_LRUN_DESTINATION_ADDRESS_NS) \ + || !defined(EXTMEM_LRUN_SOURCE_ADDRESS_NS)) +#error "ExtMem user configuration incorrect : undefined parameters for Non-Secure image loading" +#endif +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +BOOTStatus_TypeDef MapMemory(void); +BOOTStatus_TypeDef CopyApplication(void); +BOOTStatus_TypeDef JumpToApplication(void); +BOOTStatus_TypeDef GetBaseAddress(uint32_t MemIndex, uint32_t *BaseAddress); + +/** + * @addtogroup BOOT_LRUN_Exported_Functions Boot LRUN exported functions + * @{ + */ +BOOTStatus_TypeDef BOOT_Application(void) +{ + BOOTStatus_TypeDef retr; + + /* mount the memory */ + retr = MapMemory(); + if (BOOT_OK == retr) + { + retr = CopyApplication(); + if (BOOT_OK == retr) + { + /* jump on the application */ + retr = JumpToApplication(); + } + } + return retr; +} + +/** + * @} + */ + +/** + * @defgroup BOOT_LRUN_Private_Functions Boot LRUN private functions + * @{ + */ + +/** + * @brief this function maps the memory + * @return @ref BOOTStatus_TypeDef + */ +BOOTStatus_TypeDef MapMemory(void) +{ + BOOTStatus_TypeDef retr = BOOT_OK; + uint32_t BaseAddress = 0; + + /* Map all the memory */ + for (uint8_t index = 0; index < (sizeof(extmem_list_config) / sizeof(EXTMEM_DefinitionTypeDef)); index++) + { + switch(EXTMEM_GetMapAddress(index, &BaseAddress)) + { + case EXTMEM_OK :{ + if (EXTMEM_MemoryMappedMode(index, EXTMEM_ENABLE) != EXTMEM_OK) + { + retr = BOOT_ERROR_MAPPEDMODEFAIL; + } + break; + } + case EXTMEM_ERROR_NOTSUPPORTED :{ + /* the memory doesn't support map mode, nothing to do */ + break; + } + default :{ + retr = BOOT_ERROR_NOBASEADDRESS; + break; + } + } + } + return retr; +} + +/** + * @brief This function copy the data from source to destination + * @return @ref BOOTStatus_TypeDef + */ +BOOTStatus_TypeDef CopyApplication(void) +{ + BOOTStatus_TypeDef retr = BOOT_OK; + uint8_t *source; + uint8_t *destination; + uint32_t MapAddress; + uint32_t img_size; + +#if defined(EXTMEM_LRUN_DESTINATION_INTERNAL) + /* this case correspond to copy the SW from external memory into internal memory */ + destination = (uint8_t *)EXTMEM_LRUN_DESTINATION_ADDRESS; +#else + if (EXTMEM_OK != EXTMEM_GetMapAddress(EXTMEM_LRUN_DESTINATION, &MapAddress)) + { + return BOOT_ERROR_MAPPEDMODEFAIL; + } + destination = (uint8_t *)(MapAddress + EXTMEM_LRUN_DESTINATION_ADDRESS); +#endif + + /* get the map address of the source memory */ + switch(EXTMEM_GetMapAddress(EXTMEM_LRUN_SOURCE, &MapAddress)){ + case EXTMEM_OK :{ + /* manage the copy in mapped mode */ + source = (uint8_t*)(MapAddress + EXTMEM_LRUN_SOURCE_ADDRESS); + img_size = BOOT_GetApplicationSize((uint32_t) source); + /* copy form source to destination in mapped mode */ + for (uint32_t index=0; index < img_size; index++) + { + destination[index] = source[index]; + } +#if defined(EXTMEM_LRUN_TZ_ENABLE_NS) + source = (uint8_t*)(MapAddress + EXTMEM_LRUN_SOURCE_ADDRESS_NS); + img_size = BOOT_GetApplicationSize((uint32_t) source); + destination = (uint8_t *)EXTMEM_LRUN_DESTINATION_ADDRESS_NS; + /* copy Non-Secure form source to destination in mapped mode */ + for (uint32_t index=0; index < img_size; index++) + { + destination[index] = source[index]; + } +#endif + break; + } + + case EXTMEM_ERROR_NOTSUPPORTED:{ + img_size = BOOT_GetApplicationSize(EXTMEM_LRUN_SOURCE_ADDRESS); + /* manage the copy using EXTMEM_Read */ + if (EXTMEM_OK != EXTMEM_Read(EXTMEM_LRUN_SOURCE, EXTMEM_LRUN_SOURCE_ADDRESS, destination, img_size)) + { + retr = BOOT_ERROR_COPY; + } +#if defined(EXTMEM_LRUN_TZ_ENABLE_NS) + img_size = BOOT_GetApplicationSize(EXTMEM_LRUN_SOURCE_ADDRESS_NS); + destination = (uint8_t *)EXTMEM_LRUN_DESTINATION_ADDRESS_NS; + /* copy Non-Secure form source to destination in mapped mode */ + if (EXTMEM_OK != EXTMEM_Read(EXTMEM_LRUN_SOURCE, EXTMEM_LRUN_SOURCE_ADDRESS_NS, destination, img_size)) + { + retr = BOOT_ERROR_COPY; + } +#endif + break; + } + + default :{ + /* return an error */ + retr = BOOT_ERROR_MAPPEDMODEFAIL; + break; + } +} + return retr; +} + +/** + * @brief This function jumps to the application through its vector table + * @return @ref BOOTStatus_TypeDef + */ +BOOTStatus_TypeDef JumpToApplication(void) +{ + uint32_t primask_bit; + typedef void (*pFunction)(void); + static pFunction JumpToApp; + uint32_t Application_vector; + /* Suspend SysTick */ + HAL_SuspendTick(); + +#if defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + /* if I-Cache is enabled, disable I-Cache-----------------------------------*/ + if (SCB->CCR & SCB_CCR_IC_Msk) + { + SCB_DisableICache(); + } +#endif /* defined(ICACHE_PRESENT) && (ICACHE_PRESENT == 1U) */ + +#if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + /* if D-Cache is enabled, disable D-Cache-----------------------------------*/ + if (SCB->CCR & SCB_CCR_DC_Msk) + { + SCB_DisableDCache(); + } +#endif /* defined(DCACHE_PRESENT) && (DCACHE_PRESENT == 1U) */ + + /* Initialize user application's Stack Pointer & Jump to user application */ + primask_bit = __get_PRIMASK(); + __disable_irq(); + + Application_vector = BOOT_GetApplicationVectorTable(); + + SCB->VTOR = (uint32_t)Application_vector; + JumpToApp = (pFunction) (*(__IO uint32_t *)(Application_vector + 4)); + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + /* on ARM v8m, set MSPLIM before setting MSP to avoid unwanted stack overflow faults */ + __set_MSPLIM(0x00000000); +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + + __set_MSP(*(__IO uint32_t*)Application_vector); + + /* Re-enable the interrupts */ + __set_PRIMASK(primask_bit); + + JumpToApp(); + return BOOT_OK; +} + + + __weak uint32_t BOOT_GetApplicationSize(uint32_t img_addr) +{ + UNUSED(img_addr); + return EXTMEM_LRUN_SOURCE_SIZE; +} + +__weak uint32_t BOOT_GetApplicationVectorTable(void) +{ + uint32_t vector_table; +#if defined(EXTMEM_LRUN_DESTINATION_INTERNAL) + vector_table = EXTMEM_LRUN_DESTINATION_ADDRESS; +#else + if (EXTMEM_OK != EXTMEM_GetMapAddress(EXTMEM_LRUN_DESTINATION, &vector_table)) + { + return 0xffffffff; + } + vector_table += EXTMEM_LRUN_DESTINATION_ADDRESS; +#endif + vector_table += EXTMEM_HEADER_OFFSET; + return vector_table; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/Middlewares/ST/STM32_ExtMem_Manager/boot/stm32_boot_lrun.h b/Middlewares/ST/STM32_ExtMem_Manager/boot/stm32_boot_lrun.h new file mode 100644 index 0000000..db6b7d4 --- /dev/null +++ b/Middlewares/ST/STM32_ExtMem_Manager/boot/stm32_boot_lrun.h @@ -0,0 +1,84 @@ +/** + ****************************************************************************** + * @file stm32_boot_lrun.h + * @author MCD Application Team + * @brief Header for stm32_boot_lrun.c file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_BOOT_LRUN_H__ +#define __STM32_BOOT_LRUN_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_extmem_conf.h" + +/** @addtogroup BOOT_LRUN + * @{ + */ + +/* Exported defines ---------------------------------------------------------*/ +/** + * @defgroup BOOT_LRUN_Private_Defines Boot LRUN exported definitions + * @{ + */ +/** + * @brief List of status codes for LRUN + */ +typedef enum { + BOOT_OK, + BOOT_ERROR_UNSUPPORTED_MEMORY, /* !< unsupported memory type */ + BOOT_ERROR_NOBASEADDRESS, /* !< not base address for the memory */ + BOOT_ERROR_MAPPEDMODEFAIL, /* !< */ + BOOT_ERROR_COPY, +}BOOTStatus_TypeDef; + +/** + * @} + */ + + +/* Private function prototypes -----------------------------------------------*/ +/** + * @defgroup BOOT_LRUN_Exported_Functions Boot LRUN exported functions + * @{ + */ + +/** + * @brief This function boots on the application, the operation consists in mapping + * the memories, loading the code and jumping in the application. + * + * @return @ref BOOTStatus_TypeDef + **/ + BOOTStatus_TypeDef BOOT_Application(void); + + uint32_t BOOT_GetApplicationSize(uint32_t img_addr); + uint32_t BOOT_GetApplicationVectorTable(void); + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32_BOOT_LRUN_H__ */ \ No newline at end of file diff --git a/Middlewares/ST/STM32_ExtMem_Manager/boot/stm32_boot_xip.c b/Middlewares/ST/STM32_ExtMem_Manager/boot/stm32_boot_xip.c new file mode 100644 index 0000000..05a9ce6 --- /dev/null +++ b/Middlewares/ST/STM32_ExtMem_Manager/boot/stm32_boot_xip.c @@ -0,0 +1,183 @@ +/** + ****************************************************************************** + * @file stm32_boot_xip.c + * @author MCD Application Team + * @brief this file manages the boot in the mode execute in place. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_boot_xip.h" +#include "stm32_extmem_conf.h" + +/** @addtogroup BOOT + * @{ + */ + +/** @addtogroup BOOT_XIP + * @{ + */ + +/* Private typedefs ----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ + +/* offset of the image from the boot memory base */ +#ifndef EXTMEM_XIP_IMAGE_OFFSET +#define EXTMEM_XIP_IMAGE_OFFSET 0 +#endif + +/* offset of the vector table from the start of the image */ +#ifndef EXTMEM_HEADER_OFFSET +#define EXTMEM_HEADER_OFFSET 0 +#endif + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +BOOTStatus_TypeDef JumpToApplication(void); +BOOTStatus_TypeDef MapMemory(void); +BOOTStatus_TypeDef GetBaseAddress(uint32_t MemIndex, uint32_t *BaseAddress); + +/** + * @addtogroup BOOT_XIP_Exported_Functions Boot XIP exported functions + * @{ + */ + +BOOTStatus_TypeDef BOOT_Application(void) +{ + BOOTStatus_TypeDef retr; + + /* mount the memory */ + retr = MapMemory(); + if (BOOT_OK == retr) + { + /* jump on the application */ + retr = JumpToApplication(); + } + return retr; +} + +/** + * @} + */ + +/** + * @defgroup BOOT_XIP_Private_Functions Boot XIP private functions + * @{ + */ + +/** + * @brief this function maps the memory + * @return @ref BOOTStatus_TypeDef + */ +BOOTStatus_TypeDef MapMemory(void) +{ + BOOTStatus_TypeDef retr = BOOT_OK; + + /* Map all the memory */ + for (uint8_t index = 0; index < (sizeof(extmem_list_config) / sizeof(EXTMEM_DefinitionTypeDef)); index++) + { + switch(EXTMEM_MemoryMappedMode(index, EXTMEM_ENABLE)) + { + case EXTMEM_ERROR_NOTSUPPORTED : + if (EXTMEM_MEMORY_BOOTXIP == index) + { + retr = BOOT_ERROR_INCOMPATIBLEMEMORY; + } + else + { + /* We considers the memory will be not used any more */ + EXTMEM_DeInit(index); + } + case EXTMEM_OK: + break; + default : + retr = BOOT_ERROR_MAPPEDMODEFAIL; + break; + } + } + return retr; +} + +/** + * @brief This function jumps to the application through its vector table + * @return @ref BOOTStatus_TypeDef + */ +BOOTStatus_TypeDef JumpToApplication(void) +{ + uint32_t primask_bit; + typedef void (*pFunction)(void); + static pFunction JumpToApp; + uint32_t Application_vector; + + if (EXTMEM_OK != EXTMEM_GetMapAddress(EXTMEM_MEMORY_BOOTXIP, &Application_vector)) + { + return BOOT_ERROR_INCOMPATIBLEMEMORY; + } + + /* Suspend SysTick */ + HAL_SuspendTick(); + +#if defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + /* if I-Cache is enabled, disable I-Cache-----------------------------------*/ + if (SCB->CCR & SCB_CCR_IC_Msk) + { + SCB_DisableICache(); + } +#endif /* defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) */ + +#if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + /* if D-Cache is enabled, disable D-Cache-----------------------------------*/ + if (SCB->CCR & SCB_CCR_DC_Msk) + { + SCB_DisableDCache(); + } +#endif /* defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) */ + + /* Initialize user application's Stack Pointer & Jump to user application */ + primask_bit = __get_PRIMASK(); + __disable_irq(); + + /* Apply offsets for image location and vector table offset */ + Application_vector += EXTMEM_XIP_IMAGE_OFFSET + EXTMEM_HEADER_OFFSET; + + SCB->VTOR = (uint32_t)Application_vector; + JumpToApp = (pFunction) (*(__IO uint32_t *)(Application_vector + 4u)); + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + /* on ARM v8m, set MSPLIM before setting MSP to avoid unwanted stack overflow faults */ + __set_MSPLIM(0x00000000); +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + + __set_MSP(*(__IO uint32_t*) Application_vector); + + /* Re-enable the interrupts */ + __set_PRIMASK(primask_bit); + + JumpToApp(); + return BOOT_OK; +} + +/** + * @} + */ + + /** + * @} + */ + +/** + * @} + */ diff --git a/Middlewares/ST/STM32_ExtMem_Manager/boot/stm32_boot_xip.h b/Middlewares/ST/STM32_ExtMem_Manager/boot/stm32_boot_xip.h new file mode 100644 index 0000000..080d902 --- /dev/null +++ b/Middlewares/ST/STM32_ExtMem_Manager/boot/stm32_boot_xip.h @@ -0,0 +1,81 @@ +/** + ****************************************************************************** + * @file stm32_boot_xip.h + * @author MCD Application Team + * @brief Header for stm32_boot_xip.c file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_BOOT_XIP_H__ +#define __STM32_BOOT_XIP_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + +/** @addtogroup BOOT_XIP + * @{ + */ + +/* Exported defines ---------------------------------------------------------*/ +/** + * @defgroup BOOT_XIP_Private_Defines Boot XIP exported definitions + * @{ + */ +/** + * @brief List of status codes for XIP + */ +typedef enum { + BOOT_OK, + BOOT_ERROR_UNSUPPORTED_MEMORY, /* !< unsupported memory type */ + BOOT_ERROR_NOBASEADDRESS, /* !< not base address for the memory */ + BOOT_ERROR_MAPPEDMODEFAIL, /* !< error during map processing */ + BOOT_ERROR_INCOMPATIBLEMEMORY, /* !< selected memory not compatible with XIP boot */ + BOOT_ERROR_DRIVER, +}BOOTStatus_TypeDef; + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** + * @defgroup BOOT_XIP_Exported_Functions Boot XIP exported functions + * @{ + */ + +/** + * @brief This function boots on the application, the operation consists in mapping + * the memory and jumping in the application. + * + * @return @ref BOOTStatus_TypeDef + **/ +BOOTStatus_TypeDef BOOT_Application(void); + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32_BOOT_XIP_H__ */ \ No newline at end of file diff --git a/Middlewares/ST/STM32_ExtMem_Manager/nor_sfdp/stm32_sfdp_data.c b/Middlewares/ST/STM32_ExtMem_Manager/nor_sfdp/stm32_sfdp_data.c new file mode 100644 index 0000000..211f9ab --- /dev/null +++ b/Middlewares/ST/STM32_ExtMem_Manager/nor_sfdp/stm32_sfdp_data.c @@ -0,0 +1,2625 @@ +/** + ****************************************************************************** + * @file stm32_sfdp_data.c + * @author MCD Application Team + * @brief This file includes a driver for SFDP support + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_extmem_conf.h" + +#if defined(EXTMEM_DRIVER_NOR_SFDP) && (EXTMEM_DRIVER_NOR_SFDP == 1) +#include "stm32_sfdp_driver_api.h" +#include "stm32_sfdp_data.h" +#if EXTMEM_DRIVER_NOR_SFDP_DEBUG_LEVEL != 0 && defined(EXTMEM_MACRO_DEBUG) +#include +#endif /* EXTMEM_DRIVER_NOR_SFDP_DEBUG_LEVEL != 0 && defined(EXTMEM_MACRO_DEBUG) */ +#include + +/** @defgroup NOR_SFDP_DATA Data module + * @ingroup NOR_SFDP + * @{ + */ + +/* Private defines ------------------------------------------------------------*/ +/** @defgroup NOR_SFDP_DATA_Private_define Private defines + * this group contains all the private define of the sfdp data module. + * @{ + */ + +/** @brief true definition + * + * definition of the reset method + */ + typedef enum { + RESET_NONE, + RESET_Fh_4DATA_8CLOCK, + RESET_Fh_4DATA_10CLOCK, + RESET_Fh_4DATA_16CLOCK, + RESET_INSTRUCTION_F0, + RESET_INSTRUCTION_66_99, + RESET_ERROR + } RESET_METHOD; + +/** @brief true definition + * + * definition of the value true and false + */ +#define EXTMEM_SFDP_TRUE 1u /**< true value */ + +/** @brief false definition + * + * definition of the value true and false + */ +#define EXTMEM_SFDP_FALSE 0u /**< false value */ + +/** @brief address none definition + * + * definition of the value to detect no address management case + */ +#define EXTMEM_ADDRESS_NONE 0xFFu /**< no address management */ + +/** + * @brief clock definition 200Mhz + */ +#define CLOCK_200MHZ 200000000u +/** + * @brief clock definition 166Mhz + */ +#define CLOCK_166MHZ 166000000u +/** + * @brief clock definition 133Mhz + */ +#define CLOCK_133MHZ 133000000u +/** + * @brief clock definition 100Mhz + */ +#define CLOCK_100MHZ 100000000u + +/** + * @brief SFDP signature + */ +#define SFDP_SIGNATURE 0x50444653U +#define SFDP_SIGNATURE_INVERTED 0x44505346U +/** + * @brief SFDP header size + */ +#define SFDP_HEADER_SIZE 8U + +/** + * @brief SFDP param header size + */ +#define SFDP_PARAM_HEADER_SIZE 8U + +/** + * @brief SFDP basic table default size + */ +#define SFDP_PARAMS_BASIC_TABLE_DEFAULTSIZE 23u + +/** + * @brief SFDP Basic Parameter Table (MSB and LSB) + */ +#define SFDP_BASIC_PARAMETER_TABLE_MSB 0xFFU +#define SFDP_BASIC_PARAMETER_TABLE_LSB 0x00U + +/** + * @brief DEBUG macro string + */ +#if EXTMEM_DRIVER_NOR_SFDP_DEBUG_LEVEL > 3 && defined(EXTMEM_MACRO_DEBUG) +#define SFDP_DEBUG_STR(_STR_) do{ \ + EXTMEM_MACRO_DEBUG("\t\tSFDP::");\ + EXTMEM_MACRO_DEBUG(_STR_); \ + EXTMEM_MACRO_DEBUG("\n"); \ + }while(0); +#else +#define SFDP_DEBUG_STR(_STR_) +#endif /* */ + +/** + * @brief DEBUG macro string + integer value + */ +#if EXTMEM_DRIVER_NOR_SFDP_DEBUG_LEVEL > 3 && defined(EXTMEM_MACRO_DEBUG) +#define SFDP_DEBUG_INT(_STR_,_INT_) do { \ + char int_char[50]; \ + EXTMEM_MACRO_DEBUG("\t\tSFDP::"); \ + (void)sprintf(int_char,"%s0x%x",_STR_, _INT_); \ + EXTMEM_MACRO_DEBUG((uint8_t *)int_char); \ + EXTMEM_MACRO_DEBUG("\n"); \ + }while(0); +#else +#define SFDP_DEBUG_INT(_STR_,_INT_) +#endif + +/** + * @brief DEBUG macro for function call + */ +#define CHECK_FUNCTION_CALL(_FUNC_) do{ \ + retr = _FUNC_; \ + if ( EXTMEM_SFDP_OK != retr)\ + { \ + goto error; \ + } \ + }while(0); + +/** + * @} + */ + +/* Private typedefs ---------------------------------------------------------*/ +/** @defgroup NOR_SFDP_DATA_Private_TypeDefs Private typedefs + * @{ + */ + +/** + * @brief Memory link configuration + */ +typedef struct { + SAL_XSPI_PhysicalLinkTypeDef PhyLink; + uint8_t DummyCycle; +} TableConfig_Typedef; + + +/** + * @brief SFDP header definition + */ +typedef struct { + uint8_t ID_lsb; /*!< ID lsb */ + uint8_t Minor_revision; /*!< minor revision */ + uint8_t Major_revision; /*!< major revision */ + uint8_t Length; /*!< Length */ + uint8_t TableAddressPointer[3]; /*!< address of the table pointer */ + uint8_t ID_msb; /*!< ID msb */ +} SFDP_ParameterHeaderTypeDef; + +/** + * @brief SFDP param definition + */ +typedef struct { + SFDP_ParamID_TypeDef type; /*!< list of the param table available */ + uint32_t address; /*!< address of the table */ + uint8_t size; /*!< size of the table */ +} SFDP_ParameterTableTypeDef; + +/** + * @brief SFDP JEDEC Basic Params definition + */ +typedef struct { + uint32_t size; + union { + uint8_t data_BYTE[23*4]; /*!< data in bytes format */ + uint32_t data_DWORD[23]; /*!< data in DWORD format */ + struct { + struct { + uint32_t BlockSectorEraseSizes:2; + uint32_t WriteGranularity:1; + uint32_t VolatileRegisterProtect:1; + uint32_t WriteEnableInstructionVolatileRegister:1; + uint32_t :3; + uint32_t _4KEraseInstruction:8; + uint32_t Support_1S1S2SFastRead:1; + uint32_t AddressBytes:2; + uint32_t Support_DTR:1; + uint32_t Support_1S2S2SFastRead:1; + uint32_t Support_1S4S4SFastRead:1; + uint32_t Support_1S1S4SFastRead:1; + uint32_t :8; + } D1; + struct { + uint32_t FlashSize; + } D2; + + /* Fast read */ + struct { + uint32_t _1S4S4S_DummyClock:5; + uint32_t _1S4S4S_ModeClock:3; + uint32_t _1S4S4S_FastReadInstruction:8; + uint32_t _1S1S4S_DummyClock:5; + uint32_t _1S1S4S_ModeClock:3; + uint32_t _1S1S4S_FastReadInstruction:8; + } D3; + struct { + uint32_t _1S1S2S_DummyClock:5; + uint32_t _1S1S2S_ModeClock:3; + uint32_t _1S1S2S_FastReadInstruction:8; + uint32_t _1S2S2S_DummyClock:5; + uint32_t _1S2S2S_ModeClock:3; + uint32_t _1S2S2S_FastReadInstruction:8; + } D4; + struct { + uint32_t _2S2S2S_FastReadSupport:1; + uint32_t :3; + uint32_t _4S4S4S_FastReadSupport:1; + uint32_t :27; + } D5; + struct { + uint32_t :16; + uint32_t _2S2S2S_DummyClock:5; + uint32_t _2S2S2S_ModeClock:3; + uint32_t _2S2S2S_FastReadInstruction:8; + } D6; + struct { + uint32_t :16; + uint32_t _4S4S4S_DummyClock:5; + uint32_t _4S4S4S_ModeClock:3; + uint32_t _4S4S4S_FastReadInstruction:8; + } D7; + + /* Erase */ + struct { + uint32_t EraseType1_Size:8; + uint32_t EraseType1_Instruction:8; + uint32_t EraseType2_Size:8; + uint32_t EraseType2_Instruction:8; + } D8; + struct { + uint32_t EraseType3_Size:8; + uint32_t EraseType3_Instruction:8; + uint32_t EraseType4_Size:8; + uint32_t EraseType4_Instruction:8; + } D9; + + /* Timing */ + struct { + uint32_t MutliplierEraseTime:4; + uint32_t EraseType1_TypicalTime_count:5; + uint32_t EraseType1_TypicalTime_units:2; + uint32_t EraseType2_TypicalTime_count:5; + uint32_t EraseType2_TypicalTime_units:2; + uint32_t EraseType3_TypicalTime_count:5; + uint32_t EraseType3_TypicalTime_units:2; + uint32_t EraseType4_TypicalTime_count:5; + uint32_t EraseType4_TypicalTime_units:2; + } D10; + struct { + uint32_t MutliplierProgamTime:4; + uint32_t PageSize:4; + uint32_t PageProgram_TypicalTime:6; + uint32_t ByteProgram_TypicalTime:5; + uint32_t AddByteProgram_TypicalTime:5; + + uint32_t ChipErase_TypicalTime_count:5; /* 28:24 count */ + uint32_t ChipErase_TypicalTime_units:2; /* 30:29 units (00b: 16 ms, 01b: 256 ms, 10b: 4 s, 11b: 64 s) */ + + uint32_t :1; + } D11; + struct { + uint32_t ProhibitedOpDuringProgramSuspend:4; + uint32_t ProhibitedOpDuringEraseSuspend:4; + uint32_t :1; + uint32_t ProgramResumeToSuspendInterval:4; + uint32_t SuspendInProgress_ProgramMaxLatency:7; + uint32_t EraseResumeToSuspendInterval:4; + uint32_t SuspendInProgress_EraseMaxLatency:7; + uint32_t :1; + } D12; + struct { + uint32_t ProgramResume_Intruction:8; + uint32_t ProgramSuspend_Intruction:8; + uint32_t Resume_Intruction:8; + uint32_t Suspend_Intruction:8; + } D13; + struct { + uint32_t :2; + uint32_t StatusRegister:6; + uint32_t ExitDeepPowerdownDelay:7; + uint32_t ExitDeepPowerdown_Instruction:8; + uint32_t EnterDeepPowerdown_Instruction:8; + uint32_t DeepPowerdown_Support:1; + } D14; + struct { + uint32_t _4S4S4S_DisableSequence:4; + uint32_t _4S4S4S_EnableSequence:5; + uint32_t _0S4S4S_Support:1; + uint32_t _0S4S4S_ExitMethod:6; + uint32_t _0S4S4S_EntryMethod:4; + uint32_t QuadEnableRequirement:3; + uint32_t HoldORReset_Disable:1; + uint32_t :8; + } D15; + struct { + uint32_t VolatileNonVolatileRegister_WriteEnable:7; + uint32_t :1; + uint32_t SoftResetRescueSequence_Support:6; + uint32_t Exit4ByteAddressing:10; + uint32_t Enter4ByteAddressing:8; + } D16; + /* Added one for octal management, this part depends on the information size of the flash device */ + struct { + uint32_t _1S8S8S_DummyClock:5; + uint32_t _1S8S8S_ModeClock:3; + uint32_t _1S8S8S_FastReadInstruction:8; + uint32_t _1S1S8S_DummyClock:5; + uint32_t _1S1S8S_ModeClock:3; + uint32_t _1S1S8S_FastReadInstruction:8; + } D17; + struct { + uint32_t :18; + uint32_t VariableOutputDriverStrength:5; + uint32_t JEDECSPIProtocolReset:1; + uint32_t DataStrobeSTRMode:2; + uint32_t DataSTrobeQPISTRMode:1; + uint32_t DataSTrobeQPIDTRMode:1; + uint32_t :1; + uint32_t OctalDTRCommandExtension:2; + uint32_t OctalByteOrder:1; + } D18; + struct { + uint32_t _8s8s8s_DisableSequence:4; + uint32_t _8s8s8s_EnableSequence:5; + uint32_t _8S8S8S_Support:1; + uint32_t _8S8S8S_ExitMethod:6; + uint32_t _8S8S8S_EnterMethod:4; + uint32_t OctalRequirement:3; + uint32_t :9; + } D19; + struct { + uint32_t _4S4S4S_MaximunSpeedWithoutStrobe:4; /* 1111b: not supported, 1110b: not characterized , 1010b: Reserved + 1100b: 400 MHz*, 1011b: 333 MHz*, 1010b: 266 MHz*, 1001b: 250 MHz* + 1000b: 200 MHz, 0111b: 166 MHz, 0110b: 133 MHz , 0101b: 100 MHz + 0100b: 80 MHz, 0011b: 66 MHz , 0010b: 50 MHz , 0001b: 33 MHz */ + uint32_t _4S4S4S_MaximunSpeedWithStrobe:4; + uint32_t _4S4D4D_MaximunSpeedWithoutStrobe:4; + uint32_t _4S4D4D_MaximunSpeedWithStrobe:4; + uint32_t _8S8S8S_MaximunSpeedWithoutStrobe:4; + uint32_t _8S8S8S_MaximunSpeedWithStrobe:4; + uint32_t _8D8D8D_MaximunSpeedWithoutStrobe:4; + uint32_t _8D8D8D_MaximunSpeedWithStrobe:4; + } D20; + struct { + uint32_t _1S1D1D_FastReadSupport:1; + uint32_t _1S2D2D_FastReadSupport:1; + uint32_t _1S4D4D_FastReadSupport:1; + uint32_t _4S4D4D_FastReadSupport:1; + uint32_t :28; + } D21; + struct { + uint32_t _1S1D1D_DummyClock:5; + uint32_t _1S1D1D_ModeClock:3; + uint32_t _1S1D1D_FastReadInstruction:8; + uint32_t _1S2D2D_DummyClock:5; + uint32_t _1S2D2D_ModeClock:3; + uint32_t _1S2D2D_FastReadInstruction:8; + } D22; + struct { + uint32_t _1S4D4D_DummyClock:5; + uint32_t _1S4D4D_ModeClock:3; + uint32_t _1S4D4D_FastReadInstruction:8; + uint32_t _4S4D4D_DummyClock:5; + uint32_t _4S4D4D_ModeClock:3; + uint32_t _4S4D4D_FastReadInstruction:8; + } D23; + }Param_DWORD; + } Params; +}SFDP_JEDECBasic_Params; + +/** + * @brief SFDP JEDEC 4ByteAddress Params definition + */ +typedef union { + uint8_t data_BYTE[2*4]; /*!< data in BYTE format */ + uint32_t data_DWORD[2]; /*!< data in DWORD format */ + struct { + struct { + uint32_t Support_1S1S1S_ReadCommand:1; /*!< Instruction=13h */ + uint32_t Support_1S1S1S_FastReadCommand:1; /*!< Instruction=0Ch */ + uint32_t Support_1S1S2S_FastReadCommand:1; /*!< Instruction=3Ch */ + uint32_t Support_1S2S2S_FastReadCommand:1; /*!< Instruction=BCh */ + uint32_t Support_1S1S4S_FastReadCommand:1; /*!< Instruction=6Ch */ + uint32_t Support_1S4S4S_FastReadCommand:1; /*!< Instruction=ECh */ + uint32_t Support_1S1S1S_PageProgramCommand:1;/*!< Instruction=12h */ + uint32_t Support_1S1S4S_PageProgramCommand:1;/*!< Instruction=34h */ + uint32_t Support_1S4S4S_PageProgramCommand:1;/*!< Instruction=3Eh */ + uint32_t Support_EraseCommandType1size:1; /*!< support of erase type1 */ + uint32_t Support_EraseCommandType2size:1; /*!< Instruction lookup in next Dword */ + uint32_t Support_EraseCommandType3size:1; /*!< Instruction lookup in next Dword */ + uint32_t Support_EraseCommandType4size:1; /*!< Instruction lookup in next Dword */ + uint32_t Support_1S1D1D_DTRReadCommand:1; /*!< Instruction=0Eh */ + uint32_t Support_1S2D2D_DTRReadCommand:1; /*!< Instruction=BEh */ + uint32_t Support_1S4D4D_DTRReadCommand:1; /*!< Instruction=EEh */ + uint32_t Support_VolatileIndividualSectorLockReadCommand:1; /* Instruction=E0h */ + uint32_t Support_VolatileIndividualSectorLockWriteCommand:1; /* Instruction=E1h */ + uint32_t Support_NVolatileIndividualSectorLockReadCommand:1; /* Instruction=E2h */ + uint32_t Support_NVolatileIndividualSectorLockWriteCommand:1;/* Instruction=E3h */ + uint32_t Support_1S1S8S_FastReadCommand:1; /* Instruction=7Ch */ + uint32_t Support_1S8S8S_FastReadCommand:1; /* Instruction=CCh */ + uint32_t Support_1S8D8D_DTRReadCommand:1; /* Instruction=FDh */ + uint32_t Support_1S1S8S_PageProgramCommand:1;/* Instruction=84h */ + uint32_t Support_1S8S8S_PageProgramCommand:1;/* Instruction=8Eh */ + uint32_t :7; + }D1; + struct { + uint32_t InstructionEraseType1:8; /* common usage is:21h for 4 kbyte erase*/ + uint32_t InstructionEraseType2:8; /* common usage is:5Ch for 32 kbyte erase*/ + uint32_t InstructionEraseType3:8; /* common usage is:DCh for 64 kbyte erase*/ + uint32_t InstructionEraseType4:8; /* common usage is:DCh for 256 kbyte erase*/ + }D2; + }Param_DWORD; +} SFDP_JEDEC4ByteAddress_Params; + + +/** + * @brief SFDP JEDEC XSPI10 Params definition + */ +typedef union { + uint8_t data_BYTE[6*4]; /*!< data in BYTE format */ + uint32_t data_DWORD[6]; /*!< data in DWORD format */ + struct { + /* Command Codes used in 8D-8D-8D protocol mode */ + struct { + uint32_t ReadFastWrapCommand:8; /* 0 means not supported */ + uint32_t ReadFastCommand:8; + uint32_t :6; + uint32_t NumberOfDataBytesForWriteRegisterCommand:1; + uint32_t NumberOfAdditionnalModifierBytesForWriteRegisterCommand:1; + uint32_t NumberOfAdditionnalModifierBytesForStatusConfigRegisterCommand:1; + uint32_t InitialLaLatencyForReadNonVolatileRegisterCommand:1; + uint32_t InitialLatencyForReadVolatileRegisterCommand:1; + uint32_t NumberOfAdditionalModifierBytesForReadRegisterCommand:1; + uint32_t InitialLatencyForReadStatusRegisterCommand:1; + uint32_t NumberOfAdditionalModifierBytesForReadStatusRegisterCommand:1; + uint32_t SFDPCommand_8D8D8DMode_DummyCycles:1; + uint32_t SFDPCommand_8D8D8DMode_AddressBytes:1; + } D1; + /* Commands Codes used in 8D-8D-8D protocol mode */ + struct { + uint32_t WriteNVolatileRegisterCommand:8; + uint32_t WriteVolatileRegisterCommand:8; + uint32_t ReadNVolatileRegisterCommand:8; + uint32_t ReadVolatileRegisterCommand:8; + } D2; + /* Memory Commands in 8D-8D-8D protocol mode */ + struct { + uint32_t :10; + uint32_t EnterDefaultProtocolMode_support:1; + uint32_t SoftResetAndEnterDefaultProtocolMode_support:1; + uint32_t ResetEnable_support:1; + uint32_t SoftReset_support:1; + uint32_t ExitDeepPowerDown_support:1; + uint32_t EnterDeepPowerDown_support:1; + uint32_t WriteNVolatileRegister_support:1; + uint32_t WriteVolatileRegister_support:1; + uint32_t WriteRegister_support:1; + uint32_t ClearFlagStatusReg_support:1; + uint32_t WriteStatusConfigurationRegister_support:1; + uint32_t ReadNVolatileRegister_support:1; + uint32_t ReadVolatileRegister_support:1; + uint32_t ReadRegister_support:1; + uint32_t ReadFlagStatusRegister_support:1; + uint32_t ReadConfigurationRegister_support:1; + uint32_t EraseChip_support:1; + uint32_t Erase_32Kbytes_support:1; + uint32_t Erase_4Kbytes_support:1; + uint32_t SetupReadWrap_support:1; + uint32_t ReadFastWrap_support:1; + uint32_t ReadSFDP_8D8D8D:1; + } D3; /* this naming to be aligned with the specification */ + /* Dummy cycles used for various frequencies */ + struct { + uint32_t :2; + uint32_t Operation200Mhz_ConfigPattern:5; + uint32_t Operation200Mhz_DummyCycle:5; + uint32_t :20; + } D4; + /* Dummy cycles used for various frequencies */ + struct { + uint32_t :2; + uint32_t Operation100Mhz_ConfigPattern:5; + uint32_t Operation100Mhz_DummyCycle:5; + uint32_t Operation133Mhz_ConfigPattern:5; + uint32_t Operation133Mhz_DummyCycle:5; + uint32_t Operation166Mhz_ConfigPattern:5; + uint32_t Operation166Mhz_DummyCycle:5; + } D5; + /* Default Dummy cycles after POR */ + struct { + uint32_t _8D8D8DDefaultPOR_DummyCycle:5; + uint32_t _8S8S8SDefaultPOR_DummyCycle:5; + uint32_t :22; + } D6; + + } Param_DWORD; +} SFDP_JEDEC_XSPI10; /* contains the command codes used in 8D-8D-8D protocol mode */ + +/** + * @brief SFDP JEDEC octal ddr params definition + */ +typedef union { + uint8_t data_BYTE[8*4]; /*!< data in BYTE format */ + uint32_t data_DWORD[8]; /*!< data in DWORD format */ + struct { + /* 1st DWORD - First Command Sequence */ + struct { + uint32_t Byte3CommandSequence:8; + uint32_t Byte2CommandSequence:8; + uint32_t Byte1CommandSequence:8; + uint32_t LengthCommand:8; + } D1; + /* 2nd DWORD - First Command Sequence (continued)*/ + struct { + uint32_t Byte7CommandSequence:8; + uint32_t Byte6CommandSequence:8; + uint32_t Byte5CommandSequence:8; + uint32_t Byte4CommandSequence:8; + } D2; + /* 1st DWORD - Second Command Sequence */ + struct { + uint32_t Byte3CommandSequence:8; + uint32_t Byte2CommandSequence:8; + uint32_t Byte1CommandSequence:8; + uint32_t LengthCommand:8; + } D3; + /* 2nd DWORD - Second Command Sequence (continued)*/ + struct { + uint32_t Byte7CommandSequence:8; + uint32_t Byte6CommandSequence:8; + uint32_t Byte5CommandSequence:8; + uint32_t Byte4CommandSequence:8; + } D4; + /* 1st DWORD - third Command Sequence */ + struct { + uint32_t Byte3CommandSequence:8; + uint32_t Byte2CommandSequence:8; + uint32_t Byte1CommandSequence:8; + uint32_t LengthCommand:8; + } D5; + /* 2nd DWORD - third Command Sequence (continued)*/ + struct { + uint32_t Byte7CommandSequence:8; + uint32_t Byte6CommandSequence:8; + uint32_t Byte5CommandSequence:8; + uint32_t Byte4CommandSequence:8; + } D6; + /* 1st DWORD - fourth Command Sequence */ + struct { + uint32_t Byte3CommandSequence:8; + uint32_t Byte2CommandSequence:8; + uint32_t Byte1CommandSequence:8; + uint32_t LengthCommand:8; + } D7; + /* 2nd DWORD - fourth Command Sequence (continued)*/ + struct { + uint32_t Byte7CommandSequence:8; + uint32_t Byte6CommandSequence:8; + uint32_t Byte5CommandSequence:8; + uint32_t Byte4CommandSequence:8; + } D8; + } Param_DWORD; +} SFDP_JEDEC_OCTALDDR; /* contains the command codes used in 8D-8D-8D protocol mode */ + +/** + * @brief SFDP JEDEC SCCR Params definition + */ +typedef union { + uint8_t data_b[28*4]; /*!< data in byte format */ + uint32_t data_DWORD[28]; /*!< data in DWORD format */ + struct { + + uint32_t AddressOffsetVolatileRegister; + uint32_t AddressOffsetNonVolatileRegister; + + + /* Generic Addressable Read/Write Status/Control register commands for volatile registers */ + struct { + uint32_t NbDummyCyclesReadStatusControlRegisterCommandForVolatileRegisters_1S1S1S:4; + uint32_t :2; + uint32_t NbDummyCyclesReadRegisterCmdVolatileRegister_8D8D8D_mode:4; + uint32_t NbDummyCyclesReadRegisterCmdVolatileRegister_8S8S8S_mode:4; + uint32_t NbDummyCyclesReadRegisterCmdVolatileRegister_4S4D4D_mode:4; + uint32_t NbDummyCyclesReadRegisterCmdVolatileRegister_4S4S4S_mode:4; + uint32_t NbDummyCyclesReadRegisterCmdVolatileRegister_2S2S2S_mode:4; + uint32_t NbDummyCyclesReadRegisterCmdVolatileRegister_1S1S1S_mode:2; + + uint32_t NbAddressBytesGenericAddressableReadWriteStatusControlRegisterCommandsVolatileRegisters:2; + uint32_t GenericAddressableWriteRegisterCmdVolatileRegister_support:1; + uint32_t GenericAddressableReadRegisterCmdVolatileRegister_support:1; + } D3; + /* Generic Addressable Read/Write Status/Control register commands for non-volatile registers */ + struct { + uint32_t NbDummyCyclesReadStatusControlRegisterCommandForNVolatileRegisters_1S1S1S:4; + uint32_t :2; + uint32_t NbDummyCyclesReadRegisterCmdNonVolatileRegister_8D8D8D_mode:4; + uint32_t NbDummyCyclesReadRegisterCmdNonVolatileRegister_8S8S8S_mode:4; + uint32_t NbDummyCyclesReadRegisterCmdNonVolatileRegister_4S4D4D_mode:4; + uint32_t NbDummyCyclesReadRegisterCmdNonVolatileRegister_4S4S4S_mode:4; + uint32_t NbDummyCyclesReadRegisterCmdNonVolatileRegister_2S2S2S_mode:4; + uint32_t NbDummyCyclesReadRegisterCmdNonVolatileRegister_1S1S1S_mode:2; + + uint32_t NbAddressBytesGenericAddressableReadWriteStatusControlRegisterCommandsNVolatileRegisters:2; + uint32_t GenericAddressableWriteRegisterCmdNonVolatileRegister_support:1; + uint32_t GenericAddressableReadRegisterCmdNonVolatileRegister_support:1; + } D4; + /* WIP (Required for xSPI) */ + struct { + uint32_t CommandWriteAccess:8; + uint32_t CommandReadAccess:8; + uint32_t AddressRegisterOrModesSupported:8; /* If Bit 28 is 1: Address of register where bit is located + Local address AAAA-AAAA + If Bit 28 is 0: Modes supported and dummy cycles used for direct command + */ + uint8_t WIPBitLocationRegister:3; + uint32_t LocalAddressForWIP:1; + uint32_t BitAccessedByCommandsUsingAddress:1; + uint32_t :1; + uint32_t WIPpolarity:1; + uint32_t WIPBitAvailable:1; + } D5; + /* WEL */ + struct { + uint32_t CommandWriteAccess:8; + uint32_t CommandReadAccess:8; + uint32_t AddressRegisterOrModesSupported:8; /* If Bit 28 is 1: Address of register where bit is located + Local address AAAA-AAAA + If Bit 28 is 0: Modes supported and dummy cycles used for direct command + */ + uint8_t WELBitLocationRegister:3; + uint32_t WELLocalAddress:1; + uint32_t BitAccessedByCommandsUsingAddress:1; + uint32_t WELWriteAccessBit:1; + uint32_t WELpolarity:1; + uint32_t WELBitAvailable:1; + } D6; + /* Program Error */ + struct { + uint32_t CommandWriteAccess:8; + uint32_t CommandReadAccess:8; + uint32_t AddressRegisterOrModesSupported:8; /* If Bit 28 is 1: Address of register where bit is located + Local address AAAA-AAAA + If Bit 28 is 0: Modes supported and dummy cycles used for direct command + */ + uint8_t BitLocationRegister:3; + uint32_t LocalAddress:1; + uint32_t BitAccessedByCommandsUsingAddress:1; + uint32_t Sharing:1; + uint32_t Polarity:1; + uint32_t BitAvailable:1; + } D7; + /* Erase Error */ + struct { + uint32_t CommandWriteAccess:8; + uint32_t CommandReadAccess:8; + uint32_t AddressRegisterOrModesSupported:8; /* If Bit 28 is 1: Address of register where bit is located + Local address AAAA-AAAA + If Bit 28 is 0: Modes supported and dummy cycles used for direct command + */ + uint8_t BitLocationRegister:3; + uint32_t LocalAddress:1; + uint32_t BitAccessedByCommandsUsingAddress:1; + uint32_t Sharing:1; + uint32_t Polarity:1; + uint32_t BitAvailable:1; + } D8; + /* 9th DWORD * Variable Dummy Cycle Settings * Volatile Register */ + struct { + uint32_t CommandWriteAccess:8; + uint32_t CommandReadAccess:8; + uint32_t AddressRegisterOrModesSupported:8; /* If Bit 28 is 1: Address of register where bit is located + Local address AAAA-AAAA + If Bit 28 is 0: Modes supported and dummy cycles used for direct command + */ + uint8_t BitLocationLSBPhysicalBitsRegister:3; + uint32_t LocalAddress:1; + uint32_t BitAccessedByCommandsUsingAddress:1; + uint32_t NumberBitsUsedToSetWaitStates:2; + uint32_t BitAvailable:1; + } D9; + /* 10th DWORD * Variable Dummy Cycle Settings * Non Volatile Register */ + struct { + uint32_t CommandWriteAccess:8; + uint32_t CommandReadAccess:8; + uint32_t AddressRegisterOrModesSupported:8; /* If Bit 28 is 1: Address of register where bit is located + Local address AAAA-AAAA + If Bit 28 is 0: Modes supported and dummy cycles used for direct command + */ + uint8_t BitLocationLSBPhysicalBitsRegister:3; + uint32_t LocalAddress:1; + uint32_t BitAccessedByCommandsUsingAddress:1; + uint32_t NumberBitsUsedToSetWaitStates:2; + uint32_t BitAvailable:1; + } D10; + /* 11th DWORD * Variable Dummy Cycle Settings * bit patterns */ + struct { + uint32_t :2; + uint32_t BitPatternUsedToSet_22DummyCycles:5; + uint32_t Support_22DummyCycles:1; + uint32_t BitPatternUsedToSet_24DummyCycles:5; + uint32_t Support_24DummyCycles:1; + uint32_t BitPatternUsedToSet_26DummyCycles:5; + uint32_t Support_26DummyCycles:1; + uint32_t BitPatternUsedToSet_28DummyCycles:5; + uint32_t Support_28DummyCycles:1; + uint32_t BitPatternUsedToSet_30DummyCycles:5; + uint32_t Support_30DummyCycles:1; + } D11; + /* 12th DWORD * Variable Dummy Cycle Settings * bit patterns */ + struct { + uint32_t :2; + uint32_t BitPatternUsedToSet_12DummyCycles:5; + uint32_t Support_12DummyCycles:1; + uint32_t BitPatternUsedToSet_14DummyCycles:5; + uint32_t Support_14DummyCycles:1; + uint32_t BitPatternUsedToSet_16DummyCycles:5; + uint32_t Support_16DummyCycles:1; + uint32_t BitPatternUsedToSet_18DummyCycles:5; + uint32_t Support_18DummyCycles:1; + uint32_t BitPatternUsedToSet_20DummyCycles:5; + uint32_t Support_20DummyCycles:1; + } D12; + /* 13th DWORD * Variable Dummy Cycle Settings * bit patterns */ + struct { + uint32_t :2; + uint32_t BitPatternUsedToSet_2DummyCycles:5; + uint32_t Support_2DummyCycles:1; + uint32_t BitPatternUsedToSet_4DummyCycles:5; + uint32_t Support_4DummyCycles:1; + uint32_t BitPatternUsedToSet_6DummyCycles:5; + uint32_t Support_6DummyCycles:1; + uint32_t BitPatternUsedToSet_8DummyCycles:5; + uint32_t Support_8DummyCycles:1; + uint32_t BitPatternUsedToSet_10DummyCycles:5; + uint32_t Support_10DummyCycles:1; + } D13; + /* 14th DWORD * QPI Mode Enable Volatile */ + struct { + uint32_t CommandWriteAccess:8; + uint32_t CommandReadAccess:8; + uint32_t AddressRegisterOrModesSupported:8; /* If Bit 28 is 1: Address of register where bit is located + Local address AAAA-AAAA + If Bit 28 is 0: Modes supported and dummy cycles used for direct command + */ + uint8_t BitLocationRegister:3; + uint32_t LocalAddress:1; + uint32_t BitAccessedByCommandsUsingAddress:1; + uint32_t :1; + uint32_t BitPolarity:1; + uint32_t BitAvailable:1; + } D14; + /* 15th DWORD * QPI Mode Enable - Non Volatile */ + struct { + uint32_t CommandWriteAccess:8; + uint32_t CommandReadAccess:8; + uint32_t AddressRegisterOrModesSupported:8; /* If Bit 28 is 1: Address of register where bit is located + Local address AAAA-AAAA + If Bit 28 is 0: Modes supported and dummy cycles used for direct command + */ + uint8_t BitLocationRegister:3; + uint32_t LocalAddress:1; + uint32_t BitAccessedByCommandsUsingAddress:1; + uint32_t :1; + uint32_t BitPolarity:1; + uint32_t BitAvailable:1; + } D15; + /* 16th DWORD * Octal Mode Enable Volatile */ + struct { + uint32_t CommandWriteAccess:8; + uint32_t CommandReadAccess:8; + uint32_t AddressRegisterOrModesSupported:8; /* If Bit 28 is 1: Address of register where bit is located + Local address AAAA-AAAA + If Bit 28 is 0: Modes supported and dummy cycles used for direct command + */ + uint8_t BitLocationRegister:3; + uint32_t LocalAddress:1; + uint32_t BitAccessedByCommandsUsingAddress:1; + uint32_t :1; + uint32_t BitPolarity:1; + uint32_t BitAvailable:1; + } D16; + /* 17th DWORD * Octal Mode Enable - Non Volatile */ + struct { + uint32_t CommandWriteAccess:8; + uint32_t CommandReadAccess:8; + uint32_t AddressRegisterOrModesSupported:8; /* If Bit 28 is 1: Address of register where bit is located + Local address AAAA-AAAA + If Bit 28 is 0: Modes supported and dummy cycles used for direct command + */ + uint8_t BitLocationRegister:3; + uint32_t LocalAddress:1; + uint32_t BitAccessedByCommandsUsingAddress:1; + uint32_t :1; + uint32_t BitPolarity:1; + uint32_t BitAvailable:1; + } D17; + /* 18th DWORD * STR or DTR mode select * Volatile */ + struct { + uint32_t CommandWriteAccess:8; + uint32_t CommandReadAccess:8; + uint32_t AddressRegisterOrModesSupported:8; /* If Bit 28 is 1: Address of register where bit is located + Local address AAAA-AAAA + If Bit 28 is 0: Modes supported and dummy cycles used for direct command + */ + uint8_t BitLocationRegister:3; + uint32_t LocalAddress:1; + uint32_t BitAccessedByCommandsUsingAddress:1; + uint32_t :1; + uint32_t BitPolarity:1; + uint32_t BitAvailable:1; + } D18; + /* 19th DWORD * STR or DTR mode select * Non Volatile */ + struct { + uint32_t CommandWriteAccess:8; + uint32_t CommandReadAccess:8; + uint32_t AddressRegisterOrModesSupported:8; /* If Bit 28 is 1: Address of register where bit is located + Local address AAAA-AAAA + If Bit 28 is 0: Modes supported and dummy cycles used for direct command + */ + uint8_t BitLocationRegister:3; + uint32_t LocalAddress:1; + uint32_t BitAccessedByCommandsUsingAddress:1; + uint32_t :1; + uint32_t BitPolarity:1; + uint32_t BitAvailable:1; + } D19; + /* 20th DWORD * STR Octal Mode Enable * Volatile */ + struct { + uint32_t CommandWriteAccess:8; + uint32_t CommandReadAccess:8; + uint32_t AddressRegisterOrModesSupported:8; /* If Bit 28 is 1: Address of register where bit is located + Local address AAAA-AAAA + If Bit 28 is 0: Modes supported and dummy cycles used for direct command + */ + uint8_t BitLocationRegister:3; + uint32_t LocalAddress:1; + uint32_t BitAccessedByCommandsUsingAddress:1; + uint32_t :1; + uint32_t BitPolarity:1; + uint32_t BitAvailable:1; + } D20; + /* 21th DWORD * STR Octal Mode Enable * Non Volatile */ + struct { + uint32_t CommandWriteAccess:8; + uint32_t CommandReadAccess:8; + uint32_t AddressRegisterOrModesSupported:8; /* If Bit 28 is 1: Address of register where bit is located + Local address AAAA-AAAA + If Bit 28 is 0: Modes supported and dummy cycles used for direct command + */ + uint8_t BitLocationRegister:3; + uint32_t LocalAddress:1; + uint32_t BitAccessedByCommandsUsingAddress:1; + uint32_t :1; + uint32_t BitPolarity:1; + uint32_t BitAvailable:1; + } D21; + /* 22th DWORD * DTR Octal Mode Enable * Volatile */ + struct { + uint32_t CommandWriteAccess:8; + uint32_t CommandReadAccess:8; + uint32_t AddressRegisterOrModesSupported:8; /* If Bit 28 is 1: Address of register where bit is located + Local address AAAA-AAAA + If Bit 28 is 0: Modes supported and dummy cycles used for direct command + */ + uint8_t BitLocationRegister:3; + uint32_t LocalAddress:1; + uint32_t BitAccessedByCommandsUsingAddress:1; + uint32_t :1; + uint32_t BitPolarity:1; + uint32_t BitAvailable:1; + } D22; + /* 23th DWORD * DTR Octal Mode Enable * Non Volatile */ + struct { + uint32_t CommandWriteAccess:8; + uint32_t CommandReadAccess:8; + uint32_t AddressRegisterOrModesSupported:8; /* If Bit 28 is 1: Address of register where bit is located + Local address AAAA-AAAA + If Bit 28 is 0: Modes supported and dummy cycles used for direct command + */ + uint8_t BitLocationRegister:3; + uint32_t LocalAddress:1; + uint32_t BitAccessedByCommandsUsingAddress:1; + uint32_t :1; + uint32_t BitPolarity:1; + uint32_t BitAvailable:1; + } D23; + /* 24th DWORD * DPD Status */ + struct { + uint32_t CommandWriteAccess:8; + uint32_t CommandReadAccess:8; + uint32_t AddressRegisterOrModesSupported:8; /* If Bit 28 is 1: Address of register where bit is located + Local address AAAA-AAAA + If Bit 28 is 0: Modes supported and dummy cycles used for direct command + */ + uint8_t BitLocationRegister:3; + uint32_t LocalAddress:1; + uint32_t BitAccessedByCommandsUsingAddress:1; + uint32_t :1; + uint32_t BitPolarity:1; + uint32_t BitAvailable:1; + } D24; + /* 25th DWORD * UDPD Status */ + struct { + uint32_t CommandWriteAccess:8; + uint32_t CommandReadAccess:8; + uint32_t AddressRegisterOrModesSupported:8; /* If Bit 28 is 1: Address of register where bit is located + Local address AAAA-AAAA + If Bit 28 is 0: Modes supported and dummy cycles used for direct command + */ + uint8_t BitLocationRegister:3; + uint32_t LocalAddress:1; + uint32_t BitAccessedByCommandsUsingAddress:1; + uint32_t :1; + uint32_t BitPolarity:1; + uint32_t BitAvailable:1; + } D25; + /* 26th DWORD * Output Driver Strength - Volatile */ + struct { + uint32_t CommandWriteAccess:8; + uint32_t CommandReadAccess:8; + uint32_t AddressRegisterOrModesSupported:8; /* If Bit 28 is 1: Address of register where bit is located + Local address AAAA-AAAA + If Bit 28 is 0: Modes supported and dummy cycles used for direct command + */ + uint8_t BitLocationRegister:3; + uint32_t LocalAddress:1; + uint32_t BitAccessedByCommandsUsingAddress:1; + uint32_t :1; + uint32_t NumberOfPhysicalBits:2; + } D26; + /* 27th DWORD * Output Driver Strength - Non Volatile */ + struct { + uint32_t CommandWriteAccess:8; + uint32_t CommandReadAccess:8; + uint32_t AddressRegisterOrModesSupported:8; /* If Bit 28 is 1: Address of register where bit is located + Local address AAAA-AAAA + If Bit 28 is 0: Modes supported and dummy cycles used for direct command + */ + uint8_t BitLocationRegister:3; + uint32_t LocalAddress:1; + uint32_t BitAccessedByCommandsUsingAddress:1; + uint32_t :1; + uint32_t NumberOfPhysicalBits:2; + } D27; + /* 27th DWORD * Output Driver Strength - Non Volatile */ + struct { + uint32_t :16; + uint32_t BitPatternSupportDriverType4 :3; + uint32_t BitPatternSupportDriverType3 :3; + uint32_t BitPatternSupportDriverType2 :3; + uint32_t BitPatternSupportDriverType1 :3; + uint32_t BitPatternSupportDriverType0 :3; + } D28; + + + } Param_DWORD; +} SFDP_JEDEC_SCCR_Map; /* contains the command codes used in 8D-8D-8D protocol mode */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup NOR_SFDP_DATA_Private_Variables Private Variables + * @{ + */ +/** + * @brief this variable contains all the table available on a memory + */ +static SFDP_ParameterTableTypeDef sfdp_param_info[SFDP_MAX_NB_OF_PARAM]; + +/** + * @brief this variable contains the JEDEC basic table info + */ +static SFDP_JEDECBasic_Params JEDEC_Basic = {0}; + +/** + * @brief this variable contains the JEDEC address 4-Byte address table info + */ +static SFDP_JEDEC4ByteAddress_Params JEDEC_Address4Bytes = {0}; + +/** + * @brief this variable contains the JEDEC XSPIV1.0 table info + */ +static SFDP_JEDEC_XSPI10 JEDEC_XSPI10; + +/** + * @brief this variable contains the JEDEC SCCR table info + */ +static SFDP_JEDEC_SCCR_Map JEDEC_SCCR_Map; + +/** + * @brief this variable contains the JEDEC octal DDR table info + */ +static SFDP_JEDEC_OCTALDDR JEDEC_OctalDdr; + + + + + + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup NOR_SFDP_DATA_Private_Functions Private Functions + * @{ + */ +SFDP_StatusTypeDef sfdp_get_paraminfo(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *Object, uint32_t sfdp_address, SFDP_ParameterTableTypeDef *Param_info); +SFDP_StatusTypeDef sfdp_enter_octal_mode(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *Object); +uint32_t sfdp_getfrequencevalue(uint32_t BitField); +SFDP_StatusTypeDef sfdp_set_dummycycle(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *Object, uint32_t Value); +/** + * @} + */ + +/** @defgroup NOR_SFDP_DATA_Private_JEDEC_Functions Private Functions for JEDEC decoding + * @{ + */ +SFDP_StatusTypeDef JEDEC_Basic_ManageQuadEnableRequirement(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *Object); +SFDP_StatusTypeDef JEDEC_Basic_Manage4S4S4SEnableSequence(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *Object); + +/** @defgroup NOR_SFDP_DATA_Private_Singature_Functions Private Functions for SFDP signature + * @{ + */ +SFDP_StatusTypeDef CheckSFDP_Signature(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *Object, uint32_t Signature ); +/** + * @} + */ + + +/** @defgroup NOR_SFDP_DATA_Exported_Functions Exported Functions + * @{ + */ + +/** + * @brief This function reads and checks the SFDP header and adjusts + * @param Object memory Object + * @param sfdp_header data of the SFDP header + * @return @ref SFDP_StatusTypeDef + */ +SFDP_StatusTypeDef SFDP_ReadHeader(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *Object, SFDP_HeaderTypeDef *sfdp_header) +{ + SFDP_StatusTypeDef retr; + uint8_t retry_counter = 0; + SFDP_DEBUG_STR(__func__); + + do { + /* Reset the signature value */ + sfdp_header->Signature = 0; + + /* send the SFDP command to read the header */ + if(HAL_OK != SAL_XSPI_GetSFDP(&Object->sfdp_private.SALObject, 0, (uint8_t*)sfdp_header, SFDP_HEADER_SIZE)) + { + retr = EXTMEM_SFDP_ERROR_SFDPREAD; + goto error; + } + + /* view the header signature value */ + SFDP_DEBUG_INT("SFDP signature::", sfdp_header->Signature); + + switch(CheckSFDP_Signature(Object, sfdp_header->Signature)) + { + case EXTMEM_SFDP_OK: + SFDP_DEBUG_INT("param_number=", sfdp_header->param_number); + SFDP_DEBUG_INT("AccessProtocol=", sfdp_header->AccessProtocol); + retr = EXTMEM_SFDP_OK; + retry_counter = 2u; + break; + case EXTMEM_SFDP_ERROR_SIGNATUREMTYPE: + retr = EXTMEM_SFDP_ERROR_SIGNATURE; + retry_counter++; + break; + /* case EXTMEM_SFDP_ERROR_SIGNATURE :*/ + default : + retr = EXTMEM_SFDP_ERROR_SIGNATURE; + retry_counter = 2u; + break; + } + } while(retry_counter < 2u); + +error: + return retr; +} + + +SFDP_StatusTypeDef SFDP_GetHeader(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *Object, SFDP_HeaderTypeDef *sfdp_header) +{ + SFDP_StatusTypeDef retr = EXTMEM_SFDP_ERROR_SIGNATURE; + SFDP_DEBUG_STR(__func__); + const TableConfig_Typedef table_config[] = + { + {PHY_LINK_1S1S1S, 8u}, + {PHY_LINK_4S4S4S, 2u}, + {PHY_LINK_4S4S4S, 8u}, + {PHY_LINK_4S4S4S, 6u}, + {PHY_LINK_8D8D8D, 8u}, + {PHY_LINK_8D8D8D, 20u}, + {PHY_LINK_8D8D8D, 10u}, + {PHY_LINK_8D8D8D, 16u} + }; + + /* loop to find the link configuration of the memory */ + for (uint8_t index = 0u; + (index < (sizeof(table_config)/sizeof(TableConfig_Typedef))) && + (retr == EXTMEM_SFDP_ERROR_SIGNATURE) + ; index++) + { + /* Set the command mode */ + SFDP_DEBUG_STR("try a command configuration"); + + /* Configure the link */ + Object->sfdp_private.DriverInfo.SpiPhyLink = table_config[index].PhyLink; + (void)SAL_XSPI_MemoryConfig(&Object->sfdp_private.SALObject, PARAM_PHY_LINK, &Object->sfdp_private.DriverInfo.SpiPhyLink); + SAL_XSPI_SET_SFDPDUMMYCYLE(Object->sfdp_private.SALObject, table_config[index].DummyCycle); + + /* Loop on the instruction extension */ + for (uint8_t IExt = 0u; + (IExt < 2u) && (retr == EXTMEM_SFDP_ERROR_SIGNATURE); IExt++) + { + SAL_XSPI_SET_COMMANDEXTENSION(Object->sfdp_private.SALObject, IExt); + /* Read the sfdp header */ + if (EXTMEM_SFDP_OK == SFDP_ReadHeader(Object, sfdp_header)) + { + retr = EXTMEM_SFDP_OK; + } + + if (table_config[index].PhyLink < PHY_LINK_4S4S4S) + { + /* Config 1 is invalid so exit the loop */ + break; + } + } + } + return retr; +} + +SFDP_StatusTypeDef SFDP_CollectData(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *Object) +{ + SFDP_StatusTypeDef retr = EXTMEM_SFDP_OK; + uint32_t sfdp_address = SFDP_HEADER_SIZE; + SFDP_DEBUG_STR(__func__); + + /* reset the table mask */ + Object->sfdp_private.Sfdp_table_mask = 0; + + /* reset the param info */ + (void)memset(sfdp_param_info, 0x0, sizeof(sfdp_param_info)); + + /* get the table param info */ + for(uint8_t index = 0u; index < (Object->sfdp_private.Sfdp_param_number + 1u); index++) + { + CHECK_FUNCTION_CALL(sfdp_get_paraminfo(Object, sfdp_address, &sfdp_param_info[index])) + Object->sfdp_private.Sfdp_table_mask |= (uint32_t)sfdp_param_info[index].type; + sfdp_address+= SFDP_PARAM_HEADER_SIZE; + } + + /* Read each table param to extract the information to build the driver */ + for (uint8_t index = 0u; sfdp_param_info[index].type != SFDP_PARAMID_UNKNOWN; index++) + { + uint8_t *ptr = NULL; + uint32_t size = sfdp_param_info[index].size; + switch(sfdp_param_info[index].type) + { + case SFDP_PARAMID_BASIC_SPIPROTOCOL: + JEDEC_Basic.size = sfdp_param_info[index].size; + ptr = JEDEC_Basic.Params.data_BYTE; + break; + case SFDP_PARAMID_4BYTE_ADDRESS_INSTRUCTION: + ptr = JEDEC_Address4Bytes.data_BYTE; + break; + case SFDP_PARAMID_STATUS_CONTROL_CONFIG_REGISTER_MAP: + ptr = JEDEC_SCCR_Map.data_b; + break; + case SFDP_PARAMID_XSPI_V1_0: + ptr = JEDEC_XSPI10.data_BYTE; + break; + case SFDP_PARAMID_OCTAL_DDR: + ptr = JEDEC_OctalDdr.data_BYTE; + break; + default : + SFDP_DEBUG_STR("the table is not yet handled by the SW"); + break; + } + if (ptr != NULL) + { + if (HAL_OK != SAL_XSPI_GetSFDP(&Object->sfdp_private.SALObject, + sfdp_param_info[index].address, + ptr, size * 4u)) + { + retr = EXTMEM_SFDP_ERROR_DRIVER; + goto error; + } + } + + if (SFDP_PARAMID_BASIC_SPIPROTOCOL == sfdp_param_info[index].type) + { + /* save data about the reset procedure */ + Object->sfdp_private.Reset_info = JEDEC_Basic.Params.Param_DWORD.D16.SoftResetRescueSequence_Support; + } + } + +error: + return retr; +} + +SFDP_StatusTypeDef SFDP_MemoryReset(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *Object) +{ + RESET_METHOD reset_method; + SFDP_StatusTypeDef retr = EXTMEM_SFDP_ERROR_NO_PARAMTABLE_BASIC; + uint32_t sfdp_address = SFDP_HEADER_SIZE; + uint8_t find = 0u; + SFDP_DEBUG_STR(__func__); + + /* get the table param info */ + for(uint8_t index = 0u; index < (Object->sfdp_private.Sfdp_param_number + 1u); index++) + { + retr = sfdp_get_paraminfo(Object, sfdp_address, &sfdp_param_info[0]); + if (EXTMEM_SFDP_OK == retr) + { + /* check if the table is basic table */ + if (SFDP_PARAMID_BASIC_SPIPROTOCOL == sfdp_param_info[0].type) + { + /* read the JEDEC basic param */ + if (HAL_OK != SAL_XSPI_GetSFDP(&Object->sfdp_private.SALObject, + sfdp_param_info[0].address, + JEDEC_Basic.Params.data_BYTE, + ((uint32_t)sfdp_param_info[0].size) * 4u)) + { + retr = EXTMEM_SFDP_ERROR_DRIVER; + } + else + { + retr = EXTMEM_SFDP_OK; + find = 1u; + } + } + } + + if ((EXTMEM_SFDP_OK != retr) || (1u == find)) + { + /* stop the read, if there is an error or if the table has been found */ + break; + } + /* look for the next table */ + sfdp_address+= SFDP_PARAM_HEADER_SIZE; + } + + /* if an error has been returned or if the table has not been found */ + if ((EXTMEM_SFDP_OK != retr) || (0u == find)) + { + retr = EXTMEM_SFDP_ERROR_DRIVER; + goto error; + } + + /* determine how to proceed memory reset */ + if( 0x0u == JEDEC_Basic.Params.Param_DWORD.D16.SoftResetRescueSequence_Support) + { + /* 00_0000b: no software reset instruction is supported */ + reset_method = RESET_NONE; + } + else if (0x1u == (0x1u & JEDEC_Basic.Params.Param_DWORD.D16.SoftResetRescueSequence_Support)) + { + /* xx_xxx1b: drive Fh on all 4 data wires for 8 clocks */ + reset_method = RESET_Fh_4DATA_8CLOCK; + } + else if (0x2u == (0x2u & JEDEC_Basic.Params.Param_DWORD.D16.SoftResetRescueSequence_Support)) + { + /* xx_xx1xb: drive Fh on all 4 data wires for 10 clocks if device is operating in 4-byte address mode */ + reset_method = RESET_Fh_4DATA_10CLOCK; + } + else if (0x4u == (0x4u & JEDEC_Basic.Params.Param_DWORD.D16.SoftResetRescueSequence_Support)) + { + /* xx_x1xxb: drive Fh on all 4 data wires for 16 clocks */ + reset_method = RESET_Fh_4DATA_16CLOCK; + } + else if (0x8u == (0x8u & JEDEC_Basic.Params.Param_DWORD.D16.SoftResetRescueSequence_Support)) + { + /* xx_1xxxb: issue instruction F0h */ + reset_method = RESET_INSTRUCTION_F0; + } + else if (0x10u == (0x10u & JEDEC_Basic.Params.Param_DWORD.D16.SoftResetRescueSequence_Support)) + { + /* x1_xxxxb: issue reset enable instruction 66h, then issue reset instruction 99h. The reset enable, + reset sequence may be issued on 1, 2, or 4 wires depending on the device operating mode. + */ + reset_method = RESET_INSTRUCTION_66_99; + } + else if (0x20u == (0x20u & JEDEC_Basic.Params.Param_DWORD.D16.SoftResetRescueSequence_Support)) + { + /* 1x_xxxxb: exit 0-4-4 mode is required prior to other reset sequences above if the device may be + operating in this mode. See 6.4.18, 0-4-4 Mode Exit + */ + /* JEDEC_Basic.Params.Param_DWORD.D16.Exit4ByteAddressing + Exit 4-Byte Addressing + xx_xxxx_xxx1b: issue instruction E9h to exit 4-Byte address mode (write enable instruction 06h is not required) + xx_xxxx_xx1xb: issue write enable instruction 06h, then issue instruction E9h to exit 4-Byte address mode + xx_xxxx_x1xxb: 8-bit volatile extended address register used to define A[31:A24] bits. Read with instruction C8h. Write instruction is C5h, data length is 1 byte. Return to lowest memory segment by setting A[31:24] to 00h and use 3-Byte addressing. + xx_xxxx_1xxxb: 8-bit volatile bank register used to define A[30:A24] bits. MSB (bit[7]) is used to enable/disable 4-byte address mode. When MSB is cleared to 0, 3-byte address mode is active and A30:A24 are used to select the active 128 Mbit memory segment. Read with instruction 16h. Write instruction is 17h, data length is 1 byte. + xx_xxx1_xxxxb: A 16-bit nonvolatile configuration register controls 3-Byte/4-Byte address mode. Read instruction is B5h. Bit[0] controls address mode [0=3-Byte; 1=4-Byte]. Write configuration register instruction is B1h, data length is 2 bytes. + xx_xx1x_xxxxb: Hardware reset + xx_x1xx_xxxxb: Software reset (see bits 13:8 in this DWORD) + xx_1xxx_xxxxb: Power cycle + x1_xxxx_xxxxb: Reserved + */ + retr = EXTMEM_SFDP_ERROR_NOTYETHANDLED; + goto error; + } + else + { + /* no coherence, should be managed as error */ + retr = EXTMEM_SFDP_ERROR_DRIVER; + goto error; + } + + switch(reset_method) + { + case RESET_NONE: + break; + case RESET_INSTRUCTION_66_99: + /* perform the reset in 1, 2 and 4 lines */ + SFDP_DEBUG_STR("::reset 0x66 0x99"); + (void)SAL_XSPI_CommandSendData(&Object->sfdp_private.SALObject, 0x66, NULL, 0); + (void)SAL_XSPI_CommandSendData(&Object->sfdp_private.SALObject, 0x99, NULL, 0); + break; + case RESET_INSTRUCTION_F0: + case RESET_Fh_4DATA_8CLOCK: + case RESET_Fh_4DATA_10CLOCK: + case RESET_Fh_4DATA_16CLOCK: + retr = EXTMEM_SFDP_ERROR_NOTYETHANDLED; + break; + /* case RESET_ERROR:*/ + default : + retr = EXTMEM_SFDP_ERROR_PARAM; + break; + } +error : + return retr; +} + +SFDP_StatusTypeDef SFDP_BuildGenericDriver(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *Object, uint8_t *FreqUpdated) +{ + SFDP_StatusTypeDef retr = EXTMEM_SFDP_OK; + static const uint16_t block_erase_unit[] = { 16u, 256u, 4000u, 64000u}; + static const uint32_t chip_erase_unit[] = { 16u, 256u, 4000u, 64000u}; + SFDP_DEBUG_STR(__func__); + uint8_t flag4byteAddress = 0u; + uint32_t dummyCycles, dummyCyclesValue; + uint8_t FlashSize; + + if ((Object->sfdp_private.Sfdp_table_mask & (uint32_t)SFDP_PARAMID_BASIC_SPIPROTOCOL) != (uint32_t)SFDP_PARAMID_BASIC_SPIPROTOCOL) + { + /* This table is mandatory to build the driver data */ + retr = EXTMEM_SFDP_ERROR_NO_PARAMTABLE_BASIC; + goto error; + } + + /* --------------------------------------------------- + * Flash sizing + * --------------------------------------------------- + */ + /* Calculation of the flash density in puissance of 2 */ + if ((JEDEC_Basic.Params.Param_DWORD.D2.FlashSize & 0x80000000u) == 0x0u) + { +#if( __CORTEX_M == 0) +#error "the assembly instruction is not available" +#else + Object->sfdp_private.FlashSize = 31u - (uint8_t)__CLZ((JEDEC_Basic.Params.Param_DWORD.D2.FlashSize + 1u)); +#endif /* __CORTEX_M */ + } + else + { + Object->sfdp_private.FlashSize = (uint8_t)(JEDEC_Basic.Params.Param_DWORD.D2.FlashSize & 0x7FFFFFFFu); + } + + /* Conversion bit to byte */ + Object->sfdp_private.FlashSize = Object->sfdp_private.FlashSize - 3u; /* divide by eight the value */ + + SFDP_DEBUG_INT("-> flash size: 2^", Object->sfdp_private.FlashSize); + FlashSize = Object->sfdp_private.FlashSize - 1u; + (void) SAL_XSPI_MemoryConfig(&Object->sfdp_private.SALObject, PARAM_FLASHSIZE, &FlashSize); + + /* get the page size info */ + Object->sfdp_private.PageSize = ((uint32_t)1u << JEDEC_Basic.Params.Param_DWORD.D11.PageSize); + + /* --------------------------------------------------- + * Set default command + * --------------------------------------------------- + */ + Object->sfdp_private.DriverInfo.PageProgramInstruction = SFDP_DRIVER_PAGE_PROGRAM_COMMAND; + + + /* --------------------------------------------------- + * Erase management + * --------------------------------------------------- + */ + /* Manage erase data */ + Object->sfdp_private.DriverInfo.EraseType1Size = (uint8_t)JEDEC_Basic.Params.Param_DWORD.D8.EraseType1_Size; + Object->sfdp_private.DriverInfo.EraseType1Command = (uint8_t)JEDEC_Basic.Params.Param_DWORD.D8.EraseType1_Instruction; + Object->sfdp_private.DriverInfo.EraseType2Size = (uint8_t)JEDEC_Basic.Params.Param_DWORD.D8.EraseType2_Size; + Object->sfdp_private.DriverInfo.EraseType2Command = (uint8_t)JEDEC_Basic.Params.Param_DWORD.D8.EraseType2_Instruction; + Object->sfdp_private.DriverInfo.EraseType3Size = (uint8_t)JEDEC_Basic.Params.Param_DWORD.D9.EraseType3_Size; + Object->sfdp_private.DriverInfo.EraseType3Command = (uint8_t)JEDEC_Basic.Params.Param_DWORD.D9.EraseType3_Instruction; + Object->sfdp_private.DriverInfo.EraseType4Size = (uint8_t)JEDEC_Basic.Params.Param_DWORD.D9.EraseType4_Size; + Object->sfdp_private.DriverInfo.EraseType4Command = (uint8_t)JEDEC_Basic.Params.Param_DWORD.D9.EraseType4_Instruction; + + if (Object->sfdp_private.DriverInfo.EraseType1Command != 0x0u) + { + Object->sfdp_private.DriverInfo.EraseType1Timing = (uint32_t)JEDEC_Basic.Params.Param_DWORD.D10.MutliplierEraseTime * (JEDEC_Basic.Params.Param_DWORD.D10.EraseType1_TypicalTime_count + 1u)* block_erase_unit[JEDEC_Basic.Params.Param_DWORD.D10.EraseType1_TypicalTime_units]; + } + + if (Object->sfdp_private.DriverInfo.EraseType2Command != 0x0u) + { + Object->sfdp_private.DriverInfo.EraseType2Timing = (uint32_t)JEDEC_Basic.Params.Param_DWORD.D10.MutliplierEraseTime * (JEDEC_Basic.Params.Param_DWORD.D10.EraseType2_TypicalTime_count + 1u)* block_erase_unit[JEDEC_Basic.Params.Param_DWORD.D10.EraseType2_TypicalTime_units]; + } + + if (Object->sfdp_private.DriverInfo.EraseType3Command != 0x0u) + { + Object->sfdp_private.DriverInfo.EraseType3Timing = (uint32_t)JEDEC_Basic.Params.Param_DWORD.D10.MutliplierEraseTime * (JEDEC_Basic.Params.Param_DWORD.D10.EraseType3_TypicalTime_count + 1u)* block_erase_unit[JEDEC_Basic.Params.Param_DWORD.D10.EraseType3_TypicalTime_units]; + } + + if (Object->sfdp_private.DriverInfo.EraseType4Command != 0x0u) + { + Object->sfdp_private.DriverInfo.EraseType4Timing = (uint32_t)JEDEC_Basic.Params.Param_DWORD.D10.MutliplierEraseTime * (JEDEC_Basic.Params.Param_DWORD.D10.EraseType4_TypicalTime_count + 1u)* block_erase_unit[JEDEC_Basic.Params.Param_DWORD.D10.EraseType4_TypicalTime_units]; + } + + Object->sfdp_private.DriverInfo.EraseChipTiming = JEDEC_Basic.Params.Param_DWORD.D10.MutliplierEraseTime * (JEDEC_Basic.Params.Param_DWORD.D11.ChipErase_TypicalTime_count + 1u)* chip_erase_unit[JEDEC_Basic.Params.Param_DWORD.D11.ChipErase_TypicalTime_units]; + + /* ------------------------------------------------------ + * WIP/WEL : write in progress/ write enable management + * ------------------------------------------------------ + */ + /* This bit definition is maintained for legacy compatibility only. New system implementations + should refer to 6.4.19 for a full definition of volatile and non-volatile behavior. */ + Object->sfdp_private.DriverInfo.ReadWELCommand = SFDP_DRIVER_READ_STATUS_REGISTER_COMMAND; + Object->sfdp_private.DriverInfo.ReadWIPCommand = SFDP_DRIVER_READ_STATUS_REGISTER_COMMAND; + if (JEDEC_Basic.Params.Param_DWORD.D1.WriteEnableInstructionVolatileRegister == 0u) + { + Object->sfdp_private.DriverInfo.WriteWELCommand = SFDP_DRIVER_WRITE_ENABLE_50H_COMMAND; + } + else + { + Object->sfdp_private.DriverInfo.WriteWELCommand = SFDP_DRIVER_WRITE_ENABLE_06H_COMMAND; + } + + /* Volatile or Non-Volatile Register and Write Enable Instruction for Status Register 1 + The instruction 01h is typically used to write status register 1 which contains Block Protection (BP) and other bits. Status register 1 is written by the first data byte following the instruction 01h. The protection bits must be written to zero to enable writes/erases to the device. + This field describes how to modify the writable bits in status register 1 in either a volatile or non-volatile manner. Bits 1:0 in status register 1 are de-facto standard write enable and busy status and are excluded from the definitions below. + */ + /* xxx_xxx1b: Non-Volatile Status Register 1, powers-up to last written value, use instruction 06h to enable write */ + if ((JEDEC_Basic.Params.Param_DWORD.D16.VolatileNonVolatileRegister_WriteEnable & 0x1u) != 0u) + { + Object->sfdp_private.DriverInfo.WriteWELCommand = SFDP_DRIVER_WRITE_ENABLE_06H_COMMAND; + } + /* xxx_xx1xb: Volatile Status Register 1, status register powers-up with bits set to "1"s, use instruction 06h to enable write */ + else if ((JEDEC_Basic.Params.Param_DWORD.D16.VolatileNonVolatileRegister_WriteEnable & 0x02u) != 0u) + { + Object->sfdp_private.DriverInfo.WriteWELCommand = SFDP_DRIVER_WRITE_ENABLE_06H_COMMAND; + } + /* xxx_x1xxb: Volatile Status Register 1, status register powers-up with bits set to "1"s, use instruction 50h to enable write */ + else if ((JEDEC_Basic.Params.Param_DWORD.D16.VolatileNonVolatileRegister_WriteEnable & 0x04u) != 0u) + { + Object->sfdp_private.DriverInfo.WriteWELCommand = SFDP_DRIVER_WRITE_ENABLE_50H_COMMAND; + } + /* xxx_1xxxb: Non-Volatile/Volatile status register 1 powers-up to last written value in the non-volatile status register, + use instruction 06h to enable write to non-volatile status register. Volatile status register may be activated after + power-up to override the non-volatile status register, use instruction 50h to enable write and activate the volatile + status register.*/ + else if ((JEDEC_Basic.Params.Param_DWORD.D16.VolatileNonVolatileRegister_WriteEnable & 0x08u) != 0u) + { + Object->sfdp_private.DriverInfo.WriteWELCommand = SFDP_DRIVER_WRITE_ENABLE_06H_COMMAND; + } + /* xx1_xxxxb: Status Register 1 contains a mix of volatile and non-volatile bits. The 06h instruction is used to + enable writing of the register.*/ + else if ((JEDEC_Basic.Params.Param_DWORD.D16.VolatileNonVolatileRegister_WriteEnable & 0x10u) != 0u) + { + Object->sfdp_private.DriverInfo.WriteWELCommand = SFDP_DRIVER_WRITE_ENABLE_06H_COMMAND; + } + /* x1x_xxxxb: Reserved + 1xx_xxxxb: Reserved + NOTE If the status register is read-only then this field will contain all zeros in bits 4:0. + */ + else + { + retr = EXTMEM_SFDP_ERROR_JEDECBASIC_D16; + goto error; + } + + if(0u != (Object->sfdp_private.Sfdp_table_mask & (uint32_t)SFDP_PARAMID_STATUS_CONTROL_CONFIG_REGISTER_MAP)) + { + /* WIP */ + if (0u != JEDEC_SCCR_Map.Param_DWORD.D5.WIPBitAvailable) + { + Object->sfdp_private.DriverInfo.ReadWIPCommand = (uint8_t)JEDEC_SCCR_Map.Param_DWORD.D5.CommandReadAccess; + Object->sfdp_private.DriverInfo.WIPPosition = JEDEC_SCCR_Map.Param_DWORD.D5.WIPBitLocationRegister; + Object->sfdp_private.DriverInfo.WIPBusyPolarity = (uint8_t)JEDEC_SCCR_Map.Param_DWORD.D5.WIPpolarity; + Object->sfdp_private.DriverInfo.WIPPosition = JEDEC_SCCR_Map.Param_DWORD.D5.WIPBitLocationRegister; + + if (0u != JEDEC_SCCR_Map.Param_DWORD.D5.BitAccessedByCommandsUsingAddress) + { + /* Address management */ + Object->sfdp_private.DriverInfo.WIPAddress = (uint8_t)JEDEC_SCCR_Map.Param_DWORD.D5.LocalAddressForWIP; + } + else + { + /* in that case there is no address to manage, the value EXTMEM_ADDRESS_NONE is used to detect the difference */ + Object->sfdp_private.DriverInfo.WIPAddress = EXTMEM_ADDRESS_NONE; + } + } + + /* WEL */ + if (0u != JEDEC_SCCR_Map.Param_DWORD.D6.WELBitAvailable) + { + Object->sfdp_private.DriverInfo.ReadWELCommand = (uint8_t)JEDEC_SCCR_Map.Param_DWORD.D6.CommandReadAccess; + Object->sfdp_private.DriverInfo.WELPosition = JEDEC_SCCR_Map.Param_DWORD.D6.WELBitLocationRegister; + Object->sfdp_private.DriverInfo.WELBusyPolarity = (uint8_t)JEDEC_SCCR_Map.Param_DWORD.D6.WELpolarity; + Object->sfdp_private.DriverInfo.WELPosition = JEDEC_SCCR_Map.Param_DWORD.D6.WELBitLocationRegister; + + if (0u != JEDEC_SCCR_Map.Param_DWORD.D5.BitAccessedByCommandsUsingAddress) + { + /* Address management */ + Object->sfdp_private.DriverInfo.WELAddress = (uint8_t)JEDEC_SCCR_Map.Param_DWORD.D6.WELLocalAddress; + } + else + { + /* in that case there is no address to manage, the value EXTMEM_ADDRESS_NONE is used to detect the difference */ + Object->sfdp_private.DriverInfo.WELAddress = EXTMEM_ADDRESS_NONE; + } + } + } + else + { + Object->sfdp_private.DriverInfo.WELPosition = 1; + Object->sfdp_private.DriverInfo.WELBusyPolarity = 0; + + /* + * WIP : Status register read management + * Basic D14 Status register Polling device Busy + */ + if (0x01u == (JEDEC_Basic.Params.Param_DWORD.D14.StatusRegister & 0x01u)) + { + /* xx_xxx1b: Use of legacy polling is supported by reading the Status Register with 05h instruction + and checking WIP bit[0] (0=ready; 1=busy). */ + Object->sfdp_private.DriverInfo.ReadWIPCommand = SFDP_DRIVER_READ_STATUS_REGISTER_COMMAND; + Object->sfdp_private.DriverInfo.WIPPosition = 0u; + Object->sfdp_private.DriverInfo.WIPBusyPolarity = 0u; + } + else if (0x02u == (JEDEC_Basic.Params.Param_DWORD.D14.StatusRegister & 0x02u)) + { + /* xx_xx1xb: Bit 7 of the Flag Status Register may be polled any time a Program, Erase, Suspend/Resume + command is issued, or after a Reset command while the device is busy. The read instruction is 70h. + Flag Status Register bit definitions: bit[7]: Program or erase controller status (0=busy; 1=ready)*/ + Object->sfdp_private.DriverInfo.ReadWIPCommand = 0x70; + Object->sfdp_private.DriverInfo.WIPPosition = 7u; + Object->sfdp_private.DriverInfo.WIPBusyPolarity = 0u; + } + else + { + retr = EXTMEM_SFDP_ERROR_JEDECBASIC_D14; + goto error; + } + } + + /* Set default value for Read instruction */ + Object->sfdp_private.DriverInfo.ReadInstruction = SFDP_DRIVER_READ_COMMAND; + + /* --------------------------------------------------- + * command based on SFDP_PARAMID_BASIC_SPIPROTOCOL + * --------------------------------------------------- + */ + if (((Object->sfdp_private.Sfdp_table_mask & (uint32_t)SFDP_PARAMID_BASIC_SPIPROTOCOL) + == (uint32_t)SFDP_PARAMID_BASIC_SPIPROTOCOL) + && (Object->sfdp_private.Config < EXTMEM_LINK_CONFIG_8LINES)) + { + dummyCycles = 0; + Object->sfdp_private.DriverInfo.SpiPhyLink = PHY_LINK_1S1S1S; + + if (Object->sfdp_private.Config > EXTMEM_LINK_CONFIG_1LINE) + { + /* control if read 1s1s2s is available */ + if (JEDEC_Basic.Params.Param_DWORD.D4._1S1S2S_FastReadInstruction != 0u) + { + dummyCycles = JEDEC_Basic.Params.Param_DWORD.D4._1S1S2S_DummyClock + JEDEC_Basic.Params.Param_DWORD.D4._1S1S2S_ModeClock; + Object->sfdp_private.DriverInfo.ReadInstruction = (uint8_t)JEDEC_Basic.Params.Param_DWORD.D4._1S1S2S_FastReadInstruction; + Object->sfdp_private.DriverInfo.SpiPhyLink = PHY_LINK_1S1S2S; + } + + /* control if read 1S2S2S is available */ + if (JEDEC_Basic.Params.Param_DWORD.D4._1S2S2S_FastReadInstruction != 0u) + { + dummyCycles = JEDEC_Basic.Params.Param_DWORD.D4._1S2S2S_DummyClock + JEDEC_Basic.Params.Param_DWORD.D4._1S2S2S_ModeClock; + Object->sfdp_private.DriverInfo.ReadInstruction = (uint8_t)JEDEC_Basic.Params.Param_DWORD.D4._1S2S2S_FastReadInstruction; + Object->sfdp_private.DriverInfo.SpiPhyLink = PHY_LINK_1S2S2S; + } + + /* The memory work only in 2S2S2S */ + if (JEDEC_Basic.Params.Param_DWORD.D5._2S2S2S_FastReadSupport != 0u) + { + dummyCycles = JEDEC_Basic.Params.Param_DWORD.D6._2S2S2S_DummyClock + JEDEC_Basic.Params.Param_DWORD.D6._2S2S2S_ModeClock; + Object->sfdp_private.DriverInfo.ReadInstruction = (uint8_t)JEDEC_Basic.Params.Param_DWORD.D6._2S2S2S_FastReadInstruction; + } + } + + /* the command set is only based on this table */ + /* determine the best line configuration */ + if (Object->sfdp_private.Config > EXTMEM_LINK_CONFIG_2LINES) + { + if (JEDEC_Basic.Params.Param_DWORD.D5._4S4S4S_FastReadSupport != 0u) + { + dummyCycles = JEDEC_Basic.Params.Param_DWORD.D7._4S4S4S_DummyClock + JEDEC_Basic.Params.Param_DWORD.D7._4S4S4S_ModeClock; + Object->sfdp_private.DriverInfo.ReadInstruction = (uint8_t)JEDEC_Basic.Params.Param_DWORD.D7._4S4S4S_FastReadInstruction; + Object->sfdp_private.DriverInfo.SpiPhyLink = PHY_LINK_4S4S4S; + + retr = JEDEC_Basic_Manage4S4S4SEnableSequence(Object); + if ( retr != EXTMEM_SFDP_OK) + { + goto error; + } + } + else /* other configuration with more 4 lines */ + { + /* not yet handled */ + } + SAL_XSPI_SET_SFDPDUMMYCYLE(Object->sfdp_private.SALObject, (uint8_t)dummyCycles); + +#if defined(IS25WP032D_ENABLE_DTR) + /* Check support of DTR feature (DTR Support in D1) */ + if (JEDEC_Basic.Params.Param_DWORD.D1.Support_DTR == 1u) + { + /* Additional information regarding DTR read instruction and dummy cycles might be present in + D21 : Fast Read (1S-1D-1D), (1S-2D-2D), (1S-4D-4D), and (4S-4D-4D) Support + and + D23 : Fast Read (1S-4D-4D) and (4S-4D-4D) Wait States, Mode Bit Clocks, and Instruction */ + /* Extract values for 4S4D4D */ + if (JEDEC_Basic.Params.Param_DWORD.D21._4S4D4D_FastReadSupport == 1u) + { + dummyCycles = JEDEC_Basic.Params.Param_DWORD.D23._4S4D4D_DummyClock + JEDEC_Basic.Params.Param_DWORD.D23._4S4D4D_ModeClock; + Object->sfdp_private.DriverInfo.ReadInstruction = (uint8_t)JEDEC_Basic.Params.Param_DWORD.D23._4S4D4D_FastReadInstruction; + Object->sfdp_private.DriverInfo.SpiPhyLink = PHY_LINK_4S4D4D; + } + else + { + /* Other specific cases to be managed : for example, when Basic Flash Parameter Table is not long enough + and D21, ... are not provided by the card. Specific cases section might have to be updated when adding + support for new memories whose SFDP paramter table is not complete */ + + /* Specific case for ISSI memories */ + if (Object->sfdp_private.ManuID == EXTMEM_MANFACTURER_ISSI) /* ISSI manufacturer ID */ + { + dummyCycles = 6u; + Object->sfdp_private.DriverInfo.ReadInstruction = 0x0D; + Object->sfdp_private.DriverInfo.SpiPhyLink = PHY_LINK_4S4D4D; + SAL_XSPI_SET_DTRREADDUMMYCYLE(Object->sfdp_private.SALObject, (uint8_t)dummyCycles); + } + + } + } +#endif /* IS25WP032D_ENABLE_DTR */ + + } + + /* Configure the link */ + if (HAL_OK != SAL_XSPI_MemoryConfig(&Object->sfdp_private.SALObject, PARAM_PHY_LINK, &Object->sfdp_private.DriverInfo.SpiPhyLink)) + { + retr = EXTMEM_SFDP_ERROR_DRIVER; + goto error; + } + + if (HAL_OK != SAL_XSPI_MemoryConfig(&Object->sfdp_private.SALObject, PARAM_DUMMY_CYCLES, &dummyCycles)) + { + retr = EXTMEM_SFDP_ERROR_DRIVER; + goto error; + } + } + + /* ------------------------------------------------------------------------------------------------------------------- + If an octal DDR table is present and the target is 8D8D8D, + when switch in octal DDR mode + ------------------------------------------------------------------------------------------------------------------- + */ + if (((uint32_t)SFDP_PARAMID_OCTAL_DDR == (Object->sfdp_private.Sfdp_table_mask & (uint32_t)SFDP_PARAMID_OCTAL_DDR)) + && (EXTMEM_LINK_CONFIG_8LINES == Object->sfdp_private.Config)) + { + /* check if we are not already in octal mode */ + if (PHY_LINK_8D8D8D == Object->sfdp_private.DriverInfo.SpiPhyLink) + { + flag4byteAddress = 1u; + } + else + { + /* Execute the flash command sequence to switch in octal DDR */ + if (EXTMEM_SFDP_OK == sfdp_enter_octal_mode(Object)) + { + /* switch the memory interface configuration according to the Access protocol field */ + flag4byteAddress = 1u; + /* Specific case of GigaDevice memory GD25LX512ME whose Instruction mode remains on 8S (8bit commands) */ + if (Object->sfdp_private.ManuID == EXTMEM_MANFACTURER_GIGADEVICE) + { + Object->sfdp_private.DriverInfo.SpiPhyLink = PHY_LINK_8S8D8D; + } + else + { + Object->sfdp_private.DriverInfo.SpiPhyLink = PHY_LINK_8D8D8D; + } + + /* update the physical link */ + if (HAL_OK != SAL_XSPI_MemoryConfig(&Object->sfdp_private.SALObject, PARAM_PHY_LINK, &Object->sfdp_private.DriverInfo.SpiPhyLink)) + { + retr = EXTMEM_SFDP_ERROR_DRIVER; + goto error; + } + + if (Object->sfdp_private.Sfdp_AccessProtocol == 0xFDu) + { + /* set 20 wait state */ + dummyCycles = 20; + (void)SAL_XSPI_MemoryConfig(&Object->sfdp_private.SALObject, PARAM_DUMMY_CYCLES, (void*)&dummyCycles); + } + if (Object->sfdp_private.Sfdp_AccessProtocol == 0xFEu) + { + /* set 8 wait state */ + dummyCycles = 8; + (void)SAL_XSPI_MemoryConfig(&Object->sfdp_private.SALObject, PARAM_DUMMY_CYCLES, (void*)&dummyCycles); + } + } + else + { + /* an error occurs when trying to switch the mode */ + /* when continue the process and check if another mode could be targeted */ + } + } + + if ((0u != (Object->sfdp_private.Sfdp_table_mask & (uint32_t)SFDP_PARAMID_BASIC_SPIPROTOCOL)) && + (JEDEC_Basic.size > 16u)) + { + /* check octal information to determine */ + /* 0b00 The Command Extension is the same as the Command. (The Command / Command Extension has the same value for the whole clock period.)*/ + /* 0b01 The Command Extension is the inverse of the Command. The Command Extension acts as a confirmation of the Command */ + /* 0b11 Command and Command Extension forms a 16-bit command word */ + if (JEDEC_Basic.Params.Param_DWORD.D18.OctalDTRCommandExtension > 1u) + { + retr = EXTMEM_SFDP_ERROR_NOTYETHANDLED; + goto error; + } + SAL_XSPI_SET_COMMANDEXTENSION(Object->sfdp_private.SALObject, (uint8_t)JEDEC_Basic.Params.Param_DWORD.D18.OctalDTRCommandExtension); + } + } + + /* Check WIP flag with new access mode */ + if (EXTMEM_DRIVER_NOR_SFDP_OK != driver_check_FlagBUSY(Object, 100u)) + { + retr = EXTMEM_SFDP_ERROR_DRIVER; + goto error; + } + + if ((Object->sfdp_private.Sfdp_table_mask & (uint32_t)SFDP_PARAMID_4BYTE_ADDRESS_INSTRUCTION) == (uint32_t)SFDP_PARAMID_4BYTE_ADDRESS_INSTRUCTION) + { + if (0u == flag4byteAddress) + { + /* xxxx_xxx1b: issue instruction B7h (preceding write enable not required) */ + if (0x01u == (JEDEC_Basic.Params.Param_DWORD.D16.Enter4ByteAddressing & 0x01u)) + { + /* send command to enter 4-bytes Address mode */ + if (HAL_OK != SAL_XSPI_CommandSendData(&Object->sfdp_private.SALObject,0xB7, NULL, 0)) + { + retr = EXTMEM_SFDP_ERROR_DRIVER; + goto error; + } + + /* Set 4-Byte addressing on PHY side */ + if (HAL_OK != SAL_XSPI_MemoryConfig(&Object->sfdp_private.SALObject, PARAM_ADDRESS_4BYTES, NULL)) + { + retr = EXTMEM_SFDP_ERROR_DRIVER; + goto error; + } + + /* flag4byteAddress = 1u; this setting is not needed because variable is no more used */ + } + /* xxxx_xx1xb: issue write enable instruction 06h, then issue instruction B7h */ + else if (0x2u == (JEDEC_Basic.Params.Param_DWORD.D16.Enter4ByteAddressing & 0x2u)) + { + /* send command to write enable */ + if (HAL_OK != SAL_XSPI_CommandSendData(&Object->sfdp_private.SALObject, + Object->sfdp_private.DriverInfo.WriteWELCommand, NULL, 0u)) + { + retr = EXTMEM_SFDP_ERROR_DRIVER; + goto error; + } + + /* control the write enable */ + if (HAL_OK != SAL_XSPI_CheckStatusRegister(&Object->sfdp_private.SALObject, + Object->sfdp_private.DriverInfo.ReadWELCommand, + Object->sfdp_private.DriverInfo.WELAddress, + ((Object->sfdp_private.DriverInfo.WELBusyPolarity == 0u) ? 1u: 0u) << Object->sfdp_private.DriverInfo.WELPosition, + 1u << Object->sfdp_private.DriverInfo.WELPosition, + Object->sfdp_private.ManuID, 1000)) + { + retr = EXTMEM_SFDP_ERROR_DRIVER; + goto error; + } + + /* send command to enter 4-bytes Address mode */ + if (HAL_OK != SAL_XSPI_CommandSendData(&Object->sfdp_private.SALObject, 0xB7, NULL, 0u)) + { + retr = EXTMEM_SFDP_ERROR_DRIVER; + goto error; + } + } + /* x1xx_xxxxb: Always operates in 4-Byte address mode */ + else if (0x40u == (JEDEC_Basic.Params.Param_DWORD.D16.Enter4ByteAddressing & 0x40u)) + { + /* nothing to do */ + /* flag4byteAddress = 1u; this setting is not needed because variable is no more used */ + } + /* xx1x_xxxxb: Supports dedicated 4-Byte address instruction set. Consult vendor data sheet for the instruction set definition.*/ + else if (0x20u == (JEDEC_Basic.Params.Param_DWORD.D16.Enter4ByteAddressing & 0x20u)) + { + /* specific memory */ + /* on Macronix nothing to do the command are 4Byte specific so nothing to do */ + /* flag4byteAddress = 1u; this setting is not needed because variable is no more used */ + } + /* xxxx_x1xxb: 8-bit volatile extended address register used to define A[31:24] bits. Read with instruction C8h. Write instruction is C5h with 1 byte of data. Select the active 128 Mbit memory segment by setting the appropriate A[31:24] bits and use 3-Byte addressing. + xxxx_1xxxb: 8-bit volatile bank register used to define A[30:A24] bits. MSB (bit[7]) is used to enable/disable 4-byte address mode. When MSB is set to 1, 4-byte address mode is active and A[30:24] bits are do not care. Read with instruction 16h. Write instruction is 17h with 1 byte of data. When MSB is cleared to 0, select the active 128 Mbit segment by setting the appropriate A[30:24] bits and use 3-Byte addressing. + xxx1_xxxxb: A 16-bit nonvolatile configuration register controls 3-Byte/4-Byte address mode. Read instruction is B5h. Bit[0] controls address mode [0=3-Byte;1=4-Byte]. Write configuration register instruction is B1h, data length is 2 bytes. + */ + else { + retr = EXTMEM_SFDP_ERROR_NOTYETHANDLED; + goto error; + + } + + /* Set 4 bytes addressing on PHY side */ + if (HAL_OK != SAL_XSPI_MemoryConfig(&Object->sfdp_private.SALObject, PARAM_ADDRESS_4BYTES, NULL)) + { + retr = EXTMEM_SFDP_ERROR_DRIVER; + goto error; + } + + /* Set the read function for 4 bytes Address */ + Object->sfdp_private.DriverInfo.ReadInstruction = 0x13U; + } + + if ((EXTMEM_LINK_CONFIG_8LINES == Object->sfdp_private.Config) && (PHY_LINK_1S1S1S == Object->sfdp_private.DriverInfo.SpiPhyLink)) + { + /* check if we can switch to if the config is still 1S8S8S */ + if ((0u != JEDEC_Address4Bytes.Param_DWORD.D1.Support_1S8S8S_FastReadCommand) && (0u != JEDEC_Address4Bytes.Param_DWORD.D1.Support_1S8S8S_PageProgramCommand)) + { + /* Patch Micron write command 0x81 @0x0 0xE7 */ + Object->sfdp_private.DriverInfo.SpiPhyLink = PHY_LINK_1S8S8S; + if (HAL_OK != SAL_XSPI_MemoryConfig(&Object->sfdp_private.SALObject, PARAM_PHY_LINK, &Object->sfdp_private.DriverInfo.SpiPhyLink)) + { + retr = EXTMEM_SFDP_ERROR_DRIVER; + goto error; + } + Object->sfdp_private.DriverInfo.ReadInstruction = 0xCC; + Object->sfdp_private.DriverInfo.PageProgramInstruction = 0x8E; + } + } + + /* + need to be study more; it seems that Macronix used it to define the command maybe because only one mode is + supported in their case + */ + if ((Object->sfdp_private.DriverInfo.SpiPhyLink == PHY_LINK_8D8D8D) || + (Object->sfdp_private.DriverInfo.SpiPhyLink == PHY_LINK_1S1S1S)) + { + if (0u != JEDEC_Address4Bytes.Param_DWORD.D1.Support_1S1S1S_PageProgramCommand) {Object->sfdp_private.DriverInfo.PageProgramInstruction = 0x12u;} + if (0u != JEDEC_Address4Bytes.Param_DWORD.D1.Support_1S1S1S_ReadCommand) {Object->sfdp_private.DriverInfo.ReadInstruction = 0x13u;} + if (0u != JEDEC_Address4Bytes.Param_DWORD.D1.Support_1S1S1S_FastReadCommand) {Object->sfdp_private.DriverInfo.ReadInstruction = 0x0Cu;} + } + + if (Object->sfdp_private.DriverInfo.SpiPhyLink == PHY_LINK_8S8D8D) + { + if (0u != JEDEC_Address4Bytes.Param_DWORD.D1.Support_1S8S8S_PageProgramCommand) {Object->sfdp_private.DriverInfo.PageProgramInstruction = 0x02u;} + if (0u != JEDEC_Address4Bytes.Param_DWORD.D1.Support_1S8S8S_FastReadCommand) {Object->sfdp_private.DriverInfo.ReadInstruction = 0xCCu;} + if (0u != JEDEC_Address4Bytes.Param_DWORD.D1.Support_1S8D8D_DTRReadCommand) {Object->sfdp_private.DriverInfo.ReadInstruction = 0xFDu;} + } + + Object->sfdp_private.DriverInfo.EraseType1Command = (uint8_t)JEDEC_Address4Bytes.Param_DWORD.D2.InstructionEraseType1; + Object->sfdp_private.DriverInfo.EraseType2Command = (uint8_t)JEDEC_Address4Bytes.Param_DWORD.D2.InstructionEraseType2; + Object->sfdp_private.DriverInfo.EraseType3Command = (uint8_t)JEDEC_Address4Bytes.Param_DWORD.D2.InstructionEraseType3; + Object->sfdp_private.DriverInfo.EraseType4Command = (uint8_t)JEDEC_Address4Bytes.Param_DWORD.D2.InstructionEraseType4; + } + + if(((uint32_t)SFDP_PARAMID_XSPI_V1_0 == (Object->sfdp_private.Sfdp_table_mask & (uint32_t)SFDP_PARAMID_XSPI_V1_0)) + && + ((PHY_LINK_8D8D8D == Object->sfdp_private.DriverInfo.SpiPhyLink) || (PHY_LINK_8S8D8D == Object->sfdp_private.DriverInfo.SpiPhyLink))) + { + uint32_t ClockOut = 0u; + uint32_t MaxFreqMhz; + /* Read command */ + if (0u != JEDEC_XSPI10.Param_DWORD.D1.ReadFastCommand) + { + Object->sfdp_private.DriverInfo.ReadInstruction = (uint8_t)JEDEC_XSPI10.Param_DWORD.D1.ReadFastCommand; + } + + if (JEDEC_XSPI10.Param_DWORD.D6._8D8D8DDefaultPOR_DummyCycle != 0u) + { + /* Set the default dummy cycle of this mode */ + dummyCycles = JEDEC_XSPI10.Param_DWORD.D6._8D8D8DDefaultPOR_DummyCycle; + (void)SAL_XSPI_MemoryConfig(&Object->sfdp_private.SALObject, PARAM_DUMMY_CYCLES, (void*)&dummyCycles); + } + + /* adapt the memory interface frequency according to its capabilities */ + MaxFreqMhz = sfdp_getfrequencevalue(JEDEC_Basic.Params.Param_DWORD.D20._8D8D8D_MaximunSpeedWithStrobe); + if (MaxFreqMhz > Object->sfdp_private.DriverInfo.ClockIn) + { + /* Adjust the frequence with the ClockIn */ + MaxFreqMhz = Object->sfdp_private.DriverInfo.ClockIn; + } + + /* Update the clock to be aligned with selected configuration */ + if(HAL_OK != SAL_XSPI_SetClock(&Object->sfdp_private.SALObject, Object->sfdp_private.DriverInfo.ClockIn, MaxFreqMhz, &ClockOut)) + { + retr = EXTMEM_SFDP_ERROR_SETCLOCK; + goto error; + } + *FreqUpdated = 1u; /* Used to indicate that the clock configuration has been updated */ + + /* get the dummy cycle value according to the real output clock */ + if ((ClockOut >= CLOCK_200MHZ) && (JEDEC_XSPI10.Param_DWORD.D4.Operation200Mhz_DummyCycle != 0u)) + { + dummyCycles = JEDEC_XSPI10.Param_DWORD.D4.Operation200Mhz_DummyCycle; + dummyCyclesValue = JEDEC_XSPI10.Param_DWORD.D4.Operation200Mhz_ConfigPattern; + } + else if ((ClockOut >= CLOCK_166MHZ) && (JEDEC_XSPI10.Param_DWORD.D5.Operation166Mhz_DummyCycle != 0u)) + { + dummyCycles = JEDEC_XSPI10.Param_DWORD.D5.Operation166Mhz_DummyCycle; + dummyCyclesValue = JEDEC_XSPI10.Param_DWORD.D5.Operation166Mhz_ConfigPattern; + } + else if ((ClockOut >= CLOCK_133MHZ) && (JEDEC_XSPI10.Param_DWORD.D5.Operation133Mhz_DummyCycle != 0u)) + { + dummyCycles = JEDEC_XSPI10.Param_DWORD.D5.Operation133Mhz_DummyCycle; + dummyCyclesValue = JEDEC_XSPI10.Param_DWORD.D5.Operation133Mhz_ConfigPattern; + } + else /* if (ClockOut =< 100Mhz) */ + { + dummyCycles = JEDEC_XSPI10.Param_DWORD.D5.Operation100Mhz_DummyCycle; + dummyCyclesValue = JEDEC_XSPI10.Param_DWORD.D5.Operation100Mhz_ConfigPattern; + } + + /* Specific case of GigaDevice memory with wrongly coded SFDP table in JEDEC_SCCR_Map.Param_DWORD.D9 */ + if (Object->sfdp_private.ManuID == EXTMEM_MANFACTURER_GIGADEVICE) + { + dummyCycles = 16; + (void)SAL_XSPI_MemoryConfig(&Object->sfdp_private.SALObject, PARAM_DUMMY_CYCLES, (void*)&dummyCycles); + } + else + { + /* Write the dummy cycle value in the configuration register using information coming from SCCR Map */ + if((0u != (Object->sfdp_private.Sfdp_table_mask & (uint32_t)SFDP_PARAMID_STATUS_CONTROL_CONFIG_REGISTER_MAP)) + && (0u != JEDEC_SCCR_Map.Param_DWORD.D9.BitAvailable)) + { + /* Update the frequence with MaxFreqMhz information */ + if( sfdp_set_dummycycle(Object, dummyCyclesValue) == EXTMEM_SFDP_OK) + { + /* Set the dummy cycle corresponding */ + (void)SAL_XSPI_MemoryConfig(&Object->sfdp_private.SALObject, PARAM_DUMMY_CYCLES, (void*)&dummyCycles); + } + } + else + { + retr = EXTMEM_SFDP_ERROR_CONFIGDUMMY; + goto error; + } + } + } + +error : + return retr; +} + + +EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef driver_check_FlagBUSY(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *SFDPObject, uint32_t Timeout) +{ + EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef retr = EXTMEM_DRIVER_NOR_SFDP_ERROR_BUSY; + SFDP_DEBUG_STR((uint8_t *)__func__) + if (0u != SFDPObject->sfdp_private.DriverInfo.ReadWIPCommand) + { + /* check that the WIP flag is not set */ + if (HAL_OK == SAL_XSPI_CheckStatusRegister(&SFDPObject->sfdp_private.SALObject, + SFDPObject->sfdp_private.DriverInfo.ReadWIPCommand, + SFDPObject->sfdp_private.DriverInfo.WIPAddress, + SFDPObject->sfdp_private.DriverInfo.WIPBusyPolarity << SFDPObject->sfdp_private.DriverInfo.WIPPosition, + 1u << SFDPObject->sfdp_private.DriverInfo.WIPPosition, + SFDPObject->sfdp_private.ManuID, Timeout)) + { + retr = EXTMEM_DRIVER_NOR_SFDP_OK; + } + } + return retr; +} + +/** + * @} + */ + +/** @addtogroup NOR_SFDP_DATA_Functions + * @{ + */ + +/** + * @brief This function returns the frequency value corresponding to a frequency + * @param BitField bit field value + * @return frequency value + */ +uint32_t sfdp_getfrequencevalue(uint32_t BitField) +{ + const uint16_t freqMhz_table[] = { 0x0, 33, 50, 66, 80, 100, 133, 166, 200, 250, 266, 333, 400 }; + SFDP_DEBUG_STR(__func__); + + if (BitField < 0b1010u) + { + return (uint32_t)freqMhz_table[BitField]* 1000000u; + } + return 0; /* the max frequency is unknown */ +} + +/** + * @brief This function reads and checks the SFDP header + * @param Object memory Object + * @param sfdp_address address of the SFDP table + * @param sfdp_param_info pointer on parameter info + * @return @ref SFDP_StatusTypeDef + */ +SFDP_StatusTypeDef sfdp_get_paraminfo(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *Object, uint32_t sfdp_address, + SFDP_ParameterTableTypeDef *Param_info) +{ + SFDP_StatusTypeDef retr = EXTMEM_SFDP_OK; + SFDP_ParameterHeaderTypeDef sfdp_param_header = {0}; + SFDP_DEBUG_STR(__func__); + + /* send the SFDP command to read the header */ + if(HAL_OK != SAL_XSPI_GetSFDP(&Object->sfdp_private.SALObject, sfdp_address, + (uint8_t*)&sfdp_param_header, SFDP_PARAM_HEADER_SIZE)) + { + retr = EXTMEM_SFDP_ERROR_SFDPREAD; + goto error; + } + + Param_info->type = SFDP_PARAMID_UNKNOWN; + Param_info->size = sfdp_param_header.Length ; + Param_info->address = (((uint32_t)sfdp_param_header.TableAddressPointer[2u] << 16u) + |((uint32_t)sfdp_param_header.TableAddressPointer[1u] << 8u) + |((uint32_t)sfdp_param_header.TableAddressPointer[0u])); + + if ((sfdp_param_header.ID_msb > 0x00u) && (sfdp_param_header.ID_msb < 0x80u)) + { + if ((sfdp_param_header.ID_lsb & 0x01u) == 0x01u) + { + Param_info->type = SFDP_PARAMID_VENDOR; + SFDP_DEBUG_STR("-> type SFDP_PARAMID_VENDOR"); + } + else + { + Param_info->type = SFDP_PARAMID_FUNCTION_VENDOR; + SFDP_DEBUG_STR("-> type SFDP_PARAMID_FUNCTION_VENDOR"); + } + } + else if (sfdp_param_header.ID_msb >= 0x80u) + { + if((sfdp_param_header.ID_lsb & 0x01u) == 0x00u) + { + Param_info->type = SFDP_PARAMID_FUNCTION_JEDEC; + SFDP_DEBUG_STR("-> type SFDP_PARAMID_FUNCTION_JEDEC"); + } + + if (sfdp_param_header.ID_msb == SFDP_BASIC_PARAMETER_TABLE_MSB) + { + switch(sfdp_param_header.ID_lsb) + { + case SFDP_BASIC_PARAMETER_TABLE_LSB : + Param_info->type = SFDP_PARAMID_BASIC_SPIPROTOCOL; + SFDP_DEBUG_STR("-> info SFDP_PARAMID_BASIC_SPIPROTOCOL"); + Param_info->size = ((sfdp_param_header.Length ) < SFDP_PARAMS_BASIC_TABLE_DEFAULTSIZE) + ? sfdp_param_header.Length : SFDP_PARAMS_BASIC_TABLE_DEFAULTSIZE; + break; + case 0x81u: + Param_info->type = SFDP_PARAMID_SECTORMAP; + SFDP_DEBUG_STR("-> info SFDP_PARAMID_SECTORMAP"); + break; + case 0x03u: + Param_info->type = SFDP_PARAMID_RPMC; + SFDP_DEBUG_STR("-> info SFDP_PARAMID_RPMC"); + break; + case 0x84u: + Param_info->type = SFDP_PARAMID_4BYTE_ADDRESS_INSTRUCTION; + SFDP_DEBUG_STR("-> info SFDP_PARAMID_4BYTE_ADDRESS_INSTRUCTION"); + break; + case 0x05u: + Param_info->type = SFDP_PARAMID_XSPI_V1_0; + SFDP_DEBUG_STR("-> info SFDP_PARAMID_XSPI_V1_0"); + break; + case 0x06u: + Param_info->type = SFDP_PARAMID_XSPI_V2_0; + SFDP_DEBUG_STR("-> info SFDP_PARAMID_XSPI_V2_0"); + break; + case 0x87u: + Param_info->type = SFDP_PARAMID_STATUS_CONTROL_CONFIG_REGISTER_MAP; + SFDP_DEBUG_STR("-> info SFDP_PARAMID_STATUS_CONTROL_CONFIG_REGISTER_MAP"); + break; + case 0x88u: + Param_info->type = SFDP_PARAMID_STATUS_CONTROL_CONFIG_REGISTER_MAP_MULTICHIP; + SFDP_DEBUG_STR("-> info SFDP_PARAMID_STATUS_CONTROL_CONFIG_REGISTER_MAP_MULTICHIP"); + break; + case 0x09u: + Param_info->type = SFDP_PARAMID_STATUS_CONTROL_CONFIG_XSPI_V2_0; + SFDP_DEBUG_STR("-> info SFDP_PARAMID_STATUS_CONTROL_CONFIG_XSPI_V2_0"); + break; + case 0x0Au: + Param_info->type = SFDP_PARAMID_OCTAL_DDR; + SFDP_DEBUG_STR("-> info SFDP_PARAMID_OCTAL_DDR"); + break; + case 0x8Bu: + Param_info->type = SFDP_PARAMID_MSPT; + SFDP_DEBUG_STR("-> info SFDP_PARAMID_MSPT"); + break; + case 0x0Cu: + Param_info->type = SFDP_PARAMID_X4QUAD_DS; + SFDP_DEBUG_STR("-> info SFDP_PARAMID_X4QUAD_DS"); + break; + case 0x8Du: + Param_info->type = SFDP_PARAMID_QUAD_DDR; + SFDP_DEBUG_STR("-> info SFDP_PARAMID_QUAD_DDR"); + break; + case 0x8Eu: + Param_info->type = SFDP_PARAMID_SECURE_PACKET_READ_WRITE; + SFDP_DEBUG_STR("-> info SFDP_PARAMID_SECURE_PACKET_READ_WRITE"); + break; + case 0x0Fu: + Param_info->type = SFDP_PARAMID_RESERVED; + SFDP_DEBUG_STR("-> info SFDP_PARAMID_RESERVED"); + break; + default : + SFDP_DEBUG_STR("-> info SFDP_PARAMID_????"); + break; + } + } + + if( Param_info->type == SFDP_PARAMID_UNKNOWN) + { + SFDP_DEBUG_STR("-> the table is not compliant with to JEDEC standard"); + } + } + else + { + /* Unexpected value for MSB field of SFDP Parameter ID */ + SFDP_DEBUG_STR("-> Unexpected value for MSB field of SFDP Parameter ID"); + retr = EXTMEM_SFDP_ERROR_SFDPREAD; + goto error; + } + +error: + return retr; +} + +/** + * @brief This function executes the octal DDR table to enter octal DDR mode + * @param Object memory Object + * @return @ref SFDP_StatusTypeDef + */ +SFDP_StatusTypeDef sfdp_enter_octal_mode(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *Object) +{ + SFDP_StatusTypeDef retr = EXTMEM_SFDP_OK; + uint8_t data[7]; + SFDP_DEBUG_STR(__func__); + /* D1-D2 command */ + if (0u != JEDEC_OctalDdr.Param_DWORD.D1.LengthCommand) + { + data[0] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D1.Byte1CommandSequence; + data[1] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D1.Byte2CommandSequence; + data[2] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D1.Byte3CommandSequence; + data[3] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D2.Byte4CommandSequence; + data[4] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D2.Byte5CommandSequence; + data[5] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D2.Byte6CommandSequence; + data[6] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D2.Byte7CommandSequence; + + if (HAL_OK != SAL_XSPI_CommandSendData(&Object->sfdp_private.SALObject, data[0], &data[1], + (uint16_t)(JEDEC_OctalDdr.Param_DWORD.D1.LengthCommand - 1u))) + { + retr = EXTMEM_SFDP_ERROR_OCTALMODE; + goto error; + } + } + + /* D3-D4 command */ + if (0u != JEDEC_OctalDdr.Param_DWORD.D3.LengthCommand) + { + /* wait for busy flag clear */ + if (EXTMEM_DRIVER_NOR_SFDP_OK != driver_check_FlagBUSY(Object, 100u)) + { + retr = EXTMEM_SFDP_ERROR_DRIVER; + goto error; + } + + data[0] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D3.Byte1CommandSequence; + data[1] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D3.Byte2CommandSequence; + data[2] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D3.Byte3CommandSequence; + data[3] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D4.Byte4CommandSequence; + data[4] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D4.Byte5CommandSequence; + data[5] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D4.Byte6CommandSequence; + data[6] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D4.Byte7CommandSequence; + + if (HAL_OK != SAL_XSPI_CommandSendData(&Object->sfdp_private.SALObject, data[0], &data[1], + (uint16_t)(JEDEC_OctalDdr.Param_DWORD.D3.LengthCommand - 1u))) + { + retr = EXTMEM_SFDP_ERROR_OCTALMODE; + goto error; + } + } + + /* D5-D6 command */ + if (0u != JEDEC_OctalDdr.Param_DWORD.D5.LengthCommand) + { + /* wait for busy flag clear */ + if (EXTMEM_DRIVER_NOR_SFDP_OK != driver_check_FlagBUSY(Object, 100u)) + { + retr = EXTMEM_SFDP_ERROR_DRIVER; + goto error; + } + + data[0] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D5.Byte1CommandSequence; + data[1] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D5.Byte2CommandSequence; + data[2] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D5.Byte3CommandSequence; + data[3] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D6.Byte4CommandSequence; + data[4] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D6.Byte5CommandSequence; + data[5] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D6.Byte6CommandSequence; + data[6] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D6.Byte7CommandSequence; + + if (HAL_OK != SAL_XSPI_CommandSendData(&Object->sfdp_private.SALObject, data[0], &data[1], + (uint16_t)(JEDEC_OctalDdr.Param_DWORD.D5.LengthCommand - 1u))) + { + retr = EXTMEM_SFDP_ERROR_OCTALMODE; + goto error; + } + } + + /* D7-D8 command */ + if (0u != JEDEC_OctalDdr.Param_DWORD.D7.LengthCommand) + { + /* wait for busy flag clear */ + if (EXTMEM_DRIVER_NOR_SFDP_OK != driver_check_FlagBUSY(Object, 100u)) + { + retr = EXTMEM_SFDP_ERROR_DRIVER; + goto error; + } + + data[0] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D7.Byte1CommandSequence; + data[1] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D7.Byte2CommandSequence; + data[2] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D7.Byte3CommandSequence; + data[3] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D8.Byte4CommandSequence; + data[4] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D8.Byte5CommandSequence; + data[5] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D8.Byte6CommandSequence; + data[6] = (uint8_t)JEDEC_OctalDdr.Param_DWORD.D8.Byte7CommandSequence; + + if (HAL_OK != SAL_XSPI_CommandSendData(&Object->sfdp_private.SALObject, data[0], &data[1], + (uint16_t)(JEDEC_OctalDdr.Param_DWORD.D7.LengthCommand - 1u))) + { + retr = EXTMEM_SFDP_ERROR_OCTALMODE; + goto error; + } + + /* no more wait for busy flag clear here, as command format might have changed to Octal */ + } + + /* Abort any ongoing transfer to avoid performance issue */ + SAL_XSPI_Abort(&Object->sfdp_private.SALObject); + +error: + return retr; +} + +/** + * @brief This function writes the config register to set dummy cycle + * @param Object memory Object + * @return @ref SFDP_StatusTypeDef + */ +SFDP_StatusTypeDef sfdp_set_dummycycle(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *Object, uint32_t DummyValue) +{ +const uint8_t MaskWaitStateValue[4] = { 0x3u, 0x7u, 0xFu, 0x1Fu }; +SFDP_StatusTypeDef retr = EXTMEM_SFDP_OK; +uint8_t localValue[2] = { 0 }; +uint32_t Address; + + if((JEDEC_SCCR_Map.Param_DWORD.D9.BitAccessedByCommandsUsingAddress == 0u) && + (JEDEC_SCCR_Map.Param_DWORD.D9.BitAvailable == 1u)) + { + /* Not yet supported */ + retr = EXTMEM_SFDP_ERROR_DRIVER; + goto error; + } + + /* Compute the Address */ + if (JEDEC_SCCR_Map.Param_DWORD.D9.LocalAddress == 1u) + { + /* Local Address is found in Byte 1 of 32-bit address */ + Address = JEDEC_SCCR_Map.Param_DWORD.D9.AddressRegisterOrModesSupported << 8; + } + else + { + /* Specific case of GigaDevice GD25LX512ME where register address is wrongly coded in SFDP table */ + if (Object->sfdp_private.ManuID == 0xC8) + { + /* Address value in datasheet : 1, address value coded in SFDP table 200 */ + Address = 1U; + } + else + { + /* Local address for Variable Dummy Cycle Settings bits is found in last byte of the address */ + Address = JEDEC_SCCR_Map.Param_DWORD.D9.AddressRegisterOrModesSupported; + } + } + + /* Read the configuration */ + if (HAL_OK != SAL_XSPI_CommandSendReadAddress(&Object->sfdp_private.SALObject, + (uint8_t)JEDEC_SCCR_Map.Param_DWORD.D9.CommandReadAccess, + Address, + (uint8_t *)localValue, + 2u, + Object->sfdp_private.ManuID)) + { + retr = EXTMEM_SFDP_ERROR_DRIVER; + goto error; + } + + /* send command to write enable */ + if (HAL_OK != SAL_XSPI_CommandSendData(&Object->sfdp_private.SALObject, + Object->sfdp_private.DriverInfo.WriteWELCommand, NULL, 0u)) + { + retr = EXTMEM_SFDP_ERROR_DRIVER; + goto error; + } + + /* control the write enable */ + if (HAL_OK != SAL_XSPI_CheckStatusRegister(&Object->sfdp_private.SALObject, + Object->sfdp_private.DriverInfo.ReadWELCommand, + Object->sfdp_private.DriverInfo.WELAddress, + ((Object->sfdp_private.DriverInfo.WELBusyPolarity == 0u) ? 1u: 0u) << Object->sfdp_private.DriverInfo.WELPosition, + 1u << Object->sfdp_private.DriverInfo.WELPosition, + Object->sfdp_private.ManuID, 1000)) + { + retr = EXTMEM_SFDP_ERROR_DRIVER; + goto error; + } + + /* clear the value */ + localValue[0] = localValue[0] & ~(MaskWaitStateValue[JEDEC_SCCR_Map.Param_DWORD.D9.NumberBitsUsedToSetWaitStates] << JEDEC_SCCR_Map.Param_DWORD.D9.BitLocationLSBPhysicalBitsRegister); + + /* Apply the value with the mask */ + localValue[0] = localValue[0] | (uint8_t)(DummyValue << JEDEC_SCCR_Map.Param_DWORD.D9.BitLocationLSBPhysicalBitsRegister); + localValue[1] = localValue[0]; + + /* Write de configuration */ + if (HAL_OK != SAL_XSPI_Write(&Object->sfdp_private.SALObject, (uint8_t)JEDEC_SCCR_Map.Param_DWORD.D9.CommandWriteAccess, Address, (uint8_t *)localValue, 2u)) + { + retr = EXTMEM_SFDP_ERROR_DRIVER; + goto error; + } + + /* wait for busy flag clear */ + if (EXTMEM_DRIVER_NOR_SFDP_OK != driver_check_FlagBUSY(Object, 100u)) + { + retr = EXTMEM_SFDP_ERROR_DRIVER; + goto error; + } + + /* Read the configuration, line can be removed it is only used for debug purpose */ + if (HAL_OK != SAL_XSPI_Read(&Object->sfdp_private.SALObject, (uint8_t)JEDEC_SCCR_Map.Param_DWORD.D9.CommandReadAccess, + Address, (uint8_t *)localValue, 2u)) + { + retr = EXTMEM_SFDP_ERROR_DRIVER; + goto error; + } + +error : + return retr; +} + +/** + * @brief This function is in charge to manages the action corresponding to + JEDEC_Basic.Params.Param_DWORD.D15.QuadEnableRequirement parameter + * @param Object memory Object + * @return @ref SFDP_StatusTypeDef + */ +SFDP_StatusTypeDef JEDEC_Basic_ManageQuadEnableRequirement(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *Object) +{ + SFDP_StatusTypeDef retr = EXTMEM_SFDP_ERROR_NOTYETHANDLED; + uint8_t localValue[2]; + + /* switch the mode in QSPI if available */ + switch (JEDEC_Basic.Params.Param_DWORD.D15.QuadEnableRequirement & 0x7u) + { + case 0x0u: /* 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4 reads based on instruction. IO3/HOLD# functions as hold during instruction phase.*/ + break; + case 0x1u: /* 001b: QE is bit 1 of status register 2. It is set via Write Status with two data bytes where bit 1 of the second byte is one. + It is cleared via Write Status with two data bytes where bit 1 of the second byte is zero. Writing only one byte to the status register has the side-effect of clearing status register 2, + including the QE bit. The 100b code is used if writing one byte to the status register does not modify status register 2. + */ + break; + case 0x2u: {/* 010b: QE is bit 6 of status register 1. It is set via Write Status with one data byte where bit 6 is one. + It is cleared via Write Status with one data byte where bit 6 is zero. */ + /* 1 - set the write enable */ + if (HAL_OK != SAL_XSPI_SendReadCommand(&Object->sfdp_private.SALObject, + Object->sfdp_private.DriverInfo.WriteWELCommand, NULL, 0u)) + { + retr = EXTMEM_SFDP_ERROR_DRIVER; + goto error; + } + + /* 2 - read the status register */ + if (HAL_OK != SAL_XSPI_SendReadCommand(&Object->sfdp_private.SALObject, SFDP_DRIVER_READ_STATUS_REGISTER_COMMAND, + (uint8_t *)&localValue[0], 1u)) + { + retr = EXTMEM_SFDP_ERROR_DRIVER; + goto error; + } + + /* 3 - update the status register to enable QPI mode*/ + localValue[0] = localValue[0] | 0x40u; + + /* 4 - write the status register with QPI mode to 1 */ + if (HAL_OK != SAL_XSPI_CommandSendData(&Object->sfdp_private.SALObject, 0x1u, (uint8_t *)&localValue[0], 1u)) + { + retr = EXTMEM_SFDP_ERROR_DRIVER; + goto error; + } + + /* wait busy flag */ + if (EXTMEM_DRIVER_NOR_SFDP_OK != driver_check_FlagBUSY(Object, 100)) + { + retr = EXTMEM_SFDP_ERROR_DRIVER; + goto error; + } + + retr = EXTMEM_SFDP_OK; + break; + } + case 0x3u: /* 011b: QE is bit 7 of status register 2. It is set via Write status register 2 instruction 3Eh with one data byte where bit 7 is one. It is cleared via Write status register 2 instruction 3Eh with one data byte where bit 7 is zero. The status register 2 is read using instruction 3Fh.*/ + break; + case 0x4u:{ /* 100b: QE is bit 1 of status register 2. It is set via Write Status with two data bytes where bit 1 of the second byte is one. + It is cleared via Write Status with two data bytes where bit 1 of the second byte is zero. + In contrast to the 001b code, writing one byte to the status register does not modify status register 2.*/ + + /* read the status register */ + if (HAL_OK != SAL_XSPI_SendReadCommand(&Object->sfdp_private.SALObject, 0x5, (uint8_t *)&localValue[0], 2u)) + { + retr = EXTMEM_SFDP_ERROR_DRIVER; + goto error; + } + + /* update the status register */ + localValue[1] |= 2u; + + /* WEL */ + if (HAL_OK != SAL_XSPI_SendReadCommand(&Object->sfdp_private.SALObject, Object->sfdp_private.DriverInfo.WriteWELCommand, NULL, 0u)) + { + retr = EXTMEM_SFDP_ERROR_DRIVER; + goto error; + } + + /* write the status register */ + if (HAL_OK != SAL_XSPI_CommandSendData(&Object->sfdp_private.SALObject, 0x1u, (uint8_t *)&localValue[0], 2u)) + { + retr = EXTMEM_SFDP_ERROR_DRIVER; + goto error; + } + + /* wait busy flag */ + if (EXTMEM_DRIVER_NOR_SFDP_OK != driver_check_FlagBUSY(Object, 100)) + { + retr = EXTMEM_SFDP_ERROR_DRIVER; + goto error; + } + + /* Optional : only for control read the status register and check write operation is OK */ + localValue[1] = 0xFF; + if (HAL_OK != SAL_XSPI_SendReadCommand(&Object->sfdp_private.SALObject, 0x5, (uint8_t *)&localValue[0], 2u)) + { + retr = EXTMEM_SFDP_ERROR_DRIVER; + goto error; + } + + retr = EXTMEM_SFDP_OK; + break; + } + case 0x5u: /* 101b: QE is bit 1 of the status register 2. Status register 1 is read using Read Status instruction 05h. Status register 2 is read using instruction 35h. QE is set via Write Status instruction 01h with two data bytes where bit 1 of the second byte is one. It is cleared via Write Status with two data bytes where bit 1 of the second byte is zero.*/ + break; + case 0x6u: /* 110b: QE is bit 1 of the status register 2. Status register 1 is read using Read Status instruction 05h. Status register 2 is read using instruction 35h, and status register 3 is read using instruction 15h. QE is set via Write Status Register instruction 31h with one data byte where bit 1 is one. It is cleared via Write Status Register instruction 31h with one data byte where bit 1 is zero.*/ + break; + case 0x7u: /*111b: Reserved */ + break; + default :/* Added for Misra */ + break; + } +error : + return retr; +} + +/** + * @brief This function is in charge to manages the action corresponding to + JEDEC_Basic.Params.Param_DWORD.D15._4S4S4S_EnableSequence parameter + * @param Object memory Object + * @return @ref SFDP_StatusTypeDef + */ +SFDP_StatusTypeDef JEDEC_Basic_Manage4S4S4SEnableSequence(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *Object) +{ + SFDP_StatusTypeDef retr = EXTMEM_SFDP_ERROR_NOTYETHANDLED; + uint8_t instruction = 0x00u; + + /* 4-4-4 mode enable sequences; This field describes the supported methods to enter 4-4-4 mode from 1-1-1 mode */ + /* x_xxx1b: set QE per QER description above, then issue instruction 38h */ + if ((JEDEC_Basic.Params.Param_DWORD.D15._4S4S4S_EnableSequence & 0x1u) == 0x1u) + { + retr = JEDEC_Basic_ManageQuadEnableRequirement(Object); + instruction = 0x38u; + } + /* x_x1xxb: issue instruction 35h */ + else if ((JEDEC_Basic.Params.Param_DWORD.D15._4S4S4S_EnableSequence & 0x4u) == 0x4u) + { + /* If QE bit exists, Quad Enable Requirement describes method to enable Quad operations */ + retr = JEDEC_Basic_ManageQuadEnableRequirement(Object); + instruction = 0x35u; + } + else + { + /* nothing to do managed as EXTMEM_SFDP_ERROR_NOTYETHANDLED */ + } + + /* + x_1xxxb: device uses a read-modify-write sequence of operations: read configuration using instruction 65h followed by address 800003h, + set bit 6, write configuration using instruction 71h followed by address 800003h. This configuration is volatile. + 1_xxxxb: + 4-4-4 mode enable sequences + Device uses a read-modify-write sequence of operations: + Read Volatile Enhanced Configuration Register using instruction 65h, no address is required, reset bit 7 to 0. + Write Volatile Enhanced Configuration Register using instruction 61h, no address is required. This configuration is volatile. + 4-4-4 mode disable sequences + Device uses a read-modify-write sequence of operations: + Read Volatile Enhanced Configuration Register using instruction 65h, no address is required, set bit 7 to 1. + Write Volatile Enhanced Configuration Register using instruction 61h, no address is required. This configuration is volatile. + NOTE If device is in 0-4-4 mode, then this mode must be exited before the 4-4-4 enable sequence is issued. + */ + if ((retr == EXTMEM_SFDP_OK) && (instruction != 0u)) + { + (void)SAL_XSPI_SendReadCommand(&Object->sfdp_private.SALObject, instruction, NULL, 0u); + /* @note on memory W25Q64JV the command 38h does not exist so the control on command execution has been removed */ + retr = EXTMEM_SFDP_OK; + } + + return retr; +} + +/** + * @brief This function check the validity of the memory type + * @param Object memory Object + * @param Signature value of the SFDP signature + * @return @ref SFDP_StatusTypeDef + */ +SFDP_StatusTypeDef CheckSFDP_Signature(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *Object, uint32_t Signature ) +{ + SFDP_StatusTypeDef retr = EXTMEM_SFDP_ERROR_SIGNATURE; + + /* check the magic number */ + switch(Signature) + { + case SFDP_SIGNATURE : + SFDP_DEBUG_STR("signature of the header: OK"); + retr = EXTMEM_SFDP_OK; + break; + case SFDP_SIGNATURE_INVERTED : + SFDP_DEBUG_STR("signature of the header: KO inverted data order"); + /* Change the memory type settings */ + if (HAL_OK == SAL_XSPI_UpdateMemoryType(&Object->sfdp_private.SALObject, SAL_XSPI_ORDERINVERTED)) + { + retr = EXTMEM_SFDP_ERROR_SIGNATUREMTYPE; + } + break; + default : + SFDP_DEBUG_STR("signature of the header: KO"); + break; + } + return retr; +} +/** + * @} + */ + + #endif /* EXTMEM_DRIVER_NOR_SFDP == 1 */ + diff --git a/Middlewares/ST/STM32_ExtMem_Manager/nor_sfdp/stm32_sfdp_data.h b/Middlewares/ST/STM32_ExtMem_Manager/nor_sfdp/stm32_sfdp_data.h new file mode 100644 index 0000000..1a3c7f6 --- /dev/null +++ b/Middlewares/ST/STM32_ExtMem_Manager/nor_sfdp/stm32_sfdp_data.h @@ -0,0 +1,185 @@ +/** + ****************************************************************************** + * @file stm32_sfdp_data.h + * @author MCD Application Team + * @brief This file contains the sfdp functions prototypes. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_SFDP_DATA_H +#define __STM32_SFDP_DATA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#if EXTMEM_SAL_XSPI == 1 +#include "../sal/stm32_sal_xspi_api.h" +#else +#error "the driver SFDP requires the enable of EXTMEM_SAL_XSPI" +#endif /* EXTMEM_SAL_XSPI_ENABLED */ + +/** + * @addtogroup NOR_SFDP_DATA + * @ingroup NOR_SFDP + * @{ + */ + +/* Exported constants --------------------------------------------------------*/ + +/** + * @brief Maximum number of SFDP parameter in SFDP table + */ +#define SFDP_MAX_NB_OF_PARAM 10U + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup NOR_SFDP_DATA_Exported_Types Exported Types + * @ingroup NOR_SFDP_DATA + * @{ + */ + +/** + * @brief SFDP parameter table ID + */ +typedef enum +{ + SFDP_PARAMID_UNKNOWN = 0x00000u, + SFDP_PARAMID_VENDOR = 0x00001u, + SFDP_PARAMID_FUNCTION_VENDOR = 0x00002u, + SFDP_PARAMID_FUNCTION_JEDEC = 0x00004u, + SFDP_PARAMID_BASIC_SPIPROTOCOL = 0x00008u, + SFDP_PARAMID_SECTORMAP = 0x00010u, + SFDP_PARAMID_RPMC = 0x00020u, + SFDP_PARAMID_4BYTE_ADDRESS_INSTRUCTION = 0x00040u, + SFDP_PARAMID_XSPI_V1_0 = 0x00080u, + SFDP_PARAMID_XSPI_V2_0 = 0x00100u, + SFDP_PARAMID_STATUS_CONTROL_CONFIG_REGISTER_MAP = 0x00200u, + SFDP_PARAMID_STATUS_CONTROL_CONFIG_REGISTER_MAP_MULTICHIP= 0x00400u, + SFDP_PARAMID_STATUS_CONTROL_CONFIG_XSPI_V2_0 = 0x00800u, + SFDP_PARAMID_OCTAL_DDR = 0x01000u, + SFDP_PARAMID_MSPT = 0x02000u, + SFDP_PARAMID_X4QUAD_DS = 0x04000u, + SFDP_PARAMID_QUAD_DDR = 0x08000u, + SFDP_PARAMID_SECURE_PACKET_READ_WRITE = 0x10000u, + SFDP_PARAMID_RESERVED = 0x20000u +} SFDP_ParamID_TypeDef; + +/** + * @brief SFDP status typedef + */ +typedef enum +{ + EXTMEM_SFDP_OK, /*!< status OK */ + EXTMEM_SFDP_ERROR_PARAM, + EXTMEM_SFDP_ERROR_NOREADFUNCTION, + EXTMEM_SFDP_ERROR_SFDPREAD, + EXTMEM_SFDP_ERROR_SIGNATURE, /*!< the signature is invalid */ + EXTMEM_SFDP_ERROR_SIGNATUREMTYPE, /*!< the signature is invalid due to wrong memory type */ + EXTMEM_SFDP_ERROR_PARAMTABLE_NOTFOUND, + EXTMEM_SFDP_ERROR_NO_PARAMTABLE_BASIC, + EXTMEM_SFDP_ERROR_NO_32BITADDRESSING, + EXTMEM_SFDP_ERROR_JEDECBASIC_D14, + EXTMEM_SFDP_ERROR_JEDECBASIC_D16, + EXTMEM_SFDP_ERROR_OCTALMODE, + EXTMEM_SFDP_ERROR_DRIVER, + EXTMEM_SFDP_ERROR_SETCLOCK, + EXTMEM_SFDP_ERROR_CONFIGDUMMY, + EXTMEM_SFDP_ERROR_NOTYETHANDLED +} SFDP_StatusTypeDef; + +/** + * @brief SFDP header + */ +typedef struct +{ + uint32_t Signature; /*!< signature value */ + uint8_t Minor_revision; /*!< minor revision */ + uint8_t Major_revision; /*!< major revision */ + uint8_t param_number; /*!< number of param */ + uint8_t AccessProtocol; /*!< access protocol */ +} SFDP_HeaderTypeDef; + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup NOR_SFDP_Data_Exported_Functions Exported Functions + * @{ + */ + + /** + * @brief This function gets the SFDP header + * @param Object memory instance object descriptor + * @return @ref SFDP_StatusTypeDef + **/ +SFDP_StatusTypeDef SFDP_GetHeader(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *Object, + SFDP_HeaderTypeDef *sfdp_header); + + /** + * @brief This function reads the SFDP header for current configuration + and adjusts the memory type if required + * @param Object memory instance object descriptor + * @return @ref SFDP_StatusTypeDef + **/ +SFDP_StatusTypeDef SFDP_ReadHeader(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *Object, + SFDP_HeaderTypeDef *sfdp_header); + +/** + * @brief This function collects all the SFDP information + * @param Object memory instance object descriptor + * @return @ref SFDP_StatusTypeDef + */ +SFDP_StatusTypeDef SFDP_CollectData(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *Object); + +/** + * @brief This function resets the memory + * @param Object memory instance object descriptor + * @return @ref SFDP_StatusTypeDef + */ +SFDP_StatusTypeDef SFDP_MemoryReset(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *Object); + +/** + * @brief This function builds the driver info + * @param Object memory instance object descriptor + * @param FreqUpdated set to 1 if the freqence is updated + * @return @ref SFDP_StatusTypeDef + */ +SFDP_StatusTypeDef SFDP_BuildGenericDriver(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *Object, uint8_t *FreqUpdated); + +/** + * @brief This function checks the busy flag + * + * @param SFDPObject memory Object + * @param timeout timeout value + * @return @ref EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef + **/ +EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef driver_check_FlagBUSY(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *SFDPObject, uint32_t Timeout); + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32_SFDP_DATA_H */ diff --git a/Middlewares/ST/STM32_ExtMem_Manager/nor_sfdp/stm32_sfdp_driver.c b/Middlewares/ST/STM32_ExtMem_Manager/nor_sfdp/stm32_sfdp_driver.c new file mode 100644 index 0000000..5cdf40a --- /dev/null +++ b/Middlewares/ST/STM32_ExtMem_Manager/nor_sfdp/stm32_sfdp_driver.c @@ -0,0 +1,684 @@ +/** + ****************************************************************************** + * @file stm32_sfdp_driver.c + * @author MCD Application Team + * @brief This file includes a driver for SFDP support + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_extmem_conf.h" + +#if EXTMEM_DRIVER_NOR_SFDP == 1 +#include "stm32_sfdp_driver_type.h" +#include "stm32_sfdp_driver_api.h" +#include "stm32_sfdp_data.h" +#if EXTMEM_DRIVER_NOR_SFDP_DEBUG_LEVEL != 0 && defined(EXTMEM_MACRO_DEBUG) +#include +#endif /* EXTMEM_DRIVER_NOR_SFDP_DEBUG_LEVEL != 0 && defined(EXTMEM_MACRO_DEBUG) */ +#include + +/** @defgroup NOR_SFDP NOR SFDP driver + * @ingroup EXTMEM_DRIVER + * @{ + */ + + + +/* Private Macros ------------------------------------------------------------*/ +/** @defgroup NOR_SFDP_Private_Macro DRIVER NOR SFDP Private Macro + * @{ + */ +/** + * @brief MIN macro + */ +#define MIN(_A_,_B_) ((_A_) > (_B_))?(_B_):(_A_); + +/** + * @brief default timeout + */ +#define DRIVER_DEFAULT_TIMEOUT 300 + +/** + * @brief default clock value to read SFDP data + */ +#define DRIVER_SFDP_DEFAULT_CLOCK 50000000u + +/** + * @brief DEBUG macro + */ +#if EXTMEM_DRIVER_NOR_SFDP_DEBUG_LEVEL > 1 && defined(EXTMEM_MACRO_DEBUG) +/** + * @brief debug macro for a string + * @param _STR_ string + */ +#define SFDP_DEBUG_STR(_STR_) { \ + EXTMEM_MACRO_DEBUG("\tSFDP::"); \ + EXTMEM_MACRO_DEBUG(_STR_); \ + EXTMEM_MACRO_DEBUG("\n\r"); \ + } + +/** + * @brief debug macro for low level + */ +#if EXTMEM_DRIVER_NOR_SFDP_DEBUG_LEVEL > 2 +#define DEBUG_DRIVER(_STR_) { \ + EXTMEM_MACRO_DEBUG("\tSFDP::DRIVER::"); \ + EXTMEM_MACRO_DEBUG(_STR_); \ + EXTMEM_MACRO_DEBUG("\n"); \ + } +#else +#define DEBUG_DRIVER(_STR_) +#endif /* EXTMEM_DRIVER_NOR_SFDP_DEBUG_LEVEL > 2 */ + +/** + * @brief debug macro for an integer + */ +#define DEBUG_ID(_ID_) { \ + char StrID[40]; \ + EXTMEM_MACRO_DEBUG("\tSFDP:: Flash ID("); \ + (void)sprintf(StrID, "0x%x:0x%x:0x%x:0x%x", \ + _ID_[0],_ID_[1],_ID_[2],_ID_[3]); \ + EXTMEM_MACRO_DEBUG(StrID); \ + EXTMEM_MACRO_DEBUG(")\n"); \ + } + + +/** + * @brief debug macro for error + */ +#define DEBUG_DRIVER_ERROR(_STR_) SFDP_DEBUG_STR(_STR_) +#else +#define DEBUG_ID(_ID_) +#define SFDP_DEBUG_STR(_STR_) +#define DEBUG_DRIVER(_STR_) +#define DEBUG_DRIVER_ERROR(_STR_) +#endif /* EXTMEM_DRIVER_NOR_SFDP_DEBUG_LEVEL > 1 && defined(EXTMEM_MACRO_DEBUG) */ + +/** + * @} + */ + +/* Private typedefs ---------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup DRIVER_SFDP_Private_Functions DRIVER SFDP Private Functions + * @{ + */ +static EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef driver_set_FlagWEL(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *SFDPObject, uint32_t Timeout); +__weak void EXTMEM_MemCopy( uint32_t* destination_Address, const uint8_t* ptrData, uint32_t DataSize); + +/** + * @} + */ + +/** @defgroup DRIVER_SFDP_Exported_Functions DRIVER SFDP Exported Functions + * @{ + */ + +EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef EXTMEM_DRIVER_NOR_SFDP_Init(void *Peripheral, EXTMEM_LinkConfig_TypeDef Config, uint32_t ClockInput, EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *SFDPObject) +{ + EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef retr = EXTMEM_DRIVER_NOR_SFDP_OK; + SFDP_HeaderTypeDef JEDEC_SFDP_Header; + uint8_t FreqUpdate = 0u; + uint8_t DataID[6]; + uint32_t ClockOut; + + /* reset data of SFDPObject to zero */ + SFDP_DEBUG_STR("1 - reset data SFDPObject to zero") + (void)memset((void *)&SFDPObject->sfdp_private, 0x0, sizeof(SFDPObject->sfdp_private)); + + /* initialize the SFDPObject */ + SFDP_DEBUG_STR("2 - initialize the SFDPObject") + SFDPObject->sfdp_private.Config = Config; + SFDPObject->sfdp_private.DriverInfo.SpiPhyLink = PHY_LINK_1S1S1S; + SFDPObject->sfdp_private.DriverInfo.ClockIn = ClockInput; + SAL_XSPI_SET_SFDPDUMMYCYLE(SFDPObject->sfdp_private.SALObject, EXTMEM_READ_SFDP_NB_DUMMY_CYCLES_DEFAULT); + + /* set memory speed to 50Mhz maximum */ + SFDP_DEBUG_STR("3 - set memory link and speed to 50Mhz maximum") + (void)SAL_XSPI_Init(&SFDPObject->sfdp_private.SALObject, Peripheral); + (void)SAL_XSPI_SetClock(&SFDPObject->sfdp_private.SALObject, ClockInput, DRIVER_SFDP_DEFAULT_CLOCK, &ClockOut); + + /* Abort any ongoing XSPI action */ + (void)SAL_XSPI_DisableMapMode(&SFDPObject->sfdp_private.SALObject); + + /* analyze the SFDP structure to get driver information */ + SFDP_DEBUG_STR("4 - analyze the SFDP structure to get driver information") + if(EXTMEM_SFDP_OK != SFDP_GetHeader(SFDPObject, &JEDEC_SFDP_Header)) + { + /* + * for the future, we can try to get SFDP by using different mode + * the SFDP read is only performed in 1S1S1S mode + */ + SFDP_DEBUG_STR("ERROR::EXTMEM_DRIVER_NOR_SFDP_ERROR_SFDP") + retr = EXTMEM_DRIVER_NOR_SFDP_ERROR_SFDP; + goto error; + } + + /* Reset the memory */ + SFDP_DEBUG_STR("5 - reset the memory") + if(EXTMEM_SFDP_OK != SFDP_MemoryReset(SFDPObject)) + { + /* + * for the future, we can try to get SFDP by using different mode + * the SFDP read is only performed in 1S1S1S mode + */ + SFDP_DEBUG_STR("ERROR::on the call of SFDP_MemoryReset but no error returned") + } + + /* wait few ms after the reset operation, this is done to avoid issue on SFDP read */ + HAL_Delay(10); + + /* analyze the SFDP structure to get driver information after the reset */ + SFDP_DEBUG_STR("6 - analyze the SFDP structure to get driver information") + if(EXTMEM_SFDP_OK != SFDP_GetHeader(SFDPObject, &JEDEC_SFDP_Header)) + { + /* + * for the future, we can try to get SFDP by using different mode + * the SFDP read is only perform in 1S1S1S mode + */ + SFDP_DEBUG_STR("ERROR::EXTMEM_DRIVER_NOR_SFDP_ERROR_SFDP") + retr = EXTMEM_DRIVER_NOR_SFDP_ERROR_SFDP; + goto error; + } + + /* Save information from the SFDP table + Nb of parameters starts at 0 (0 means 1 parameter) */ + if (JEDEC_SFDP_Header.param_number >= SFDP_MAX_NB_OF_PARAM) + { + SFDPObject->sfdp_private.Sfdp_param_number = SFDP_MAX_NB_OF_PARAM - 1; + } + else + { + SFDPObject->sfdp_private.Sfdp_param_number = JEDEC_SFDP_Header.param_number; + } + SFDPObject->sfdp_private.Sfdp_AccessProtocol = JEDEC_SFDP_Header.AccessProtocol; + + /* read the flash ID */ + SFDP_DEBUG_STR("7 - read the flash ID") + (void)SAL_XSPI_GetId(&SFDPObject->sfdp_private.SALObject, DataID, EXTMEM_READ_JEDEC_ID_SIZE); + DEBUG_ID(DataID); + + /* Keep manufacturer information, it could be used to help in + building of consistent driver */ + SFDPObject->sfdp_private.ManuID = DataID[0]; + + /* get the SFDP data */ + SFDP_DEBUG_STR("8 - collect the SFDP data") + if(EXTMEM_SFDP_OK != SFDP_CollectData(SFDPObject)) + { + SFDP_DEBUG_STR("ERROR::EXTMEM_DRIVER_NOR_SFDP_ERROR_SFDP") + retr = EXTMEM_DRIVER_NOR_SFDP_ERROR_SFDP; + goto error; + } + + /* setup the generic driver information and prepare the physical layer */ + SFDP_DEBUG_STR("9 - build the generic driver information and prepare the physical layer") + if(EXTMEM_SFDP_OK != SFDP_BuildGenericDriver(SFDPObject, &FreqUpdate)) + { + SFDP_DEBUG_STR("ERROR::EXTMEM_DRIVER_NOR_SFDP_ERROR_BUILD") + retr = EXTMEM_DRIVER_NOR_SFDP_ERROR_BUILD; + goto error; + } + + SFDP_DEBUG_STR("10 - adjust the frequency if required") + if ((FreqUpdate == 0u) && (SFDPObject->sfdp_public.MaxFreq != 0u)) + { + (void)SAL_XSPI_SetClock(&SFDPObject->sfdp_private.SALObject, ClockInput, SFDPObject->sfdp_public.MaxFreq, &ClockOut); + SFDP_DEBUG_STR("--> new freq configured"); + } + + SFDP_DEBUG_STR("11 - read again the SFDP header to adjust memory type if necessary") + if(EXTMEM_SFDP_OK != SFDP_ReadHeader(SFDPObject, &JEDEC_SFDP_Header)) + { + SFDP_DEBUG_STR("ERROR::EXTMEM_DRIVER_NOR_SFDP_MEMTYPE_CHECK") + retr = EXTMEM_DRIVER_NOR_SFDP_ERROR_MEMTYPE_CHECK; + goto error; + } + + (void)SAL_XSPI_GetId(&SFDPObject->sfdp_private.SALObject, DataID, EXTMEM_READ_JEDEC_ID_SIZE); + DEBUG_ID(DataID); + +error: + return retr; +} + +EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef EXTMEM_DRIVER_NOR_SFDP_DeInit(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *SFDPObject) +{ + SFDPObject->sfdp_private.FlashSize = 0; + return EXTMEM_DRIVER_NOR_SFDP_OK; +} + +void EXTMEM_DRIVER_NOR_SFDP_GetFlashInfo(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *SFDPObject, EXTMEM_NOR_SFDP_FlashInfoTypeDef *FlashInfo) +{ + DEBUG_DRIVER((uint8_t *)__func__) + /* Format the info */ + FlashInfo->FlashSize = SFDPObject->sfdp_private.FlashSize; + FlashInfo->PageSize = SFDPObject->sfdp_private.PageSize; + FlashInfo->EraseType1Size = (SFDPObject->sfdp_private.DriverInfo.EraseType1Size == 0u) ? 0u: + ((uint32_t)1u << SFDPObject->sfdp_private.DriverInfo.EraseType1Size); + FlashInfo->EraseType2Size = (SFDPObject->sfdp_private.DriverInfo.EraseType2Size == 0u) ? 0u: + ((uint32_t)1u << SFDPObject->sfdp_private.DriverInfo.EraseType2Size); + FlashInfo->EraseType3Size = (SFDPObject->sfdp_private.DriverInfo.EraseType3Size == 0u) ? 0u: + ((uint32_t)1u << SFDPObject->sfdp_private.DriverInfo.EraseType3Size); + FlashInfo->EraseType4Size = (SFDPObject->sfdp_private.DriverInfo.EraseType4Size == 0u) ? 0u: + ((uint32_t)1u << SFDPObject->sfdp_private.DriverInfo.EraseType4Size); +} + +EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef EXTMEM_DRIVER_NOR_SFDP_Write(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *SFDPObject, uint32_t Address, const uint8_t* Data, uint32_t Size) +{ + EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef retr; + uint32_t size_write; + uint32_t local_size = Size; + uint32_t local_Address = Address; + uint32_t local_Data = (uint32_t)Data; + uint32_t misalignment = 0u; + + if (0u != (local_Address % SFDPObject->sfdp_private.PageSize)) + { + misalignment = 1u; + } + + DEBUG_DRIVER((uint8_t *)__func__) + while(local_size != 0u) + { + if (misalignment == 1u) + { + size_write = SFDPObject->sfdp_private.PageSize - (local_Address % SFDPObject->sfdp_private.PageSize); + size_write = MIN(local_size, size_write); + misalignment = 0u; + } + else + { + size_write = MIN(local_size, SFDPObject->sfdp_private.PageSize); + } + + /* check WIP flag */ + retr = driver_check_FlagBUSY(SFDPObject, 5000u); + if ( EXTMEM_DRIVER_NOR_SFDP_OK != retr) + { + DEBUG_DRIVER_ERROR("EXTMEM_DRIVER_NOR_SFDP_Write::ERROR_CHECK_BUSY") + goto error; + } + + /* wait for WEL flag */ + retr = driver_set_FlagWEL(SFDPObject, DRIVER_DEFAULT_TIMEOUT); + if ( EXTMEM_DRIVER_NOR_SFDP_OK != retr) + { + DEBUG_DRIVER_ERROR("EXTMEM_DRIVER_NOR_SFDP_Write::ERROR_CHECK_WEL") + goto error; + } + + /* Write the data */ + if (HAL_OK != SAL_XSPI_Write(&SFDPObject->sfdp_private.SALObject, SFDPObject->sfdp_private.DriverInfo.PageProgramInstruction, local_Address, (uint8_t *)local_Data, size_write)) + { + DEBUG_DRIVER_ERROR("EXTMEM_DRIVER_NOR_SFDP_Write::ERROR_WRITE") + retr = EXTMEM_DRIVER_NOR_SFDP_ERROR_WRITE; + goto error; + } + + local_size = local_size - size_write; + local_Address = local_Address + size_write; + local_Data = local_Data + size_write; + } + + /* check busy flag */ + retr = driver_check_FlagBUSY(SFDPObject, 5000); +#if EXTMEM_MACRO_DEBUG + if ( EXTMEM_DRIVER_NOR_SFDP_OK != retr) + { + DEBUG_DRIVER_ERROR("EXTMEM_DRIVER_NOR_SFDP_Write::ERROR_CHECK_BUSY_ON_EXIT") + } +#endif /* EXTMEM_MACRO_DEBUG */ + +error: + return retr; +} + +EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef EXTMEM_DRIVER_NOR_SFDP_WriteInMappedMode(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *SFDPObject, uint32_t Address, const uint8_t* Data, uint32_t Size) +{ + EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef retr = EXTMEM_DRIVER_NOR_SFDP_OK; + uint32_t size_write; + uint32_t local_size = Size; + uint32_t local_Address = Address; + const uint8_t *local_Data = Data; + uint32_t size; + uint32_t misalignment = 0u; + + DEBUG_DRIVER((uint8_t *)__func__) + + /* check if the input address is 32bit aligned */ + if (0u != (local_Address % 4u)) + { + retr = EXTMEM_DRIVER_NOR_SFDP_ERROR_ADDRESS_ALIGNMENT; + goto error; + } + + if (0u != (local_Address % SFDPObject->sfdp_private.PageSize)) + { + misalignment = 1u; + } + + while(local_size != 0u) { + + if (misalignment == 1u) + { + size_write = SFDPObject->sfdp_private.PageSize - (local_Address % SFDPObject->sfdp_private.PageSize); + size_write = MIN(local_size, size_write); + misalignment = 0u; + } + else + { + if (local_size > SFDPObject->sfdp_private.PageSize) + { + size_write = SFDPObject->sfdp_private.PageSize; + } + else + { + size_write = local_size; + if (0u != (local_size % sizeof(uint32_t))) + { + size_write = size_write + sizeof(uint32_t) - (local_size % sizeof(uint32_t)); + } + } + } + + /* wait for Write enable flag */ + retr = driver_set_FlagWEL(SFDPObject, DRIVER_DEFAULT_TIMEOUT); + if ( EXTMEM_DRIVER_NOR_SFDP_OK != retr) + { + DEBUG_DRIVER_ERROR("EXTMEM_DRIVER_NOR_SFDP_write::ERROR_CHECK_WEL") + goto error; + } + + /* enter the mapped mode */ + retr = EXTMEM_DRIVER_NOR_SFDP_Enable_MemoryMappedMode(SFDPObject); + if ( EXTMEM_DRIVER_NOR_SFDP_OK != retr) + { + goto error; + } + + size = size_write; + /* Execute the copy */ + EXTMEM_MemCopy((uint32_t *)local_Address, local_Data, size_write); + + /* enter the mapped mode */ + retr = EXTMEM_DRIVER_NOR_SFDP_Disable_MemoryMappedMode(SFDPObject); + if ( EXTMEM_DRIVER_NOR_SFDP_OK != retr) + { + goto error; + } + + /* check busy flag */ + retr = driver_check_FlagBUSY(SFDPObject, 5000); + if ( EXTMEM_DRIVER_NOR_SFDP_OK != retr) + { + DEBUG_DRIVER_ERROR("EXTMEM_DRIVER_NOR_SFDP_write::ERROR_CHECK_BUSY_ON_EXIT") + goto error; + } + + /* decrement the transfer size */ + if (local_size > size ) + { + local_size = local_size - size; + local_Data = &local_Data[size]; + local_Address = local_Address + size; + } + else + { + local_size = 0; + } + } + +error: + return retr; +} + +EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef EXTMEM_DRIVER_NOR_SFDP_Read(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *SFDPObject, uint32_t Address, uint8_t* Data, uint32_t Size) +{ + EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef retr; + DEBUG_DRIVER((uint8_t *)__func__) + /* check busy flag */ + retr = driver_check_FlagBUSY(SFDPObject, 5000); + if ( EXTMEM_DRIVER_NOR_SFDP_OK != retr) + { + DEBUG_DRIVER_ERROR("EXTMEM_DRIVER_NOR_SFDP_Read::ERROR_CHECK_BUSY") + goto error; + } + + if (HAL_OK != SAL_XSPI_Read(&SFDPObject->sfdp_private.SALObject, SFDPObject->sfdp_private.DriverInfo.ReadInstruction, Address, Data, Size)) + { + DEBUG_DRIVER_ERROR("EXTMEM_DRIVER_NOR_SFDP_Read::ERROR_READ") + retr = EXTMEM_DRIVER_NOR_SFDP_ERROR_READ; + } +error : + return retr; +} + +EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef EXTMEM_DRIVER_NOR_SFDP_SectorErase(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *SFDPObject, uint32_t Address, EXTMEM_DRIVER_NOR_SFDP_SectorTypeTypeDef SectorType) +{ + EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef retr; + uint8_t command, size; + uint32_t timeout; + DEBUG_DRIVER((uint8_t *)__func__) + + /* check if the selected sector type is available */ + switch(SectorType) + { + case EXTMEM_DRIVER_NOR_SFDP_SECTOR_TYPE1: + command = SFDPObject->sfdp_private.DriverInfo.EraseType1Command; + size = SFDPObject->sfdp_private.DriverInfo.EraseType1Size; + timeout = SFDPObject->sfdp_private.DriverInfo.EraseType1Timing; + break; + case EXTMEM_DRIVER_NOR_SFDP_SECTOR_TYPE2: + command = SFDPObject->sfdp_private.DriverInfo.EraseType2Command; + size = SFDPObject->sfdp_private.DriverInfo.EraseType2Size; + timeout = SFDPObject->sfdp_private.DriverInfo.EraseType2Timing; + break; + case EXTMEM_DRIVER_NOR_SFDP_SECTOR_TYPE3: + command = SFDPObject->sfdp_private.DriverInfo.EraseType3Command; + size = SFDPObject->sfdp_private.DriverInfo.EraseType3Size; + timeout = SFDPObject->sfdp_private.DriverInfo.EraseType3Timing; + break; + case EXTMEM_DRIVER_NOR_SFDP_SECTOR_TYPE4: + command = SFDPObject->sfdp_private.DriverInfo.EraseType4Command; + size = SFDPObject->sfdp_private.DriverInfo.EraseType4Size; + timeout = SFDPObject->sfdp_private.DriverInfo.EraseType4Timing; + break; + default : + retr = EXTMEM_DRIVER_NOR_SFDP_ERROR_SECTORTYPE; + goto error; + break; + } + + /* check if the command for this sector size is available */ + if (0x0u == command) + { + retr = EXTMEM_DRIVER_NOR_SFDP_ERROR_SECTORTYPE_UNAVAILABLE; + goto error; + } + + /* check @ alignment */ + if (0x0u != (Address % ((uint32_t)1u << size))) + { + retr = EXTMEM_DRIVER_NOR_SFDP_ERROR_ADDRESS_ALIGNMENT; + goto error; + } + + /* check busy flag */ + retr = driver_check_FlagBUSY(SFDPObject, 5000u); + if ( EXTMEM_DRIVER_NOR_SFDP_OK != retr) + { + goto error; + } + + /* wait for write enable flag */ + retr = driver_set_FlagWEL(SFDPObject, DRIVER_DEFAULT_TIMEOUT); + if (EXTMEM_DRIVER_NOR_SFDP_OK != retr ) + { + goto error; + } + + /* launch erase command */ + (void)SAL_XSPI_CommandSendAddress(&SFDPObject->sfdp_private.SALObject, command, Address); + + /* check busy flag */ + retr = driver_check_FlagBUSY(SFDPObject, timeout); /* the timeout is set according the memory characteristic */ + if (EXTMEM_DRIVER_NOR_SFDP_OK != retr) + { + goto error; + } + + +error: + return retr; +} + +EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef EXTMEM_DRIVER_NOR_SFDP_MassErase(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *SFDPObject) +{ + EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef retr; + DEBUG_DRIVER((uint8_t *)__func__) + + /* check busy flag */ + retr = driver_check_FlagBUSY(SFDPObject, 1000); + if ( EXTMEM_DRIVER_NOR_SFDP_OK != retr) + { + DEBUG_DRIVER_ERROR("EXTMEM_DRIVER_NOR_SFDP_read::ERROR_CHECK_BUSY") + retr = EXTMEM_DRIVER_NOR_SFDP_ERROR_FLASHBUSY; + goto error; + } + + /* wait for write enable flag */ + retr = driver_set_FlagWEL(SFDPObject, DRIVER_DEFAULT_TIMEOUT); + if (EXTMEM_DRIVER_NOR_SFDP_OK != retr) + { + DEBUG_DRIVER_ERROR("EXTMEM_DRIVER_NOR_SFDP_read::ERROR_CHECK_WEL") + goto error; + } + + /* launch mass erase command */ + (void)SAL_XSPI_CommandSendData(&SFDPObject->sfdp_private.SALObject, SFDP_DRIVER_ERASE_CHIP_COMMAND, NULL, 0); + + + /* check busy flag */ + retr = driver_check_FlagBUSY(SFDPObject, SFDPObject->sfdp_private.DriverInfo.EraseChipTiming); /* time to used should be set according the memory characteristic */ + if ( EXTMEM_DRIVER_NOR_SFDP_OK != retr) + { + DEBUG_DRIVER_ERROR("EXTMEM_DRIVER_NOR_SFDP_MassErase::ERROR_CHECK_BUSY_ON_EXIT") + retr = EXTMEM_DRIVER_NOR_SFDP_ERROR_ERASE_TIMEOUT; + goto error; + } + +error: + return retr; +} + +EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef EXTMEM_DRIVER_NOR_SFDP_Enable_MemoryMappedMode(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *SFDPObject) +{ + EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef retr = EXTMEM_DRIVER_NOR_SFDP_OK; + + /* enter the mapped mode */ + if (HAL_OK != SAL_XSPI_EnableMapMode(&SFDPObject->sfdp_private.SALObject, SFDPObject->sfdp_private.DriverInfo.ReadInstruction, + (uint8_t)SFDPObject->sfdp_private.SALObject.Commandbase.DummyCycles, + SFDPObject->sfdp_private.DriverInfo.PageProgramInstruction, 0)) + { + retr = EXTMEM_DRIVER_NOR_SFDP_ERROR_MAP_ENABLE; + } + + return retr; +} + +EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef EXTMEM_DRIVER_NOR_SFDP_Disable_MemoryMappedMode(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *SFDPObject) +{ + EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef retr = EXTMEM_DRIVER_NOR_SFDP_OK; + + /* exit the mapped mode */ + if (HAL_OK != SAL_XSPI_DisableMapMode(&SFDPObject->sfdp_private.SALObject)) + { + retr = EXTMEM_DRIVER_NOR_SFDP_ERROR_MAP_ENABLE; + } + + return retr; +} + + +/** + * @} + */ + +/** @addtogroup DRIVER_SFDP_Internal_Functions DRIVER SFDP Internal Functions + * @{ + */ + + + +/** + * @} + */ + +/** @addtogroup DRIVER_SFDP_Private_Functions DRIVER SFDP Private Functions + * @{ + */ + +/** + * @brief This function enables the WEL Flag and checks its activation + * + * @param SFDPObject memory object + * @param timeout timeout value + * @return @ref EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef + **/ +EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef driver_set_FlagWEL(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *SFDPObject, uint32_t Timeout) +{ + EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef retr = EXTMEM_DRIVER_NOR_SFDP_ERROR_WRITEENABLE; + DEBUG_DRIVER((uint8_t *)__func__) + /* send the command write enable */ + (void)SAL_XSPI_CommandSendData(&SFDPObject->sfdp_private.SALObject, SFDPObject->sfdp_private.DriverInfo.WriteWELCommand, NULL, 0); + + /* wait for write enable status */ + if (0u != SFDPObject->sfdp_private.DriverInfo.ReadWELCommand) + { + /* check if flag write enable is enabled */ + if (HAL_OK == SAL_XSPI_CheckStatusRegister(&SFDPObject->sfdp_private.SALObject, + SFDPObject->sfdp_private.DriverInfo.ReadWELCommand, + SFDPObject->sfdp_private.DriverInfo.WELAddress, + ((SFDPObject->sfdp_private.DriverInfo.WELBusyPolarity == 0u) ? 1u: 0u) << SFDPObject->sfdp_private.DriverInfo.WELPosition, + 1u << SFDPObject->sfdp_private.DriverInfo.WELPosition, + SFDPObject->sfdp_private.ManuID, Timeout)) + { + retr = EXTMEM_DRIVER_NOR_SFDP_OK; + } + } + return retr; +} + +__weak void EXTMEM_MemCopy(uint32_t* destination_Address, const uint8_t* ptrData, uint32_t DataSize) +{ + uint32_t *ptrDest = destination_Address; + /* Write the data */ + for (uint32_t index = 0u; index < DataSize; index = index + 4u){ + *ptrDest = ((uint32_t)ptrData[index] | ((uint32_t)ptrData[index+1u] << 8u) | + ( (uint32_t)ptrData[index+2u] << 16u) | ((uint32_t)ptrData[index+3u] << 24u)); + ptrDest++; + } +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* EXTMEM_DRIVER_NOR_SFDP == 1 */ diff --git a/Middlewares/ST/STM32_ExtMem_Manager/nor_sfdp/stm32_sfdp_driver_api.h b/Middlewares/ST/STM32_ExtMem_Manager/nor_sfdp/stm32_sfdp_driver_api.h new file mode 100644 index 0000000..82c13ab --- /dev/null +++ b/Middlewares/ST/STM32_ExtMem_Manager/nor_sfdp/stm32_sfdp_driver_api.h @@ -0,0 +1,190 @@ +/** + ****************************************************************************** + * @file stm32_sfdp_driver_api.h + * @author MCD Application Team + * @brief This file contains the sfdp driver definition. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_NOR_SFDP_DRIVER_API_H +#define __STM32_NOR_SFDP_DRIVER_API_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ + +/** @addtogroup NOR_SFDP + * @ingroup EXTMEM_DRIVER + * @{ + */ + +/* Exported constants --------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup DRIVER_SFDP_Exported_Types DRIVER SFDP Memory Exported Types + * @{ + */ + + +/** + * @brief List of error codes for the SFDP driver + */ +typedef enum { + EXTMEM_DRIVER_NOR_SFDP_OK = 0, + EXTMEM_DRIVER_NOR_SFDP_ERROR_SFDP = -1, + EXTMEM_DRIVER_NOR_SFDP_ERROR_READ = -2, + EXTMEM_DRIVER_NOR_SFDP_ERROR_BUILD = -3, + EXTMEM_DRIVER_NOR_SFDP_ERROR_UNKNOWN_COMMAND = -4, + EXTMEM_DRIVER_NOR_SFDP_ERROR_BUSY = -5, + EXTMEM_DRIVER_NOR_SFDP_ERROR_WRITEENABLE = -6, + EXTMEM_DRIVER_NOR_SFDP_ERROR_WRITE = -7, + EXTMEM_DRIVER_NOR_SFDP_ERROR_SECTORTYPE = -8, + EXTMEM_DRIVER_NOR_SFDP_ERROR_SECTORTYPE_UNAVAILABLE = -9, + EXTMEM_DRIVER_NOR_SFDP_ERROR_ADDRESS_ALIGNMENT = -10, + EXTMEM_DRIVER_NOR_SFDP_ERROR_ERASE_TIMEOUT = -11, + EXTMEM_DRIVER_NOR_SFDP_ERROR_FLASHBUSY = -12, + EXTMEM_DRIVER_NOR_SFDP_ERROR_MAP_ENABLE = -13, + EXTMEM_DRIVER_NOR_SFDP_ERROR_MEMTYPE_CHECK = -14, + EXTMEM_DRIVER_NOR_SFDP_ERROR = -128, +} EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef; + +/** + * @brief List of sector types for the SFDP driver + */ +typedef enum { + EXTMEM_DRIVER_NOR_SFDP_SECTOR_TYPE1, + EXTMEM_DRIVER_NOR_SFDP_SECTOR_TYPE2, + EXTMEM_DRIVER_NOR_SFDP_SECTOR_TYPE3, + EXTMEM_DRIVER_NOR_SFDP_SECTOR_TYPE4 +}EXTMEM_DRIVER_NOR_SFDP_SectorTypeTypeDef; + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** + * @addtogroup DRIVER_SFDP_Exported_Functions DRIVER SFDP exported functions + * @{ + */ +/** + * @brief This function initializes the driver SFDP + * + * @param Peripheral Peripheral pointer + * @param Config config type + * @param ClockInput timeout value + * @param SFDPObject memory object + * @return @ref EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef + **/ +EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef EXTMEM_DRIVER_NOR_SFDP_Init(void *Peripheral, EXTMEM_LinkConfig_TypeDef Config, uint32_t ClockInput, EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *SFDPObject); + +/** + * @brief This function un-initializes the driver SFDP + * + * @param SFDPObject IP object + * @return @ref EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef + **/ +EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef EXTMEM_DRIVER_NOR_SFDP_DeInit(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *SFDPObject); + +/** + * @brief This function returns the flash information + * + * @param SFDPObject memory objecte + * @param FlashInfo pointer on flash info structure + **/ +void EXTMEM_DRIVER_NOR_SFDP_GetFlashInfo(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *SFDPObject, EXTMEM_NOR_SFDP_FlashInfoTypeDef *FlashInfo); + +/** + * @brief This function reads the memory + * + * @param SFDPObject memory object + * @param Address memory address + * @param Data pointer on the data + * @param Size data size to read + * @return @ref EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef + **/ +EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef EXTMEM_DRIVER_NOR_SFDP_Read(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *SFDPObject, uint32_t Address, uint8_t* Data, uint32_t Size); + +/** + * @brief This function writes data in the memory + * + * @param SFDPObject memory object + * @param Address memory address + * @param Data pointer on the data + * @param Size data size to write + * @return @ref EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef + **/ +EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef EXTMEM_DRIVER_NOR_SFDP_Write(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *SFDPObject, uint32_t Address, const uint8_t* Data, uint32_t Size); + +/** + * @brief This function writes data in the memory in mapped mode + * + * @param SFDPObject memory object + * @param Address memory address in mapped mode + * @param Data pointer on the data + * @param Size data size to write + * @return @ref EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef + **/ +EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef EXTMEM_DRIVER_NOR_SFDP_WriteInMappedMode(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *SFDPObject, uint32_t Address, const uint8_t* Data, uint32_t Size); + +/** + * @brief This function erases all the memory + * + * @param SFDPObject memory object + * @return @ref EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef + **/ +EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef EXTMEM_DRIVER_NOR_SFDP_MassErase(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *SFDPObject); + +/** + * @brief This function erases memory sector + * + * @param SFDPObject memory object + * @param Address memory address + * @param SectorType type of sector + * @return @ref EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef + **/ +EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef EXTMEM_DRIVER_NOR_SFDP_SectorErase(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *SFDPObject, uint32_t Address, EXTMEM_DRIVER_NOR_SFDP_SectorTypeTypeDef SectorType); + +/** + * @brief This function enables the memory mapped mode + * + * @param SFDPObject memory object + * @return @ref EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef + **/ +EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef EXTMEM_DRIVER_NOR_SFDP_Enable_MemoryMappedMode(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *SFDPObject); + +/** + * @brief This function disables the memory mapped mode + * + * @param SFDPObject memory object + * @return @ref EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef + **/ +EXTMEM_DRIVER_NOR_SFDP_StatusTypeDef EXTMEM_DRIVER_NOR_SFDP_Disable_MemoryMappedMode(EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef *SFDPObject); + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32_NOR_SFDP_DRIVER_API_H */ diff --git a/Middlewares/ST/STM32_ExtMem_Manager/nor_sfdp/stm32_sfdp_driver_type.h b/Middlewares/ST/STM32_ExtMem_Manager/nor_sfdp/stm32_sfdp_driver_type.h new file mode 100644 index 0000000..6625ace --- /dev/null +++ b/Middlewares/ST/STM32_ExtMem_Manager/nor_sfdp/stm32_sfdp_driver_type.h @@ -0,0 +1,152 @@ +/** + ****************************************************************************** + * @file stm32_sfdp_driver_type.h + * @author MCD Application Team + * @brief This file contains the sfdp driver definition. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_SFDP_DRIVER_TYPE_H +#define __STM32_SFDP_DRIVER_TYPE_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/* Includes ------------------------------------------------------------------*/ +/** @addtogroup NOR_SFDP + * @ingroup EXTMEM_DRIVER + * @{ + */ + +#include "stm32_extmem.h" + +/* Exported constants --------------------------------------------------------*/ +/** + * @brief Instruction ID for common JEDEC commands + */ +#define SFDP_DRIVER_READ_COMMAND 0x03U + +#define SFDP_DRIVER_PAGE_PROGRAM_COMMAND 0x02U + +#define SFDP_DRIVER_READ_STATUS_REGISTER_COMMAND 0x05U + +#define SFDP_DRIVER_WRITE_ENABLE_50H_COMMAND 0x50U +#define SFDP_DRIVER_WRITE_ENABLE_06H_COMMAND 0x06U + +#define SFDP_DRIVER_ERASE_CHIP_COMMAND 0x60U + + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup DRIVER_SFDP_Exported_Types DRIVER SFDP Memory Exported Types + * @{ + */ + +/** + * @brief driver data used to manage the flash + */ +typedef struct { + + SAL_XSPI_PhysicalLinkTypeDef SpiPhyLink; /*!< physical link information */ + uint32_t ClockIn; /*!< clock d'entree */ + + /* Table of instructions an instruction equal to zero means not supported */ + /* WIP : write in progress */ + uint8_t ReadWIPCommand; /*!< read write in progress command */ + uint8_t WIPPosition; /*!< write in progress byte position */ + uint8_t WIPBusyPolarity; /*!< 0: Positive (WIP=1 means write is in progress) 1: Inverted (WIP=0 means write is in progress) */ + uint8_t WIPAddress; /*!< read write in progress address */ + + /* WEL: write enable */ + uint8_t WriteWELCommand; /*!< write enable command */ + + /* WEL : read write enable */ + uint8_t ReadWELCommand; /*!< read write enable status command */ + uint8_t WELPosition; /*!< write enable position */ + uint8_t WELBusyPolarity; /*!< 0: Positive (WIP=1 means write is in progress) 1: Inverted (WIP=0 means write is in progress) */ + uint8_t WELAddress; /*!< write enable address */ + + /* Page Program */ + uint8_t PageProgramInstruction; /*!< page program command */ + + /* Read management */ + uint8_t ReadInstruction; /*!< read command */ + + /* Erase management */ + uint8_t EraseType1Size; /*!< erase 1 size */ + uint8_t EraseType1Command; /*!< erase 1 command */ + uint8_t EraseType2Size; /*!< erase 2 size */ + uint8_t EraseType2Command; /*!< erase 2 command */ + uint8_t EraseType3Size; /*!< erase 3 size */ + uint8_t EraseType3Command; /*!< erase 3 command */ + uint8_t EraseType4Size; /*!< erase 4 size */ + uint8_t EraseType4Command; /*!< erase 4 command */ + + uint32_t EraseType1Timing; /*!< erase 1 timing */ + uint32_t EraseType2Timing; /*!< erase 2 timing */ + uint32_t EraseType3Timing; /*!< erase 3 timing */ + uint32_t EraseType4Timing; /*!< erase 4 timing */ + uint32_t EraseChipTiming; /*!< erase chip timing */ +} EXTMEM_DRIVER_NOR_SFDP_InfoTypeDef; + + +/** + * @brief driver SFDP Object definition + */ +typedef struct { + struct { + uint32_t MaxFreq; /*!< Maximum frequency supported by the memory + @note if the value is equal to zero, the parameters is ignored */ + uint8_t DtrReadDummyCycle; /*!< Number of dummy cycle for DTR read command + @note used only for JEDEC basic with DTR option */ + } sfdp_public; + struct { + SAL_XSPI_ObjectTypeDef SALObject; /*!< Instance of the memory */ + EXTMEM_LinkConfig_TypeDef Config; /*!< memory configuration */ + uint8_t ManuID; /*!< manufacturer ID */ + uint8_t FlashSize; /*!< Flash size in power of two */ + uint32_t PageSize; /*!< Page size */ + EXTMEM_DRIVER_NOR_SFDP_InfoTypeDef DriverInfo; /*!< driver information */ + uint32_t Sfdp_table_mask; /*!< sfdp table mask */ + uint32_t Reset_info; /*!< this bit is a copy of JEDEC Basic 16 Reset/Rescue info */ + uint8_t Sfdp_param_number; /*!< Number of param from the SFDP header table */ + uint8_t Sfdp_AccessProtocol; /*!< Access protocol from the SFDP header table */ + } sfdp_private; +} EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef; + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** + * @addtogroup DRIVER_SFDP_Exported_Functions DRIVER SFDP exported functions + * @{ + */ +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32_SFDP_DRIVER_TYPE_H */ diff --git a/Middlewares/ST/STM32_ExtMem_Manager/psram/stm32_psram_driver.c b/Middlewares/ST/STM32_ExtMem_Manager/psram/stm32_psram_driver.c new file mode 100644 index 0000000..41e34c8 --- /dev/null +++ b/Middlewares/ST/STM32_ExtMem_Manager/psram/stm32_psram_driver.c @@ -0,0 +1,251 @@ +/** + ****************************************************************************** + * @file stm32_psram_driver.c + * @author MCD Application Team + * @brief This file includes a driver for psram support + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_extmem.h" +#include "stm32_extmem_conf.h" +#if EXTMEM_DRIVER_PSRAM == 1 +#if EXTMEM_SAL_XSPI == 1 +#include "../sal/stm32_sal_xspi_api.h" +#else +#error "the driver PSRAM requires the enable of EXTMEM_SAL_XSPI" +#endif /* EXTMEM_SAL_XSPI */ +#include "stm32_psram_driver_api.h" +#if EXTMEM_DRIVER_PSRAM_DEBUG_LEVEL > 0 && defined(EXTMEM_MACRO_DEBUG) +#include +#endif /* #if EXTMEM_DRIVER_PSRAM_DEBUG_LEVEL > 0 && defined(EXTMEM_MACRO_DEBUG) */ + +/** @defgroup PSRAM PSRAM driver + * @ingroup EXTMEM_DRIVER + * @{ + */ + +/* Private Macro ------------------------------------------------------------*/ +/** @defgroup PSRAM_Private_Macro Private Macro + * @{ + */ + +/** + * @brief default timeout + */ +#define DRIVER_DEFAULT_TIMEOUT 300 + +#if EXTMEM_DRIVER_PSRAM_DEBUG_LEVEL > 0 && defined(EXTMEM_MACRO_DEBUG) +/** + * @brief debug macro for a string + */ +#define DEBUG_STR(_STR_) { \ + EXTMEM_MACRO_DEBUG("\tPSRAM::"); \ + EXTMEM_MACRO_DEBUG(_STR_); \ + EXTMEM_MACRO_DEBUG("\n\r"); \ + } +#else +/** + * @brief debug macro for a string + */ +#define DEBUG_STR(_STR_) +#endif /* EXTMEM_DRIVER_PSRAM_DEBUG_LEVEL > 0 && defined(EXTMEM_MACRO_DEBUG) */ + +/** + * @} + */ + +/* Private typedefs ---------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup PSRAM_Private_Functions Private Functions + * @{ + */ +EXTMEM_DRIVER_PSRAM_StatusTypeDef PSRAM_ExecuteCommand(EXTMEM_DRIVER_PSRAM_ObjectTypeDef *PsramObject, uint8_t Index); +/** + * @} + */ + +/** @defgroup PSRAM_Exported_Functions Exported Functions + * @{ + */ + +EXTMEM_DRIVER_PSRAM_StatusTypeDef EXTMEM_DRIVER_PSRAM_Init(void *Peripheral, EXTMEM_LinkConfig_TypeDef Config, + uint32_t ClockInput, + EXTMEM_DRIVER_PSRAM_ObjectTypeDef *PsramObject) +{ + EXTMEM_DRIVER_PSRAM_StatusTypeDef retr = EXTMEM_DRIVER_PSRAM_OK; + uint32_t ClockOut; + SAL_XSPI_PhysicalLinkTypeDef linkvalue; + + /* initialize the instance */ + DEBUG_STR("initialize the instance") + + /* Initialize XSPI low layer */ + (void)SAL_XSPI_Init(&PsramObject->psram_private.SALObject, Peripheral); + + /* Abort any ongoing XSPI action */ + (void)SAL_XSPI_DisableMapMode(&PsramObject->psram_private.SALObject); + + /* Set the frequency prescaler */ + DEBUG_STR("set memory speed according freqIn and freqMax supported by the memory") + if (HAL_OK != SAL_XSPI_SetClock(&PsramObject->psram_private.SALObject, ClockInput, PsramObject->psram_public.FreqMax, &ClockOut)) + { + retr = EXTMEM_DRIVER_PSRAM_ERROR; + goto error; + } + + /* Set the memory size */ + DEBUG_STR("set memory size according") + (void)SAL_XSPI_MemoryConfig(&PsramObject->psram_private.SALObject, PARAM_FLASHSIZE, &PsramObject->psram_public.MemorySize); + + /* Set the memory size */ + DEBUG_STR("set xspi link config") + linkvalue = PHY_LINK_RAM8; + (void)SAL_XSPI_MemoryConfig(&PsramObject->psram_private.SALObject, PARAM_PHY_LINK, &linkvalue); + + /* Set the configuration to perform register operation */ + (void)SAL_XSPI_MemoryConfig(&PsramObject->psram_private.SALObject, PARAM_DUMMY_CYCLES, &PsramObject->psram_public.REG_DummyCycle); + + /* Execute the command sequence */ + for (uint8_t command_index = 0u; command_index < PsramObject->psram_public.NumberOfConfig; command_index++) + { + retr = PSRAM_ExecuteCommand(PsramObject, command_index); + if (retr != EXTMEM_DRIVER_PSRAM_OK) + { + goto error; + } + } + + switch(Config) + { + case EXTMEM_LINK_CONFIG_16LINES: + linkvalue = PHY_LINK_RAM16; + (void)SAL_XSPI_MemoryConfig(&PsramObject->psram_private.SALObject, PARAM_PHY_LINK, &linkvalue); + break; + + case EXTMEM_LINK_CONFIG_8LINES: + default: + retr = EXTMEM_DRIVER_PSRAM_ERROR; + goto error; + break; + } + +error: + return retr; +} + +EXTMEM_DRIVER_PSRAM_StatusTypeDef EXTMEM_DRIVER_PSRAM_DeInit(EXTMEM_DRIVER_PSRAM_ObjectTypeDef *PsramObject) +{ + /* Abort any ongoing XSPI action */ + (void)SAL_XSPI_DisableMapMode(&PsramObject->psram_private.SALObject); + return EXTMEM_DRIVER_PSRAM_OK; +} + +EXTMEM_DRIVER_PSRAM_StatusTypeDef EXTMEM_DRIVER_PSRAM_Enable_MemoryMappedMode(EXTMEM_DRIVER_PSRAM_ObjectTypeDef *PsramObject) +{ + EXTMEM_DRIVER_PSRAM_StatusTypeDef retr = EXTMEM_DRIVER_PSRAM_OK; + + /* configure the read wrap mode */ + if (HAL_OK != SAL_XSPI_ConfigureWrappMode(&PsramObject->psram_private.SALObject, + PsramObject->psram_public.WrapRead_command, + PsramObject->psram_public.Write_DummyCycle)) + { + retr = EXTMEM_DRIVER_PSRAM_ERROR_MAP_ENABLE; + } + + /* launch the memory mapped mode */ + if (HAL_OK != SAL_XSPI_EnableMapMode(&PsramObject->psram_private.SALObject, + PsramObject->psram_public.Read_command, + PsramObject->psram_public.Read_DummyCycle, + PsramObject->psram_public.Write_command, + PsramObject->psram_public.Write_DummyCycle)) + { + retr = EXTMEM_DRIVER_PSRAM_ERROR_MAP_ENABLE; + } + return retr; +} + +EXTMEM_DRIVER_PSRAM_StatusTypeDef EXTMEM_DRIVER_PSRAM_Disable_MemoryMappedMode(EXTMEM_DRIVER_PSRAM_ObjectTypeDef *PsramObject) +{ + EXTMEM_DRIVER_PSRAM_StatusTypeDef retr = EXTMEM_DRIVER_PSRAM_OK; + + /* launch mass erase command */ + if (HAL_OK != SAL_XSPI_DisableMapMode(&PsramObject->psram_private.SALObject)) + { + retr = EXTMEM_DRIVER_PSRAM_ERROR_MAP_DISABLE; + } + return retr; +} + +/** + * @} + */ + +/** @addtogroup PSRAM_Private_Functions + * @{ + */ + +/** + * @brief This function executes a command + * + * @param PsramObject psram memory object + * @param Index command index + * @return @ref EXTMEM_DRIVER_PSRAM_StatusTypeDef + **/ +EXTMEM_DRIVER_PSRAM_StatusTypeDef PSRAM_ExecuteCommand(EXTMEM_DRIVER_PSRAM_ObjectTypeDef *PsramObject, uint8_t Index) +{ + EXTMEM_DRIVER_PSRAM_StatusTypeDef retr = EXTMEM_DRIVER_PSRAM_OK; + uint8_t regval[2]; + + if (PsramObject->psram_public.ReadREGSize > 2u) + { + retr = EXTMEM_DRIVER_PSRAM_ERROR_REGSIZE; + goto error; + } + + if (HAL_OK != SAL_XSPI_Read(&PsramObject->psram_private.SALObject, + PsramObject->psram_public.ReadREG, + PsramObject->psram_public.config[Index].REGAddress, + regval, PsramObject->psram_public.ReadREGSize)) + { + retr = EXTMEM_DRIVER_PSRAM_ERROR_READREG; + goto error; + } + + MODIFY_REG(regval[0], + PsramObject->psram_public.config[Index].WriteMask, + PsramObject->psram_public.config[Index].WriteValue); + + if (HAL_OK != SAL_XSPI_Write(&PsramObject->psram_private.SALObject, + PsramObject->psram_public.WriteREG, + PsramObject->psram_public.config[Index].REGAddress, + regval, PsramObject->psram_public.ReadREGSize)) + { + retr = EXTMEM_DRIVER_PSRAM_ERROR_WRITEREG; + goto error; + } + +error: + return retr; +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* EXTMEM_DRIVER_PSRAM == 1 */ diff --git a/Middlewares/ST/STM32_ExtMem_Manager/psram/stm32_psram_driver_api.h b/Middlewares/ST/STM32_ExtMem_Manager/psram/stm32_psram_driver_api.h new file mode 100644 index 0000000..ee80c85 --- /dev/null +++ b/Middlewares/ST/STM32_ExtMem_Manager/psram/stm32_psram_driver_api.h @@ -0,0 +1,114 @@ +/** + ****************************************************************************** + * @file stm32_psram_driver.h + * @author MCD Application Team + * @brief This file contains the psram driver definition. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_PSRAM_DRIVER_H +#define __STM32_PSRAM_DRIVER_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#if EXTMEM_DRIVER_PSRAM == 1 + +/** @addtogroup PSRAM + * @ingroup EXTMEM_DRIVER + * @{ + */ +/* Exported constants --------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup PSRAM_Exported_Types Exported Types + * @{ + */ + +/** + * @brief List of error codes of the PSRAM driver + */ +typedef enum { + EXTMEM_DRIVER_PSRAM_OK = 0, + EXTMEM_DRIVER_PSRAM_ERROR_READREG = -1, + EXTMEM_DRIVER_PSRAM_ERROR_WRITEREG = -2, + EXTEM_DRIVER_PSRAM_ERROR_READ = -3, + EXTEM_DRIVER_PSRAM_ERROR_WRITE = -4, + EXTMEM_DRIVER_PSRAM_ERROR_MAP_ENABLE = -5, + EXTMEM_DRIVER_PSRAM_ERROR_MAP_DISABLE = -6, + EXTMEM_DRIVER_PSRAM_ERROR_REGSIZE = -7, + EXTMEM_DRIVER_PSRAM_ERROR = -128, +} EXTMEM_DRIVER_PSRAM_StatusTypeDef; + +/* Exported functions --------------------------------------------------------*/ +/** + * @addtogroup PSRAM_Exported_Functions Exported functions + * @{ + */ +/** + * @brief This function initializes the driver PSRAM + * + * @param Peripheral ptr on the Peripheral handle + * @param Config link configuration + * @param ClockInput timeout value + * @param PsramObject object PSRAM + * @return @ref EXTMEM_DRIVER_PSRAM_StatusTypeDef + **/ +EXTMEM_DRIVER_PSRAM_StatusTypeDef EXTMEM_DRIVER_PSRAM_Init(void *Peripheral, EXTMEM_LinkConfig_TypeDef Config, + uint32_t ClockInput, + EXTMEM_DRIVER_PSRAM_ObjectTypeDef *PsramObject); + +/** + * @brief This function un-initializes the driver PSRAM + * + * @param PsramObject IP instance + * @return @ref EXTMEM_DRIVER_PSRAM_StatusTypeDef + **/ +EXTMEM_DRIVER_PSRAM_StatusTypeDef EXTMEM_DRIVER_PSRAM_DeInit(EXTMEM_DRIVER_PSRAM_ObjectTypeDef *PsramObject); + +/** + * @brief This function enables the memory mapped mode + * + * @param PsramObject memory instance + * @return @ref EXTMEM_DRIVER_PSRAM_StatusTypeDef + **/ +EXTMEM_DRIVER_PSRAM_StatusTypeDef EXTMEM_DRIVER_PSRAM_Enable_MemoryMappedMode(EXTMEM_DRIVER_PSRAM_ObjectTypeDef *PsramObject); + +/** + * @brief This function disables the memory mapped mode + * + * @param PsramObject memory instance + * @return @ref EXTMEM_DRIVER_PSRAM_StatusTypeDef + **/ +EXTMEM_DRIVER_PSRAM_StatusTypeDef EXTMEM_DRIVER_PSRAM_Disable_MemoryMappedMode(EXTMEM_DRIVER_PSRAM_ObjectTypeDef *PsramObject); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* EXTMEM_DRIVER_PSRAM == 1 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32_PSRAM_DRIVER_H */ diff --git a/Middlewares/ST/STM32_ExtMem_Manager/psram/stm32_psram_driver_type.h b/Middlewares/ST/STM32_ExtMem_Manager/psram/stm32_psram_driver_type.h new file mode 100644 index 0000000..cea6859 --- /dev/null +++ b/Middlewares/ST/STM32_ExtMem_Manager/psram/stm32_psram_driver_type.h @@ -0,0 +1,102 @@ +/** + ****************************************************************************** + * @file stm32_psram_type.h + * @author MCD Application Team + * @brief This file contains the psram driver definition. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_PSRAM_TYPE_H +#define __STM32_PSRAM_TYPE_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/** @addtogroup PSRAM + * @ingroup EXTMEM_DRIVER + * @{ + */ + +#if EXTMEM_DRIVER_PSRAM == 1 + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PSRAM_Exported_constants Exported constants + * @{ + */ + +/** + * @brief driver PSRAM maximum number of commands + */ +#define PSRAM_MAX_COMMAND 3u + +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup PSRAM_Exported_Types Exported Types + * @{ + */ + +/** + * @brief driver PSRAM object definition + */ +typedef struct { + struct { + SAL_XSPI_ObjectTypeDef SALObject; /*!< SAL object */ + } psram_private; /*!< private data of the object */ + + struct { + uint32_t MemorySize; /*!< memory size @ref XSPI_MemorySize */ + uint32_t FreqMax; /*!< maximum frequency supported by the memory */ + + /* Configuration */ + uint8_t NumberOfConfig; /*!< Number of config, each config consists to perform read and write operation */ + struct { + uint8_t WriteMask; /*!< write mask */ + uint8_t WriteValue; /*!< write value */ + uint8_t REGAddress; /*!< register address */ + } config[PSRAM_MAX_COMMAND]; + + /* Command REG */ + uint8_t ReadREG; + uint8_t WriteREG; + uint8_t ReadREGSize; + uint8_t REG_DummyCycle; + + /* Command read write */ + uint8_t Write_command; + uint8_t Write_DummyCycle; + uint8_t Read_command; + uint8_t WrapRead_command; + uint8_t Read_DummyCycle; + } psram_public; /*!< public data of the object */ +} EXTMEM_DRIVER_PSRAM_ObjectTypeDef; + +/** + * @} + */ + +/** + * @} + */ +#endif /* EXTMEM_DRIVER_PSRAM == 1 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32_PSRAM_TYPE_H */ diff --git a/Middlewares/ST/STM32_ExtMem_Manager/sal/stm32_sal_sd.c b/Middlewares/ST/STM32_ExtMem_Manager/sal/stm32_sal_sd.c new file mode 100644 index 0000000..6d982d4 --- /dev/null +++ b/Middlewares/ST/STM32_ExtMem_Manager/sal/stm32_sal_sd.c @@ -0,0 +1,201 @@ +/** + ****************************************************************************** + * @file stm32_sal_sd.c + * @author MCD Application Team + * @brief This file is the software adaptation layer for SD + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_extmem.h" +#include "stm32_extmem_conf.h" +#if EXTMEM_SAL_SD_DEBUG_LEVEL != 0 && defined(EXTMEM_MACRO_DEBUG) +#include +#endif /*EXTMEM_SAL_SD_DEBUG_LEVEL != 0 && defined(EXTMEM_MACRO_DEBUG)*/ + +#if EXTMEM_SAL_SD == 1 +#include "stm32_sal_sd_type.h" +#include "stm32_sal_sd_api.h" + +/** @defgroup SAL_SD SAL_SD : Software adaptation layer for the HAL_SD + * @ingroup EXTMEM_SAL + * @{ + */ + +/** + * @brief ready timeout value + */ +#define READY_TIMEOUT 1000u + +/* Private Macros ------------------------------------------------------------*/ + +/** @defgroup SAL_SD_Private_Macros SAL SD Private Macros + * @{ + */ +#if EXTMEM_SAL_SD_DEBUG_LEVEL == 0 || !defined(EXTMEM_MACRO_DEBUG) +#define DEBUG_PARAM_BEGIN() +#define DEBUG_PARAM_DATA(_STR_) +#define DEBUG_PARAM_INT(_INT_ ) +#define DEBUG_PARAM_END() +#else +/** + * @brief trace header macro + */ +#define DEBUG_PARAM_BEGIN() EXTMEM_MACRO_DEBUG("\t\tSALSD::"); + +/** + * @brief trace data string macro + */ +#define DEBUG_PARAM_DATA(_STR_) EXTMEM_MACRO_DEBUG(_STR_); + +/** + * @brief trace data integer macro + */ +#define DEBUG_PARAM_INT(_INT_ ) { \ + char str[10]; \ + (void)snprintf(str, sizeof(str), "0x%x", _INT_);\ + EXTMEM_MACRO_DEBUG(str); \ + } +/** + * @brief trace close macro + */ +#define DEBUG_PARAM_END() EXTMEM_MACRO_DEBUG("\n"); + +#endif /* EXTMEM_SFDP_DEBUG */ + +/** + * @} + */ + +/* Private typedefs ---------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup SAL_SD_Private_Functions SAL XSP Private Functions + * @{ + */ + +/** + * @} + */ + +/* Exported variables ---------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup SAL_SD_Exported_Functions SAL XSP Exported Functions + * @{ + */ + +HAL_StatusTypeDef SAL_SD_Init(SAL_SD_ObjectTypeDef* SalSD, void* HALHandle, EXTMEM_DRIVER_SDCARD_InfoTypeDef* Info) +{ + SalSD->hSD = (SD_HandleTypeDef *)HALHandle; + + Info->BlockNbr = SalSD->hSD->SdCard.BlockNbr; + Info->BlockSize = SalSD->hSD->SdCard.BlockSize; + +#if 0 /* It seems that operation is already in the HAL initialization */ + /* Enable Wide Operation */ + HAL_SD_ConfigWideBusOperation(&hsd_sdmmc[Instance], SDMMC_BUS_WIDE_4B); +#endif + + /* Switch to the highest Speed mode supported by the sd-card */ + return HAL_SD_ConfigSpeedBusOperation(SalSD->hSD, SDMMC_SPEED_MODE_AUTO); +} + +HAL_StatusTypeDef SAL_SD_DeInit(SAL_SD_ObjectTypeDef* SalSD) +{ + SalSD->hSD->SdCard.BlockNbr= 0; + return HAL_OK; +} + +HAL_StatusTypeDef SAL_SD_ReadData(SAL_SD_ObjectTypeDef* SalSD, uint32_t BlockIdx, uint8_t* Data, uint32_t NumberOfBlock) +{ + uint32_t timeout = 100UL * NumberOfBlock; + HAL_StatusTypeDef retr = HAL_SD_ReadBlocks(SalSD->hSD, (uint8_t *)Data, BlockIdx, NumberOfBlock, timeout); + if (HAL_OK == retr) + { + timeout = HAL_GetTick(); + /* check the SD status */ + while(HAL_SD_GetCardState(SalSD->hSD) != HAL_SD_CARD_TRANSFER) + { + if ((HAL_GetTick() - timeout) > READY_TIMEOUT) + { + retr = HAL_TIMEOUT; + break; + } + } + } + return retr; +} + + +HAL_StatusTypeDef SAL_SD_WriteData(SAL_SD_ObjectTypeDef* SalSD, uint32_t BlockIdx, const uint8_t* const Data, uint32_t NumberOfBlock) +{ + uint32_t timeout = 100UL * NumberOfBlock; + HAL_StatusTypeDef retr; + + retr = HAL_SD_WriteBlocks(SalSD->hSD, Data, BlockIdx, NumberOfBlock, timeout); + if (HAL_OK == retr) + { + timeout = HAL_GetTick(); + /* check the SD status */ + while(HAL_SD_GetCardState(SalSD->hSD) != HAL_SD_CARD_TRANSFER) + { + if ((HAL_GetTick() - timeout) > READY_TIMEOUT) + { + retr = HAL_TIMEOUT; + break; + } + } + } + return retr; +} + +HAL_StatusTypeDef SAL_SD_EraseBlock(SAL_SD_ObjectTypeDef* SalSD, uint32_t BlockIdx, uint32_t BlockCount) +{ + uint32_t timeout; + HAL_StatusTypeDef retr; + + retr = HAL_SD_Erase(SalSD->hSD, BlockIdx, BlockIdx + BlockCount); + if (HAL_OK == retr) + { + timeout = HAL_GetTick(); + /* check the SD status */ + while(HAL_SD_GetCardState(SalSD->hSD) != HAL_SD_CARD_TRANSFER) + { + if ((HAL_GetTick() - timeout) > (READY_TIMEOUT * BlockCount)) + { + retr = HAL_TIMEOUT; + break; + } + } + } + return retr; +} + +HAL_StatusTypeDef SAL_SD_MassErase(SAL_SD_ObjectTypeDef* SalSD) +{ + return SAL_SD_EraseBlock(SalSD, 0, SalSD->hSD->SdCard.BlockNbr); +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* EXTMEM_SAL_SD == 1 */ \ No newline at end of file diff --git a/Middlewares/ST/STM32_ExtMem_Manager/sal/stm32_sal_sd_api.h b/Middlewares/ST/STM32_ExtMem_Manager/sal/stm32_sal_sd_api.h new file mode 100644 index 0000000..2ca2c9e --- /dev/null +++ b/Middlewares/ST/STM32_ExtMem_Manager/sal/stm32_sal_sd_api.h @@ -0,0 +1,121 @@ +/** + ****************************************************************************** + * @file stm32_sal_sd_api.h + * @author MCD Application Team + * @brief This file contains the software adaptation layer SD functions + * prototypes. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_SAL_SD_API_H +#define __STM32_SAL_SD_API_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup SAL_SD + * @ingroup EXTMEM_SAL + * @{ + */ + +/** @defgroup SAL_SD + * @{ + */ + +/* Includes ------------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SAL_SD_Exported_types SAL SD exported types + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SAL_SD_Exported_Functions SAL XSP Exported Functions + * @{ + */ + +/** + * @brief This function initializes the SD SAL context + * @param SalSD SAL SD Object + * @param HALHandle HAL handle + * @param Info information on the SD card + * @return @ref HAL_StatusTypeDef + **/ +HAL_StatusTypeDef SAL_SD_Init(SAL_SD_ObjectTypeDef* SalSD, void* HALHandle, EXTMEM_DRIVER_SDCARD_InfoTypeDef* Info); + +/** + * @brief This function un-initializes the SD SAL context + * @param SalSD SAL SD Object + * @return @ref HAL_StatusTypeDef + **/ +HAL_StatusTypeDef SAL_SD_DeInit(SAL_SD_ObjectTypeDef* SalSD); + +/** + * @brief This function reads data from the SD + * @param SalSD SAL SD Object + * @param BlockIdx block index + * @param Data data pointer + * @param NumberOfBlock number of block + * @return @ref HAL_StatusTypeDef + **/ +HAL_StatusTypeDef SAL_SD_ReadData(SAL_SD_ObjectTypeDef* SalSD, uint32_t BlockIdx, uint8_t* Data, uint32_t NumberOfBlock); + +/** + * @brief This function writes data on the SD + * @param SalSD SAL SD Object + * @param BlockIdx block index + * @param Data data pointer + * @param NumberOfBlock number of block + * @return @ref HAL_StatusTypeDef + **/ +HAL_StatusTypeDef SAL_SD_WriteData(SAL_SD_ObjectTypeDef* SalSD, uint32_t BlockIdx, const uint8_t* const Data, uint32_t NumberOfBlock); + +/** + * @brief This function erases an amount of blocks on the SD + * @param SalSD SAL SD Object + * @param BlockIdx block index + * @param BlockCount number of block + * @return @ref HAL_StatusTypeDef + **/ +HAL_StatusTypeDef SAL_SD_EraseBlock(SAL_SD_ObjectTypeDef* SalSD, uint32_t BlockIdx, uint32_t BlockCount); + +/** + * @brief This function erases all the SD + * @param SalSD SAL SD Object + * @return @ref HAL_StatusTypeDef + **/ +HAL_StatusTypeDef SAL_SD_MassErase(SAL_SD_ObjectTypeDef* SalSD); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32_SAL_SD_API_H */ \ No newline at end of file diff --git a/Middlewares/ST/STM32_ExtMem_Manager/sal/stm32_sal_sd_type.h b/Middlewares/ST/STM32_ExtMem_Manager/sal/stm32_sal_sd_type.h new file mode 100644 index 0000000..3e242a4 --- /dev/null +++ b/Middlewares/ST/STM32_ExtMem_Manager/sal/stm32_sal_sd_type.h @@ -0,0 +1,74 @@ +/** + ****************************************************************************** + * @file stm32_sal_sd_type.h + * @author MCD Application Team + * @brief This file contains the software adaptation layer SD functions + * prototypes. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_SAL_SD_TYPE_H +#define __STM32_SAL_SD_TYPE_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup SAL_SD + * @ingroup EXTMEM_SAL + * @{ + */ + +/** @defgroup SAL_SD + * @{ + */ + +/* Includes ------------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SAL_SD_Exported_types SAL SD exported types + * @{ + */ + +typedef struct { + SD_HandleTypeDef *hSD; /*!< handle on the SD instance */ +} SAL_SD_ObjectTypeDef; + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SAL_SD_Exported_Functions SAL XSP Exported Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32_SAL_SD_TYPE_H */ diff --git a/Middlewares/ST/STM32_ExtMem_Manager/sal/stm32_sal_xspi.c b/Middlewares/ST/STM32_ExtMem_Manager/sal/stm32_sal_xspi.c new file mode 100644 index 0000000..0eb1d40 --- /dev/null +++ b/Middlewares/ST/STM32_ExtMem_Manager/sal/stm32_sal_xspi.c @@ -0,0 +1,1074 @@ +/** + ****************************************************************************** + * @file stm32_sal_xspi.c + * @author MCD Application Team + * @brief This file is the software adaptation layer for XSPI + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_extmem.h" +#include "stm32_extmem_conf.h" +#if EXTMEM_SAL_XSPI_DEBUG_LEVEL != 0 && defined(EXTMEM_MACRO_DEBUG) +#include +#endif /*EXTMEM_SAL_XSPI_DEBUG_LEVEL != 0 && defined(EXTMEM_MACRO_DEBUG)*/ + +#if EXTMEM_SAL_XSPI == 1 +#include "stm32_sal_xspi_type.h" +#include "stm32_sal_xspi_api.h" + +/** @defgroup SAL_XSPI SAL_XSPI : Software adaptation layer for XSPI + * @ingroup EXTMEM_SAL + * @{ + */ + +/* Private Macros ------------------------------------------------------------*/ +/** @defgroup SAL_XSPI_Private_Macros SAL XSPI Private Macros + * @{ + */ + +#if EXTMEM_SAL_XSPI_DEBUG_LEVEL == 0 || !defined(EXTMEM_MACRO_DEBUG) +#define DEBUG_PARAM_BEGIN() +#define DEBUG_PARAM_DATA(_STR_) +#define DEBUG_PARAM_INT(_INT_ ) +#define DEBUG_PARAM_INTD(_INT_ ) +#define DEBUG_PARAM_END() +#define DEBUG_AUTOPOLLING(_DR_,_MVAL_,_MMASK_) +#define STR_PHY_LINK(_PHY_) +#else +/** + * @brief trace header macro + */ +#define DEBUG_PARAM_BEGIN() EXTMEM_MACRO_DEBUG("\t\tSALXSPI::"); + +const uint8_t phylink_string[][17] = {"PHY_LINK_1S1S1S", + "PHY_LINK_1S1S2S", + "PHY_LINK_1S2S2S", + "PHY_LINK_1S1D1D", + "PHY_LINK_4S4S4S", + "PHY_LINK_4S4D4D", + "PHY_LINK_4D4D4D", + "PHY_LINK_1S8S8S", + "PHY_LINK_8S8D8D", + "PHY_LINK_8D8D8D", + "PHY_LINK_RAM8" +#if defined(HAL_XSPI_DATA_16_LINES) + ,"PHY_LINK_RAM16" +#endif /* defined(HAL_XSPI_DATA_16_LINES) */ + }; + +#define STR_PHY_LINK(_PHY_) phylink_string[_PHY_] + +/** + * @brief trace data string macro + */ +#define DEBUG_PARAM_DATA(_STR_) EXTMEM_MACRO_DEBUG(_STR_); + +/** + * @brief trace data integer macro + */ +#define DEBUG_PARAM_INT(_INT_) { \ + char str[10]; \ + (void)snprintf(str, sizeof(str), "0x%x", _INT_);\ + EXTMEM_MACRO_DEBUG(str); \ + } +#define DEBUG_PARAM_INTD(_INT_) { \ + char str[15]; \ + (void)snprintf(str, sizeof(str), "%zu", _INT_);\ + EXTMEM_MACRO_DEBUG(str); \ + } +/** + * @brief trace close macro + */ +#define DEBUG_PARAM_END() EXTMEM_MACRO_DEBUG("\n"); + +#if EXTMEM_SAL_XSPI_DEBUG_LEVEL == 2 +#define DEBUG_AUTOPOLLING(_DR_,_MVAL_,_MMASK_) \ + { \ + char str[50]; \ + (void)snprintf(str, sizeof(str),"DR:0x%x::MVal:0x%x::MMask:0x%x\n\r", _DR_, _MVAL_, _MMASK_); \ + DEBUG_PARAM_BEGIN() \ + DEBUG_PARAM_DATA(str) \ + DEBUG_PARAM_END() \ + } +#else +#define DEBUG_AUTOPOLLING(_DR_,_MVAL_,_MMASK_) +#endif /* EXTMEM_SAL_XSPI_DEBUG_LEVEL == 2 */ +#endif /* EXTMEM_SAL_XSPI_DEBUG_LEVEL == 0 || !defined(EXTMEM_MACRO_DEBUG) */ + +/** + * @brief default SAL timeout (100 ms) + */ + +#define SAL_XSPI_TIMEOUT_DEFAULT_VALUE (100U) + +/** + * @} + */ + +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) +/** @defgroup SAL_XSPI_Private_Transfer SAL XSPI Dma transfer management definition + * @{ + */ +/** + * @brief state of the transfer status + */ +typedef enum { + SALXSPI_TRANSFER_NONE, /*!< */ + SALXSPI_TRANSFER_OK, + SALXSPI_TRANSFER_ERROR +}SAL_XSPI_TRANSFER_STATUS; + +/** + * @brief variable of the transfer status + */ +volatile SAL_XSPI_TRANSFER_STATUS salXSPI_status = SALXSPI_TRANSFER_NONE; + +/** + * @} + */ +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + +/* Private typedefs ---------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup SAL_XSPI_Private_Functions SAL XSP Private Functions + * @{ + */ +uint16_t XSPI_FormatCommand(uint8_t CommandExtension, uint32_t InstructionWidth, uint8_t Command); +HAL_StatusTypeDef XSPI_Transmit(SAL_XSPI_ObjectTypeDef *SalXspi, const uint8_t *Data); +HAL_StatusTypeDef XSPI_Receive(SAL_XSPI_ObjectTypeDef *SalXspi, uint8_t *Data); +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) +void SAL_XSPI_ErrorCallback(struct __XSPI_HandleTypeDef *hxspi); +void SAL_XSPI_CompleteCallback(struct __XSPI_HandleTypeDef *hxspi); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + +/** + * @} + */ + +/* Exported variables ---------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup SAL_XSPI_Exported_Functions SAL XSP Exported Functions + * @{ + */ +HAL_StatusTypeDef SAL_XSPI_SetClock(SAL_XSPI_ObjectTypeDef *SalXspi, uint32_t ClockIn, uint32_t ClockRequested, uint32_t *ClockReal) +{ + HAL_StatusTypeDef retr = HAL_OK; + uint32_t divider; + + if (ClockRequested == 0u) + { + retr = HAL_ERROR; + } + else + { + divider = (ClockIn / ClockRequested); + if (divider >= 1u) + { + *ClockReal = ClockIn / divider; + if (*ClockReal <= ClockRequested) + { + divider--; + } + } + + /* real clock calculation */ + *ClockReal = ClockIn / (divider + 1u); + + DEBUG_PARAM_BEGIN(); DEBUG_PARAM_DATA("::CLOCKDIV::"); DEBUG_PARAM_INT(divider+1); DEBUG_PARAM_END(); + DEBUG_PARAM_BEGIN(); DEBUG_PARAM_DATA("::CLKFREQ::"); DEBUG_PARAM_INTD(*ClockReal); DEBUG_PARAM_END(); + MODIFY_REG(SalXspi->hxspi->Instance->DCR2, XSPI_DCR2_PRESCALER, (uint32_t)divider << XSPI_DCR2_PRESCALER_Pos); + } + + return retr; +} + +/* +* This function is used to configure the way to discuss with the memory +* +*/ +HAL_StatusTypeDef SAL_XSPI_Init(SAL_XSPI_ObjectTypeDef *SalXspi, void *HALHandle) +{ + XSPI_RegularCmdTypeDef s_commandbase = { + .OperationType = HAL_XSPI_OPTYPE_COMMON_CFG, + .IOSelect = HAL_XSPI_SELECT_IO_7_0, + .InstructionMode = HAL_XSPI_INSTRUCTION_1_LINE, + .Instruction = EXTMEM_READ_SFDP_COMMAND, + .InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS, + .InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE, + .AlternateBytesMode = HAL_XSPI_ALT_BYTES_NONE, + .AddressMode = HAL_XSPI_ADDRESS_1_LINE, + .AddressWidth = HAL_XSPI_ADDRESS_24_BITS, + .Address = 0x0, + .AddressDTRMode = HAL_XSPI_ADDRESS_DTR_DISABLE, + .DataMode = HAL_XSPI_DATA_1_LINE, + .DataLength = 0x0, + .DataDTRMode = HAL_XSPI_DATA_DTR_DISABLE, + .DummyCycles = EXTMEM_READ_SFDP_NB_DUMMY_CYCLES_DEFAULT, + .DQSMode = HAL_XSPI_DQS_DISABLE, +#if defined(XSPI_CCR_SIOO) + .SIOOMode = HAL_XSPI_SIOO_INST_EVERY_CMD, +#endif /* HAL_XSPI_SIOO_INST_EVERY_CMD */ + }; + + SalXspi->hxspi = (XSPI_HandleTypeDef *)HALHandle; + SalXspi->Commandbase = s_commandbase; + SalXspi->CommandExtension = 0; + SalXspi->PhyLink = PHY_LINK_1S1S1S; + +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + /* set completion call back */ + HAL_XSPI_RegisterCallback(SalXspi->hxspi,HAL_XSPI_RX_CPLT_CB_ID, SAL_XSPI_CompleteCallback); + HAL_XSPI_RegisterCallback(SalXspi->hxspi,HAL_XSPI_TX_CPLT_CB_ID, SAL_XSPI_CompleteCallback); + /* set the error callback */ + HAL_XSPI_RegisterCallback(SalXspi->hxspi,HAL_XSPI_ERROR_CB_ID, SAL_XSPI_ErrorCallback); +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + + return HAL_OK; +} + +HAL_StatusTypeDef SAL_XSPI_MemoryConfig(SAL_XSPI_ObjectTypeDef *SalXspi, SAL_XSPI_MemParamTypeTypeDef ParametersType, void *ParamVal) +{ + HAL_StatusTypeDef retr = HAL_OK; + XSPI_RegularCmdTypeDef s_commandbase = SalXspi->Commandbase; + + switch (ParametersType) { + case PARAM_PHY_LINK:{ + SalXspi->PhyLink = *((SAL_XSPI_PhysicalLinkTypeDef *)ParamVal); + DEBUG_PARAM_BEGIN(); DEBUG_PARAM_DATA("::PARAM_PHY_LINK::");DEBUG_PARAM_DATA(STR_PHY_LINK(SalXspi->PhyLink)); + switch (SalXspi->PhyLink) + { + case PHY_LINK_1S1D1D: + case PHY_LINK_1S2S2S: + case PHY_LINK_1S1S2S: + case PHY_LINK_1S1S1S: { + s_commandbase.InstructionMode = HAL_XSPI_INSTRUCTION_1_LINE; + s_commandbase.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS; + s_commandbase.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE; + s_commandbase.AddressMode = HAL_XSPI_ADDRESS_1_LINE; + s_commandbase.AddressWidth = HAL_XSPI_ADDRESS_24_BITS; + s_commandbase.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_DISABLE; + s_commandbase.DataMode = HAL_XSPI_DATA_1_LINE; + s_commandbase.DataDTRMode = HAL_XSPI_DATA_DTR_DISABLE; + s_commandbase.DummyCycles = 8; + s_commandbase.DQSMode = HAL_XSPI_DQS_DISABLE; + break; + } + + case PHY_LINK_4S4D4D: + case PHY_LINK_4S4S4S: { + s_commandbase.InstructionMode = HAL_XSPI_INSTRUCTION_4_LINES; + s_commandbase.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS; + s_commandbase.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE; + s_commandbase.AddressMode = HAL_XSPI_ADDRESS_4_LINES; + s_commandbase.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_DISABLE; + s_commandbase.AddressWidth = HAL_XSPI_ADDRESS_24_BITS; + s_commandbase.DataMode = HAL_XSPI_DATA_4_LINES; + s_commandbase.DataDTRMode = HAL_XSPI_DATA_DTR_DISABLE; + s_commandbase.DummyCycles = 6; + s_commandbase.DQSMode = HAL_XSPI_DQS_DISABLE; + break; + } + case PHY_LINK_4D4D4D: { + s_commandbase.InstructionMode = HAL_XSPI_INSTRUCTION_4_LINES; + s_commandbase.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS; + s_commandbase.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_ENABLE; + s_commandbase.AddressMode = HAL_XSPI_ADDRESS_4_LINES; + s_commandbase.AddressWidth = HAL_XSPI_ADDRESS_24_BITS; + s_commandbase.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_ENABLE; + s_commandbase.DataMode = HAL_XSPI_DATA_4_LINES; + s_commandbase.DataDTRMode = HAL_XSPI_DATA_DTR_ENABLE; + s_commandbase.DummyCycles = 6; + s_commandbase.DQSMode = HAL_XSPI_DQS_DISABLE; + break; + } + case PHY_LINK_1S8S8S: { + s_commandbase.InstructionMode = HAL_XSPI_INSTRUCTION_1_LINE; + s_commandbase.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS; + s_commandbase.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE; + s_commandbase.AddressMode = HAL_XSPI_ADDRESS_8_LINES; + s_commandbase.AddressWidth = HAL_XSPI_ADDRESS_32_BITS; + s_commandbase.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_DISABLE; + s_commandbase.DataMode = HAL_XSPI_DATA_8_LINES; + s_commandbase.DataDTRMode = HAL_XSPI_DATA_DTR_DISABLE; + s_commandbase.DummyCycles = 8; + s_commandbase.DQSMode = HAL_XSPI_DQS_DISABLE; + break; + } + case PHY_LINK_8S8D8D: { + s_commandbase.InstructionMode = HAL_XSPI_INSTRUCTION_8_LINES; + s_commandbase.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS; + s_commandbase.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE; + s_commandbase.AddressMode = HAL_XSPI_ADDRESS_8_LINES; + s_commandbase.AddressWidth = HAL_XSPI_ADDRESS_32_BITS; + s_commandbase.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_ENABLE; + s_commandbase.DataMode = HAL_XSPI_DATA_8_LINES; + s_commandbase.DataDTRMode = HAL_XSPI_DATA_DTR_ENABLE; + s_commandbase.DummyCycles = 8; + s_commandbase.DQSMode = HAL_XSPI_DQS_ENABLE; + break; + } + + case PHY_LINK_8D8D8D: { + s_commandbase.InstructionMode = HAL_XSPI_INSTRUCTION_8_LINES; + s_commandbase.InstructionWidth = HAL_XSPI_INSTRUCTION_16_BITS; + s_commandbase.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_ENABLE; + s_commandbase.AddressMode = HAL_XSPI_ADDRESS_8_LINES; + s_commandbase.AddressWidth = HAL_XSPI_ADDRESS_32_BITS; + s_commandbase.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_ENABLE; + s_commandbase.DataMode = HAL_XSPI_DATA_8_LINES; + s_commandbase.DataDTRMode = HAL_XSPI_DATA_DTR_ENABLE; + s_commandbase.DummyCycles = 20; + s_commandbase.DQSMode = HAL_XSPI_DQS_ENABLE; + break; + } + case PHY_LINK_RAM8:{ + s_commandbase.InstructionMode = HAL_XSPI_INSTRUCTION_8_LINES; + s_commandbase.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS; + s_commandbase.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE; + s_commandbase.AddressMode = HAL_XSPI_ADDRESS_8_LINES; + s_commandbase.AddressWidth = HAL_XSPI_ADDRESS_32_BITS; + s_commandbase.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_ENABLE; + s_commandbase.AlternateBytesMode = HAL_XSPI_ALT_BYTES_NONE; + s_commandbase.DataMode = HAL_XSPI_DATA_8_LINES; + s_commandbase.DataDTRMode = HAL_XSPI_DATA_DTR_ENABLE; + s_commandbase.DummyCycles = 10; + s_commandbase.DQSMode = HAL_XSPI_DQS_ENABLE; + break; + } +#if defined(HAL_XSPI_DATA_16_LINES) + case PHY_LINK_RAM16 :{ + s_commandbase.InstructionMode = HAL_XSPI_INSTRUCTION_8_LINES; + s_commandbase.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS; + s_commandbase.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE; + s_commandbase.AddressMode = HAL_XSPI_ADDRESS_8_LINES; + s_commandbase.AddressWidth = HAL_XSPI_ADDRESS_32_BITS; + s_commandbase.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_ENABLE; + s_commandbase.AlternateBytesMode = HAL_XSPI_ALT_BYTES_NONE; + s_commandbase.DataMode = HAL_XSPI_DATA_16_LINES; + s_commandbase.DataDTRMode = HAL_XSPI_DATA_DTR_ENABLE; + s_commandbase.DummyCycles = 10; + s_commandbase.DQSMode = HAL_XSPI_DQS_ENABLE; + break; + } +#endif /* defined(HAL_XSPI_DATA_16_LINES) */ + default: + retr = HAL_ERROR; + break; + } + DEBUG_PARAM_END(); + break; + } + case PARAM_ADDRESS_4BYTES: { + DEBUG_PARAM_BEGIN(); DEBUG_PARAM_DATA("::PARAM_ADDRESS_4BYTES"); DEBUG_PARAM_END(); + s_commandbase.AddressWidth = HAL_XSPI_ADDRESS_32_BITS; + break; + } + case PARAM_FLASHSIZE:{ + uint8_t valParam = *((uint8_t *)ParamVal); + DEBUG_PARAM_BEGIN(); DEBUG_PARAM_DATA("::PARAM_FLASHSIZE::"); DEBUG_PARAM_INT(valParam); DEBUG_PARAM_END(); + MODIFY_REG(SalXspi->hxspi->Instance->DCR1, XSPI_DCR1_DEVSIZE, ((uint32_t)valParam) << XSPI_DCR1_DEVSIZE_Pos); + break; + } + case PARAM_DUMMY_CYCLES:{ + uint8_t valParam = *((uint8_t *)ParamVal); + DEBUG_PARAM_BEGIN(); DEBUG_PARAM_DATA("::PARAM_DUMMY_CYCLES::"); DEBUG_PARAM_INT(valParam); DEBUG_PARAM_END(); + s_commandbase.DummyCycles = valParam; + break; + } + default: + DEBUG_PARAM_BEGIN(); DEBUG_PARAM_DATA("::SAL_XSPI_MemoryConfig::ERROR"); DEBUG_PARAM_END(); + retr = HAL_ERROR; + break; + } + SalXspi->Commandbase = s_commandbase; + return retr; +} + +HAL_StatusTypeDef SAL_XSPI_GetSFDP(SAL_XSPI_ObjectTypeDef *SalXspi, uint32_t Address, uint8_t *Data, uint32_t DataSize) +{ + HAL_StatusTypeDef retr; + XSPI_RegularCmdTypeDef s_command = SalXspi->Commandbase; + + /* Initialize the read ID command */ + s_command.Instruction = XSPI_FormatCommand(SalXspi->CommandExtension, s_command.InstructionWidth, + EXTMEM_READ_SFDP_COMMAND); + + s_command.Address = Address; + s_command.DataLength = DataSize; + /* Nb of Dummy cycles for READ SFDP command does not correspond to SFDPDummyCycle field of SAL structure, + as initialised after SFDP Header analysis */ + s_command.DummyCycles = EXTMEM_READ_SFDP_NB_DUMMY_CYCLES_DEFAULT; + + if (s_command.AddressMode == HAL_XSPI_ADDRESS_1_LINE) + { + s_command.AddressWidth = HAL_XSPI_ADDRESS_24_BITS; + } + + if (s_command.DataDTRMode == HAL_XSPI_DATA_DTR_ENABLE) + { + s_command.DQSMode = HAL_XSPI_DQS_ENABLE; + } + else + { + s_command.DQSMode = HAL_XSPI_DQS_DISABLE; + } + + /* Configure the command */ + retr = HAL_XSPI_Command(SalXspi->hxspi, &s_command, SAL_XSPI_TIMEOUT_DEFAULT_VALUE); + if ( retr != HAL_OK) + { + goto error; + } + + /* Reception of the data */ + retr = HAL_XSPI_Receive(SalXspi->hxspi, Data, SAL_XSPI_TIMEOUT_DEFAULT_VALUE); + +error: + if (retr != HAL_OK ) + { + /* abort any ongoing transaction for the next action */ + (void)HAL_XSPI_Abort(SalXspi->hxspi); + } + return retr; +} + +HAL_StatusTypeDef SAL_XSPI_GetId(SAL_XSPI_ObjectTypeDef *SalXspi, uint8_t *Data, uint32_t DataSize) +{ + HAL_StatusTypeDef retr; + XSPI_RegularCmdTypeDef s_command = SalXspi->Commandbase; + + /* Initialize the Read ID command */ + s_command.Instruction = XSPI_FormatCommand(SalXspi->CommandExtension, s_command.InstructionWidth, + EXTMEM_READ_JEDEC_ID_SPI_COMMAND); + + s_command.DataLength = DataSize; + + if (s_command.InstructionMode == HAL_XSPI_INSTRUCTION_1_LINE) + { + s_command.AddressMode = HAL_XSPI_ADDRESS_NONE; + s_command.DummyCycles = 0; + /* this behavior is linked with micron memory to read ID in 1S8S8S */ + s_command.DataMode = HAL_XSPI_DATA_1_LINE; + } + else if (s_command.InstructionMode == HAL_XSPI_INSTRUCTION_4_LINES) + { + s_command.AddressMode = HAL_XSPI_ADDRESS_NONE; + s_command.DummyCycles = 0; + /* this behavior is linked with ISSI memory to read ID in 4S4S4S */ + s_command.DataMode = HAL_XSPI_DATA_4_LINES; + } + else if (s_command.InstructionMode == HAL_XSPI_INSTRUCTION_8_LINES) + { + s_command.Address = 0; + + /* Specific case for Macronix memories : RDID is not Data DTR */ + if ((Data[0] == 0xC2) && (s_command.DataDTRMode == HAL_XSPI_DATA_DTR_ENABLE)) + { + s_command.DummyCycles = 4; + s_command.DataDTRMode = HAL_XSPI_DATA_DTR_DISABLE; + } + /* Specific case for GigaDevice memories : RDID has no address even in Octal mode */ + else if ((Data[0] == 0xC8) && (s_command.DataDTRMode == HAL_XSPI_DATA_DTR_ENABLE)) + { + s_command.DummyCycles = 8; + s_command.AddressMode = HAL_XSPI_ADDRESS_NONE; + } + else + { + s_command.DummyCycles = 8; + } + /* Required behavior to be confirmed on the other memories */ + } + else + { + s_command.Address = 0; + s_command.DummyCycles = 8; + } + + /* Configure the command */ + retr = HAL_XSPI_Command(SalXspi->hxspi, &s_command, SAL_XSPI_TIMEOUT_DEFAULT_VALUE); + if ( retr != HAL_OK) + { + goto error; + } + + /* Reception of the data */ + retr = HAL_XSPI_Receive(SalXspi->hxspi, Data, SAL_XSPI_TIMEOUT_DEFAULT_VALUE); + +error: + if (retr != HAL_OK ) + { + /* abort any ongoing transaction for the next action */ + (void)HAL_XSPI_Abort(SalXspi->hxspi); + } + return retr; +} + +HAL_StatusTypeDef SAL_XSPI_Read(SAL_XSPI_ObjectTypeDef *SalXspi, uint8_t Command, uint32_t Address, uint8_t *Data, uint32_t DataSize) +{ + HAL_StatusTypeDef retr; + XSPI_RegularCmdTypeDef s_command = SalXspi->Commandbase; + + /* Initialize the read ID command */ + s_command.Instruction = XSPI_FormatCommand(SalXspi->CommandExtension, s_command.InstructionWidth, Command); + + s_command.Address = Address; + s_command.DataLength = DataSize; + + /* DTR management for single/dual/quad */ + switch(SalXspi->PhyLink) + { + case PHY_LINK_4S4D4D :{ + s_command.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_ENABLE; + s_command.DataDTRMode = HAL_XSPI_DATA_DTR_ENABLE; + s_command.DummyCycles = SalXspi->DTRDummyCycle; + break; + } + case PHY_LINK_1S2S2S :{ + s_command.AddressMode = HAL_XSPI_ADDRESS_2_LINES; + s_command.DataMode = HAL_XSPI_DATA_2_LINES; + break; + } + case PHY_LINK_1S1S2S :{ + s_command.DataMode = HAL_XSPI_DATA_2_LINES; + break; + } + default :{ + /* keep default parameters */ + break; + } + } + + /* Configure the command */ + retr = HAL_XSPI_Command(SalXspi->hxspi, &s_command, SAL_XSPI_TIMEOUT_DEFAULT_VALUE); + if (retr != HAL_OK) + { + goto error; + } + + /* read the data */ + retr = XSPI_Receive(SalXspi, Data); + +error: + if (retr != HAL_OK ) + { + /* abort any ongoing transaction for the next action */ + (void)HAL_XSPI_Abort(SalXspi->hxspi); + } + return retr; +} + +HAL_StatusTypeDef SAL_XSPI_Write(SAL_XSPI_ObjectTypeDef *SalXspi, uint8_t Command, uint32_t Address, const uint8_t *Data, uint32_t DataSize) +{ + HAL_StatusTypeDef retr; + XSPI_RegularCmdTypeDef s_command = SalXspi->Commandbase; + + /* Initialize the read ID command */ + s_command.Instruction = XSPI_FormatCommand(SalXspi->CommandExtension, s_command.InstructionWidth, Command); + + s_command.Address = Address; + s_command.DataLength = DataSize; + s_command.DummyCycles = 0u; + s_command.DQSMode = HAL_XSPI_DQS_DISABLE; + + /* Configure the command */ + retr = HAL_XSPI_Command(SalXspi->hxspi, &s_command, SAL_XSPI_TIMEOUT_DEFAULT_VALUE); + if (HAL_OK != retr) + { + goto error; + } + + /* transmit data */ + retr = XSPI_Transmit(SalXspi, Data); + +error: + if (retr != HAL_OK ) + { + /* abort any ongoing transaction for the next action */ + (void)HAL_XSPI_Abort(SalXspi->hxspi); + } + return retr; +} + +HAL_StatusTypeDef SAL_XSPI_CommandSendAddress(SAL_XSPI_ObjectTypeDef *SalXspi, uint8_t Command, + uint32_t Address) +{ + HAL_StatusTypeDef retr; + XSPI_RegularCmdTypeDef s_command = SalXspi->Commandbase; + + /* Initialize the writing of status register */ + s_command.Instruction = XSPI_FormatCommand(SalXspi->CommandExtension, s_command.InstructionWidth, Command); + + if (s_command.InstructionMode == HAL_XSPI_INSTRUCTION_1_LINE) + { + s_command.AddressMode = HAL_XSPI_ADDRESS_1_LINE; + } + + s_command.Address = Address; + s_command.DummyCycles = 0U; + s_command.DataMode = HAL_XSPI_DATA_NONE; + s_command.DQSMode = HAL_XSPI_DQS_DISABLE; + + /* Send the command */ + retr = HAL_XSPI_Command(SalXspi->hxspi, &s_command, SAL_XSPI_TIMEOUT_DEFAULT_VALUE); + if (retr != HAL_OK ) + { + /* abort any ongoing transaction for the next action */ + (void)HAL_XSPI_Abort(SalXspi->hxspi); + } + return retr; +} + +HAL_StatusTypeDef SAL_XSPI_CommandSendData(SAL_XSPI_ObjectTypeDef *SalXspi, uint8_t Command, + uint8_t *Data, uint16_t DataSize) +{ + XSPI_RegularCmdTypeDef s_command = SalXspi->Commandbase; + HAL_StatusTypeDef retr; + + /* Initialize the writing of status register */ + s_command.Instruction = XSPI_FormatCommand(SalXspi->CommandExtension, s_command.InstructionWidth, Command); + + s_command.AddressMode = HAL_XSPI_ADDRESS_NONE; + s_command.DummyCycles = 0U; + s_command.DataLength = DataSize; + s_command.DQSMode = HAL_XSPI_DQS_DISABLE; + + if (DataSize == 0u) + { + s_command.DataMode = HAL_XSPI_DATA_NONE; + } + + /* Send the command */ + retr = HAL_XSPI_Command(SalXspi->hxspi, &s_command, SAL_XSPI_TIMEOUT_DEFAULT_VALUE); + + if (( retr == HAL_OK) && (DataSize != 0u)) + { + retr = HAL_XSPI_Transmit(SalXspi->hxspi, Data, SAL_XSPI_TIMEOUT_DEFAULT_VALUE); + } + + if (retr != HAL_OK ) + { + /* abort any ongoing transaction for the next action */ + (void)HAL_XSPI_Abort(SalXspi->hxspi); + } + return retr; +} + +HAL_StatusTypeDef SAL_XSPI_SendReadCommand(SAL_XSPI_ObjectTypeDef *SalXspi, uint8_t Command, + uint8_t *Data, uint16_t DataSize) +{ + XSPI_RegularCmdTypeDef s_command = SalXspi->Commandbase; + HAL_StatusTypeDef retr; + + /* Initialize the reading of status register */ + s_command.Instruction = XSPI_FormatCommand(SalXspi->CommandExtension, s_command.InstructionWidth, Command); + + s_command.AddressMode = HAL_XSPI_ADDRESS_NONE; + s_command.DummyCycles = 0u; + s_command.DataLength = DataSize; + s_command.DQSMode = HAL_XSPI_DQS_DISABLE; + + if (DataSize == 0u) + { + s_command.DataMode = HAL_XSPI_DATA_NONE; + } + + /* Send the command */ + retr = HAL_XSPI_Command(SalXspi->hxspi, &s_command, SAL_XSPI_TIMEOUT_DEFAULT_VALUE); + + if (( retr == HAL_OK) && (DataSize != 0u)) + { + /* Get the data */ + retr = HAL_XSPI_Receive(SalXspi->hxspi, Data, SAL_XSPI_TIMEOUT_DEFAULT_VALUE); + } + + if (retr != HAL_OK ) + { + /* abort any ongoing transaction for the next action */ + (void)HAL_XSPI_Abort(SalXspi->hxspi); + } + return retr; +} + +HAL_StatusTypeDef SAL_XSPI_CommandSendReadAddress(SAL_XSPI_ObjectTypeDef *SalXspi, uint8_t Command, + uint32_t Address, uint8_t *Data, uint16_t DataSize, + uint8_t ManuId) +{ + XSPI_RegularCmdTypeDef s_command = SalXspi->Commandbase; + HAL_StatusTypeDef retr; + + /* Initialize the reading of status register */ + s_command.Instruction = XSPI_FormatCommand(SalXspi->CommandExtension, s_command.InstructionWidth, Command); + + s_command.Address = Address; + s_command.DummyCycles = SalXspi->SFDPDummyCycle; + s_command.DataLength = DataSize; + /* Specific case for Macronix memories : RDID and RDCR are not Data DTR */ + if ((ManuId == EXTMEM_MANFACTURER_MACRONIX) && (s_command.DataDTRMode == HAL_XSPI_DATA_DTR_ENABLE)) + { + s_command.DataDTRMode = HAL_XSPI_DATA_DTR_DISABLE; + } + /* Specific case for GigaDevice memories : Read Configuration Register are not Data DTR */ + else if ((ManuId == 0xC8) && (s_command.DataDTRMode == HAL_XSPI_DATA_DTR_ENABLE)) + { + s_command.DataDTRMode = HAL_XSPI_DATA_DTR_DISABLE; + s_command.DQSMode = HAL_XSPI_DQS_DISABLE; + } + else + { + s_command.DQSMode = HAL_XSPI_DQS_DISABLE; + } + + /* Send the command */ + retr = HAL_XSPI_Command(SalXspi->hxspi, &s_command, SAL_XSPI_TIMEOUT_DEFAULT_VALUE); + + if ( retr == HAL_OK) + { + /* Get the data */ + retr = HAL_XSPI_Receive(SalXspi->hxspi, Data, SAL_XSPI_TIMEOUT_DEFAULT_VALUE); + } + + if (retr != HAL_OK ) + { + /* abort any ongoing transaction for the next action */ + (void)HAL_XSPI_Abort(SalXspi->hxspi); + } + return retr; +} + +HAL_StatusTypeDef SAL_XSPI_CheckStatusRegister(SAL_XSPI_ObjectTypeDef *SalXspi, uint8_t Command, uint32_t Address, + uint8_t MatchValue, uint8_t MatchMask, uint8_t ManuId, + uint32_t Timeout) +{ + XSPI_RegularCmdTypeDef s_command = SalXspi->Commandbase; + XSPI_AutoPollingTypeDef s_config = { + .MatchValue = MatchValue, + .MatchMask = MatchMask, + .MatchMode = HAL_XSPI_MATCH_MODE_AND, + .AutomaticStop = HAL_XSPI_AUTOMATIC_STOP_ENABLE, + .IntervalTime = 0x10 + }; + HAL_StatusTypeDef retr; + + /* Initialize the reading of status register */ + s_command.Instruction = XSPI_FormatCommand(SalXspi->CommandExtension, s_command.InstructionWidth, Command); + + s_command.DataLength = 1u; + s_command.DQSMode = HAL_XSPI_DQS_DISABLE; + + if (s_command.InstructionMode == HAL_XSPI_INSTRUCTION_1_LINE) + { + /* patch cypress to force 1 line on status read */ + s_command.DataMode = HAL_XSPI_DATA_1_LINE; + s_command.AddressMode = HAL_XSPI_DATA_NONE; + s_command.DummyCycles = 0u; + } + + /* @ is used only in 8 LINES format */ + if (s_command.DataMode == HAL_XSPI_DATA_8_LINES) + { + /* Specific case for Macronix memories : RDID and RDCR are not Data DTR */ + if ((ManuId == EXTMEM_MANFACTURER_MACRONIX) && (s_command.DataDTRMode == HAL_XSPI_DATA_DTR_ENABLE)) + { + s_command.DQSMode = HAL_XSPI_DQS_ENABLE; + s_command.DataDTRMode = HAL_XSPI_DATA_DTR_DISABLE; + } + s_command.AddressMode = HAL_XSPI_ADDRESS_8_LINES; + s_command.AddressWidth = HAL_XSPI_ADDRESS_32_BITS; + s_command.Address = Address; + } + + /* Send the command */ + retr = HAL_XSPI_Command(SalXspi->hxspi, &s_command, SAL_XSPI_TIMEOUT_DEFAULT_VALUE); + if ( retr == HAL_OK) + { + retr = HAL_XSPI_AutoPolling(SalXspi->hxspi, &s_config, Timeout); + DEBUG_AUTOPOLLING(SalXspi->hxspi->Instance->DR, s_config.MatchValue, s_config.MatchMask) + } + + if (retr != HAL_OK ) + { + /* abort any ongoing transaction for the next action */ + (void)HAL_XSPI_Abort(SalXspi->hxspi); + } + /* return status */ + return retr; +} + +HAL_StatusTypeDef SAL_XSPI_ConfigureWrappMode(SAL_XSPI_ObjectTypeDef *SalXspi, uint8_t WrapCommand, uint8_t WrapDummy) +{ + HAL_StatusTypeDef retr; + XSPI_RegularCmdTypeDef s_command = SalXspi->Commandbase; + + /* Initialize the read ID command */ + s_command.OperationType = HAL_XSPI_OPTYPE_WRAP_CFG; + s_command.Instruction = XSPI_FormatCommand(SalXspi->CommandExtension, s_command.InstructionWidth, WrapCommand); + s_command.DummyCycles = WrapDummy; + /* Configure the read command */ + retr = HAL_XSPI_Command(SalXspi->hxspi, &s_command, SAL_XSPI_TIMEOUT_DEFAULT_VALUE); + if ( retr != HAL_OK) + { + goto error; + } + +error: + if (retr != HAL_OK ) + { + /* abort any ongoing transaction for the next action */ + (void)HAL_XSPI_Abort(SalXspi->hxspi); + } + /* return status */ + return retr; +} + +HAL_StatusTypeDef SAL_XSPI_EnableMapMode(SAL_XSPI_ObjectTypeDef *SalXspi, uint8_t CommandRead, uint8_t DummyRead, + uint8_t CommandWrite, uint8_t DummyWrite) +{ + HAL_StatusTypeDef retr; + XSPI_RegularCmdTypeDef s_command = SalXspi->Commandbase; + XSPI_MemoryMappedTypeDef sMemMappedCfg = {0}; + + /* Initialize the read ID command */ + s_command.OperationType = HAL_XSPI_OPTYPE_READ_CFG; + s_command.Instruction = XSPI_FormatCommand(SalXspi->CommandExtension, s_command.InstructionWidth, CommandRead); + s_command.DummyCycles = DummyRead; + /* Configure the read command */ + retr = HAL_XSPI_Command(SalXspi->hxspi, &s_command, SAL_XSPI_TIMEOUT_DEFAULT_VALUE); + if ( retr != HAL_OK) + { + goto error; + } + + /* Initialize the read ID command */ + s_command.OperationType = HAL_XSPI_OPTYPE_WRITE_CFG; + s_command.Instruction = XSPI_FormatCommand(SalXspi->CommandExtension, s_command.InstructionWidth, CommandWrite); + s_command.DummyCycles = DummyWrite; + /* Configure the read command */ + retr = HAL_XSPI_Command(SalXspi->hxspi, &s_command, SAL_XSPI_TIMEOUT_DEFAULT_VALUE); + if ( retr != HAL_OK) + { + goto error; + } + + /* Activation of memory-mapped mode */ + sMemMappedCfg.TimeOutActivation = HAL_XSPI_TIMEOUT_COUNTER_DISABLE; + sMemMappedCfg.TimeoutPeriodClock = 0x50; + retr = HAL_XSPI_MemoryMapped(SalXspi->hxspi, &sMemMappedCfg); + +error: + if (retr != HAL_OK ) + { + /* abort any ongoing transaction for the next action */ + (void)HAL_XSPI_Abort(SalXspi->hxspi); + } + /* return status */ + return retr; +} + +HAL_StatusTypeDef SAL_XSPI_DisableMapMode(SAL_XSPI_ObjectTypeDef *SalXspi) +{ + __DSB(); + return HAL_XSPI_Abort(SalXspi->hxspi); +} + + +HAL_StatusTypeDef SAL_XSPI_UpdateMemoryType(SAL_XSPI_ObjectTypeDef *SalXspi, SAL_XSPI_DataOrderTypeDef DataOrder) +{ +HAL_StatusTypeDef retr = HAL_OK; + + /* read the memory type value */ + uint32_t memorytype = READ_REG(SalXspi->hxspi->Instance->DCR1) & XSPI_DCR1_MTYP; + + switch(DataOrder) + { + case SAL_XSPI_ORDERINVERTED : + if (memorytype == HAL_XSPI_MEMTYPE_MICRON) { + memorytype = HAL_XSPI_MEMTYPE_MACRONIX; + } else if (memorytype == HAL_XSPI_MEMTYPE_MACRONIX) { + memorytype = HAL_XSPI_MEMTYPE_MICRON; + } else { + retr = HAL_ERROR; + } + MODIFY_REG(SalXspi->hxspi->Instance->DCR1, XSPI_DCR1_MTYP, memorytype); + break; + default : + return HAL_ERROR; + break; + } + + DEBUG_PARAM_BEGIN(); DEBUG_PARAM_DATA("::SAL_XSPI_UpdateMemoryType::"); DEBUG_PARAM_INT(memorytype); DEBUG_PARAM_END(); + return retr; +} + +HAL_StatusTypeDef SAL_XSPI_Abort(SAL_XSPI_ObjectTypeDef *SalXspi) +{ + return HAL_XSPI_Abort(SalXspi->hxspi); +} + +/** + * @} + */ + +/** @defgroup SAL_XSPI_Private_Functions SAL XSP Private Functions + * @{ + */ +/** + * @brief This function return a formatted command + * + * @param CommandExtension type of the command extension 0: the complement 1 : the same + * @param InstructionWidth instruction width + * @param Command command + * @return the formatted command + */ +uint16_t XSPI_FormatCommand(uint8_t CommandExtension, uint32_t InstructionWidth, uint8_t Command) +{ + uint16_t retr; + if (InstructionWidth == HAL_XSPI_INSTRUCTION_16_BITS) + { + /* 0b00 The Command Extension is the same as the Command. (The Command / Command Extension has the same value for the whole clock period.)*/ + /* 0b01 The Command Extension is the inverse of the Command. The Command Extension acts as a confirmation of the Command */ + /* 0b11 Command and Command Extension forms a 16 bit command word :: Not yet handled */ + retr = ((uint16_t)Command << 8u); + if (CommandExtension == 1u) + { + retr|= (uint8_t)(~Command & 0xFFu); + } + else + { + retr|= (uint8_t)(Command & 0xFFu); + } + } + else + { + retr = Command; + } + + return retr; +} + +/** + * @brief This function trasnmits the data + * + * @param SalXspi handle on the XSPI IP + * @param Data data pointer + * @return none + */ +HAL_StatusTypeDef XSPI_Transmit(SAL_XSPI_ObjectTypeDef *SalXspi, const uint8_t *Data) +{ +HAL_StatusTypeDef retr; + +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + if (SalXspi->hxspi->hdmatx == NULL) +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + { + /* transmit data */ + retr = HAL_XSPI_Transmit(SalXspi->hxspi, Data, SAL_XSPI_TIMEOUT_DEFAULT_VALUE); + } +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + else + { + /* set completion call back */ + salXSPI_status = SALXSPI_TRANSFER_NONE; + + /* Reception of the data */ + retr = HAL_XSPI_Transmit_DMA(SalXspi->hxspi, (uint8_t *)Data); + + if (retr == HAL_OK) + { + /* wait data completion */ + while(salXSPI_status == SALXSPI_TRANSFER_NONE); + if (salXSPI_status == SALXSPI_TRANSFER_ERROR) + { + retr = HAL_ERROR; + } + } + } +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + + return retr; +} + +/** + * @brief this is called to start the data transfer in polling mode or DMA + * + * @param SalXspi handle on the XSPI IP + * @param Data data pointer + * @return none + */ +HAL_StatusTypeDef XSPI_Receive(SAL_XSPI_ObjectTypeDef *SalXspi, uint8_t *Data) +{ +HAL_StatusTypeDef retr; + +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + if (SalXspi->hxspi->hdmarx == NULL) +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + { + /* Reception of the data */ + retr = HAL_XSPI_Receive(SalXspi->hxspi, Data, SAL_XSPI_TIMEOUT_DEFAULT_VALUE); + } +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) + else + { + /* set completion call back */ + salXSPI_status = SALXSPI_TRANSFER_NONE; + + /* Reception of the data */ + retr = HAL_XSPI_Receive_DMA(SalXspi->hxspi, Data); + + if (retr == HAL_OK) + { + /* wait data completion */ + while(salXSPI_status == SALXSPI_TRANSFER_NONE); + if (salXSPI_status == SALXSPI_TRANSFER_ERROR) + { + retr = HAL_ERROR; + } + } + } +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ + return retr; +} + +#if defined (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) +/** + * @brief this is called when a DMA transfer error occurs + * + * @param hxspi handle on the XSPI IP + * @return none + */ +void SAL_XSPI_ErrorCallback(struct __XSPI_HandleTypeDef *hxspi) +{ + salXSPI_status = SALXSPI_TRANSFER_ERROR; +} + +/** + * @brief this is called when a DMA transfer is complete + * + * @param hxspi handle on the XSPI IP + * @return none + */ +void SAL_XSPI_CompleteCallback(struct __XSPI_HandleTypeDef *hxspi) +{ + salXSPI_status = SALXSPI_TRANSFER_OK; +} +#endif /* (USE_HAL_XSPI_REGISTER_CALLBACKS) && (USE_HAL_XSPI_REGISTER_CALLBACKS == 1U) */ +/** + * @} + */ + +/** + * @} + */ + +#endif /* EXTMEM_SAL_XSPI == 1 */ diff --git a/Middlewares/ST/STM32_ExtMem_Manager/sal/stm32_sal_xspi_api.h b/Middlewares/ST/STM32_ExtMem_Manager/sal/stm32_sal_xspi_api.h new file mode 100644 index 0000000..7a55c4e --- /dev/null +++ b/Middlewares/ST/STM32_ExtMem_Manager/sal/stm32_sal_xspi_api.h @@ -0,0 +1,238 @@ +/** + ****************************************************************************** + * @file stm32_sal_xspi_api.h + * @author MCD Application Team + * @brief This file contains the software adaptation layer XSPI functions + * prototypes. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_SAL_XSPI_API_H +#define __STM32_SAL_XSPI_API_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @defgroup SAL_XSPI + * @ingroup EXTMEM_SAL + * @{ + */ + +/* Includes ------------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SAL_XSPI_Exported_types SAL XSPI exported types + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SAL_XSPI_Exported_Functions SAL XSP Exported Functions + * @{ + */ +/** + * @brief This function initializes a memory + * @param SalXspi SAL XSPI handle + * @return @ref HAL_StatusTypeDef + **/ +HAL_StatusTypeDef SAL_XSPI_Init(SAL_XSPI_ObjectTypeDef* SalXspi, void* HALHandle); + +/** + * @brief This function gets SFDP data + * @param SalXspi SAL XSPI handle + * @param Address address to read the data + * @param Data Data pointer + * @param DataSize size of the data to read + * @return @ref HAL_StatusTypeDef + **/ +HAL_StatusTypeDef SAL_XSPI_GetSFDP(SAL_XSPI_ObjectTypeDef* SalXspi, uint32_t Address, + uint8_t* Data, uint32_t DataSize); + +/** + * @brief This function reads data from the flash + * @param SalXspi SAL XSPI handle + * @param Command command to execute + * @param Address address to read the data + * @param Data Data pointer + * @param DataSize size of the data to read + * @return @ref HAL_StatusTypeDef + **/ +HAL_StatusTypeDef SAL_XSPI_Read(SAL_XSPI_ObjectTypeDef* SalXspi, uint8_t Command, uint32_t Address, uint8_t* Data, uint32_t DataSize); + +/** + * @brief This function reads the flash ID + * @param SalXspi SAL XSPI handle + * @param Data data pointer + * @param DataSize number of data to read + * @return @ref HAL_StatusTypeDef + **/ +HAL_StatusTypeDef SAL_XSPI_GetId(SAL_XSPI_ObjectTypeDef* SalXspi, uint8_t* Data, uint32_t DataSize); + +/** + * @brief This function sends a command + data + * @param SalXspi SAL XSPI handle + * @param Command command to execute + * @param Data Data pointer + * @param DataSize size of the data to write + * @return @ref HAL_StatusTypeDef + **/ +HAL_StatusTypeDef SAL_XSPI_CommandSendData(SAL_XSPI_ObjectTypeDef* SalXspi, uint8_t Command, + uint8_t* Data, uint16_t DataSize); + + +/** + * @brief This function sends a command to read the data + * @param SalXspi SAL XSPI handle + * @param Command command to execute + * @param Data Data pointer + * @param DataSize size of the data to read + * @return @ref HAL_StatusTypeDef + **/ +HAL_StatusTypeDef SAL_XSPI_SendReadCommand(SAL_XSPI_ObjectTypeDef *SalXspi, uint8_t Command, + uint8_t *Data, uint16_t DataSize); + +/** + * @brief This function sends a command with address and read the data + * @param SalXspi SAL XSPI handle + * @param Command command to execute + * @param Address Address value + * @param Data Data pointer + * @param DataSize Size of the data to read + * @param ManuId Manufacturer Identifier + * @return @ref HAL_StatusTypeDef + **/ +HAL_StatusTypeDef SAL_XSPI_CommandSendReadAddress(SAL_XSPI_ObjectTypeDef *SalXspi, uint8_t Command, + uint32_t Address, uint8_t *Data, uint16_t DataSize, + uint8_t ManuId); + +/** + * @brief This function controls the status register + * @param SalXspi SAL XSPI handle + * @param Command command to execute + * @param Address specify the address + * @param MatchValue expected value + * @param MatchMask mask used to control the expected value + * @param ManuId Manufacturer Identifier + * @param Timeout timeout parameter + * @return @ref HAL_StatusTypeDef + **/ +HAL_StatusTypeDef SAL_XSPI_CheckStatusRegister(SAL_XSPI_ObjectTypeDef* SalXspi, + uint8_t Command, uint32_t Address, uint8_t MatchValue, uint8_t MatchMask, + uint8_t ManuId, uint32_t Timeout); + +/** + * @brief This function writes data at an Address + * @param SalXspi SAL XSPI handle + * @param Command command to execute + * @param Address address to write the data + * @param Data Data pointer + * @param DataSize size of the data to write + * @return @ref HAL_StatusTypeDef + **/ +HAL_StatusTypeDef SAL_XSPI_Write(SAL_XSPI_ObjectTypeDef* SalXspi, uint8_t Command, uint32_t Address, const uint8_t* Data, uint32_t DataSize); + +/** + * @brief This function sends a command and an address + * @param SalXspi SAL XSPI handle + * @param Command command to execute + * @param Address address to write the data + * @return @ref HAL_StatusTypeDef + **/ +HAL_StatusTypeDef SAL_XSPI_CommandSendAddress(SAL_XSPI_ObjectTypeDef* SalXspi, uint8_t Command, uint32_t Address); + +/** + * @brief This function sets the clock according the clock in and the expected clock + * @param SalXspi SAL XSPI handle + * @param ClockIn clock in input + * @param ClockRequested clock requested + * @param ClockReal pointer on the value of the real clock used + * @return @ref HAL_StatusTypeDef + **/ +HAL_StatusTypeDef SAL_XSPI_SetClock(SAL_XSPI_ObjectTypeDef* SalXspi, uint32_t ClockIn, uint32_t ClockRequested, uint32_t* ClockReal); + +/** + * @brief This function sets a configuration parameter + * @param SalXspi SAL XSPI handle + * @param ParametersType @ref SAL_XSPI_MemParamTypeTypeDef + * @param ParamVal pointer on the parameter value + * @return @ref HAL_StatusTypeDef + **/ +HAL_StatusTypeDef SAL_XSPI_MemoryConfig(SAL_XSPI_ObjectTypeDef* SalXspi, SAL_XSPI_MemParamTypeTypeDef ParametersType, void* ParamVal); + +/** + * @brief This function enables the memory mapped mode + * @param SalXspi SAL XSPI handle + * @param WrapCommand wrap command to execute in case of write operation + * @param WrapDummy number of dummy cycle for the read operation + * @return @ref HAL_StatusTypeDef + **/ +HAL_StatusTypeDef SAL_XSPI_ConfigureWrappMode(SAL_XSPI_ObjectTypeDef* SalXspi, uint8_t WrapCommand, uint8_t WrapDummy); + +/** + * @brief This function enables the memory mapped mode + * @param SalXspi SAL XSPI handle + * @param CommandRead command to execute in case of read operation + * @param DummyRead number of dummy cycle for the read operation + * @param CommandWrite command to execute in case of write operation + * @param DummyWrite number of dummy cycle for the read operation + * @return @ref HAL_StatusTypeDef + **/ +HAL_StatusTypeDef SAL_XSPI_EnableMapMode(SAL_XSPI_ObjectTypeDef *SalXspi, uint8_t CommandRead, uint8_t DummyRead, + uint8_t CommandWrite, uint8_t DummyWrite); + +/** + * @brief This function disables the memory mapped mode + * @param SalXspi SAL XSPI handle + * @return @ref HAL_StatusTypeDef + **/ +HAL_StatusTypeDef SAL_XSPI_DisableMapMode(SAL_XSPI_ObjectTypeDef *SalXspi); + +/** + * @brief This function updates the memory according the SFDP signature value + * @param SalXspi SAL XSPI handle + * @param DataOrder + * @return @ref HAL_StatusTypeDef + **/ +HAL_StatusTypeDef SAL_XSPI_UpdateMemoryType(SAL_XSPI_ObjectTypeDef *SalXspi, SAL_XSPI_DataOrderTypeDef DataOrder); + +/** + * @brief This function aborts the transaction + * @param SalXspi SAL XSPI handle + * @return @ref HAL_StatusTypeDef + **/ +HAL_StatusTypeDef SAL_XSPI_Abort(SAL_XSPI_ObjectTypeDef *SalXspi); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32_SAL_XSPI_API_H */ + + diff --git a/Middlewares/ST/STM32_ExtMem_Manager/sal/stm32_sal_xspi_type.h b/Middlewares/ST/STM32_ExtMem_Manager/sal/stm32_sal_xspi_type.h new file mode 100644 index 0000000..02ae9e8 --- /dev/null +++ b/Middlewares/ST/STM32_ExtMem_Manager/sal/stm32_sal_xspi_type.h @@ -0,0 +1,128 @@ +/** + ****************************************************************************** + * @file stm32_sal_xspi_type.h + * @author MCD Application Team + * @brief This file contains the software adaptation layer XSPI functions + * prototypes. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_SAL_XSPI_TYPE_H +#define __STM32_SAL_XSPI_TYPE_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup SAL_XSPI + * @ingroup EXTMEM_SAL + * @{ + */ + +/* Includes ------------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ + + +/** @defgroup SAL_XSPI_Exported_types SAL XSPI exported types + * @{ + */ + +/** + * @brief data order information + */ + +typedef enum { + SAL_XSPI_ORDERINVERTED = 0, +} SAL_XSPI_DataOrderTypeDef; + +/** + * @brief list of the supported configuration link + */ + +typedef enum { + PHY_LINK_1S1S1S, /*!< physical link configure in 1S1S1S */ + PHY_LINK_1S1S2S, /*!< physical link configure in 1S1S2S */ + PHY_LINK_1S2S2S, /*!< physical link configure in 1S2S2S */ + PHY_LINK_1S1D1D, /*!< physical link configure in 1S1D1D */ + PHY_LINK_4S4S4S, /*!< physical link configure in 4S4S4S */ + PHY_LINK_4S4D4D, /*!< physical link configure in 4S4D4D */ + PHY_LINK_4D4D4D, /*!< physical link configure in 4D4D4D */ + PHY_LINK_1S8S8S, /*!< physical link configure in 1S8S8S */ + PHY_LINK_8S8D8D, /*!< physical link configure in 8S8D8D */ + PHY_LINK_8D8D8D, /*!< physical link configure in 8D8D8D */ + + PHY_LINK_RAM8, /*!< physical link configure for RAM 8lines of data */ +#if defined(HAL_XSPI_DATA_16_LINES) + PHY_LINK_RAM16, /*!< physical link configure for RAM 16lines of data */ +#endif /* defined(HAL_XSPI_DATA_16_LINES) */ +} SAL_XSPI_PhysicalLinkTypeDef; + +typedef struct { + XSPI_HandleTypeDef *hxspi; /*!< handle on the XSPI instance */ + XSPI_RegularCmdTypeDef Commandbase; /*!< command base configuration */ + uint8_t CommandExtension; /*!< Flag on the 16-bit command extension 0 inverted 1 the same */ + uint8_t SFDPDummyCycle; /*!< SDPF dummy cycle */ + SAL_XSPI_PhysicalLinkTypeDef PhyLink; /*!< Only used for data Read in 4S4D4d 2S2D2D 1S1D1D */ + uint8_t DTRDummyCycle; /*!< Specify that DTR read only valid for data read using DTRDummyCycle value */ +} SAL_XSPI_ObjectTypeDef; + +/** + * @brief define the list of the parameter + */ +typedef enum { + PARAM_PHY_LINK, /*!< physical link parameter */ + PARAM_DUMMY_CYCLES, /*!< dummy cycle parameter */ + PARAM_ADDRESS_4BYTES, /*!< Adddress size parameter */ + PARAM_DATA_STROBE, /*!< data strobe parameter */ + PARAM_FLASHSIZE, /*!< set the flash size on the IP */ +} SAL_XSPI_MemParamTypeTypeDef; +/** + * @} + */ + +/* Exported Macro ------------------------------------------------------------*/ + +#define SAL_XSPI_SET_DTRREADDUMMYCYLE(_OBJ_,_VAL_) (_OBJ_).DTRDummyCycle = (_VAL_) +#define SAL_XSPI_SET_SFDPDUMMYCYLE(_OBJ_,_VAL_) (_OBJ_).SFDPDummyCycle = (_VAL_) +#define SAL_XSPI_SET_COMMANDEXTENSION(_OBJ_,_VAL_) (_OBJ_).CommandExtension = (_VAL_) + +#define SAL_XSPI_FORMAT_COMMANDSEND(_PTR_, _CMD_) \ + _PTR_.CommandType = SAL_XSPI_COMMAND_SEND; \ + _PTR_.Command = _CMD_; + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SAL_XSPI_Exported_Functions SAL XSP Exported Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32_SAL_XSPI_TYPE_H */ + + diff --git a/Middlewares/ST/STM32_ExtMem_Manager/sdcard/stm32_sdcard_driver.c b/Middlewares/ST/STM32_ExtMem_Manager/sdcard/stm32_sdcard_driver.c new file mode 100644 index 0000000..b8c8282 --- /dev/null +++ b/Middlewares/ST/STM32_ExtMem_Manager/sdcard/stm32_sdcard_driver.c @@ -0,0 +1,306 @@ +/** + ****************************************************************************** + * @file stm32_sdcard_driver.c + * @author MCD Application Team + * @brief This file includes a driver for SDCARD support + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_extmem.h" +#include "stm32_extmem_conf.h" +#if EXTMEM_DRIVER_SDCARD == 1 +#if EXTMEM_SAL_SD == 1 +#include "../sal/stm32_sal_sd_api.h" +#endif /* EXTMEM_SAL_SD */ +#if EXTMEM_SAL_MMC == 1 +#include "../sal/stm32_sal_mmc_api.h" +#endif /* EXTMEM_SAL_MMC */ + +#include "stm32_sdcard_driver_api.h" +#if EXTMEM_DRIVER_SDCARD_DEBUG_LEVEL > 0 && defined(EXTMEM_MACRO_DEBUG) +#include "string.h" +#include "stdio.h" +#endif /* EXTMEM_DRIVER_SDCARD_DEBUG_LEVEL > 0 || defined(EXTMEM_MACRO_DEBUG) */ + +/** @defgroup SDCARD SDCARD driver + * @ingroup EXTMEM_DRIVER + * @{ + */ + +/* Private Macros ------------------------------------------------------------*/ +/** @defgroup SDCARD_Private_Macro Private Macro + * @{ + */ + +/** + * @brief default timeout + */ +#define DRIVER_DEFAULT_TIMEOUT 300 + +/** + * @brief debug macro for a string + */ +#if EXTMEM_DRIVER_SDCARD_DEBUG_LEVEL > 0 && defined(EXTMEM_MACRO_DEBUG) +#define SDCARD_DEBUG_STR(_STR_) { \ + EXTMEM_MACRO_DEBUG("\tSDCARD::"); \ + EXTMEM_MACRO_DEBUG(_STR_); \ + EXTMEM_MACRO_DEBUG("\n\r"); \ + } +#else +#define SDCARD_DEBUG_STR(_STR_) +#endif /* EXTMEM_DRIVER_SDCARD_DEBUG_LEVEL > 0 || defined(EXTMEM_MACRO_DEBUG) */ + +/** + * @} + */ + +/* Private typedefs ---------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup SDCARD_Exported_Functions Exported Functions + * @{ + */ + +EXTMEM_DRIVER_SDCARD_StatusTypeDef EXTMEM_DRIVER_SDCARD_Init(void *Peripheral, EXTMEM_DRIVER_SDCARD_ObjectTypeDef* SDCARDObject) +{ + EXTMEM_DRIVER_SDCARD_StatusTypeDef retr = EXTMEM_DRIVER_SDCARD_OK; + + /* initialize the instance */ + SDCARD_DEBUG_STR("initialize the instance") + switch(SDCARDObject->sdcard_public.Link) + { + case EXTMEM_DRIVER_SDCARD_LINKSD : + if( HAL_OK != SAL_SD_Init(&SDCARDObject->sdcard_private.SALObject.SDObject, Peripheral, &SDCARDObject->sdcard_private.Info)) + { + retr = EXTMEM_DRIVER_SDCARD_ERROR; + } + break; +#if EXTMEM_SAL_MMC == 1 + case EXTMEM_DRIVER_SDCARD_LINKMMC: + if( HAL_OK != SAL_MMC_Init(&SDCARDObject->SALObject.MMCObject, Peripheral)) + { + retr = EXTMEM_DRIVER_SDCARD_ERROR; + } + break; +#endif /* EXTMEM_SAL_MMC == 1 */ + default : + retr = EXTMEM_DRIVER_SDCARD_ERROR_LINKTYPE; + break; + } + + return retr; +} + +EXTMEM_DRIVER_SDCARD_StatusTypeDef EXTMEM_DRIVER_SDCARD_DeInit(EXTMEM_DRIVER_SDCARD_ObjectTypeDef* SDCARDObject) +{ + EXTMEM_DRIVER_SDCARD_StatusTypeDef retr = EXTMEM_DRIVER_SDCARD_OK; + SDCARDObject->sdcard_private.Info.BlockNbr = 0; + return retr; +} + +EXTMEM_DRIVER_SDCARD_StatusTypeDef EXTMEM_DRIVER_SDCARD_Read(EXTMEM_DRIVER_SDCARD_ObjectTypeDef* SDCARDObject, + uint32_t Address, uint8_t* Data, uint32_t Size) +{ + EXTMEM_DRIVER_SDCARD_StatusTypeDef retr = EXTMEM_DRIVER_SDCARD_OK; + HAL_StatusTypeDef hal_status = HAL_OK; + uint32_t block_size = SDCARDObject->sdcard_private.Info.BlockSize; + + if (block_size == 0u) + { + retr = EXTMEM_DRIVER_SDCARD_ERROR; + } + else + { + uint32_t block_num = Address / block_size; + uint32_t block_count = Size / block_size; + + /* check if*/ + if(((Address % block_size) != 0u ) || ((Size % block_size) != 0u)) + { + retr = EXTMEM_DRIVER_SDCARD_ERROR_PARAM; + goto error; + } + + if( block_count > SDCARDObject->sdcard_private.Info.BlockNbr) + { + retr = EXTMEM_DRIVER_SDCARD_ERROR_PARAM; + goto error; + } + + switch(SDCARDObject->sdcard_public.Link) + { + case EXTMEM_DRIVER_SDCARD_LINKSD : + hal_status = SAL_SD_ReadData(&SDCARDObject->sdcard_private.SALObject.SDObject, block_num, Data, block_count); + break; +#if EXTMEM_SAL_MMC == 1 + case EXTMEM_DRIVER_SDCARD_LINKMMC: + hal_status = SAL_MMC_Read(&SDCARDObject->sdcard_private.SALObject.MMCObject, block_num, Data, block_count); + break; +#endif /* EXTMEM_SAL_MMC == 1 */ + default : + retr = EXTMEM_DRIVER_SDCARD_ERROR_LINKTYPE; + break; + } + + if (HAL_OK != hal_status) + { + retr = EXTMEM_DRIVER_SDCARD_ERROR_READ; + } + } +error: + return retr; +} + +EXTMEM_DRIVER_SDCARD_StatusTypeDef EXTMEM_DRIVER_SDCARD_Write(EXTMEM_DRIVER_SDCARD_ObjectTypeDef* SDCARDObject, + uint32_t Address, const uint8_t *Data, uint32_t Size) +{ + EXTMEM_DRIVER_SDCARD_StatusTypeDef retr = EXTMEM_DRIVER_SDCARD_OK; + HAL_StatusTypeDef hal_status = HAL_OK; + uint32_t block_size = SDCARDObject->sdcard_private.Info.BlockSize; + if (block_size == 0u) + { + retr = EXTMEM_DRIVER_SDCARD_ERROR; + } + else + { + uint32_t block_num = Address / block_size; + uint32_t block_count = Size / block_size; + + /* check if */ + if(((Address % block_size) != 0u ) || ((Size % block_size) != 0u)) + { + retr = EXTMEM_DRIVER_SDCARD_ERROR_PARAM; + goto error; + } + + if( block_count > SDCARDObject->sdcard_private.Info.BlockNbr) + { + retr = EXTMEM_DRIVER_SDCARD_ERROR_PARAM; + goto error; + } + + switch(SDCARDObject->sdcard_public.Link) + { + case EXTMEM_DRIVER_SDCARD_LINKSD : + hal_status = SAL_SD_WriteData(&SDCARDObject->sdcard_private.SALObject.SDObject, block_num, Data, block_count); + break; + case EXTMEM_DRIVER_SDCARD_LINKMMC: + default : + retr = EXTMEM_DRIVER_SDCARD_ERROR_LINKTYPE; + break; + } + + if (HAL_OK != hal_status) + { + retr = EXTMEM_DRIVER_SDCARD_ERROR_WRITE; + } + } +error: + return retr; +} + +EXTMEM_DRIVER_SDCARD_StatusTypeDef EXTMEM_DRIVER_SDCARD_EraseBlock(EXTMEM_DRIVER_SDCARD_ObjectTypeDef* SDCARDObject, + uint32_t Address, uint32_t Size) +{ + EXTMEM_DRIVER_SDCARD_StatusTypeDef retr = EXTMEM_DRIVER_SDCARD_OK; + HAL_StatusTypeDef hal_status = HAL_OK; + uint32_t block_size = SDCARDObject->sdcard_private.Info.BlockSize; + + if (block_size == 0u) + { + retr = EXTMEM_DRIVER_SDCARD_ERROR; + } + else + { + uint32_t block_num = Address / block_size; + uint32_t block_count = Size / block_size; + + if ((Size % block_size) != 0u) + { + block_count = block_count + 1u; + } + + /* check if */ + if((Address % block_size) != 0u) + { + retr = EXTMEM_DRIVER_SDCARD_ERROR_PARAM; + goto error; + } + + if( block_count > SDCARDObject->sdcard_private.Info.BlockNbr) + { + retr = EXTMEM_DRIVER_SDCARD_ERROR_PARAM; + goto error; + } + + switch(SDCARDObject->sdcard_public.Link) + { + case EXTMEM_DRIVER_SDCARD_LINKSD : + hal_status = SAL_SD_EraseBlock(&SDCARDObject->sdcard_private.SALObject.SDObject, block_num, block_count); + break; + case EXTMEM_DRIVER_SDCARD_LINKMMC: + default : + retr = EXTMEM_DRIVER_SDCARD_ERROR_LINKTYPE; + break; + } + + if (HAL_OK != hal_status) + { + retr = EXTMEM_DRIVER_SDCARD_ERROR; + } + } +error: + return retr; +} + +EXTMEM_DRIVER_SDCARD_StatusTypeDef EXTMEM_DRIVER_SDCARD_Erase(EXTMEM_DRIVER_SDCARD_ObjectTypeDef* SDCARDObject) +{ + EXTMEM_DRIVER_SDCARD_StatusTypeDef retr = EXTMEM_DRIVER_SDCARD_OK; + HAL_StatusTypeDef hal_status = HAL_OK; + switch(SDCARDObject->sdcard_public.Link) + { + case EXTMEM_DRIVER_SDCARD_LINKSD : + hal_status = SAL_SD_MassErase(&SDCARDObject->sdcard_private.SALObject.SDObject); + break; + case EXTMEM_DRIVER_SDCARD_LINKMMC: + default : + retr = EXTMEM_DRIVER_SDCARD_ERROR_LINKTYPE; + break; + } + + if (HAL_OK != hal_status) + { + retr = EXTMEM_DRIVER_SDCARD_ERROR; + } + return retr; +} + +EXTMEM_DRIVER_SDCARD_StatusTypeDef EXTMEM_DRIVER_SDCARD_GetInfo(EXTMEM_DRIVER_SDCARD_ObjectTypeDef* SDCARDObject, EXTMEM_DRIVER_SDCARD_InfoTypeDef *Info) +{ + Info->BlockSize = SDCARDObject->sdcard_private.Info.BlockSize; + Info->BlockNbr = SDCARDObject->sdcard_private.Info.BlockNbr; + return EXTMEM_DRIVER_SDCARD_OK; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* EXTMEM_DRIVER_SDCARD == 1 */ diff --git a/Middlewares/ST/STM32_ExtMem_Manager/sdcard/stm32_sdcard_driver_api.h b/Middlewares/ST/STM32_ExtMem_Manager/sdcard/stm32_sdcard_driver_api.h new file mode 100644 index 0000000..52fbe67 --- /dev/null +++ b/Middlewares/ST/STM32_ExtMem_Manager/sdcard/stm32_sdcard_driver_api.h @@ -0,0 +1,138 @@ +/** + ****************************************************************************** + * @file stm32_sdcard_driver_api.h + * @author MCD Application Team + * @brief This file contains the sd card driver definition. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_SDCARD_DRIVER_API_H +#define __STM32_SDCARD_DRIVER_API_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#if EXTMEM_DRIVER_SDCARD == 1 + +/** @addtogroup SDCARD + * @ingroup EXTMEM_DRIVER + * @{ + */ + +/* Exported constants --------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ + +/** @addtogroup SDCARD_Exported_Types + * @{ + */ + +/** + * @brief list of error code of the SDCARD driver + */ +typedef enum { + EXTMEM_DRIVER_SDCARD_OK = 0, /*!< status ok */ + EXTMEM_DRIVER_SDCARD_ERROR_LINKTYPE = -1, /*!< error on the link type */ + EXTMEM_DRIVER_SDCARD_ERROR_READ = -2, /*!< error on the read operation */ + EXTMEM_DRIVER_SDCARD_ERROR_WRITE = -3, /*!< error on the write operation */ + EXTMEM_DRIVER_SDCARD_ERROR_PARAM = -4, /*!< error on the parameter */ + EXTMEM_DRIVER_SDCARD_ERROR =-128, /*!< error */ +} EXTMEM_DRIVER_SDCARD_StatusTypeDef; + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** + * @addtogroup SDCARD_Exported_Functions exported functions + * @{ + */ +/** + * @brief This function initializes the driver SDCARD + * @param Peripheral pointer on preipheral object + * @param SDCARDObject object SDCARD + * @return @ref EXTMEM_DRIVER_SDCARD_StatusTypeDef + **/ +EXTMEM_DRIVER_SDCARD_StatusTypeDef EXTMEM_DRIVER_SDCARD_Init(void *Peripheral, + EXTMEM_DRIVER_SDCARD_ObjectTypeDef* SDCARDObject); + +/** + * @brief This function un-initializes the driver SDCARD + * @param SDCARDObject object SDCARD + * @return @ref EXTMEM_DRIVER_SDCARD_StatusTypeDef + **/ +EXTMEM_DRIVER_SDCARD_StatusTypeDef EXTMEM_DRIVER_SDCARD_DeInit(EXTMEM_DRIVER_SDCARD_ObjectTypeDef* SDCARDObject); + +/** + * @brief This function reads SDCARD memory + * @param SDCARDObject object SDCARD + * @param Address memory address + * @param Data pointer on the data + * @param Size data size to read + * @return @ref EXTMEM_DRIVER_SDCARD_StatusTypeDef + **/ +EXTMEM_DRIVER_SDCARD_StatusTypeDef EXTMEM_DRIVER_SDCARD_Read(EXTMEM_DRIVER_SDCARD_ObjectTypeDef* SDCARDObject, + uint32_t Address, uint8_t* Data, uint32_t Size); +/** + * @brief This function writes data on the SDCARD memory + * @param SDCARDObject object SDCARD + * @param Address memory address + * @param Data pointer on the data + * @param Size data size to write + * @return @ref EXTMEM_DRIVER_SDCARD_StatusTypeDef + **/ +EXTMEM_DRIVER_SDCARD_StatusTypeDef EXTMEM_DRIVER_SDCARD_Write(EXTMEM_DRIVER_SDCARD_ObjectTypeDef* SDCARDObject, + uint32_t Address, const uint8_t* Data, uint32_t Size); + +/** + * @brief This function erases SDCARD blocks + * @param SDCARDObject object SDCARD + * @param Address memory address + * @param Size data size to erase + * @return @ref EXTMEM_DRIVER_SDCARD_StatusTypeDef + **/ +EXTMEM_DRIVER_SDCARD_StatusTypeDef EXTMEM_DRIVER_SDCARD_EraseBlock(EXTMEM_DRIVER_SDCARD_ObjectTypeDef* SDCARDObject, + uint32_t Address, uint32_t Size); + +/** + * @brief This function erases the SDCARD memory + * @param SDCARDObject object SDCARD + * @return @ref EXTMEM_DRIVER_SDCARD_StatusTypeDef + **/ +EXTMEM_DRIVER_SDCARD_StatusTypeDef EXTMEM_DRIVER_SDCARD_Erase(EXTMEM_DRIVER_SDCARD_ObjectTypeDef* SDCARDObject); + +/** + * @brief This function gets the SDCARD information + * @param SDCARDObject SD card object + * @param Info pointer on SDcard information struct + * @return @ref EXTMEM_DRIVER_SDCARD_StatusTypeDef + **/ +EXTMEM_DRIVER_SDCARD_StatusTypeDef EXTMEM_DRIVER_SDCARD_GetInfo(EXTMEM_DRIVER_SDCARD_ObjectTypeDef* SDCARDObject, EXTMEM_DRIVER_SDCARD_InfoTypeDef *Info); + +/** + * @} + */ + +/** + * @} + */ +#endif /* EXTMEM_DRIVER_SDCARD == 1 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32_SDCARD_DRIVER_API_H */ diff --git a/Middlewares/ST/STM32_ExtMem_Manager/sdcard/stm32_sdcard_driver_type.h b/Middlewares/ST/STM32_ExtMem_Manager/sdcard/stm32_sdcard_driver_type.h new file mode 100644 index 0000000..f610321 --- /dev/null +++ b/Middlewares/ST/STM32_ExtMem_Manager/sdcard/stm32_sdcard_driver_type.h @@ -0,0 +1,90 @@ +/** + ****************************************************************************** + * @file stm32_sdcard_type.h + * @author MCD Application Team + * @brief This file contains the sd card driver definition. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_SDCARD_TYPE_H +#define __STM32_SDCARD_TYPE_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#if EXTMEM_DRIVER_SDCARD == 1 + +/** @addtogroup SDCARD + * @ingroup EXTMEM_DRIVER + * @{ + */ +/* Exported constants --------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SDCARD_Exported_Types Exported Types + * @{ + */ + +/** + * @brief physical link to drive SDCARD communication + */ +typedef enum { + EXTMEM_DRIVER_SDCARD_LINKSD, /*!< link SD card */ + EXTMEM_DRIVER_SDCARD_LINKMMC, /*!< link EMMC card */ + EXTMEM_DRIVER_SDCARD_LINKSPI /*!< link SPI card */ +} SDCardLinkTypeDef; + +/** + * @brief driver SDCARD instance definition + */ + typedef struct + { + struct + { + SDCardLinkTypeDef Link; /*!< physical link */ + }sdcard_public; + + struct + { + EXTMEM_DRIVER_SDCARD_InfoTypeDef Info; /*!< sdcard information */ + union + { +#if EXTMEM_SAL_SD == 1 + SAL_SD_ObjectTypeDef SDObject; /*!< SD Object memory */ +#endif /* EXTMEM_SAL_SD == 1 */ +#if EXTMEM_SAL_MMC == 1 + SAL_MMC_ObjectTypeDef MMCObject; /*!< MMC Object memory */ +#endif /* EXTMEM_SAL_MMC == 1 */ + } SALObject; + }sdcard_private; + +} EXTMEM_DRIVER_SDCARD_ObjectTypeDef; + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** + * @} + */ +#endif /* EXTMEM_DRIVER_SDCARD == 1 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32_SDCARD_TYPE_H */ diff --git a/Middlewares/ST/STM32_ExtMem_Manager/stm32_extmem.c b/Middlewares/ST/STM32_ExtMem_Manager/stm32_extmem.c new file mode 100644 index 0000000..a7dbb74 --- /dev/null +++ b/Middlewares/ST/STM32_ExtMem_Manager/stm32_extmem.c @@ -0,0 +1,849 @@ +/** + ****************************************************************************** + * @file stm32_extmem.c + * @author MCD Application Team + * @brief This file includes a driver for external memory support + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/** + * @brief macro to get memory table definition + */ +#define EXTMEM_C + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_extmem.h" +#include "stm32_extmem_conf.h" + +#if EXTMEM_DRIVER_NOR_SFDP == 1 +#include "nor_sfdp/stm32_sfdp_driver_api.h" +#endif /* EXTMEM_DRIVER_NOR_SFDP */ + +#if EXTMEM_DRIVER_PSRAM == 1 +#include "psram/stm32_psram_driver_api.h" +#endif /* EXTMEM_DRIVER_PSRAM */ + +#if EXTMEM_DRIVER_SDCARD == 1 +#include "sdcard/stm32_sdcard_driver_api.h" +#endif /* EXTMEM_DRIVER_SDCARD */ + +#if EXTMEM_DRIVER_USER == 1 +#include "user/stm32_user_driver_api.h" +#endif /* EXTMEM_DRIVER_USER */ + +/** + * @defgroup EXTMEM_DRIVER + * @{ + */ + +/** + * @} + */ + +/** + * @defgroup EXTMEM_SAL + * @{ + */ + +/** + * @} + */ + +/** + * @defgroup EXTMEM + * @{ + */ + +/* Private Macros ------------------------------------------------------------*/ +/** + * @defgroup EXTMEM_Private_Macros External Memory Private Macros + * @{ + */ +/** + * @brief EXTMEM debug function + */ +/** + * @brief Macro used to trace EXTMEM function calls + */ + +#if defined(EXTMEM_DEBUG_LEVEL) && defined(EXTMEM_MACRO_DEBUG) +#if EXTMEM_DEBUG_LEVEL > 0 +#define EXTMEM_DEBUG(_MSG_) EXTMEM_MACRO_DEBUG(_MSG_) +#if EXTMEM_DEBUG_LEVEL > 1 +#define EXTMEM_FUNC_CALL() \ + do \ + { \ + EXTMEM_DEBUG(__func__); \ + EXTMEM_DEBUG("\n"); \ + } while (0); +#else +#define EXTMEM_FUNC_CALL() +#endif /* EXTMEM_DEBUG_LEVEL > 1 */ +#else +#define EXTMEM_DEBUG(_MSG_) +#define EXTMEM_FUNC_CALL() +#endif /* EXTMEM_DEBUG_LEVEL > 0 */ +#else +#define EXTMEM_DEBUG(_MSG_) +#define EXTMEM_FUNC_CALL() +#endif /* defined(EXTMEM_DEBUG_LEVEL) && defined(EXTMEM_MACRO_DEBUG) */ + +/** + * @brief Macro used to trace EXTMEM debug information + */ +#define EXTMEM_DEBUG_ENDL(_STRING_) \ + do \ + { \ + EXTMEM_DEBUG(_STRING_); \ + EXTMEM_DEBUG("\n"); \ + } while (0); + +/** + * @} + */ + +/* Private typedefs ---------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported variables ---------------------------------------------------------*/ +/** @defgroup EXTMEM_Exported_Functions External Memory Exported Functions + * @{ + */ + +EXTMEM_StatusTypeDef EXTMEM_Init(uint32_t MemId, uint32_t ClockInput) +{ + EXTMEM_StatusTypeDef retr = EXTMEM_ERROR_INVALID_ID; + EXTMEM_FUNC_CALL(); + + /* control the memory ID */ + if (MemId < (sizeof(extmem_list_config) / sizeof(EXTMEM_DefinitionTypeDef))) + { + retr = EXTMEM_OK; + switch (extmem_list_config[MemId].MemType) + { +#if EXTMEM_DRIVER_NOR_SFDP == 1 + case EXTMEM_NOR_SFDP:{ + /* Initialize the SFDP memory */ + if (EXTMEM_DRIVER_NOR_SFDP_OK != EXTMEM_DRIVER_NOR_SFDP_Init(extmem_list_config[MemId].Handle, + extmem_list_config[MemId].ConfigType, + ClockInput, + &extmem_list_config[MemId].NorSfdpObject)) + { + retr = EXTMEM_ERROR_DRIVER; + } + break; + } +#endif /* EXTMEM_DRIVER_NOR_SFDP == 1 */ +#if EXTMEM_DRIVER_SDCARD == 1 + case EXTMEM_SDCARD:{ + /* Initialize the SFDP memory */ + if (EXTMEM_DRIVER_SDCARD_OK != EXTMEM_DRIVER_SDCARD_Init(extmem_list_config[MemId].Handle, + &extmem_list_config[MemId].SdCardObject)) + { + retr = EXTMEM_ERROR_DRIVER; + } + break; + } +#endif /* EXTMEM_DRIVER_SDCARD == 1 */ +#if EXTMEM_DRIVER_PSRAM == 1 + case EXTMEM_PSRAM : { + /* Initialize the SFDP memory */ + if (EXTMEM_DRIVER_PSRAM_OK != EXTMEM_DRIVER_PSRAM_Init(extmem_list_config[MemId].Handle, + extmem_list_config[MemId].ConfigType, + ClockInput, + &extmem_list_config[MemId].PsramObject)) + { + retr = EXTMEM_ERROR_DRIVER; + } + break; + } +#endif /* EXTMEM_DRIVER_PSRAM == 1 */ +#if EXTMEM_DRIVER_USER == 1 + case EXTMEM_USER :{ + /* Initialize the SFDP memory */ + EXTMEM_DRIVER_USER_StatusTypeDef status; + status = EXTMEM_DRIVER_USER_Init(MemId, + &extmem_list_config[MemId].UserObject); + switch(status){ + case EXTMEM_DRIVER_USER_NOTSUPPORTED:{ + retr = EXTMEM_ERROR_NOTSUPPORTED; + break; + } + case EXTMEM_DRIVER_USER_OK:{ + /* nothing to do */ + retr = EXTMEM_OK; + break; + } + default:{ + retr = EXTMEM_ERROR_DRIVER; + break; + } + } + break; + } +#endif /* EXTMEM_DRIVER_USER == 1 */ + default:{ + EXTMEM_DEBUG("\terror unknown type\n"); + retr = EXTMEM_ERROR_UNKNOWNMEMORY; + break; + } + } + } + return retr; +} + +EXTMEM_StatusTypeDef EXTMEM_DeInit(uint32_t MemId) +{ + EXTMEM_StatusTypeDef retr = EXTMEM_ERROR_INVALID_ID; + EXTMEM_FUNC_CALL(); + + /* control the memory ID */ + if (MemId < (sizeof(extmem_list_config) / sizeof(EXTMEM_DefinitionTypeDef))) + { + retr = EXTMEM_OK; + switch (extmem_list_config[MemId].MemType) + { +#if EXTMEM_DRIVER_NOR_SFDP == 1 + case EXTMEM_NOR_SFDP:{ + /* UnInitialize the SFDP memory, the return is always OK no need to test the returned value */ + (void)EXTMEM_DRIVER_NOR_SFDP_DeInit(&extmem_list_config[MemId].NorSfdpObject); + break; + } +#endif /* EXTMEM_DRIVER_NOR_SFDP == 1 */ +#if EXTMEM_DRIVER_SDCARD == 1 + case EXTMEM_SDCARD:{ + /* UnInitialize the SDCRAD memory */ + if (EXTMEM_DRIVER_SDCARD_OK != EXTMEM_DRIVER_SDCARD_DeInit(&extmem_list_config[MemId].SdCardObject)) + { + retr = EXTMEM_ERROR_DRIVER; + } + break; + } +#endif /* EXTMEM_DRIVER_SDCARD == 1 */ +#if EXTMEM_DRIVER_PSRAM == 1 + case EXTMEM_PSRAM : { + /* UnInitialize the PSRAM memory, the return is always OK no need to test the returned value */ + (void)EXTMEM_DRIVER_PSRAM_DeInit(&extmem_list_config[MemId].PsramObject); + break; + } +#endif /* EXTMEM_DRIVER_PSRAM == 1 */ +#if EXTMEM_DRIVER_USER == 1 + case EXTMEM_USER :{ + /* Initialize the SFDP memory */ + EXTMEM_DRIVER_USER_StatusTypeDef status = EXTMEM_DRIVER_USER_DeInit(&extmem_list_config[MemId].UserObject); + switch(status){ + case EXTMEM_DRIVER_USER_NOTSUPPORTED: + retr = EXTMEM_ERROR_NOTSUPPORTED; + break; + case EXTMEM_DRIVER_USER_OK: + /* nothing to do, the returned status is already set to EXTMEM_OK */ + break; + default: + retr = EXTMEM_ERROR_DRIVER; + break; + } + break; + } +#endif /* EXTMEM_DRIVER_USER == 1 */ + default:{ + EXTMEM_DEBUG("\terror unknown type\n"); + retr = EXTMEM_ERROR_UNKNOWNMEMORY; + break; + } + } + } + return retr; +} + +EXTMEM_StatusTypeDef EXTMEM_Read(uint32_t MemId, uint32_t Address, uint8_t* Data, uint32_t Size) +{ + EXTMEM_StatusTypeDef retr = EXTMEM_ERROR_INVALID_ID; + EXTMEM_FUNC_CALL() + + /* control the memory ID */ + if (MemId < (sizeof(extmem_list_config) / sizeof(EXTMEM_DefinitionTypeDef))) + { + retr = EXTMEM_OK; + switch (extmem_list_config[MemId].MemType) + { +#if EXTMEM_DRIVER_NOR_SFDP == 1 + case EXTMEM_NOR_SFDP:{ + if (EXTMEM_DRIVER_NOR_SFDP_OK != EXTMEM_DRIVER_NOR_SFDP_Read(&extmem_list_config[MemId].NorSfdpObject, + Address, Data, Size)) + { + retr = EXTMEM_ERROR_DRIVER; + } + break; + } +#endif /* EXTMEM_DRIVER_NOR_SFDP == 1 */ +#if EXTMEM_DRIVER_SDCARD == 1 + case EXTMEM_SDCARD:{ + if (EXTMEM_DRIVER_SDCARD_OK != EXTMEM_DRIVER_SDCARD_Read(&extmem_list_config[MemId].SdCardObject, + Address, Data, Size)) + { + retr = EXTMEM_ERROR_DRIVER; + } + break; + } +#endif /* EXTMEM_DRIVER_SDCARD == 1 */ +#if EXTMEM_DRIVER_PSRAM == 1 + case EXTMEM_PSRAM : { + retr = EXTMEM_ERROR_NOTSUPPORTED; + break; + } +#endif /* EXTMEM_DRIVER_PSRAM == 1 */ +#if EXTMEM_DRIVER_USER == 1 + case EXTMEM_USER :{ + /* Initialize the SFDP memory */ + EXTMEM_DRIVER_USER_StatusTypeDef status = EXTMEM_DRIVER_USER_Read(&extmem_list_config[MemId].UserObject, + Address, Data, Size); + switch(status){ + case EXTMEM_DRIVER_USER_NOTSUPPORTED: + retr = EXTMEM_ERROR_NOTSUPPORTED; + break; + case EXTMEM_DRIVER_USER_OK: + /* nothing to do, the returned status is already set to EXTMEM_OK */ + break; + default: + retr = EXTMEM_ERROR_DRIVER; + break; + } + break; + } +#endif /* EXTMEM_DRIVER_USER == 1 */ + default:{ + EXTMEM_DEBUG("\terror unknown type\n"); + retr = EXTMEM_ERROR_UNKNOWNMEMORY; + break; + } + } + } + return retr; +} + +EXTMEM_StatusTypeDef EXTMEM_Write(uint32_t MemId, uint32_t Address, const uint8_t* Data, uint32_t Size) +{ + EXTMEM_StatusTypeDef retr = EXTMEM_ERROR_INVALID_ID; + EXTMEM_FUNC_CALL() + + /* control the memory ID */ + if (MemId < (sizeof(extmem_list_config) / sizeof(EXTMEM_DefinitionTypeDef))) + { + retr = EXTMEM_OK; + switch (extmem_list_config[MemId].MemType) + { +#if EXTMEM_DRIVER_NOR_SFDP == 1 + case EXTMEM_NOR_SFDP:{ + if (EXTMEM_DRIVER_NOR_SFDP_OK != EXTMEM_DRIVER_NOR_SFDP_Write(&extmem_list_config[MemId].NorSfdpObject, + Address, Data, Size)) + { + retr = EXTMEM_ERROR_DRIVER; + } + break; + } +#endif /* EXTMEM_DRIVER_NOR_SFDP == 1 */ +#if EXTMEM_DRIVER_SDCARD == 1 + case EXTMEM_SDCARD:{ + /* Initialize the SFDP memory */ + if (EXTMEM_DRIVER_SDCARD_OK != EXTMEM_DRIVER_SDCARD_Write(&extmem_list_config[MemId].SdCardObject, + Address, Data, Size)) + { + retr = EXTMEM_ERROR_DRIVER; + } + break; + } +#endif /* EXTMEM_DRIVER_SDCARD == 1 */ +#if EXTMEM_DRIVER_PSRAM == 1 + case EXTMEM_PSRAM : { + retr = EXTMEM_ERROR_NOTSUPPORTED; + break; + } +#endif /* EXTMEM_DRIVER_PSRAM == 1 */ +#if EXTMEM_DRIVER_USER == 1 + case EXTMEM_USER :{ + /* Initialize the SFDP memory */ + EXTMEM_DRIVER_USER_StatusTypeDef status = EXTMEM_DRIVER_USER_Write(&extmem_list_config[MemId].UserObject, + Address, Data, Size); + switch(status){ + case EXTMEM_DRIVER_USER_NOTSUPPORTED: + retr = EXTMEM_ERROR_NOTSUPPORTED; + break; + case EXTMEM_DRIVER_USER_OK: + break; + default: + retr = EXTMEM_ERROR_DRIVER; + break; + } + break; + } +#endif /* EXTMEM_DRIVER_USER == 1 */ + default:{ + EXTMEM_DEBUG("\terror unknown type\n"); + retr = EXTMEM_ERROR_UNKNOWNMEMORY; + break; + } + } + } + return retr; +} + +EXTMEM_StatusTypeDef EXTMEM_WriteInMappedMode(uint32_t MemId, uint32_t Address, const uint8_t* const Data, uint32_t Size) +{ + EXTMEM_StatusTypeDef retr = EXTMEM_ERROR_INVALID_ID; + EXTMEM_FUNC_CALL() + + /* control the memory ID */ + if (MemId < (sizeof(extmem_list_config) / sizeof(EXTMEM_DefinitionTypeDef))) + { + retr = EXTMEM_OK; + switch (extmem_list_config[MemId].MemType) + { +#if EXTMEM_DRIVER_NOR_SFDP == 1 + case EXTMEM_NOR_SFDP:{ + if (EXTMEM_DRIVER_NOR_SFDP_OK != EXTMEM_DRIVER_NOR_SFDP_WriteInMappedMode(&extmem_list_config[MemId].NorSfdpObject, + Address, Data, Size)) + { + retr = EXTMEM_ERROR_DRIVER; + } + break; + } +#endif /* EXTMEM_DRIVER_NOR_SFDP == 1 */ + case EXTMEM_SDCARD : + case EXTMEM_PSRAM : + case EXTMEM_USER : + retr = EXTMEM_ERROR_NOTSUPPORTED; + break; + default:{ + EXTMEM_DEBUG("\terror unknown type\n"); + retr = EXTMEM_ERROR_UNKNOWNMEMORY; + break; + } + } + } + return retr; + } + +EXTMEM_StatusTypeDef EXTMEM_EraseSector(uint32_t MemId, uint32_t Address, uint32_t Size) +{ + EXTMEM_StatusTypeDef retr = EXTMEM_ERROR_INVALID_ID; + EXTMEM_FUNC_CALL() + + /* control the memory ID */ + if (MemId < (sizeof(extmem_list_config) / sizeof(EXTMEM_DefinitionTypeDef))) + { + retr = EXTMEM_OK; + switch (extmem_list_config[MemId].MemType) + { +#if EXTMEM_DRIVER_NOR_SFDP == 1 + case EXTMEM_NOR_SFDP:{ + const EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef* const object = &extmem_list_config[MemId].NorSfdpObject; + EXTMEM_DRIVER_NOR_SFDP_SectorTypeTypeDef sector_type = EXTMEM_DRIVER_NOR_SFDP_SECTOR_TYPE1; + uint32_t local_address = Address; + uint32_t local_size = Size; + uint32_t sector_size = (uint32_t)1u << object->sfdp_private.DriverInfo.EraseType4Size; + + while (local_size != 0u) + { + /* if address is a modulo a sector size if sector */ + if ((object->sfdp_private.DriverInfo.EraseType4Size != 0u) + && (local_size >= sector_size) + && ((local_address % sector_size) == 0u)) + { + sector_type = EXTMEM_DRIVER_NOR_SFDP_SECTOR_TYPE4; + } + else + { + sector_size = (uint32_t)1u << object->sfdp_private.DriverInfo.EraseType3Size; + if ((object->sfdp_private.DriverInfo.EraseType3Size != 0u) + && (local_size >= sector_size) + && ((local_address % sector_size) == 0u)) + { + sector_type = EXTMEM_DRIVER_NOR_SFDP_SECTOR_TYPE3; + } + else + { + sector_size = (uint32_t)1u << object->sfdp_private.DriverInfo.EraseType2Size; + if ((object->sfdp_private.DriverInfo.EraseType2Size != 0u) + && (local_size >= sector_size) + && ((local_address % sector_size) == 0u)) + { + sector_type = EXTMEM_DRIVER_NOR_SFDP_SECTOR_TYPE2; + } + else + { + sector_size = (uint32_t)1u << object->sfdp_private.DriverInfo.EraseType1Size; + if ((object->sfdp_private.DriverInfo.EraseType1Size != 0u) + && ((local_address % sector_size) == 0u)) + { + sector_type = EXTMEM_DRIVER_NOR_SFDP_SECTOR_TYPE1; + } + else + { + retr = EXTMEM_ERROR_SECTOR_SIZE; + } + } + } + } + + if (retr == EXTMEM_OK) + { + if (EXTMEM_DRIVER_NOR_SFDP_OK != EXTMEM_DRIVER_NOR_SFDP_SectorErase(&extmem_list_config[MemId].NorSfdpObject, + local_address, sector_type)) + { + retr = EXTMEM_ERROR_DRIVER; + } + } + + if (retr != EXTMEM_OK) + { + local_size = 0u; + } + else + { + local_address = local_address + sector_size; + if (sector_size > local_size) + { + local_size = 0u; + } + else + { + local_size = local_size - sector_size; + } + } + } + break; + } +#endif /* EXTMEM_DRIVER_NOR_SFDP == 1 */ +#if EXTMEM_DRIVER_SDCARD == 1 + case EXTMEM_SDCARD:{ + /* Initialize the SFDP memory */ + if (EXTMEM_DRIVER_SDCARD_OK != EXTMEM_DRIVER_SDCARD_EraseBlock(&extmem_list_config[MemId].SdCardObject, + Address, Size)) + { + retr = EXTMEM_ERROR_DRIVER; + } + break; + } +#endif /* EXTMEM_DRIVER_SDCARD == 1 */ + case EXTMEM_PSRAM : { + retr = EXTMEM_ERROR_NOTSUPPORTED; + break; + } +#if EXTMEM_DRIVER_USER == 1 + case EXTMEM_USER :{ + /* Initialize the SFDP memory */ + EXTMEM_DRIVER_USER_StatusTypeDef status = EXTMEM_DRIVER_USER_EraseSector(&extmem_list_config[MemId].UserObject, + Address, Size); + switch(status){ + case EXTMEM_DRIVER_USER_NOTSUPPORTED: + retr = EXTMEM_ERROR_NOTSUPPORTED; + break; + case EXTMEM_DRIVER_USER_OK: + break; + default: + retr = EXTMEM_ERROR_DRIVER; + break; + } + break; + } +#endif /* EXTMEM_DRIVER_USER == 1 */ + default:{ + EXTMEM_DEBUG("\terror unknown type\n"); + retr = EXTMEM_ERROR_UNKNOWNMEMORY; + break; + } + } + } + return retr; +} + +EXTMEM_StatusTypeDef EXTMEM_EraseAll(uint32_t MemId) +{ + EXTMEM_StatusTypeDef retr = EXTMEM_ERROR_INVALID_ID; + EXTMEM_FUNC_CALL() + + /* control the memory ID */ + if (MemId < (sizeof(extmem_list_config) / sizeof(EXTMEM_DefinitionTypeDef))) + { + retr = EXTMEM_OK; + switch (extmem_list_config[MemId].MemType) + { +#if EXTMEM_DRIVER_NOR_SFDP == 1 + case EXTMEM_NOR_SFDP:{ + if (EXTMEM_DRIVER_NOR_SFDP_OK != EXTMEM_DRIVER_NOR_SFDP_MassErase(&extmem_list_config[MemId].NorSfdpObject)) + { + retr = EXTMEM_ERROR_DRIVER; + } + break; + } +#endif /* EXTMEM_DRIVER_NOR_SFDP == 1 */ +#if EXTMEM_DRIVER_SDCARD == 1 + case EXTMEM_SDCARD:{ + if (EXTMEM_DRIVER_SDCARD_OK != EXTMEM_DRIVER_SDCARD_Erase(&extmem_list_config[MemId].SdCardObject)) + { + retr = EXTMEM_ERROR_DRIVER; + } + break; + } +#endif /* EXTMEM_DRIVER_SDCARD == 1 */ + case EXTMEM_PSRAM:{ + retr = EXTMEM_ERROR_NOTSUPPORTED; + break; + } +#if EXTMEM_DRIVER_USER == 1 + case EXTMEM_USER :{ + EXTMEM_DRIVER_USER_StatusTypeDef status = EXTMEM_DRIVER_USER_MassErase(&extmem_list_config[MemId].UserObject); + switch(status){ + case EXTMEM_DRIVER_USER_NOTSUPPORTED: + retr = EXTMEM_ERROR_NOTSUPPORTED; + break; + case EXTMEM_DRIVER_USER_OK: + break; + default: + retr = EXTMEM_ERROR_DRIVER; + break; + } + break; + } +#endif /* EXTMEM_DRIVER_USER == 1 */ + default:{ + EXTMEM_DEBUG("\terror unknown type\n"); + retr = EXTMEM_ERROR_UNKNOWNMEMORY; + break; + } + } + } + return retr; +} + +EXTMEM_StatusTypeDef EXTMEM_GetInfo(uint32_t MemId, void *Info) +{ + EXTMEM_StatusTypeDef retr = EXTMEM_ERROR_INVALID_ID; + EXTMEM_FUNC_CALL() + /* control the memory ID */ + if (MemId < (sizeof(extmem_list_config) / sizeof(EXTMEM_DefinitionTypeDef))) + { + retr = EXTMEM_OK; + switch (extmem_list_config[MemId].MemType) + { +#if EXTMEM_DRIVER_NOR_SFDP == 1 + case EXTMEM_NOR_SFDP:{ + EXTMEM_DRIVER_NOR_SFDP_GetFlashInfo(&extmem_list_config[MemId].NorSfdpObject, (EXTMEM_NOR_SFDP_FlashInfoTypeDef *)Info); + break; + } +#endif /* EXTMEM_DRIVER_NOR_SFDP == 1 */ +#if EXTMEM_DRIVER_SDCARD == 1 + case EXTMEM_SDCARD : { + if(EXTMEM_DRIVER_SDCARD_OK != EXTMEM_DRIVER_SDCARD_GetInfo(&extmem_list_config[MemId].SdCardObject, (EXTMEM_DRIVER_SDCARD_InfoTypeDef *)Info)) + { + retr = EXTMEM_ERROR_DRIVER; + } + break; + } +#endif /* EXTMEM_DRIVER_PSRAM == 1 */ +#if EXTMEM_DRIVER_USER == 1 + case EXTMEM_USER : { + if( EXTMEM_DRIVER_USER_OK != EXTMEM_DRIVER_USER_GetInfo(&extmem_list_config[MemId].UserObject, (EXTMEM_USER_MemInfoTypeDef *)Info)) + { + retr = EXTMEM_ERROR_DRIVER; + } + break; + } +#endif /* EXTMEM_DRIVER_USER == 1 */ + case EXTMEM_PSRAM : + retr = EXTMEM_ERROR_NOTSUPPORTED; + break; + default:{ + EXTMEM_DEBUG("\terror unknown type\n"); + retr = EXTMEM_ERROR_UNKNOWNMEMORY; + break; + } + } + } + return retr; +} + +EXTMEM_StatusTypeDef EXTMEM_MemoryMappedMode(uint32_t MemId, EXTMEM_StateTypeDef State) +{ + EXTMEM_StatusTypeDef retr = EXTMEM_ERROR_INVALID_ID; + EXTMEM_FUNC_CALL(); + /* control the memory ID */ + if (MemId < (sizeof(extmem_list_config) / sizeof(EXTMEM_DefinitionTypeDef))) + { + retr = EXTMEM_OK; + switch (extmem_list_config[MemId].MemType) + { +#if EXTMEM_DRIVER_NOR_SFDP == 1 + case EXTMEM_NOR_SFDP:{ + if (EXTMEM_ENABLE == State) + { + /* start the memory mapped mode */ + if (EXTMEM_DRIVER_NOR_SFDP_OK != + EXTMEM_DRIVER_NOR_SFDP_Enable_MemoryMappedMode(&extmem_list_config[MemId].NorSfdpObject)) + { + return EXTMEM_ERROR_DRIVER; + } + } + else + { + /* stop the memory mapped mode */ + if (EXTMEM_DRIVER_NOR_SFDP_OK != + EXTMEM_DRIVER_NOR_SFDP_Disable_MemoryMappedMode(&extmem_list_config[MemId].NorSfdpObject)) + { + return EXTMEM_ERROR_DRIVER; + } + } + break; + } +#endif /* EXTMEM_DRIVER_NOR_SFDP == 1 */ +#if EXTMEM_DRIVER_PSRAM == 1 + case EXTMEM_PSRAM : { + if (EXTMEM_ENABLE == State) + { + /* start the memory mapped mode */ + if (EXTMEM_DRIVER_PSRAM_OK != + EXTMEM_DRIVER_PSRAM_Enable_MemoryMappedMode(&extmem_list_config[MemId].PsramObject)) + { + return EXTMEM_ERROR_DRIVER; + } + } + else + { + /* stop the memory mapped mode */ + if (EXTMEM_DRIVER_PSRAM_OK != + EXTMEM_DRIVER_PSRAM_Disable_MemoryMappedMode(&extmem_list_config[MemId].PsramObject)) + { + return EXTMEM_ERROR_DRIVER; + } + } + break; + } +#endif /* EXTMEM_DRIVER_PSRAM == 1 */ +#if EXTMEM_DRIVER_USER == 1 + case EXTMEM_USER :{ + /* Initialize the SFDP memory */ + EXTMEM_DRIVER_USER_StatusTypeDef status; + if (EXTMEM_ENABLE == State) + { + status = EXTMEM_DRIVER_USER_Enable_MemoryMappedMode(&extmem_list_config[MemId].UserObject); + } + else + { + status = EXTMEM_DRIVER_USER_Disable_MemoryMappedMode(&extmem_list_config[MemId].UserObject); + } + switch(status){ + case EXTMEM_DRIVER_USER_NOTSUPPORTED: + retr = EXTMEM_ERROR_NOTSUPPORTED; + break; + case EXTMEM_DRIVER_USER_OK: + break; + default: + retr = EXTMEM_ERROR_DRIVER; + break; + } + break; + } +#endif /* EXTMEM_DRIVER_USER == 1 */ + case EXTMEM_SDCARD : + retr = EXTMEM_ERROR_NOTSUPPORTED; + break; + default:{ + EXTMEM_DEBUG("\terror unknown type\n"); + retr = EXTMEM_ERROR_UNKNOWNMEMORY; + break; + } + } + } + return retr; +} + +EXTMEM_StatusTypeDef EXTMEM_GetMapAddress(uint32_t MemId, uint32_t *BaseAddress) +{ + EXTMEM_StatusTypeDef retr = EXTMEM_ERROR_INVALID_ID; + EXTMEM_FUNC_CALL(); + /* control the memory ID */ + if (MemId < (sizeof(extmem_list_config) / sizeof(EXTMEM_DefinitionTypeDef))) + { + retr = EXTMEM_OK; + switch (extmem_list_config[MemId].MemType) + { +#if EXTMEM_DRIVER_NOR_SFDP == 1 || EXTMEM_DRIVER_PSRAM == 1 + case EXTMEM_PSRAM: + case EXTMEM_NOR_SFDP:{ +#if defined(XSPI1) + if (((XSPI_HandleTypeDef *)extmem_list_config[MemId].Handle)->Instance == XSPI1) + { + *BaseAddress = XSPI1_BASE; + } +#if defined(XSPI2) + else if (((XSPI_HandleTypeDef *)extmem_list_config[MemId].Handle)->Instance == XSPI2) + { + *BaseAddress = XSPI2_BASE; + } +#if defined(XSPI3) + else if (((XSPI_HandleTypeDef *)extmem_list_config[MemId].Handle)->Instance == XSPI3) + { + *BaseAddress = XSPI3_BASE; + } +#endif /* XSPI3 */ +#endif /* XSPI2 */ +#else /* XSPI1 */ + if (((XSPI_HandleTypeDef *)extmem_list_config[MemId].Handle)->Instance == OCTOSPI1) + { + *BaseAddress = OCTOSPI1_BASE; + } +#endif /* XSPI1 */ + else + { + retr = EXTMEM_ERROR_DRIVER; + } + + break; + } +#endif /* EXTMEM_DRIVER_NOR_SFDP == 1 || EXTMEM_DRIVER_PSRAM == 1 */ +#if EXTMEM_DRIVER_SDCARD == 1 + case EXTMEM_SDCARD : { + retr = EXTMEM_ERROR_NOTSUPPORTED; + break; + } +#endif /* EXTMEM_DRIVER_PSRAM == 1 */ +#if EXTMEM_DRIVER_USER == 1 + case EXTMEM_USER:{ + switch(EXTMEM_DRIVER_USER_GetMapAddress(&extmem_list_config[MemId].UserObject, BaseAddress)) + { + case EXTMEM_DRIVER_USER_OK: + break; + case EXTMEM_DRIVER_USER_NOTSUPPORTED: + retr = EXTMEM_ERROR_NOTSUPPORTED; + break; + default : + retr = EXTMEM_ERROR_DRIVER; + break; + } + break; + } +#endif /* EXTMEM_DRIVER_USER == 1 */ + default : + { + retr = EXTMEM_ERROR_UNKNOWNMEMORY; + break; + } + } + } + return retr; +} +/** + * @} + */ + +/** + * @} + */ diff --git a/Middlewares/ST/STM32_ExtMem_Manager/stm32_extmem.h b/Middlewares/ST/STM32_ExtMem_Manager/stm32_extmem.h new file mode 100644 index 0000000..ec3aa99 --- /dev/null +++ b/Middlewares/ST/STM32_ExtMem_Manager/stm32_extmem.h @@ -0,0 +1,250 @@ +/** + ****************************************************************************** + * @file stm32_extmem.h + * @author MCD Application Team + * @brief This file contains the external memory functions prototypes. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_EXTMEM_H_ +#define __STM32_EXTMEM_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup EXTMEM + * @{ + */ + +/* Includes ------------------------------------------------------------------*/ +#include + +/* Exported constants --------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup EXTMEM_Exported_Types External Memory Exported Types + * @{ + */ + +/** + * @brief Middleware version number + */ +#define EXTMEM_VERSION 0x00010400 /* version v1.4.0 */ + +/** + * @brief Types of supported memories + */ +typedef enum +{ + EXTMEM_NOR_SFDP, + EXTMEM_NOR_CFI, + EXTMEM_PSRAM, + EXTMEM_SDCARD, + EXTMEM_USER +} EXTMEM_TypeTypeDef; + +/** + * @brief EXTMEM module function call return values + */ +typedef enum +{ + EXTMEM_OK, /*!< action performed with a status ok */ + EXTMEM_ERROR_NOTSUPPORTED = -1, /*!< action not supported by the memory type */ + EXTMEM_ERROR_UNKNOWNMEMORY= -2, /*!< unknown memory type */ + EXTMEM_ERROR_DRIVER = -3, /*!< error return by the driver layer */ + EXTMEM_ERROR_SECTOR_SIZE = -4, /*!< inconsistency between the size an the sector size of the memory */ + EXTMEM_ERROR_INVALID_ID = -5, /*!< the memory ID is invalid */ + EXTMEM_ERROR_PARAM = -6, /*!< parameter value error */ +} EXTMEM_StatusTypeDef; + +/** + * @brief Enable/disable state of the module + */ +typedef enum +{ + EXTMEM_ENABLE, /*!< state enable */ + EXTMEM_DISABLE /*!< state disable */ +} EXTMEM_StateTypeDef; + +/** + * @brief NOR SFDP memory information structure + */ +typedef struct { + uint8_t FlashSize; /*!< Flash size in power of 2 */ + uint32_t PageSize; /*!< Page size */ + uint32_t EraseType1Size; /*!< erase 1 size */ + uint32_t EraseType2Size; /*!< erase 2 size */ + uint32_t EraseType3Size; /*!< erase 3 size */ + uint32_t EraseType4Size; /*!< erase 4 size */ +} EXTMEM_NOR_SFDP_FlashInfoTypeDef; + + +/** + * @brief USER memory information structure + */ +typedef struct { + uint8_t MemSize; /*!< mem size in power of 2 */ + uint32_t MpuCache; /*!< */ +} EXTMEM_USER_MemInfoTypeDef; + +/** + * @brief SD card information structure + */ + typedef struct { + uint32_t CardType; /*!< Specifies the card type */ + uint32_t CardVersion; /*!< Specifies the card version */ + uint32_t Class; /*!< Specifies the class of the card */ + uint32_t RelCardAdd; /*!< Specifies the celative card Address */ + uint32_t BlockNbr; /*!< Specifies the card capacity in blocks */ + uint32_t BlockSize; /*!< Specifies one block size in bytes */ + uint32_t LogBlockNbr; /*!< Specifies the card logical capacity in blocks */ + uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */ + uint32_t CardSpeed; /*!< Specifies the card speed */ +} EXTMEM_DRIVER_SDCARD_InfoTypeDef; + +/** + * @brief Number of physical I/O line(s) connected with the memory + */ +typedef enum { + EXTMEM_LINK_CONFIG_1LINE, /*!< Configuration using 1 line */ + EXTMEM_LINK_CONFIG_2LINES, /*!< Configuration using 2 lines */ + EXTMEM_LINK_CONFIG_4LINES, /*!< Configuration using 4 lines */ + EXTMEM_LINK_CONFIG_8LINES, /*!< Configuration using 8 lines */ + EXTMEM_LINK_CONFIG_16LINES, /*!< Configuration using 16 lines */ +} EXTMEM_LinkConfig_TypeDef; + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup EXTMEM_Exported_Functions External Memory Exported Functions + * @{ + */ + +/** + * @brief This function initializes a memory + * + * @param MemId memory id + * @param ClockInput clock in input of the memory + * @return @ref EXTMEM_StatusTypeDef + **/ +EXTMEM_StatusTypeDef EXTMEM_Init(uint32_t MemId, uint32_t ClockInput); + +/** + * @brief This function un-initializes a memory + * + * @param MemId memory id + * @return @ref EXTMEM_StatusTypeDef + **/ +EXTMEM_StatusTypeDef EXTMEM_DeInit(uint32_t MemId); + +/** + * @brief This function reads a buffer from the memory + * + * @param MemId memory id + * @param Address location of the data memory + * @param Data data pointer + * @param Size data size in bytes + * @return @ref EXTMEM_StatusTypeDef + **/ +EXTMEM_StatusTypeDef EXTMEM_Read(uint32_t MemId, uint32_t Address, uint8_t* Data, uint32_t Size); + +/** + * @brief This function writes data to the memory + * + * @param MemId memory id + * @param Address location of the data memory + * @param Data data pointer + * @param Size data size in bytes + * @return @ref EXTMEM_StatusTypeDef + **/ +EXTMEM_StatusTypeDef EXTMEM_Write(uint32_t MemId, uint32_t Address, const uint8_t* Data, uint32_t Size); + +/** + * @brief This function writes data in memory mapped mode + * + * @param MemId memory id + * @param Address location of the data memory + * @param Data data pointer aligned 32 bits (this assumption is really important for the writing process) + * @param Size data size in bytes + * @return @ref EXTMEM_StatusTypeDef + * + * @note this function perform write in mapped mode need to perform a specific processing due to the management of + * the write enable which can be manage when the memory is mapped. The operation consists to cut the write + * in packet of page size and for each packet perform a write before enter mapped mode. + * + * @note to avoid any issue on the execution of this processing, its mandatory to have targeted memory area + * this the following characteristic: the write region must be not bufferable, not shareable and not cacheable. + **/ +EXTMEM_StatusTypeDef EXTMEM_WriteInMappedMode(uint32_t MemId, uint32_t Address, const uint8_t* const Data, uint32_t Size); + +/** + * @brief This function erases a number of sector + * + * @param MemId memory id + * @param Address location of the data memory + * @param Size data size in bytes + * @return @ref EXTMEM_StatusTypeDef + **/ +EXTMEM_StatusTypeDef EXTMEM_EraseSector(uint32_t MemId, uint32_t Address, uint32_t Size); + +/** + * @brief This function erases all the memory + * + * @param MemId memory id + * @return @ref EXTMEM_StatusTypeDef + **/ +EXTMEM_StatusTypeDef EXTMEM_EraseAll(uint32_t MemId); + +/** + * @brief This function returns information about the memory + * + * @param MemId memory id + * @param Info structure information of the memory + * @return @ref EXTMEM_StatusTypeDef + **/ +EXTMEM_StatusTypeDef EXTMEM_GetInfo(uint32_t MemId, void *Info); + +/** + * @brief This function enables/disables the memory mapped mode + * + * @param MemId memory id + * @param State @ref EXTMEM_StateTypeDef + * @return @ref EXTMEM_StatusTypeDef + **/ +EXTMEM_StatusTypeDef EXTMEM_MemoryMappedMode(uint32_t MemId, EXTMEM_StateTypeDef State); + +/** + * @brief This function gets the memory mapped address + * + * @param MemId memory id + * @param BaseAddress memory map address + * @return @ref EXTMEM_StatusTypeDef + **/ +EXTMEM_StatusTypeDef EXTMEM_GetMapAddress(uint32_t MemId, uint32_t *BaseAddress); + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32_EXTMEM_H_ */ diff --git a/Middlewares/ST/STM32_ExtMem_Manager/stm32_extmem_conf_template.h b/Middlewares/ST/STM32_ExtMem_Manager/stm32_extmem_conf_template.h new file mode 100644 index 0000000..7fb1d4c --- /dev/null +++ b/Middlewares/ST/STM32_ExtMem_Manager/stm32_extmem_conf_template.h @@ -0,0 +1,197 @@ +/** + ****************************************************************************** + * @file stm32_extmem_conf_template.h + * @author MCD Application Team + * @brief Header configuration for extmem module + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_EXTMEM_CONF__H__ +#define __STM32_EXTMEM_CONF__H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @defgroup EXTMEM_CONF + * @{ + */ + +/** @defgroup EXTMEM_CONF_Driver_selection External Memory configuration selection of the driver. + * This section is used to select the driver\n + * #define EXTMEM_DRIVER_NOR_SFDP 1\n + * #define EXTMEM_DRIVER_PSRAM 1\n + * #define EXTMEM_DRIVER_SDCARD 0\n + * #define EXTMEM_DRIVER_USER 0 + * @{ + */ +#define EXTMEM_DRIVER_NOR_SFDP 1 +#define EXTMEM_DRIVER_PSRAM 1 +#define EXTMEM_DRIVER_SDCARD 0 +#define EXTMEM_DRIVER_USER 0 + +/** + * @} + */ + +/** @defgroup EXTMEM_CONF_SAL_selection External Memory configuration selection of the SAL + * This section is used to select the software adaptation layer (SAL)\n + * #define EXTMEM_SAL_XSPI 1\n + * #define EXTMEM_SAL_SD 0 + * @{ + */ +#define EXTMEM_SAL_XSPI 1 +#define EXTMEM_SAL_SD 0 + +/** + * @} + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7rsxx_hal.h" +#include "stm32_extmem.h" +#include "stm32_extmem_type.h" + +/** @defgroup EXTMEM_CONF_SAL_imported_variable External Memory configuration list of the imported variables + * this section is used to import the HAL handle variable. Handle Can be one of the following: + * extern XSPI_HandleTypeDef \n + * extern SD_HandleTypeDef + * @{ + */ + +/* + @brief Import of the HAL handle used for EXTMEMORY_2 +*/ +extern XSPI_HandleTypeDef hxspi2; + +/* + @brief Import of the HAL handle used for EXTMEMORY_1 +*/ +extern XSPI_HandleTypeDef hxspi1; +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup EXTMEM_CONF_Exported_constants EXTMEM_CONF exported constants + * @{ + */ +enum { + EXTMEMORY_1 = 0, /*!< ID=0 for the first external memory */ + EXTMEMORY_2 = 1, /*!< ID=1 for the second external memory */ +}; + +/* + @brief Management of the external memory used as boot layer +*/ +#define EXTMEM_MEMORY_BOOTXIP EXTMEMORY_1 +/** + * @} + */ + +/* Exported configuration --------------------------------------------------------*/ +/** @defgroup EXTMEM_CONF_Exported_configuration EXTMEM_CONF exported configuration definition + * Memory type can be EXTMEM_SDCARD, EXTMEM_NOR_SFDP, EXTMEM_PSRAM + * @{ + */ +extern EXTMEM_DefinitionTypeDef extmem_list_config[2]; +#if defined(EXTMEM_C) +EXTMEM_DefinitionTypeDef extmem_list_config[2] = +{ + /* EXTMEMORY_1 */ + { + .MemType = EXTMEM_NOR_SFDP, + .Handle = (void*)&hxspi2, + .ConfigType = EXTMEM_LINK_CONFIG_8LINES, +#if !defined ( __GNUC__ ) + .NorSfdpObject = + { + 0u + } +#endif /* __GNUC__ */ + }, + /* EXTMEMORY_2 */ + { + .MemType = EXTMEM_PSRAM, + .Handle = (void*)&hxspi1, + .ConfigType = EXTMEM_LINK_CONFIG_16LINES, + .PsramObject = + { + .psram_public = + { + .MemorySize = HAL_XSPI_SIZE_256MB, + .FreqMax = 200 * 1000000u, + .NumberOfConfig = 1u, + /* Config */ + { + {.WriteMask = 0x40u, .WriteValue = 0x40u, .REGAddress = 0x08u}, + }, + /* Memory command configuration */ + .ReadREG = 0x40u, + .WriteREG = 0xC0u, + .ReadREGSize = 2u, + .REG_DummyCycle = 4u, + .Write_command = 0xA0u, + .Write_DummyCycle = 4u, + .Read_command = 0x20u, + .WrapRead_command = 0x00u, + .Read_DummyCycle = 4u, + } + } + } +}; +#endif /* EXTMEM_C */ + +/** + * @} + */ + +/* Exported trace --------------------------------------------------------*/ +/** @defgroup EXTMEM_CONF_Exported_debug EXTMEM_CONF exported debug definition + * @{ + */ + +/* + * @brief Import of the trace function + */ +extern void EXTMEM_TRACE(uint8_t *Message); +/* + * @brief Definition of the debug macro + */ +#define EXTMEM_MACRO_DEBUG(_MSG_) EXTMEM_TRACE((uint8_t *)_MSG_) + +/* + * @brief Debug level of the different layers + */ +#define EXTMEM_DEBUG_LEVEL 0 + +#define EXTMEM_DRIVER_NOR_SFDP_DEBUG_LEVEL 0 +#define EXTMEM_DRIVER_PSRAM_DEBUG_LEVEL 0 + +#define EXTMEM_SAL_XSPI_DEBUG_LEVEL 0 +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32_EXTMEM_CONF__H__ */ diff --git a/Middlewares/ST/STM32_ExtMem_Manager/stm32_extmem_type.h b/Middlewares/ST/STM32_ExtMem_Manager/stm32_extmem_type.h new file mode 100644 index 0000000..11bce49 --- /dev/null +++ b/Middlewares/ST/STM32_ExtMem_Manager/stm32_extmem_type.h @@ -0,0 +1,147 @@ +/** + ****************************************************************************** + * @file stm32_extmem_type.h + * @author MCD Application Team + * @brief This file contains the external memory type definition. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_EXTMEM_TYPE_H_ +#define __STM32_EXTMEM_TYPE_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup EXTMEM + * @{ + */ + +/* Includes ------------------------------------------------------------------*/ +#if EXTMEM_SAL_XSPI == 1 +#include "sal/stm32_sal_xspi_type.h" +#endif /* EXTMEM_SAL_XSPI */ + +#if EXTMEM_SAL_SD == 1 +#include "sal/stm32_sal_sd_type.h" +#endif /* EXTMEM_SAL_SD */ + +#if EXTMEM_SAL_MMC == 1 +#include "sal/stm32_sal_mmc_type.h" +#endif /* EXTMEM_SAL_MMC */ + +#if EXTMEM_DRIVER_NOR_SFDP == 1 +#include "nor_sfdp/stm32_sfdp_driver_type.h" +#endif /* DRIVER_SFDP_ENABLED */ + +#if EXTMEM_DRIVER_SDCARD == 1 +#include "sdcard/stm32_sdcard_driver_type.h" +#endif /* DRIVER_SDCARD_ENABLED */ + +#if EXTMEM_DRIVER_PSRAM == 1 +#include "psram/stm32_psram_driver_type.h" +#endif /* DRIVER_PSRAM_ENABLED */ + +#if EXTMEM_DRIVER_USER == 1 +#include "user/stm32_user_driver_type.h" +#endif /* DRIVER_USER_ENABLED */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup EXTMEM_Exported_Macros External Memory Exported Macros + * @{ + */ +/** + * @brief Macro to get the minimum value + */ +#define EXTMEM_MIN(_A_,_B_) ((_A_)>(_B_))?(_B_):(_A_); +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup EXTMEM_Exported_Constants External Memory Exported Constants + * @{ + */ + +/** @defgroup EXTMEM_Manufacturer_IDs EXTMEM JEDEC Manufacturer IDs + * @{ + */ +#define EXTMEM_MANFACTURER_MACRONIX (0xC2U) /*!< Macronix */ +#define EXTMEM_MANFACTURER_GIGADEVICE (0xC8U) /*!< GigaDevices */ +#define EXTMEM_MANFACTURER_ISSI (0x9DU) /*!< ISSI */ +/** + * @} + */ + +/** @defgroup EXTMEM_Common_JEDEC_Commands EXTMEM Common JEDEC commands identifiers + * @{ + */ +#define EXTMEM_READ_JEDEC_ID_SPI_COMMAND 0x9FU +#define EXTMEM_READ_JEDEC_ID_SIZE 0x04U + +#define EXTMEM_READ_SFDP_COMMAND 0x5AU +#define EXTMEM_READ_SFDP_NB_DUMMY_CYCLES_DEFAULT 0x08U +/** + * @} + */ + +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup EXTMEM_Exported_Typedef External Memory Exported Type definition + * @{ + */ + +/** + * @brief Definition of the memory + */ +typedef struct +{ + EXTMEM_TypeTypeDef MemType; /*!< Memory driver type */ + void *Handle; /*!< HAL handle */ + EXTMEM_LinkConfig_TypeDef ConfigType; /*!< Physical link config */ + union + { +#if EXTMEM_DRIVER_NOR_SFDP == 1 + EXTMEM_DRIVER_NOR_SFDP_ObjectTypeDef NorSfdpObject; /*!< NorSfdp object */ +#endif /* EXTMEM_DRIVER_NOR_SFDP == 1 */ +#if EXTMEM_DRIVER_SDCARD == 1 + EXTMEM_DRIVER_SDCARD_ObjectTypeDef SdCardObject; /*!< SdCard object */ +#endif /* EXTMEM_DRIVER_SDCARD == 1 */ +#if EXTMEM_DRIVER_PSRAM == 1 + EXTMEM_DRIVER_PSRAM_ObjectTypeDef PsramObject; /*!< Psram object */ +#endif /* EXTMEM_DRIVER_PSRAM == 1 */ +#if EXTMEM_DRIVER_USER == 1 + EXTMEM_DRIVER_USER_ObjectTypeDef UserObject; /*!< User object */ +#endif /* EXTMEM_DRIVER_USER == 1 */ + }; +} EXTMEM_DefinitionTypeDef; + +/** + * @} + */ + + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32_EXTMEM_TYPE_H_ */ diff --git a/Middlewares/ST/STM32_ExtMem_Manager/user/stm32_user_driver.c b/Middlewares/ST/STM32_ExtMem_Manager/user/stm32_user_driver.c new file mode 100644 index 0000000..93c2170 --- /dev/null +++ b/Middlewares/ST/STM32_ExtMem_Manager/user/stm32_user_driver.c @@ -0,0 +1,147 @@ +/** + ****************************************************************************** + * @file stm32_user_driver.c + * @author MCD Application Team + * @brief This file includes a driver for user support + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32_extmem.h" +#include "stm32_extmem_conf.h" +#if EXTMEM_DRIVER_USER == 1 +#include "stm32_user_driver_api.h" +#include "stm32_user_driver_type.h" + +/** @defgroup USER USER driver + * @ingroup EXTMEM_DRIVER + * @{ + */ + +/* Private Macro ------------------------------------------------------------*/ +/** @defgroup USER_Private_Macro Private Macro + * @{ + */ + +/** + * @} + */ +/* Private typedefs ---------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup USER_Exported_Functions Exported Functions + * @{ + */ + +__weak EXTMEM_DRIVER_USER_StatusTypeDef EXTMEM_DRIVER_USER_Init(uint32_t MemoryId, + EXTMEM_DRIVER_USER_ObjectTypeDef* UserObject) +{ + EXTMEM_DRIVER_USER_StatusTypeDef retr = EXTMEM_DRIVER_USER_NOTSUPPORTED; + UserObject->MemID = MemoryId; /* Keep the memory id, could be used to control more than one user memory */ + UserObject->PtrUserDriver = NULL; /* could be used to link data with the memory id */ + return retr; +} + +__weak EXTMEM_DRIVER_USER_StatusTypeDef EXTMEM_DRIVER_USER_DeInit(EXTMEM_DRIVER_USER_ObjectTypeDef* UserObject) +{ + EXTMEM_DRIVER_USER_StatusTypeDef retr = EXTMEM_DRIVER_USER_NOTSUPPORTED; + (void)UserObject; + return retr; +} + +__weak EXTMEM_DRIVER_USER_StatusTypeDef EXTMEM_DRIVER_USER_Read(EXTMEM_DRIVER_USER_ObjectTypeDef* UserObject, + uint32_t Address, uint8_t* Data, uint32_t Size) +{ + EXTMEM_DRIVER_USER_StatusTypeDef retr = EXTMEM_DRIVER_USER_NOTSUPPORTED; + (void)*UserObject; + (void)Address; + (void)Data; + (void)Size; + return retr; +} + +__weak EXTMEM_DRIVER_USER_StatusTypeDef EXTMEM_DRIVER_USER_Write(EXTMEM_DRIVER_USER_ObjectTypeDef* UserObject, + uint32_t Address, const uint8_t* Data, uint32_t Size) +{ + EXTMEM_DRIVER_USER_StatusTypeDef retr = EXTMEM_DRIVER_USER_NOTSUPPORTED; + (void)*UserObject; + (void)Address; + (void)Data; + (void)Size; + return retr; +} + +__weak EXTMEM_DRIVER_USER_StatusTypeDef EXTMEM_DRIVER_USER_EraseSector(EXTMEM_DRIVER_USER_ObjectTypeDef* UserObject, + uint32_t Address, uint32_t Size) +{ + EXTMEM_DRIVER_USER_StatusTypeDef retr = EXTMEM_DRIVER_USER_NOTSUPPORTED; + (void)*UserObject; + (void)Address; + (void)Size; + return retr; +} + +__weak EXTMEM_DRIVER_USER_StatusTypeDef EXTMEM_DRIVER_USER_MassErase(EXTMEM_DRIVER_USER_ObjectTypeDef* UserObject) +{ + EXTMEM_DRIVER_USER_StatusTypeDef retr = EXTMEM_DRIVER_USER_NOTSUPPORTED; + (void)*UserObject; + return retr; +} + +__weak EXTMEM_DRIVER_USER_StatusTypeDef EXTMEM_DRIVER_USER_Enable_MemoryMappedMode(EXTMEM_DRIVER_USER_ObjectTypeDef* UserObject) +{ + EXTMEM_DRIVER_USER_StatusTypeDef retr = EXTMEM_DRIVER_USER_NOTSUPPORTED; + (void)*UserObject; + return retr; +} + +__weak EXTMEM_DRIVER_USER_StatusTypeDef EXTMEM_DRIVER_USER_Disable_MemoryMappedMode(EXTMEM_DRIVER_USER_ObjectTypeDef* UserObject) +{ + EXTMEM_DRIVER_USER_StatusTypeDef retr = EXTMEM_DRIVER_USER_NOTSUPPORTED; + (void)*UserObject; + return retr; +} + +__weak EXTMEM_DRIVER_USER_StatusTypeDef EXTMEM_DRIVER_USER_GetMapAddress(EXTMEM_DRIVER_USER_ObjectTypeDef* UserObject, uint32_t* BaseAddress) +{ + EXTMEM_DRIVER_USER_StatusTypeDef retr = EXTMEM_DRIVER_USER_NOTSUPPORTED; + (void)*UserObject; + (void)BaseAddress; + return retr; +} + +__weak EXTMEM_DRIVER_USER_StatusTypeDef EXTMEM_DRIVER_USER_GetInfo(EXTMEM_DRIVER_USER_ObjectTypeDef* UserObject, EXTMEM_USER_MemInfoTypeDef* MemInfo) +{ + EXTMEM_DRIVER_USER_StatusTypeDef retr = EXTMEM_DRIVER_USER_NOTSUPPORTED; + (void)*UserObject; + (void)MemInfo; + return retr; +} + +/** + * @} + */ + +/** @addtogroup USER_Private_Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* EXTMEM_DRIVER_USER == 1 */ diff --git a/Middlewares/ST/STM32_ExtMem_Manager/user/stm32_user_driver_api.h b/Middlewares/ST/STM32_ExtMem_Manager/user/stm32_user_driver_api.h new file mode 100644 index 0000000..b6e94fc --- /dev/null +++ b/Middlewares/ST/STM32_ExtMem_Manager/user/stm32_user_driver_api.h @@ -0,0 +1,177 @@ +/** + ****************************************************************************** + * @file stm32_user_driver_api.h + * @author MCD Application Team + * @brief This file contains the user driver API definition. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_USER_DRIVER_API_H +#define __STM32_USER_DRIVER_API_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#if EXTMEM_DRIVER_USER == 1 + +/** @addtogroup USER + * @ingroup EXTMEM_DRIVER + * @{ + */ +/* Exported constants --------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup USER_Exported_Types Exported Types + * @{ + */ + +/** + * @brief list of error code of the USER driver + */ +typedef enum { + EXTMEM_DRIVER_USER_OK = 0, + EXTMEM_DRIVER_USER_ERROR_1 = -1, + EXTMEM_DRIVER_USER_ERROR_2 = -2, + EXTMEM_DRIVER_USER_ERROR_3 = -3, + EXTMEM_DRIVER_USER_ERROR_4 = -4, + EXTMEM_DRIVER_USER_ERROR_5 = -5, + EXTMEM_DRIVER_USER_ERROR_6 = -6, + EXTMEM_DRIVER_USER_ERROR_7 = -7, + EXTMEM_DRIVER_USER_ERROR_8 = -8, + EXTMEM_DRIVER_USER_ERROR_9 = -9, + EXTMEM_DRIVER_USER_ERROR_10 = -10, + + EXTMEM_DRIVER_USER_NOTSUPPORTED =-128 +} EXTMEM_DRIVER_USER_StatusTypeDef; + +/* Exported functions --------------------------------------------------------*/ +/** + * @addtogroup USER_Exported_Functions Exported functions + * @{ + */ +/** + * @brief This function initializes the driver USER + * + * @param MemoryID id of the memory + * @param UsersObject object USER + * @return @ref EXTMEM_DRIVER_USER_StatusTypeDef + **/ +EXTMEM_DRIVER_USER_StatusTypeDef EXTMEM_DRIVER_USER_Init(uint32_t MemoryId, + EXTMEM_DRIVER_USER_ObjectTypeDef* UserObject); + +/** + * @brief This function un-initializes the driver USER + * + * @param UserObject object user + * @return @ref EXTMEM_DRIVER_USER_StatusTypeDef + **/ +EXTMEM_DRIVER_USER_StatusTypeDef EXTMEM_DRIVER_USER_DeInit(EXTMEM_DRIVER_USER_ObjectTypeDef* UserObject); + +/** + * @brief This function reads a buffer from the memory + * + * @param UserObject memory instance + * @param Address location of the data memory + * @param Data data pointer + * @param Size data size in bytes + * @return @ref EXTMEM_DRIVER_USER_StatusTypeDef + **/ +EXTMEM_DRIVER_USER_StatusTypeDef EXTMEM_DRIVER_USER_Read(EXTMEM_DRIVER_USER_ObjectTypeDef* UserObject, + uint32_t Address, uint8_t* Data, uint32_t Size); + +/** + * @brief This function writes data from the memory into buffer + * + * @param UserObject memory instance + * @param Address location of the data memory + * @param Data data pointer + * @param Size data size in bytes + * @return @ref EXTMEM_DRIVER_USER_StatusTypeDef + **/ +EXTMEM_DRIVER_USER_StatusTypeDef EXTMEM_DRIVER_USER_Write(EXTMEM_DRIVER_USER_ObjectTypeDef* UserObject, + uint32_t Address, const uint8_t* Data, uint32_t Size); + +/** + * @brief This function erases a number of sectors + * + * @param UserObject memory instance + * @param Address location of the data memory + * @param Size data size in bytes + * @return @ref EXTMEM_DRIVER_USER_StatusTypeDef + **/ +EXTMEM_DRIVER_USER_StatusTypeDef EXTMEM_DRIVER_USER_EraseSector(EXTMEM_DRIVER_USER_ObjectTypeDef* UserObject, + uint32_t Address, uint32_t Size); + +/** + * @brief This function erases all the memory + * + * @param UserObject memory instance + * @return @ref EXTMEM_DRIVER_USER_StatusTypeDef + **/ +EXTMEM_DRIVER_USER_StatusTypeDef EXTMEM_DRIVER_USER_MassErase(EXTMEM_DRIVER_USER_ObjectTypeDef* UserObject); + +/** + * @brief This function enables the memory mapped mode + * + * @param UserObject memory instance + * @return @ref EXTMEM_DRIVER_USER_StatusTypeDef + **/ +EXTMEM_DRIVER_USER_StatusTypeDef EXTMEM_DRIVER_USER_Enable_MemoryMappedMode(EXTMEM_DRIVER_USER_ObjectTypeDef* UserObject); + +/** + * @brief This function disables the memory mapped mode + * + * @param UserObject memory instance + * @return @ref EXTMEM_DRIVER_USER_StatusTypeDef + **/ +EXTMEM_DRIVER_USER_StatusTypeDef EXTMEM_DRIVER_USER_Disable_MemoryMappedMode(EXTMEM_DRIVER_USER_ObjectTypeDef* UserObject); + +/** + * @brief This function gets the mapped address + * + * @param UserObject memory instance + * @param BaseAddress memory map address + * @return @ref EXTMEM_DRIVER_USER_StatusTypeDef + **/ +EXTMEM_DRIVER_USER_StatusTypeDef EXTMEM_DRIVER_USER_GetMapAddress(EXTMEM_DRIVER_USER_ObjectTypeDef* UserObject, uint32_t* BaseAddress); + +/** + * @brief This function gets the memory information + * + * @param UserObject memory instance + * @param MemInfo memory information + * @return @ref EXTMEM_DRIVER_USER_StatusTypeDef + **/ +EXTMEM_DRIVER_USER_StatusTypeDef EXTMEM_DRIVER_USER_GetInfo(EXTMEM_DRIVER_USER_ObjectTypeDef* UserObject, EXTMEM_USER_MemInfoTypeDef* MemInfo); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* EXTMEM_DRIVER_USER == 1 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32_USER_DRIVER_API_H */ diff --git a/Middlewares/ST/STM32_ExtMem_Manager/user/stm32_user_driver_type.h b/Middlewares/ST/STM32_ExtMem_Manager/user/stm32_user_driver_type.h new file mode 100644 index 0000000..d70668f --- /dev/null +++ b/Middlewares/ST/STM32_ExtMem_Manager/user/stm32_user_driver_type.h @@ -0,0 +1,71 @@ +/** + ****************************************************************************** + * @file stm32_user_driver_type.h + * @author MCD Application Team + * @brief This file contains the user driver type definition. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_USER_DRIVER_TYPE_H +#define __STM32_USER_DRIVER_TYPE_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/** @addtogroup USER + * @ingroup EXTMEM_DRIVER + * @{ + */ + +#if EXTMEM_DRIVER_USER == 1 + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup USER_Exported_constants Exported constants + * @{ + */ + + +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup USER_Exported_Types Exported Types + * @{ + */ + +/** + * @brief driver USER object definition + */ +typedef struct { + uint32_t MemID; + void* PtrUserDriver; +} EXTMEM_DRIVER_USER_ObjectTypeDef; + +/** + * @} + */ + +/** + * @} + */ +#endif /* EXTMEM_DRIVER_USER == 1 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32_USER_DRIVER_TYPE_H */