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gencpu.c
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/*
* UAE - The Un*x Amiga Emulator
*
* MC68000 emulation generator
*
* This is a fairly stupid program that generates a lot of case labels that
* can be #included in a switch statement.
* As an alternative, it can generate functions that handle specific
* MC68000 instructions, plus a prototype header file and a function pointer
* array to look up the function for an opcode.
* Error checking is bad, an illegal table68k file will cause the program to
* call abort().
* The generated code is sometimes sub-optimal, an optimizing compiler should
* take care of this.
*
* The source for the insn timings is Markt & Technik's Amiga Magazin 8/1992.
*
* Copyright 1995, 1996, 1997, 1998, 1999, 2000 Bernd Schmidt
*/
#include "sysconfig.h"
#include "sysdeps.h"
#include <ctype.h>
#include "readcpu.h"
#define BOOL_TYPE "int"
static FILE *headerfile;
static FILE *stblfile;
static int using_prefetch;
static int using_exception_3;
static int using_ce;
static int cpu_level;
static int optimized_flags;
#define GF_APDI 1
#define GF_AD8R 2
#define GF_PC8R 4
#define GF_AA 7
#define GF_NOREFILL 8
#define GF_PREFETCH 16
/* For the current opcode, the next lower level that will have different code.
* Initialized to -1 for each opcode. If it remains unchanged, indicates we
* are done with that opcode. */
static int next_cpu_level;
static int *opcode_map;
static int *opcode_next_clev;
static int *opcode_last_postfix;
static unsigned long *counts;
static void read_counts (void)
{
FILE *file;
unsigned long opcode, count, total;
char name[20];
int nr = 0;
memset (counts, 0, 65536 * sizeof *counts);
count = 0;
file = fopen ("frequent.68k", "r");
if (file) {
fscanf (file, "Total: %lu\n", &total);
while (fscanf (file, "%lx: %lu %s\n", &opcode, &count, name) == 3) {
opcode_next_clev[nr] = 4;
opcode_last_postfix[nr] = -1;
opcode_map[nr++] = opcode;
counts[opcode] = count;
}
fclose (file);
}
if (nr == nr_cpuop_funcs)
return;
for (opcode = 0; opcode < 0x10000; opcode++) {
if (table68k[opcode].handler == -1 && table68k[opcode].mnemo != i_ILLG
&& counts[opcode] == 0)
{
opcode_next_clev[nr] = 4;
opcode_last_postfix[nr] = -1;
opcode_map[nr++] = opcode;
counts[opcode] = count;
}
}
if (nr != nr_cpuop_funcs)
abort ();
}
static char endlabelstr[80];
static int endlabelno = 0;
static int need_endlabel;
static int n_braces = 0, limit_braces;
static int m68k_pc_offset = 0;
static int insn_n_cycles;
static void fpulimit (void)
{
if (limit_braces)
return;
printf ("\n#ifdef FPUEMU\n");
limit_braces = n_braces;
n_braces = 0;
}
static void cpulimit (void)
{
printf ("#ifndef CPUEMU_68000_ONLY\n");
}
static void returncycles (const char *s, int cycles)
{
if (using_ce) return;
printf ("%sreturn %d * %d;\n", s, cycles, CYCLE_UNIT / 2);
}
static void addcycles (int cycles)
{
if (!using_ce) return;
printf ("\tdo_cycles_ce (%d * %d);\n", cycles, CYCLE_UNIT / 2);
}
static void addcycles2 (const char *s, int cycles)
{
if (!using_ce) return;
printf ("%sdo_cycles_ce (%d * %d);\n", s, cycles, CYCLE_UNIT / 2);
}
static void addcycles3 (const char *s)
{
if (!using_ce) return;
printf ("%sif (cycles > 0) do_cycles_ce (cycles);\n", s);
}
static int isreg(amodes mode)
{
if (mode == Dreg || mode == Areg)
return 1;
return 0;
}
static void start_brace (void)
{
n_braces++;
printf ("{");
}
static void close_brace (void)
{
assert (n_braces > 0);
n_braces--;
printf ("}");
}
static void finish_braces (void)
{
while (n_braces > 0)
close_brace ();
}
static void pop_braces (int to)
{
while (n_braces > to)
close_brace ();
}
static int bit_size (int size)
{
switch (size) {
case sz_byte: return 8;
case sz_word: return 16;
case sz_long: return 32;
default: abort ();
}
return 0;
}
static const char *bit_mask (int size)
{
switch (size) {
case sz_byte: return "0xff";
case sz_word: return "0xffff";
case sz_long: return "0xffffffff";
default: abort ();
}
return 0;
}
static void gen_nextilong (const char *type, const char *name, int norefill)
{
int r = m68k_pc_offset;
m68k_pc_offset += 4;
if (using_ce) {
printf ("\t%s %s;\n", type, name);
/* we must do this because execution order of (something | something2) is not defined */
if (norefill) {
printf ("\t%s = get_word_ce_prefetch (regs, %d) << 16;\n", name, r + 2);
printf ("\t%s |= regs->irc;\n", name);
} else {
printf ("\t%s = get_word_ce_prefetch (regs, %d) << 16;\n", name, r + 2);
printf ("\t%s |= get_word_ce_prefetch (regs, %d);\n", name, r + 4);
}
} else {
if (using_prefetch) {
if (norefill) {
printf ("\t%s %s;\n", type, name);
printf ("\t%s = get_word_prefetch (regs, %d) << 16;\n", name, r + 2);
printf ("\t%s |= regs->irc;\n", name);
insn_n_cycles += 4;
} else {
printf ("\t%s %s = get_long_prefetch (regs, %d);\n", type, name, r + 2);
insn_n_cycles += 8;
}
} else {
insn_n_cycles += 8;
printf ("\t%s %s = get_ilong (regs, %d);\n", type, name, r);
}
}
}
static const char *gen_nextiword (int norefill)
{
static char buffer[80];
int r = m68k_pc_offset;
m68k_pc_offset += 2;
if (using_ce) {
if (norefill)
strcpy (buffer, "regs->irc");
else
sprintf (buffer, "get_word_ce_prefetch (regs, %d)", r + 2);
} else {
if (using_prefetch) {
if (norefill) {
sprintf (buffer, "regs->irc", r);
} else {
sprintf (buffer, "get_word_prefetch (regs, %d)", r + 2);
insn_n_cycles += 4;
}
} else {
sprintf (buffer, "get_iword (regs, %d)", r);
insn_n_cycles += 4;
}
}
return buffer;
}
static const char *gen_nextibyte (int norefill)
{
static char buffer[80];
int r = m68k_pc_offset;
m68k_pc_offset += 2;
if (using_ce) {
if (norefill)
strcpy (buffer, "(uae_u8)regs->irc");
else
sprintf (buffer, "(uae_u8)get_word_ce_prefetch (regs, %d)", r + 2);
} else {
insn_n_cycles += 4;
if (using_prefetch) {
if (norefill) {
sprintf (buffer, "(uae_u8)regs->irc", r);
} else {
sprintf (buffer, "(uae_u8)get_word_prefetch (regs, %d)", r + 2);
insn_n_cycles += 4;
}
} else {
sprintf (buffer, "get_ibyte (regs, %d)", r);
insn_n_cycles += 4;
}
}
return buffer;
}
static void irc2ir (void)
{
if (!using_prefetch)
return;
printf ("\tregs->ir = regs->irc;\n");
}
static int did_prefetch;
static void fill_prefetch_2 (void)
{
if (!using_prefetch)
return;
if (using_ce)
printf ("\tget_word_ce_prefetch (regs, %d);\n", m68k_pc_offset + 2);
else
printf ("\tget_word_prefetch (regs, %d);\n", m68k_pc_offset + 2);
did_prefetch = 1;
insn_n_cycles += 4;
}
static void fill_prefetch_1 (int o)
{
if (!using_prefetch)
return;
if (using_ce) {
printf ("\tget_word_ce_prefetch (regs, %d);\n", o);
} else {
printf ("\tget_word_prefetch (regs, %d);\n", o);
}
did_prefetch = 1;
insn_n_cycles += 4;
}
static void fill_prefetch_full (void)
{
fill_prefetch_1 (0);
irc2ir ();
fill_prefetch_1 (2);
}
static void fill_prefetch_0 (void)
{
if (!using_prefetch)
return;
if (using_ce)
printf ("\tget_word_ce_prefetch (regs, 0);\n");
else
printf ("\tget_word_prefetch (regs, 0);\n");
did_prefetch = 1;
insn_n_cycles += 4;
}
static void fill_prefetch_next_1 (void)
{
irc2ir ();
fill_prefetch_1 (m68k_pc_offset + 2);
}
static void fill_prefetch_next (void)
{
fill_prefetch_next_1 ();
}
#if 0
static void fill_prefetch_next_delay (int extracycles)
{
if (!using_prefetch)
return;
if (using_ce) {
if (extracycles > 0) {
printf("\t{\n");
fill_prefetch_next ();
printf("\tif (%d > 0) do_cycles(%d * %d);\n",
extracycles, CYCLE_UNIT / 2, extracycles);
printf("\t}\n");
} else {
fill_prefetch_next ();
}
} else {
fill_prefetch_next ();
}
}
#endif
static void fill_prefetch_finish (void)
{
if (did_prefetch || !using_prefetch)
return;
fill_prefetch_1 (m68k_pc_offset);
}
static void sync_m68k_pc (void)
{
if (m68k_pc_offset == 0)
return;
printf ("\tm68k_incpc (regs, %d);\n", m68k_pc_offset);
m68k_pc_offset = 0;
}
/* getv == 1: fetch data; getv != 0: check for odd address. If movem != 0,
* the calling routine handles Apdi and Aipi modes.
* gb-- movem == 2 means the same thing but for a MOVE16 instruction */
static void genamode (amodes mode, const char *reg, wordsizes size, const char *name, int getv, int movem, int flags)
{
char namea[100];
int m68k_pc_offset_last = m68k_pc_offset;
sprintf (namea, "%sa", name);
start_brace ();
switch (mode) {
case Dreg:
if (movem)
abort ();
if (getv == 1)
switch (size) {
case sz_byte:
#ifdef USE_DUBIOUS_BIGENDIAN_OPTIMIZATION
/* This causes the target compiler to generate better code on few systems */
printf ("\tuae_s8 %s = ((uae_u8*)&m68k_dreg (regs, %s))[3];\n", name, reg);
#else
printf ("\tuae_s8 %s = m68k_dreg (regs, %s);\n", name, reg);
#endif
break;
case sz_word:
#ifdef USE_DUBIOUS_BIGENDIAN_OPTIMIZATION
printf ("\tuae_s16 %s = ((uae_s16*)&m68k_dreg (regs, %s))[1];\n", name, reg);
#else
printf ("\tuae_s16 %s = m68k_dreg (regs, %s);\n", name, reg);
#endif
break;
case sz_long:
printf ("\tuae_s32 %s = m68k_dreg (regs, %s);\n", name, reg);
break;
default:
abort ();
}
return;
case Areg:
if (movem)
abort ();
if (getv == 1)
switch (size) {
case sz_word:
printf ("\tuae_s16 %s = m68k_areg (regs, %s);\n", name, reg);
break;
case sz_long:
printf ("\tuae_s32 %s = m68k_areg (regs, %s);\n", name, reg);
break;
default:
abort ();
}
return;
case Aind:
printf ("\tuaecptr %sa = m68k_areg (regs, %s);\n", name, reg);
break;
case Aipi:
printf ("\tuaecptr %sa = m68k_areg (regs, %s);\n", name, reg);
break;
case Apdi:
printf ("\tuaecptr %sa;\n", name);
switch (size) {
case sz_byte:
if (movem)
printf ("\t%sa = m68k_areg (regs, %s);\n", name, reg);
else
printf ("\t%sa = m68k_areg (regs, %s) - areg_byteinc[%s];\n", name, reg, reg);
break;
case sz_word:
printf ("\t%sa = m68k_areg (regs, %s) - %d;\n", name, reg, movem ? 0 : 2);
break;
case sz_long:
printf ("\t%sa = m68k_areg (regs, %s) - %d;\n", name, reg, movem ? 0 : 4);
break;
default:
abort ();
}
if (!(flags & GF_APDI)) {
addcycles (2);
insn_n_cycles += 2;
}
break;
case Ad16:
printf ("\tuaecptr %sa = m68k_areg (regs, %s) + (uae_s32)(uae_s16)%s;\n", name, reg, gen_nextiword (flags & GF_NOREFILL));
break;
case Ad8r:
printf ("\tuaecptr %sa;\n", name);
if (cpu_level > 1) {
if (next_cpu_level < 1)
next_cpu_level = 1;
sync_m68k_pc ();
start_brace ();
/* This would ordinarily be done in gen_nextiword, which we bypass. */
insn_n_cycles += 4;
printf ("\t%sa = get_disp_ea_020 (regs, m68k_areg (regs, %s), next_iword (regs));\n", name, reg);
} else
printf ("\t%sa = get_disp_ea_000 (regs, m68k_areg (regs, %s), %s);\n", name, reg, gen_nextiword (flags & GF_NOREFILL));
if (!(flags & GF_AD8R)) {
addcycles (2);
insn_n_cycles += 2;
}
break;
case PC16:
printf ("\tuaecptr %sa = m68k_getpc (regs) + %d;\n", name, m68k_pc_offset);
printf ("\t%sa += (uae_s32)(uae_s16)%s;\n", name, gen_nextiword (flags & GF_NOREFILL));
break;
case PC8r:
printf ("\tuaecptr tmppc;\n");
printf ("\tuaecptr %sa;\n", name);
if (cpu_level > 1) {
if (next_cpu_level < 1)
next_cpu_level = 1;
sync_m68k_pc ();
start_brace ();
/* This would ordinarily be done in gen_nextiword, which we bypass. */
insn_n_cycles += 4;
printf ("\ttmppc = m68k_getpc (regs);\n");
printf ("\t%sa = get_disp_ea_020 (regs, tmppc, next_iword (regs));\n", name);
} else {
printf ("\ttmppc = m68k_getpc (regs) + %d;\n", m68k_pc_offset);
printf ("\t%sa = get_disp_ea_000 (regs, tmppc, %s);\n", name, gen_nextiword (flags & GF_NOREFILL));
}
if (!(flags & GF_PC8R)) {
addcycles (2);
insn_n_cycles += 2;
}
break;
case absw:
printf ("\tuaecptr %sa = (uae_s32)(uae_s16)%s;\n", name, gen_nextiword (flags & GF_NOREFILL));
break;
case absl:
gen_nextilong ("uaecptr", namea, flags & GF_NOREFILL);
break;
case imm:
if (getv != 1)
abort ();
switch (size) {
case sz_byte:
printf ("\tuae_s8 %s = %s;\n", name, gen_nextibyte (flags & GF_NOREFILL));
break;
case sz_word:
printf ("\tuae_s16 %s = %s;\n", name, gen_nextiword (flags & GF_NOREFILL));
break;
case sz_long:
gen_nextilong ("uae_s32", name, flags & GF_NOREFILL);
break;
default:
abort ();
}
return;
case imm0:
if (getv != 1)
abort ();
printf ("\tuae_s8 %s = %s;\n", name, gen_nextibyte (flags & GF_NOREFILL));
return;
case imm1:
if (getv != 1)
abort ();
printf ("\tuae_s16 %s = %s;\n", name, gen_nextiword (flags & GF_NOREFILL));
return;
case imm2:
if (getv != 1)
abort ();
gen_nextilong ("uae_s32", name, flags & GF_NOREFILL);
return;
case immi:
if (getv != 1)
abort ();
printf ("\tuae_u32 %s = %s;\n", name, reg);
return;
default:
abort ();
}
/* We get here for all non-reg non-immediate addressing modes to
* actually fetch the value. */
if ((using_prefetch || using_ce) && using_exception_3 && getv != 0 && size != sz_byte) {
printf ("\tif (%sa & 1) {\n", name);
printf ("\t\texception3 (opcode, m68k_getpc (regs) + %d, %sa);\n", m68k_pc_offset_last, name);
printf ("\t\tgoto %s;\n", endlabelstr);
printf ("\t}\n");
need_endlabel = 1;
start_brace ();
}
if (flags & GF_PREFETCH)
fill_prefetch_next ();
if (getv == 1) {
start_brace ();
if (using_ce) {
switch (size) {
case sz_byte: printf ("\tuae_s8 %s = get_byte_ce (%sa);\n", name, name); break;
case sz_word: printf ("\tuae_s16 %s = get_word_ce (%sa);\n", name, name); break;
case sz_long: printf ("\tuae_s32 %s = get_word_ce (%sa) << 16; %s |= get_word_ce (%sa + 2);\n", name, name, name, name); break;
default: abort ();
}
} else {
switch (size) {
case sz_byte: insn_n_cycles += 4; printf ("\tuae_s8 %s = get_byte (%sa);\n", name, name); break;
case sz_word: insn_n_cycles += 4; printf ("\tuae_s16 %s = get_word (%sa);\n", name, name); break;
case sz_long: insn_n_cycles += 8; printf ("\tuae_s32 %s = get_long (%sa);\n", name, name); break;
default: abort ();
}
}
}
/* We now might have to fix up the register for pre-dec or post-inc
* addressing modes. */
if (!movem)
switch (mode) {
case Aipi:
switch (size) {
case sz_byte:
printf ("\tm68k_areg (regs, %s) += areg_byteinc[%s];\n", reg, reg);
break;
case sz_word:
printf ("\tm68k_areg (regs, %s) += 2;\n", reg);
break;
case sz_long:
printf ("\tm68k_areg (regs, %s) += 4;\n", reg);
break;
default:
abort ();
}
break;
case Apdi:
printf ("\tm68k_areg (regs, %s) = %sa;\n", reg, name);
break;
default:
break;
}
}
static void genastore_2 (const char *from, amodes mode, const char *reg, wordsizes size, const char *to, int store_dir)
{
switch (mode) {
case Dreg:
switch (size) {
case sz_byte:
#ifdef USE_DUBIOUS_BIGENDIAN_OPTIMIZATION
/* This causes the target compiler to generate better code on few systems */
printf ("\t((uae_u8*)&m68k_dreg (regs, %s))[3] = %s;\n", reg, from);
#else
printf ("\tm68k_dreg (regs, %s) = (m68k_dreg (regs, %s) & ~0xff) | ((%s) & 0xff);\n", reg, reg, from);
#endif
break;
case sz_word:
#ifdef USE_DUBIOUS_BIGENDIAN_OPTIMIZATION
printf ("\t((uae_s16*)&m68k_dreg (regs, %s))[1] = %s;\n", reg, from);
#else
printf ("\tm68k_dreg (regs, %s) = (m68k_dreg (regs, %s) & ~0xffff) | ((%s) & 0xffff);\n", reg, reg, from);
#endif
break;
case sz_long:
printf ("\tm68k_dreg (regs, %s) = (%s);\n", reg, from);
break;
default:
abort ();
}
break;
case Areg:
switch (size) {
case sz_word:
write_log ("Foo\n");
printf ("\tm68k_areg (regs, %s) = (uae_s32)(uae_s16)(%s);\n", reg, from);
break;
case sz_long:
printf ("\tm68k_areg (regs, %s) = (%s);\n", reg, from);
break;
default:
abort ();
}
break;
case Aind:
case Aipi:
case Apdi:
case Ad16:
case Ad8r:
case absw:
case absl:
case PC16:
case PC8r:
if (using_ce) {
switch (size) {
case sz_byte:
printf ("\tput_byte_ce (%sa,%s);\n", to, from);
break;
case sz_word:
if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
abort ();
printf ("\tput_word_ce (%sa,%s);\n", to, from);
break;
case sz_long:
if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
abort ();
if (store_dir)
printf ("\tput_word_ce (%sa + 2, %s); put_word_ce (%sa, %s >> 16);\n", to, from, to, from);
else
printf ("\tput_word_ce (%sa, %s >> 16); put_word_ce (%sa + 2, %s);\n", to, from, to, from);
break;
default:
abort ();
}
} else {
switch (size) {
case sz_byte:
insn_n_cycles += 4;
printf ("\tput_byte (%sa,%s);\n", to, from);
break;
case sz_word:
insn_n_cycles += 4;
if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
abort ();
printf ("\tput_word (%sa,%s);\n", to, from);
break;
case sz_long:
insn_n_cycles += 8;
if (cpu_level < 2 && (mode == PC16 || mode == PC8r))
abort ();
printf ("\tput_long (%sa,%s);\n", to, from);
break;
default:
abort ();
}
}
break;
case imm:
case imm0:
case imm1:
case imm2:
case immi:
abort ();
break;
default:
abort ();
}
}
static void genastore (const char *from, amodes mode, const char *reg, wordsizes size, const char *to)
{
genastore_2 (from, mode, reg, size, to, 0);
}
static void genastore_rev (const char *from, amodes mode, const char *reg, wordsizes size, const char *to)
{
genastore_2 (from, mode, reg, size, to, 1);
}
static void genmovemel (uae_u16 opcode)
{
char getcode[100];
int size = table68k[opcode].size == sz_long ? 4 : 2;
if (table68k[opcode].size == sz_long) {
strcpy (getcode, "get_long(srca)");
} else {
strcpy (getcode, "(uae_s32)(uae_s16)get_word(srca)");
}
printf ("\tuae_u16 mask = %s;\n", gen_nextiword (0));
printf ("\tunsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
genamode (table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1, 0);
start_brace ();
printf ("\twhile (dmask) { m68k_dreg (regs, movem_index1[dmask]) = %s; srca += %d; dmask = movem_next[dmask]; }\n",
getcode, size);
printf ("\twhile (amask) { m68k_areg (regs, movem_index1[amask]) = %s; srca += %d; amask = movem_next[amask]; }\n",
getcode, size);
if (table68k[opcode].dmode == Aipi)
printf ("\tm68k_areg (regs, dstreg) = srca;\n");
}
static void genmovemel_ce (uae_u16 opcode)
{
int size = table68k[opcode].size == sz_long ? 4 : 2;
printf ("\tuae_u16 mask = %s;\n", gen_nextiword (0));
printf ("\tunsigned int dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
printf ("\tuae_u32 v;\n");
genamode (table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1, GF_AA);
if (table68k[opcode].dmode == Ad8r || table68k[opcode].dmode == PC8r)
addcycles (2);
start_brace ();
if (table68k[opcode].size == sz_long) {
printf ("\twhile (dmask) { v = get_word_ce(srca) << 16; v |= get_word_ce(srca + 2); m68k_dreg (regs, movem_index1[dmask]) = v; srca += %d; dmask = movem_next[dmask]; }\n",
size);
printf ("\twhile (amask) { v = get_word_ce(srca) << 16; v |= get_word_ce(srca + 2); m68k_areg (regs, movem_index1[amask]) = v; srca += %d; amask = movem_next[amask]; }\n",
size);
} else {
printf ("\twhile (dmask) { m68k_dreg (regs, movem_index1[dmask]) = (uae_s32)(uae_s16)get_word_ce(srca); srca += %d; dmask = movem_next[dmask]; }\n",
size);
printf ("\twhile (amask) { m68k_areg (regs, movem_index1[amask]) = (uae_s32)(uae_s16)get_word_ce(srca); srca += %d; amask = movem_next[amask]; }\n",
size);
}
printf ("\tget_word_ce (srca);\n");
if (table68k[opcode].dmode == Aipi)
printf ("\tm68k_areg (regs, dstreg) = srca;\n");
}
static void genmovemle (uae_u16 opcode)
{
char putcode[100];
int size = table68k[opcode].size == sz_long ? 4 : 2;
if (table68k[opcode].size == sz_long) {
strcpy (putcode, "put_long(srca,");
} else {
strcpy (putcode, "put_word(srca,");
}
printf ("\tuae_u16 mask = %s;\n", gen_nextiword (0));
genamode (table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1, 0);
if (using_prefetch)
sync_m68k_pc ();
start_brace ();
if (table68k[opcode].dmode == Apdi) {
printf ("\tuae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;\n");
printf ("\twhile (amask) { srca -= %d; %s m68k_areg (regs, movem_index2[amask])); amask = movem_next[amask]; }\n",
size, putcode);
printf ("\twhile (dmask) { srca -= %d; %s m68k_dreg (regs, movem_index2[dmask])); dmask = movem_next[dmask]; }\n",
size, putcode);
printf ("\tm68k_areg (regs, dstreg) = srca;\n");
} else {
printf ("\tuae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
printf ("\twhile (dmask) { %s m68k_dreg (regs, movem_index1[dmask])); srca += %d; dmask = movem_next[dmask]; }\n",
putcode, size);
printf ("\twhile (amask) { %s m68k_areg (regs, movem_index1[amask])); srca += %d; amask = movem_next[amask]; }\n",
putcode, size);
}
}
static void genmovemle_ce (uae_u16 opcode)
{
int size = table68k[opcode].size == sz_long ? 4 : 2;
printf ("\tuae_u16 mask = %s;\n", gen_nextiword (0));
genamode (table68k[opcode].dmode, "dstreg", table68k[opcode].size, "src", 2, 1, GF_AA);
if (table68k[opcode].dmode == Ad8r || table68k[opcode].dmode == PC8r)
addcycles (2);
start_brace ();
if (table68k[opcode].size == sz_long) {
if (table68k[opcode].dmode == Apdi) {
printf ("\tuae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;\n");
printf ("\twhile (amask) { srca -= %d; put_word_ce (srca, m68k_areg (regs, movem_index2[amask]) >> 16); put_word_ce (srca + 2, m68k_areg (regs, movem_index2[amask])); amask = movem_next[amask]; }\n",
size);
printf ("\twhile (dmask) { srca -= %d; put_word_ce (srca, m68k_dreg (regs, movem_index2[dmask]) >> 16); put_word_ce (srca + 2, m68k_dreg (regs, movem_index2[dmask])); dmask = movem_next[dmask]; }\n",
size);
printf ("\tm68k_areg (regs, dstreg) = srca;\n");
} else {
printf ("\tuae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
printf ("\twhile (dmask) { put_word_ce (srca, m68k_dreg (regs, movem_index1[dmask]) >> 16); put_word_ce (srca + 2, m68k_dreg (regs, movem_index1[dmask])); srca += %d; dmask = movem_next[dmask]; }\n",
size);
printf ("\twhile (amask) { put_word_ce (srca, m68k_areg (regs, movem_index1[amask]) >> 16); put_word_ce (srca + 2, m68k_areg (regs, movem_index1[amask])); srca += %d; amask = movem_next[amask]; }\n",
size);
}
} else {
if (table68k[opcode].dmode == Apdi) {
printf ("\tuae_u16 amask = mask & 0xff, dmask = (mask >> 8) & 0xff;\n");
printf ("\twhile (amask) { srca -= %d; put_word_ce (srca, m68k_areg (regs, movem_index2[amask])); amask = movem_next[amask]; }\n",
size);
printf ("\twhile (dmask) { srca -= %d; put_word_ce (srca, m68k_dreg (regs, movem_index2[dmask])); dmask = movem_next[dmask]; }\n",
size);
printf ("\tm68k_areg (regs, dstreg) = srca;\n");
} else {
printf ("\tuae_u16 dmask = mask & 0xff, amask = (mask >> 8) & 0xff;\n");
printf ("\twhile (dmask) { put_word_ce (srca, m68k_dreg (regs, movem_index1[dmask])); srca += %d; dmask = movem_next[dmask]; }\n",
size);
printf ("\twhile (amask) { put_word_ce (srca, m68k_areg (regs, movem_index1[amask])); srca += %d; amask = movem_next[amask]; }\n",
size);
}
}
}
static void duplicate_carry (int n)
{
int i;
for (i = 0; i <= n; i++)
printf ("\t");
printf ("COPY_CARRY (®s->ccrflags);\n");
}
typedef enum
{
flag_logical_noclobber, flag_logical, flag_add, flag_sub, flag_cmp, flag_addx, flag_subx, flag_zn,
flag_av, flag_sv
}
flagtypes;
static void genflags_normal (flagtypes type, wordsizes size, const char *value, const char *src, const char *dst)
{
char vstr[100], sstr[100], dstr[100];
char usstr[100], udstr[100];
char unsstr[100], undstr[100];
switch (size) {
case sz_byte:
strcpy (vstr, "((uae_s8)(");
strcpy (usstr, "((uae_u8)(");
break;
case sz_word:
strcpy (vstr, "((uae_s16)(");
strcpy (usstr, "((uae_u16)(");
break;
case sz_long:
strcpy (vstr, "((uae_s32)(");
strcpy (usstr, "((uae_u32)(");
break;
default:
abort ();
}
strcpy (unsstr, usstr);
strcpy (sstr, vstr);
strcpy (dstr, vstr);
strcat (vstr, value);
strcat (vstr, "))");
strcat (dstr, dst);
strcat (dstr, "))");
strcat (sstr, src);
strcat (sstr, "))");
strcpy (udstr, usstr);
strcat (udstr, dst);
strcat (udstr, "))");
strcat (usstr, src);
strcat (usstr, "))");
strcpy (undstr, unsstr);
strcat (unsstr, "-");
strcat (undstr, "~");
strcat (undstr, dst);
strcat (undstr, "))");
strcat (unsstr, src);
strcat (unsstr, "))");
switch (type) {
case flag_logical_noclobber:
case flag_logical:
case flag_zn:
case flag_av:
case flag_sv:
case flag_addx:
case flag_subx:
break;
case flag_add:
start_brace ();
printf ("uae_u32 %s = %s + %s;\n", value, dstr, sstr);
break;
case flag_sub:
case flag_cmp:
start_brace ();
printf ("uae_u32 %s = %s - %s;\n", value, dstr, sstr);
break;
}
switch (type) {
case flag_logical_noclobber:
case flag_logical:
case flag_zn:
break;
case flag_add:
case flag_sub:
case flag_addx:
case flag_subx:
case flag_cmp:
case flag_av:
case flag_sv:
start_brace ();
printf ("\t" BOOL_TYPE " flgs = %s < 0;\n", sstr);
printf ("\t" BOOL_TYPE " flgo = %s < 0;\n", dstr);
printf ("\t" BOOL_TYPE " flgn = %s < 0;\n", vstr);
break;
}
switch (type) {
case flag_logical:
printf ("\tCLEAR_CZNV (®s->ccrflags);\n");
printf ("\tSET_ZFLG (®s->ccrflags, %s == 0);\n", vstr);
printf ("\tSET_NFLG (®s->ccrflags, %s < 0);\n", vstr);
break;
case flag_logical_noclobber:
printf ("\tSET_ZFLG (®s->ccrflags, %s == 0);\n", vstr);
printf ("\tSET_NFLG (®s->ccrflags, %s < 0);\n", vstr);
break;
case flag_av:
printf ("\tSET_VFLG (®s->ccrflags, (flgs ^ flgn) & (flgo ^ flgn));\n");
break;
case flag_sv:
printf ("\tSET_VFLG (®s->ccrflags, (flgs ^ flgo) & (flgn ^ flgo));\n");
break;
case flag_zn:
printf ("\tSET_ZFLG (®s->ccrflags, GET_ZFLG (&(regs->ccrflags)) & (%s == 0));\n", vstr);
printf ("\tSET_NFLG (®s->ccrflags, %s < 0);\n", vstr);
break;
case flag_add:
printf ("\tSET_ZFLG (®s->ccrflags, %s == 0);\n", vstr);
printf ("\tSET_VFLG (®s->ccrflags, (flgs ^ flgn) & (flgo ^ flgn));\n");
printf ("\tSET_CFLG (®s->ccrflags, %s < %s);\n", undstr, usstr);
duplicate_carry (0);
printf ("\tSET_NFLG (®s->ccrflags, flgn != 0);\n");
break;
case flag_sub:
printf ("\tSET_ZFLG (®s->ccrflags, %s == 0);\n", vstr);
printf ("\tSET_VFLG (®s->ccrflags, (flgs ^ flgo) & (flgn ^ flgo));\n");
printf ("\tSET_CFLG (®s->ccrflags, %s > %s);\n", usstr, udstr);
duplicate_carry (0);
printf ("\tSET_NFLG (®s->ccrflags, flgn != 0);\n");
break;
case flag_addx:
printf ("\tSET_VFLG (®s->ccrflags, (flgs ^ flgn) & (flgo ^ flgn));\n"); /* minterm SON: 0x42 */
printf ("\tSET_CFLG (®s->ccrflags, flgs ^ ((flgs ^ flgo) & (flgo ^ flgn)));\n"); /* minterm SON: 0xD4 */
duplicate_carry (0);
break;
case flag_subx:
printf ("\tSET_VFLG (®s->ccrflags, (flgs ^ flgo) & (flgo ^ flgn));\n"); /* minterm SON: 0x24 */
printf ("\tSET_CFLG (®s->ccrflags, flgs ^ ((flgs ^ flgn) & (flgo ^ flgn)));\n"); /* minterm SON: 0xB2 */
duplicate_carry (0);
break;
case flag_cmp: