From 5ca850f3e8522a62683d45a935dc1245be1f9fe1 Mon Sep 17 00:00:00 2001 From: Martin Swany Date: Fri, 30 Sep 2016 18:58:12 -0400 Subject: [PATCH] more galileo stuff --- include/clock.h | 12 + include/delay.h | 11 + include/platform/x86-galileo/icu.h | 9 + include/platform/x86-galileo/icu.s | 15 + include/platform/x86-galileo/multiboot.h | 59 ++++ include/platform/x86-galileo/pci.h | 80 ++++++ include/platform/x86-galileo/pxe.h | 43 +++ include/platform/x86-galileo/quark_eth.h | 146 ++++++++++ include/platform/x86-galileo/quark_irq.h | 22 ++ include/platform/x86-galileo/quark_pdat.h | 41 +++ include/platform/x86-galileo/sdmc.h | 327 ++++++++++++++++++++++ 11 files changed, 765 insertions(+) create mode 100644 include/platform/x86-galileo/icu.h create mode 100644 include/platform/x86-galileo/icu.s create mode 100644 include/platform/x86-galileo/multiboot.h create mode 100755 include/platform/x86-galileo/pci.h create mode 100644 include/platform/x86-galileo/pxe.h create mode 100644 include/platform/x86-galileo/quark_eth.h create mode 100644 include/platform/x86-galileo/quark_irq.h create mode 100644 include/platform/x86-galileo/quark_pdat.h create mode 100644 include/platform/x86-galileo/sdmc.h diff --git a/include/clock.h b/include/clock.h index 7a74d36..13df557 100644 --- a/include/clock.h +++ b/include/clock.h @@ -7,6 +7,18 @@ extern int32 slnonempty; /* nonzero if sleepq is nonempty */ extern int32 *sltop; /* ptr to key in first item on sleepq */ extern uint32 preempt; /* preemption counter */ +#ifdef X86_GALILEO +/* Intel 8254-2 clock chip constants */ + +#define CLOCKBASE 0x40 /* I/O base port of clock chip */ +#define CLOCK0 CLOCKBASE +#define CLKCNTL (CLOCKBASE+3) /* chip CSW I/O port */ + + +#define CLKTICKS_PER_SEC 1000 /* clock timer resolution */ + +#endif /* X86_GALILEO */ + #ifdef ARM_QEMU #define CLKTICKS_PER_SEC 1000 diff --git a/include/delay.h b/include/delay.h index 5ffe34f..7758df4 100644 --- a/include/delay.h +++ b/include/delay.h @@ -3,6 +3,15 @@ /* * Delay units are in microseconds. */ +#ifdef X86_GALILEO +#define DELAY(n) \ +{ \ + register int i = 0; \ + \ + while(i < (n * 100)) i++; \ +} + +#else /* !X86_GALILEO */ #define DELAY(n) \ { \ volatile long N = 2*n; \ @@ -11,6 +20,7 @@ N--; \ } \ } +#endif /* * Delay units are in milli-seconds. @@ -23,3 +33,4 @@ DELAY(1000); \ } \ } + diff --git a/include/platform/x86-galileo/icu.h b/include/platform/x86-galileo/icu.h new file mode 100644 index 0000000..2e2f5b2 --- /dev/null +++ b/include/platform/x86-galileo/icu.h @@ -0,0 +1,9 @@ +/* icu.h */ + +#define ICU1 0x20 /* I/O port address, 8259A #1 */ +#define ICU2 0xA0 /* I/O port address, 8258A #2 */ + +#define OCR ICU1 /* Operation Command Register */ +#define IMR (ICU1+1) /* Interrupt Mask Register */ + +#define EOI 0x20 /* non-specific end of interrupt */ diff --git a/include/platform/x86-galileo/icu.s b/include/platform/x86-galileo/icu.s new file mode 100644 index 0000000..96b86a6 --- /dev/null +++ b/include/platform/x86-galileo/icu.s @@ -0,0 +1,15 @@ +/* icu.s */ + +/* Interrupt controller symbolic constants for assembly language */ +/* Note: icu.h defines equivalent constants for C functions */ + + .set ICU1,0x20 /* I/O port address, 8259A #1 */ + .set ICU2,0xA0 /* I/O port address, 8258A #2 */ + + .set OCW1_2,ICU1 + .set OCW2_2,ICU2 + + .set IMR1,ICU1 + 1 /* Interrupt Mask Register for #1 */ + .set IMR2,ICU2 + 1 /* Interrupt Mask Register for #2 */ + + .set EOI,0x20 /* non-specific end of interrupt */ diff --git a/include/platform/x86-galileo/multiboot.h b/include/platform/x86-galileo/multiboot.h new file mode 100644 index 0000000..a2b7e4d --- /dev/null +++ b/include/platform/x86-galileo/multiboot.h @@ -0,0 +1,59 @@ +/* multiboot.h - definitions for the multiboot header */ + +struct mbootinfo { + uint32 flags; /* Multiboot information flags */ + uint32 mem_lower; /* Memory in KB below 1M */ + uint32 mem_upper; /* Memory in KB above 1M */ + uint32 boot_device; /* Boot device containing image */ + uint32 cmdline; /* Address of command line */ + uint32 mods_count; /* No. of modules loaded */ + uint32 mods_addr; /* Address to the module info */ + uint32 syms[4]; /* Info regarding ELF sections */ + uint32 mmap_length; /* Length(bytes) of mmap region */ + uint32 mmap_addr; /* Address of the mmap regios */ + uint32 drives_length; /* Size of drives structures */ + uint32 drives_addr; /* Address of Drive structures */ + uint32 config_table; /* Address of ROM config table */ + uint32 boot_loader_name; /* Address of boot loader name */ + uint32 apm_table; /* Address of APM table */ + uint32 vbe_control_info; /* VBE control info */ + uint32 vbe_mode_info; /* VBE mode info */ + uint16 vbe_mode; /* Current Video mode */ + uint16 vbe_interface_seg; /* VBE related information */ + uint16 vbe_interface_off; /* VBE related information */ + uint32 vbe_interface_len; /* VBE related informarion */ +}; + +struct mbmregion { + uint32 size; /* Entry Size */ + uint64 base_addr; /* Memory region base address */ + uint64 length; /* Memory region length */ + uint32 type; /* Memory region type */ +}; + +/* Multiboot header magic number */ +#define MULTIBOOT_HEADER_MAGIC 0x1BADB002 + +/* Flags for required multiboot info */ +#define MULTIBOOT_HEADER_FLAGS 0x00010003 + +/* Multiboot signature verification */ +#define MULTIBOOT_SIGNATURE 0x2BADB002 + +/* mem_upper mem_lower fields valid */ +#define MULTIBOOT_BOOFINFO_MEM 0x00000001 + +/* boot device field valid */ +#define MULTIBOOT_BOOTINFO_BOOTDEV 0x00000002 + +/* cmdline field valid */ +#define MULTIBOOT_BOOTINFO_CMDLINE 0x00000004 + +/* mods_count mods_addr valid */ +#define MULTIBOOT_BOOTINFO_MODS 0x00000008 + +/* mmap_length mmap_addr valid */ +#define MULTIBOOT_BOOTINFO_MMAP 0x00000040 + +/* Usable memory region */ +#define MULTIBOOT_MMAP_TYPE_USABLE 0x00000001 diff --git a/include/platform/x86-galileo/pci.h b/include/platform/x86-galileo/pci.h new file mode 100755 index 0000000..72b2847 --- /dev/null +++ b/include/platform/x86-galileo/pci.h @@ -0,0 +1,80 @@ +/* + * pci.h + */ + + +#define PCI_MAX_BUSES 256 +#define PCI_DEVICES_PER_BUS 32 +#define PCI_FUNCTIONS_PER_DEVICE 8 +#define PCI_BUS_MASK (PCI_MAX_BUSES - 1) +#define PCI_DEV_MASK (PCI_DEVICES_PER_BUS - 1) +#define PCI_FUNC_MASK (PCI_FUNCTIONS_PER_DEVICE - 1) +#define PCIE_BYTES_PER_FUNCTION 0x1000 +#define PCIE_BYTES_PER_DEVICE (PCIE_BYTES_PER_FUNCTION * \ + PCI_FUNCTIONS_PER_DEVICE) +#define PCIE_BYTES_PER_BUS (PCIE_BYTES_PER_DEVICE * \ + PCI_DEVICES_PER_BUS) + +#define PCI_BARS_PER_HEADER 6 /* Base addr regs per header */ + +#define PCI_HEADER_TYPE0_SIZE 0x40 /* Size of type0 header */ +#define PCI_HDR_TYPE_MULTIFUNCTION (1 << 7) /* Multifunction device */ + +#define PCI_BUS_SHIFT 16 /* Bits to shift bus value */ +#define PCI_DEV_SHIFT 3 /* Bits to shift dev value */ + +/* Definitions of PCI base address register (bar) bits:*/ +#define PCI_BAR_REGION_TYPE_IO_MASK 1 /* 0=memory space, 1=I/O */ +#define PCI_BAR_LOCATABLE_1MB_MASK 2 /* 1=Must be < 1MB */ +#define PCI_BAR_LOCATABLE_64B_MASK 4 /* 1=Any 64-bit phys addr */ +#define PCI_BAR_LOCATABLE_PREFETCH 8 /* 1=Prefetchable */ +#define PCI_BAR_BASE_ADDRESS_MASK 0xfffffff0 /* MMIO base phys addr mask */ + +#ifndef offsetof +#define offsetof(type, member) ((int)((unsigned int)&((type *)0)->member)) +#endif + +/* Define the layout of PCI config headers (type 0) */ + +struct __attribute__ ((__packed__)) pci_config_header { + /* PCI header field Byte offset */ + unsigned short vendorID; /* 0x0 */ + unsigned short deviceID; /* 2 */ + unsigned short command; /* 4 */ + unsigned short status; /* 6 */ + unsigned char revID; /* 8 */ + unsigned char progIF; /* 9 */ + unsigned char subClass; /* a */ + unsigned char classCode; /* b */ + unsigned char clSize; /* c */ + unsigned char latencyTimer; /* d */ + unsigned char headerType; /* e */ + unsigned char BIST; /* f */ + unsigned int bars[PCI_BARS_PER_HEADER]; /* 10 */ + unsigned int cardbusCISPtr; /* 28 */ + unsigned short subsystemVendorID; /* 2c */ + unsigned short subsystemID; /* 2e */ + unsigned int expansionROMAddr; /* 30 */ + unsigned char capabilitiesPtr; /* 34 */ + unsigned char reserved0; /* 35 */ + unsigned char reserved1; /* 36 */ + unsigned char reserved2; /* 37 */ + unsigned int reserved3; /* 38 */ + unsigned char interruptLine; /* 3c */ + unsigned char interruptPin; /* 3d */ + unsigned char minGrant; /* 3e */ + unsigned char maxLatency; /* 3f */ +}; + +extern int pci_init(void); +extern int find_pci_device(int32, int32, int32); +extern struct eth_pd* eth_txring; +extern struct eth_pd* eth_rxring; + +extern int pci_read_config_byte(uint32, int, unsigned char *); +extern int pci_read_config_word(uint32, int, uint16 *); +extern int pci_read_config_dword(uint32, int, uint32 *); +extern int pci_write_config_byte(uint32, int, unsigned char); +extern int pci_write_config_word(uint32, int, uint16); +extern int pci_write_config_dword(uint32, int, uint32); +extern int pci_get_dev_mmio_base_addr(uint32, int, void **); diff --git a/include/platform/x86-galileo/pxe.h b/include/platform/x86-galileo/pxe.h new file mode 100644 index 0000000..c1b4ed8 --- /dev/null +++ b/include/platform/x86-galileo/pxe.h @@ -0,0 +1,43 @@ +/* pxe.h - Definitions for Pre-Execution Boot Environment */ + +/* BIOS SYSID Structure Table */ +#define SYSID_ENTRY_POINT_SADDR 0x000E0000 +#define SYSID_ENTRY_POINT_EADDR 0x000FFFFF + +#define SYSID_ENTRY_POINT_HDR "_SYSID_" +#define SYSID_ENTRY_UUID_HDR "_UUID_" + +#pragma pack(1) +struct sysid_bios_struct +{ + byte header[6]; + byte checksum; + uint16 len; +}; +#pragma pack() + +#pragma pack(1) +struct sysid_entry_point +{ + byte header[7]; + byte checksum; + uint16 len; + uint32 bios_structure_addr; + uint16 bios_struct_count; + byte sysid_bios_revision; +}; +#pragma pack() + +struct sysid_entry_point* get_sysid_entry_point(); +char* get_uuid(uint16* uuid_len); + +/* PXE client specification string */ +/* Tells the boot server information about client architecture */ +/* and supported PXE version */ +/* Client architecture - 000000 - IA x86 PC */ +/* PXE Version - 2.1 */ +#define PXE_CLIENT_STRING "PXEClient:Arch:00000:UNDI:002001" +#define PXE_CLIENT_STRING_LEN 32 + +int32 build_dhcp_discover_pxe(struct dhcpmsg* dmsg); +int32 build_dhcp_request_pxe(struct dhcpmsg* dmsg, const struct dhcpmsg* dmsg_offer); diff --git a/include/platform/x86-galileo/quark_eth.h b/include/platform/x86-galileo/quark_eth.h new file mode 100644 index 0000000..b67016a --- /dev/null +++ b/include/platform/x86-galileo/quark_eth.h @@ -0,0 +1,146 @@ +/* quark_eth.h */ + +/* Definitions for Intel Quark Ethernet */ + +#define INTEL_ETH_QUARK_PCI_DID 0x0937 /* MAC PCI Device ID */ +#define INTEL_ETH_QUARK_PCI_VID 0x8086 /* MAC PCI Vendor ID */ + +struct eth_q_csreg { + uint32 maccr; /* MAC Configuration Register */ + uint32 macff; /* MAC Frame Filter Register */ + uint32 hthr; /* Hash Table High Register */ + uint32 htlr; /* Hash Table Low Register */ + uint32 gmiiar; /* GMII Address Register */ + uint32 gmiidr; /* GMII Data Register */ + uint32 fcr; /* Flow Control Register */ + uint32 vlantag; /* VLAV Tag Register */ + uint32 version; /* Version Register */ + uint32 debug; /* Debug Register */ + uint32 res1[4]; /* Skipped Addresses */ + uint32 ir; /* Interrupt Register */ + uint32 imr; /* Interrupt Mask Register */ + uint32 macaddr0h; /* MAC Address0 High Register */ + uint32 macaddr0l; /* MAC Address0 Low Register */ + uint32 res2[46]; + uint32 mmccr; /* MAC Management Counter Cntl Register */ + uint32 mmcrvcir; /* MMC Receive Interrupt Register */ + uint32 mmctxir; /* MMC Transmit Interrupt Register */ + uint32 res3[957]; /* Skipped Addresses */ + uint32 bmr; /* Bus Mode Register */ + uint32 tpdr; /* Transmit Poll Demand Register */ + uint32 rpdr; /* Receive Poll Demand Register */ + uint32 rdla; /* Receive Descriptor List Addr */ + uint32 tdla; /* Transmit Descriptor List Addr */ + uint32 sr; /* Status Register */ + uint32 omr; /* Operation Mode Register */ + uint32 ier; /* Interrupt Enable Register */ +}; + +/* Individual Bits in Control and Status Registers */ + +/* MAC Configuration Register */ + +#define ETH_QUARK_MACCR_PE2K 0x08000000 /* Enable 2K Packets */ +#define ETH_QUARK_MACCR_WD 0x00800000 /* Watchdog Disable */ +#define ETH_QUARK_MACCR_JD 0x00400000 /* Jabber Disable */ +#define ETH_QUARK_MACCR_JE 0x00100000 /* Jumbo Frame Enable */ + +/* Inter-frame gap values */ +#define ETH_QUARK_MACCR_IFG96 0x00000000 /* 96 bit times */ +#define ETH_QUARK_MACCR_IFG88 0x00020000 /* 88 bit times */ +#define ETH_QUARK_MACCR_IFG80 0x00040000 /* 80 bit times */ +#define ETH_QUARK_MACCR_IFG40 0x000E0000 /* 40 bit times */ +#define ETH_QUARK_MACCR_IFG64 0x00080000 /* 64 bit times */ + +#define ETH_QUARK_MACCR_DCRS 0x00010000 /* Dis. C. Sense dur TX */ +#define ETH_QUARK_MACCR_RMIISPD10 0x00000000 /* RMII Speed = 10 Mbps */ +#define ETH_QUARK_MACCR_RMIISPD100 0x00004000 /* RMII Speed = 100 Mbps*/ +#define ETH_QUARK_MACCR_DO 0x00002000 /* Disable Receive Own */ +#define ETH_QUARK_MACCR_LM 0x00001000 /* Loopback Mode Enable */ +#define ETH_QUARK_MACCR_DM 0x00000800 /* Duplex Mode Enable */ +#define ETH_QUARK_MACCR_IPC 0x00000400 /* Checksum Offload */ +#define ETH_QUARK_MACCR_DR 0x00000200 /* Disable Retry */ +#define ETH_QUARK_MACCR_ACS 0x00000080 /* Auto Pad or CRC Strip*/ +#define ETH_QUARK_MACCR_DC 0x00000010 /* Deferral Check */ +#define ETH_QUARK_MACCR_TE 0x00000008 /* Transmitter Enable */ +#define ETH_QUARK_MACCR_RE 0x00000004 /* Receiver Enable */ +#define ETH_QUARK_MACCR_PRELEN7 0x00000000 /* Preamble = 7 bytes */ +#define ETH_QUARK_MACCR_PRELEN5 0x00000001 /* Preamble = 5 bytes */ +#define ETH_QUARK_MACCR_PRELEN3 0x00000002 /* Preamble = 3 bytes */ + +#define ETH_QUARK_MMC_CNTFREEZ 0x00000008 /* Freeze MMC counter values*/ +#define ETH_QUARK_MMC_CNTRST 0x00000001 /* Reset all cntrs to zero */ + +/* GMII Address Register */ +#define ETH_QUARK_GMIIAR_PAMASK 0x0000F800 /* Phys Layer Addr Mask */ +#define ETH_QUARK_GMIIAR_GRMASK 0x000007C0 /* GMII Register Mask */ +#define ETH_QUARK_GMIIAR_CR 0x00000004 /* Clk Range = 100-150 */ + /* MHz for Quark */ +#define ETH_QUARK_GMIIAR_GW 0x00000002 /* GMII Write Enable */ +#define ETH_QUARK_GMIIAR_GB 0x00000001 /* GMII Busy */ + +/* Bus Mode Register */ +#define ETH_QUARK_BMR_SWR 0x00000001 /* Software Reset */ + +/* Status Register */ +#define ETH_QUARK_SR_MMCI 0x08000000 /* MAC MMC interrupt */ +#define ETH_QUARK_SR_TS_SUSP 0x00600000 /* TX DMA is suspended */ +#define ETH_QUARK_SR_NIS 0x00010000 /* Normal Int summary */ +#define ETH_QUARK_SR_AIS 0x00008000 /* Abnorm Intrupt summ. */ +#define ETH_QUARK_SR_RI 0x00000040 /* Receive Interrupt */ +#define ETH_QUARK_SR_TI 0x00000001 /* Transmit Interrupt */ + +/* Operation Mode Register */ +#define ETH_QUARK_OMR_TSF 0x00200000 /* Tx store and forward */ +#define ETH_QUARK_OMR_ST 0x00002000 /* Start/Stop TX */ +#define ETH_QUARK_OMR_SR 0x00000002 /* Start/Stop RX */ + +/* Interrupt Enable Register */ +#define ETH_QUARK_IER_NIE 0x00010000 /* Enable Norm Int Summ.*/ +#define ETH_QUARK_IER_AIE 0x00008000 /* Enable Abnnom " " */ +#define ETH_QUARK_IER_RIE 0x00000040 /* Enable RX Interrupt */ +#define ETH_QUARK_IER_TIE 0x00000001 /* Enable TX Interrupt */ + +/* Quark Ethernet Transmit Descriptor */ + +struct eth_q_tx_desc { + uint32 ctrlstat; /* Control and status */ + uint16 buf1size; /* Size of buffer 1 */ + uint16 buf2size; /* Size of buffer 2 */ + uint32 buffer1; /* Address of buffer 1 */ + uint32 buffer2; /* Address of buffer 2 */ +}; + +#define ETH_QUARK_TDCS_OWN 0x80000000 /* Descrip. owned by DMA*/ +#define ETH_QUARK_TDCS_IC 0x40000000 /* Int on Completion */ +#define ETH_QUARK_TDCS_LS 0x20000000 /* Last Segment */ +#define ETH_QUARK_TDCS_FS 0x10000000 /* First Segment */ +#define ETH_QUARK_TDCS_TER 0x00200000 /* Transmit End of Ring */ +#define ETH_QUARK_TDCS_ES 0x00008000 /* Error Summary */ + +/* Quark Ethernet Receive Descriptor */ + +struct eth_q_rx_desc { + uint32 status; /* Desc status word */ + uint16 buf1size; /* Size of buffer 1 */ + uint16 buf2size; /* Size of buffer 2 */ + uint32 buffer1; /* Address of buffer 1 */ + uint32 buffer2; /* Address of buffer 2 */ +}; +#define rdctl1 buf1size /* Buffer 1 size field has control bits too */ +#define rdctl2 buf2size /* Buffer 2 size field has control bits too */ + +#define ETH_QUARK_RDST_OWN 0x80000000 /* Descrip. owned by DMA*/ +#define ETH_QUARK_RDST_ES 0x00008000 /* Error Summary */ +#define ETH_QUARK_RDST_FS 0x00000200 /* First Segment */ +#define ETH_QUARK_RDST_LS 0x00000100 /* Last segment */ +#define ETH_QUARK_RDST_FTETH 0x00000020 /* Frame Type = Ethernet*/ + +#define ETH_QUARK_RDCTL1_DIC 0x8000 /* Dis. Int on Complet. */ +#define ETH_QUARK_RDCTL1_RER 0x8000 /* Recv End of Ring */ + +#define ETH_QUARK_RX_RING_SIZE 32 +#define ETH_QUARK_TX_RING_SIZE 16 + +#define ETH_QUARK_INIT_DELAY 500000 /* Delay in micro secs */ +#define ETH_QUARK_MAX_RETRIES 3 /* Max retries for init */ diff --git a/include/platform/x86-galileo/quark_irq.h b/include/platform/x86-galileo/quark_irq.h new file mode 100644 index 0000000..edafd0b --- /dev/null +++ b/include/platform/x86-galileo/quark_irq.h @@ -0,0 +1,22 @@ +#define INTEL_QUARK_LEGBR_PCI_DID 0x095E /* Legacy Bridge Device ID */ +#define INTEL_QUARK_LEGBR_PCI_VID 0x8086 /* Legacy Bridge Vendor ID */ + +#define PABCDRC_OFFSET 0x60 /* PIRQ A-D Routing Control offset */ +#define PEFGHRC_OFFSET 0x64 /* PIRQ E-H Routing control offset */ + +#define PABCDRC_VALUE 0x06050403 /* PIRQ A-D routed to 8259 IRQ 2-5 resp. */ +#define PEFGHRC_VALUE 0x0C0B0A09 /* PIRQ E-H routed to 8259 IRQ 6-9 resp. */ + +#define RCBA_OFFSET 0xF0 /* RCBA offset in PCI config space */ +#define RCBA_MASK 0xffffc000 + +/* IRQAGENTx offset from the Root Complex Base Address */ +#define IRQAGENT0_OFFSET 0x3140 +#define IRQAGENT1_OFFSET 0x3142 +#define IRQAGENT2_OFFSET 0x3144 +#define IRQAGENT3_OFFSET 0x3146 + +#define IRQAGENT0_VALUE 0x0000 /* Remote Management Unit, only PCI INTA, routed to PIRQA */ +#define IRQAGENT1_VALUE 0x3210 /* PCIe* Multi-function, PCI INTA-D, routed to PIRQA-D resp */ +#define IRQAGENT2_VALUE 0x0001 /* Reserved */ +#define IRQAGENT3_VALUE 0x7654 /* IO Fabric Multi-func, PCI INTA-D, routed to PIRQE-H resp */ diff --git a/include/platform/x86-galileo/quark_pdat.h b/include/platform/x86-galileo/quark_pdat.h new file mode 100644 index 0000000..9134452 --- /dev/null +++ b/include/platform/x86-galileo/quark_pdat.h @@ -0,0 +1,41 @@ +/* quark_pdat.h - Functions for reading the platform data */ + +/* Structures and Values used to read the platform data from the memory mapped SPI flash */ +#define QUARK_PDAT_MAGIC "PDAT" /* Platform header signature */ +#define QUARK_PDAT_MEMORY_LOC 0xFFF10000 /* Memory mapped location of the platform data */ + +/* Platform Type Identifiers */ +#define QUARK_PLAT_TYPE_ID 1 +#define QUARK_MAC1_ID 3 +#define QUARK_MAC2_ID 4 +#define QUARK_MRCPARAMS_ID 6 + +/* Platform entry descriptions */ +#define QUARK_PLAT_TYPE_DESC "PlatformID" +#define QUARK_MRCPARAMS_DESC "MrcParams" +#define QUARK_MAC1_DESC "1st MAC" +#define QUARK_MAC2_DESC "2nd MAC" + +#pragma pack(2) +struct quark_pdat_header { + char quark_pdat_magic[4]; /* Platform header signature */ + uint32 quark_pdat_len; /* Size in bytes of the platform data (not including the header */ + uint32 quark_pdat_crc; /* CRC value for the platform data (not including the header) */ + + /* Platform data entries follow here */ +}; +#pragma pack() + +#pragma pack(2) +struct quark_pdat_entry { + uint16 pdat_entry_id; /* Type identifier for the platform data entry */ + uint16 pdat_entry_len; /* Length in bytes of the platform entry (not including the entry header) */ + char pdat_entry_desc[10]; /* Description string of the platform entry */ + uint16 pdat_entry_ver; /* Version of the platform entry */ + + /* variable length data for the entry */ +}; +#pragma pack() + +int get_quark_pdat_entry_data_by_id(uint16 type_id, char* buf, uint32 size); +int get_quark_pdat_entry_data_by_desc(const char* entry_desc, char* buf, uint32 size); diff --git a/include/platform/x86-galileo/sdmc.h b/include/platform/x86-galileo/sdmc.h new file mode 100644 index 0000000..1f19613 --- /dev/null +++ b/include/platform/x86-galileo/sdmc.h @@ -0,0 +1,327 @@ +#define INTEL_QUARK_SDIO_PCI_DID 0x08A7 /* Intel Quark SDIO PCI Device ID */ +#define INTEL_QUARK_SDIO_PCI_VID 0x8086 /* Intel Quark SDIO MAC PCI Vendor ID */ + +#ifndef Nsdmc +#define Nsdmc 1 /* number of SD Memory Cards */ +#endif + +struct sdmcblk { + sid32 cmd_sem; /* command semaphore */ + sid32 tx_sem; /* transfer semaphore */ + uint32 rca; /* relative card address */ + char cid[16]; /* Card identifier */ + uint8 cmd8 :1; /* Card supports CMD8 */ + uint8 sdio :1; /* Card is an SDIO card */ + uint8 rsvd :6; +}; +extern struct sdmcblk sdmctab[]; + +#pragma pack(1) +struct sdmc_csreg { + uint32 sys_adr; /* sdma system address register */ + uint16 blk_size; /* block size register */ + uint16 blk_count; /* block count register */ + uint32 argument; /* argument register */ + uint16 tx_mode; /* transfer mode register */ + uint16 cmd; /* command register */ + uint32 response0; /* response register 0 */ + uint32 response2; /* response register 2 */ + uint32 response4; /* response register 4 */ + uint32 response6; /* response register 6 */ + uint32 buf_data_port; /* buffer data port register */ + uint32 pre_state; /* present state register */ + uint8 host_ctl; /* host control register */ + uint8 pwr_ctl; /* power control register */ + uint8 blk_gap_ctl; /* block gap control register */ + uint8 wakeup_ctl; /* wakeup control register */ + uint16 clk_ctl; /* clock control register */ + uint8 timeout_ctl; /* timeout control register */ + uint8 sw_rst; /* software reset register */ + uint16 nml_int_status; /* normal interrupt status register */ + uint16 err_int_status; /* error interrupt status register */ + uint16 nrm_int_status_en; /* normal interrupt status enable */ + uint16 err_int_stat_en; /* error interrupt status enable register */ + uint16 nrm_int_sig_en; /* normal interrupt signal enable register */ + uint16 err_int_sig_en; /* error interrupt signal enable register */ + uint16 cmd12_err_stat; /* auto cmd12 error status register */ + uint16 host_ctrl_2; /* host control 2 register */ + uint32 capabilities; /* capabilities register */ + uint32 capabilities_2; /* capabilities register 2 */ + uint32 max_cur_cap; /* maximum current capabilities register */ + byte rsvd1[4]; + uint16 force_event_cmd12_err_stat; /* force event register for auto cmd12 error status */ + uint16 force_event_err_int_stat; /* force event register for error interrupt status */ + uint8 adma_err_stat; /* adma error status register */ + byte rsvd2[3]; + uint32 adma_sys_addr; /* adma system address register */ + byte rsvd3[4]; + uint16 preset_value_0; /* initialization preset values register */ + uint16 preset_value_1; /* default speed preset values register */ + uint16 preset_value_2; /* high speed preset values register */ + uint16 preset_value_3; /* sdr12 preset values register */ + uint16 preset_value_4; /* sdr25 preset values register */ + uint16 preset_value_5; /* sdr50 preset values register */ + uint16 preset_value_6; /* sdr104 preset values register */ + uint16 preset_value_7; /* ddr50 preset values register */ + uint32 boot_timeout_ctrl; /* boot time-out control register */ + uint8 debug_sel; /* debug selection register */ + byte rsvd4[107]; + uint32 shared_bus; /* shared bus control register */ + byte rsvd5[12]; + uint8 spi_int_sup; /* spi interrupt support register */ + byte rsvd6[11]; + uint16 slot_int_stat; /* slot interrupt status register */ + uint16 host_ctrl_ver; /* host controller version register */ +}; +#pragma pack() + +struct sdmc_cmd { + uint16 resp_type_sel :2; + uint16 cmd_crc_chk_en :1; + uint16 cmd_index_chk_en:1; + uint16 dat_pr_sel :2; + uint16 cmd_type :2; + uint16 cmd_index :6; + uint16 rsvd :2; +}; + +struct sdmc_capabilities { + uint32 timeout_clock_frequency :6; /* Timeout Clock Frequency */ + uint32 rsvd6 :1; /* RSVD6 */ + uint32 timeout_clock_unit :1; /* Timeout Clock Unit */ + uint32 base_clock_frequency_sd_clk:8; /* Base Clock Frequency for SD Clock */ + uint32 max_block_length :2; /* Max Block Length */ + uint32 extended_media_bus_support:1; /* Extended Media Bus Support */ + uint32 adma2_support :1; /* ADMA2 Support */ + uint32 rsvd5 :1; /* RSVD5 */ + uint32 high_speed_support :1; /* High Speed Support */ + uint32 sdma_support :1; /* SDMA Support */ + uint32 suspend_resume_support :1; /* Suspend / Resume Support */ + uint32 volt_support_3p3v :1; /* Voltage Support 3.3V */ + uint32 volt_support_3p0v :1; /* Voltage Support 3.0V */ + uint32 volt_support_1p8v :1; /* Voltage Support 1.8V */ + uint32 rsvd4 :1; /* RSVD4 */ + uint32 sys_bus_support_64b :1; /* 64-bit System Bus Support */ + uint32 async_int_support :1; /* Asynchronous Interrupt Support */ + uint32 slot_type :2; /* Slot Type */ +}; + +/* Individual Bits in Control and Status Registers */ + +/* Normal Interrupt Status Enable */ +#define SDMC_CMD_COMP_STAT_EN 0x0001 /* Command Complete Status Enable */ +#define SDMC_TX_COMP_STAT_EN 0x0002 /* Transfer Complete Status Enable */ +#define SDMC_BLK_GAP_EVENT_STAT_EN 0x0004 /* Block Gap Event Status Enable */ +#define SDMC_DMA_INT_STAT_EN 0x0008 /* DMA Interrupt Status Enable */ +#define SDMC_BUF_WR_RDY_STAT_EN 0x0010 /* Buffer Write Ready Status Enable */ +#define SDMC_BUF_RD_RDY_STAT_EN 0x0020 /* Buffer Read Ready Status Enable */ +#define SDMC_CRD_INS_STAT_EN 0x0040 /* Card Insertion Status Enable */ +#define SDMC_CRD_RMV_STAT_EN 0x0080 /* Card Removal Status Enable */ +#define SDMC_CRD_INT_STAT_EN 0x0100 /* Card Interrupt Status Enable */ +#define SDMC_INT_A_STAT_EN 0x0200 /* INT_A Status Enable */ +#define SDMC_INT_B_STAT_EN 0x0400 /* INT_A Status Enable */ +#define SDMC_INT_C_STAT_EN 0x0800 /* INT_A Status Enable */ +#define SDMC_RE_TUNE_STAT_EN 0x1000 /* Re-Tuning Event Status Enable */ + +/* Normal Interrupt Signal Enable */ +#define SDMC_CMD_COMP_SIG_EN 0x0001 /* Command Complete Signal Enable */ +#define SDMC_TX_COMP_SIG_EN 0x0002 /* Transfer Complete Signal Enable */ +#define SDMC_BLK_GAP_EVENT_SIG_EN 0x0004 /* Block Gap Event Signal Enable */ +#define SDMC_DMA_INT_SIG_EN 0x0008 /* DMA Interrupt Signal Enable */ +#define SDMC_BUF_WR_RDY_SIG_EN 0x0010 /* Buffer Write Ready Signal Enable */ +#define SDMC_BUF_RD_RDY_SIG_EN 0x0020 /* Buffer Read Ready Signal Enable */ +#define SDMC_CRD_INS_SIG_EN 0x0040 /* Card Insertion Signal Enable */ +#define SDMC_CRD_RMV_SIG_EN 0x0080 /* Card Removal Signal Enable */ +#define SDMC_CRD_INT_SIG_EN 0x0100 /* Card Interrupt Signal Enable */ +#define SDMC_INT_A_SIG_EN 0x0200 /* INT_A Signal Enable */ +#define SDMC_INT_B_SIG_EN 0x0400 /* INT_A Signal Enable */ +#define SDMC_INT_C_SIG_EN 0x0800 /* INT_A Signal Enable */ +#define SDMC_RE_TUNE_SIG_EN 0x1000 /* Re-Tuning Event Signal Enable */ + +/* Normal Interrupt Status Register */ +#define SDMC_NML_INT_CMD_COMP 0x0001 /* Command Complete */ +#define SDMC_NML_INT_TX_COMP 0x0002 /* Transfer Complete */ +#define SDMC_NML_INT_BLK_GAP_EVENT 0x0004 /* Block Gap Event */ +#define SDMC_NML_INT_DMA_INT 0x0008 /* DMA Interrupt */ +#define SDMC_NML_INT_BUF_WR_RDY 0x0010 /* Buffer Write Ready */ +#define SDMC_NML_INT_BUF_RD_RDY 0x0020 /* Buffer Read Ready */ +#define SDMC_NML_INT_CRD_INS 0x0040 /* Card Insertion */ +#define SDMC_NML_INT_CRD_RM 0x0080 /* Card Removal */ +#define SDMC_NML_INT_CRD_INT 0x0100 /* Card Interrupt */ +#define SDMC_NML_INT_INT_A 0x0200 /* INT_A */ +#define SDMC_NML_INT_INT_B 0x0400 /* INT_B */ +#define SDMC_NML_INT_INT_C 0x0800 /* INT_C */ +#define SDMC_NML_INT_RE_TUNE 0x1000 /* Re-Tuning Event */ +#define SDMC_NML_INT_BOOT_CK_RCV 0x2000 /* Boot Acknowledge Received */ +#define SDMC_NML_INT_BOOT_TER_INT 0x4000 /* Boot Terminate Interrupt */ +#define SDMC_NML_INT_ERR_INT 0x8000 /* Error Interrupt */ + +/* Error Interrupt Status Enable */ +#define SDMC_ERR_INT_CMD_TIMEOUT_ERR_STAT_EN 0x0001 /* Command Timeout Error Status Enable */ +#define SDMC_ERR_INT_CMD_CRC_ERR_STAT_EN 0x0002 /* Command CRC Error Status Enable */ +#define SDMC_ERR_INT_CMD_END_BIT_ERR_STAT_EN 0x0004 /* Command End Bit Error Status Enable */ +#define SDMC_ERR_INT_CMD_IND_ERR_STAT_EN 0x0008 /* Command Index Error Status Enable */ +#define SDMC_ERR_INT_DATA_TIMEOUT_ERR_STAT_EN 0x0010 /* Data Timeout Error Status Enable */ +#define SDMC_ERR_INT_DATA_CRC_ERR_STAT_EN 0x0020 /* Data CRC Error Status Enable */ +#define SDMC_ERR_INT_DATA_END_BIT_ERR_STAT_EN 0x0040 /* Data End Bit Error Status Enable */ +#define SDMC_ERR_INT_CUR_LIMIT_ERR_STAT_EN 0x0080 /* Current Limit Error Status Enable */ +#define SDMC_ERR_INT_CMD12_ERR_STAT_EN 0x0100 /* Auto CMD12 Error Status Enable */ +#define SDMC_ERR_INT_ADMA_ERR_STAT_EN 0x0200 /* ADMA Error Status Enable */ +#define SDMC_ERR_INT_TUNE_ERR_STAT_EN 0x0400 /* Tuning Error Status Enable */ +#define SDMC_ERR_INT_TGT_RSP_ERR_EN 0x1000 /* Target Response Error Status Enable */ +#define SDMC_ERR_INT_CEATA_ERR_EN 0x2000 /* CEATA Error Status Enable */ + +/* Error Interrupt Signal Enable */ +#define SDMC_ERR_INT_CMD_TIMEOUT_ERR_SIG_EN 0x0001 /* Command Timeout Error Signal Enable */ +#define SDMC_ERR_INT_CMD_CRC_ERR_SIG_EN 0x0002 /* Command CRC Error Signal Enable */ +#define SDMC_ERR_INT_CMD_END_BIT_ERR_SIG_EN 0x0004 /* Command End Bit Error Signal Enable */ +#define SDMC_ERR_INT_CMD_IND_ERR_SIG_EN 0x0008 /* Command Index Error Signal Enable */ +#define SDMC_ERR_INT_DATA_TIMEOUT_ERR_SIG_EN 0x0010 /* Data Timeout Error Signal Enable */ +#define SDMC_ERR_INT_DATA_CRC_ERR_SIG_EN 0x0020 /* Data CRC Error Signal Enable */ +#define SDMC_ERR_INT_DATA_END_BIT_ERR_SIG_EN 0x0040 /* Data End Bit Error Signal Enable */ +#define SDMC_ERR_INT_CUR_LIMIT_ERR_SIG_EN 0x0080 /* Current Limit Error Signal Enable */ +#define SDMC_ERR_INT_CMD12_ERR_SIG_EN 0x0100 /* Auto CMD12 Error Signal Enable */ +#define SDMC_ERR_INT_ADMA_ERR_SIG_EN 0x0200 /* ADMA Error Signal Enable */ +#define SDMC_ERR_INT_TUNE_ERR_SIG_EN 0x0400 /* Tuning Error Signal Enable */ +#define SDMC_ERR_INT_TGT_RSP_ERR_SIG_EN 0x1000 /* Target Response Error Signal Enable */ +#define SDMC_ERR_INT_CEATA_ERR_SIG_EN 0x2000 /* CEATA Error Signal Enable */ + +/* Error Interrupt Status Register */ +#define SDMC_ERR_INT_CMD_TIMEOUT_ERR 0x0001 /* Command Timeout Error */ +#define SDMC_ERR_INT_CMD_CRC_ERR 0x0002 /* Command CRC Error */ +#define SDMC_ERR_INT_CMD_END_BIT_ERR 0x0004 /* Command End Bit Error */ +#define SDMC_ERR_INT_CMD_INDEX_ERR 0x0008 /* Command Index Error */ +#define SDMC_ERR_INT_DATA_TIMEOUT_ERR 0x0010 /* Data Timeout Error */ +#define SDMC_ERR_INT_DATA_CRC_ERR 0x0020 /* Data CRC Error */ +#define SDMC_ERR_INT_DATA_END_BIT_ERR 0x0040 /* Data End Bit Error */ +#define SDMC_ERR_INT_CUR_LIMIT_ERR 0x0080 /* Current Limit Error */ +#define SDMC_ERR_INT_CMD12_ERR 0x0100 /* Auto CMD Error */ +#define SDMC_ERR_INT_ADMA_ERR 0x0200 /* ADMA Error */ +#define SDMC_ERR_INT_TUNE_ERR 0x0400 /* Tuning Error */ +#define SDMC_ERR_INT_TGT_RSP_ERR 0x1000 /* Target Response Error */ +#define SDMC_ERR_INT_CEATA_ERR 0x2000 /* CEATA Error */ + +/* Software Reset Register */ +#define SDMC_SW_RST_ALL 0x01 /* Software Reset For All */ +#define SDMC_SW_RST_CMD_LN 0x02 /* Software Reset For CMD Line */ +#define SDMC_SW_RST_DAT_LN 0x04 /* Software Reset for DAT Line */ + +/* Capabilities Register */ +#define SDMC_CAP_VOLT_SUPPORT_3P3V 0x01000000 /* Voltage Support 3.3V */ +#define SDMC_CAP_VOLT_SUPPORT_3P0V 0x02000000 /* Voltage Support 3.0V */ +#define SDMC_CAP_VOLT_SUPPORT_1P8V 0x04000000 /* Voltage Support 1.8V */ + +/* Present State Status Register */ +#define SDMC_PRE_STATE_CMD_INHIBIT_CMD 0x00000001 /* Command Inhibit */ +#define SDMC_PRE_STATE_CMD_INHIBIT_DAT 0x00000002 /* Command Inhibit DAT */ +#define SDMC_PRE_STATE_CRD_INS 0x00010000 /* Card Inserted */ +#define SDMC_PRE_STATE_DATA_LN_SIG_LVL 0x00F00000 /* Line Signal Level */ + +/* Clock Control Register */ +#define SDMC_CLK_CTL_INT_CLK_EN 0x0001 /* Internal Clock Enable */ +#define SDMC_CLK_CTL_INT_CLK_STABLE 0x0002 /* Internal Clock Stable */ +#define SDMC_CLK_CTL_SD_CLK_EN 0x0004 /* SD Clock Enable */ +#define SDMC_CLK_CTL_CLK_GEN_SEL 0x0020 /* Clock Generator Select */ +#define SDMC_CLK_CTL_SD_FREQ_HIGH_MASK 0x00FF /* Mask to set SD clock frequency to max*/ + +/* Power Control Register */ +#define SDMC_PWR_CTL_SD_BUS_PWR 0x01 /* SD Bus Power */ +#define SDMC_PWR_CTL_HW_RST 0x10 /* HW Reset */ +#define SDMC_PWR_CTL_SD_BUS_VOL_SEL_CLR 0xF1 /* Clear mask for SD bus voltage*/ +#define SDMC_PWR_CTL_SD_BUS_VOL_SEL_3P3V 0x0E /* Set mask for 3.3V */ +#define SDMC_PWR_CTL_SD_BUS_VOL_SEL_3P0V 0x0C /* Set mask for 3.0V */ +#define SDMC_PWR_CTL_SD_BUS_VOL_SEL_1P8V 0x0A /* Set mask for 1.8V */ + +/* Card Status Response (R1) */ +#define SDMC_R1_AKE_SEQ_ERROR 0x00000008 /* Authentication Error */ +#define SDMC_R1_APP_CMD 0x00000020 /* Next command is application */ +#define SDMC_R1_READY_FOR_DATA 0x00000100 /* Card ready for data */ +#define SDMC_R1_CURRENT_STATE 0x00001E00 /* Current card state */ +#define SDMC_R1_ERASE_RESET 0x00002000 /* Erase processes reset */ +#define SDMC_R1_CARD_ECC_DISABLED 0x00004000 /* Command without ECC */ +#define SDMC_R1_WP_ERASE_SKIP 0x00008000 /* Write protected */ +#define SDMC_R1_CSD_OVERWRITE 0x00010000 /* Error in CSD overwrite */ +#define SDMC_R1_ERROR 0x00080000 /* Unknown error */ +#define SDMC_R1_CC_ERROR 0x00100000 /* Internal controller error */ +#define SDMC_R1_CARD_ECC_FAILED 0x00200000 /* ECC correction failed */ +#define SDMC_R1_ILLEGAL_COMMAND 0x00400000 /* Not a legal command */ +#define SDMC_R1_COM_CRC_ERROR 0x00800000 /* Previous command CRC failed */ +#define SDMC_R1_LOCK_UNLOCK_FAILED 0x01000000 /* Lock/unlock of card failed */ +#define SDMC_R1_CARD_IS_LOCKED 0x02000000 /* Card is locked */ +#define SDMC_R1_WP_VIOLATION 0x04000000 /* Write to protected block */ +#define SDMC_R1_ERASE_PARAM 0x08000000 /* Invalid erase parameter */ +#define SDMC_R1_ERASE_SEQ_ERROR 0x10000000 /* Invalid erase sequence */ +#define SDMC_R1_BLOCK_LEN_ERROR 0x20000000 /* TX block length not allowed */ +#define SDMC_R1_ADDRESS_ERROR 0x40000000 /* Misaligned address */ +#define SDMC_R1_OUT_OF_RANGE 0x80000000 /* Argument out of range */ + +/* Card state */ +#define SDMC_R1_IDLE_STATE 0x00000000 /* Idle State */ +#define SDMC_R1_READY_STATE 0x00000200 /* Ready State */ +#define SDMC_R1_IDENT_STATE 0x00000400 /* Identification State */ +#define SMDC_R1_STBY_STATE 0x00000600 /* Standby State */ +#define SDMC_R1_TRAN_STATE 0x00000800 /* Transfer State */ +#define SDMC_R1_DATA_STATE 0x00000A00 /* Sending-data State */ +#define SDMC_R1_RCV_STATE 0x00000C00 /* Receive-data State */ +#define SDMC_R1_PRG_STATE 0x00000E00 /* Programming State */ +#define SMDC_R1_DIS_STATE 0x00001000 /* Disconnect State */ + +/* Operating Conditions Register Response (R3) */ +#define SDMC_R3_2P7_2P8 0x00008000 /* Voltage Range 2.7V - 2.8V */ +#define SDMC_R3_2P8_2P9 0x00010000 /* Voltage Range 2.8V - 2.9V */ +#define SDMC_R3_2P9_3P0 0x00020000 /* Voltage Range 2.9V - 3.0V */ +#define SDMC_R3_3P0_3P1 0x00040000 /* Voltage Range 3.0V - 3.1V */ +#define SDMC_R3_3P1_3P2 0x00080000 /* Voltage Range 3.1V - 3.2V */ +#define SDMC_R3_3P2_3P3 0x00100000 /* Voltage Range 3.2V - 3.3V */ +#define SDMC_R3_3P3_3P4 0x00200000 /* Voltage Range 3.3V - 3.4V */ +#define SDMC_R3_3P4_3P5 0x00400000 /* Voltage Range 3.4V - 3.5V */ +#define SDMC_R3_3P5_3P6 0x00800000 /* Voltage Range 3.5V - 3.6V */ +#define SDMC_R3_S18A 0x01000000 /* Switching to 1.8V accepted */ +#define SDMC_R3_UHS_II_STS 0x20000000 /* UHS-II card status */ +#define SDMC_R3_CCS 0x40000000 /* Card capacity status */ +#define SDMC_R3_BUSY 0x80000000 /* Card power up status (busy) */ + +/* Published RCA Response (R6) */ +#define SDMC_R6_RCA_MASK 0xFFFF0000 /* Relative card address mask */ +#define SDMC_R6_AKE_SEQ_ERROR 0x00000008 /* Authentication Error */ +#define SDMC_R6_APP_CMD 0x00000020 /* Next command is application */ +#define SDMC_R6_READY_FOR_DATA 0x00000100 /* Card ready for data */ +#define SDMC_R6_CURRENT_STATE 0x00001E00 /* Current card state */ +#define SDMC_R6_ERROR 0x00002000 /* Unknown error */ +#define SDMC_R6_ILLEGAL_COMMAND 0x00004000 /* Not a legal command */ +#define SDMC_R6_COM_CRC_ERROR 0x00008000 /* Previous command CRC failed */ + +/* ACMD41 Argument flags */ +#define SDMC_OCR_MASK 0x00FFFF00 /* OCR set mask */ +#define SDMC_ACMD41_S18R 0x01000000 /* Switching to 1.8V request */ +#define SDMC_ACMD41_XPC 0x10000000 /* Extended capacity power ctl */ +#define SDMC_ACMD41_HCS 0x40000000 /* High capacity card support */ + +#define SDMC_ABT 0x0CC0 /* CMD12 - Abort */ +#define SDMC_CMD0 0x0000 /* CMD0 - Go Idle State (Reset) */ +#define SDMC_CMD2 0x0209 /* CMD2 - All send card identifier */ +#define SDMC_CMD3 0x031A /* CMD3 - Send relative card address */ +#define SDMC_CMD7 0x071B /* CMD7 - Select/Deselect card */ +#define SDMC_CMD8 0x081A /* CMD8 - Voltage check */ +#define SDMC_CMD9 0x0909 /* CMD9 - Send CSD */ +#define SDMC_CMD10 0x0A09 /* CMD10 - Send CID */ +#define SDMC_CMD12 0x0C1B /* CMD12 - Stop Transmission */ +#define SDMC_CMD13 0x0D1A /* CMD13 - Send status */ +#define SDMC_CMD16 0x101A /* CMD16 - Set block length */ +#define SDMC_CMD17 0x113A /* CMD17 - Single block read */ +#define SDMC_CMD55 0x371A /* CMD55 - Application specific command */ +#define SDMC_ACMD41 0x2902 /* ACMD41 - Card Initialization/Inquiry */ + +#define SDMC_CMD_DELAY 100000 /* Delay in micro secs */ + +#define SDMC_RC_OK (0) +#define SDMC_RC_RECOVERABLE_ERR (-1) +#define SDMC_RC_NON_RECOVERABLE_ERROR (-2) + +#define SDMC_CMD_NO_FLAGS 0x00 /* No flags used with the command */ +#define SDMC_CMD_NO_ERR_RCVY 0x01 /* Do not perform error recovery */ +#define SDMC_CMD_DAT_TRNS 0x02 /* Wait for data transmission */ + +devcall sdmc_issue_cmd_sync (volatile struct sdmc_csreg *csrptr, uint16 cmd_value, uint32 arg_value, uint16* error_sts, uint8 flags); +devcall sdmc_issue_cmd_async (volatile struct sdmc_csreg *csrptr, uint16 cmd_value, uint32 arg_value); +devcall sdmc_finalize_cmd_async (volatile struct sdmc_csreg *csrptr, uint16* error_sts); \ No newline at end of file