Following the VHDL verification tutorial, and using yosys and ghdl, the resulting adder_yosys.json file can be load into SAW as described in the tutorial.

For TabbyCAD the following commands result into adder_tabby.json:

yosys> read -vhd adder.vhdl
yosys> hierarchy -check -top add4
yosys> write_json adder_tabby.json

However, importing adder_tabby.json to SAW yields the following error:

Error: Encountered a cell "$verific$i5$adder.vhd:15$37" with type "$_BUF_", but could not find a submodule named "$_BUF_".

It seems that $_BUF is a cell inserted by Verific (both files attached).

1. am I missing some setting or do I need to call TabbyCAD differently to produce SAW-digestible output? If so, we should update the tutorial to mention it
2. if not, SAW should be able to handle verific parsed VHDL designs, as TabbyCAD+verific is the commercial version of yosys+ghdl

adder_yosys.json

adder_tabby.json