Is rflags value reproducible/portable?

[McSinyx]

I'm getting a few (4) reg test failures due to differences in rflags value, not only in the reserved bits but also direction flag (bit 10) and I/O privilage level (bit 12):

Unified diff

--- after.out	2024-11-18 06:34:58.376875501 +0000
+++ after.exp	1970-01-01 00:00:01.000000000 +0000
@@ -25,22 +25,22 @@
 000000000a0001cb:000000000c007fe0:0000000000000600: 4d 01 ca                add %r9, %r10
 000000000a0001cf:000000000c007fe0:ffffffffffff9600: 49 83 e8 08             sub $0x8, %r8
 000000000a0001d2:000000000c007fe0:0000000000000700: 4d 29 c2                sub %r8, %r10
-000000000a0001d5:000000000c007fe0:0000000000000701: 49 f7 ea                imul %r10
-000000000a0001d9:000000000c007fe0:0000000000000701: 4d 0f af d3             imul %r11, %r10
-000000000a0001dd:000000000c007fe0:0000000000000600: 4d 6b d3 77             imul $0x77, %r11, %r10
+000000000a0001d5:000000000c007fe0:0000000000000301: 49 f7 ea                imul %r10
+000000000a0001d9:000000000c007fe0:ffffffffffff8701: 4d 0f af d3             imul %r11, %r10
+000000000a0001dd:000000000c007fe0:0000000000000200: 4d 6b d3 77             imul $0x77, %r11, %r10
 000000000a0001e3:000000000c007fe0:0000000000000200: 48 25 fe 00 00 00       and $0xfe, %rax
 000000000a0001e6:000000000c007fe0:0000000000000200: 48 21 c3                and %rax, %rbx
 000000000a0001ea:000000000c007fe0:0000000000000200: 48 83 cb 13             or $0x13, %rbx
 000000000a0001ed:000000000c007fe0:ffffffffffff8200: 48 09 cb                or %rcx, %rbx
 000000000a0001f0:000000000c007fe0:ffffffffffff8200: 48 f7 d1                not %rcx
 000000000a0001f3:000000000c007fe0:ffffffffffff9300: 48 f7 d9                neg %rcx
-000000000a0001f7:000000000c007fe0:0000000000001200: 48 c1 e7 07             shl $0x7, %rdi
-000000000a0001fb:000000000c007fe0:0000000000001200: 48 c1 ff 03             sar $0x3, %rdi
-000000000a0001fd:000000000c007fd8:0000000000001200: 41 55                   push %r13
-000000000a000204:000000000c007fd8:0000000000001200: 48 c7 c0 19 45 00 00    mov $0x4519, %rax
-000000000a000208:000000000c007fd8:0000000000001200: 66 0f ef c0             pxor %xmm0, %xmm0
-000000000a00020d:000000000c007fd8:0000000000001200: f3 48 0f 2a c0          cvtsi2ss %rax, %xmm0
-000000000a000211:000000000c007fd8:0000000000001200: f3 0f 51 c8             sqrtss %xmm0, %xmm1
+000000000a0001f7:000000000c007fe0:0000000000000200: 48 c1 e7 07             shl $0x7, %rdi
+000000000a0001fb:000000000c007fe0:0000000000000200: 48 c1 ff 03             sar $0x3, %rdi
+000000000a0001fd:000000000c007fd8:0000000000000200: 41 55                   push %r13
+000000000a000204:000000000c007fd8:0000000000000200: 48 c7 c0 19 45 00 00    mov $0x4519, %rax
+000000000a000208:000000000c007fd8:0000000000000200: 66 0f ef c0             pxor %xmm0, %xmm0
+000000000a00020d:000000000c007fd8:0000000000000200: f3 48 0f 2a c0          cvtsi2ss %rax, %xmm0
+000000000a000211:000000000c007fd8:0000000000000200: f3 0f 51 c8             sqrtss %xmm0, %xmm1
 000000000a000214:000000000c007fd8:0000000000000300: 0f 2f c8                comiss %xmm0, %xmm1
 000000000a000216:000000000c007fd8:0000000000000300: 74 e5                   jz 0xa0001fb
 000000000a00021b:000000000c007fd8:0000000000000300: f3 48 0f 2c c1          cvttss2si %xmm1, %rax
--- example_12.out	2024-11-18 06:34:58.564876573 +0000
+++ example_12.exp	1970-01-01 00:00:01.000000000 +0000
@@ -7,16 +7,16 @@
 0000000000000600:0000000000000008:8877665544332211: 49 83 e8 08             sub $0x8, %r8
 ffffffffffff9600:8877665544332209:000000008d83851b: 4d 29 c2                sub %r8, %r10
 0000000000000700:778899ab49506312:0000000000000000: 49 f7 ea                imul %r10
-0000000000000701:00000000a5a5a5a5:778899ab49506312: 4d 0f af d3             imul %r11, %r10
-0000000000000701:0000000000000077:00000000a5a5a5a5: 4d 6b d3 77             imul $0x77, %r11, %r10
-0000000000000600:00000000000000fe:2d9bfa6b1014f832: 48 25 fe 00 00 00       and $0xfe, %rax
+0000000000000301:00000000a5a5a5a5:778899ab49506312: 4d 0f af d3             imul %r11, %r10
+ffffffffffff8701:0000000000000077:00000000a5a5a5a5: 4d 6b d3 77             imul $0x77, %r11, %r10
+0000000000000200:00000000000000fe:2d9bfa6b1014f832: 48 25 fe 00 00 00       and $0xfe, %rax
 0000000000000200:0000000000000032:8877665544332211: 48 21 c3                and %rax, %rbx
 0000000000000200:0000000000000013:0000000000000010: 48 83 cb 13             or $0x13, %rbx
 0000000000000200:ffffffffffff8889:0000000000000013: 48 09 cb                or %rcx, %rbx
 ffffffffffff8200:0000000000007776:0000000000000000: 48 f7 d9                neg %rcx
 ffffffffffff9300:0000000000000007:0000000061616161: 48 c1 e7 07             shl $0x7, %rdi
-0000000000001200:0000000000000003:00000030b0b0b080: 48 c1 ff 03             sar $0x3, %rdi
-0000000000001200:0000000000000000:0000000000000000: 0f 2f c8                comiss %xmm0, %xmm1
+0000000000000200:0000000000000003:00000030b0b0b080: 48 c1 ff 03             sar $0x3, %rdi
+0000000000000200:0000000000000000:0000000000000000: 0f 2f c8                comiss %xmm0, %xmm1
 0000000000000300:0000000000000085:0000000000000085: 48 3d 85 00 00 00       cmp $0x85, %rax
 0000000000004600:0000000000000000:0000000000000000: 48 85 c0                test %rax, %rax
 0000000000004600:0000000050505050:0000000050505050: 31 f6                   xor %esi, %esi
--- rip_rsp_rflags.out	2024-11-18 06:34:58.892878444 +0000
+++ rip_rsp_rflags.exp	1970-01-01 00:00:01.000000000 +0000
@@ -40,22 +40,22 @@
 000000000a0001cb:000000000c007fe0:0000000000000600: 49 83 e8 08             sub $0x8, %r8
 000000000a0001cf:000000000c007fe0:ffffffffffff9600: 4d 29 c2                sub %r8, %r10
 000000000a0001d2:000000000c007fe0:0000000000000700: 49 f7 ea                imul %r10
-000000000a0001d5:000000000c007fe0:0000000000000701: 4d 0f af d3             imul %r11, %r10
-000000000a0001d9:000000000c007fe0:0000000000000701: 4d 6b d3 77             imul $0x77, %r11, %r10
-000000000a0001dd:000000000c007fe0:0000000000000600: 48 25 fe 00 00 00       and $0xfe, %rax
+000000000a0001d5:000000000c007fe0:0000000000000301: 4d 0f af d3             imul %r11, %r10
+000000000a0001d9:000000000c007fe0:ffffffffffff8701: 4d 6b d3 77             imul $0x77, %r11, %r10
+000000000a0001dd:000000000c007fe0:0000000000000200: 48 25 fe 00 00 00       and $0xfe, %rax
 000000000a0001e3:000000000c007fe0:0000000000000200: 48 21 c3                and %rax, %rbx
 000000000a0001e6:000000000c007fe0:0000000000000200: 48 83 cb 13             or $0x13, %rbx
 000000000a0001ea:000000000c007fe0:0000000000000200: 48 09 cb                or %rcx, %rbx
 000000000a0001ed:000000000c007fe0:ffffffffffff8200: 48 f7 d1                not %rcx
 000000000a0001f0:000000000c007fe0:ffffffffffff8200: 48 f7 d9                neg %rcx
 000000000a0001f3:000000000c007fe0:ffffffffffff9300: 48 c1 e7 07             shl $0x7, %rdi
-000000000a0001f7:000000000c007fe0:0000000000001200: 48 c1 ff 03             sar $0x3, %rdi
-000000000a0001fb:000000000c007fe0:0000000000001200: 41 55                   push %r13
-000000000a0001fd:000000000c007fd8:0000000000001200: 48 c7 c0 19 45 00 00    mov $0x4519, %rax
-000000000a000204:000000000c007fd8:0000000000001200: 66 0f ef c0             pxor %xmm0, %xmm0
-000000000a000208:000000000c007fd8:0000000000001200: f3 48 0f 2a c0          cvtsi2ss %rax, %xmm0
-000000000a00020d:000000000c007fd8:0000000000001200: f3 0f 51 c8             sqrtss %xmm0, %xmm1
-000000000a000211:000000000c007fd8:0000000000001200: 0f 2f c8                comiss %xmm0, %xmm1
+000000000a0001f7:000000000c007fe0:0000000000000200: 48 c1 ff 03             sar $0x3, %rdi
+000000000a0001fb:000000000c007fe0:0000000000000200: 41 55                   push %r13
+000000000a0001fd:000000000c007fd8:0000000000000200: 48 c7 c0 19 45 00 00    mov $0x4519, %rax
+000000000a000204:000000000c007fd8:0000000000000200: 66 0f ef c0             pxor %xmm0, %xmm0
+000000000a000208:000000000c007fd8:0000000000000200: f3 48 0f 2a c0          cvtsi2ss %rax, %xmm0
+000000000a00020d:000000000c007fd8:0000000000000200: f3 0f 51 c8             sqrtss %xmm0, %xmm1
+000000000a000211:000000000c007fd8:0000000000000200: 0f 2f c8                comiss %xmm0, %xmm1
 000000000a000214:000000000c007fd8:0000000000000300: 74 e5                   jz 0xa0001fb
 000000000a000216:000000000c007fd8:0000000000000300: f3 48 0f 2c c1          cvttss2si %xmm1, %rax
 000000000a00021b:000000000c007fd8:0000000000000300: 48 3d 85 00 00 00       cmp $0x85, %rax
--- xmm.out	2024-11-18 06:34:59.024879197 +0000
+++ xmm.exp	1970-01-01 00:00:01.000000000 +0000
@@ -1,6 +1,6 @@
-000000000a000204:0000000000004519:0000000000001200: 66 0f ef c0             pxor %xmm0, %xmm0
-000000000a000208:0000000000004519:0000000000001200: f3 48 0f 2a c0          cvtsi2ss %rax, %xmm0
-000000000a00020d:0000000000004519:0000000000001200: f3 0f 51 c8             sqrtss %xmm0, %xmm1
-000000000a000211:0000000000004519:0000000000001200: 0f 2f c8                comiss %xmm0, %xmm1
+000000000a000204:0000000000004519:0000000000000200: 66 0f ef c0             pxor %xmm0, %xmm0
+000000000a000208:0000000000004519:0000000000000200: f3 48 0f 2a c0          cvtsi2ss %rax, %xmm0
+000000000a00020d:0000000000004519:0000000000000200: f3 0f 51 c8             sqrtss %xmm0, %xmm1
+000000000a000211:0000000000004519:0000000000000200: 0f 2f c8                comiss %xmm0, %xmm1
 000000000a000216:0000000000004519:0000000000000300: f3 48 0f 2c c1          cvttss2si %xmm1, %rax
 PASSED

Is this expected across different microarchitectures?

[GJDuck]

Is this expected across different microarchitectures?

Good question.

The rflags is not really the contents of the %rflags register (since it is slow to get this value), but the value determined by:

seto   %al
lahf

So the lower byte (%al) will be set to OF, the next byte (%ah) set to SF:ZF:0:AF:0:PF:1:CF, and the rest of the bytes unchanged. I was expecting the upper bytes to be unchanged between CPUs/systems, but apparently this is not the case. Which CPU is this?

[McSinyx]

Thanks for the details! The pasted test output were generated on AMD Ryzen 7 3700X. I also have a AMD Ryzen 5 5600 at home which I recall to also have passed the test suite with that diff applied but I will try again soon just to be sure.

[GJDuck]

Likely, the differing bits are "undefined", and can be different values on different CPUs. I have not investigated thoroughly.

[McSinyx]

That is certainly the case for e.g. SF, ZF, AF and PF after IMUL. I've modified GH-92 to ignore the tests failing here by default for automated testing to not fail.

[GJDuck]

This & other regtest issues should hopefully be fixed now.

[McSinyx]

Thanks, the mentioned tests now pass on my machines. May I ask why the following doesn't make use of test/regtest/bad.csv like the others, though? It doesn't include 0xa000211 but that's not part of test/regtest/after.exp either.

e9patch/test/regtest/after.in

Line 1 in 061f8dd

./test -M 'not addr in {0xa0001d2,0xa0001d5,0xa0001d9,0xa0001f3,0xa0001f7,0xa0001fb,0xa0001fd,0xa000204,0xa000208,0xa00020d}' -P 'after entry(rip,rsp,flags,bytes,size,asm)@inst'

[GJDuck]

I did that one first, before creating bad.csv. It is fine to use different methods in a test suite. Can't comment on 0xa000211, maybe a mistake, but it does not really matter.

[McSinyx]

Cool, I was wondering if there was any semantic difference between not addr in and !defined.