Request for io_pin_order.yaml for FABulous tiles

[Guha37]

Hello,
I have generated the FPGA fabric successfully. I plan to run the tile hardening flow using a TSMC 65nm PDK instead of the default open PDK flow.

Could you please share the io_pin_order.yaml file for all the tiles, so that I can ensure correct IO pin alignment when generating the tile macros?

Thank you.

[KelvinChung2000]

The io_pin_order.yaml is generated by the tool itself. There is no way to generate that file directly right now. I will later add a command to do so. But for now, you can just use one of the open PDKs to generate the file, or use the Python API and call gen_io_pin_order_config to generate the file. However, the pin order file will not help you with the correct alignment.

The only job of that file is to specify the pin order, but it will not align the pins for you. You will need a custom pin-placement script to handle alignment if you plan to use a proprietary EDA tool. However, if you are planning to use Openroad for hardening, one option is to bring up the PDK so it works in librelane, and with that, all the hardening automation is already done for you.