diff --git a/library/SubcircuitLibrary/4_and/SN74LS76A/SN74LS76A.pro b/library/SubcircuitLibrary/4_and/SN74LS76A/SN74LS76A.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/4_and/SN74LS76A/SN74LS76A.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/4_and/SN74LS76A/SN74LS76A.proj b/library/SubcircuitLibrary/4_and/SN74LS76A/SN74LS76A.proj
new file mode 100644
index 000000000..aad6010f6
--- /dev/null
+++ b/library/SubcircuitLibrary/4_and/SN74LS76A/SN74LS76A.proj
@@ -0,0 +1 @@
+schematicFile SN74LS76A.sch
diff --git a/library/SubcircuitLibrary/SN74AUP1G99.zip b/library/SubcircuitLibrary/SN74AUP1G99.zip
new file mode 100644
index 000000000..a58f206c0
Binary files /dev/null and b/library/SubcircuitLibrary/SN74AUP1G99.zip differ
diff --git a/library/SubcircuitLibrary/SN74HC14/SN74HC14.pro b/library/SubcircuitLibrary/SN74HC14/SN74HC14.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC14/SN74HC14.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74HC14/SN74HC14.proj b/library/SubcircuitLibrary/SN74HC14/SN74HC14.proj
new file mode 100644
index 000000000..9f50a9e9f
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC14/SN74HC14.proj
@@ -0,0 +1 @@
+schematicFile SN74HC14.sch
diff --git a/library/SubcircuitLibrary/SN74LS697/SN74LS697.proj b/library/SubcircuitLibrary/SN74LS697/SN74LS697.proj
new file mode 100644
index 000000000..1ccf1f20b
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS697/SN74LS697.proj
@@ -0,0 +1 @@
+schematicFile SN74LS697.sch
diff --git a/library/SubcircuitLibrary/TL074/SN74LS75/SN74LS75.proj b/library/SubcircuitLibrary/TL074/SN74LS75/SN74LS75.proj
new file mode 100644
index 000000000..699eeab14
--- /dev/null
+++ b/library/SubcircuitLibrary/TL074/SN74LS75/SN74LS75.proj
@@ -0,0 +1 @@
+schematicFile SN74LS75.sch
diff --git a/library/SubcircuitLibrary/TL431_SUB/SN54S182/SN54S182.proj b/library/SubcircuitLibrary/TL431_SUB/SN54S182/SN54S182.proj
new file mode 100644
index 000000000..0bff4de3b
--- /dev/null
+++ b/library/SubcircuitLibrary/TL431_SUB/SN54S182/SN54S182.proj
@@ -0,0 +1 @@
+schematicFile SN54S182.sch
diff --git a/library/SubcircuitLibrary/TL431_SUB/SN74159/SN74159.proj b/library/SubcircuitLibrary/TL431_SUB/SN74159/SN74159.proj
new file mode 100644
index 000000000..8ff775798
--- /dev/null
+++ b/library/SubcircuitLibrary/TL431_SUB/SN74159/SN74159.proj
@@ -0,0 +1 @@
+schematicFile SN74159.sch
diff --git a/library/SubcircuitLibrary/TL431_SUB/SN74HC4020/SN74HC4020.proj b/library/SubcircuitLibrary/TL431_SUB/SN74HC4020/SN74HC4020.proj
new file mode 100644
index 000000000..c2a758cb7
--- /dev/null
+++ b/library/SubcircuitLibrary/TL431_SUB/SN74HC4020/SN74HC4020.proj
@@ -0,0 +1 @@
+schematicFile SN74HC4020.sch
diff --git a/library/SubcircuitLibrary/TL431_SUB/SN74LS147/SN74LS147.proj b/library/SubcircuitLibrary/TL431_SUB/SN74LS147/SN74LS147.proj
new file mode 100644
index 000000000..7d2c8133c
--- /dev/null
+++ b/library/SubcircuitLibrary/TL431_SUB/SN74LS147/SN74LS147.proj
@@ -0,0 +1 @@
+schematicFile SN74LS147.sch
diff --git a/library/SubcircuitLibrary/TL431_SUB/SN74LVC8T245/SN74LVC8T245.proj b/library/SubcircuitLibrary/TL431_SUB/SN74LVC8T245/SN74LVC8T245.proj
new file mode 100644
index 000000000..011093a0d
--- /dev/null
+++ b/library/SubcircuitLibrary/TL431_SUB/SN74LVC8T245/SN74LVC8T245.proj
@@ -0,0 +1 @@
+schematicFile SN74LVC8T245.sch
diff --git a/library/SubcircuitLibrary/TL783/SN74ALS8161/SN74ALS8161.proj b/library/SubcircuitLibrary/TL783/SN74ALS8161/SN74ALS8161.proj
new file mode 100644
index 000000000..45f35f1f9
--- /dev/null
+++ b/library/SubcircuitLibrary/TL783/SN74ALS8161/SN74ALS8161.proj
@@ -0,0 +1 @@
+schematicFile SN74ALS8161.sch
diff --git a/library/SubcircuitLibrary/TL783/SN74LVC1G57/SN74LVC1G57.proj b/library/SubcircuitLibrary/TL783/SN74LVC1G57/SN74LVC1G57.proj
new file mode 100644
index 000000000..11a662e07
--- /dev/null
+++ b/library/SubcircuitLibrary/TL783/SN74LVC1G57/SN74LVC1G57.proj
@@ -0,0 +1 @@
+schematicFile SN74LVC1G57.sch
diff --git a/library/SubcircuitLibrary/TLC2272/CD74HC238/3_and-cache.lib b/library/SubcircuitLibrary/TLC2272/CD74HC238/3_and-cache.lib
new file mode 100644
index 000000000..af0586415
--- /dev/null
+++ b/library/SubcircuitLibrary/TLC2272/CD74HC238/3_and-cache.lib
@@ -0,0 +1,61 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/TLC2272/CD74HC238/3_and.cir b/library/SubcircuitLibrary/TLC2272/CD74HC238/3_and.cir
new file mode 100644
index 000000000..ba296cf01
--- /dev/null
+++ b/library/SubcircuitLibrary/TLC2272/CD74HC238/3_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
+U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/TLC2272/CD74HC238/3_and.cir.out b/library/SubcircuitLibrary/TLC2272/CD74HC238/3_and.cir.out
new file mode 100644
index 000000000..d7cf79a07
--- /dev/null
+++ b/library/SubcircuitLibrary/TLC2272/CD74HC238/3_and.cir.out
@@ -0,0 +1,20 @@
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/TLC2272/CD74HC238/3_and.pro b/library/SubcircuitLibrary/TLC2272/CD74HC238/3_and.pro
new file mode 100644
index 000000000..00597a5ad
--- /dev/null
+++ b/library/SubcircuitLibrary/TLC2272/CD74HC238/3_and.pro
@@ -0,0 +1,43 @@
+update=05/31/19 15:26:09
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_User
+LibName9=eSim_Sources
+LibName10=eSim_Subckt
diff --git a/library/SubcircuitLibrary/TLC2272/CD74HC238/3_and.sch b/library/SubcircuitLibrary/TLC2272/CD74HC238/3_and.sch
new file mode 100644
index 000000000..d6ac89f95
--- /dev/null
+++ b/library/SubcircuitLibrary/TLC2272/CD74HC238/3_and.sch
@@ -0,0 +1,130 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:3_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60 0000 C CNN
+F 1 "d_and" H 4300 2800 60 0000 C CNN
+F 2 "" H 4250 2700 60 0000 C CNN
+F 3 "" H 4250 2700 60 0000 C CNN
+ 1 4250 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60 0000 C CNN
+F 1 "d_and" H 5200 3000 60 0000 C CNN
+F 2 "" H 5150 2900 60 0000 C CNN
+F 3 "" H 5150 2900 60 0000 C CNN
+ 1 5150 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30 0000 C CNN
+F 1 "PORT" H 3050 2600 30 0000 C CNN
+F 2 "" H 3050 2600 60 0000 C CNN
+F 3 "" H 3050 2600 60 0000 C CNN
+ 1 3050 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30 0000 C CNN
+F 1 "PORT" H 3050 2800 30 0000 C CNN
+F 2 "" H 3050 2800 60 0000 C CNN
+F 3 "" H 3050 2800 60 0000 C CNN
+ 2 3050 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30 0000 C CNN
+F 1 "PORT" H 3050 3100 30 0000 C CNN
+F 2 "" H 3050 3100 60 0000 C CNN
+F 3 "" H 3050 3100 60 0000 C CNN
+ 3 3050 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30 0000 C CNN
+F 1 "PORT" H 6900 2850 30 0000 C CNN
+F 2 "" H 6900 2850 60 0000 C CNN
+F 3 "" H 6900 2850 60 0000 C CNN
+ 4 6900 2850
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4700 2650 4700 2800
+Wire Wire Line
+ 5600 2850 6650 2850
+Wire Wire Line
+ 3800 2600 3300 2600
+Wire Wire Line
+ 3800 2700 3300 2700
+Wire Wire Line
+ 3300 2700 3300 2800
+Wire Wire Line
+ 3300 3100 4700 3100
+Wire Wire Line
+ 4700 3100 4700 2900
+Text Notes 3500 2600 0 60 ~ 12
+in1
+Text Notes 3450 2800 0 60 ~ 12
+in2\n
+Text Notes 3500 3100 0 60 ~ 12
+in3
+Text Notes 6100 2850 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/TLC2272/CD74HC238/3_and.sub b/library/SubcircuitLibrary/TLC2272/CD74HC238/3_and.sub
new file mode 100644
index 000000000..3d9120bb6
--- /dev/null
+++ b/library/SubcircuitLibrary/TLC2272/CD74HC238/3_and.sub
@@ -0,0 +1,14 @@
+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/TLC2272/CD74HC238/3_and_Previous_Values.xml b/library/SubcircuitLibrary/TLC2272/CD74HC238/3_and_Previous_Values.xml
new file mode 100644
index 000000000..abc5faaae
--- /dev/null
+++ b/library/SubcircuitLibrary/TLC2272/CD74HC238/3_and_Previous_Values.xml
@@ -0,0 +1 @@
+d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/TLC2272/CD74HC238/CD74HC238-cache.lib b/library/SubcircuitLibrary/TLC2272/CD74HC238/CD74HC238-cache.lib
new file mode 100644
index 000000000..08f5b6f59
--- /dev/null
+++ b/library/SubcircuitLibrary/TLC2272/CD74HC238/CD74HC238-cache.lib
@@ -0,0 +1,109 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and
+#
+DEF 3_and X 0 40 Y Y 1 F N
+F0 "X" 100 -50 60 H V C CNN
+F1 "3_and" 150 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 150 50 158 716 -716 0 1 0 N 200 200 200 -100
+P 2 0 1 0 -150 200 200 200 N
+P 3 0 1 0 -150 200 -150 -100 200 -100 N
+X in1 1 -350 150 200 R 50 50 1 1 I
+X in2 2 -350 50 200 R 50 50 1 1 I
+X in3 3 -350 -50 200 R 50 50 1 1 I
+X out 4 500 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# INVCMOS
+#
+DEF INVCMOS X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "INVCMOS" -450 150 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+C 400 0 112 0 1 0 N
+S -250 200 -250 -200 0 1 0 N
+P 3 0 1 0 -250 200 300 0 -250 -200 N
+X in 1 -450 0 200 R 50 50 1 1 P
+X out 2 700 0 200 L 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_buffer
+#
+DEF d_buffer U 0 40 Y Y 1 F N
+F0 "U" 0 -50 60 H V C CNN
+F1 "d_buffer" 0 50 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N
+X IN 1 -500 0 200 R 50 50 1 1 I
+X OUT 2 650 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/TLC2272/CD74HC238/CD74HC238.cir b/library/SubcircuitLibrary/TLC2272/CD74HC238/CD74HC238.cir
new file mode 100644
index 000000000..5dc59774d
--- /dev/null
+++ b/library/SubcircuitLibrary/TLC2272/CD74HC238/CD74HC238.cir
@@ -0,0 +1,45 @@
+* D:\eSimWorkspace\CD74HC238\CD74HC238.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/20/25 16:21:10
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_buffer
+U3 Net-_U1-Pad2_ Net-_U3-Pad2_ d_buffer
+U4 Net-_U1-Pad3_ Net-_U4-Pad2_ d_buffer
+X1 Net-_U1-Pad4_ Net-_X1-Pad2_ INVCMOS
+X2 Net-_U1-Pad5_ Net-_X2-Pad2_ INVCMOS
+U5 Net-_U1-Pad6_ Net-_U5-Pad2_ d_buffer
+X4 Net-_U2-Pad2_ Net-_X11-Pad1_ INVCMOS
+X5 Net-_U3-Pad2_ Net-_X11-Pad2_ INVCMOS
+X6 Net-_U4-Pad2_ Net-_X10-Pad3_ INVCMOS
+X3 Net-_X1-Pad2_ Net-_X2-Pad2_ Net-_U5-Pad2_ Net-_U10-Pad2_ 3_and
+X7 Net-_X11-Pad1_ Net-_X11-Pad2_ Net-_X10-Pad3_ Net-_U6-Pad1_ 3_and
+X8 Net-_U2-Pad2_ Net-_X11-Pad2_ Net-_X10-Pad3_ Net-_U7-Pad1_ 3_and
+X9 Net-_X11-Pad1_ Net-_U3-Pad2_ Net-_X10-Pad3_ Net-_U8-Pad1_ 3_and
+X10 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_X10-Pad3_ Net-_U9-Pad1_ 3_and
+X11 Net-_X11-Pad1_ Net-_X11-Pad2_ Net-_U4-Pad2_ Net-_U10-Pad1_ 3_and
+X12 Net-_U2-Pad2_ Net-_X11-Pad2_ Net-_U4-Pad2_ Net-_U12-Pad1_ 3_and
+X13 Net-_X11-Pad1_ Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U13-Pad1_ 3_and
+X14 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U11-Pad1_ 3_and
+U6 Net-_U6-Pad1_ Net-_U10-Pad2_ Net-_U14-Pad1_ d_and
+U7 Net-_U7-Pad1_ Net-_U10-Pad2_ Net-_U15-Pad1_ d_and
+U8 Net-_U8-Pad1_ Net-_U10-Pad2_ Net-_U16-Pad1_ d_and
+U9 Net-_U9-Pad1_ Net-_U10-Pad2_ Net-_U17-Pad1_ d_and
+U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_and
+U12 Net-_U12-Pad1_ Net-_U10-Pad2_ Net-_U12-Pad3_ d_and
+U13 Net-_U13-Pad1_ Net-_U10-Pad2_ Net-_U13-Pad3_ d_and
+U11 Net-_U11-Pad1_ Net-_U10-Pad2_ Net-_U11-Pad3_ d_and
+U14 Net-_U14-Pad1_ Net-_U1-Pad15_ d_buffer
+U15 Net-_U15-Pad1_ Net-_U1-Pad14_ d_buffer
+U16 Net-_U16-Pad1_ Net-_U1-Pad13_ d_buffer
+U17 Net-_U17-Pad1_ Net-_U1-Pad12_ d_buffer
+U18 Net-_U10-Pad3_ Net-_U1-Pad11_ d_buffer
+U19 Net-_U12-Pad3_ Net-_U1-Pad10_ d_buffer
+U20 Net-_U13-Pad3_ Net-_U1-Pad9_ d_buffer
+U21 Net-_U11-Pad3_ Net-_U1-Pad7_ d_buffer
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT
+
+.end
diff --git a/library/SubcircuitLibrary/TLC2272/CD74HC238/CD74HC238.cir.out b/library/SubcircuitLibrary/TLC2272/CD74HC238/CD74HC238.cir.out
new file mode 100644
index 000000000..cda1ab41b
--- /dev/null
+++ b/library/SubcircuitLibrary/TLC2272/CD74HC238/CD74HC238.cir.out
@@ -0,0 +1,108 @@
+* d:\esimworkspace\cd74hc238\cd74hc238.cir
+
+.include 3_and.sub
+.include INVCMOS.sub
+* u2 net-_u1-pad1_ net-_u2-pad2_ d_buffer
+* u3 net-_u1-pad2_ net-_u3-pad2_ d_buffer
+* u4 net-_u1-pad3_ net-_u4-pad2_ d_buffer
+x1 net-_u1-pad6_ net-_x1-pad2_ INVCMOS
+x2 net-_u1-pad4_ net-_x2-pad2_ INVCMOS
+* u5 net-_u1-pad5_ net-_u5-pad2_ d_buffer
+x4 net-_u2-pad2_ net-_x11-pad1_ INVCMOS
+x5 net-_u3-pad2_ net-_x11-pad2_ INVCMOS
+x6 net-_u4-pad2_ net-_x10-pad3_ INVCMOS
+x3 net-_x1-pad2_ net-_x2-pad2_ net-_u5-pad2_ net-_u10-pad2_ 3_and
+x7 net-_x11-pad1_ net-_x11-pad2_ net-_x10-pad3_ net-_u6-pad1_ 3_and
+x8 net-_u2-pad2_ net-_x11-pad2_ net-_x10-pad3_ net-_u7-pad1_ 3_and
+x9 net-_x11-pad1_ net-_u3-pad2_ net-_x10-pad3_ net-_u8-pad1_ 3_and
+x10 net-_u2-pad2_ net-_u3-pad2_ net-_x10-pad3_ net-_u9-pad1_ 3_and
+x11 net-_x11-pad1_ net-_x11-pad2_ net-_u4-pad2_ net-_u10-pad1_ 3_and
+x12 net-_u2-pad2_ net-_x11-pad2_ net-_u4-pad2_ net-_u12-pad1_ 3_and
+x13 net-_x11-pad1_ net-_u3-pad2_ net-_u4-pad2_ net-_u13-pad1_ 3_and
+x14 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u11-pad1_ 3_and
+* u6 net-_u6-pad1_ net-_u10-pad2_ net-_u14-pad1_ d_and
+* u7 net-_u7-pad1_ net-_u10-pad2_ net-_u15-pad1_ d_and
+* u8 net-_u8-pad1_ net-_u10-pad2_ net-_u16-pad1_ d_and
+* u9 net-_u9-pad1_ net-_u10-pad2_ net-_u17-pad1_ d_and
+* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and
+* u12 net-_u12-pad1_ net-_u10-pad2_ net-_u12-pad3_ d_and
+* u13 net-_u13-pad1_ net-_u10-pad2_ net-_u13-pad3_ d_and
+* u11 net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_and
+* u14 net-_u14-pad1_ net-_u1-pad7_ d_buffer
+* u15 net-_u15-pad1_ net-_u1-pad8_ d_buffer
+* u16 net-_u16-pad1_ net-_u1-pad9_ d_buffer
+* u17 net-_u17-pad1_ net-_u1-pad14_ d_buffer
+* u18 net-_u10-pad3_ net-_u1-pad10_ d_buffer
+* u19 net-_u12-pad3_ net-_u1-pad11_ d_buffer
+* u20 net-_u13-pad3_ net-_u1-pad12_ d_buffer
+* u21 net-_u11-pad3_ net-_u1-pad13_ d_buffer
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port
+a1 net-_u1-pad1_ net-_u2-pad2_ u2
+a2 net-_u1-pad2_ net-_u3-pad2_ u3
+a3 net-_u1-pad3_ net-_u4-pad2_ u4
+a4 net-_u1-pad5_ net-_u5-pad2_ u5
+a5 [net-_u6-pad1_ net-_u10-pad2_ ] net-_u14-pad1_ u6
+a6 [net-_u7-pad1_ net-_u10-pad2_ ] net-_u15-pad1_ u7
+a7 [net-_u8-pad1_ net-_u10-pad2_ ] net-_u16-pad1_ u8
+a8 [net-_u9-pad1_ net-_u10-pad2_ ] net-_u17-pad1_ u9
+a9 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a10 [net-_u12-pad1_ net-_u10-pad2_ ] net-_u12-pad3_ u12
+a11 [net-_u13-pad1_ net-_u10-pad2_ ] net-_u13-pad3_ u13
+a12 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11
+a13 net-_u14-pad1_ net-_u1-pad7_ u14
+a14 net-_u15-pad1_ net-_u1-pad8_ u15
+a15 net-_u16-pad1_ net-_u1-pad9_ u16
+a16 net-_u17-pad1_ net-_u1-pad14_ u17
+a17 net-_u10-pad3_ net-_u1-pad10_ u18
+a18 net-_u12-pad3_ net-_u1-pad11_ u19
+a19 net-_u13-pad3_ net-_u1-pad12_ u20
+a20 net-_u11-pad3_ net-_u1-pad13_ u21
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u2 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u3 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u4 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u5 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u14 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u15 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u16 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u17 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u18 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u19 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u20 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u21 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 1e-06 10e-03 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/TLC2272/CD74HC238/CD74HC238.dcm b/library/SubcircuitLibrary/TLC2272/CD74HC238/CD74HC238.dcm
new file mode 100644
index 000000000..1980d0d11
--- /dev/null
+++ b/library/SubcircuitLibrary/TLC2272/CD74HC238/CD74HC238.dcm
@@ -0,0 +1,7 @@
+EESchema-DOCLIB Version 2.0
+#
+$CMP SCR
+D Thyristor
+$ENDCMP
+#
+#End Doc Library
diff --git a/library/SubcircuitLibrary/TLC2272/CD74HC238/CD74HC238.lib b/library/SubcircuitLibrary/TLC2272/CD74HC238/CD74HC238.lib
new file mode 100644
index 000000000..cc8e79430
--- /dev/null
+++ b/library/SubcircuitLibrary/TLC2272/CD74HC238/CD74HC238.lib
@@ -0,0 +1,707 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 10bitDAC
+#
+DEF 10bitDAC X 0 40 Y Y 1 F N
+F0 "X" 0 50 60 H V C CNN
+F1 "10bitDAC" -50 -50 60 H V C CNN
+F2 "" 0 50 60 H I C CNN
+F3 "" 0 50 60 H I C CNN
+DRAW
+S -500 500 400 -600 0 1 0 N
+X D0 1 -700 -500 200 R 50 50 1 1 I
+X D1 2 -700 -400 200 R 50 50 1 1 I
+X D2 3 -700 -300 200 R 50 50 1 1 I
+X D3 4 -700 -200 200 R 50 50 1 1 I
+X D4 5 -700 -100 200 R 50 50 1 1 I
+X D5 6 -700 0 200 R 50 50 1 1 I
+X D6 7 -700 100 200 R 50 50 1 1 I
+X D7 8 -700 200 200 R 50 50 1 1 I
+X D8 9 -700 300 200 R 50 50 1 1 I
+X D9 10 -700 400 200 R 50 50 1 1 I
+X AnalogOut 11 600 350 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 2BITMUL
+#
+DEF 2BITMUL X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "2BITMUL" 0 0 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -300 400 300 -400 0 1 0 N
+X A0 1 -500 300 200 R 50 50 1 1 I
+X A1 2 -500 150 200 R 50 50 1 1 I
+X B0 3 -500 -50 200 R 50 50 1 1 I
+X B1 4 -500 -250 200 R 50 50 1 1 I
+X M0 5 500 250 200 L 50 50 1 1 O
+X M1 6 500 100 200 L 50 50 1 1 O
+X M2 7 500 -50 200 L 50 50 1 1 O
+X M3 8 500 -250 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 3_and
+#
+DEF 3_and X 0 40 Y Y 1 F N
+F0 "X" 100 -50 60 H V C CNN
+F1 "3_and" 150 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 150 50 158 716 -716 0 1 0 N 200 200 200 -100
+P 2 0 1 0 -150 200 200 200 N
+P 3 0 1 0 -150 200 -150 -100 200 -100 N
+X in1 1 -350 150 200 R 50 50 1 1 I
+X in2 2 -350 50 200 R 50 50 1 1 I
+X in3 3 -350 -50 200 R 50 50 1 1 I
+X out 4 500 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 4_OR
+#
+DEF 4_OR X 0 40 Y Y 1 F N
+F0 "X" 150 -100 60 H V C CNN
+F1 "4_OR" 150 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250
+A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0
+A -30 -99 393 627 146 0 1 0 N 150 250 350 0
+P 2 0 1 0 -200 -250 150 -250 N
+P 2 0 1 0 -200 250 150 250 N
+X in1 1 -350 150 200 R 50 50 1 1 I
+X in2 2 -350 50 200 R 50 50 1 1 I
+X in3 3 -350 -50 200 R 50 50 1 1 I
+X in4 4 -350 -150 200 R 50 50 1 1 I
+X out 5 550 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 4_and
+#
+DEF 4_and X 0 40 Y Y 1 F N
+F0 "X" 50 -50 60 H V C CNN
+F1 "4_and" 100 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 100 0 206 760 -760 0 1 0 N 150 200 150 -200
+P 2 0 1 0 -200 200 150 200 N
+P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N
+X in1 1 -400 150 200 R 50 50 1 1 I
+X in2 2 -400 50 200 R 50 50 1 1 I
+X in3 3 -400 -50 200 R 50 50 1 1 I
+X in4 4 -400 -150 200 R 50 50 1 1 I
+X out 5 500 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 556
+#
+DEF 556 X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "556" 0 0 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -300 400 250 -550 0 1 0 N
+X dis1 1 -500 150 200 R 50 50 1 1 I
+X thr1 2 -500 -150 200 R 50 50 1 1 I
+X cv1 3 -150 -750 200 U 50 50 1 1 I
+X rst1 4 -200 600 200 D 50 50 1 1 I
+X out1 5 -500 0 200 R 50 50 1 1 O
+X trig1 6 -500 -300 200 R 50 50 1 1 I
+X gnd 7 0 -750 200 U 50 50 1 1 I
+X trig2 8 450 -300 200 L 50 50 1 1 I
+X out2 9 450 0 200 L 50 50 1 1 O
+X rst2 10 100 600 200 D 50 50 1 1 I
+X cv2 11 150 -750 200 U 50 50 1 1 I
+X thr2 12 450 -150 200 L 50 50 1 1 I
+X dis2 13 450 150 200 L 50 50 1 1 I
+X vcc 14 -50 600 200 D 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# 5_and
+#
+DEF 5_and X 0 40 Y Y 1 F N
+F0 "X" 50 -100 60 H V C CNN
+F1 "5_and" 100 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 100 0 255 787 -787 0 1 0 N 150 250 150 -250
+P 2 0 1 0 -250 250 150 250 N
+P 3 0 1 0 -250 250 -250 -250 150 -250 N
+X in1 1 -450 200 200 R 50 50 1 1 I
+X in2 2 -450 100 200 R 50 50 1 1 I
+X in3 3 -450 0 200 R 50 50 1 1 I
+X in4 4 -450 -100 200 R 50 50 1 1 I
+X in5 5 -450 -200 200 R 50 50 1 1 I
+X out 6 550 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# CD74HC238
+#
+DEF CD74HC238 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "CD74HC238" 0 0 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -2950 3700 2900 -3350 1 1 0 N
+X A0 1 -3150 2900 200 R 50 50 1 1 I
+X A1 2 -3150 2100 200 R 50 50 1 1 I
+X A2 3 -3150 1300 200 R 50 50 1 1 I
+X G0_b 4 -3150 550 200 R 50 50 1 1 I
+X G1_b 5 -3150 -300 200 R 50 50 1 1 I
+X G2 6 -3150 -1050 200 R 50 50 1 1 I
+X Y7 7 -3150 -1800 200 R 50 50 1 1 O
+X GND 8 -3150 -2550 200 R 50 50 1 1 O
+X Y6 9 3100 -2550 200 L 50 50 1 1 O
+X Y5 10 3100 -1800 200 L 50 50 1 1 O
+X Y4 11 3100 -1050 200 L 50 50 1 1 O
+X Y3 12 3100 -300 200 L 50 50 1 1 O
+X Y2 13 3100 550 200 L 50 50 1 1 O
+X Y1 14 3100 1250 200 L 50 50 1 1 O
+X Y0 15 3100 2150 200 L 50 50 1 1 O
+X Vcc 16 3100 2900 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# CMOS_NAND
+#
+DEF CMOS_NAND X 0 40 Y Y 1 F N
+F0 "X" -100 -150 60 H V C CNN
+F1 "CMOS_NAND" 0 -50 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+A 150 -50 381 668 -668 0 1 0 N 300 300 300 -400
+C 550 0 50 0 1 0 N
+P 2 0 1 0 -350 300 300 300 N
+P 3 0 1 0 -350 300 -350 -400 300 -400 N
+X in1 1 -550 250 200 R 50 50 1 1 I
+X in2 2 -550 -300 200 R 50 50 1 1 I
+X out 3 800 0 279 L 79 79 1 1 I
+ENDDRAW
+ENDDEF
+#
+# Clock_pulse_generator
+#
+DEF Clock_pulse_generator X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "Clock_pulse_generator" 0 -100 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -550 200 600 -300 0 1 0 N
+X Vdd 1 -750 100 200 R 50 50 1 1 I
+X R 2 -750 -50 200 R 50 50 1 1 I
+X C 3 -750 -200 200 R 50 50 1 1 I
+X Clkout 4 800 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# IC_4002
+#
+DEF IC_4002 X 0 40 Y Y 1 F N
+F0 "X" 0 150 60 H V C CNN
+F1 "IC_4002" 0 0 60 H V C CNN
+F2 "" 50 -150 60 H V C CNN
+F3 "" 50 -150 60 H V C CNN
+DRAW
+S -250 350 250 -400 0 1 0 N
+X 1Y 1 -450 250 200 R 50 50 1 1 O
+X 1A 2 -450 150 200 R 50 50 1 1 I
+X 1B 3 -450 50 200 R 50 50 1 1 I
+X 1C 4 -450 -50 200 R 50 50 1 1 I
+X 1D 5 -450 -150 200 R 50 50 1 1 I
+X NC 6 -450 -250 200 R 50 50 1 1 I
+X GND 7 -450 -350 200 R 50 50 1 1 I
+X NC 8 450 -350 200 L 50 50 1 1 I
+X 2A 9 450 -250 200 L 50 50 1 1 I
+X 2B 10 450 -150 200 L 50 50 1 1 I
+X 2C 11 450 -50 200 L 50 50 1 1 I
+X 2D 12 450 50 200 L 50 50 1 1 I
+X 2Y 13 450 150 200 L 50 50 1 1 O
+X VCC 14 450 250 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# IC_4012
+#
+DEF IC_4012 X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "IC_4012" 0 200 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -300 400 350 -400 0 1 0 N
+X Q1 1 -500 300 200 R 50 50 1 1 O
+X A1 2 -500 200 200 R 50 50 1 1 I
+X B1 3 -500 100 200 R 50 50 1 1 I
+X C1 4 -500 0 200 R 50 50 1 1 I
+X D1 5 -500 -100 200 R 50 50 1 1 I
+X NC 6 -500 -200 200 R 50 50 1 1 N
+X VSS 7 -500 -300 200 R 50 50 1 1 I
+X NC 8 550 -300 200 L 50 50 1 1 N
+X A2 9 550 -200 200 L 50 50 1 1 I
+X B2 10 550 -100 200 L 50 50 1 1 I
+X C2 11 550 0 200 L 50 50 1 1 I
+X D2 12 550 100 200 L 50 50 1 1 I
+X Q2 13 550 200 200 L 50 50 1 1 O
+X VDD 14 550 300 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# IC_4017
+#
+DEF IC_4017 X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "IC_4017" 0 0 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -350 850 400 -850 0 1 0 N
+X 1 1 600 650 200 L 50 50 1 1 O
+X 2 2 600 500 200 L 50 50 1 1 O
+X 3 3 600 350 200 L 50 50 1 1 O
+X 4 4 600 200 200 L 50 50 1 1 O
+X 5 5 600 50 200 L 50 50 1 1 O
+X 6 6 600 -100 200 L 50 50 1 1 O
+X 7 7 600 -250 200 L 50 50 1 1 O
+X 8 8 600 -400 200 L 50 50 1 1 O
+X 9 9 600 -600 200 L 50 50 1 1 O
+X 10 10 600 -750 200 L 50 50 1 1 O
+X RST 11 -550 -400 200 R 50 50 1 1 I
+X CLK 12 -550 350 200 R 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# IC_4023
+#
+DEF IC_4023 X 0 40 Y Y 1 F N
+F0 "X" 0 -100 60 H V C CNN
+F1 "IC_4023" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -300 450 300 -450 0 1 0 N
+X A1 1 -500 300 200 R 50 50 1 1 I
+X B1 2 -500 200 200 R 50 50 1 1 I
+X A2 3 -500 100 200 R 50 50 1 1 I
+X B2 4 -500 0 200 R 50 50 1 1 I
+X C2 5 -500 -100 200 R 50 50 1 1 I
+X Q2 6 -500 -200 200 R 50 50 1 1 O
+X Vss 7 -500 -300 200 R 50 50 1 1 I
+X C1 8 500 -300 200 L 50 50 1 1 I
+X Q1 9 500 -200 200 L 50 50 1 1 O
+X Q3 10 500 -100 200 L 50 50 1 1 O
+X C3 11 500 0 200 L 50 50 1 1 I
+X B3 12 500 100 200 L 50 50 1 1 I
+X A3 13 500 200 200 L 50 50 1 1 I
+X Vdd 14 500 300 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# IC_4028
+#
+DEF IC_4028 X 0 40 Y Y 1 F N
+F0 "X" 0 -100 60 H V C CNN
+F1 "IC_4028" 0 50 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -300 450 300 -450 0 1 0 N
+X Q4 1 -500 350 200 R 50 50 1 1 O
+X Q2 2 -500 250 200 R 50 50 1 1 O
+X Q0 3 -500 150 200 R 50 50 1 1 O
+X Q7 4 -500 50 200 R 50 50 1 1 O
+X Q9 5 -500 -50 200 R 50 50 1 1 O
+X Q5 6 -500 -150 200 R 50 50 1 1 O
+X Q6 7 -500 -250 200 R 50 50 1 1 O
+X Vss 8 -500 -350 200 R 50 50 1 1 I
+X Q8 9 500 -350 200 L 50 50 1 1 O
+X A0 10 500 -250 200 L 50 50 1 1 I
+X A3 11 500 -150 200 L 50 50 1 1 I
+X A2 12 500 -50 200 L 50 50 1 1 I
+X A1 13 500 50 200 L 50 50 1 1 I
+X Q1 14 500 150 200 L 50 50 1 1 O
+X Q3 15 500 250 200 L 50 50 1 1 O
+X Vdd 16 500 350 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# IC_4073
+#
+DEF IC_4073 X 0 40 Y Y 1 F N
+F0 "X" 0 -100 60 H V C CNN
+F1 "IC_4073" 0 50 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -300 400 300 -400 0 1 0 N
+X A1 1 -500 300 200 R 50 50 1 1 I
+X B1 2 -500 200 200 R 50 50 1 1 I
+X A2 3 -500 100 200 R 50 50 1 1 I
+X B2 4 -500 0 200 R 50 50 1 1 I
+X C2 5 -500 -100 200 R 50 50 1 1 I
+X Q2 6 -500 -200 200 R 50 50 1 1 O
+X Vss 7 -500 -300 200 R 50 50 1 1 I
+X C1 8 500 -300 200 L 50 50 1 1 I
+X Q1 9 500 -200 200 L 50 50 1 1 O
+X Q3 10 500 -100 200 L 50 50 1 1 O
+X A3 11 500 0 200 L 50 50 1 1 I
+X B3 12 500 100 200 L 50 50 1 1 I
+X C3 13 500 200 200 L 50 50 1 1 I
+X Vdd 14 500 300 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# IC_74153
+#
+DEF IC_74153 X 0 40 Y Y 1 F N
+F0 "X" 100 50 60 H V C CNN
+F1 "IC_74153" 100 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+T 0 100 -200 60 0 0 0 4:1 Normal 0 C C
+T 0 100 -100 60 0 0 0 DUAL Normal 0 C C
+T 0 100 -300 60 0 0 0 MUX Normal 0 C C
+S -200 500 350 -550 0 1 0 N
+X a0 1 -400 350 200 R 50 50 1 1 I
+X a1 2 -400 250 200 R 50 50 1 1 I
+X a2 3 -400 150 200 R 50 50 1 1 I
+X a3 4 -400 50 200 R 50 50 1 1 I
+X EA 5 0 700 200 D 50 50 1 1 I I
+X b0 6 -400 -150 200 R 50 50 1 1 I
+X b1 7 -400 -250 200 R 50 50 1 1 I
+X b2 8 -400 -350 200 R 50 50 1 1 I
+X b3 9 -400 -450 200 R 50 50 1 1 I
+X EB 10 200 700 200 D 50 50 1 1 I I
+X s1 11 50 -750 200 U 50 50 1 1 I
+X s0 12 150 -750 200 U 50 50 1 1 I
+X ya 13 550 250 200 L 50 50 1 1 O
+X yb 14 550 -300 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# IC_74154
+#
+DEF IC_74154 X 0 40 Y Y 1 F N
+F0 "X" 0 -200 60 H V C CNN
+F1 "IC_74154" 50 -50 60 H V C CNN
+F2 "" 0 50 60 H V C CNN
+F3 "" 0 50 60 H V C CNN
+DRAW
+T 0 0 400 60 0 0 0 4:16~ Normal 0 C C
+T 0 0 250 60 0 0 0 decoder Normal 0 C C
+S -350 700 400 -700 0 0 0 N
+X ~Y0 1 -550 550 200 R 50 50 1 1 O I
+X ~Y1 2 -550 450 200 R 50 50 1 1 O I
+X ~Y2 3 -550 350 200 R 50 50 1 1 O I
+X ~Y3 4 -550 250 200 R 50 50 1 1 O I
+X ~Y4 5 -550 150 200 R 50 50 1 1 O I
+X ~Y5 6 -550 50 200 R 50 50 1 1 O I
+X ~Y6 7 -550 -50 200 R 50 50 1 1 O I
+X ~Y7 8 -550 -150 200 R 50 50 1 1 O I
+X ~Y8 9 -550 -250 200 R 50 50 1 1 O I
+X ~Y9 10 -550 -350 200 R 50 50 1 1 O I
+X A3 20 600 150 200 L 50 50 1 1 I
+X ~Y10 11 -550 -450 200 R 50 50 1 1 O I
+X A2 21 600 250 200 L 50 50 1 1 I
+X GND 12 -550 -550 200 R 50 50 1 1 I
+X A1 22 600 350 200 L 50 50 1 1 I
+X ~Y11 13 600 -550 200 L 50 50 1 1 O I
+X A0 23 600 450 200 L 50 50 1 1 I
+X ~Y12 14 600 -450 200 L 50 50 1 1 O I
+X Vcc 24 600 550 200 L 50 50 1 1 I
+X ~Y13 15 600 -350 200 L 50 50 1 1 O I
+X ~Y14 16 600 -250 200 L 50 50 1 1 O I
+X ~Y15 17 600 -150 200 L 50 50 1 1 O I
+X ~E0 18 600 -50 200 L 50 50 1 1 I I
+X ~E1 19 600 50 200 L 50 50 1 1 I I
+ENDDRAW
+ENDDEF
+#
+# IC_74157
+#
+DEF IC_74157 X 0 40 Y Y 1 F N
+F0 "X" 50 -50 60 H V C CNN
+F1 "IC_74157" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+T 0 50 -300 60 0 0 0 2:1 Normal 0 C C
+T 0 50 -400 60 0 0 0 MUX Normal 0 C C
+T 0 50 -200 60 0 0 0 QUAD Normal 0 C C
+S -350 550 400 -650 0 1 0 N
+X a0 1 -550 450 200 R 50 50 1 1 I
+X a1 2 -550 300 200 R 50 50 1 1 I
+X b0 3 -550 200 200 R 50 50 1 1 I
+X b1 4 -550 100 200 R 50 50 1 1 I
+X c0 5 -550 0 200 R 50 50 1 1 I
+X c1 6 -550 -100 200 R 50 50 1 1 I
+X d0 7 -550 -200 200 R 50 50 1 1 I
+X d1 8 -550 -300 200 R 50 50 1 1 I
+X EN 9 -550 -550 200 R 50 50 1 1 I I
+X S 10 -550 -450 200 R 50 50 1 1 I
+X Yd 11 600 0 200 L 50 50 1 1 O
+X Ya 12 600 300 200 L 50 50 1 1 O
+X Yb 13 600 200 200 L 50 50 1 1 O
+X Yc 14 600 100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# IC_7485
+#
+DEF IC_7485 X 0 40 Y Y 1 F N
+F0 "X" -50 -100 60 H V C CNN
+F1 "IC_7485" -50 50 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+T 0 0 550 60 0 0 0 4~BIT~comparator Normal 0 C C
+S -350 450 400 -400 0 1 0 N
+X AB(in) 3 600 -300 200 L 50 50 1 1 I
+X A3 4 -550 100 200 R 50 50 1 1 I
+X B3 5 -550 -350 200 R 50 50 1 1 I
+X A2 6 -550 200 200 R 50 50 1 1 I
+X B2 7 -550 -250 200 R 50 50 1 1 I
+X A1 8 -550 300 200 R 50 50 1 1 I
+X B1 9 -550 -150 200 R 50 50 1 1 I
+X A0 10 -550 400 200 R 50 50 1 1 I
+X B0 11 -550 -50 200 R 50 50 1 1 I
+X A>B(out) 12 600 350 200 L 50 50 1 1 O
+X A=B(out) 13 600 250 200 L 50 50 1 1 O
+X Ad_bufferd_bufferd_bufferd_bufferd_andd_andd_andd_andd_andd_andd_andd_andd_bufferd_bufferd_bufferd_bufferd_bufferd_bufferd_bufferd_bufferD:\FOSSEE\eSim\library\SubcircuitLibrary\INVCMOSD:\FOSSEE\eSim\library\SubcircuitLibrary\INVCMOSD:\FOSSEE\eSim\library\SubcircuitLibrary\INVCMOSD:\FOSSEE\eSim\library\SubcircuitLibrary\INVCMOSD:\FOSSEE\eSim\library\SubcircuitLibrary\INVCMOSD:\FOSSEE\eSim\library\SubcircuitLibrary\3_andD:\FOSSEE\eSim\library\SubcircuitLibrary\3_andD:\FOSSEE\eSim\library\SubcircuitLibrary\3_andD:\FOSSEE\eSim\library\SubcircuitLibrary\3_andD:\FOSSEE\eSim\library\SubcircuitLibrary\3_andD:\FOSSEE\eSim\library\SubcircuitLibrary\3_andD:\FOSSEE\eSim\library\SubcircuitLibrary\3_andD:\FOSSEE\eSim\library\SubcircuitLibrary\3_andD:\FOSSEE\eSim\library\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes0110secusms
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/TLC2272/CD74HC238/INVCMOS-cache.lib b/library/SubcircuitLibrary/TLC2272/CD74HC238/INVCMOS-cache.lib
new file mode 100644
index 000000000..cc25b0c9d
--- /dev/null
+++ b/library/SubcircuitLibrary/TLC2272/CD74HC238/INVCMOS-cache.lib
@@ -0,0 +1,146 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# DC
+#
+DEF DC v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 w
+X - 2 0 -450 300 U 50 50 1 1 w
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_C
+#
+DEF eSim_C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_C" 25 -100 50 H V L CNN
+F2 "" 38 -150 30 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ C_*
+$ENDFPLIST
+DRAW
+P 2 0 1 20 -80 -30 80 -30 N
+P 2 0 1 20 -80 30 80 30 N
+X ~ 1 0 150 110 D 40 40 1 1 P
+X ~ 2 0 -150 110 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_N
+#
+DEF eSim_MOS_N M 0 0 Y N 1 F N
+F0 "M" 0 -150 50 H V R CNN
+F1 "eSim_MOS_N" 100 -50 50 H V R CNN
+F2 "" 300 -300 29 H V C CNN
+F3 "" 100 -200 60 H V C CNN
+DRAW
+C 150 -200 111 0 1 10 N
+P 2 0 1 10 130 -290 130 -250 N
+P 2 0 1 0 130 -270 200 -270 N
+P 2 0 1 10 130 -220 130 -180 N
+P 2 0 1 0 130 -200 200 -200 N
+P 2 0 1 10 130 -150 130 -110 N
+P 2 0 1 0 130 -130 200 -130 N
+P 2 0 1 0 200 -300 200 -270 N
+P 2 0 1 0 200 -130 200 -100 N
+P 3 0 1 10 110 -275 110 -125 110 -125 N
+P 3 0 1 0 200 -200 300 -200 300 -250 N
+P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F
+X D 1 200 0 100 D 50 50 1 1 P
+X G 2 -100 -200 210 R 50 50 1 1 P
+X S 3 200 -400 100 U 50 50 1 1 P
+X B 4 300 -350 98 U 47 47 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_P
+#
+DEF eSim_MOS_P M 0 0 Y N 1 F N
+F0 "M" -50 50 50 H V R CNN
+F1 "eSim_MOS_P" 50 150 50 H V R CNN
+F2 "" 250 100 29 H V C CNN
+F3 "" 50 0 60 H V C CNN
+DRAW
+C 100 0 111 0 1 10 N
+P 2 0 1 0 80 -70 150 -70 N
+P 2 0 1 10 80 -50 80 -90 N
+P 2 0 1 0 80 0 150 0 N
+P 2 0 1 10 80 20 80 -20 N
+P 2 0 1 0 80 70 150 70 N
+P 2 0 1 10 80 90 80 50 N
+P 2 0 1 0 150 -70 150 -100 N
+P 2 0 1 0 150 100 150 70 N
+P 3 0 1 10 60 75 60 -75 60 -75 N
+P 3 0 1 0 150 0 250 0 250 -50 N
+P 4 0 1 0 140 0 100 -15 100 15 140 0 F
+X D 1 150 200 100 D 50 50 1 1 P
+X G 2 -150 0 210 R 50 50 1 1 P
+X S 3 150 -200 100 U 50 50 1 1 P
+X B 4 250 -150 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/TLC2272/CD74HC238/INVCMOS.cir b/library/SubcircuitLibrary/TLC2272/CD74HC238/INVCMOS.cir
new file mode 100644
index 000000000..44f1df814
--- /dev/null
+++ b/library/SubcircuitLibrary/TLC2272/CD74HC238/INVCMOS.cir
@@ -0,0 +1,15 @@
+* /home/saurabh/Downloads/eSim-1.1.2/src/SubcircuitLibrary/INVCMOS/INVCMOS.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Sun Aug 25 17:34:16 2019
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U1 Net-_M1-Pad2_ Net-_C1-Pad1_ PORT
+M1 Net-_C1-Pad1_ Net-_M1-Pad2_ GND GND eSim_MOS_N
+M2 Net-_M2-Pad1_ Net-_M1-Pad2_ Net-_C1-Pad1_ Net-_M2-Pad1_ eSim_MOS_P
+v1 Net-_M2-Pad1_ GND 5
+C1 Net-_C1-Pad1_ GND 1u
+
+.end
diff --git a/library/SubcircuitLibrary/TLC2272/CD74HC238/INVCMOS.cir.out b/library/SubcircuitLibrary/TLC2272/CD74HC238/INVCMOS.cir.out
new file mode 100644
index 000000000..cb2b6641c
--- /dev/null
+++ b/library/SubcircuitLibrary/TLC2272/CD74HC238/INVCMOS.cir.out
@@ -0,0 +1,18 @@
+* /home/saurabh/downloads/esim-1.1.2/src/subcircuitlibrary/invcmos/invcmos.cir
+
+.include NMOS-180nm.lib
+.include PMOS-180nm.lib
+* u1 net-_m1-pad2_ net-_c1-pad1_ port
+m1 net-_c1-pad1_ net-_m1-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+m2 net-_m2-pad1_ net-_m1-pad2_ net-_c1-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1
+v1 net-_m2-pad1_ gnd 5
+c1 net-_c1-pad1_ gnd 1u
+.tran 0e-03 0e-03 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/TLC2272/CD74HC238/INVCMOS.pro b/library/SubcircuitLibrary/TLC2272/CD74HC238/INVCMOS.pro
new file mode 100644
index 000000000..81bd9ad40
--- /dev/null
+++ b/library/SubcircuitLibrary/TLC2272/CD74HC238/INVCMOS.pro
@@ -0,0 +1,70 @@
+update=Sun Aug 25 15:54:56 2019
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Subckt
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_Plot
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_User
+
diff --git a/library/SubcircuitLibrary/TLC2272/CD74HC238/INVCMOS.sch b/library/SubcircuitLibrary/TLC2272/CD74HC238/INVCMOS.sch
new file mode 100644
index 000000000..13a7fc092
--- /dev/null
+++ b/library/SubcircuitLibrary/TLC2272/CD74HC238/INVCMOS.sch
@@ -0,0 +1,189 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_User
+LIBS:eSim_Plot
+LIBS:eSim_PSpice
+LIBS:eSim_Subckt
+LIBS:INVCMOS-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "29 apr 2015"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Wire Wire Line
+ 5900 4000 5900 4150
+Connection ~ 5800 2450
+Connection ~ 5800 4150
+Wire Wire Line
+ 5900 4150 5800 4150
+Connection ~ 5050 3350
+Wire Wire Line
+ 4000 3350 5050 3350
+Wire Wire Line
+ 5050 3850 5500 3850
+Wire Wire Line
+ 5050 2700 5050 3850
+Wire Wire Line
+ 5050 2700 5500 2700
+Wire Wire Line
+ 5800 3650 5800 2900
+Wire Wire Line
+ 5800 2500 5800 2300
+Connection ~ 4200 3350
+$Comp
+L PORT U1
+U 1 1 5D6263BC
+P 3750 3350
+F 0 "U1" H 3800 3450 30 0000 C CNN
+F 1 "PORT" H 3750 3350 30 0000 C CNN
+F 2 "" H 3750 3350 60 0000 C CNN
+F 3 "" H 3750 3350 60 0000 C CNN
+ 1 3750 3350
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6050 3250 5800 3250
+Connection ~ 5800 3250
+Wire Wire Line
+ 5800 4050 5800 4550
+$Comp
+L eSim_MOS_N M1
+U 1 1 5D6265DB
+P 5600 3650
+F 0 "M1" H 5600 3500 50 0000 R CNN
+F 1 "eSim_MOS_N" H 5700 3600 50 0000 R CNN
+F 2 "" H 5900 3350 29 0000 C CNN
+F 3 "" H 5700 3450 60 0000 C CNN
+ 1 5600 3650
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M2
+U 1 1 5D626659
+P 5650 2700
+F 0 "M2" H 5600 2750 50 0000 R CNN
+F 1 "eSim_MOS_P" H 5700 2850 50 0000 R CNN
+F 2 "" H 5900 2800 29 0000 C CNN
+F 3 "" H 5700 2700 60 0000 C CNN
+ 1 5650 2700
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5900 2850 6050 2850
+Wire Wire Line
+ 6050 2850 6050 2450
+Wire Wire Line
+ 6050 2450 5800 2450
+Connection ~ 6000 3250
+Connection ~ 5800 4300
+$Comp
+L GND #PWR1
+U 1 1 5D626C59
+P 5800 4550
+F 0 "#PWR1" H 5800 4300 50 0001 C CNN
+F 1 "GND" H 5800 4400 50 0000 C CNN
+F 2 "" H 5800 4550 50 0001 C CNN
+F 3 "" H 5800 4550 50 0001 C CNN
+ 1 5800 4550
+ 1 0 0 -1
+$EndComp
+$Comp
+L DC v1
+U 1 1 5D626C7F
+P 6250 2300
+F 0 "v1" H 6050 2400 60 0000 C CNN
+F 1 "5" H 6050 2250 60 0000 C CNN
+F 2 "R1" H 5950 2300 60 0000 C CNN
+F 3 "" H 6250 2300 60 0000 C CNN
+ 1 6250 2300
+ 0 -1 -1 0
+$EndComp
+$Comp
+L GND #PWR2
+U 1 1 5D626CF6
+P 6850 2300
+F 0 "#PWR2" H 6850 2050 50 0001 C CNN
+F 1 "GND" H 6850 2150 50 0000 C CNN
+F 2 "" H 6850 2300 50 0001 C CNN
+F 3 "" H 6850 2300 50 0001 C CNN
+ 1 6850 2300
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6850 2300 6700 2300
+$Comp
+L PORT U1
+U 2 1 5D626DCB
+P 6300 3250
+F 0 "U1" H 6350 3350 30 0000 C CNN
+F 1 "PORT" H 6300 3250 30 0000 C CNN
+F 2 "" H 6300 3250 60 0000 C CNN
+F 3 "" H 6300 3250 60 0000 C CNN
+ 2 6300 3250
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_C C1
+U 1 1 5D62796C
+P 6050 3850
+F 0 "C1" H 6075 3950 50 0000 L CNN
+F 1 "1u" H 6075 3750 50 0000 L CNN
+F 2 "" H 6088 3700 30 0000 C CNN
+F 3 "" H 6050 3850 60 0000 C CNN
+ 1 6050 3850
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6050 3700 6050 3400
+Wire Wire Line
+ 6050 3400 6000 3400
+Wire Wire Line
+ 6000 3400 6000 3250
+Wire Wire Line
+ 6050 4000 6050 4300
+Wire Wire Line
+ 6050 4300 5800 4300
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/TLC2272/CD74HC238/INVCMOS.sub b/library/SubcircuitLibrary/TLC2272/CD74HC238/INVCMOS.sub
new file mode 100644
index 000000000..2319995c9
--- /dev/null
+++ b/library/SubcircuitLibrary/TLC2272/CD74HC238/INVCMOS.sub
@@ -0,0 +1,12 @@
+* Subcircuit INVCMOS
+.subckt INVCMOS net-_m1-pad2_ net-_c1-pad1_
+* /home/saurabh/downloads/esim-1.1.2/src/subcircuitlibrary/invcmos/invcmos.cir
+.include NMOS-180nm.lib
+.include PMOS-180nm.lib
+m1 net-_c1-pad1_ net-_m1-pad2_ gnd gnd CMOSN W=100u L=100u M=1
+m2 net-_m2-pad1_ net-_m1-pad2_ net-_c1-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1
+v1 net-_m2-pad1_ gnd 5
+c1 net-_c1-pad1_ gnd 1u
+* Control Statements
+
+.ends INVCMOS
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/TLC2272/CD74HC238/INVCMOS_Previous_Values.xml b/library/SubcircuitLibrary/TLC2272/CD74HC238/INVCMOS_Previous_Values.xml
new file mode 100644
index 000000000..e5bb98c76
--- /dev/null
+++ b/library/SubcircuitLibrary/TLC2272/CD74HC238/INVCMOS_Previous_Values.xml
@@ -0,0 +1 @@
+5/home/saurabh/Downloads/eSim-1.1.2/src/deviceModelLibrary/MOS/NMOS-180nm.lib/home/saurabh/Downloads/eSim-1.1.2/src/deviceModelLibrary/MOS/PMOS-180nm.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes000Secmsms
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/TLC2272/CD74HC238/NMOS-180nm.lib b/library/SubcircuitLibrary/TLC2272/CD74HC238/NMOS-180nm.lib
new file mode 100644
index 000000000..51e9b1196
--- /dev/null
+++ b/library/SubcircuitLibrary/TLC2272/CD74HC238/NMOS-180nm.lib
@@ -0,0 +1,13 @@
+.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697
++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0
++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18
++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4
++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0
++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0
++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3
++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1
++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1
++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12
++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286
++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078
++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3)
diff --git a/library/SubcircuitLibrary/TLC2272/CD74HC238/PMOS-180nm.lib b/library/SubcircuitLibrary/TLC2272/CD74HC238/PMOS-180nm.lib
new file mode 100644
index 000000000..032b5b95e
--- /dev/null
+++ b/library/SubcircuitLibrary/TLC2272/CD74HC238/PMOS-180nm.lib
@@ -0,0 +1,11 @@
+.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015
++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363
++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478
++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677
++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9
++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148
++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10
++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9
++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5
++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3
++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3)
diff --git a/library/SubcircuitLibrary/TLC2272/CD74HC238/analysis b/library/SubcircuitLibrary/TLC2272/CD74HC238/analysis
new file mode 100644
index 000000000..4ccdff53b
--- /dev/null
+++ b/library/SubcircuitLibrary/TLC2272/CD74HC238/analysis
@@ -0,0 +1 @@
+.tran 1e-06 10e-03 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/TLC272/SN54LS181/SN54LS181.proj b/library/SubcircuitLibrary/TLC272/SN54LS181/SN54LS181.proj
new file mode 100644
index 000000000..db3664c7b
--- /dev/null
+++ b/library/SubcircuitLibrary/TLC272/SN54LS181/SN54LS181.proj
@@ -0,0 +1 @@
+schematicFile SN54LS181.sch
diff --git a/library/SubcircuitLibrary/tl431/CD4012B/CD4012B.proj b/library/SubcircuitLibrary/tl431/CD4012B/CD4012B.proj
new file mode 100644
index 000000000..029802894
--- /dev/null
+++ b/library/SubcircuitLibrary/tl431/CD4012B/CD4012B.proj
@@ -0,0 +1 @@
+schematicFile CD74HC4002.sch
diff --git a/library/SubcircuitLibrary/tl431/CD4025B/CD4025B.pro b/library/SubcircuitLibrary/tl431/CD4025B/CD4025B.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/tl431/CD4025B/CD4025B.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/tl431/CD4025B/CD4025B.proj b/library/SubcircuitLibrary/tl431/CD4025B/CD4025B.proj
new file mode 100644
index 000000000..965731c59
--- /dev/null
+++ b/library/SubcircuitLibrary/tl431/CD4025B/CD4025B.proj
@@ -0,0 +1 @@
+schematicFile CD4025B.sch
diff --git a/library/SubcircuitLibrary/tl431/CD74HC4002/CD74HC4002.proj b/library/SubcircuitLibrary/tl431/CD74HC4002/CD74HC4002.proj
new file mode 100644
index 000000000..9c66865de
--- /dev/null
+++ b/library/SubcircuitLibrary/tl431/CD74HC4002/CD74HC4002.proj
@@ -0,0 +1 @@
+schematicFile CD4012B.sch
diff --git a/library/SubcircuitLibrary/tl431/SN54ALS560A/SN54ALS560A.proj b/library/SubcircuitLibrary/tl431/SN54ALS560A/SN54ALS560A.proj
new file mode 100644
index 000000000..b2ed7f35f
--- /dev/null
+++ b/library/SubcircuitLibrary/tl431/SN54ALS560A/SN54ALS560A.proj
@@ -0,0 +1 @@
+schematicFile SN54ALS560A.sch
diff --git a/library/SubcircuitLibrary/tl431/SN74ALS677A/SN74ALS677A.proj b/library/SubcircuitLibrary/tl431/SN74ALS677A/SN74ALS677A.proj
new file mode 100644
index 000000000..e7daf839a
--- /dev/null
+++ b/library/SubcircuitLibrary/tl431/SN74ALS677A/SN74ALS677A.proj
@@ -0,0 +1 @@
+schematicFile SN74ALS677A.sch
diff --git a/library/SubcircuitLibrary/tl431/SN74AS10/SN74AS10.proj b/library/SubcircuitLibrary/tl431/SN74AS10/SN74AS10.proj
new file mode 100644
index 000000000..623278bf7
--- /dev/null
+++ b/library/SubcircuitLibrary/tl431/SN74AS10/SN74AS10.proj
@@ -0,0 +1 @@
+schematicFile SN74AS10.sch
diff --git a/library/SubcircuitLibrary/tl431/SN74LS91/SN74LS91.proj b/library/SubcircuitLibrary/tl431/SN74LS91/SN74LS91.proj
new file mode 100644
index 000000000..16cd9ead2
--- /dev/null
+++ b/library/SubcircuitLibrary/tl431/SN74LS91/SN74LS91.proj
@@ -0,0 +1 @@
+schematicFile SN74LS91.sch