diff --git a/library/SubcircuitLibrary/CD4030/CD4030-cache.lib b/library/SubcircuitLibrary/CD4030/CD4030-cache.lib
new file mode 100644
index 000000000..6c512720e
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030/CD4030-cache.lib
@@ -0,0 +1,100 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_N
+#
+DEF eSim_MOS_N M 0 0 Y N 1 F N
+F0 "M" 0 -150 50 H V R CNN
+F1 "eSim_MOS_N" 100 -50 50 H V R CNN
+F2 "" 300 -300 29 H V C CNN
+F3 "" 100 -200 60 H V C CNN
+ALIAS mosfet_n
+DRAW
+C 150 -200 111 0 1 10 N
+P 2 0 1 10 130 -290 130 -250 N
+P 2 0 1 0 130 -270 200 -270 N
+P 2 0 1 10 130 -220 130 -180 N
+P 2 0 1 0 130 -200 200 -200 N
+P 2 0 1 10 130 -150 130 -110 N
+P 2 0 1 0 130 -130 200 -130 N
+P 2 0 1 0 200 -300 200 -270 N
+P 2 0 1 0 200 -130 200 -100 N
+P 3 0 1 10 110 -275 110 -125 110 -125 N
+P 3 0 1 0 200 -200 300 -200 300 -250 N
+P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F
+X D 1 200 0 100 D 50 50 1 1 P
+X G 2 -100 -200 210 R 50 50 1 1 P
+X S 3 200 -400 100 U 50 50 1 1 P
+X B 4 300 -350 98 U 47 47 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_P
+#
+DEF eSim_MOS_P M 0 0 Y N 1 F N
+F0 "M" -50 50 50 H V R CNN
+F1 "eSim_MOS_P" 50 150 50 H V R CNN
+F2 "" 250 100 29 H V C CNN
+F3 "" 50 0 60 H V C CNN
+ALIAS mosfet_p
+DRAW
+C 100 0 111 0 1 10 N
+P 2 0 1 0 80 -70 150 -70 N
+P 2 0 1 10 80 -50 80 -90 N
+P 2 0 1 0 80 0 150 0 N
+P 2 0 1 10 80 20 80 -20 N
+P 2 0 1 0 80 70 150 70 N
+P 2 0 1 10 80 90 80 50 N
+P 2 0 1 0 150 -70 150 -100 N
+P 2 0 1 0 150 100 150 70 N
+P 3 0 1 10 60 75 60 -75 60 -75 N
+P 3 0 1 0 150 0 250 0 250 -50 N
+P 4 0 1 0 140 0 100 -15 100 15 140 0 F
+X D 1 150 200 100 D 50 50 1 1 P
+X G 2 -150 0 210 R 50 50 1 1 P
+X S 3 150 -200 100 U 50 50 1 1 P
+X B 4 250 -150 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/CD4030/CD4030.cir b/library/SubcircuitLibrary/CD4030/CD4030.cir
new file mode 100644
index 000000000..59d9f0115
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030/CD4030.cir
@@ -0,0 +1,55 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD4030\CD4030.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/29/25 12:06:45
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+M3  Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P		
+M6  Net-_M1-Pad1_ Net-_M2-Pad2_ Net-_M10-Pad2_ Net-_M11-Pad3_ eSim_MOS_P		
+M8  Net-_M8-Pad1_ Net-_M2-Pad1_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P		
+M11  Net-_M10-Pad1_ Net-_M10-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P		
+M9  Net-_M8-Pad1_ Net-_M1-Pad1_ Net-_M10-Pad2_ Net-_M11-Pad3_ eSim_MOS_P		
+M7  Net-_M10-Pad2_ Net-_M1-Pad1_ Net-_M2-Pad1_ Net-_M1-Pad3_ eSim_MOS_N		
+M10  Net-_M10-Pad1_ Net-_M10-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N		
+M1  Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N		
+M5  Net-_M1-Pad1_ Net-_M2-Pad1_ Net-_M10-Pad2_ Net-_M1-Pad3_ eSim_MOS_N		
+M4  Net-_M2-Pad1_ Net-_M2-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P		
+M2  Net-_M2-Pad1_ Net-_M2-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N		
+M14  Net-_M12-Pad1_ Net-_M12-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P		
+M17  Net-_M12-Pad1_ Net-_M13-Pad2_ Net-_M16-Pad3_ Net-_M11-Pad3_ eSim_MOS_P		
+M19  Net-_M19-Pad1_ Net-_M13-Pad1_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P		
+M22  Net-_M21-Pad1_ Net-_M16-Pad3_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P		
+M20  Net-_M19-Pad1_ Net-_M12-Pad1_ Net-_M16-Pad3_ Net-_M11-Pad3_ eSim_MOS_P		
+M21  Net-_M21-Pad1_ Net-_M16-Pad3_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N		
+M12  Net-_M12-Pad1_ Net-_M12-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N		
+M16  Net-_M12-Pad1_ Net-_M13-Pad1_ Net-_M16-Pad3_ Net-_M1-Pad3_ eSim_MOS_N		
+M15  Net-_M13-Pad1_ Net-_M13-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P		
+M13  Net-_M13-Pad1_ Net-_M13-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N		
+M25  Net-_M23-Pad1_ Net-_M23-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P		
+M28  Net-_M23-Pad1_ Net-_M24-Pad2_ Net-_M27-Pad3_ Net-_M11-Pad3_ eSim_MOS_P		
+M30  Net-_M30-Pad1_ Net-_M24-Pad1_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P		
+M33  Net-_M32-Pad1_ Net-_M27-Pad3_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P		
+M31  Net-_M30-Pad1_ Net-_M23-Pad1_ Net-_M27-Pad3_ Net-_M11-Pad3_ eSim_MOS_P		
+M29  Net-_M27-Pad3_ Net-_M23-Pad1_ Net-_M24-Pad1_ Net-_M1-Pad3_ eSim_MOS_N		
+M32  Net-_M32-Pad1_ Net-_M27-Pad3_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N		
+M23  Net-_M23-Pad1_ Net-_M23-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N		
+M27  Net-_M23-Pad1_ Net-_M24-Pad1_ Net-_M27-Pad3_ Net-_M1-Pad3_ eSim_MOS_N		
+M26  Net-_M24-Pad1_ Net-_M24-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P		
+M24  Net-_M24-Pad1_ Net-_M24-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N		
+M36  Net-_M34-Pad1_ Net-_M34-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P		
+M39  Net-_M34-Pad1_ Net-_M35-Pad2_ Net-_M38-Pad3_ Net-_M11-Pad3_ eSim_MOS_P		
+M41  Net-_M41-Pad1_ Net-_M35-Pad1_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P		
+M44  Net-_M43-Pad1_ Net-_M38-Pad3_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P		
+M42  Net-_M41-Pad1_ Net-_M34-Pad1_ Net-_M38-Pad3_ Net-_M11-Pad3_ eSim_MOS_P		
+M40  Net-_M38-Pad3_ Net-_M34-Pad1_ Net-_M35-Pad1_ Net-_M1-Pad3_ eSim_MOS_N		
+M43  Net-_M43-Pad1_ Net-_M38-Pad3_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N		
+M34  Net-_M34-Pad1_ Net-_M34-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N		
+M38  Net-_M34-Pad1_ Net-_M35-Pad1_ Net-_M38-Pad3_ Net-_M1-Pad3_ eSim_MOS_N		
+M37  Net-_M35-Pad1_ Net-_M35-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P		
+M35  Net-_M35-Pad1_ Net-_M35-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N		
+U1  Net-_M2-Pad2_ Net-_M1-Pad2_ Net-_M10-Pad1_ Net-_M21-Pad1_ Net-_M12-Pad2_ Net-_M13-Pad2_ Net-_M1-Pad3_ Net-_M24-Pad2_ Net-_M23-Pad2_ Net-_M32-Pad1_ Net-_M43-Pad1_ Net-_M34-Pad2_ Net-_M35-Pad2_ Net-_M11-Pad3_ PORT		
+M18  Net-_M16-Pad3_ Net-_M12-Pad1_ Net-_M13-Pad1_ Net-_M1-Pad3_ eSim_MOS_N		
+
+.end
diff --git a/library/SubcircuitLibrary/CD4030/CD4030.cir.out b/library/SubcircuitLibrary/CD4030/CD4030.cir.out
new file mode 100644
index 000000000..aa0777a60
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030/CD4030.cir.out
@@ -0,0 +1,58 @@
+* c:\fossee\esim\library\subcircuitlibrary\cd4030\cd4030.cir
+
+.include PMOS-5um.lib
+.include NMOS-5um.lib
+m3 net-_m1-pad1_ net-_m1-pad2_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m6 net-_m1-pad1_ net-_m2-pad2_ net-_m10-pad2_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m8 net-_m8-pad1_ net-_m2-pad1_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m11 net-_m10-pad1_ net-_m10-pad2_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m9 net-_m8-pad1_ net-_m1-pad1_ net-_m10-pad2_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m7 net-_m10-pad2_ net-_m1-pad1_ net-_m2-pad1_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m10 net-_m10-pad1_ net-_m10-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m5 net-_m1-pad1_ net-_m2-pad1_ net-_m10-pad2_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m4 net-_m2-pad1_ net-_m2-pad2_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m2 net-_m2-pad1_ net-_m2-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m14 net-_m12-pad1_ net-_m12-pad2_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m17 net-_m12-pad1_ net-_m13-pad2_ net-_m16-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m19 net-_m19-pad1_ net-_m13-pad1_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m22 net-_m21-pad1_ net-_m16-pad3_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m20 net-_m19-pad1_ net-_m12-pad1_ net-_m16-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m21 net-_m21-pad1_ net-_m16-pad3_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m12 net-_m12-pad1_ net-_m12-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m16 net-_m12-pad1_ net-_m13-pad1_ net-_m16-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m15 net-_m13-pad1_ net-_m13-pad2_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m13 net-_m13-pad1_ net-_m13-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m25 net-_m23-pad1_ net-_m23-pad2_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m28 net-_m23-pad1_ net-_m24-pad2_ net-_m27-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m30 net-_m30-pad1_ net-_m24-pad1_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m33 net-_m32-pad1_ net-_m27-pad3_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m31 net-_m30-pad1_ net-_m23-pad1_ net-_m27-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m29 net-_m27-pad3_ net-_m23-pad1_ net-_m24-pad1_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m32 net-_m32-pad1_ net-_m27-pad3_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m23 net-_m23-pad1_ net-_m23-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m27 net-_m23-pad1_ net-_m24-pad1_ net-_m27-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m26 net-_m24-pad1_ net-_m24-pad2_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m24 net-_m24-pad1_ net-_m24-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m36 net-_m34-pad1_ net-_m34-pad2_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m39 net-_m34-pad1_ net-_m35-pad2_ net-_m38-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m41 net-_m41-pad1_ net-_m35-pad1_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m44 net-_m43-pad1_ net-_m38-pad3_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m42 net-_m41-pad1_ net-_m34-pad1_ net-_m38-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m40 net-_m38-pad3_ net-_m34-pad1_ net-_m35-pad1_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m43 net-_m43-pad1_ net-_m38-pad3_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m34 net-_m34-pad1_ net-_m34-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m38 net-_m34-pad1_ net-_m35-pad1_ net-_m38-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m37 net-_m35-pad1_ net-_m35-pad2_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m35 net-_m35-pad1_ net-_m35-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+* u1  net-_m2-pad2_ net-_m1-pad2_ net-_m10-pad1_ net-_m21-pad1_ net-_m12-pad2_ net-_m13-pad2_ net-_m1-pad3_ net-_m24-pad2_ net-_m23-pad2_ net-_m32-pad1_ net-_m43-pad1_ net-_m34-pad2_ net-_m35-pad2_ net-_m11-pad3_ port
+m18 net-_m16-pad3_ net-_m12-pad1_ net-_m13-pad1_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/CD4030/CD4030.pro b/library/SubcircuitLibrary/CD4030/CD4030.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030/CD4030.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/CD4030/CD4030.proj b/library/SubcircuitLibrary/CD4030/CD4030.proj
new file mode 100644
index 000000000..9d102c1a3
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030/CD4030.proj
@@ -0,0 +1 @@
+schematicFile CD4030.sch
diff --git a/library/SubcircuitLibrary/CD4030/CD4030.sch b/library/SubcircuitLibrary/CD4030/CD4030.sch
new file mode 100644
index 000000000..308f59cce
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030/CD4030.sch
@@ -0,0 +1,1381 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
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+	-6600 1500 -6600 1050
+Wire Wire Line
+	-7950 1050 -5950 1050
+Connection ~ -7950 1050
+Connection ~ -6600 1500
+Wire Wire Line
+	-7950 3050 -5200 3050
+Wire Wire Line
+	-7100 3050 -7100 1700
+Connection ~ -7950 3050
+Wire Wire Line
+	-5200 500  -5000 500 
+Wire Wire Line
+	-5100 500  -5100 550 
+Wire Wire Line
+	-6450 350  -7900 350 
+Connection ~ -7900 350 
+Wire Wire Line
+	-5150 500  -5150 100 
+Wire Wire Line
+	-7900 100  -2800 100 
+Connection ~ -7900 100 
+Connection ~ -5150 500 
+Wire Wire Line
+	-5500 700  -5850 700 
+Wire Wire Line
+	-5850 700  -5850 3050
+Connection ~ -7100 3050
+Wire Wire Line
+	-5200 900  -5200 1150
+Connection ~ -7900 3550
+Wire Wire Line
+	-2800 3850 -7900 3850
+Connection ~ -7900 3850
+Wire Wire Line
+	-5200 1550 -5200 1750
+Wire Wire Line
+	-5500 1350 -5500 1950
+Wire Wire Line
+	-5500 1650 -5950 1650
+Wire Wire Line
+	-5950 1650 -5950 1050
+Connection ~ -6600 1050
+Connection ~ -5500 1650
+Wire Wire Line
+	-5100 3850 -5100 2100
+Connection ~ -6700 3850
+Wire Wire Line
+	-5200 3050 -5200 2150
+Connection ~ -5850 3050
+Wire Wire Line
+	-4250 950  -4150 950 
+Wire Wire Line
+	-4150 950  -4150 1000
+Wire Wire Line
+	-4200 100  -4200 950 
+Connection ~ -4200 950 
+Connection ~ -5150 100 
+Wire Wire Line
+	-4550 1150 -4550 1850
+Wire Wire Line
+	-5200 1650 -4550 1650
+Wire Wire Line
+	-4550 1650 -4550 1550
+Connection ~ -4550 1550
+Connection ~ -5200 1650
+Wire Wire Line
+	-4250 2050 -4150 2050
+Wire Wire Line
+	-4150 2050 -4150 2000
+Wire Wire Line
+	-4200 3850 -4200 2050
+Connection ~ -4200 2050
+Connection ~ -5100 3850
+Wire Wire Line
+	-4250 1350 -4250 1650
+Wire Wire Line
+	-2850 500  -2750 500 
+Wire Wire Line
+	-2750 500  -2750 550 
+Wire Wire Line
+	-2850 900  -2850 1150
+Connection ~ -2800 500 
+Wire Wire Line
+	-2850 1550 -2750 1550
+Wire Wire Line
+	-2750 1550 -2750 1500
+Wire Wire Line
+	-2800 1550 -2800 1800
+Connection ~ -2800 1550
+Wire Wire Line
+	-3150 700  -3150 1350
+Wire Wire Line
+	-2850 2450 -2750 2450
+Wire Wire Line
+	-2750 2450 -2750 2500
+Wire Wire Line
+	-2850 2850 -2850 3100
+Connection ~ -2800 2450
+Wire Wire Line
+	-2850 3500 -2750 3500
+Wire Wire Line
+	-2750 3500 -2750 3450
+Wire Wire Line
+	-3150 2650 -3150 3300
+Wire Wire Line
+	-1700 1450 -1250 1450
+Wire Wire Line
+	-1700 1850 -1250 1850
+Wire Wire Line
+	-1600 1800 -1600 3800
+Wire Wire Line
+	-1500 1450 -1500 1000
+Wire Wire Line
+	-2850 1000 -850 1000
+Connection ~ -2850 1000
+Connection ~ -1500 1450
+Wire Wire Line
+	-2850 3000 50   3000
+Wire Wire Line
+	-2000 3000 -2000 1650
+Connection ~ -2850 3000
+Wire Wire Line
+	-1350 300  -2800 300 
+Connection ~ -2800 300 
+Wire Wire Line
+	-2800 50   2650 50  
+Wire Wire Line
+	-750 650  -250 650 
+Wire Wire Line
+	-750 3000 -750 650 
+Connection ~ -2000 3000
+Wire Wire Line
+	-100 850  -100 1100
+Connection ~ -2800 3500
+Wire Wire Line
+	-2800 3800 2650 3800
+Connection ~ -2800 3800
+Wire Wire Line
+	-100 1500 -100 1700
+Wire Wire Line
+	-400 1300 -400 1900
+Wire Wire Line
+	-400 1600 -850 1600
+Wire Wire Line
+	-850 1600 -850 1000
+Connection ~ -1500 1000
+Connection ~ -400 1600
+Wire Wire Line
+	0    3800 0    2050
+Connection ~ -1600 3800
+Wire Wire Line
+	850  900  950  900 
+Wire Wire Line
+	950  900  950  950 
+Wire Wire Line
+	900  50   900  900 
+Connection ~ 900  900 
+Wire Wire Line
+	550  1100 550  1800
+Wire Wire Line
+	-100 1600 550  1600
+Wire Wire Line
+	550  1600 550  1500
+Connection ~ 550  1500
+Connection ~ -100 1600
+Wire Wire Line
+	850  2000 950  2000
+Wire Wire Line
+	950  2000 950  1950
+Wire Wire Line
+	900  3800 900  2000
+Connection ~ 900  2000
+Connection ~ 0    3800
+Wire Wire Line
+	850  1300 850  1600
+Wire Wire Line
+	2600 550  2700 550 
+Wire Wire Line
+	2700 550  2700 600 
+Wire Wire Line
+	2600 950  2600 1200
+Connection ~ 2650 550 
+Wire Wire Line
+	2600 1600 2700 1600
+Wire Wire Line
+	2700 1600 2700 1550
+Wire Wire Line
+	2650 1600 2650 1700
+Connection ~ 2650 1600
+Wire Wire Line
+	2300 750  2300 1400
+Wire Wire Line
+	2600 2500 2700 2500
+Wire Wire Line
+	2700 2500 2700 2550
+Wire Wire Line
+	2600 2900 2600 3150
+Connection ~ 2650 2500
+Wire Wire Line
+	2600 3550 2700 3550
+Wire Wire Line
+	2700 3550 2700 3500
+Wire Wire Line
+	2300 2700 2300 3350
+Wire Wire Line
+	3750 1500 4200 1500
+Wire Wire Line
+	3750 1900 4200 1900
+Wire Wire Line
+	3850 1850 3850 3850
+Wire Wire Line
+	4100 1850 4100 350 
+Wire Wire Line
+	3950 1500 3950 1050
+Wire Wire Line
+	2600 1050 4600 1050
+Connection ~ 2600 1050
+Connection ~ 3950 1500
+Wire Wire Line
+	2600 3050 5350 3050
+Wire Wire Line
+	3450 3050 3450 1700
+Connection ~ 2600 3050
+Wire Wire Line
+	5350 500  5650 500 
+Wire Wire Line
+	5450 500  5450 550 
+Wire Wire Line
+	4100 350  2650 350 
+Connection ~ 2650 350 
+Wire Wire Line
+	5400 100  5400 500 
+Wire Wire Line
+	2650 100  7900 100 
+Connection ~ 5400 500 
+Wire Wire Line
+	5050 700  4700 700 
+Wire Wire Line
+	4700 700  4700 3050
+Connection ~ 3450 3050
+Wire Wire Line
+	5350 900  5350 1150
+Connection ~ 2650 3550
+Wire Wire Line
+	7900 3850 2650 3850
+Wire Wire Line
+	5350 1550 5350 1750
+Wire Wire Line
+	5050 1350 5050 1950
+Wire Wire Line
+	5050 1650 4600 1650
+Wire Wire Line
+	4600 1650 4600 1050
+Connection ~ 3950 1050
+Connection ~ 5050 1650
+Wire Wire Line
+	5450 3850 5450 2100
+Connection ~ 3850 3850
+Wire Wire Line
+	5350 3050 5350 2150
+Connection ~ 4700 3050
+Wire Wire Line
+	6300 950  6400 950 
+Wire Wire Line
+	6400 950  6400 1000
+Wire Wire Line
+	6350 100  6350 950 
+Connection ~ 6350 950 
+Connection ~ 5400 100 
+Wire Wire Line
+	6000 1150 6000 1850
+Wire Wire Line
+	5350 1650 6000 1650
+Wire Wire Line
+	6000 1650 6000 1550
+Connection ~ 6000 1550
+Connection ~ 5350 1650
+Wire Wire Line
+	6300 2050 6400 2050
+Wire Wire Line
+	6400 2050 6400 2000
+Wire Wire Line
+	6350 3850 6350 2050
+Connection ~ 6350 2050
+Connection ~ 5450 3850
+Wire Wire Line
+	6300 1350 6300 1650
+Wire Wire Line
+	-2800 2450 -2800 2000
+Wire Wire Line
+	-2800 2000 -2400 2000
+Wire Wire Line
+	-2400 2000 -2400 50  
+Connection ~ -2400 50  
+Wire Wire Line
+	7850 500  7950 500 
+Wire Wire Line
+	7950 500  7950 550 
+Wire Wire Line
+	7850 900  7850 1150
+Connection ~ 7900 500 
+Wire Wire Line
+	7850 1550 7950 1550
+Wire Wire Line
+	7950 1550 7950 1500
+Wire Wire Line
+	7900 1550 7900 1650
+Connection ~ 7900 1550
+Wire Wire Line
+	7550 700  7550 1350
+Wire Wire Line
+	7850 2450 7950 2450
+Wire Wire Line
+	7950 2450 7950 2500
+Wire Wire Line
+	7850 2850 7850 3100
+Connection ~ 7900 2450
+Wire Wire Line
+	7850 3500 7950 3500
+Wire Wire Line
+	7950 3500 7950 3450
+Wire Wire Line
+	7550 2650 7550 3300
+Wire Wire Line
+	9000 1450 9450 1450
+Wire Wire Line
+	9000 1850 9450 1850
+Wire Wire Line
+	9100 1800 9100 3800
+Wire Wire Line
+	9350 1800 9350 300 
+Wire Wire Line
+	9200 1450 9200 1000
+Wire Wire Line
+	7850 1000 9850 1000
+Connection ~ 7850 1000
+Connection ~ 9200 1450
+Wire Wire Line
+	7850 3000 10600 3000
+Wire Wire Line
+	8700 3000 8700 1650
+Connection ~ 7850 3000
+Wire Wire Line
+	10600 450  10850 450 
+Wire Wire Line
+	10700 450  10700 500 
+Wire Wire Line
+	9350 300  7900 300 
+Connection ~ 7900 300 
+Wire Wire Line
+	10650 50   10650 450 
+Wire Wire Line
+	7900 50   11600 50  
+Connection ~ 10650 450 
+Wire Wire Line
+	10300 650  9950 650 
+Wire Wire Line
+	9950 650  9950 3000
+Connection ~ 8700 3000
+Wire Wire Line
+	10600 850  10600 1100
+Connection ~ 7900 3500
+Wire Wire Line
+	7900 3800 11600 3800
+Connection ~ 7900 3800
+Wire Wire Line
+	10600 1500 10600 1700
+Wire Wire Line
+	10300 1300 10300 1900
+Wire Wire Line
+	10300 1600 9850 1600
+Wire Wire Line
+	9850 1600 9850 1000
+Connection ~ 9200 1000
+Connection ~ 10300 1600
+Wire Wire Line
+	10700 3800 10700 2050
+Connection ~ 9100 3800
+Wire Wire Line
+	10600 3000 10600 2100
+Connection ~ 9950 3000
+Wire Wire Line
+	11550 900  11650 900 
+Wire Wire Line
+	11650 900  11650 950 
+Wire Wire Line
+	11600 50   11600 900 
+Connection ~ 11600 900 
+Connection ~ 10650 50  
+Wire Wire Line
+	11250 1100 11250 1800
+Wire Wire Line
+	10600 1600 11250 1600
+Wire Wire Line
+	11250 1600 11250 1500
+Connection ~ 11250 1500
+Connection ~ 10600 1600
+Wire Wire Line
+	11550 2000 11650 2000
+Wire Wire Line
+	11650 2000 11650 1950
+Wire Wire Line
+	11600 3800 11600 2000
+Connection ~ 11600 2000
+Connection ~ 10700 3800
+Wire Wire Line
+	11550 1300 11550 1600
+Wire Wire Line
+	2650 50   2650 100 
+Connection ~ 900  50  
+Wire Wire Line
+	7900 100  7900 50  
+Connection ~ 6350 100 
+Connection ~ 6350 3850
+Wire Wire Line
+	2650 3850 2650 3550
+Connection ~ 900  3800
+Wire Wire Line
+	-2800 3500 -2800 3850
+Connection ~ -4200 3850
+Wire Wire Line
+	2650 2500 2650 2100
+Wire Wire Line
+	2650 2100 3100 2100
+Wire Wire Line
+	3100 2100 3100 100 
+Connection ~ 3100 100 
+Wire Wire Line
+	7900 2450 7900 1950
+Wire Wire Line
+	7900 1950 8200 1950
+Wire Wire Line
+	8200 1950 8200 50  
+Connection ~ 8200 50  
+Wire Wire Line
+	-2800 100  -2800 50  
+Connection ~ -4200 100 
+Connection ~ -8250 1100
+Connection ~ -8250 3050
+Wire Wire Line
+	-4250 1500 -4100 1500
+Connection ~ -4250 1500
+Wire Wire Line
+	-8850 3050 -8250 3050
+Wire Wire Line
+	-3450 1000 -3150 1000
+Connection ~ -3150 1000
+Wire Wire Line
+	-3500 3000 -3150 3000
+Connection ~ -3150 3000
+Wire Wire Line
+	-6050 1700 -6050 2050
+Wire Wire Line
+	-6050 2050 -8500 2050
+Wire Wire Line
+	-8500 2050 -8500 3050
+Connection ~ -8500 3050
+Wire Wire Line
+	-950 1650 -950 2150
+Wire Wire Line
+	-950 2150 -3300 2150
+Wire Wire Line
+	-3300 2150 -3300 3000
+Connection ~ -3300 3000
+Wire Wire Line
+	4500 1700 4500 2350
+Wire Wire Line
+	4500 2350 2000 2350
+Wire Wire Line
+	2000 2350 2000 3050
+Wire Wire Line
+	1700 3050 2300 3050
+Connection ~ 2300 3050
+Wire Wire Line
+	9750 1650 9750 2150
+Wire Wire Line
+	9750 2150 7350 2150
+Wire Wire Line
+	7350 2150 7350 2950
+Wire Wire Line
+	7100 2950 7550 2950
+Connection ~ 7550 2950
+Wire Wire Line
+	850  1450 1050 1450
+Connection ~ 850  1450
+Connection ~ 2000 3050
+Wire Wire Line
+	1850 1100 2300 1100
+Connection ~ 2300 1100
+Wire Wire Line
+	6300 1450 6550 1450
+Connection ~ 6300 1450
+Wire Wire Line
+	11550 1450 11750 1450
+Connection ~ 11550 1450
+Wire Wire Line
+	7150 1050 7550 1050
+Connection ~ 7550 1050
+Connection ~ 7350 2950
+Connection ~ 2650 3800
+Wire Wire Line
+	7900 3500 7900 3850
+Wire Wire Line
+	-8050 50   -7900 50  
+Connection ~ -7900 50  
+Wire Wire Line
+	-8200 4000 -7900 4000
+Connection ~ -7900 4000
+Wire Wire Line
+	-5100 1500 -5000 1500
+Wire Wire Line
+	-5000 1500 -5000 500 
+Connection ~ -5100 500 
+Wire Wire Line
+	-2800 150  -2800 500 
+Wire Wire Line
+	-2800 150  -2650 150 
+Wire Wire Line
+	-2650 150  -2650 50  
+Connection ~ -2650 50  
+Wire Wire Line
+	5450 1500 5650 1500
+Wire Wire Line
+	5650 1500 5650 500 
+Connection ~ 5450 500 
+Wire Wire Line
+	10700 1450 10850 1450
+Wire Wire Line
+	10850 1450 10850 450 
+Connection ~ 10700 450 
+Wire Wire Line
+	2650 200  2650 550 
+Wire Wire Line
+	2650 200  2800 200 
+Wire Wire Line
+	2800 200  2800 100 
+Connection ~ 2800 100 
+Wire Wire Line
+	7900 200  7900 500 
+Wire Wire Line
+	7900 200  8000 200 
+Wire Wire Line
+	8000 200  8000 50  
+Connection ~ 8000 50  
+Wire Wire Line
+	-1350 300  -1350 1800
+Wire Wire Line
+	-400 1300 -200 1300
+Wire Wire Line
+	-100 1500 100  1500
+Wire Wire Line
+	-100 1100 100  1100
+Wire Wire Line
+	50   450  200  450 
+Wire Wire Line
+	150  50   150  500 
+Wire Wire Line
+	200  450  200  1450
+Connection ~ 150  450 
+Wire Wire Line
+	-400 1900 -250 1900
+Wire Wire Line
+	-250 1900 -250 1950
+$Comp
+L eSim_MOS_N M18
+U 1 1 68374D68
+P -150 1750
+F 0 "M18" H -150 1600 50  0000 R CNN
+F 1 "eSim_MOS_N" H -50 1700 50  0000 R CNN
+F 2 "" H 150 1450 29  0000 C CNN
+F 3 "" H -50 1550 60  0000 C CNN
+	1    -150 1750
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	50   3000 50   2150
+Connection ~ -750 3000
+Wire Wire Line
+	150  2100 150  3800
+Wire Wire Line
+	150  3800 100  3800
+Connection ~ 100  3800
+Wire Wire Line
+	-100 1700 50   1700
+Wire Wire Line
+	50   1700 50   1750
+Wire Wire Line
+	-100 850  50   850 
+Wire Wire Line
+	-7900 2500 -7900 2200
+Wire Wire Line
+	-7900 2200 -7450 2200
+Wire Wire Line
+	-7450 2200 -7450 100 
+Connection ~ -7450 100 
+Wire Wire Line
+	150  50   200  50  
+Connection ~ 200  50  
+Wire Wire Line
+	-7900 50   -7900 550 
+Wire Wire Line
+	-7900 4000 -7900 3550
+Wire Wire Line
+	-8700 1100 -8250 1100
+Wire Wire Line
+	-8050 -350 -8050 50  
+Wire Wire Line
+	-2800 1800 -4000 1800
+Wire Wire Line
+	-4000 1800 -4000 3850
+Connection ~ -4000 3850
+Wire Wire Line
+	-7900 1700 -7650 1700
+Wire Wire Line
+	-7650 1700 -7650 3850
+Connection ~ -7650 3850
+Wire Wire Line
+	2650 1700 3050 1700
+Wire Wire Line
+	3050 1700 3050 3850
+Connection ~ 3050 3850
+Wire Wire Line
+	7900 1650 8100 1650
+Wire Wire Line
+	8100 1650 8100 3800
+Connection ~ 8100 3800
+Wire Wire Line
+	9250 1850 9250 3400
+Connection ~ 9250 1850
+Wire Wire Line
+	9250 3400 10950 3400
+Wire Wire Line
+	10950 3400 10950 1600
+Connection ~ 10950 1600
+Wire Wire Line
+	3950 1900 3950 3600
+Wire Wire Line
+	3950 3600 5650 3600
+Wire Wire Line
+	5650 3600 5650 1650
+Connection ~ 5650 1650
+Connection ~ 3950 1900
+Wire Wire Line
+	-1500 1850 -1500 2850
+Wire Wire Line
+	-1500 2850 250  2850
+Wire Wire Line
+	250  2850 250  1600
+Connection ~ 250  1600
+Connection ~ -1500 1850
+Wire Wire Line
+	-6550 1900 -6550 2650
+Wire Wire Line
+	-6550 2650 -4900 2650
+Wire Wire Line
+	-4900 2650 -4900 1650
+Connection ~ -4900 1650
+Connection ~ -6550 1900
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD4030/CD4030.sub b/library/SubcircuitLibrary/CD4030/CD4030.sub
new file mode 100644
index 000000000..6db18def6
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030/CD4030.sub
@@ -0,0 +1,52 @@
+* Subcircuit CD4030
+.subckt CD4030 net-_m2-pad2_ net-_m1-pad2_ net-_m10-pad1_ net-_m21-pad1_ net-_m12-pad2_ net-_m13-pad2_ net-_m1-pad3_ net-_m24-pad2_ net-_m23-pad2_ net-_m32-pad1_ net-_m43-pad1_ net-_m34-pad2_ net-_m35-pad2_ net-_m11-pad3_ 
+* c:\fossee\esim\library\subcircuitlibrary\cd4030\cd4030.cir
+.include PMOS-5um.lib
+.include NMOS-5um.lib
+m3 net-_m1-pad1_ net-_m1-pad2_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m6 net-_m1-pad1_ net-_m2-pad2_ net-_m10-pad2_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m8 net-_m8-pad1_ net-_m2-pad1_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m11 net-_m10-pad1_ net-_m10-pad2_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m9 net-_m8-pad1_ net-_m1-pad1_ net-_m10-pad2_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m7 net-_m10-pad2_ net-_m1-pad1_ net-_m2-pad1_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m10 net-_m10-pad1_ net-_m10-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m5 net-_m1-pad1_ net-_m2-pad1_ net-_m10-pad2_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m4 net-_m2-pad1_ net-_m2-pad2_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m2 net-_m2-pad1_ net-_m2-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m14 net-_m12-pad1_ net-_m12-pad2_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m17 net-_m12-pad1_ net-_m13-pad2_ net-_m16-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m19 net-_m19-pad1_ net-_m13-pad1_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m22 net-_m21-pad1_ net-_m16-pad3_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m20 net-_m19-pad1_ net-_m12-pad1_ net-_m16-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m21 net-_m21-pad1_ net-_m16-pad3_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m12 net-_m12-pad1_ net-_m12-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m16 net-_m12-pad1_ net-_m13-pad1_ net-_m16-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m15 net-_m13-pad1_ net-_m13-pad2_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m13 net-_m13-pad1_ net-_m13-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m25 net-_m23-pad1_ net-_m23-pad2_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m28 net-_m23-pad1_ net-_m24-pad2_ net-_m27-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m30 net-_m30-pad1_ net-_m24-pad1_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m33 net-_m32-pad1_ net-_m27-pad3_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m31 net-_m30-pad1_ net-_m23-pad1_ net-_m27-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m29 net-_m27-pad3_ net-_m23-pad1_ net-_m24-pad1_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m32 net-_m32-pad1_ net-_m27-pad3_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m23 net-_m23-pad1_ net-_m23-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m27 net-_m23-pad1_ net-_m24-pad1_ net-_m27-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m26 net-_m24-pad1_ net-_m24-pad2_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m24 net-_m24-pad1_ net-_m24-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m36 net-_m34-pad1_ net-_m34-pad2_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m39 net-_m34-pad1_ net-_m35-pad2_ net-_m38-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m41 net-_m41-pad1_ net-_m35-pad1_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m44 net-_m43-pad1_ net-_m38-pad3_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m42 net-_m41-pad1_ net-_m34-pad1_ net-_m38-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m40 net-_m38-pad3_ net-_m34-pad1_ net-_m35-pad1_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m43 net-_m43-pad1_ net-_m38-pad3_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m34 net-_m34-pad1_ net-_m34-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m38 net-_m34-pad1_ net-_m35-pad1_ net-_m38-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m37 net-_m35-pad1_ net-_m35-pad2_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m35 net-_m35-pad1_ net-_m35-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m18 net-_m16-pad3_ net-_m12-pad1_ net-_m13-pad1_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+* Control Statements
+
+.ends CD4030
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4030/CD4030_Previous_Values.xml b/library/SubcircuitLibrary/CD4030/CD4030_Previous_Values.xml
new file mode 100644
index 000000000..275563399
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030/CD4030_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model /><devicemodel><m3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib</field><field /><field /><field /></m3><m6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib</field><field /><field /><field /></m6><m8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib</field><field /><field /><field /></m8><m11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib</field><field /><field /><field /></m11><m9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib</field><field /><field /><field /></m9><m7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib</field><field /><field /><field /></m7><m10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib</field><field /><field /><field /></m10><m1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib</field><field /><field /><field /></m1><m5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib</field><field /><field /><field /></m5><m4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib</field><field /><field /><field /></m4><m2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib</field><field /><field /><field /></m2><m14><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib</field><field /><field /><field /></m14><m17><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib</field><field /><field /><field /></m17><m19><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib</field><field /><field /><field /></m19><m22><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib</field><field /><field /><field /></m22><m20><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib</field><field /><field /><field /></m20><m21><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib</field><field /><field /><field /></m21><m12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib</field><field /><field /><field /></m12><m16><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib</field><field /><field /><field /></m16><m15><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib</field><field /><field /><field /></m15><m13><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib</field><field /><field /><field /></m13><m25><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib</field><field /><field /><field /></m25><m28><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib</field><field /><field /><field /></m28><m30><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib</field><field /><field /><field /></m30><m33><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib</field><field /><field /><field /></m33><m31><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib</field><field /><field /><field /></m31><m29><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib</field><field /><field /><field /></m29><m32><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib</field><field /><field /><field /></m32><m23><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib</field><field /><field /><field /></m23><m27><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib</field><field /><field /><field /></m27><m26><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib</field><field /><field /><field /></m26><m24><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib</field><field /><field /><field /></m24><m36><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib</field><field /><field /><field /></m36><m39><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib</field><field /><field /><field /></m39><m41><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib</field><field /><field /><field /></m41><m44><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib</field><field /><field /><field /></m44><m42><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib</field><field /><field /><field /></m42><m40><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib</field><field /><field /><field /></m40><m43><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib</field><field /><field /><field /></m43><m34><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib</field><field /><field /><field /></m34><m38><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib</field><field /><field /><field /></m38><m37><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib</field><field /><field /><field /></m37><m35><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib</field><field /><field /><field /></m35><m18><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib</field><field /><field /><field /></m18></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4030/NMOS-5um.lib b/library/SubcircuitLibrary/CD4030/NMOS-5um.lib
new file mode 100644
index 000000000..a237e1fe3
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030/NMOS-5um.lib
@@ -0,0 +1,5 @@
+* 5um technology
+
+.model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7 
++ Level=1
++ Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n  )
diff --git a/library/SubcircuitLibrary/CD4030/PMOS-5um.lib b/library/SubcircuitLibrary/CD4030/PMOS-5um.lib
new file mode 100644
index 000000000..9c3ed9760
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030/PMOS-5um.lib
@@ -0,0 +1,5 @@
+*5um technology
+
+.model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65
++ Level=1
++ Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n  )
diff --git a/library/SubcircuitLibrary/CD4030/analysis b/library/SubcircuitLibrary/CD4030/analysis
new file mode 100644
index 000000000..6783e70d4
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030/analysis
@@ -0,0 +1 @@
+.tran 10e-06 10e-03 0e-03
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4030/xor_test-cache.lib b/library/SubcircuitLibrary/CD4030/xor_test-cache.lib
new file mode 100644
index 000000000..3366a5975
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030/xor_test-cache.lib
@@ -0,0 +1,96 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# CD4030
+#
+DEF CD4030 X 0 40 Y Y 1 F N
+F0 "X" 0 -650 60 H V C CNN
+F1 "CD4030" 0 350 60 H V C CNN
+F2 "" 0 350 60 H I C CNN
+F3 "" 0 350 60 H I C CNN
+DRAW
+S -250 250 250 -550 0 1 0 N
+X A 1 -450 150 200 R 50 50 1 1 I
+X B 2 -450 50 200 R 50 50 1 1 I
+X J 3 -450 -50 200 R 50 50 1 1 O
+X K 4 -450 -150 200 R 50 50 1 1 O
+X C 5 -450 -250 200 R 50 50 1 1 I
+X D 6 -450 -350 200 R 50 50 1 1 I
+X VSS 7 -450 -450 200 R 50 50 1 1 I
+X E 8 450 -450 200 L 50 50 1 1 I
+X F 9 450 -350 200 L 50 50 1 1 I
+X L 10 450 -250 200 L 50 50 1 1 O
+X M 11 450 -150 200 L 50 50 1 1 O
+X G 12 450 -50 200 L 50 50 1 1 I
+X H 13 450 50 200 L 50 50 1 1 I
+X VDD 14 450 150 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# DC
+#
+DEF DC v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 w
+X - 2 0 -450 300 U 50 50 1 1 w
+ENDDRAW
+ENDDEF
+#
+# eSim_GND
+#
+DEF eSim_GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "eSim_GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# pulse
+#
+DEF pulse v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "pulse" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -25 -450 501 928 871 0 1 0 N -50 50 0 50
+A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50
+A 75 600 551 -926 -873 0 1 0 N 50 50 100 50
+A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50
+A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50
+A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/CD4030/xor_test.cir b/library/SubcircuitLibrary/CD4030/xor_test.cir
new file mode 100644
index 000000000..3bff35fc3
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030/xor_test.cir
@@ -0,0 +1,17 @@
+* C:\Users\pavithra\eSim-Workspace\xor_test\xor_test.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/29/25 12:14:05
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+v1  A GND pulse		
+v2  B GND pulse		
+U4  J plot_v1		
+v9  Net-_X1-Pad14_ GND DC		
+U1  A plot_v1		
+U2  B plot_v1		
+X1  A B J ? ? ? GND ? ? ? ? ? ? Net-_X1-Pad14_ CD4030		
+
+.end
diff --git a/library/SubcircuitLibrary/CD4030/xor_test.cir.out b/library/SubcircuitLibrary/CD4030/xor_test.cir.out
new file mode 100644
index 000000000..252d284e1
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030/xor_test.cir.out
@@ -0,0 +1,20 @@
+* c:\users\pavithra\esim-workspace\xor_test\xor_test.cir
+
+.include CD4030.sub
+v1  a gnd pulse(0 5 2m 0.1n 0.1n 1m 2m)
+v2  b gnd pulse(0 5 4m 0.1n 0.1n 2m 4m)
+* u4  j plot_v1
+v9 net-_x1-pad14_ gnd  dc 5
+* u1  a plot_v1
+* u2  b plot_v1
+x1 a b j ? ? ? gnd ? ? ? ? ? ? net-_x1-pad14_ CD4030
+.tran 10e-06 10e-03 0e-03
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(j)+6v(a)+12v(b)
+.endc
+.end
diff --git a/library/SubcircuitLibrary/CD4030/xor_test.pro b/library/SubcircuitLibrary/CD4030/xor_test.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030/xor_test.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/CD4030/xor_test.proj b/library/SubcircuitLibrary/CD4030/xor_test.proj
new file mode 100644
index 000000000..6ff11795c
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030/xor_test.proj
@@ -0,0 +1 @@
+schematicFile xor_test.sch
diff --git a/library/SubcircuitLibrary/CD4030/xor_test.sch b/library/SubcircuitLibrary/CD4030/xor_test.sch
new file mode 100644
index 000000000..63b84e400
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030/xor_test.sch
@@ -0,0 +1,248 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:xor_test-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L pulse v1
+U 1 1 683745BA
+P 2100 3850
+F 0 "v1" H 1900 3950 60  0000 C CNN
+F 1 "pulse" H 1900 3800 60  0000 C CNN
+F 2 "R1" H 1800 3850 60  0000 C CNN
+F 3 "" H 2100 3850 60  0000 C CNN
+	1    2100 3850
+	1    0    0    -1  
+$EndComp
+$Comp
+L pulse v2
+U 1 1 68374A0F
+P 2400 4050
+F 0 "v2" H 2200 4150 60  0000 C CNN
+F 1 "pulse" H 2200 4000 60  0000 C CNN
+F 2 "R1" H 2100 4050 60  0000 C CNN
+F 3 "" H 2400 4050 60  0000 C CNN
+	1    2400 4050
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_GND #PWR01
+U 1 1 68374AF4
+P 2100 4550
+F 0 "#PWR01" H 2100 4300 50  0001 C CNN
+F 1 "eSim_GND" H 2100 4400 50  0000 C CNN
+F 2 "" H 2100 4550 50  0001 C CNN
+F 3 "" H 2100 4550 50  0001 C CNN
+	1    2100 4550
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_GND #PWR02
+U 1 1 68374B3B
+P 2400 4650
+F 0 "#PWR02" H 2400 4400 50  0001 C CNN
+F 1 "eSim_GND" H 2400 4500 50  0000 C CNN
+F 2 "" H 2400 4650 50  0001 C CNN
+F 3 "" H 2400 4650 50  0001 C CNN
+	1    2400 4650
+	1    0    0    -1  
+$EndComp
+$Comp
+L plot_v1 U4
+U 1 1 68377A71
+P 5050 5550
+F 0 "U4" H 5050 6050 60  0000 C CNN
+F 1 "plot_v1" H 5250 5900 60  0000 C CNN
+F 2 "" H 5050 5550 60  0000 C CNN
+F 3 "" H 5050 5550 60  0000 C CNN
+	1    5050 5550
+	1    0    0    -1  
+$EndComp
+Text GLabel 4850 5500 0    60   Input ~ 0
+J
+$Comp
+L eSim_GND #PWR03
+U 1 1 68375687
+P 5000 3750
+F 0 "#PWR03" H 5000 3500 50  0001 C CNN
+F 1 "eSim_GND" H 5000 3600 50  0000 C CNN
+F 2 "" H 5000 3750 50  0001 C CNN
+F 3 "" H 5000 3750 50  0001 C CNN
+	1    5000 3750
+	1    0    0    -1  
+$EndComp
+$Comp
+L DC v9
+U 1 1 683757DD
+P 6150 2650
+F 0 "v9" H 5950 2750 60  0000 C CNN
+F 1 "DC" H 5950 2600 60  0000 C CNN
+F 2 "R1" H 5850 2650 60  0000 C CNN
+F 3 "" H 6150 2650 60  0000 C CNN
+	1    6150 2650
+	1    0    0    1   
+$EndComp
+$Comp
+L eSim_GND #PWR04
+U 1 1 683758F0
+P 6300 2200
+F 0 "#PWR04" H 6300 1950 50  0001 C CNN
+F 1 "eSim_GND" H 6300 2050 50  0000 C CNN
+F 2 "" H 6300 2200 50  0001 C CNN
+F 3 "" H 6300 2200 50  0001 C CNN
+	1    6300 2200
+	1    0    0    -1  
+$EndComp
+NoConn ~ 6000 3200
+NoConn ~ 6000 3300
+NoConn ~ 6000 3400
+NoConn ~ 6000 3500
+NoConn ~ 6000 3600
+NoConn ~ 6000 3700
+NoConn ~ 5100 3600
+NoConn ~ 5100 3500
+NoConn ~ 5100 3400
+$Comp
+L plot_v1 U1
+U 1 1 683808AA
+P 3000 3300
+F 0 "U1" H 3000 3800 60  0000 C CNN
+F 1 "plot_v1" H 3200 3650 60  0000 C CNN
+F 2 "" H 3000 3300 60  0000 C CNN
+F 3 "" H 3000 3300 60  0000 C CNN
+	1    3000 3300
+	1    0    0    -1  
+$EndComp
+$Comp
+L plot_v1 U2
+U 1 1 6838092D
+P 3050 3950
+F 0 "U2" H 3050 4450 60  0000 C CNN
+F 1 "plot_v1" H 3250 4300 60  0000 C CNN
+F 2 "" H 3050 3950 60  0000 C CNN
+F 3 "" H 3050 3950 60  0000 C CNN
+	1    3050 3950
+	1    0    0    -1  
+$EndComp
+Text GLabel 2700 3150 0    60   Input ~ 0
+A
+Wire Wire Line
+	2100 3400 2100 3250
+Wire Wire Line
+	2100 3250 4400 3250
+Wire Wire Line
+	2400 3600 2400 3350
+Wire Wire Line
+	2400 3350 4450 3350
+Wire Wire Line
+	2100 4300 2100 4550
+Wire Wire Line
+	2400 4500 2400 4650
+Wire Wire Line
+	4700 3300 4700 5350
+Wire Wire Line
+	4700 5350 5050 5350
+Wire Wire Line
+	4850 5500 4900 5500
+Wire Wire Line
+	4900 5500 4900 5350
+Connection ~ 4900 5350
+Wire Wire Line
+	6000 3100 6150 3100
+Wire Wire Line
+	6150 2200 6300 2200
+Wire Wire Line
+	4400 3250 4400 3100
+Wire Wire Line
+	4400 3100 5100 3100
+Wire Wire Line
+	4450 3350 4450 3200
+Wire Wire Line
+	4450 3200 5100 3200
+Wire Wire Line
+	5000 3750 5000 3700
+Wire Wire Line
+	5000 3700 5100 3700
+Wire Wire Line
+	4700 3300 5100 3300
+Wire Wire Line
+	3000 3100 3000 3250
+Connection ~ 3000 3250
+Wire Wire Line
+	3050 3750 3550 3750
+Wire Wire Line
+	3550 3750 3550 3350
+Connection ~ 3550 3350
+Wire Wire Line
+	2700 3150 3000 3150
+Connection ~ 3000 3150
+Text GLabel 3200 3950 0    60   Input ~ 0
+B
+Wire Wire Line
+	3200 3950 3350 3950
+Wire Wire Line
+	3350 3950 3350 3750
+Connection ~ 3350 3750
+$Comp
+L CD4030 X1
+U 1 1 68380AFF
+P 5550 3250
+F 0 "X1" H 5550 2600 60  0000 C CNN
+F 1 "CD4030" H 5550 3600 60  0000 C CNN
+F 2 "" H 5550 3600 60  0001 C CNN
+F 3 "" H 5550 3600 60  0001 C CNN
+	1    5550 3250
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD4030/xor_test_Previous_Values.xml b/library/SubcircuitLibrary/CD4030/xor_test_Previous_Values.xml
new file mode 100644
index 000000000..2a955c48a
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030/xor_test_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source><v1 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">2m</field3><field4 name="Rise Time">0.1n</field4><field5 name="Fall Time">0.1n</field5><field5 name="Pulse width">1m</field5><field5 name="Period">2m</field5></v1><v2 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">4m</field3><field4 name="Rise Time">0.1n</field4><field5 name="Fall Time">0.1n</field5><field5 name="Pulse width">2m</field5><field5 name="Period">4m</field5></v2><v3 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">2m</field3><field4 name="Rise Time">0.1n</field4><field5 name="Fall Time">0.1n</field5><field5 name="Pulse width">1m</field5><field5 name="Period">2m</field5></v3><v4 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">2m</field3><field4 name="Rise Time">0.1n</field4><field5 name="Fall Time">0.1n</field5><field5 name="Pulse width">1m</field5><field5 name="Period">2m</field5></v4><v8 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">2m</field3><field4 name="Rise Time">0.1n</field4><field5 name="Fall Time">0.1n</field5><field5 name="Pulse width">1m</field5><field5 name="Period">2m</field5></v8><v7 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">2m</field3><field4 name="Rise Time">0.1n</field4><field5 name="Fall Time">0.1n</field5><field5 name="Pulse width">1m</field5><field5 name="Period">2m</field5></v7><v6 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">2m</field3><field4 name="Rise Time">0.1n</field4><field5 name="Fall Time">0.1n</field5><field5 name="Pulse width">1m</field5><field5 name="Period">2m</field5></v6><v5 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">2m</field3><field4 name="Rise Time">0.1n</field4><field5 name="Fall Time">0.1n</field5><field5 name="Pulse width">1m</field5><field5 name="Period">2m</field5></v5><v9 name="Source type">dc<field1 name="Value">5</field1></v9></source><model><u1 name="type">adc_bridge<field1 name="Enter value for in_low (default=1.0)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter Fall Delay (default=1.0e-9)" /></u1><u8 name="type">adc_bridge<field5 name="Enter value for in_low (default=1.0)" /><field6 name="Enter value for in_high (default=2.0)" /><field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /></u8><u3 name="type">dac_bridge<field9 name="Enter value for out_low (default=0.0)" /><field10 name="Enter value for out_high (default=5.0)" /><field11 name="Enter value for out_undef (default=0.5)" /><field12 name="Enter value for input load (default=1.0e-12)" /><field13 name="Enter the Rise Time (default=1.0e-9)" /><field14 name="Enter the Fall Time (default=1.0e-9)" /></u3><u6 name="type">dac_bridge<field15 name="Enter value for out_low (default=0.0)" /><field16 name="Enter value for out_high (default=5.0)" /><field17 name="Enter value for out_undef (default=0.5)" /><field18 name="Enter value for input load (default=1.0e-12)" /><field19 name="Enter the Rise Time (default=1.0e-9)" /><field20 name="Enter the Fall Time (default=1.0e-9)" /></u6></model><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\CD4030</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">10</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">us</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4098/CD4098-cache.lib b/library/SubcircuitLibrary/CD4098/CD4098-cache.lib
new file mode 100644
index 000000000..23a1ef279
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/CD4098-cache.lib
@@ -0,0 +1,195 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_1
+#
+DEF adc_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# cd4098_latch
+#
+DEF cd4098_latch U 0 40 Y Y 1 F N
+F0 "U" 2850 1800 60 H V C CNN
+F1 "cd4098_latch" 2850 2000 60 H V C CNN
+F2 "" 2850 1950 60 H V C CNN
+F3 "" 2850 1950 60 H V C CNN
+DRAW
+S 2350 2100 3350 1400 0 1 0 N
+X D0 1 2150 1900 200 R 50 50 1 1 I
+X C0 2 2150 1800 200 R 50 50 1 1 I
+X R10 3 2150 1700 200 R 50 50 1 1 I
+X R20 4 2150 1600 200 R 50 50 1 1 I
+X Q0 5 3550 1900 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nand
+#
+DEF d_nand U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nand" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nor
+#
+DEF d_nor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nor" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_1
+#
+DEF dac_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_N
+#
+DEF eSim_MOS_N M 0 0 Y N 1 F N
+F0 "M" 0 -150 50 H V R CNN
+F1 "eSim_MOS_N" 100 -50 50 H V R CNN
+F2 "" 300 -300 29 H V C CNN
+F3 "" 100 -200 60 H V C CNN
+ALIAS mosfet_n
+DRAW
+C 150 -200 111 0 1 10 N
+P 2 0 1 10 130 -290 130 -250 N
+P 2 0 1 0 130 -270 200 -270 N
+P 2 0 1 10 130 -220 130 -180 N
+P 2 0 1 0 130 -200 200 -200 N
+P 2 0 1 10 130 -150 130 -110 N
+P 2 0 1 0 130 -130 200 -130 N
+P 2 0 1 0 200 -300 200 -270 N
+P 2 0 1 0 200 -130 200 -100 N
+P 3 0 1 10 110 -275 110 -125 110 -125 N
+P 3 0 1 0 200 -200 300 -200 300 -250 N
+P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F
+X D 1 200 0 100 D 50 50 1 1 P
+X G 2 -100 -200 210 R 50 50 1 1 P
+X S 3 200 -400 100 U 50 50 1 1 P
+X B 4 300 -350 98 U 47 47 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_P
+#
+DEF eSim_MOS_P M 0 0 Y N 1 F N
+F0 "M" -50 50 50 H V R CNN
+F1 "eSim_MOS_P" 50 150 50 H V R CNN
+F2 "" 250 100 29 H V C CNN
+F3 "" 50 0 60 H V C CNN
+ALIAS mosfet_p
+DRAW
+C 100 0 111 0 1 10 N
+P 2 0 1 0 80 -70 150 -70 N
+P 2 0 1 10 80 -50 80 -90 N
+P 2 0 1 0 80 0 150 0 N
+P 2 0 1 10 80 20 80 -20 N
+P 2 0 1 0 80 70 150 70 N
+P 2 0 1 10 80 90 80 50 N
+P 2 0 1 0 150 -70 150 -100 N
+P 2 0 1 0 150 100 150 70 N
+P 3 0 1 10 60 75 60 -75 60 -75 N
+P 3 0 1 0 150 0 250 0 250 -50 N
+P 4 0 1 0 140 0 100 -15 100 15 140 0 F
+X D 1 150 200 100 D 50 50 1 1 P
+X G 2 -150 0 210 R 50 50 1 1 P
+X S 3 150 -200 100 U 50 50 1 1 P
+X B 4 250 -150 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/CD4098/CD4098.cir b/library/SubcircuitLibrary/CD4098/CD4098.cir
new file mode 100644
index 000000000..919af079a
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/CD4098.cir
@@ -0,0 +1,32 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD4098\CD4098.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/26/25 13:17:11
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ d_inverter		
+U5  Net-_U1-Pad2_ Net-_U5-Pad2_ d_inverter		
+U2  Net-_U19-Pad2_ Net-_U2-Pad2_ d_inverter		
+U3  Net-_U19-Pad3_ Net-_U11-Pad1_ d_inverter		
+U8  Net-_U5-Pad2_ Net-_U2-Pad2_ Net-_U4-Pad2_ d_nand		
+U4  Net-_U19-Pad10_ Net-_U4-Pad2_ Net-_U11-Pad1_ Net-_U12-Pad2_ Net-_U10-Pad1_ cd4098_latch		
+U6  Net-_U10-Pad3_ Net-_U6-Pad2_ d_inverter		
+U9  Net-_U10-Pad3_ Net-_U19-Pad4_ d_inverter		
+U10  Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_nor		
+U7  Net-_U6-Pad2_ Net-_U19-Pad5_ d_inverter		
+U11  Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U10-Pad2_ d_nor		
+U12  Net-_U11-Pad2_ Net-_U12-Pad2_ d_inverter		
+U13  Net-_U13-Pad1_ Net-_U10-Pad1_ Net-_U13-Pad3_ d_nor		
+U14  Net-_U11-Pad2_ Net-_U13-Pad1_ d_inverter		
+U15  Net-_U13-Pad3_ Net-_U11-Pad1_ Net-_U15-Pad3_ d_nor		
+M1  Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N		
+M2  Net-_M2-Pad1_ Net-_M2-Pad2_ Net-_M2-Pad3_ Net-_M2-Pad3_ eSim_MOS_P		
+U17  Net-_U15-Pad3_ Net-_M2-Pad2_ dac_bridge_1		
+M3  Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M2-Pad1_ Net-_M2-Pad3_ eSim_MOS_P		
+U18  Net-_M1-Pad1_ Net-_U11-Pad2_ adc_bridge_1		
+U16  Net-_U10-Pad1_ Net-_M1-Pad2_ dac_bridge_1		
+U19  Net-_U1-Pad1_ Net-_U19-Pad2_ Net-_U19-Pad3_ Net-_U19-Pad4_ Net-_U19-Pad5_ Net-_M2-Pad3_ Net-_M1-Pad3_ ? Net-_U11-Pad2_ Net-_U19-Pad10_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/CD4098/CD4098.cir.out b/library/SubcircuitLibrary/CD4098/CD4098.cir.out
new file mode 100644
index 000000000..57f317163
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/CD4098.cir.out
@@ -0,0 +1,89 @@
+* c:\fossee\esim\library\subcircuitlibrary\cd4098\cd4098.cir
+
+.include PMOS-180nm.lib
+.include NMOS-180nm.lib
+* u1  net-_u1-pad1_ net-_u1-pad2_ d_inverter
+* u5  net-_u1-pad2_ net-_u5-pad2_ d_inverter
+* u2  net-_u19-pad2_ net-_u2-pad2_ d_inverter
+* u3  net-_u19-pad3_ net-_u11-pad1_ d_inverter
+* u8  net-_u5-pad2_ net-_u2-pad2_ net-_u4-pad2_ d_nand
+* u4  net-_u19-pad10_ net-_u4-pad2_ net-_u11-pad1_ net-_u12-pad2_ net-_u10-pad1_ cd4098_latch
+* u6  net-_u10-pad3_ net-_u6-pad2_ d_inverter
+* u9  net-_u10-pad3_ net-_u19-pad4_ d_inverter
+* u10  net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nor
+* u7  net-_u6-pad2_ net-_u19-pad5_ d_inverter
+* u11  net-_u11-pad1_ net-_u11-pad2_ net-_u10-pad2_ d_nor
+* u12  net-_u11-pad2_ net-_u12-pad2_ d_inverter
+* u13  net-_u13-pad1_ net-_u10-pad1_ net-_u13-pad3_ d_nor
+* u14  net-_u11-pad2_ net-_u13-pad1_ d_inverter
+* u15  net-_u13-pad3_ net-_u11-pad1_ net-_u15-pad3_ d_nor
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+m2 net-_m2-pad1_ net-_m2-pad2_ net-_m2-pad3_ net-_m2-pad3_ CMOSP W=100u L=100u M=1
+* u17  net-_u15-pad3_ net-_m2-pad2_ dac_bridge_1
+m3 net-_m1-pad1_ net-_m1-pad2_ net-_m2-pad1_ net-_m2-pad3_ CMOSP W=100u L=100u M=1
+* u18  net-_m1-pad1_ net-_u11-pad2_ adc_bridge_1
+* u16  net-_u10-pad1_ net-_m1-pad2_ dac_bridge_1
+* u19  net-_u1-pad1_ net-_u19-pad2_ net-_u19-pad3_ net-_u19-pad4_ net-_u19-pad5_ net-_m2-pad3_ net-_m1-pad3_ ? net-_u11-pad2_ net-_u19-pad10_ port
+a1 net-_u1-pad1_ net-_u1-pad2_ u1
+a2 net-_u1-pad2_ net-_u5-pad2_ u5
+a3 net-_u19-pad2_ net-_u2-pad2_ u2
+a4 net-_u19-pad3_ net-_u11-pad1_ u3
+a5 [net-_u5-pad2_ net-_u2-pad2_ ] net-_u4-pad2_ u8
+a6 [net-_u19-pad10_ ] [net-_u4-pad2_ ] [net-_u11-pad1_ ] [net-_u12-pad2_ ] [net-_u10-pad1_ ] u4
+a7 net-_u10-pad3_ net-_u6-pad2_ u6
+a8 net-_u10-pad3_ net-_u19-pad4_ u9
+a9 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a10 net-_u6-pad2_ net-_u19-pad5_ u7
+a11 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u10-pad2_ u11
+a12 net-_u11-pad2_ net-_u12-pad2_ u12
+a13 [net-_u13-pad1_ net-_u10-pad1_ ] net-_u13-pad3_ u13
+a14 net-_u11-pad2_ net-_u13-pad1_ u14
+a15 [net-_u13-pad3_ net-_u11-pad1_ ] net-_u15-pad3_ u15
+a16 [net-_u15-pad3_ ] [net-_m2-pad2_ ] u17
+a17 [net-_m1-pad1_ ] [net-_u11-pad2_ ] u18
+a18 [net-_u10-pad1_ ] [net-_m1-pad2_ ] u16
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             cd4098_latch, NgSpice Name: cd4098_latch
+.model u4 cd4098_latch(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u10 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u11 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u13 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u15 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u17 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u18 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u16 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/CD4098/CD4098.pro b/library/SubcircuitLibrary/CD4098/CD4098.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/CD4098.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/CD4098/CD4098.proj b/library/SubcircuitLibrary/CD4098/CD4098.proj
new file mode 100644
index 000000000..da1524788
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/CD4098.proj
@@ -0,0 +1 @@
+schematicFile CD4098.sch
diff --git a/library/SubcircuitLibrary/CD4098/CD4098.sch b/library/SubcircuitLibrary/CD4098/CD4098.sch
new file mode 100644
index 000000000..ca0e5bf4a
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/CD4098.sch
@@ -0,0 +1,537 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:CD4098-cache
+EELAYER 25 0
+EELAYER END
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+encoding utf-8
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+Date ""
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+F 3 "" H 15150 7900 60  0000 C CNN
+	1    15150 7900
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diff --git a/library/SubcircuitLibrary/CD4098/CD4098.sub b/library/SubcircuitLibrary/CD4098/CD4098.sub
new file mode 100644
index 000000000..2774be7b8
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/CD4098.sub
@@ -0,0 +1,83 @@
+* Subcircuit CD4098
+.subckt CD4098 net-_u1-pad1_ net-_u19-pad2_ net-_u19-pad3_ net-_u19-pad4_ net-_u19-pad5_ net-_m2-pad3_ net-_m1-pad3_ ? net-_u11-pad2_ net-_u19-pad10_ 
+* c:\fossee\esim\library\subcircuitlibrary\cd4098\cd4098.cir
+.include PMOS-180nm.lib
+.include NMOS-180nm.lib
+* u1  net-_u1-pad1_ net-_u1-pad2_ d_inverter
+* u5  net-_u1-pad2_ net-_u5-pad2_ d_inverter
+* u2  net-_u19-pad2_ net-_u2-pad2_ d_inverter
+* u3  net-_u19-pad3_ net-_u11-pad1_ d_inverter
+* u8  net-_u5-pad2_ net-_u2-pad2_ net-_u4-pad2_ d_nand
+* u4  net-_u19-pad10_ net-_u4-pad2_ net-_u11-pad1_ net-_u12-pad2_ net-_u10-pad1_ cd4098_latch
+* u6  net-_u10-pad3_ net-_u6-pad2_ d_inverter
+* u9  net-_u10-pad3_ net-_u19-pad4_ d_inverter
+* u10  net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nor
+* u7  net-_u6-pad2_ net-_u19-pad5_ d_inverter
+* u11  net-_u11-pad1_ net-_u11-pad2_ net-_u10-pad2_ d_nor
+* u12  net-_u11-pad2_ net-_u12-pad2_ d_inverter
+* u13  net-_u13-pad1_ net-_u10-pad1_ net-_u13-pad3_ d_nor
+* u14  net-_u11-pad2_ net-_u13-pad1_ d_inverter
+* u15  net-_u13-pad3_ net-_u11-pad1_ net-_u15-pad3_ d_nor
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+m2 net-_m2-pad1_ net-_m2-pad2_ net-_m2-pad3_ net-_m2-pad3_ CMOSP W=100u L=100u M=1
+* u17  net-_u15-pad3_ net-_m2-pad2_ dac_bridge_1
+m3 net-_m1-pad1_ net-_m1-pad2_ net-_m2-pad1_ net-_m2-pad3_ CMOSP W=100u L=100u M=1
+* u18  net-_m1-pad1_ net-_u11-pad2_ adc_bridge_1
+* u16  net-_u10-pad1_ net-_m1-pad2_ dac_bridge_1
+a1 net-_u1-pad1_ net-_u1-pad2_ u1
+a2 net-_u1-pad2_ net-_u5-pad2_ u5
+a3 net-_u19-pad2_ net-_u2-pad2_ u2
+a4 net-_u19-pad3_ net-_u11-pad1_ u3
+a5 [net-_u5-pad2_ net-_u2-pad2_ ] net-_u4-pad2_ u8
+a6 [net-_u19-pad10_ ] [net-_u4-pad2_ ] [net-_u11-pad1_ ] [net-_u12-pad2_ ] [net-_u10-pad1_ ] u4
+a7 net-_u10-pad3_ net-_u6-pad2_ u6
+a8 net-_u10-pad3_ net-_u19-pad4_ u9
+a9 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a10 net-_u6-pad2_ net-_u19-pad5_ u7
+a11 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u10-pad2_ u11
+a12 net-_u11-pad2_ net-_u12-pad2_ u12
+a13 [net-_u13-pad1_ net-_u10-pad1_ ] net-_u13-pad3_ u13
+a14 net-_u11-pad2_ net-_u13-pad1_ u14
+a15 [net-_u13-pad3_ net-_u11-pad1_ ] net-_u15-pad3_ u15
+a16 [net-_u15-pad3_ ] [net-_m2-pad2_ ] u17
+a17 [net-_m1-pad1_ ] [net-_u11-pad2_ ] u18
+a18 [net-_u10-pad1_ ] [net-_m1-pad2_ ] u16
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             cd4098_latch, NgSpice Name: cd4098_latch
+.model u4 cd4098_latch(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u10 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u11 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u13 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nor, NgSpice Name: d_nor
+.model u15 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u17 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u18 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u16 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Control Statements
+
+.ends CD4098
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4098/CD4098_Previous_Values.xml b/library/SubcircuitLibrary/CD4098/CD4098_Previous_Values.xml
new file mode 100644
index 000000000..d5270ce15
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/CD4098_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u1 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u1><u5 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u5><u2 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u3><u8 name="type">d_nand<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u8><u4 name="type">cd4098_latch<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /><field19 name="Enter Instance ID (Between 0-99)" /></u4><u6 name="type">d_inverter<field20 name="Enter Rise Delay (default=1.0e-9)" /><field21 name="Enter Fall Delay (default=1.0e-9)" /><field22 name="Enter Input Load (default=1.0e-12)" /></u6><u9 name="type">d_inverter<field23 name="Enter Rise Delay (default=1.0e-9)" /><field24 name="Enter Fall Delay (default=1.0e-9)" /><field25 name="Enter Input Load (default=1.0e-12)" /></u9><u10 name="type">d_nor<field26 name="Enter Rise Delay (default=1.0e-9)" /><field27 name="Enter Fall Delay (default=1.0e-9)" /><field28 name="Enter Input Load (default=1.0e-12)" /></u10><u7 name="type">d_inverter<field29 name="Enter Rise Delay (default=1.0e-9)" /><field30 name="Enter Fall Delay (default=1.0e-9)" /><field31 name="Enter Input Load (default=1.0e-12)" /></u7><u11 name="type">d_nor<field32 name="Enter Rise Delay (default=1.0e-9)" /><field33 name="Enter Fall Delay (default=1.0e-9)" /><field34 name="Enter Input Load (default=1.0e-12)" /></u11><u12 name="type">d_inverter<field35 name="Enter Rise Delay (default=1.0e-9)" /><field36 name="Enter Fall Delay (default=1.0e-9)" /><field37 name="Enter Input Load (default=1.0e-12)" /></u12><u13 name="type">d_nor<field38 name="Enter Rise Delay (default=1.0e-9)" /><field39 name="Enter Fall Delay (default=1.0e-9)" /><field40 name="Enter Input Load (default=1.0e-12)" /></u13><u14 name="type">d_inverter<field41 name="Enter Rise Delay (default=1.0e-9)" /><field42 name="Enter Fall Delay (default=1.0e-9)" /><field43 name="Enter Input Load (default=1.0e-12)" /></u14><u15 name="type">d_nor<field44 name="Enter Rise Delay (default=1.0e-9)" /><field45 name="Enter Fall Delay (default=1.0e-9)" /><field46 name="Enter Input Load (default=1.0e-12)" /></u15><u17 name="type">dac_bridge<field47 name="Enter value for out_low (default=0.0)" /><field48 name="Enter value for out_high (default=5.0)" /><field49 name="Enter value for out_undef (default=0.5)" /><field50 name="Enter value for input load (default=1.0e-12)" /><field51 name="Enter the Rise Time (default=1.0e-9)" /><field52 name="Enter the Fall Time (default=1.0e-9)" /></u17><u18 name="type">adc_bridge<field53 name="Enter value for in_low (default=1.0)" /><field54 name="Enter value for in_high (default=2.0)" /><field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /></u18><u16 name="type">dac_bridge<field57 name="Enter value for out_low (default=0.0)" /><field58 name="Enter value for out_high (default=5.0)" /><field59 name="Enter value for out_undef (default=0.5)" /><field60 name="Enter value for input load (default=1.0e-12)" /><field61 name="Enter the Rise Time (default=1.0e-9)" /><field62 name="Enter the Fall Time (default=1.0e-9)" /></u16><u20 name="type">dac_bridge<field63 name="Enter value for out_low (default=0.0)" /><field64 name="Enter value for out_high (default=5.0)" /><field65 name="Enter value for out_undef (default=0.5)" /><field66 name="Enter value for input load (default=1.0e-12)" /><field67 name="Enter the Rise Time (default=1.0e-9)" /><field68 name="Enter the Fall Time (default=1.0e-9)" /></u20></model><devicemodel><m1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m1><m2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m2><m3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m3></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4098/CD4098_latch.v b/library/SubcircuitLibrary/CD4098/CD4098_latch.v
new file mode 100644
index 000000000..85e13b4ec
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/CD4098_latch.v
@@ -0,0 +1,18 @@
+ module CD4098_latch(
+input D,
+input C,
+input R1,
+input R2,
+output reg Q);
+
+ 
+
+always@(posedge R1 or posedge R2 or posedge C)
+begin
+if(R1 || R2)
+Q<=0;
+else
+Q<=D;
+end
+endmodule 
+
diff --git a/library/SubcircuitLibrary/CD4098/CD4098_test-cache.lib b/library/SubcircuitLibrary/CD4098/CD4098_test-cache.lib
new file mode 100644
index 000000000..e9e616527
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/CD4098_test-cache.lib
@@ -0,0 +1,178 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# DC
+#
+DEF DC v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 w
+X - 2 0 -450 300 U 50 50 1 1 w
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_1
+#
+DEF adc_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_2
+#
+DEF adc_bridge_2 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_2" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -100 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X OUT1 3 550 50 200 L 50 50 1 1 O
+X OUT2 4 550 -50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_2
+#
+DEF dac_bridge_2 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_2" 50 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -250 200 350 -100 0 1 0 N
+X IN1 1 -450 50 200 R 50 50 1 1 I
+X IN2 2 -450 -50 200 R 50 50 1 1 I
+X OUT1 3 550 50 200 L 50 50 1 1 O
+X OUT4 4 550 -50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_CP1
+#
+DEF eSim_CP1 C 0 10 N N 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_CP1" 25 -100 50 H V L CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+ALIAS capacitor_polarised
+$FPLIST
+ CP_*
+$ENDFPLIST
+DRAW
+A 0 -150 128 1287 513 0 1 20 N -80 -50 80 -50
+P 2 0 1 20 -80 30 80 30 N
+P 2 0 1 0 -70 90 -30 90 N
+P 2 0 1 0 -50 70 -50 110 N
+X ~ 1 0 150 110 D 50 50 1 1 P
+X ~ 2 0 -150 130 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_GND
+#
+DEF eSim_GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "eSim_GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# mono
+#
+DEF mono x 0 40 Y Y 1 F N
+F0 "x" 0 -650 60 H V C CNN
+F1 "mono" 0 650 60 H V C CNN
+F2 "" 0 650 60 H I C CNN
+F3 "" 0 650 60 H I C CNN
+DRAW
+S -500 400 550 -550 0 1 0 N
+X TR_plus 1 -700 300 200 R 50 50 1 1 I
+X TR_minus 2 -700 100 200 R 50 50 1 1 I
+X RST 3 -700 -100 200 R 50 50 1 1 I
+X Q 4 750 300 200 L 50 50 1 1 O
+X Q_bar 5 750 100 200 L 50 50 1 1 O
+X VDD 6 -700 -300 200 R 50 50 1 1 I
+X VSS 7 750 -150 200 L 50 50 1 1 I
+X Cx 8 750 -350 200 L 50 50 1 1 I
+X RxCx 9 -700 -450 200 R 50 50 1 1 I
+X DVCC 10 750 -500 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# pulse
+#
+DEF pulse v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "pulse" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -25 -450 501 928 871 0 1 0 N -50 50 0 50
+A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50
+A 75 600 551 -926 -873 0 1 0 N 50 50 100 50
+A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50
+A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50
+A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/CD4098/CD4098_test.cir b/library/SubcircuitLibrary/CD4098/CD4098_test.cir
new file mode 100644
index 000000000..5e71b4e94
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/CD4098_test.cir
@@ -0,0 +1,26 @@
+* C:\Users\pavithra\eSim-Workspace\CD4098_test\CD4098_test.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/26/25 15:32:18
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U1  trig rst Net-_U1-Pad3_ Net-_U1-Pad4_ adc_bridge_2		
+v1  trig GND pulse		
+v2  rst GND pulse		
+C1  Net-_C1-Pad1_ Net-_C1-Pad2_ 1u		
+R1  Net-_R1-Pad1_ Net-_C1-Pad2_ 5k		
+U4  Net-_U4-Pad1_ Net-_U4-Pad2_ Q Q_bar dac_bridge_2		
+U5  Q plot_v1		
+U6  Q_bar plot_v1		
+U2  rst plot_v1		
+U3  trig plot_v1		
+x1  Net-_U1-Pad3_ Net-_U7-Pad2_ Net-_U1-Pad4_ Net-_U4-Pad1_ Net-_U4-Pad2_ Net-_R1-Pad1_ GND Net-_C1-Pad1_ Net-_U8-Pad2_ Net-_U7-Pad2_ mono		
+U7  Net-_U7-Pad1_ Net-_U7-Pad2_ adc_bridge_1		
+v3  Net-_U7-Pad1_ GND DC		
+U8  Net-_C1-Pad2_ Net-_U8-Pad2_ adc_bridge_1		
+R2  Net-_C1-Pad2_ Net-_C1-Pad1_ 1k		
+v4  Net-_R1-Pad1_ GND DC		
+
+.end
diff --git a/library/SubcircuitLibrary/CD4098/CD4098_test.cir.out b/library/SubcircuitLibrary/CD4098/CD4098_test.cir.out
new file mode 100644
index 000000000..707d438a0
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/CD4098_test.cir.out
@@ -0,0 +1,43 @@
+ * c:\users\pavithra\esim-workspace\cd4098_test\cd4098_test.cir
+
+.include CD4098.sub
+* u1  trig rst net-_u1-pad3_ net-_u1-pad4_ adc_bridge_2
+v1  trig gnd pulse(0 5 2 0.1n 0.1n 0.125 3)
+v2  rst gnd pulse(5 0 1 0.1n 0.1n 0.3 3)
+c1  net-_c1-pad1_ net-_c1-pad2_ 1u
+r1  net-_r1-pad1_ net-_c1-pad2_ 5k
+* u4  net-_u4-pad1_ net-_u4-pad2_ q q_bar dac_bridge_2
+* u5  q plot_v1
+* u6  q_bar plot_v1
+* u2  rst plot_v1
+* u3  trig plot_v1
+x1 net-_u1-pad3_ net-_u7-pad2_ net-_u1-pad4_ net-_u4-pad1_ net-_u4-pad2_ net-_r1-pad1_ gnd net-_c1-pad1_ net-_u8-pad2_ net-_u7-pad2_ CD4098
+* u7  net-_u7-pad1_ net-_u7-pad2_ adc_bridge_1
+v3 net-_u7-pad1_ gnd  dc 5
+* u8  net-_c1-pad2_ net-_u8-pad2_ adc_bridge_1
+r2  net-_c1-pad2_ net-_c1-pad1_ 1k
+v4 net-_r1-pad1_ gnd  dc 0
+a1 [trig rst ] [net-_u1-pad3_ net-_u1-pad4_ ] u1
+a2 [net-_u4-pad1_ net-_u4-pad2_ ] [q q_bar ] u4
+a3 [net-_u7-pad1_ ] [net-_u7-pad2_ ] u7
+a4 [net-_c1-pad2_ ] [net-_u8-pad2_ ] u8
+* Schematic Name:                             adc_bridge_2, NgSpice Name: adc_bridge
+.model u1 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_2, NgSpice Name: dac_bridge
+.model u4 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u7 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u8 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+.tran 1e-00 3e-00 0e-00
+.ic V(q)=0
+.ic V(q_bar)=5
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(q)+6 v(q_bar)+12v(rst)+18 v(trig)
+.endc
+.end
diff --git a/library/SubcircuitLibrary/CD4098/CD4098_test.pro b/library/SubcircuitLibrary/CD4098/CD4098_test.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/CD4098_test.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/CD4098/CD4098_test.proj b/library/SubcircuitLibrary/CD4098/CD4098_test.proj
new file mode 100644
index 000000000..7a80cae0d
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/CD4098_test.proj
@@ -0,0 +1 @@
+schematicFile CD4098_test.sch
diff --git a/library/SubcircuitLibrary/CD4098/CD4098_test.sch b/library/SubcircuitLibrary/CD4098/CD4098_test.sch
new file mode 100644
index 000000000..d76034731
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/CD4098_test.sch
@@ -0,0 +1,405 @@
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+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:CD4098_test-cache
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+EELAYER END
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diff --git a/library/SubcircuitLibrary/CD4098/CD4098_test_Previous_Values.xml b/library/SubcircuitLibrary/CD4098/CD4098_test_Previous_Values.xml
new file mode 100644
index 000000000..ce4cec994
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/CD4098_test_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source><v3 name="Source type">dc<field1 name="Value">5</field1></v3><v1 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">2</field3><field4 name="Rise Time">0.1n</field4><field5 name="Fall Time">0.1n</field5><field5 name="Pulse width">0.125</field5><field5 name="Period">3</field5></v1><v2 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">1</field3><field4 name="Rise Time">0.1n</field4><field5 name="Fall Time">0.1n</field5><field5 name="Pulse width">0.3</field5><field5 name="Period">3</field5></v2><v4 name="Source type">dc<field1 name="Value">0</field1></v4></source><model><u1 name="type">adc_bridge<field1 name="Enter value for in_low (default=1.0)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter Fall Delay (default=1.0e-9)" /></u1><u4 name="type">dac_bridge<field5 name="Enter value for out_low (default=0.0)" /><field6 name="Enter value for out_high (default=5.0)" /><field7 name="Enter value for out_undef (default=0.5)" /><field8 name="Enter value for input load (default=1.0e-12)" /><field9 name="Enter the Rise Time (default=1.0e-9)" /><field10 name="Enter the Fall Time (default=1.0e-9)" /></u4><u7 name="type">adc_bridge<field11 name="Enter value for in_low (default=1.0)" /><field12 name="Enter value for in_high (default=2.0)" /><field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /></u7><u8 name="type">adc_bridge<field15 name="Enter value for in_low (default=1.0)" /><field16 name="Enter value for in_high (default=2.0)" /><field17 name="Enter Rise Delay (default=1.0e-9)" /><field18 name="Enter Fall Delay (default=1.0e-9)" /></u8></model><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\CD4098</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">1</field2><field3 name="Stop Time">3</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4098/NMOS-0.5um.lib b/library/SubcircuitLibrary/CD4098/NMOS-0.5um.lib
new file mode 100644
index 000000000..2e6f4635c
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/NMOS-0.5um.lib
@@ -0,0 +1,6 @@
+.model mos_n NMOS( TPG=1 TOX=9.5n CJ=550u ETA=0.02125 VMAX=1.8E05 
++ GAMMA=0.62 CGSO=0.3n LD=50n MJSW=0.35 PB=1.1 
++ CGBO=0.45n XJ=0.2U CGDO=0.3n KAPPA=0.1 LEVEL=3 
++ VTO=0.6 NFS=7.20E11 THETA=0.23 CJSW=0.3n PHI=0.7 
++ RSH=2.0 MJ=0.6 UO=420 KP=156u DELTA=0.88 
++ NSUB=1.40E17 )
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4098/NMOS-180nm.lib b/library/SubcircuitLibrary/CD4098/NMOS-180nm.lib
new file mode 100644
index 000000000..51e9b1196
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/NMOS-180nm.lib
@@ -0,0 +1,13 @@
+.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 
++            K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 
++            DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18
++            UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4
++            A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0
++            XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0
++            CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3    
++            PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1
++            PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1
++            WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12
++            CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 
++            MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 
++            PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3)
diff --git a/library/SubcircuitLibrary/CD4098/NMOS-5um.lib b/library/SubcircuitLibrary/CD4098/NMOS-5um.lib
new file mode 100644
index 000000000..a237e1fe3
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/NMOS-5um.lib
@@ -0,0 +1,5 @@
+* 5um technology
+
+.model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7 
++ Level=1
++ Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n  )
diff --git a/library/SubcircuitLibrary/CD4098/PMOS-0.5um.lib b/library/SubcircuitLibrary/CD4098/PMOS-0.5um.lib
new file mode 100644
index 000000000..848e8b051
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/PMOS-0.5um.lib
@@ -0,0 +1,6 @@
+.model mos_p PMOS( TPG=-1 TOX=9.5n CJ=950u ETA=0.025 VMAX=0.3u 
++ GAMMA=0.52 CGSO=0.35n LD=70n MJSW=0.25 PB=1 
++ CGBO=0.45n XJ=0.2U CGDO=0.35n KAPPA=8.0 LEVEL=3 
++ VTO=-0.6 NFS=6.50E11 THETA=0.2 CJSW=0.2n PHI=0.7 
++ RSH=2.5 MJ=0.5 UO=130 KP=48u DELTA=0.25 
++ NSUB=1.0E17 )
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4098/PMOS-180nm.lib b/library/SubcircuitLibrary/CD4098/PMOS-180nm.lib
new file mode 100644
index 000000000..032b5b95e
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/PMOS-180nm.lib
@@ -0,0 +1,11 @@
+.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015
++            K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363
++            DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478
++            AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677
++            PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 
++            VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148
++            DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10
++            PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9
++            UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5
++            CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8            +            MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3    
++            WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3)
diff --git a/library/SubcircuitLibrary/CD4098/PMOS-5um.lib b/library/SubcircuitLibrary/CD4098/PMOS-5um.lib
new file mode 100644
index 000000000..9c3ed9760
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/PMOS-5um.lib
@@ -0,0 +1,5 @@
+*5um technology
+
+.model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65
++ Level=1
++ Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n  )
diff --git a/library/SubcircuitLibrary/CD4098/analysis b/library/SubcircuitLibrary/CD4098/analysis
new file mode 100644
index 000000000..a2a273682
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/analysis
@@ -0,0 +1 @@
+.tran 1e-00 3e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/LM3900/D.lib b/library/SubcircuitLibrary/LM3900/D.lib
new file mode 100644
index 000000000..f53bf3e03
--- /dev/null
+++ b/library/SubcircuitLibrary/LM3900/D.lib
@@ -0,0 +1,2 @@
+.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04)
+
diff --git a/library/SubcircuitLibrary/LM3900/LM3900-cache.lib b/library/SubcircuitLibrary/LM3900/LM3900-cache.lib
new file mode 100644
index 000000000..fea7ae574
--- /dev/null
+++ b/library/SubcircuitLibrary/LM3900/LM3900-cache.lib
@@ -0,0 +1,147 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# dc
+#
+DEF dc I 0 40 Y Y 1 F N
+F0 "I" -200 100 60 H V C CNN
+F1 "dc" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+P 2 0 1 0 0 -100 0 -100 N
+P 2 0 1 0 0 100 -50 50 N
+P 2 0 1 0 0 100 0 -100 N
+P 2 0 1 0 0 100 50 50 N
+X ~ 1 0 450 300 D 50 50 1 1 P
+X ~ 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_C
+#
+DEF eSim_C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_C" 25 -100 50 H V L CNN
+F2 "" 38 -150 30 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS capacitor
+$FPLIST
+ C_*
+$ENDFPLIST
+DRAW
+P 2 0 1 20 -80 -30 80 -30 N
+P 2 0 1 20 -80 30 80 30 N
+X ~ 1 0 150 110 D 40 40 1 1 P
+X ~ 2 0 -150 110 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_Diode
+#
+DEF eSim_Diode D 0 40 N N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "eSim_Diode" 0 -100 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ TO-???*
+ *SingleDiode
+ *_Diode_*
+ *SingleDiode*
+ D_*
+$ENDFPLIST
+DRAW
+T 0 -100 50 60 0 0 0 A Normal 0 C C
+T 0 100 50 60 0 0 0 K Normal 0 C C
+P 2 0 1 6 50 50 50 -50 N
+P 3 0 1 0 -50 50 50 0 -50 -50 F
+X A 1 -150 0 100 R 40 40 1 1 P
+X K 2 150 0 100 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_PNP
+#
+DEF eSim_PNP Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_PNP" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/LM3900/LM3900.cir b/library/SubcircuitLibrary/LM3900/LM3900.cir
new file mode 100644
index 000000000..2de03b570
--- /dev/null
+++ b/library/SubcircuitLibrary/LM3900/LM3900.cir
@@ -0,0 +1,20 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\LM3900\LM3900.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/29/25 15:20:35
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+Q1  Net-_Q1-Pad1_ Net-_D1-Pad1_ Net-_C1-Pad2_ eSim_NPN		
+Q5  Net-_I1-Pad2_ Net-_I1-Pad1_ Net-_I2-Pad2_ eSim_NPN		
+Q2  Net-_C1-Pad1_ Net-_Q1-Pad1_ Net-_C1-Pad2_ eSim_NPN		
+Q4  Net-_C1-Pad2_ Net-_C1-Pad1_ Net-_I2-Pad2_ eSim_PNP		
+Q3  Net-_I2-Pad2_ Net-_C1-Pad1_ Net-_I1-Pad1_ eSim_PNP		
+D1  Net-_D1-Pad1_ Net-_C1-Pad2_ eSim_Diode		
+I2  Net-_C1-Pad2_ Net-_I2-Pad2_ 1.3m		
+I1  Net-_I1-Pad1_ Net-_I1-Pad2_ 200u		
+C1  Net-_C1-Pad1_ Net-_C1-Pad2_ 10p		
+U1  Net-_Q1-Pad1_ Net-_D1-Pad1_ Net-_I2-Pad2_ Net-_I1-Pad2_ Net-_C1-Pad2_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/LM3900/LM3900.cir.out b/library/SubcircuitLibrary/LM3900/LM3900.cir.out
new file mode 100644
index 000000000..394ca23a3
--- /dev/null
+++ b/library/SubcircuitLibrary/LM3900/LM3900.cir.out
@@ -0,0 +1,24 @@
+* c:\fossee\esim\library\subcircuitlibrary\lm3900\lm3900.cir
+
+.include PNP.lib
+.include NPN.lib
+.include D.lib
+q1 net-_q1-pad1_ net-_d1-pad1_ net-_c1-pad2_ Q2N2222
+q5 net-_i1-pad2_ net-_i1-pad1_ net-_i2-pad2_ Q2N2222
+q2 net-_c1-pad1_ net-_q1-pad1_ net-_c1-pad2_ Q2N2222
+q4 net-_c1-pad2_ net-_c1-pad1_ net-_i2-pad2_ Q2N2907A
+q3 net-_i2-pad2_ net-_c1-pad1_ net-_i1-pad1_ Q2N2907A
+d1 net-_d1-pad1_ net-_c1-pad2_ 1N4148
+i2  net-_c1-pad2_ net-_i2-pad2_ 1.3m
+i1  net-_i1-pad1_ net-_i1-pad2_ 200u
+c1  net-_c1-pad1_ net-_c1-pad2_ 10p
+* u1  net-_q1-pad1_ net-_d1-pad1_ net-_i2-pad2_ net-_i1-pad2_ net-_c1-pad2_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/LM3900/LM3900.pro b/library/SubcircuitLibrary/LM3900/LM3900.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/LM3900/LM3900.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/LM3900/LM3900.proj b/library/SubcircuitLibrary/LM3900/LM3900.proj
new file mode 100644
index 000000000..21c9011d4
--- /dev/null
+++ b/library/SubcircuitLibrary/LM3900/LM3900.proj
@@ -0,0 +1 @@
+schematicFile LM3900.sch
diff --git a/library/SubcircuitLibrary/LM3900/LM3900.sch b/library/SubcircuitLibrary/LM3900/LM3900.sch
new file mode 100644
index 000000000..a7a7d4cb6
--- /dev/null
+++ b/library/SubcircuitLibrary/LM3900/LM3900.sch
@@ -0,0 +1,276 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:LM3900-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L eSim_NPN Q1
+U 1 1 6835ED47
+P 3300 4550
+F 0 "Q1" H 3200 4600 50  0000 R CNN
+F 1 "eSim_NPN" H 3250 4700 50  0000 R CNN
+F 2 "" H 3500 4650 29  0000 C CNN
+F 3 "" H 3300 4550 60  0000 C CNN
+	1    3300 4550
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_NPN Q5
+U 1 1 6835ED7F
+P 5100 2650
+F 0 "Q5" H 5000 2700 50  0000 R CNN
+F 1 "eSim_NPN" H 5050 2800 50  0000 R CNN
+F 2 "" H 5300 2750 29  0000 C CNN
+F 3 "" H 5100 2650 60  0000 C CNN
+	1    5100 2650
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_NPN Q2
+U 1 1 6835EDA3
+P 3750 4050
+F 0 "Q2" H 3650 4100 50  0000 R CNN
+F 1 "eSim_NPN" H 3700 4200 50  0000 R CNN
+F 2 "" H 3950 4150 29  0000 C CNN
+F 3 "" H 3750 4050 60  0000 C CNN
+	1    3750 4050
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_PNP Q4
+U 1 1 6835EDDD
+P 4200 3650
+F 0 "Q4" H 4100 3700 50  0000 R CNN
+F 1 "eSim_PNP" H 4150 3800 50  0000 R CNN
+F 2 "" H 4400 3750 29  0000 C CNN
+F 3 "" H 4200 3650 60  0000 C CNN
+	1    4200 3650
+	1    0    0    1   
+$EndComp
+$Comp
+L eSim_PNP Q3
+U 1 1 6835EE0A
+P 4200 3000
+F 0 "Q3" H 4100 3050 50  0000 R CNN
+F 1 "eSim_PNP" H 4150 3150 50  0000 R CNN
+F 2 "" H 4400 3100 29  0000 C CNN
+F 3 "" H 4200 3000 60  0000 C CNN
+	1    4200 3000
+	1    0    0    1   
+$EndComp
+$Comp
+L eSim_Diode D1
+U 1 1 6835EE44
+P 2900 4700
+F 0 "D1" H 2900 4800 50  0000 C CNN
+F 1 "eSim_Diode" H 2900 4600 50  0000 C CNN
+F 2 "" H 2900 4700 60  0000 C CNN
+F 3 "" H 2900 4700 60  0000 C CNN
+	1    2900 4700
+	0    1    1    0   
+$EndComp
+$Comp
+L dc I2
+U 1 1 6835EE74
+P 5200 3900
+F 0 "I2" H 5000 4000 60  0000 C CNN
+F 1 "1.3m" H 5000 3850 60  0000 C CNN
+F 2 "R1" H 4900 3900 60  0000 C CNN
+F 3 "" H 5200 3900 60  0000 C CNN
+	1    5200 3900
+	1    0    0    1   
+$EndComp
+$Comp
+L dc I1
+U 1 1 6835EEBA
+P 4300 2200
+F 0 "I1" H 4100 2300 60  0000 C CNN
+F 1 "200u" H 4100 2150 60  0000 C CNN
+F 2 "R1" H 4000 2200 60  0000 C CNN
+F 3 "" H 4300 2200 60  0000 C CNN
+	1    4300 2200
+	1    0    0    1   
+$EndComp
+$Comp
+L capacitor C1
+U 1 1 6835F4C8
+P 4050 4300
+F 0 "C1" H 4075 4400 50  0000 L CNN
+F 1 "10p" H 4075 4200 50  0000 L CNN
+F 2 "" H 4088 4150 30  0000 C CNN
+F 3 "" H 4050 4300 60  0000 C CNN
+	1    4050 4300
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	3400 4350 3400 4050
+Wire Wire Line
+	2700 4050 3550 4050
+Wire Wire Line
+	3850 3850 3850 3650
+Wire Wire Line
+	3850 3650 4000 3650
+Wire Wire Line
+	4300 3200 4300 3450
+Wire Wire Line
+	4000 3650 4000 3000
+Wire Wire Line
+	4300 2650 4300 2800
+Wire Wire Line
+	4900 2650 4300 2650
+Wire Wire Line
+	4300 1750 5350 1750
+Wire Wire Line
+	5200 1750 5200 2450
+Connection ~ 5200 1750
+Wire Wire Line
+	5200 2850 5200 3450
+Wire Wire Line
+	2550 4550 3100 4550
+Wire Wire Line
+	2900 4850 5200 4850
+Wire Wire Line
+	3400 4850 3400 4750
+Wire Wire Line
+	3850 4850 3850 4250
+Connection ~ 3400 4850
+Wire Wire Line
+	4300 4850 4300 3850
+Connection ~ 3850 4850
+Wire Wire Line
+	5200 4850 5200 4350
+Connection ~ 4300 4850
+Wire Wire Line
+	4300 3300 5200 3300
+Connection ~ 5200 3300
+Connection ~ 4300 3300
+Wire Wire Line
+	4050 4150 4050 3650
+Wire Wire Line
+	4050 3650 3950 3650
+Connection ~ 3950 3650
+Wire Wire Line
+	4050 4450 4050 4850
+Connection ~ 4050 4850
+Wire Wire Line
+	2900 4950 2900 4850
+$Comp
+L PORT U1
+U 1 1 6835FDE8
+P 2450 4050
+F 0 "U1" H 2500 4150 30  0000 C CNN
+F 1 "PORT" H 2450 4050 30  0000 C CNN
+F 2 "" H 2450 4050 60  0000 C CNN
+F 3 "" H 2450 4050 60  0000 C CNN
+	1    2450 4050
+	1    0    0    -1  
+$EndComp
+Connection ~ 2900 4550
+$Comp
+L PORT U1
+U 3 1 6835FE7F
+P 5750 3400
+F 0 "U1" H 5800 3500 30  0000 C CNN
+F 1 "PORT" H 5750 3400 30  0000 C CNN
+F 2 "" H 5750 3400 60  0000 C CNN
+F 3 "" H 5750 3400 60  0000 C CNN
+	3    5750 3400
+	-1   0    0    -1  
+$EndComp
+Connection ~ 3400 4050
+$Comp
+L PORT U1
+U 5 1 6835FEF1
+P 2400 4950
+F 0 "U1" H 2450 5050 30  0000 C CNN
+F 1 "PORT" H 2400 4950 30  0000 C CNN
+F 2 "" H 2400 4950 60  0000 C CNN
+F 3 "" H 2400 4950 60  0000 C CNN
+	5    2400 4950
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5200 3400 5500 3400
+Connection ~ 5200 3400
+$Comp
+L PORT U1
+U 4 1 6835FFC6
+P 5650 1950
+F 0 "U1" H 5700 2050 30  0000 C CNN
+F 1 "PORT" H 5650 1950 30  0000 C CNN
+F 2 "" H 5650 1950 60  0000 C CNN
+F 3 "" H 5650 1950 60  0000 C CNN
+	4    5650 1950
+	-1   0    0    -1  
+$EndComp
+Wire Wire Line
+	5350 1750 5350 1950
+Wire Wire Line
+	5350 1950 5400 1950
+$Comp
+L PORT U1
+U 2 1 68360C1F
+P 2300 4550
+F 0 "U1" H 2350 4650 30  0000 C CNN
+F 1 "PORT" H 2300 4550 30  0000 C CNN
+F 2 "" H 2300 4550 60  0000 C CNN
+F 3 "" H 2300 4550 60  0000 C CNN
+	2    2300 4550
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2650 4950 2900 4950
+Text Label 5300 3350 0    60   ~ 0
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/LM3900/LM3900.sub b/library/SubcircuitLibrary/LM3900/LM3900.sub
new file mode 100644
index 000000000..d5849dff4
--- /dev/null
+++ b/library/SubcircuitLibrary/LM3900/LM3900.sub
@@ -0,0 +1,18 @@
+* Subcircuit LM3900
+.subckt LM3900 net-_q1-pad1_ net-_d1-pad1_ net-_i2-pad2_ net-_i1-pad2_ net-_c1-pad2_ 
+* c:\fossee\esim\library\subcircuitlibrary\lm3900\lm3900.cir
+.include PNP.lib
+.include NPN.lib
+.include D.lib
+q1 net-_q1-pad1_ net-_d1-pad1_ net-_c1-pad2_ Q2N2222
+q5 net-_i1-pad2_ net-_i1-pad1_ net-_i2-pad2_ Q2N2222
+q2 net-_c1-pad1_ net-_q1-pad1_ net-_c1-pad2_ Q2N2222
+q4 net-_c1-pad2_ net-_c1-pad1_ net-_i2-pad2_ Q2N2907A
+q3 net-_i2-pad2_ net-_c1-pad1_ net-_i1-pad1_ Q2N2907A
+d1 net-_d1-pad1_ net-_c1-pad2_ 1N4148
+i2  net-_c1-pad2_ net-_i2-pad2_ 1.3m
+i1  net-_i1-pad1_ net-_i1-pad2_ 200u
+c1  net-_c1-pad1_ net-_c1-pad2_ 10p
+* Control Statements
+
+.ends LM3900
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/LM3900/LM3900_Previous_Values.xml b/library/SubcircuitLibrary/LM3900/LM3900_Previous_Values.xml
new file mode 100644
index 000000000..d9c6cbb51
--- /dev/null
+++ b/library/SubcircuitLibrary/LM3900/LM3900_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source><i2 name="Source type">1.3m</i2><i1 name="Source type">200u</i1></source><model /><devicemodel><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q4><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q3><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/LM3900/LM3900_test-cache.lib b/library/SubcircuitLibrary/LM3900/LM3900_test-cache.lib
new file mode 100644
index 000000000..6c5a94aea
--- /dev/null
+++ b/library/SubcircuitLibrary/LM3900/LM3900_test-cache.lib
@@ -0,0 +1,121 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# DC
+#
+DEF DC v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 w
+X - 2 0 -450 300 U 50 50 1 1 w
+ENDDRAW
+ENDDEF
+#
+# LM3900
+#
+DEF LM3900 X 0 40 Y Y 1 F N
+F0 "X" 0 -400 60 H V C CNN
+F1 "LM3900" 0 500 60 H V C CNN
+F2 "" 0 500 60 H I C CNN
+F3 "" 0 500 60 H I C CNN
+DRAW
+P 4 0 1 0 200 0 -150 300 -150 -300 200 0 N
+X inv 1 -350 150 200 R 50 50 1 1 I
+X non_inv 2 -350 -100 200 R 50 50 1 1 I
+X Out 3 400 0 200 L 50 50 1 1 O
+X Vcc 4 50 300 200 D 50 50 1 1 I
+X Gnd 5 50 -300 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# eSim_C
+#
+DEF eSim_C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_C" 25 -100 50 H V L CNN
+F2 "" 38 -150 30 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS capacitor
+$FPLIST
+ C_*
+$ENDFPLIST
+DRAW
+P 2 0 1 20 -80 -30 80 -30 N
+P 2 0 1 20 -80 30 80 30 N
+X ~ 1 0 150 110 D 40 40 1 1 P
+X ~ 2 0 -150 110 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_GND
+#
+DEF eSim_GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "eSim_GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# sine
+#
+DEF sine v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "sine" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -50 0 50 1 1799 0 1 0 N 0 0 -100 0
+A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 0 1 1 I
+X - 2 0 -450 300 U 50 0 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/LM3900/LM3900_test.cir b/library/SubcircuitLibrary/LM3900/LM3900_test.cir
new file mode 100644
index 000000000..90ef51162
--- /dev/null
+++ b/library/SubcircuitLibrary/LM3900/LM3900_test.cir
@@ -0,0 +1,21 @@
+* C:\Users\pavithra\eSim-Workspace\LM3900_test\LM3900_test.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/29/25 15:21:32
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+R1  Net-_C1-Pad1_ Net-_R1-Pad2_ 10k		
+R2  Net-_R2-Pad1_ Net-_R2-Pad2_ 39k		
+R3  Net-_R1-Pad2_ Net-_C2-Pad2_ 100k		
+R4  out GND 10k		
+C1  Net-_C1-Pad1_ in 1u		
+C2  out Net-_C2-Pad2_ 1u		
+v1  in GND sine		
+v2  Net-_R2-Pad1_ GND DC		
+U2  out plot_v1		
+U1  in plot_v1		
+X1  Net-_R1-Pad2_ Net-_R2-Pad2_ Net-_C2-Pad2_ Net-_R2-Pad1_ GND LM3900		
+
+.end
diff --git a/library/SubcircuitLibrary/LM3900/LM3900_test.cir.out b/library/SubcircuitLibrary/LM3900/LM3900_test.cir.out
new file mode 100644
index 000000000..efd5ef2c0
--- /dev/null
+++ b/library/SubcircuitLibrary/LM3900/LM3900_test.cir.out
@@ -0,0 +1,24 @@
+* c:\users\pavithra\esim-workspace\lm3900_test\lm3900_test.cir
+
+.include LM3900.sub
+r1  net-_c1-pad1_ net-_r1-pad2_ 10k
+r2  net-_r2-pad1_ net-_r2-pad2_ 39k
+r3  net-_r1-pad2_ net-_c2-pad2_ 100k
+r4  out gnd 10k
+c1  net-_c1-pad1_ in 1u
+c2  out net-_c2-pad2_ 1u
+v1  in gnd sine(0 10m 1k 0 0)
+v2 net-_r2-pad1_ gnd  dc 5
+* u2  out plot_v1
+* u1  in plot_v1
+x1 net-_r1-pad2_ net-_r2-pad2_ net-_c2-pad2_ net-_r2-pad1_ gnd LM3900
+.tran 10e-06 10e-03 0e-03
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(out)  v(in)
+.endc
+.end
diff --git a/library/SubcircuitLibrary/LM3900/LM3900_test.pro b/library/SubcircuitLibrary/LM3900/LM3900_test.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/LM3900/LM3900_test.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/LM3900/LM3900_test.proj b/library/SubcircuitLibrary/LM3900/LM3900_test.proj
new file mode 100644
index 000000000..a2215586a
--- /dev/null
+++ b/library/SubcircuitLibrary/LM3900/LM3900_test.proj
@@ -0,0 +1 @@
+schematicFile LM3900_test.sch
diff --git a/library/SubcircuitLibrary/LM3900/LM3900_test.sch b/library/SubcircuitLibrary/LM3900/LM3900_test.sch
new file mode 100644
index 000000000..9cec7f25d
--- /dev/null
+++ b/library/SubcircuitLibrary/LM3900/LM3900_test.sch
@@ -0,0 +1,277 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L resistor R1
+U 1 1 68382208
+P 4700 3450
+F 0 "R1" H 4750 3580 50  0000 C CNN
+F 1 "10k" H 4750 3400 50  0000 C CNN
+F 2 "" H 4750 3430 30  0000 C CNN
+F 3 "" V 4750 3500 30  0000 C CNN
+	1    4700 3450
+	1    0    0    -1  
+$EndComp
+$Comp
+L resistor R2
+U 1 1 6838222B
+P 4750 3700
+F 0 "R2" H 4800 3830 50  0000 C CNN
+F 1 "39k" H 4800 3650 50  0000 C CNN
+F 2 "" H 4800 3680 30  0000 C CNN
+F 3 "" V 4800 3750 30  0000 C CNN
+	1    4750 3700
+	1    0    0    -1  
+$EndComp
+$Comp
+L resistor R3
+U 1 1 6838224D
+P 5550 2850
+F 0 "R3" H 5600 2980 50  0000 C CNN
+F 1 "100k" H 5600 2800 50  0000 C CNN
+F 2 "" H 5600 2830 30  0000 C CNN
+F 3 "" V 5600 2900 30  0000 C CNN
+	1    5550 2850
+	1    0    0    -1  
+$EndComp
+$Comp
+L resistor R4
+U 1 1 68382273
+P 6500 3900
+F 0 "R4" H 6550 4030 50  0000 C CNN
+F 1 "10k" H 6550 3850 50  0000 C CNN
+F 2 "" H 6550 3880 30  0000 C CNN
+F 3 "" V 6550 3950 30  0000 C CNN
+	1    6500 3900
+	0    1    1    0   
+$EndComp
+$Comp
+L capacitor C1
+U 1 1 6838229D
+P 4150 3400
+F 0 "C1" H 4175 3500 50  0000 L CNN
+F 1 "1u" H 4175 3300 50  0000 L CNN
+F 2 "" H 4188 3250 30  0000 C CNN
+F 3 "" H 4150 3400 60  0000 C CNN
+	1    4150 3400
+	0    1    1    0   
+$EndComp
+$Comp
+L capacitor C2
+U 1 1 683822C6
+P 6150 3550
+F 0 "C2" H 6175 3650 50  0000 L CNN
+F 1 "1u" H 6175 3450 50  0000 L CNN
+F 2 "" H 6188 3400 30  0000 C CNN
+F 3 "" H 6150 3550 60  0000 C CNN
+	1    6150 3550
+	0    1    1    0   
+$EndComp
+$Comp
+L sine v1
+U 1 1 683822F8
+P 3700 3850
+F 0 "v1" H 3500 3950 60  0000 C CNN
+F 1 "sine" H 3500 3800 60  0000 C CNN
+F 2 "R1" H 3400 3850 60  0000 C CNN
+F 3 "" H 3700 3850 60  0000 C CNN
+	1    3700 3850
+	1    0    0    -1  
+$EndComp
+$Comp
+L DC v2
+U 1 1 6838232F
+P 4400 4250
+F 0 "v2" H 4200 4350 60  0000 C CNN
+F 1 "DC" H 4200 4200 60  0000 C CNN
+F 2 "R1" H 4100 4250 60  0000 C CNN
+F 3 "" H 4400 4250 60  0000 C CNN
+	1    4400 4250
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4650 3650 4400 3650
+Wire Wire Line
+	4400 3100 4400 3800
+Wire Wire Line
+	4950 3650 5100 3650
+Wire Wire Line
+	4900 3400 5100 3400
+Wire Wire Line
+	4300 3400 4600 3400
+Wire Wire Line
+	3700 3400 4000 3400
+Wire Wire Line
+	4400 3100 5500 3100
+Wire Wire Line
+	5500 3100 5500 3250
+Connection ~ 4400 3650
+Wire Wire Line
+	5850 3550 6000 3550
+Wire Wire Line
+	6300 3550 6550 3550
+Wire Wire Line
+	6550 3550 6550 3800
+$Comp
+L eSim_GND #PWR01
+U 1 1 6838259D
+P 6550 4300
+F 0 "#PWR01" H 6550 4050 50  0001 C CNN
+F 1 "eSim_GND" H 6550 4150 50  0000 C CNN
+F 2 "" H 6550 4300 50  0001 C CNN
+F 3 "" H 6550 4300 50  0001 C CNN
+	1    6550 4300
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_GND #PWR02
+U 1 1 683825CA
+P 3700 4500
+F 0 "#PWR02" H 3700 4250 50  0001 C CNN
+F 1 "eSim_GND" H 3700 4350 50  0000 C CNN
+F 2 "" H 3700 4500 50  0001 C CNN
+F 3 "" H 3700 4500 50  0001 C CNN
+	1    3700 4500
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_GND #PWR03
+U 1 1 68382602
+P 5500 4000
+F 0 "#PWR03" H 5500 3750 50  0001 C CNN
+F 1 "eSim_GND" H 5500 3850 50  0000 C CNN
+F 2 "" H 5500 4000 50  0001 C CNN
+F 3 "" H 5500 4000 50  0001 C CNN
+	1    5500 4000
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5500 4000 5500 3850
+Wire Wire Line
+	3700 4300 3700 4500
+Wire Wire Line
+	6550 4100 6550 4300
+$Comp
+L eSim_GND #PWR04
+U 1 1 683827B5
+P 4400 4900
+F 0 "#PWR04" H 4400 4650 50  0001 C CNN
+F 1 "eSim_GND" H 4400 4750 50  0000 C CNN
+F 2 "" H 4400 4900 50  0001 C CNN
+F 3 "" H 4400 4900 50  0001 C CNN
+	1    4400 4900
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4400 4700 4400 4900
+Wire Wire Line
+	5050 3400 5050 2800
+Wire Wire Line
+	5050 2800 5450 2800
+Connection ~ 5050 3400
+Wire Wire Line
+	5750 2800 5950 2800
+Wire Wire Line
+	5950 2800 5950 3550
+Connection ~ 5950 3550
+$Comp
+L plot_v1 U2
+U 1 1 68382854
+P 6550 3500
+F 0 "U2" H 6550 4000 60  0000 C CNN
+F 1 "plot_v1" H 6750 3850 60  0000 C CNN
+F 2 "" H 6550 3500 60  0000 C CNN
+F 3 "" H 6550 3500 60  0000 C CNN
+	1    6550 3500
+	1    0    0    -1  
+$EndComp
+$Comp
+L plot_v1 U1
+U 1 1 683828BD
+P 3700 3500
+F 0 "U1" H 3700 4000 60  0000 C CNN
+F 1 "plot_v1" H 3900 3850 60  0000 C CNN
+F 2 "" H 3700 3500 60  0000 C CNN
+F 3 "" H 3700 3500 60  0000 C CNN
+	1    3700 3500
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	3700 3300 3700 3400
+Wire Wire Line
+	6550 3300 6550 3600
+Connection ~ 6550 3600
+Text GLabel 6450 3400 0    60   Input ~ 0
+out
+Wire Wire Line
+	6450 3400 6550 3400
+Connection ~ 6550 3400
+Text GLabel 3550 3350 0    60   Input ~ 0
+in
+Wire Wire Line
+	3550 3350 3700 3350
+Connection ~ 3700 3350
+$Comp
+L LM3900 X1
+U 1 1 68382FF8
+P 5450 3550
+F 0 "X1" H 5450 3150 60  0000 C CNN
+F 1 "LM3900" H 5450 4050 60  0000 C CNN
+F 2 "" H 5450 4050 60  0001 C CNN
+F 3 "" H 5450 4050 60  0001 C CNN
+	1    5450 3550
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/LM3900/LM3900_test_Previous_Values.xml b/library/SubcircuitLibrary/LM3900/LM3900_test_Previous_Values.xml
new file mode 100644
index 000000000..d6bd25985
--- /dev/null
+++ b/library/SubcircuitLibrary/LM3900/LM3900_test_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source><v1 name="Source type">sine<field1 name="Offset Value">0</field1><field2 name="Amplitude">10m</field2><field3 name="Frequency">1k</field3><field4 name="Delay Time" /><field5 name="Damping Factor" /></v1><v2 name="Source type">dc<field1 name="Value">5</field1></v2></source><model /><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\LM3900</field></x1></subcircuit><analysis><ac><field1 name="Lin">false</field1><field2 name="Dec">true</field2><field3 name="Oct">false</field3><field4 name="Start Frequency">10</field4><field5 name="Stop Frequency">100</field5><field6 name="No. of points">10</field6><field7 name="Start Fre Combo">KHz</field7><field8 name="Stop Fre Combo">KHz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">10</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">us</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/LM3900/NPN.lib b/library/SubcircuitLibrary/LM3900/NPN.lib
new file mode 100644
index 000000000..be5f3073a
--- /dev/null
+++ b/library/SubcircuitLibrary/LM3900/NPN.lib
@@ -0,0 +1,4 @@
+.model Q2N2222  NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 
++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p 
++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p 
++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10)
diff --git a/library/SubcircuitLibrary/LM3900/PNP.lib b/library/SubcircuitLibrary/LM3900/PNP.lib
new file mode 100644
index 000000000..7edda0eab
--- /dev/null
+++ b/library/SubcircuitLibrary/LM3900/PNP.lib
@@ -0,0 +1,4 @@
+.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829
++		Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715
++		Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75
++		Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10)
diff --git a/library/SubcircuitLibrary/LM3900/analysis b/library/SubcircuitLibrary/LM3900/analysis
new file mode 100644
index 000000000..6783e70d4
--- /dev/null
+++ b/library/SubcircuitLibrary/LM3900/analysis
@@ -0,0 +1 @@
+.tran 10e-06 10e-03 0e-03
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B-cache.lib b/library/SubcircuitLibrary/MC14016B/MC14016B-cache.lib
new file mode 100644
index 000000000..3b7d214a1
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B-cache.lib
@@ -0,0 +1,128 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_1
+#
+DEF dac_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_N
+#
+DEF eSim_MOS_N M 0 0 Y N 1 F N
+F0 "M" 0 -150 50 H V R CNN
+F1 "eSim_MOS_N" 100 -50 50 H V R CNN
+F2 "" 300 -300 29 H V C CNN
+F3 "" 100 -200 60 H V C CNN
+ALIAS mosfet_n
+DRAW
+C 150 -200 111 0 1 10 N
+P 2 0 1 10 130 -290 130 -250 N
+P 2 0 1 0 130 -270 200 -270 N
+P 2 0 1 10 130 -220 130 -180 N
+P 2 0 1 0 130 -200 200 -200 N
+P 2 0 1 10 130 -150 130 -110 N
+P 2 0 1 0 130 -130 200 -130 N
+P 2 0 1 0 200 -300 200 -270 N
+P 2 0 1 0 200 -130 200 -100 N
+P 3 0 1 10 110 -275 110 -125 110 -125 N
+P 3 0 1 0 200 -200 300 -200 300 -250 N
+P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F
+X D 1 200 0 100 D 50 50 1 1 P
+X G 2 -100 -200 210 R 50 50 1 1 P
+X S 3 200 -400 100 U 50 50 1 1 P
+X B 4 300 -350 98 U 47 47 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_P
+#
+DEF eSim_MOS_P M 0 0 Y N 1 F N
+F0 "M" -50 50 50 H V R CNN
+F1 "eSim_MOS_P" 50 150 50 H V R CNN
+F2 "" 250 100 29 H V C CNN
+F3 "" 50 0 60 H V C CNN
+ALIAS mosfet_p
+DRAW
+C 100 0 111 0 1 10 N
+P 2 0 1 0 80 -70 150 -70 N
+P 2 0 1 10 80 -50 80 -90 N
+P 2 0 1 0 80 0 150 0 N
+P 2 0 1 10 80 20 80 -20 N
+P 2 0 1 0 80 70 150 70 N
+P 2 0 1 10 80 90 80 50 N
+P 2 0 1 0 150 -70 150 -100 N
+P 2 0 1 0 150 100 150 70 N
+P 3 0 1 10 60 75 60 -75 60 -75 N
+P 3 0 1 0 150 0 250 0 250 -50 N
+P 4 0 1 0 140 0 100 -15 100 15 140 0 F
+X D 1 150 200 100 D 50 50 1 1 P
+X G 2 -150 0 210 R 50 50 1 1 P
+X S 3 150 -200 100 U 50 50 1 1 P
+X B 4 250 -150 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B.cir b/library/SubcircuitLibrary/MC14016B/MC14016B.cir
new file mode 100644
index 000000000..8c317047f
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B.cir
@@ -0,0 +1,17 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\MC14016B\MC14016B.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/23/25 15:06:49
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ d_inverter		
+U2  Net-_U1-Pad2_ Net-_U2-Pad2_ d_inverter		
+M1  Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad4_ eSim_MOS_P		
+M2  Net-_M1-Pad1_ Net-_M2-Pad2_ Net-_M1-Pad3_ Net-_M2-Pad4_ eSim_MOS_N		
+U3  Net-_U2-Pad2_ Net-_M1-Pad2_ dac_bridge_1		
+U5  Net-_M1-Pad3_ Net-_U1-Pad1_ Net-_M1-Pad1_ Net-_M1-Pad4_ Net-_M2-Pad4_ PORT		
+U4  Net-_U1-Pad2_ Net-_M2-Pad2_ dac_bridge_1		
+
+.end
diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B.cir.out b/library/SubcircuitLibrary/MC14016B/MC14016B.cir.out
new file mode 100644
index 000000000..42ed3c57a
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B.cir.out
@@ -0,0 +1,32 @@
+* c:\fossee\esim\library\subcircuitlibrary\mc14016b\mc14016b.cir
+
+.include PMOS-5um.lib
+.include NMOS-5um.lib
+* u1  net-_u1-pad1_ net-_u1-pad2_ d_inverter
+* u2  net-_u1-pad2_ net-_u2-pad2_ d_inverter
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad4_ mos_p W=100u L=100u M=1
+m2 net-_m1-pad1_ net-_m2-pad2_ net-_m1-pad3_ net-_m2-pad4_ mos_n W=100u L=100u M=1
+* u3  net-_u2-pad2_ net-_m1-pad2_ dac_bridge_1
+* u5  net-_m1-pad3_ net-_u1-pad1_ net-_m1-pad1_ net-_m1-pad4_ net-_m2-pad4_ port
+* u4  net-_u1-pad2_ net-_m2-pad2_ dac_bridge_1
+a1 net-_u1-pad1_ net-_u1-pad2_ u1
+a2 net-_u1-pad2_ net-_u2-pad2_ u2
+a3 [net-_u2-pad2_ ] [net-_m1-pad2_ ] u3
+a4 [net-_u1-pad2_ ] [net-_m2-pad2_ ] u4
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u3 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u4 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B.pro b/library/SubcircuitLibrary/MC14016B/MC14016B.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B.proj b/library/SubcircuitLibrary/MC14016B/MC14016B.proj
new file mode 100644
index 000000000..fe3e0087c
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B.proj
@@ -0,0 +1 @@
+schematicFile MC14016B.sch
diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B.sch b/library/SubcircuitLibrary/MC14016B/MC14016B.sch
new file mode 100644
index 000000000..b02290ac5
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B.sch
@@ -0,0 +1,213 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:MC14016B-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_inverter U1
+U 1 1 68590916
+P 2650 3150
+F 0 "U1" H 2650 3050 60  0000 C CNN
+F 1 "d_inverter" H 2650 3300 60  0000 C CNN
+F 2 "" H 2700 3100 60  0000 C CNN
+F 3 "" H 2700 3100 60  0000 C CNN
+	1    2650 3150
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U2
+U 1 1 68590952
+P 3650 3150
+F 0 "U2" H 3650 3050 60  0000 C CNN
+F 1 "d_inverter" H 3650 3300 60  0000 C CNN
+F 2 "" H 3700 3100 60  0000 C CNN
+F 3 "" H 3700 3100 60  0000 C CNN
+	1    3650 3150
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2950 3150 3350 3150
+$Comp
+L eSim_MOS_P M1
+U 1 1 685909B0
+P 5800 3150
+F 0 "M1" H 5750 3200 50  0000 R CNN
+F 1 "eSim_MOS_P" H 5850 3300 50  0000 R CNN
+F 2 "" H 6050 3250 29  0000 C CNN
+F 3 "" H 5850 3150 60  0000 C CNN
+	1    5800 3150
+	0    1    1    0   
+$EndComp
+$Comp
+L eSim_MOS_N M2
+U 1 1 68590A0A
+P 6000 3950
+F 0 "M2" H 6000 3800 50  0000 R CNN
+F 1 "eSim_MOS_N" H 6100 3900 50  0000 R CNN
+F 2 "" H 6300 3650 29  0000 C CNN
+F 3 "" H 6100 3750 60  0000 C CNN
+	1    6000 3950
+	0    1    -1   0   
+$EndComp
+Wire Wire Line
+	5600 3300 5600 3750
+Wire Wire Line
+	6000 3300 6000 3750
+$Comp
+L dac_bridge_1 U3
+U 1 1 68590B03
+P 4750 3200
+F 0 "U3" H 4750 3200 60  0000 C CNN
+F 1 "dac_bridge_1" H 4750 3350 60  0000 C CNN
+F 2 "" H 4750 3200 60  0000 C CNN
+F 3 "" H 4750 3200 60  0000 C CNN
+	1    4750 3200
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	3950 3150 4150 3150
+$Comp
+L PORT U5
+U 2 1 68590BE8
+P 1900 3150
+F 0 "U5" H 1950 3250 30  0000 C CNN
+F 1 "PORT" H 1900 3150 30  0000 C CNN
+F 2 "" H 1900 3150 60  0000 C CNN
+F 3 "" H 1900 3150 60  0000 C CNN
+	2    1900 3150
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U5
+U 1 1 68590C23
+P 4750 3550
+F 0 "U5" H 4800 3650 30  0000 C CNN
+F 1 "PORT" H 4750 3550 30  0000 C CNN
+F 2 "" H 4750 3550 60  0000 C CNN
+F 3 "" H 4750 3550 60  0000 C CNN
+	1    4750 3550
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U5
+U 4 1 68590C48
+P 5300 3400
+F 0 "U5" H 5350 3500 30  0000 C CNN
+F 1 "PORT" H 5300 3400 30  0000 C CNN
+F 2 "" H 5300 3400 60  0000 C CNN
+F 3 "" H 5300 3400 60  0000 C CNN
+	4    5300 3400
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U5
+U 3 1 68590C87
+P 6450 3500
+F 0 "U5" H 6500 3600 30  0000 C CNN
+F 1 "PORT" H 6450 3500 30  0000 C CNN
+F 2 "" H 6450 3500 60  0000 C CNN
+F 3 "" H 6450 3500 60  0000 C CNN
+	3    6450 3500
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U5
+U 5 1 68590CB0
+P 5300 3650
+F 0 "U5" H 5350 3750 30  0000 C CNN
+F 1 "PORT" H 5300 3650 30  0000 C CNN
+F 2 "" H 5300 3650 60  0000 C CNN
+F 3 "" H 5300 3650 60  0000 C CNN
+	5    5300 3650
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2150 3150 2350 3150
+$Comp
+L dac_bridge_1 U4
+U 1 1 68592608
+P 4800 4300
+F 0 "U4" H 4800 4300 60  0000 C CNN
+F 1 "dac_bridge_1" H 4800 4450 60  0000 C CNN
+F 2 "" H 4800 4300 60  0000 C CNN
+F 3 "" H 4800 4300 60  0000 C CNN
+	1    4800 4300
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5300 3150 5650 3150
+Wire Wire Line
+	5650 3150 5650 3000
+Wire Wire Line
+	5650 3000 5800 3000
+Wire Wire Line
+	3200 3150 3200 4250
+Wire Wire Line
+	3200 4250 4200 4250
+Connection ~ 3200 3150
+Wire Wire Line
+	5350 4250 5800 4250
+Wire Wire Line
+	5800 4250 5800 4050
+Wire Wire Line
+	5550 3650 5650 3650
+Wire Wire Line
+	5550 3400 5650 3400
+Wire Wire Line
+	5000 3550 5600 3550
+Connection ~ 5600 3550
+Wire Wire Line
+	6200 3500 6000 3500
+Connection ~ 6000 3500
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B.sub b/library/SubcircuitLibrary/MC14016B/MC14016B.sub
new file mode 100644
index 000000000..abb10c93f
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B.sub
@@ -0,0 +1,26 @@
+* Subcircuit MC14016B
+.subckt MC14016B net-_m1-pad3_ net-_u1-pad1_ net-_m1-pad1_ net-_m1-pad4_ net-_m2-pad4_ 
+* c:\fossee\esim\library\subcircuitlibrary\mc14016b\mc14016b.cir
+.include PMOS-5um.lib
+.include NMOS-5um.lib
+* u1  net-_u1-pad1_ net-_u1-pad2_ d_inverter
+* u2  net-_u1-pad2_ net-_u2-pad2_ d_inverter
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad4_ mos_p W=100u L=100u M=1
+m2 net-_m1-pad1_ net-_m2-pad2_ net-_m1-pad3_ net-_m2-pad4_ mos_n W=100u L=100u M=1
+* u3  net-_u2-pad2_ net-_m1-pad2_ dac_bridge_1
+* u4  net-_u1-pad2_ net-_m2-pad2_ dac_bridge_1
+a1 net-_u1-pad1_ net-_u1-pad2_ u1
+a2 net-_u1-pad2_ net-_u2-pad2_ u2
+a3 [net-_u2-pad2_ ] [net-_m1-pad2_ ] u3
+a4 [net-_u1-pad2_ ] [net-_m2-pad2_ ] u4
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u3 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u4 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Control Statements
+
+.ends MC14016B
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B_Previous_Values.xml b/library/SubcircuitLibrary/MC14016B/MC14016B_Previous_Values.xml
new file mode 100644
index 000000000..e8c909fcb
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u1 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u1><u2 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">dac_bridge<field7 name="Enter value for out_low (default=0.0)" /><field8 name="Enter value for out_high (default=5.0)" /><field9 name="Enter value for out_undef (default=0.5)" /><field10 name="Enter value for input load (default=1.0e-12)" /><field11 name="Enter the Rise Time (default=1.0e-9)" /><field12 name="Enter the Fall Time (default=1.0e-9)" /></u3><u4 name="type">adc_bridge<field13 name="Enter value for in_low (default=1.0)" /><field14 name="Enter value for in_high (default=2.0)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /><field16 name="Enter Fall Delay (default=1.0e-9)" /></u4><u4 name="type">dac_bridge<field13 name="Enter value for out_low (default=0.0)" /><field14 name="Enter value for out_high (default=5.0)" /><field15 name="Enter value for out_undef (default=0.5)" /><field16 name="Enter value for input load (default=1.0e-12)" /><field17 name="Enter the Rise Time (default=1.0e-9)" /><field18 name="Enter the Fall Time (default=1.0e-9)" /></u4></model><devicemodel><m1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib</field><field /><field /><field /></m1><m2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib</field><field /><field /><field /></m2></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B_quad-cache.lib b/library/SubcircuitLibrary/MC14016B/MC14016B_quad-cache.lib
new file mode 100644
index 000000000..6a4c4d1a0
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B_quad-cache.lib
@@ -0,0 +1,61 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# MC14016B_1
+#
+DEF MC14016B_1 X 0 40 Y Y 1 F N
+F0 "X" 0 -650 60 H V C CNN
+F1 "MC14016B_1" 50 650 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -350 400 400 -400 0 1 0 N
+X IN 1 -550 300 200 R 50 50 1 1 I
+X CONTROL 2 -550 100 200 R 50 50 1 1 I
+X OUT 3 -550 -250 200 R 50 50 1 1 O
+X VDD 4 600 250 200 L 50 50 1 1 I
+X GND 5 600 -200 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B_quad.cir b/library/SubcircuitLibrary/MC14016B/MC14016B_quad.cir
new file mode 100644
index 000000000..4ce43c410
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B_quad.cir
@@ -0,0 +1,15 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\MC14016B_quad\MC14016B_quad.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/24/25 11:44:09
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1  Net-_U1-Pad1_ Net-_U1-Pad13_ Net-_U1-Pad2_ Net-_U1-Pad14_ Net-_U1-Pad7_ MC14016B_1		
+X2  Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad3_ Net-_U1-Pad14_ Net-_U1-Pad7_ MC14016B_1		
+X3  Net-_U1-Pad8_ Net-_U1-Pad6_ Net-_U1-Pad9_ Net-_U1-Pad14_ Net-_U1-Pad7_ MC14016B_1		
+X4  Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad10_ Net-_U1-Pad14_ Net-_U1-Pad7_ MC14016B_1		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B_quad.cir.out b/library/SubcircuitLibrary/MC14016B/MC14016B_quad.cir.out
new file mode 100644
index 000000000..d762fa9c2
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B_quad.cir.out
@@ -0,0 +1,17 @@
+* c:\fossee\esim\library\subcircuitlibrary\mc14016b_quad\mc14016b_quad.cir
+
+.include MC14016B.sub
+x1 net-_u1-pad1_ net-_u1-pad13_ net-_u1-pad2_ net-_u1-pad14_ net-_u1-pad7_ MC14016B
+x2 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad3_ net-_u1-pad14_ net-_u1-pad7_ MC14016B
+x3 net-_u1-pad8_ net-_u1-pad6_ net-_u1-pad9_ net-_u1-pad14_ net-_u1-pad7_ MC14016B
+x4 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad10_ net-_u1-pad14_ net-_u1-pad7_ MC14016B
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B_quad.pro b/library/SubcircuitLibrary/MC14016B/MC14016B_quad.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B_quad.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B_quad.sch b/library/SubcircuitLibrary/MC14016B/MC14016B_quad.sch
new file mode 100644
index 000000000..c5897efff
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B_quad.sch
@@ -0,0 +1,305 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:MC14016B_quad-cache
+EELAYER 25 0
+EELAYER END
+$Descr A1 33110 23386
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L MC14016B_1 X1
+U 1 1 685BC07B
+P 21400 8300
+F 0 "X1" H 21400 7650 60  0000 C CNN
+F 1 "MC14016B_1" H 21450 8950 60  0000 C CNN
+F 2 "" H 21400 8300 60  0001 C CNN
+F 3 "" H 21400 8300 60  0001 C CNN
+	1    21400 8300
+	1    0    0    -1  
+$EndComp
+$Comp
+L MC14016B_1 X2
+U 1 1 685BC0C0
+P 21400 9550
+F 0 "X2" H 21400 8900 60  0000 C CNN
+F 1 "MC14016B_1" H 21450 10200 60  0000 C CNN
+F 2 "" H 21400 9550 60  0001 C CNN
+F 3 "" H 21400 9550 60  0001 C CNN
+	1    21400 9550
+	1    0    0    -1  
+$EndComp
+$Comp
+L MC14016B_1 X3
+U 1 1 685BC0F0
+P 21400 10700
+F 0 "X3" H 21400 10050 60  0000 C CNN
+F 1 "MC14016B_1" H 21450 11350 60  0000 C CNN
+F 2 "" H 21400 10700 60  0001 C CNN
+F 3 "" H 21400 10700 60  0001 C CNN
+	1    21400 10700
+	1    0    0    -1  
+$EndComp
+$Comp
+L MC14016B_1 X4
+U 1 1 685BC1AF
+P 21450 11900
+F 0 "X4" H 21450 11250 60  0000 C CNN
+F 1 "MC14016B_1" H 21500 12550 60  0000 C CNN
+F 2 "" H 21450 11900 60  0001 C CNN
+F 3 "" H 21450 11900 60  0001 C CNN
+	1    21450 11900
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	22000 8050 22600 8050
+Wire Wire Line
+	22500 8050 22500 11650
+Wire Wire Line
+	22500 9300 22000 9300
+Wire Wire Line
+	22500 10450 22000 10450
+Connection ~ 22500 9300
+Wire Wire Line
+	22500 11650 22050 11650
+Connection ~ 22500 10450
+Wire Wire Line
+	22750 12100 22050 12100
+Wire Wire Line
+	22750 8500 22750 12100
+Wire Wire Line
+	22750 10900 22000 10900
+Wire Wire Line
+	22000 9750 22750 9750
+Connection ~ 22750 10900
+Wire Wire Line
+	22000 8500 22850 8500
+Connection ~ 22750 9750
+$Comp
+L PORT U1
+U 7 1 685BC5D2
+P 23100 8500
+F 0 "U1" H 23150 8600 30  0000 C CNN
+F 1 "PORT" H 23100 8500 30  0000 C CNN
+F 2 "" H 23100 8500 60  0000 C CNN
+F 3 "" H 23100 8500 60  0000 C CNN
+	7    23100 8500
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 8 1 685BC5F1
+P 20450 10400
+F 0 "U1" H 20500 10500 30  0000 C CNN
+F 1 "PORT" H 20450 10400 30  0000 C CNN
+F 2 "" H 20450 10400 60  0000 C CNN
+F 3 "" H 20450 10400 60  0000 C CNN
+	8    20450 10400
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 11 1 685BC612
+P 20500 11600
+F 0 "U1" H 20550 11700 30  0000 C CNN
+F 1 "PORT" H 20500 11600 30  0000 C CNN
+F 2 "" H 20500 11600 60  0000 C CNN
+F 3 "" H 20500 11600 60  0000 C CNN
+	11   20500 11600
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 12 1 685BC635
+P 20500 11800
+F 0 "U1" H 20550 11900 30  0000 C CNN
+F 1 "PORT" H 20500 11800 30  0000 C CNN
+F 2 "" H 20500 11800 60  0000 C CNN
+F 3 "" H 20500 11800 60  0000 C CNN
+	12   20500 11800
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 685BC65A
+P 20450 8550
+F 0 "U1" H 20500 8650 30  0000 C CNN
+F 1 "PORT" H 20450 8550 30  0000 C CNN
+F 2 "" H 20450 8550 60  0000 C CNN
+F 3 "" H 20450 8550 60  0000 C CNN
+	2    20450 8550
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 9 1 685BC681
+P 20450 10950
+F 0 "U1" H 20500 11050 30  0000 C CNN
+F 1 "PORT" H 20450 10950 30  0000 C CNN
+F 2 "" H 20450 10950 60  0000 C CNN
+F 3 "" H 20450 10950 60  0000 C CNN
+	9    20450 10950
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 13 1 685BC6AA
+P 20450 8200
+F 0 "U1" H 20500 8300 30  0000 C CNN
+F 1 "PORT" H 20450 8200 30  0000 C CNN
+F 2 "" H 20450 8200 60  0000 C CNN
+F 3 "" H 20450 8200 60  0000 C CNN
+	13   20450 8200
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 685BC6D5
+P 20400 9250
+F 0 "U1" H 20450 9350 30  0000 C CNN
+F 1 "PORT" H 20400 9250 30  0000 C CNN
+F 2 "" H 20400 9250 60  0000 C CNN
+F 3 "" H 20400 9250 60  0000 C CNN
+	4    20400 9250
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 685BC702
+P 20450 9800
+F 0 "U1" H 20500 9900 30  0000 C CNN
+F 1 "PORT" H 20450 9800 30  0000 C CNN
+F 2 "" H 20450 9800 60  0000 C CNN
+F 3 "" H 20450 9800 60  0000 C CNN
+	3    20450 9800
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 685BC735
+P 20450 8000
+F 0 "U1" H 20500 8100 30  0000 C CNN
+F 1 "PORT" H 20450 8000 30  0000 C CNN
+F 2 "" H 20450 8000 60  0000 C CNN
+F 3 "" H 20450 8000 60  0000 C CNN
+	1    20450 8000
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 685BC766
+P 20450 9450
+F 0 "U1" H 20500 9550 30  0000 C CNN
+F 1 "PORT" H 20450 9450 30  0000 C CNN
+F 2 "" H 20450 9450 60  0000 C CNN
+F 3 "" H 20450 9450 60  0000 C CNN
+	5    20450 9450
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 6 1 685BC79D
+P 20500 10600
+F 0 "U1" H 20550 10700 30  0000 C CNN
+F 1 "PORT" H 20500 10600 30  0000 C CNN
+F 2 "" H 20500 10600 60  0000 C CNN
+F 3 "" H 20500 10600 60  0000 C CNN
+	6    20500 10600
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 10 1 685BC7D2
+P 20500 12150
+F 0 "U1" H 20550 12250 30  0000 C CNN
+F 1 "PORT" H 20500 12150 30  0000 C CNN
+F 2 "" H 20500 12150 60  0000 C CNN
+F 3 "" H 20500 12150 60  0000 C CNN
+	10   20500 12150
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 14 1 685BC809
+P 22850 8050
+F 0 "U1" H 22900 8150 30  0000 C CNN
+F 1 "PORT" H 22850 8050 30  0000 C CNN
+F 2 "" H 22850 8050 60  0000 C CNN
+F 3 "" H 22850 8050 60  0000 C CNN
+	14   22850 8050
+	-1   0    0    -1  
+$EndComp
+Wire Wire Line
+	20700 8200 20850 8200
+Wire Wire Line
+	20700 8000 20850 8000
+Wire Wire Line
+	20700 8550 20850 8550
+Wire Wire Line
+	20700 9450 20850 9450
+Wire Wire Line
+	20650 9250 20850 9250
+Wire Wire Line
+	20700 9800 20850 9800
+Wire Wire Line
+	20750 10600 20850 10600
+Wire Wire Line
+	20700 10400 20850 10400
+Wire Wire Line
+	20700 10950 20850 10950
+Wire Wire Line
+	20750 11800 20900 11800
+Wire Wire Line
+	20750 11600 20900 11600
+Wire Wire Line
+	20750 12150 20900 12150
+Connection ~ 22750 8500
+Connection ~ 22500 8050
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B_quad.sub b/library/SubcircuitLibrary/MC14016B/MC14016B_quad.sub
new file mode 100644
index 000000000..23cf58569
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B_quad.sub
@@ -0,0 +1,11 @@
+* Subcircuit MC14016B_quad
+.subckt MC14016B_quad net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ 
+* c:\fossee\esim\library\subcircuitlibrary\mc14016b_quad\mc14016b_quad.cir
+.include MC14016B.sub
+x1 net-_u1-pad1_ net-_u1-pad13_ net-_u1-pad2_ net-_u1-pad14_ net-_u1-pad7_ MC14016B
+x2 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad3_ net-_u1-pad14_ net-_u1-pad7_ MC14016B
+x3 net-_u1-pad8_ net-_u1-pad6_ net-_u1-pad9_ net-_u1-pad14_ net-_u1-pad7_ MC14016B
+x4 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad10_ net-_u1-pad14_ net-_u1-pad7_ MC14016B
+* Control Statements
+
+.ends MC14016B_quad
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B_quad_Previous_Values.xml b/library/SubcircuitLibrary/MC14016B/MC14016B_quad_Previous_Values.xml
new file mode 100644
index 000000000..b1c23cb67
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B_quad_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u3 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u3><u7 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u7><u15 name="type">dac_bridge<field7 name="Enter value for out_low (default=0.0)" /><field8 name="Enter value for out_high (default=5.0)" /><field9 name="Enter value for out_undef (default=0.5)" /><field10 name="Enter value for input load (default=1.0e-12)" /><field11 name="Enter the Rise Time (default=1.0e-9)" /><field12 name="Enter the Fall Time (default=1.0e-9)" /></u15><u11 name="type">dac_bridge<field13 name="Enter value for out_low (default=0.0)" /><field14 name="Enter value for out_high (default=5.0)" /><field15 name="Enter value for out_undef (default=0.5)" /><field16 name="Enter value for input load (default=1.0e-12)" /><field17 name="Enter the Rise Time (default=1.0e-9)" /><field18 name="Enter the Fall Time (default=1.0e-9)" /></u11><u2 name="type">d_inverter<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u2><u6 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u6><u14 name="type">dac_bridge<field25 name="Enter value for out_low (default=0.0)" /><field26 name="Enter value for out_high (default=5.0)" /><field27 name="Enter value for out_undef (default=0.5)" /><field28 name="Enter value for input load (default=1.0e-12)" /><field29 name="Enter the Rise Time (default=1.0e-9)" /><field30 name="Enter the Fall Time (default=1.0e-9)" /></u14><u10 name="type">dac_bridge<field31 name="Enter value for out_low (default=0.0)" /><field32 name="Enter value for out_high (default=5.0)" /><field33 name="Enter value for out_undef (default=0.5)" /><field34 name="Enter value for input load (default=1.0e-12)" /><field35 name="Enter the Rise Time (default=1.0e-9)" /><field36 name="Enter the Fall Time (default=1.0e-9)" /></u10><u4 name="type">d_inverter<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u4><u8 name="type">d_inverter<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u8><u16 name="type">dac_bridge<field43 name="Enter value for out_low (default=0.0)" /><field44 name="Enter value for out_high (default=5.0)" /><field45 name="Enter value for out_undef (default=0.5)" /><field46 name="Enter value for input load (default=1.0e-12)" /><field47 name="Enter the Rise Time (default=1.0e-9)" /><field48 name="Enter the Fall Time (default=1.0e-9)" /></u16><u12 name="type">dac_bridge<field49 name="Enter value for out_low (default=0.0)" /><field50 name="Enter value for out_high (default=5.0)" /><field51 name="Enter value for out_undef (default=0.5)" /><field52 name="Enter value for input load (default=1.0e-12)" /><field53 name="Enter the Rise Time (default=1.0e-9)" /><field54 name="Enter the Fall Time (default=1.0e-9)" /></u12><u5 name="type">d_inverter<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u5><u9 name="type">d_inverter<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u9><u17 name="type">dac_bridge<field61 name="Enter value for out_low (default=0.0)" /><field62 name="Enter value for out_high (default=5.0)" /><field63 name="Enter value for out_undef (default=0.5)" /><field64 name="Enter value for input load (default=1.0e-12)" /><field65 name="Enter the Rise Time (default=1.0e-9)" /><field66 name="Enter the Fall Time (default=1.0e-9)" /></u17><u13 name="type">dac_bridge<field67 name="Enter value for out_low (default=0.0)" /><field68 name="Enter value for out_high (default=5.0)" /><field69 name="Enter value for out_undef (default=0.5)" /><field70 name="Enter value for input load (default=1.0e-12)" /><field71 name="Enter the Rise Time (default=1.0e-9)" /><field72 name="Enter the Fall Time (default=1.0e-9)" /></u13></model><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\MC14016B</field></x1><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\MC14016B</field></x2><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\MC14016B</field></x3><x4><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\MC14016B</field></x4></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B_test-cache.lib b/library/SubcircuitLibrary/MC14016B/MC14016B_test-cache.lib
new file mode 100644
index 000000000..2cafb8e4a
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B_test-cache.lib
@@ -0,0 +1,131 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# DC
+#
+DEF DC v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 w
+X - 2 0 -450 300 U 50 50 1 1 w
+ENDDRAW
+ENDDEF
+#
+# MC14016B
+#
+DEF MC14016B X 0 40 Y Y 1 F N
+F0 "X" 0 -1100 60 H V C CNN
+F1 "MC14016B" 50 1250 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -400 950 500 -550 0 1 0 N
+X IN_1 1 -600 800 200 R 50 50 1 1 I
+X OUT_1 2 -600 600 200 R 50 50 1 1 O
+X OUT_2 3 -600 400 200 R 50 50 1 1 O
+X IN_2 4 -600 200 200 R 50 50 1 1 I
+X CONT2 5 -600 0 200 R 50 50 1 1 I
+X CONT3 6 -600 -200 200 R 50 50 1 1 I
+X VSS 7 -600 -400 200 R 50 50 1 1 I
+X IN_3 8 700 -400 200 L 50 50 1 1 I
+X OUT_3 9 700 -200 200 L 50 50 1 1 O
+X OUT_4 10 700 0 200 L 50 50 1 1 O
+X IN_4 11 700 200 200 L 50 50 1 1 I
+X CONT4 12 700 400 200 L 50 50 1 1 I
+X CONT1 13 700 600 200 L 50 50 1 1 I
+X VDD 14 700 800 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_2
+#
+DEF adc_bridge_2 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_2" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -100 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X OUT1 3 550 50 200 L 50 50 1 1 O
+X OUT2 4 550 -50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_GND
+#
+DEF eSim_GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "eSim_GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# pulse
+#
+DEF pulse v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "pulse" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -25 -450 501 928 871 0 1 0 N -50 50 0 50
+A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50
+A 75 600 551 -926 -873 0 1 0 N 50 50 100 50
+A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50
+A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50
+A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# sine
+#
+DEF sine v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "sine" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -50 0 50 1 1799 0 1 0 N 0 0 -100 0
+A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 0 1 1 I
+X - 2 0 -450 300 U 50 0 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B_test.cir b/library/SubcircuitLibrary/MC14016B/MC14016B_test.cir
new file mode 100644
index 000000000..74c2f828d
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B_test.cir
@@ -0,0 +1,26 @@
+* C:\Users\pavithra\eSim-Workspace\MC14016B_test\MC14016B_test.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/24/25 11:45:58
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+v3  in GND sine		
+v4  Net-_X1-Pad4_ GND sine		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ adc_bridge_2		
+v1  Net-_U1-Pad1_ GND pulse		
+v2  Net-_U1-Pad2_ GND pulse		
+U3  out plot_v1		
+v5  Net-_X1-Pad14_ GND DC		
+U6  cont Net-_U6-Pad2_ Net-_U6-Pad3_ Net-_U6-Pad4_ adc_bridge_2		
+v9  cont GND pulse		
+v8  Net-_U6-Pad2_ GND pulse		
+U2  Net-_U2-Pad~_ plot_v1		
+U4  Net-_U4-Pad~_ plot_v1		
+U5  Net-_U5-Pad~_ plot_v1		
+v6  Net-_X1-Pad8_ GND sine		
+v7  Net-_X1-Pad11_ GND sine		
+X1  in out Net-_U2-Pad~_ Net-_X1-Pad4_ Net-_U1-Pad3_ Net-_U1-Pad4_ GND Net-_X1-Pad8_ Net-_U5-Pad~_ Net-_U4-Pad~_ Net-_X1-Pad11_ Net-_U6-Pad4_ Net-_U6-Pad3_ Net-_X1-Pad14_ MC14016B		
+
+.end
diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B_test.cir.out b/library/SubcircuitLibrary/MC14016B/MC14016B_test.cir.out
new file mode 100644
index 000000000..5a9ba062c
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B_test.cir.out
@@ -0,0 +1,35 @@
+* c:\users\pavithra\esim-workspace\mc14016b_test\mc14016b_test.cir
+
+.include MC14016B_quad.sub
+v3  in gnd sine(0 5 1k 0 0)
+v4  net-_x1-pad4_ gnd sine(0 5 1k 0 0)
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ adc_bridge_2
+v1  net-_u1-pad1_ gnd pulse(0 5 0 0.1n 0.1n 1m 2m)
+v2  net-_u1-pad2_ gnd pulse(0 5 0 0.1n 0.1n 1m 2m)
+* u3  out plot_v1
+v5 net-_x1-pad14_ gnd  dc 5
+* u6  cont net-_u6-pad2_ net-_u6-pad3_ net-_u6-pad4_ adc_bridge_2
+v9  cont gnd pulse(0 5 0 0.1n 0.1n 1m  2m)
+v8  net-_u6-pad2_ gnd pulse(0 5 0 0.1n 0.1n 1m 2m)
+* u2  net-_u2-pad_ plot_v1
+* u4  net-_u4-pad_ plot_v1
+* u5  net-_u5-pad_ plot_v1
+v6  net-_x1-pad8_ gnd sine(0 5 1k 0 0)
+v7  net-_x1-pad11_ gnd sine(0 5  1k 0 0)
+x1 in out net-_u2-pad_ net-_x1-pad4_ net-_u1-pad3_ net-_u1-pad4_ gnd net-_x1-pad8_ net-_u5-pad~_ net-_u4-pad_ net-_x1-pad11_ net-_u6-pad4_ net-_u6-pad3_ net-_x1-pad14_ MC14016B_quad
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] [net-_u1-pad3_ net-_u1-pad4_ ] u1
+a2 [cont net-_u6-pad2_ ] [net-_u6-pad3_ net-_u6-pad4_ ] u6
+* Schematic Name:                             adc_bridge_2, NgSpice Name: adc_bridge
+.model u1 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_2, NgSpice Name: adc_bridge
+.model u6 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+.tran 1e-06 10e-03 0e-03
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(out)+6v(in)+12v(cont)
+.endc
+.end
diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B_test.pro b/library/SubcircuitLibrary/MC14016B/MC14016B_test.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B_test.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B_test.proj b/library/SubcircuitLibrary/MC14016B/MC14016B_test.proj
new file mode 100644
index 000000000..2ef836be4
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B_test.proj
@@ -0,0 +1 @@
+schematicFile MC14016B_test.sch
diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B_test.sch b/library/SubcircuitLibrary/MC14016B/MC14016B_test.sch
new file mode 100644
index 000000000..f812946e9
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B_test.sch
@@ -0,0 +1,431 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
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diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B_test_Previous_Values.xml b/library/SubcircuitLibrary/MC14016B/MC14016B_test_Previous_Values.xml
new file mode 100644
index 000000000..f0bd5a163
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B_test_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source><v3 name="Source type">sine<field1 name="Offset Value">0</field1><field2 name="Amplitude">5</field2><field3 name="Frequency">1k</field3><field4 name="Delay Time">0</field4><field5 name="Damping Factor" /></v3><v4 name="Source type">sine<field1 name="Offset Value">0</field1><field2 name="Amplitude">5</field2><field3 name="Frequency">1k</field3><field4 name="Delay Time">0</field4><field5 name="Damping Factor" /></v4><v1 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">0.1n</field4><field5 name="Fall Time">0.1n</field5><field5 name="Pulse width">1m</field5><field5 name="Period">2m</field5></v1><v2 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">0.1n</field4><field5 name="Fall Time">0.1n</field5><field5 name="Pulse width">1m</field5><field5 name="Period">2m</field5></v2><v5 name="Source type">dc<field1 name="Value">5</field1></v5><v9 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">0.1n</field4><field5 name="Fall Time">0.1n</field5><field5 name="Pulse width">1m </field5><field5 name="Period">2m</field5></v9><v8 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">0.1n</field4><field5 name="Fall Time">0.1n</field5><field5 name="Pulse width">1m</field5><field5 name="Period">2m</field5></v8><v6 name="Source type">sine<field1 name="Offset Value">0</field1><field2 name="Amplitude">5</field2><field3 name="Frequency">1k</field3><field4 name="Delay Time">0</field4><field5 name="Damping Factor" /></v6><v7 name="Source type">sine<field1 name="Offset Value">0</field1><field2 name="Amplitude">5 </field2><field3 name="Frequency">1k</field3><field4 name="Delay Time">0</field4><field5 name="Damping Factor" /></v7></source><model><u1 name="type">adc_bridge<field1 name="Enter value for in_low (default=1.0)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter Fall Delay (default=1.0e-9)" /></u1><u6 name="type">adc_bridge<field5 name="Enter value for in_low (default=1.0)" /><field6 name="Enter value for in_high (default=2.0)" /><field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /></u6></model><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\MC14016B_quad</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">1</field2><field3 name="Stop Time">10</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">us</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14016B/NMOS-5um.lib b/library/SubcircuitLibrary/MC14016B/NMOS-5um.lib
new file mode 100644
index 000000000..a237e1fe3
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/NMOS-5um.lib
@@ -0,0 +1,5 @@
+* 5um technology
+
+.model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7 
++ Level=1
++ Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n  )
diff --git a/library/SubcircuitLibrary/MC14016B/PMOS-5um.lib b/library/SubcircuitLibrary/MC14016B/PMOS-5um.lib
new file mode 100644
index 000000000..9c3ed9760
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/PMOS-5um.lib
@@ -0,0 +1,5 @@
+*5um technology
+
+.model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65
++ Level=1
++ Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n  )
diff --git a/library/SubcircuitLibrary/MC14016B/analysis b/library/SubcircuitLibrary/MC14016B/analysis
new file mode 100644
index 000000000..b21a9e13b
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/analysis
@@ -0,0 +1 @@
+.tran 1e-06 10e-03 0e-03
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14016B_One/D.lib b/library/SubcircuitLibrary/MC14016B_One/D.lib
new file mode 100644
index 000000000..f53bf3e03
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B_One/D.lib
@@ -0,0 +1,2 @@
+.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04)
+
diff --git a/library/SubcircuitLibrary/MC14016B_One/MC14016B-cache.lib b/library/SubcircuitLibrary/MC14016B_One/MC14016B-cache.lib
new file mode 100644
index 000000000..3b7d214a1
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B_One/MC14016B-cache.lib
@@ -0,0 +1,128 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_1
+#
+DEF dac_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_N
+#
+DEF eSim_MOS_N M 0 0 Y N 1 F N
+F0 "M" 0 -150 50 H V R CNN
+F1 "eSim_MOS_N" 100 -50 50 H V R CNN
+F2 "" 300 -300 29 H V C CNN
+F3 "" 100 -200 60 H V C CNN
+ALIAS mosfet_n
+DRAW
+C 150 -200 111 0 1 10 N
+P 2 0 1 10 130 -290 130 -250 N
+P 2 0 1 0 130 -270 200 -270 N
+P 2 0 1 10 130 -220 130 -180 N
+P 2 0 1 0 130 -200 200 -200 N
+P 2 0 1 10 130 -150 130 -110 N
+P 2 0 1 0 130 -130 200 -130 N
+P 2 0 1 0 200 -300 200 -270 N
+P 2 0 1 0 200 -130 200 -100 N
+P 3 0 1 10 110 -275 110 -125 110 -125 N
+P 3 0 1 0 200 -200 300 -200 300 -250 N
+P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F
+X D 1 200 0 100 D 50 50 1 1 P
+X G 2 -100 -200 210 R 50 50 1 1 P
+X S 3 200 -400 100 U 50 50 1 1 P
+X B 4 300 -350 98 U 47 47 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_P
+#
+DEF eSim_MOS_P M 0 0 Y N 1 F N
+F0 "M" -50 50 50 H V R CNN
+F1 "eSim_MOS_P" 50 150 50 H V R CNN
+F2 "" 250 100 29 H V C CNN
+F3 "" 50 0 60 H V C CNN
+ALIAS mosfet_p
+DRAW
+C 100 0 111 0 1 10 N
+P 2 0 1 0 80 -70 150 -70 N
+P 2 0 1 10 80 -50 80 -90 N
+P 2 0 1 0 80 0 150 0 N
+P 2 0 1 10 80 20 80 -20 N
+P 2 0 1 0 80 70 150 70 N
+P 2 0 1 10 80 90 80 50 N
+P 2 0 1 0 150 -70 150 -100 N
+P 2 0 1 0 150 100 150 70 N
+P 3 0 1 10 60 75 60 -75 60 -75 N
+P 3 0 1 0 150 0 250 0 250 -50 N
+P 4 0 1 0 140 0 100 -15 100 15 140 0 F
+X D 1 150 200 100 D 50 50 1 1 P
+X G 2 -150 0 210 R 50 50 1 1 P
+X S 3 150 -200 100 U 50 50 1 1 P
+X B 4 250 -150 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/MC14016B_One/MC14016B.cir b/library/SubcircuitLibrary/MC14016B_One/MC14016B.cir
new file mode 100644
index 000000000..8c317047f
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B_One/MC14016B.cir
@@ -0,0 +1,17 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\MC14016B\MC14016B.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/23/25 15:06:49
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ d_inverter		
+U2  Net-_U1-Pad2_ Net-_U2-Pad2_ d_inverter		
+M1  Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad4_ eSim_MOS_P		
+M2  Net-_M1-Pad1_ Net-_M2-Pad2_ Net-_M1-Pad3_ Net-_M2-Pad4_ eSim_MOS_N		
+U3  Net-_U2-Pad2_ Net-_M1-Pad2_ dac_bridge_1		
+U5  Net-_M1-Pad3_ Net-_U1-Pad1_ Net-_M1-Pad1_ Net-_M1-Pad4_ Net-_M2-Pad4_ PORT		
+U4  Net-_U1-Pad2_ Net-_M2-Pad2_ dac_bridge_1		
+
+.end
diff --git a/library/SubcircuitLibrary/MC14016B_One/MC14016B.cir.out b/library/SubcircuitLibrary/MC14016B_One/MC14016B.cir.out
new file mode 100644
index 000000000..42ed3c57a
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B_One/MC14016B.cir.out
@@ -0,0 +1,32 @@
+* c:\fossee\esim\library\subcircuitlibrary\mc14016b\mc14016b.cir
+
+.include PMOS-5um.lib
+.include NMOS-5um.lib
+* u1  net-_u1-pad1_ net-_u1-pad2_ d_inverter
+* u2  net-_u1-pad2_ net-_u2-pad2_ d_inverter
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad4_ mos_p W=100u L=100u M=1
+m2 net-_m1-pad1_ net-_m2-pad2_ net-_m1-pad3_ net-_m2-pad4_ mos_n W=100u L=100u M=1
+* u3  net-_u2-pad2_ net-_m1-pad2_ dac_bridge_1
+* u5  net-_m1-pad3_ net-_u1-pad1_ net-_m1-pad1_ net-_m1-pad4_ net-_m2-pad4_ port
+* u4  net-_u1-pad2_ net-_m2-pad2_ dac_bridge_1
+a1 net-_u1-pad1_ net-_u1-pad2_ u1
+a2 net-_u1-pad2_ net-_u2-pad2_ u2
+a3 [net-_u2-pad2_ ] [net-_m1-pad2_ ] u3
+a4 [net-_u1-pad2_ ] [net-_m2-pad2_ ] u4
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u3 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u4 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/MC14016B_One/MC14016B.pro b/library/SubcircuitLibrary/MC14016B_One/MC14016B.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B_One/MC14016B.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/MC14016B_One/MC14016B.sch b/library/SubcircuitLibrary/MC14016B_One/MC14016B.sch
new file mode 100644
index 000000000..b02290ac5
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B_One/MC14016B.sch
@@ -0,0 +1,213 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:MC14016B-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_inverter U1
+U 1 1 68590916
+P 2650 3150
+F 0 "U1" H 2650 3050 60  0000 C CNN
+F 1 "d_inverter" H 2650 3300 60  0000 C CNN
+F 2 "" H 2700 3100 60  0000 C CNN
+F 3 "" H 2700 3100 60  0000 C CNN
+	1    2650 3150
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U2
+U 1 1 68590952
+P 3650 3150
+F 0 "U2" H 3650 3050 60  0000 C CNN
+F 1 "d_inverter" H 3650 3300 60  0000 C CNN
+F 2 "" H 3700 3100 60  0000 C CNN
+F 3 "" H 3700 3100 60  0000 C CNN
+	1    3650 3150
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2950 3150 3350 3150
+$Comp
+L eSim_MOS_P M1
+U 1 1 685909B0
+P 5800 3150
+F 0 "M1" H 5750 3200 50  0000 R CNN
+F 1 "eSim_MOS_P" H 5850 3300 50  0000 R CNN
+F 2 "" H 6050 3250 29  0000 C CNN
+F 3 "" H 5850 3150 60  0000 C CNN
+	1    5800 3150
+	0    1    1    0   
+$EndComp
+$Comp
+L eSim_MOS_N M2
+U 1 1 68590A0A
+P 6000 3950
+F 0 "M2" H 6000 3800 50  0000 R CNN
+F 1 "eSim_MOS_N" H 6100 3900 50  0000 R CNN
+F 2 "" H 6300 3650 29  0000 C CNN
+F 3 "" H 6100 3750 60  0000 C CNN
+	1    6000 3950
+	0    1    -1   0   
+$EndComp
+Wire Wire Line
+	5600 3300 5600 3750
+Wire Wire Line
+	6000 3300 6000 3750
+$Comp
+L dac_bridge_1 U3
+U 1 1 68590B03
+P 4750 3200
+F 0 "U3" H 4750 3200 60  0000 C CNN
+F 1 "dac_bridge_1" H 4750 3350 60  0000 C CNN
+F 2 "" H 4750 3200 60  0000 C CNN
+F 3 "" H 4750 3200 60  0000 C CNN
+	1    4750 3200
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	3950 3150 4150 3150
+$Comp
+L PORT U5
+U 2 1 68590BE8
+P 1900 3150
+F 0 "U5" H 1950 3250 30  0000 C CNN
+F 1 "PORT" H 1900 3150 30  0000 C CNN
+F 2 "" H 1900 3150 60  0000 C CNN
+F 3 "" H 1900 3150 60  0000 C CNN
+	2    1900 3150
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U5
+U 1 1 68590C23
+P 4750 3550
+F 0 "U5" H 4800 3650 30  0000 C CNN
+F 1 "PORT" H 4750 3550 30  0000 C CNN
+F 2 "" H 4750 3550 60  0000 C CNN
+F 3 "" H 4750 3550 60  0000 C CNN
+	1    4750 3550
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U5
+U 4 1 68590C48
+P 5300 3400
+F 0 "U5" H 5350 3500 30  0000 C CNN
+F 1 "PORT" H 5300 3400 30  0000 C CNN
+F 2 "" H 5300 3400 60  0000 C CNN
+F 3 "" H 5300 3400 60  0000 C CNN
+	4    5300 3400
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U5
+U 3 1 68590C87
+P 6450 3500
+F 0 "U5" H 6500 3600 30  0000 C CNN
+F 1 "PORT" H 6450 3500 30  0000 C CNN
+F 2 "" H 6450 3500 60  0000 C CNN
+F 3 "" H 6450 3500 60  0000 C CNN
+	3    6450 3500
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U5
+U 5 1 68590CB0
+P 5300 3650
+F 0 "U5" H 5350 3750 30  0000 C CNN
+F 1 "PORT" H 5300 3650 30  0000 C CNN
+F 2 "" H 5300 3650 60  0000 C CNN
+F 3 "" H 5300 3650 60  0000 C CNN
+	5    5300 3650
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2150 3150 2350 3150
+$Comp
+L dac_bridge_1 U4
+U 1 1 68592608
+P 4800 4300
+F 0 "U4" H 4800 4300 60  0000 C CNN
+F 1 "dac_bridge_1" H 4800 4450 60  0000 C CNN
+F 2 "" H 4800 4300 60  0000 C CNN
+F 3 "" H 4800 4300 60  0000 C CNN
+	1    4800 4300
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5300 3150 5650 3150
+Wire Wire Line
+	5650 3150 5650 3000
+Wire Wire Line
+	5650 3000 5800 3000
+Wire Wire Line
+	3200 3150 3200 4250
+Wire Wire Line
+	3200 4250 4200 4250
+Connection ~ 3200 3150
+Wire Wire Line
+	5350 4250 5800 4250
+Wire Wire Line
+	5800 4250 5800 4050
+Wire Wire Line
+	5550 3650 5650 3650
+Wire Wire Line
+	5550 3400 5650 3400
+Wire Wire Line
+	5000 3550 5600 3550
+Connection ~ 5600 3550
+Wire Wire Line
+	6200 3500 6000 3500
+Connection ~ 6000 3500
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/MC14016B_One/MC14016B.sub b/library/SubcircuitLibrary/MC14016B_One/MC14016B.sub
new file mode 100644
index 000000000..abb10c93f
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B_One/MC14016B.sub
@@ -0,0 +1,26 @@
+* Subcircuit MC14016B
+.subckt MC14016B net-_m1-pad3_ net-_u1-pad1_ net-_m1-pad1_ net-_m1-pad4_ net-_m2-pad4_ 
+* c:\fossee\esim\library\subcircuitlibrary\mc14016b\mc14016b.cir
+.include PMOS-5um.lib
+.include NMOS-5um.lib
+* u1  net-_u1-pad1_ net-_u1-pad2_ d_inverter
+* u2  net-_u1-pad2_ net-_u2-pad2_ d_inverter
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad4_ mos_p W=100u L=100u M=1
+m2 net-_m1-pad1_ net-_m2-pad2_ net-_m1-pad3_ net-_m2-pad4_ mos_n W=100u L=100u M=1
+* u3  net-_u2-pad2_ net-_m1-pad2_ dac_bridge_1
+* u4  net-_u1-pad2_ net-_m2-pad2_ dac_bridge_1
+a1 net-_u1-pad1_ net-_u1-pad2_ u1
+a2 net-_u1-pad2_ net-_u2-pad2_ u2
+a3 [net-_u2-pad2_ ] [net-_m1-pad2_ ] u3
+a4 [net-_u1-pad2_ ] [net-_m2-pad2_ ] u4
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u3 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u4 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Control Statements
+
+.ends MC14016B
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14016B_One/MC14016B_Previous_Values.xml b/library/SubcircuitLibrary/MC14016B_One/MC14016B_Previous_Values.xml
new file mode 100644
index 000000000..e8c909fcb
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B_One/MC14016B_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u1 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u1><u2 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">dac_bridge<field7 name="Enter value for out_low (default=0.0)" /><field8 name="Enter value for out_high (default=5.0)" /><field9 name="Enter value for out_undef (default=0.5)" /><field10 name="Enter value for input load (default=1.0e-12)" /><field11 name="Enter the Rise Time (default=1.0e-9)" /><field12 name="Enter the Fall Time (default=1.0e-9)" /></u3><u4 name="type">adc_bridge<field13 name="Enter value for in_low (default=1.0)" /><field14 name="Enter value for in_high (default=2.0)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /><field16 name="Enter Fall Delay (default=1.0e-9)" /></u4><u4 name="type">dac_bridge<field13 name="Enter value for out_low (default=0.0)" /><field14 name="Enter value for out_high (default=5.0)" /><field15 name="Enter value for out_undef (default=0.5)" /><field16 name="Enter value for input load (default=1.0e-12)" /><field17 name="Enter the Rise Time (default=1.0e-9)" /><field18 name="Enter the Fall Time (default=1.0e-9)" /></u4></model><devicemodel><m1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib</field><field /><field /><field /></m1><m2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib</field><field /><field /><field /></m2></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14016B_One/MC14016B_one.proj b/library/SubcircuitLibrary/MC14016B_One/MC14016B_one.proj
new file mode 100644
index 000000000..fe3e0087c
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B_One/MC14016B_one.proj
@@ -0,0 +1 @@
+schematicFile MC14016B.sch
diff --git a/library/SubcircuitLibrary/MC14016B_One/MC14016B_onetest-cache.lib b/library/SubcircuitLibrary/MC14016B_One/MC14016B_onetest-cache.lib
new file mode 100644
index 000000000..924b1b3b5
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B_One/MC14016B_onetest-cache.lib
@@ -0,0 +1,144 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# DC
+#
+DEF DC v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 w
+X - 2 0 -450 300 U 50 50 1 1 w
+ENDDRAW
+ENDDEF
+#
+# MC14016B_1
+#
+DEF MC14016B_1 X 0 40 Y Y 1 F N
+F0 "X" 0 -650 60 H V C CNN
+F1 "MC14016B_1" 50 650 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -350 400 400 -400 0 1 0 N
+X IN 1 -550 300 200 R 50 50 1 1 I
+X CONTROL 2 -550 100 200 R 50 50 1 1 I
+X OUT 3 -550 -250 200 R 50 50 1 1 O
+X VDD 4 600 250 200 L 50 50 1 1 I
+X GND 5 600 -200 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_1
+#
+DEF adc_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_Diode
+#
+DEF eSim_Diode D 0 40 N N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "eSim_Diode" 0 -100 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ TO-???*
+ *SingleDiode
+ *_Diode_*
+ *SingleDiode*
+ D_*
+$ENDFPLIST
+DRAW
+T 0 -100 50 60 0 0 0 A Normal 0 C C
+T 0 100 50 60 0 0 0 K Normal 0 C C
+P 2 0 1 6 50 50 50 -50 N
+P 3 0 1 0 -50 50 50 0 -50 -50 F
+X A 1 -150 0 100 R 40 40 1 1 P
+X K 2 150 0 100 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_GND
+#
+DEF eSim_GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "eSim_GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# pulse
+#
+DEF pulse v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "pulse" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -25 -450 501 928 871 0 1 0 N -50 50 0 50
+A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50
+A 75 600 551 -926 -873 0 1 0 N 50 50 100 50
+A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50
+A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50
+A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# sine
+#
+DEF sine v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "sine" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -50 0 50 1 1799 0 1 0 N 0 0 -100 0
+A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 0 1 1 I
+X - 2 0 -450 300 U 50 0 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/MC14016B_One/MC14016B_onetest.cir b/library/SubcircuitLibrary/MC14016B_One/MC14016B_onetest.cir
new file mode 100644
index 000000000..33315cfaa
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B_One/MC14016B_onetest.cir
@@ -0,0 +1,22 @@
+* C:\Users\pavithra\eSim-Workspace\MC14016B_onetest\MC14016B_onetest.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/23/25 15:37:22
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2  cont Net-_U2-Pad2_ adc_bridge_1		
+v1  cont GND pulse		
+U3  cont plot_v1		
+X1  in Net-_U2-Pad2_ out Net-_D1-Pad2_ GND MC14016B_1		
+D3  in Net-_D1-Pad2_ eSim_Diode		
+D4  GND in eSim_Diode		
+v3  Net-_D1-Pad2_ GND DC		
+v2  in GND sine		
+U4  in plot_v1		
+D1  out Net-_D1-Pad2_ eSim_Diode		
+D2  GND out eSim_Diode		
+U1  out plot_v1		
+
+.end
diff --git a/library/SubcircuitLibrary/MC14016B_One/MC14016B_onetest.cir.out b/library/SubcircuitLibrary/MC14016B_One/MC14016B_onetest.cir.out
new file mode 100644
index 000000000..a6da5e416
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B_One/MC14016B_onetest.cir.out
@@ -0,0 +1,29 @@
+* c:\users\pavithra\esim-workspace\mc14016b_onetest\mc14016b_onetest.cir
+
+.include MC14016B.sub
+.include D.lib
+* u2  cont net-_u2-pad2_ adc_bridge_1
+v1  cont gnd pulse(0 5 0 0.1n 0.1n 1m 2m)
+* u3  cont plot_v1
+x1 in net-_u2-pad2_ out net-_d1-pad2_ gnd MC14016B
+d3 in net-_d1-pad2_ 1N4148
+d4 gnd in 1N4148
+v3 net-_d1-pad2_ gnd  dc 5
+v2  in gnd sine(0 5 1k 0 0)
+* u4  in plot_v1
+d1 out net-_d1-pad2_ 1N4148
+d2 gnd out 1N4148
+* u1  out plot_v1
+a1 [cont ] [net-_u2-pad2_ ] u2
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+.tran 1e-06 10e-03 0e-03
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(out) +6v(in)+12v(cont)
+.endc
+.end
diff --git a/library/SubcircuitLibrary/MC14016B_One/MC14016B_onetest.pro b/library/SubcircuitLibrary/MC14016B_One/MC14016B_onetest.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B_One/MC14016B_onetest.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/MC14016B_One/MC14016B_onetest.proj b/library/SubcircuitLibrary/MC14016B_One/MC14016B_onetest.proj
new file mode 100644
index 000000000..8bce94bb8
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B_One/MC14016B_onetest.proj
@@ -0,0 +1 @@
+schematicFile MC14016B_onetest.sch
diff --git a/library/SubcircuitLibrary/MC14016B_One/MC14016B_onetest.sch b/library/SubcircuitLibrary/MC14016B_One/MC14016B_onetest.sch
new file mode 100644
index 000000000..f1b61e569
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B_One/MC14016B_onetest.sch
@@ -0,0 +1,308 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:MC14016B_onetest-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L adc_bridge_1 U2
+U 1 1 68590F01
+P 4800 4950
+F 0 "U2" H 4800 4950 60  0000 C CNN
+F 1 "adc_bridge_1" H 4800 5100 60  0000 C CNN
+F 2 "" H 4800 4950 60  0000 C CNN
+F 3 "" H 4800 4950 60  0000 C CNN
+	1    4800 4950
+	1    0    0    -1  
+$EndComp
+$Comp
+L pulse v1
+U 1 1 68590F45
+P 3950 5350
+F 0 "v1" H 3750 5450 60  0000 C CNN
+F 1 "pulse" H 3750 5300 60  0000 C CNN
+F 2 "R1" H 3650 5350 60  0000 C CNN
+F 3 "" H 3950 5350 60  0000 C CNN
+	1    3950 5350
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_GND #PWR01
+U 1 1 68590F9C
+P 3950 5900
+F 0 "#PWR01" H 3950 5650 50  0001 C CNN
+F 1 "eSim_GND" H 3950 5750 50  0000 C CNN
+F 2 "" H 3950 5900 50  0001 C CNN
+F 3 "" H 3950 5900 50  0001 C CNN
+	1    3950 5900
+	1    0    0    -1  
+$EndComp
+Text GLabel 3900 4850 0    60   Input ~ 0
+cont
+$Comp
+L plot_v1 U3
+U 1 1 685912DC
+P 4150 5000
+F 0 "U3" H 4150 5500 60  0000 C CNN
+F 1 "plot_v1" H 4350 5350 60  0000 C CNN
+F 2 "" H 4150 5000 60  0000 C CNN
+F 3 "" H 4150 5000 60  0000 C CNN
+	1    4150 5000
+	1    0    0    -1  
+$EndComp
+Text GLabel 5350 3000 0    60   Input ~ 0
+in
+Text GLabel 3750 3200 0    60   Input ~ 0
+out
+$Comp
+L MC14016B_1 X1
+U 1 1 6859297B
+P 6000 3400
+F 0 "X1" H 6000 2750 60  0000 C CNN
+F 1 "MC14016B_1" H 6050 4050 60  0000 C CNN
+F 2 "" H 6000 3400 60  0001 C CNN
+F 3 "" H 6000 3400 60  0001 C CNN
+	1    6000 3400
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_Diode D3
+U 1 1 685929A9
+P 5150 2750
+F 0 "D3" H 5150 2850 50  0000 C CNN
+F 1 "eSim_Diode" H 5150 2650 50  0000 C CNN
+F 2 "" H 5150 2750 60  0000 C CNN
+F 3 "" H 5150 2750 60  0000 C CNN
+	1    5150 2750
+	0    1    -1   0   
+$EndComp
+$Comp
+L eSim_Diode D4
+U 1 1 68592A10
+P 5150 3350
+F 0 "D4" H 5150 3450 50  0000 C CNN
+F 1 "eSim_Diode" H 5150 3250 50  0000 C CNN
+F 2 "" H 5150 3350 60  0000 C CNN
+F 3 "" H 5150 3350 60  0000 C CNN
+	1    5150 3350
+	0    1    -1   0   
+$EndComp
+$Comp
+L eSim_GND #PWR02
+U 1 1 68592B24
+P 6950 3600
+F 0 "#PWR02" H 6950 3350 50  0001 C CNN
+F 1 "eSim_GND" H 6950 3450 50  0000 C CNN
+F 2 "" H 6950 3600 50  0001 C CNN
+F 3 "" H 6950 3600 50  0001 C CNN
+	1    6950 3600
+	1    0    0    -1  
+$EndComp
+$Comp
+L DC v3
+U 1 1 68592BA8
+P 7000 2700
+F 0 "v3" H 6800 2800 60  0000 C CNN
+F 1 "DC" H 6800 2650 60  0000 C CNN
+F 2 "R1" H 6700 2700 60  0000 C CNN
+F 3 "" H 7000 2700 60  0000 C CNN
+	1    7000 2700
+	1    0    0    1   
+$EndComp
+$Comp
+L eSim_GND #PWR03
+U 1 1 68592C20
+P 7150 2250
+F 0 "#PWR03" H 7150 2000 50  0001 C CNN
+F 1 "eSim_GND" H 7150 2100 50  0000 C CNN
+F 2 "" H 7150 2250 50  0001 C CNN
+F 3 "" H 7150 2250 50  0001 C CNN
+	1    7150 2250
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	3900 4850 4150 4850
+Wire Wire Line
+	5150 2900 5150 3200
+Wire Wire Line
+	4650 3100 5450 3100
+Connection ~ 5150 3100
+Wire Wire Line
+	5150 3500 5150 3950
+Wire Wire Line
+	5150 3950 6750 3950
+Wire Wire Line
+	6750 3600 6750 4200
+Wire Wire Line
+	6600 3600 6950 3600
+Connection ~ 6750 3600
+Wire Wire Line
+	6600 3150 7000 3150
+Wire Wire Line
+	7000 2250 7150 2250
+Wire Wire Line
+	5150 2600 6700 2600
+Wire Wire Line
+	6700 1900 6700 3150
+Connection ~ 6700 3150
+$Comp
+L sine v2
+U 1 1 68592D40
+P 4650 3550
+F 0 "v2" H 4450 3650 60  0000 C CNN
+F 1 "sine" H 4450 3500 60  0000 C CNN
+F 2 "R1" H 4350 3550 60  0000 C CNN
+F 3 "" H 4650 3550 60  0000 C CNN
+	1    4650 3550
+	1    0    0    -1  
+$EndComp
+$Comp
+L plot_v1 U4
+U 1 1 68592DC9
+P 5400 2700
+F 0 "U4" H 5400 3200 60  0000 C CNN
+F 1 "plot_v1" H 5600 3050 60  0000 C CNN
+F 2 "" H 5400 2700 60  0000 C CNN
+F 3 "" H 5400 2700 60  0000 C CNN
+	1    5400 2700
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5400 2500 5400 3100
+Connection ~ 5400 3100
+Wire Wire Line
+	5350 3000 5400 3000
+Connection ~ 5400 3000
+$Comp
+L eSim_Diode D1
+U 1 1 68592F9A
+P 4150 2800
+F 0 "D1" H 4150 2900 50  0000 C CNN
+F 1 "eSim_Diode" H 4150 2700 50  0000 C CNN
+F 2 "" H 4150 2800 60  0000 C CNN
+F 3 "" H 4150 2800 60  0000 C CNN
+	1    4150 2800
+	0    1    -1   0   
+$EndComp
+$Comp
+L eSim_Diode D2
+U 1 1 68592FA0
+P 4150 3400
+F 0 "D2" H 4150 3500 50  0000 C CNN
+F 1 "eSim_Diode" H 4150 3300 50  0000 C CNN
+F 2 "" H 4150 3400 60  0000 C CNN
+F 3 "" H 4150 3400 60  0000 C CNN
+	1    4150 3400
+	0    1    -1   0   
+$EndComp
+Wire Wire Line
+	4150 2950 4150 3250
+Wire Wire Line
+	4150 3550 4150 4200
+Wire Wire Line
+	4150 4200 6750 4200
+Connection ~ 6750 3950
+Wire Wire Line
+	4150 2650 4150 1900
+Wire Wire Line
+	4150 1900 6700 1900
+Connection ~ 6700 2600
+$Comp
+L eSim_GND #PWR04
+U 1 1 68593ACF
+P 4650 4100
+F 0 "#PWR04" H 4650 3850 50  0001 C CNN
+F 1 "eSim_GND" H 4650 3950 50  0000 C CNN
+F 2 "" H 4650 4100 50  0001 C CNN
+F 3 "" H 4650 4100 50  0001 C CNN
+	1    4650 4100
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4650 4000 4650 4100
+Wire Wire Line
+	5450 3650 4900 3650
+Wire Wire Line
+	4900 3650 4900 3050
+Wire Wire Line
+	4900 3050 3700 3050
+Connection ~ 4150 3050
+$Comp
+L plot_v1 U1
+U 1 1 68594041
+P 3700 3250
+F 0 "U1" H 3700 3750 60  0000 C CNN
+F 1 "plot_v1" H 3900 3600 60  0000 C CNN
+F 2 "" H 3700 3250 60  0000 C CNN
+F 3 "" H 3700 3250 60  0000 C CNN
+	1    3700 3250
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	3750 3200 3850 3200
+Wire Wire Line
+	3850 3200 3850 3050
+Connection ~ 3850 3050
+Wire Wire Line
+	5350 4900 5350 3300
+Wire Wire Line
+	5350 3300 5450 3300
+Wire Wire Line
+	3950 4900 4200 4900
+Wire Wire Line
+	3950 5800 3950 5900
+Wire Wire Line
+	4150 4800 4150 4900
+Connection ~ 4150 4900
+Connection ~ 4150 4850
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/MC14016B_One/MC14016B_onetest_Previous_Values.xml b/library/SubcircuitLibrary/MC14016B_One/MC14016B_onetest_Previous_Values.xml
new file mode 100644
index 000000000..6806df558
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B_One/MC14016B_onetest_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source><v3 name="Source type">dc<field1 name="Value">5</field1></v3><v2 name="Source type">sine<field1 name="Offset Value">0</field1><field2 name="Amplitude">5</field2><field3 name="Frequency">1k</field3><field4 name="Delay Time">0</field4><field5 name="Damping Factor" /></v2><v1 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">0.1n</field4><field5 name="Fall Time">0.1n</field5><field5 name="Pulse width">1m</field5><field5 name="Period">2m</field5></v1></source><model><u2 name="type">adc_bridge<field1 name="Enter value for in_low (default=1.0)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter Fall Delay (default=1.0e-9)" /></u2></model><devicemodel><d3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d3><d4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d4><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><d2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d2></devicemodel><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\MC14016B</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">1</field2><field3 name="Stop Time">10</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">us</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14016B_One/NMOS-5um.lib b/library/SubcircuitLibrary/MC14016B_One/NMOS-5um.lib
new file mode 100644
index 000000000..a237e1fe3
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B_One/NMOS-5um.lib
@@ -0,0 +1,5 @@
+* 5um technology
+
+.model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7 
++ Level=1
++ Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n  )
diff --git a/library/SubcircuitLibrary/MC14016B_One/PMOS-5um.lib b/library/SubcircuitLibrary/MC14016B_One/PMOS-5um.lib
new file mode 100644
index 000000000..9c3ed9760
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B_One/PMOS-5um.lib
@@ -0,0 +1,5 @@
+*5um technology
+
+.model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65
++ Level=1
++ Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n  )
diff --git a/library/SubcircuitLibrary/MC14016B_One/analysis b/library/SubcircuitLibrary/MC14016B_One/analysis
new file mode 100644
index 000000000..b21a9e13b
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B_One/analysis
@@ -0,0 +1 @@
+.tran 1e-06 10e-03 0e-03
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14076B/MC14076B-cache.lib b/library/SubcircuitLibrary/MC14076B/MC14076B-cache.lib
new file mode 100644
index 000000000..8b4e4048e
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14076B/MC14076B-cache.lib
@@ -0,0 +1,143 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_flip
+#
+DEF d_flip U 0 40 Y Y 1 F N
+F0 "U" 2850 1800 60 H V C CNN
+F1 "d_flip" 2850 2000 60 H V C CNN
+F2 "" 2850 1950 60 H V C CNN
+F3 "" 2850 1950 60 H V C CNN
+DRAW
+S 2350 2100 3350 1500 0 1 0 N
+X d0 1 2150 1900 200 R 50 50 1 1 I
+X clk0 2 2150 1800 200 R 50 50 1 1 I
+X rst_n0 3 2150 1700 200 R 50 50 1 1 I
+X q0 4 3550 1900 200 L 50 50 1 1 O
+X q_bar0 5 3550 1800 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nand
+#
+DEF d_nand U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nand" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# tristate_inverter
+#
+DEF tristate_inverter U 0 40 Y Y 1 F N
+F0 "U" 2850 1800 60 H V C CNN
+F1 "tristate_inverter" 2850 2000 60 H V C CNN
+F2 "" 2850 1950 60 H V C CNN
+F3 "" 2850 1950 60 H V C CNN
+DRAW
+S 2350 2100 3350 1600 0 1 0 N
+X a0 1 2150 1900 200 R 50 50 1 1 I
+X en0 2 2150 1800 200 R 50 50 1 1 I
+X y0 3 3550 1900 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/MC14076B/MC14076B.cir b/library/SubcircuitLibrary/MC14076B/MC14076B.cir
new file mode 100644
index 000000000..b50d521a1
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14076B/MC14076B.cir
@@ -0,0 +1,37 @@
+* C:\Users\pavithra\eSim-Workspace\MC14076B\MC14076B.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/20/25 15:45:00
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U7  Net-_U19-Pad3_ Net-_U10-Pad2_ Net-_U10-Pad3_ Net-_U11-Pad1_ Net-_U24-Pad2_ d_flip		
+U19  Net-_U11-Pad3_ Net-_U12-Pad3_ Net-_U19-Pad3_ d_or		
+U11  Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_and		
+U12  Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_and		
+U5  Net-_U12-Pad2_ Net-_U11-Pad2_ d_inverter		
+U2  Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U12-Pad2_ d_nand		
+U8  Net-_U20-Pad3_ Net-_U10-Pad2_ Net-_U10-Pad3_ Net-_U13-Pad1_ Net-_U23-Pad2_ d_flip		
+U20  Net-_U13-Pad3_ Net-_U14-Pad3_ Net-_U20-Pad3_ d_or		
+U13  Net-_U13-Pad1_ Net-_U11-Pad2_ Net-_U13-Pad3_ d_and		
+U14  Net-_U14-Pad1_ Net-_U12-Pad2_ Net-_U14-Pad3_ d_and		
+U9  Net-_U21-Pad3_ Net-_U10-Pad2_ Net-_U10-Pad3_ Net-_U15-Pad1_ Net-_U25-Pad2_ d_flip		
+U21  Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U21-Pad3_ d_or		
+U15  Net-_U15-Pad1_ Net-_U11-Pad2_ Net-_U15-Pad3_ d_and		
+U16  Net-_U16-Pad1_ Net-_U12-Pad2_ Net-_U16-Pad3_ d_and		
+U10  Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ Net-_U10-Pad4_ Net-_U10-Pad5_ d_flip		
+U22  Net-_U17-Pad3_ Net-_U18-Pad3_ Net-_U10-Pad1_ d_or		
+U17  Net-_U10-Pad4_ Net-_U11-Pad2_ Net-_U17-Pad3_ d_and		
+U18  Net-_U18-Pad1_ Net-_U12-Pad2_ Net-_U18-Pad3_ d_and		
+U3  Net-_U27-Pad7_ Net-_U10-Pad2_ d_inverter		
+U4  Net-_U27-Pad15_ Net-_U10-Pad3_ d_inverter		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ d_nand		
+U6  Net-_U1-Pad3_ Net-_U23-Pad1_ d_inverter		
+U24  Net-_U23-Pad1_ Net-_U24-Pad2_ Net-_U24-Pad3_ tristate_inverter		
+U23  Net-_U23-Pad1_ Net-_U23-Pad2_ Net-_U23-Pad3_ tristate_inverter		
+U25  Net-_U23-Pad1_ Net-_U25-Pad2_ Net-_U25-Pad3_ tristate_inverter		
+U26  Net-_U23-Pad1_ Net-_U10-Pad5_ Net-_U26-Pad3_ tristate_inverter		
+U27  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U24-Pad3_ Net-_U23-Pad3_ Net-_U25-Pad3_ Net-_U26-Pad3_ Net-_U27-Pad7_ ? Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U18-Pad1_ Net-_U16-Pad1_ Net-_U14-Pad1_ Net-_U12-Pad1_ Net-_U27-Pad15_ ? PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/MC14076B/MC14076B.cir.out b/library/SubcircuitLibrary/MC14076B/MC14076B.cir.out
new file mode 100644
index 000000000..6eff3fe40
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14076B/MC14076B.cir.out
@@ -0,0 +1,116 @@
+* c:\fossee\esim\library\subcircuitlibrary\mc14076b\mc14076b.cir
+
+* u19  net-_u11-pad3_ net-_u12-pad3_ net-_u19-pad3_ d_or
+* u11  net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and
+* u12  net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_and
+* u5  net-_u12-pad2_ net-_u11-pad2_ d_inverter
+* u2  net-_u2-pad1_ net-_u2-pad2_ net-_u12-pad2_ d_nand
+* u20  net-_u13-pad3_ net-_u14-pad3_ net-_u20-pad3_ d_or
+* u13  net-_u13-pad1_ net-_u11-pad2_ net-_u13-pad3_ d_and
+* u14  net-_u14-pad1_ net-_u12-pad2_ net-_u14-pad3_ d_and
+* u21  net-_u15-pad3_ net-_u16-pad3_ net-_u21-pad3_ d_or
+* u15  net-_u15-pad1_ net-_u11-pad2_ net-_u15-pad3_ d_and
+* u16  net-_u16-pad1_ net-_u12-pad2_ net-_u16-pad3_ d_and
+* u22  net-_u17-pad3_ net-_u18-pad3_ net-_u10-pad1_ d_or
+* u17  net-_u10-pad4_ net-_u11-pad2_ net-_u17-pad3_ d_and
+* u18  net-_u18-pad1_ net-_u12-pad2_ net-_u18-pad3_ d_and
+* u3  net-_u27-pad7_ net-_u10-pad2_ d_inverter
+* u4  net-_u27-pad15_ net-_u10-pad3_ d_inverter
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_nand
+* u6  net-_u1-pad3_ net-_u23-pad1_ d_inverter
+* u24  net-_u23-pad1_ net-_u24-pad2_ net-_u24-pad3_ tristate_inverter
+* u23  net-_u23-pad1_ net-_u23-pad2_ net-_u23-pad3_ tristate_inverter
+* u25  net-_u23-pad1_ net-_u25-pad2_ net-_u25-pad3_ tristate_inverter
+* u26  net-_u23-pad1_ net-_u10-pad5_ net-_u26-pad3_ tristate_inverter
+* u27  net-_u1-pad1_ net-_u1-pad2_ net-_u24-pad3_ net-_u23-pad3_ net-_u25-pad3_ net-_u26-pad3_ net-_u27-pad7_ ? net-_u2-pad1_ net-_u2-pad2_ net-_u18-pad1_ net-_u16-pad1_ net-_u14-pad1_ net-_u12-pad1_ net-_u27-pad15_ ? port
+* u7  net-_u19-pad3_ net-_u10-pad2_ net-_u10-pad3_ net-_u11-pad1_ net-_u24-pad2_ d_flip
+* u8  net-_u20-pad3_ net-_u10-pad2_ net-_u10-pad3_ net-_u13-pad1_ net-_u23-pad2_ d_flip
+* u9  net-_u21-pad3_ net-_u10-pad2_ net-_u10-pad3_ net-_u15-pad1_ net-_u25-pad2_ d_flip
+* u10  net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ net-_u10-pad4_ net-_u10-pad5_ d_flip
+a1 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u19-pad3_ u19
+a2 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a3 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12
+a4 net-_u12-pad2_ net-_u11-pad2_ u5
+a5 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u12-pad2_ u2
+a6 [net-_u13-pad3_ net-_u14-pad3_ ] net-_u20-pad3_ u20
+a7 [net-_u13-pad1_ net-_u11-pad2_ ] net-_u13-pad3_ u13
+a8 [net-_u14-pad1_ net-_u12-pad2_ ] net-_u14-pad3_ u14
+a9 [net-_u15-pad3_ net-_u16-pad3_ ] net-_u21-pad3_ u21
+a10 [net-_u15-pad1_ net-_u11-pad2_ ] net-_u15-pad3_ u15
+a11 [net-_u16-pad1_ net-_u12-pad2_ ] net-_u16-pad3_ u16
+a12 [net-_u17-pad3_ net-_u18-pad3_ ] net-_u10-pad1_ u22
+a13 [net-_u10-pad4_ net-_u11-pad2_ ] net-_u17-pad3_ u17
+a14 [net-_u18-pad1_ net-_u12-pad2_ ] net-_u18-pad3_ u18
+a15 net-_u27-pad7_ net-_u10-pad2_ u3
+a16 net-_u27-pad15_ net-_u10-pad3_ u4
+a17 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u1
+a18 net-_u1-pad3_ net-_u23-pad1_ u6
+a19 [net-_u23-pad1_ ] [net-_u24-pad2_ ] [net-_u24-pad3_ ] u24
+a20 [net-_u23-pad1_ ] [net-_u23-pad2_ ] [net-_u23-pad3_ ] u23
+a21 [net-_u23-pad1_ ] [net-_u25-pad2_ ] [net-_u25-pad3_ ] u25
+a22 [net-_u23-pad1_ ] [net-_u10-pad5_ ] [net-_u26-pad3_ ] u26
+a23 [net-_u19-pad3_ ] [net-_u10-pad2_ ] [net-_u10-pad3_ ] [net-_u11-pad1_ ] [net-_u24-pad2_ ] u7
+a24 [net-_u20-pad3_ ] [net-_u10-pad2_ ] [net-_u10-pad3_ ] [net-_u13-pad1_ ] [net-_u23-pad2_ ] u8
+a25 [net-_u21-pad3_ ] [net-_u10-pad2_ ] [net-_u10-pad3_ ] [net-_u15-pad1_ ] [net-_u25-pad2_ ] u9
+a26 [net-_u10-pad1_ ] [net-_u10-pad2_ ] [net-_u10-pad3_ ] [net-_u10-pad4_ ] [net-_u10-pad5_ ] u10
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u19 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u20 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u21 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u22 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u1 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             tristate_inverter, NgSpice Name: tristate_inverter
+.model u24 tristate_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
+* Schematic Name:                             tristate_inverter, NgSpice Name: tristate_inverter
+.model u23 tristate_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
+* Schematic Name:                             tristate_inverter, NgSpice Name: tristate_inverter
+.model u25 tristate_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
+* Schematic Name:                             tristate_inverter, NgSpice Name: tristate_inverter
+.model u26 tristate_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
+* Schematic Name:                             d_flip, NgSpice Name: d_flip
+.model u7 d_flip(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
+* Schematic Name:                             d_flip, NgSpice Name: d_flip
+.model u8 d_flip(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
+* Schematic Name:                             d_flip, NgSpice Name: d_flip
+.model u9 d_flip(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
+* Schematic Name:                             d_flip, NgSpice Name: d_flip
+.model u10 d_flip(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/MC14076B/MC14076B.pro b/library/SubcircuitLibrary/MC14076B/MC14076B.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14076B/MC14076B.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/MC14076B/MC14076B.proj b/library/SubcircuitLibrary/MC14076B/MC14076B.proj
new file mode 100644
index 000000000..19428788d
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14076B/MC14076B.proj
@@ -0,0 +1 @@
+schematicFile MC14076B.sch
diff --git a/library/SubcircuitLibrary/MC14076B/MC14076B.sch b/library/SubcircuitLibrary/MC14076B/MC14076B.sch
new file mode 100644
index 000000000..a40dff83f
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14076B/MC14076B.sch
@@ -0,0 +1,701 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A1 33110 23386
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
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+Comment2 ""
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+Comment4 ""
+$EndDescr
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+F 2 "" H 11650 10150 60  0000 C CNN
+F 3 "" H 11650 10150 60  0000 C CNN
+	1    8800 8200
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+F 2 "" H 10350 6350 60  0000 C CNN
+F 3 "" H 10350 6350 60  0000 C CNN
+	1    10350 6350
+	1    0    0    -1  
+$EndComp
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+F 2 "" H 9300 6150 60  0000 C CNN
+F 3 "" H 9300 6150 60  0000 C CNN
+	1    9300 6150
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+F 2 "" H 9300 6550 60  0000 C CNN
+F 3 "" H 9300 6550 60  0000 C CNN
+	1    9300 6550
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+F 3 "" H 8350 7200 60  0000 C CNN
+	1    8300 7250
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+F 3 "" H 7350 7300 60  0000 C CNN
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+F 3 "" H 11700 12050 60  0000 C CNN
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+F 3 "" H 10400 8250 60  0000 C CNN
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+F 3 "" H 11750 13300 60  0000 C CNN
+	1    8900 11350
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+F 3 "" H 9400 9300 60  0000 C CNN
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+F 3 "" H 9400 9700 60  0000 C CNN
+	1    9400 9700
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+F 2 "" H 11750 14400 60  0000 C CNN
+F 3 "" H 11750 14400 60  0000 C CNN
+	1    8900 12450
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+F 3 "" H 10450 10600 60  0000 C CNN
+	1    10450 10600
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+F 2 "" H 9400 10400 60  0000 C CNN
+F 3 "" H 9400 10400 60  0000 C CNN
+	1    9400 10400
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+F 2 "" H 9400 10800 60  0000 C CNN
+F 3 "" H 9400 10800 60  0000 C CNN
+	1    9400 10800
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+F 2 "" H 7450 8650 60  0000 C CNN
+F 3 "" H 7450 8650 60  0000 C CNN
+	1    7400 8700
+	1    0    0    -1  
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+Wire Wire Line
+	9750 6500 9900 6500
+Wire Wire Line
+	9900 6500 9900 6350
+Wire Wire Line
+	9750 6100 9900 6100
+Wire Wire Line
+	9900 6100 9900 6250
+Wire Wire Line
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+Wire Wire Line
+	8850 5900 12350 5900
+Wire Wire Line
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+Wire Wire Line
+	7800 7250 8000 7250
+Wire Wire Line
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+Wire Wire Line
+	7900 6550 7900 10800
+Connection ~ 7900 7250
+Wire Wire Line
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+Wire Wire Line
+	9800 8400 9950 8400
+Wire Wire Line
+	9950 8400 9950 8250
+Wire Wire Line
+	9800 8000 9950 8000
+Wire Wire Line
+	9950 8000 9950 8150
+Wire Wire Line
+	8900 7950 8900 7800
+Wire Wire Line
+	8900 7800 12400 7800
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+	9850 9650 10000 9650
+Wire Wire Line
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+	9850 9250 10000 9250
+Wire Wire Line
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+	8950 9200 8950 9050
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+	9850 10750 10000 10750
+Wire Wire Line
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+Wire Wire Line
+	9850 10350 10000 10350
+Wire Wire Line
+	10000 10350 10000 10500
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+Wire Wire Line
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+	12450 10150 12450 10550
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+	10950 8400 11000 8400
+Wire Wire Line
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+Wire Wire Line
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+F 2 "" H 7500 11200 60  0000 C CNN
+F 3 "" H 7500 11200 60  0000 C CNN
+	1    7450 11250
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+$Comp
+L d_nand U1
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+F 2 "" H 7350 5400 60  0000 C CNN
+F 3 "" H 7350 5400 60  0000 C CNN
+	1    7350 5400
+	1    0    0    -1  
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+F 2 "" H 8500 5300 60  0000 C CNN
+F 3 "" H 8500 5300 60  0000 C CNN
+	1    8450 5350
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+$EndComp
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+F 0 "U24" H 13400 10000 60  0000 C CNN
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+F 2 "" H 13400 10150 60  0000 C CNN
+F 3 "" H 13400 10150 60  0000 C CNN
+	1    10550 8200
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+F 2 "" H 13350 12050 60  0000 C CNN
+F 3 "" H 13350 12050 60  0000 C CNN
+	1    10500 10100
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+F 2 "" H 13400 13300 60  0000 C CNN
+F 3 "" H 13400 13300 60  0000 C CNN
+	1    10550 11350
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+F 0 "U26" H 13450 14250 60  0000 C CNN
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+F 2 "" H 13450 14400 60  0000 C CNN
+F 3 "" H 13450 14400 60  0000 C CNN
+	1    10600 12450
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+F 2 "" H 6350 5450 60  0000 C CNN
+F 3 "" H 6350 5450 60  0000 C CNN
+	2    6350 5450
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+F 2 "" H 6350 5300 60  0000 C CNN
+F 3 "" H 6350 5300 60  0000 C CNN
+	1    6350 5300
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+F 2 "" H 14550 6300 60  0000 C CNN
+F 3 "" H 14550 6300 60  0000 C CNN
+	3    14550 6300
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+F 2 "" H 14550 8200 60  0000 C CNN
+F 3 "" H 14550 8200 60  0000 C CNN
+	4    14550 8200
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+F 2 "" H 14600 9450 60  0000 C CNN
+F 3 "" H 14600 9450 60  0000 C CNN
+	5    14600 9450
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+F 2 "" H 14650 10550 60  0000 C CNN
+F 3 "" H 14650 10550 60  0000 C CNN
+	6    14650 10550
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+F 2 "" H 6650 8700 60  0000 C CNN
+F 3 "" H 6650 8700 60  0000 C CNN
+	7    6650 8700
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+F 2 "" H 6500 7100 60  0000 C CNN
+F 3 "" H 6500 7100 60  0000 C CNN
+	9    6500 7100
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+$Comp
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+F 2 "" H 14050 4850 60  0000 C CNN
+F 3 "" H 14050 4850 60  0000 C CNN
+	8    14050 4850
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+F 2 "" H 8500 10700 60  0000 C CNN
+F 3 "" H 8500 10700 60  0000 C CNN
+	11   8500 10700
+	1    0    0    -1  
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+F 2 "" H 6500 7400 60  0000 C CNN
+F 3 "" H 6500 7400 60  0000 C CNN
+	10   6500 7400
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+F 2 "" H 8250 9600 60  0000 C CNN
+F 3 "" H 8250 9600 60  0000 C CNN
+	12   8250 9600
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+	13   8350 8350
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+F 2 "" H 8300 6450 60  0000 C CNN
+F 3 "" H 8300 6450 60  0000 C CNN
+	14   8300 6450
+	1    0    0    -1  
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+F 1 "PORT" H 6700 11250 30  0000 C CNN
+F 2 "" H 6700 11250 60  0000 C CNN
+F 3 "" H 6700 11250 60  0000 C CNN
+	15   6700 11250
+	1    0    0    -1  
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+$Comp
+L PORT U27
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+F 1 "PORT" H 14050 5150 30  0000 C CNN
+F 2 "" H 14050 5150 60  0000 C CNN
+F 3 "" H 14050 5150 60  0000 C CNN
+	16   14050 5150
+	1    0    0    -1  
+$EndComp
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+Wire Wire Line
+	6600 5450 6900 5450
+Wire Wire Line
+	6900 5450 6900 5400
+Wire Wire Line
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+Wire Wire Line
+	14300 8200 14050 8200
+Wire Wire Line
+	14100 9450 14350 9450
+Wire Wire Line
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+Wire Wire Line
+	6900 8700 7100 8700
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+Wire Wire Line
+	6750 7100 6900 7100
+Wire Wire Line
+	6900 7100 6900 7200
+Wire Wire Line
+	6750 7400 6900 7400
+Wire Wire Line
+	6900 7400 6900 7300
+Wire Wire Line
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+Wire Wire Line
+	8500 9600 8950 9600
+Wire Wire Line
+	8600 8350 8900 8350
+Wire Wire Line
+	8550 6450 8850 6450
+NoConn ~ 14300 5150
+Wire Wire Line
+	6950 11250 7150 11250
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/MC14076B/MC14076B.sub b/library/SubcircuitLibrary/MC14076B/MC14076B.sub
new file mode 100644
index 000000000..b4205b4d2
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14076B/MC14076B.sub
@@ -0,0 +1,110 @@
+* Subcircuit MC14076B
+.subckt MC14076B net-_u1-pad1_ net-_u1-pad2_ net-_u24-pad3_ net-_u23-pad3_ net-_u25-pad3_ net-_u26-pad3_ net-_u27-pad7_ ? net-_u2-pad1_ net-_u2-pad2_ net-_u18-pad1_ net-_u16-pad1_ net-_u14-pad1_ net-_u12-pad1_ net-_u27-pad15_ ? 
+* c:\fossee\esim\library\subcircuitlibrary\mc14076b\mc14076b.cir
+* u19  net-_u11-pad3_ net-_u12-pad3_ net-_u19-pad3_ d_or
+* u11  net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and
+* u12  net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_and
+* u5  net-_u12-pad2_ net-_u11-pad2_ d_inverter
+* u2  net-_u2-pad1_ net-_u2-pad2_ net-_u12-pad2_ d_nand
+* u20  net-_u13-pad3_ net-_u14-pad3_ net-_u20-pad3_ d_or
+* u13  net-_u13-pad1_ net-_u11-pad2_ net-_u13-pad3_ d_and
+* u14  net-_u14-pad1_ net-_u12-pad2_ net-_u14-pad3_ d_and
+* u21  net-_u15-pad3_ net-_u16-pad3_ net-_u21-pad3_ d_or
+* u15  net-_u15-pad1_ net-_u11-pad2_ net-_u15-pad3_ d_and
+* u16  net-_u16-pad1_ net-_u12-pad2_ net-_u16-pad3_ d_and
+* u22  net-_u17-pad3_ net-_u18-pad3_ net-_u10-pad1_ d_or
+* u17  net-_u10-pad4_ net-_u11-pad2_ net-_u17-pad3_ d_and
+* u18  net-_u18-pad1_ net-_u12-pad2_ net-_u18-pad3_ d_and
+* u3  net-_u27-pad7_ net-_u10-pad2_ d_inverter
+* u4  net-_u27-pad15_ net-_u10-pad3_ d_inverter
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_nand
+* u6  net-_u1-pad3_ net-_u23-pad1_ d_inverter
+* u24  net-_u23-pad1_ net-_u24-pad2_ net-_u24-pad3_ tristate_inverter
+* u23  net-_u23-pad1_ net-_u23-pad2_ net-_u23-pad3_ tristate_inverter
+* u25  net-_u23-pad1_ net-_u25-pad2_ net-_u25-pad3_ tristate_inverter
+* u26  net-_u23-pad1_ net-_u10-pad5_ net-_u26-pad3_ tristate_inverter
+* u7  net-_u19-pad3_ net-_u10-pad2_ net-_u10-pad3_ net-_u11-pad1_ net-_u24-pad2_ d_flip
+* u8  net-_u20-pad3_ net-_u10-pad2_ net-_u10-pad3_ net-_u13-pad1_ net-_u23-pad2_ d_flip
+* u9  net-_u21-pad3_ net-_u10-pad2_ net-_u10-pad3_ net-_u15-pad1_ net-_u25-pad2_ d_flip
+* u10  net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ net-_u10-pad4_ net-_u10-pad5_ d_flip
+a1 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u19-pad3_ u19
+a2 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a3 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12
+a4 net-_u12-pad2_ net-_u11-pad2_ u5
+a5 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u12-pad2_ u2
+a6 [net-_u13-pad3_ net-_u14-pad3_ ] net-_u20-pad3_ u20
+a7 [net-_u13-pad1_ net-_u11-pad2_ ] net-_u13-pad3_ u13
+a8 [net-_u14-pad1_ net-_u12-pad2_ ] net-_u14-pad3_ u14
+a9 [net-_u15-pad3_ net-_u16-pad3_ ] net-_u21-pad3_ u21
+a10 [net-_u15-pad1_ net-_u11-pad2_ ] net-_u15-pad3_ u15
+a11 [net-_u16-pad1_ net-_u12-pad2_ ] net-_u16-pad3_ u16
+a12 [net-_u17-pad3_ net-_u18-pad3_ ] net-_u10-pad1_ u22
+a13 [net-_u10-pad4_ net-_u11-pad2_ ] net-_u17-pad3_ u17
+a14 [net-_u18-pad1_ net-_u12-pad2_ ] net-_u18-pad3_ u18
+a15 net-_u27-pad7_ net-_u10-pad2_ u3
+a16 net-_u27-pad15_ net-_u10-pad3_ u4
+a17 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u1
+a18 net-_u1-pad3_ net-_u23-pad1_ u6
+a19 [net-_u23-pad1_ ] [net-_u24-pad2_ ] [net-_u24-pad3_ ] u24
+a20 [net-_u23-pad1_ ] [net-_u23-pad2_ ] [net-_u23-pad3_ ] u23
+a21 [net-_u23-pad1_ ] [net-_u25-pad2_ ] [net-_u25-pad3_ ] u25
+a22 [net-_u23-pad1_ ] [net-_u10-pad5_ ] [net-_u26-pad3_ ] u26
+a23 [net-_u19-pad3_ ] [net-_u10-pad2_ ] [net-_u10-pad3_ ] [net-_u11-pad1_ ] [net-_u24-pad2_ ] u7
+a24 [net-_u20-pad3_ ] [net-_u10-pad2_ ] [net-_u10-pad3_ ] [net-_u13-pad1_ ] [net-_u23-pad2_ ] u8
+a25 [net-_u21-pad3_ ] [net-_u10-pad2_ ] [net-_u10-pad3_ ] [net-_u15-pad1_ ] [net-_u25-pad2_ ] u9
+a26 [net-_u10-pad1_ ] [net-_u10-pad2_ ] [net-_u10-pad3_ ] [net-_u10-pad4_ ] [net-_u10-pad5_ ] u10
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u19 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u20 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u21 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u22 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u1 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             tristate_inverter, NgSpice Name: tristate_inverter
+.model u24 tristate_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name:                             tristate_inverter, NgSpice Name: tristate_inverter
+.model u23 tristate_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name:                             tristate_inverter, NgSpice Name: tristate_inverter
+.model u25 tristate_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name:                             tristate_inverter, NgSpice Name: tristate_inverter
+.model u26 tristate_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name:                             d_flip, NgSpice Name: d_flip
+.model u7 d_flip(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name:                             d_flip, NgSpice Name: d_flip
+.model u8 d_flip(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name:                             d_flip, NgSpice Name: d_flip
+.model u9 d_flip(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name:                             d_flip, NgSpice Name: d_flip
+.model u10 d_flip(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Control Statements
+
+.ends MC14076B
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14076B/MC14076B_Previous_Values.xml b/library/SubcircuitLibrary/MC14076B/MC14076B_Previous_Values.xml
new file mode 100644
index 000000000..dd87de853
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14076B/MC14076B_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u7 name="type">d_flip<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /><field4 name="Enter Instance ID (Between 0-99)" /></u7><u19 name="type">d_or<field5 name="Enter Rise Delay (default=1.0e-9)" /><field6 name="Enter Fall Delay (default=1.0e-9)" /><field7 name="Enter Input Load (default=1.0e-12)" /></u19><u11 name="type">d_and<field8 name="Enter Rise Delay (default=1.0e-9)" /><field9 name="Enter Fall Delay (default=1.0e-9)" /><field10 name="Enter Input Load (default=1.0e-12)" /></u11><u12 name="type">d_and<field11 name="Enter Rise Delay (default=1.0e-9)" /><field12 name="Enter Fall Delay (default=1.0e-9)" /><field13 name="Enter Input Load (default=1.0e-12)" /></u12><u5 name="type">d_inverter<field14 name="Enter Rise Delay (default=1.0e-9)" /><field15 name="Enter Fall Delay (default=1.0e-9)" /><field16 name="Enter Input Load (default=1.0e-12)" /></u5><u2 name="type">d_nand<field17 name="Enter Rise Delay (default=1.0e-9)" /><field18 name="Enter Fall Delay (default=1.0e-9)" /><field19 name="Enter Input Load (default=1.0e-12)" /></u2><u8 name="type">d_flip<field20 name="Enter Rise Delay (default=1.0e-9)" /><field21 name="Enter Fall Delay (default=1.0e-9)" /><field22 name="Enter Input Load (default=1.0e-12)" /><field23 name="Enter Instance ID (Between 0-99)" /></u8><u20 name="type">d_or<field24 name="Enter Rise Delay (default=1.0e-9)" /><field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /></u20><u13 name="type">d_and<field27 name="Enter Rise Delay (default=1.0e-9)" /><field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /></u13><u14 name="type">d_and<field30 name="Enter Rise Delay (default=1.0e-9)" /><field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /></u14><u9 name="type">d_flip<field33 name="Enter Rise Delay (default=1.0e-9)" /><field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Instance ID (Between 0-99)" /></u9><u21 name="type">d_or<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u21><u15 name="type">d_and<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u15><u16 name="type">d_and<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u16><u10 name="type">d_flip<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /><field49 name="Enter Instance ID (Between 0-99)" /></u10><u22 name="type">d_or<field50 name="Enter Rise Delay (default=1.0e-9)" /><field51 name="Enter Fall Delay (default=1.0e-9)" /><field52 name="Enter Input Load (default=1.0e-12)" /></u22><u17 name="type">d_and<field53 name="Enter Rise Delay (default=1.0e-9)" /><field54 name="Enter Fall Delay (default=1.0e-9)" /><field55 name="Enter Input Load (default=1.0e-12)" /></u17><u18 name="type">d_and<field56 name="Enter Rise Delay (default=1.0e-9)" /><field57 name="Enter Fall Delay (default=1.0e-9)" /><field58 name="Enter Input Load (default=1.0e-12)" /></u18><u3 name="type">d_inverter<field59 name="Enter Rise Delay (default=1.0e-9)" /><field60 name="Enter Fall Delay (default=1.0e-9)" /><field61 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_inverter<field62 name="Enter Rise Delay (default=1.0e-9)" /><field63 name="Enter Fall Delay (default=1.0e-9)" /><field64 name="Enter Input Load (default=1.0e-12)" /></u4><u1 name="type">d_nand<field65 name="Enter Rise Delay (default=1.0e-9)" /><field66 name="Enter Fall Delay (default=1.0e-9)" /><field67 name="Enter Input Load (default=1.0e-12)" /></u1><u6 name="type">d_inverter<field68 name="Enter Rise Delay (default=1.0e-9)" /><field69 name="Enter Fall Delay (default=1.0e-9)" /><field70 name="Enter Input Load (default=1.0e-12)" /></u6><u24 name="type">tristate_inverter<field71 name="Enter Rise Delay (default=1.0e-9)" /><field72 name="Enter Fall Delay (default=1.0e-9)" /><field73 name="Enter Input Load (default=1.0e-12)" /><field74 name="Enter Instance ID (Between 0-99)" /></u24><u23 name="type">tristate_inverter<field75 name="Enter Rise Delay (default=1.0e-9)" /><field76 name="Enter Fall Delay (default=1.0e-9)" /><field77 name="Enter Input Load (default=1.0e-12)" /><field78 name="Enter Instance ID (Between 0-99)" /></u23><u25 name="type">tristate_inverter<field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Fall Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /><field82 name="Enter Instance ID (Between 0-99)" /></u25><u26 name="type">tristate_inverter<field83 name="Enter Rise Delay (default=1.0e-9)" /><field84 name="Enter Fall Delay (default=1.0e-9)" /><field85 name="Enter Input Load (default=1.0e-12)" /><field86 name="Enter Instance ID (Between 0-99)" /></u26></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14076B/MC14076B_test-cache.lib b/library/SubcircuitLibrary/MC14076B/MC14076B_test-cache.lib
new file mode 100644
index 000000000..4098fce1e
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14076B/MC14076B_test-cache.lib
@@ -0,0 +1,170 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# DC
+#
+DEF DC v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 w
+X - 2 0 -450 300 U 50 50 1 1 w
+ENDDRAW
+ENDDEF
+#
+# MC14076B
+#
+DEF MC14076B X 0 40 Y Y 1 F N
+F0 "X" 0 -950 60 H V C CNN
+F1 "MC14076B" 50 850 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -450 750 450 -750 0 1 0 N
+X A 1 -650 650 200 R 50 50 1 1 I
+X B 2 -650 500 200 R 50 50 1 1 I
+X Q0 3 -650 300 200 R 50 50 1 1 O
+X Q1 4 -650 100 200 R 50 50 1 1 O
+X Q2 5 -650 -100 200 R 50 50 1 1 O
+X Q3 6 -650 -300 200 R 50 50 1 1 O
+X C 7 -650 -500 200 R 50 50 1 1 I
+X VSS 8 -650 -700 200 R 50 50 1 1 I
+X A 9 650 -700 200 L 50 50 1 1 I
+X B 10 650 -500 200 L 50 50 1 1 I
+X D3 11 650 -300 200 L 50 50 1 1 I
+X D2 12 650 -100 200 L 50 50 1 1 I
+X D1 13 650 100 200 L 50 50 1 1 I
+X D0 14 650 300 200 L 50 50 1 1 I
+X R 15 650 500 200 L 50 50 1 1 I
+X VDD 16 650 650 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_1
+#
+DEF adc_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_2
+#
+DEF adc_bridge_2 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_2" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -100 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X OUT1 3 550 50 200 L 50 50 1 1 O
+X OUT2 4 550 -50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_5
+#
+DEF adc_bridge_5 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_5" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -400 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X IN4 4 -600 -250 200 R 50 50 1 1 I
+X IN5 5 -600 -350 200 R 50 50 1 1 I
+X OUT1 6 550 50 200 L 50 50 1 1 O
+X OUT2 7 550 -50 200 L 50 50 1 1 O
+X OUT3 8 550 -150 200 L 50 50 1 1 O
+X OUT4 9 550 -250 200 L 50 50 1 1 O
+X OUT5 10 550 -350 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_4
+#
+DEF dac_bridge_4 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_4" 0 300 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -350 350 350 -200 0 1 0 N
+X IN1 1 -550 200 200 R 50 50 1 1 I
+X IN2 2 -550 100 200 R 50 50 1 1 I
+X IN3 3 -550 0 200 R 50 50 1 1 I
+X IN4 4 -550 -100 200 R 50 50 1 1 I
+X OUT1 5 550 200 200 L 50 50 1 1 O
+X OUT2 6 550 100 200 L 50 50 1 1 O
+X OUT3 7 550 0 200 L 50 50 1 1 O
+X OUT4 8 550 -100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_GND
+#
+DEF eSim_GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "eSim_GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# pulse
+#
+DEF pulse v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "pulse" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -25 -450 501 928 871 0 1 0 N -50 50 0 50
+A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50
+A 75 600 551 -926 -873 0 1 0 N 50 50 100 50
+A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50
+A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50
+A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/MC14076B/MC14076B_test.cir b/library/SubcircuitLibrary/MC14076B/MC14076B_test.cir
new file mode 100644
index 000000000..3c5fe27e7
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14076B/MC14076B_test.cir
@@ -0,0 +1,38 @@
+* C:\Users\pavithra\eSim-Workspace\MC14076B_test\MC14076B_test.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/20/25 17:49:07
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U6  Net-_U6-Pad1_ Net-_U6-Pad2_ Net-_U6-Pad3_ Net-_U6-Pad4_ adc_bridge_2		
+v1  Net-_U6-Pad1_ GND DC		
+v3  Net-_U6-Pad2_ GND DC		
+U8  Net-_U8-Pad1_ Net-_U8-Pad2_ Net-_U8-Pad3_ Net-_U8-Pad4_ W X Y Z dac_bridge_4		
+U10  Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ Net-_U10-Pad4_ adc_bridge_2		
+v6  Net-_U10-Pad1_ GND DC		
+v5  Net-_U10-Pad2_ GND DC		
+U11  RST A B C D Net-_U11-Pad6_ Net-_U11-Pad7_ Net-_U11-Pad8_ Net-_U11-Pad9_ Net-_U11-Pad10_ adc_bridge_5		
+v7  D GND pulse		
+v8  C GND pulse		
+v9  B GND pulse		
+v10  A GND pulse		
+v11  RST GND pulse		
+U9  Net-_U9-Pad1_ Net-_U9-Pad2_ adc_bridge_1		
+v4  Net-_U9-Pad1_ GND DC		
+U4  W plot_v1		
+U2  X plot_v1		
+U1  Y plot_v1		
+U3  Z plot_v1		
+U7  CLK Net-_U7-Pad2_ adc_bridge_1		
+v2  CLK GND pulse		
+U5  CLK plot_v1		
+U12  RST plot_v1		
+U13  A plot_v1		
+U14  B plot_v1		
+U15  C plot_v1		
+U16  D plot_v1		
+X1  Net-_U6-Pad3_ Net-_U6-Pad4_ Net-_U8-Pad1_ Net-_U8-Pad2_ Net-_U8-Pad3_ Net-_U8-Pad4_ Net-_U7-Pad2_ GND Net-_U10-Pad4_ Net-_U10-Pad3_ Net-_U11-Pad10_ Net-_U11-Pad9_ Net-_U11-Pad8_ Net-_U11-Pad7_ Net-_U11-Pad6_ Net-_U9-Pad2_ MC14076B		
+
+.end
diff --git a/library/SubcircuitLibrary/MC14076B/MC14076B_test.cir.out b/library/SubcircuitLibrary/MC14076B/MC14076B_test.cir.out
new file mode 100644
index 000000000..14aa58df3
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14076B/MC14076B_test.cir.out
@@ -0,0 +1,59 @@
+* c:\users\pavithra\esim-workspace\mc14076b_test\mc14076b_test.cir
+
+.include MC14076B.sub
+* u6  net-_u6-pad1_ net-_u6-pad2_ net-_u6-pad3_ net-_u6-pad4_ adc_bridge_2
+v1 net-_u6-pad1_ gnd  dc 0
+v3 net-_u6-pad2_ gnd  dc 0
+* u8  net-_u8-pad1_ net-_u8-pad2_ net-_u8-pad3_ net-_u8-pad4_ w x y z dac_bridge_4
+* u10  net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ net-_u10-pad4_ adc_bridge_2
+v6 net-_u10-pad1_ gnd  dc 0
+v5 net-_u10-pad2_ gnd  dc 0
+* u11  rst a b c d net-_u11-pad6_ net-_u11-pad7_ net-_u11-pad8_ net-_u11-pad9_ net-_u11-pad10_ adc_bridge_5
+v7  d gnd pulse(0 5 50n 0.1n 0.1n 1m 9m)
+v8  c gnd pulse(5 0 50n 0.1n 0.1n 2m 8m)
+v9  b gnd pulse(0 5 50n 0.1n 0.1n 1m 9m)
+v10  a gnd pulse(5 80n 2m 0.1n 0.1n 2m 8m)
+v11  rst gnd pulse(0 5 0 0.1n 0.1n 4m 9m)
+* u9  net-_u9-pad1_ net-_u9-pad2_ adc_bridge_1
+v4 net-_u9-pad1_ gnd  dc 9
+* u4  w plot_v1
+* u2  x plot_v1
+* u1  y plot_v1
+* u3  z plot_v1
+* u7  clk net-_u7-pad2_ adc_bridge_1
+v2  clk gnd pulse(0 5 0 0.1n 0.1n 1m 2m)
+* u5  clk plot_v1
+* u12  rst plot_v1
+* u13  a plot_v1
+* u14  b plot_v1
+* u15  c plot_v1
+* u16  d plot_v1
+x1 net-_u6-pad3_ net-_u6-pad4_ net-_u8-pad1_ net-_u8-pad2_ net-_u8-pad3_ net-_u8-pad4_ net-_u7-pad2_ gnd net-_u10-pad4_ net-_u10-pad3_ net-_u11-pad10_ net-_u11-pad9_ net-_u11-pad8_ net-_u11-pad7_ net-_u11-pad6_ net-_u9-pad2_ MC14076B
+a1 [net-_u6-pad1_ net-_u6-pad2_ ] [net-_u6-pad3_ net-_u6-pad4_ ] u6
+a2 [net-_u8-pad1_ net-_u8-pad2_ net-_u8-pad3_ net-_u8-pad4_ ] [w x y z ] u8
+a3 [net-_u10-pad1_ net-_u10-pad2_ ] [net-_u10-pad3_ net-_u10-pad4_ ] u10
+a4 [rst a b c d ] [net-_u11-pad6_ net-_u11-pad7_ net-_u11-pad8_ net-_u11-pad9_ net-_u11-pad10_ ] u11
+a5 [net-_u9-pad1_ ] [net-_u9-pad2_ ] u9
+a6 [clk ] [net-_u7-pad2_ ] u7
+* Schematic Name:                             adc_bridge_2, NgSpice Name: adc_bridge
+.model u6 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_4, NgSpice Name: dac_bridge
+.model u8 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_2, NgSpice Name: adc_bridge
+.model u10 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_5, NgSpice Name: adc_bridge
+.model u11 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u9 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u7 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+.tran 1e-06 10e-03 0e-03
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(w)+10v(x)+20 v(y)+30 v(z)+40v(clk)+50 v(rst)+60 v(a)+70 v(b)+80v(c)+90v(d)
+.endc
+.end
diff --git a/library/SubcircuitLibrary/MC14076B/MC14076B_test.pro b/library/SubcircuitLibrary/MC14076B/MC14076B_test.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14076B/MC14076B_test.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/MC14076B/MC14076B_test.proj b/library/SubcircuitLibrary/MC14076B/MC14076B_test.proj
new file mode 100644
index 000000000..78243dfc0
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14076B/MC14076B_test.proj
@@ -0,0 +1 @@
+schematicFile MC14076B_test.sch
diff --git a/library/SubcircuitLibrary/MC14076B/MC14076B_test.sch b/library/SubcircuitLibrary/MC14076B/MC14076B_test.sch
new file mode 100644
index 000000000..f70383c66
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14076B/MC14076B_test.sch
@@ -0,0 +1,732 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:MC14076B_test-cache
+EELAYER 25 0
+EELAYER END
+$Descr A1 33110 23386
+encoding utf-8
+Sheet 1 1
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+F 1 "eSim_GND" H 10150 5250 50  0000 C CNN
+F 2 "" H 10150 5400 50  0001 C CNN
+F 3 "" H 10150 5400 50  0001 C CNN
+	1    10150 5400
+	1    0    0    -1  
+$EndComp
+$Comp
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+P 10400 5350
+F 0 "#PWR09" H 10400 5100 50  0001 C CNN
+F 1 "eSim_GND" H 10400 5200 50  0000 C CNN
+F 2 "" H 10400 5350 50  0001 C CNN
+F 3 "" H 10400 5350 50  0001 C CNN
+	1    10400 5350
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_GND #PWR010
+U 1 1 68554F49
+P 10700 5200
+F 0 "#PWR010" H 10700 4950 50  0001 C CNN
+F 1 "eSim_GND" H 10700 5050 50  0000 C CNN
+F 2 "" H 10700 5200 50  0001 C CNN
+F 3 "" H 10700 5200 50  0001 C CNN
+	1    10700 5200
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+$Comp
+L adc_bridge_1 U9
+U 1 1 68555813
+P 8300 3750
+F 0 "U9" H 8300 3750 60  0000 C CNN
+F 1 "adc_bridge_1" H 8300 3900 60  0000 C CNN
+F 2 "" H 8300 3750 60  0000 C CNN
+F 3 "" H 8300 3750 60  0000 C CNN
+	1    8300 3750
+	-1   0    0    -1  
+$EndComp
+Wire Wire Line
+	7650 3700 7750 3700
+$Comp
+L DC v4
+U 1 1 6855589C
+P 9050 3250
+F 0 "v4" H 8850 3350 60  0000 C CNN
+F 1 "DC" H 8850 3200 60  0000 C CNN
+F 2 "R1" H 8750 3250 60  0000 C CNN
+F 3 "" H 9050 3250 60  0000 C CNN
+	1    9050 3250
+	1    0    0    1   
+$EndComp
+Wire Wire Line
+	8900 3700 9050 3700
+$Comp
+L eSim_GND #PWR011
+U 1 1 6855597A
+P 9200 2800
+F 0 "#PWR011" H 9200 2550 50  0001 C CNN
+F 1 "eSim_GND" H 9200 2650 50  0000 C CNN
+F 2 "" H 9200 2800 50  0001 C CNN
+F 3 "" H 9200 2800 50  0001 C CNN
+	1    9200 2800
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	9050 2800 9200 2800
+$Comp
+L plot_v1 U4
+U 1 1 685559EB
+P 4900 4450
+F 0 "U4" H 4900 4950 60  0000 C CNN
+F 1 "plot_v1" H 5100 4800 60  0000 C CNN
+F 2 "" H 4900 4450 60  0000 C CNN
+F 3 "" H 4900 4450 60  0000 C CNN
+	1    4900 4450
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4900 4250 5100 4250
+$Comp
+L plot_v1 U2
+U 1 1 68555A8F
+P 4700 4500
+F 0 "U2" H 4700 5000 60  0000 C CNN
+F 1 "plot_v1" H 4900 4850 60  0000 C CNN
+F 2 "" H 4700 4500 60  0000 C CNN
+F 3 "" H 4700 4500 60  0000 C CNN
+	1    4700 4500
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4700 4300 4700 4350
+Wire Wire Line
+	4700 4350 5100 4350
+$Comp
+L plot_v1 U1
+U 1 1 68555B2D
+P 4550 4700
+F 0 "U1" H 4550 5200 60  0000 C CNN
+F 1 "plot_v1" H 4750 5050 60  0000 C CNN
+F 2 "" H 4550 4700 60  0000 C CNN
+F 3 "" H 4550 4700 60  0000 C CNN
+	1    4550 4700
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4550 4500 5000 4500
+Wire Wire Line
+	5000 4500 5000 4450
+Wire Wire Line
+	5000 4450 5100 4450
+$Comp
+L plot_v1 U3
+U 1 1 68555BD0
+P 4700 5150
+F 0 "U3" H 4700 5650 60  0000 C CNN
+F 1 "plot_v1" H 4900 5500 60  0000 C CNN
+F 2 "" H 4700 5150 60  0000 C CNN
+F 3 "" H 4700 5150 60  0000 C CNN
+	1    4700 5150
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4700 4950 5100 4950
+Wire Wire Line
+	5100 4950 5100 4550
+$Comp
+L adc_bridge_1 U7
+U 1 1 68555C75
+P 5100 5400
+F 0 "U7" H 5100 5400 60  0000 C CNN
+F 1 "adc_bridge_1" H 5100 5550 60  0000 C CNN
+F 2 "" H 5100 5400 60  0000 C CNN
+F 3 "" H 5100 5400 60  0000 C CNN
+	1    5100 5400
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5650 5350 5650 4850
+Wire Wire Line
+	5650 4850 6350 4850
+$Comp
+L pulse v2
+U 1 1 68555D3A
+P 4150 5800
+F 0 "v2" H 3950 5900 60  0000 C CNN
+F 1 "pulse" H 3950 5750 60  0000 C CNN
+F 2 "R1" H 3850 5800 60  0000 C CNN
+F 3 "" H 4150 5800 60  0000 C CNN
+	1    4150 5800
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4150 5350 4500 5350
+$Comp
+L eSim_GND #PWR012
+U 1 1 68556377
+P 4150 6400
+F 0 "#PWR012" H 4150 6150 50  0001 C CNN
+F 1 "eSim_GND" H 4150 6250 50  0000 C CNN
+F 2 "" H 4150 6400 50  0001 C CNN
+F 3 "" H 4150 6400 50  0001 C CNN
+	1    4150 6400
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4150 6250 4150 6400
+$Comp
+L plot_v1 U5
+U 1 1 68556446
+P 4900 6200
+F 0 "U5" H 4900 6700 60  0000 C CNN
+F 1 "plot_v1" H 5100 6550 60  0000 C CNN
+F 2 "" H 4900 6200 60  0000 C CNN
+F 3 "" H 4900 6200 60  0000 C CNN
+	1    4900 6200
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4400 5350 4400 6000
+Wire Wire Line
+	4400 6000 4900 6000
+Connection ~ 4400 5350
+$Comp
+L plot_v1 U12
+U 1 1 68558D65
+P 9500 4100
+F 0 "U12" H 9500 4600 60  0000 C CNN
+F 1 "plot_v1" H 9700 4450 60  0000 C CNN
+F 2 "" H 9500 4100 60  0000 C CNN
+F 3 "" H 9500 4100 60  0000 C CNN
+	1    9500 4100
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
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+Connection ~ 9500 4150
+$Comp
+L plot_v1 U13
+U 1 1 685592FA
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+F 0 "U13" H 9850 4600 60  0000 C CNN
+F 1 "plot_v1" H 10050 4450 60  0000 C CNN
+F 2 "" H 9850 4100 60  0000 C CNN
+F 3 "" H 9850 4100 60  0000 C CNN
+	1    9850 4100
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
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+Connection ~ 9850 4250
+$Comp
+L plot_v1 U14
+U 1 1 685593DD
+P 10250 4100
+F 0 "U14" H 10250 4600 60  0000 C CNN
+F 1 "plot_v1" H 10450 4450 60  0000 C CNN
+F 2 "" H 10250 4100 60  0000 C CNN
+F 3 "" H 10250 4100 60  0000 C CNN
+	1    10250 4100
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	10250 3900 10250 4200
+Wire Wire Line
+	10250 4200 10000 4200
+Wire Wire Line
+	10000 4200 10000 4350
+Connection ~ 10000 4350
+$Comp
+L plot_v1 U15
+U 1 1 685594B5
+P 11150 4550
+F 0 "U15" H 11150 5050 60  0000 C CNN
+F 1 "plot_v1" H 11350 4900 60  0000 C CNN
+F 2 "" H 11150 4550 60  0000 C CNN
+F 3 "" H 11150 4550 60  0000 C CNN
+	1    11150 4550
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
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+Wire Wire Line
+	9650 4400 11150 4400
+Wire Wire Line
+	11150 4400 11150 4350
+Connection ~ 9650 4450
+$Comp
+L plot_v1 U16
+U 1 1 68559599
+P 10000 6600
+F 0 "U16" H 10000 7100 60  0000 C CNN
+F 1 "plot_v1" H 10200 6950 60  0000 C CNN
+F 2 "" H 10000 6600 60  0000 C CNN
+F 3 "" H 10000 6600 60  0000 C CNN
+	1    10000 6600
+	1    0    0    -1  
+$EndComp
+Text GLabel 9400 3950 0    60   Input ~ 0
+RST
+Wire Wire Line
+	9400 3950 9500 3950
+Connection ~ 9500 3950
+Text GLabel 9800 4050 0    60   Input ~ 0
+A
+Wire Wire Line
+	9800 4050 9850 4050
+Connection ~ 9850 4050
+Text GLabel 10200 4000 0    60   Input ~ 0
+B
+Wire Wire Line
+	10200 4000 10250 4000
+Connection ~ 10250 4000
+Text GLabel 10950 4250 0    60   Input ~ 0
+C
+Wire Wire Line
+	10950 4250 10950 4400
+Connection ~ 10950 4400
+Text GLabel 9900 6500 0    60   Input ~ 0
+D
+Text GLabel 5150 4000 0    60   Input ~ 0
+W
+Wire Wire Line
+	5150 4000 5150 4200
+Wire Wire Line
+	5150 4200 5050 4200
+Wire Wire Line
+	5050 4200 5050 4250
+Connection ~ 5050 4250
+Text GLabel 4850 4250 0    60   Input ~ 0
+X
+Wire Wire Line
+	4850 4250 4850 4350
+Connection ~ 4850 4350
+Text GLabel 4450 4600 0    60   Input ~ 0
+Y
+Wire Wire Line
+	4450 4600 4600 4600
+Wire Wire Line
+	4600 4600 4600 4500
+Connection ~ 4600 4500
+Text GLabel 4700 5100 0    60   Input ~ 0
+Z
+Wire Wire Line
+	4700 5100 4800 5100
+Wire Wire Line
+	4800 5100 4800 4950
+Connection ~ 4800 4950
+Text GLabel 4600 6150 0    60   Input ~ 0
+CLK
+Wire Wire Line
+	4600 6150 4650 6150
+Wire Wire Line
+	4650 6150 4650 6000
+Connection ~ 4650 6000
+Wire Wire Line
+	9600 5800 9600 5950
+Wire Wire Line
+	9150 5900 9150 6050
+$Comp
+L eSim_GND #PWR013
+U 1 1 6855893A
+P 9800 7350
+F 0 "#PWR013" H 9800 7100 50  0001 C CNN
+F 1 "eSim_GND" H 9800 7200 50  0000 C CNN
+F 2 "" H 9800 7350 50  0001 C CNN
+F 3 "" H 9800 7350 50  0001 C CNN
+	1    9800 7350
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	9800 7200 9800 7350
+Wire Wire Line
+	9150 4550 9400 4550
+Wire Wire Line
+	9400 4550 9400 6400
+Wire Wire Line
+	9400 7300 9700 7300
+Wire Wire Line
+	9700 7300 9700 7200
+Wire Wire Line
+	9700 7200 9800 7200
+Wire Wire Line
+	9400 6300 9700 6300
+Wire Wire Line
+	9700 6300 9700 6400
+Wire Wire Line
+	9700 6400 10000 6400
+Connection ~ 9400 6300
+Wire Wire Line
+	9900 6500 9900 6400
+Connection ~ 9900 6400
+$Comp
+L MC14076B X?
+U 1 1 6855C3A2
+P 7000 4350
+F 0 "X?" H 7000 3400 60  0000 C CNN
+F 1 "MC14076B" H 7050 5200 60  0000 C CNN
+F 2 "" H 7000 4350 60  0001 C CNN
+F 3 "" H 7000 4350 60  0001 C CNN
+	1    7000 4350
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/MC14076B/MC14076B_test_Previous_Values.xml b/library/SubcircuitLibrary/MC14076B/MC14076B_test_Previous_Values.xml
new file mode 100644
index 000000000..ee95fe450
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14076B/MC14076B_test_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source><v1 name="Source type">dc<field1 name="Value">0</field1></v1><v3 name="Source type">dc<field1 name="Value">0</field1></v3><v6 name="Source type">dc<field1 name="Value">0</field1></v6><v5 name="Source type">dc<field1 name="Value">0</field1></v5><v7 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">50n</field3><field4 name="Rise Time">0.1n</field4><field5 name="Fall Time">0.1n</field5><field5 name="Pulse width">1m</field5><field5 name="Period">9m</field5></v7><v8 name="Source type">pulse<field1 name="Initial Value">5</field1><field2 name="Pulse Value">0</field2><field3 name="Delay Time">50n</field3><field4 name="Rise Time">0.1n</field4><field5 name="Fall Time">0.1n</field5><field5 name="Pulse width">2m</field5><field5 name="Period">8m</field5></v8><v9 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">50n</field3><field4 name="Rise Time">0.1n</field4><field5 name="Fall Time">0.1n</field5><field5 name="Pulse width">1m</field5><field5 name="Period">9m</field5></v9><v10 name="Source type">pulse<field1 name="Initial Value">5</field1><field2 name="Pulse Value">80n</field2><field3 name="Delay Time">2m</field3><field4 name="Rise Time">0.1n</field4><field5 name="Fall Time">0.1n</field5><field5 name="Pulse width">2m</field5><field5 name="Period">8m</field5></v10><v11 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">0.1n</field4><field5 name="Fall Time">0.1n</field5><field5 name="Pulse width">4m</field5><field5 name="Period">9m</field5></v11><v4 name="Source type">dc<field1 name="Value">9</field1></v4><v2 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">0.1n</field4><field5 name="Fall Time">0.1n</field5><field5 name="Pulse width">1m</field5><field5 name="Period">2m</field5></v2></source><model><u6 name="type">adc_bridge<field1 name="Enter value for in_low (default=1.0)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter Fall Delay (default=1.0e-9)" /></u6><u8 name="type">dac_bridge<field5 name="Enter value for out_low (default=0.0)" /><field6 name="Enter value for out_high (default=5.0)" /><field7 name="Enter value for out_undef (default=0.5)" /><field8 name="Enter value for input load (default=1.0e-12)" /><field9 name="Enter the Rise Time (default=1.0e-9)" /><field10 name="Enter the Fall Time (default=1.0e-9)" /></u8><u10 name="type">adc_bridge<field11 name="Enter value for in_low (default=1.0)" /><field12 name="Enter value for in_high (default=2.0)" /><field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /></u10><u11 name="type">adc_bridge<field15 name="Enter value for in_low (default=1.0)" /><field16 name="Enter value for in_high (default=2.0)" /><field17 name="Enter Rise Delay (default=1.0e-9)" /><field18 name="Enter Fall Delay (default=1.0e-9)" /></u11><u9 name="type">adc_bridge<field19 name="Enter value for in_low (default=1.0)" /><field20 name="Enter value for in_high (default=2.0)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /><field22 name="Enter Fall Delay (default=1.0e-9)" /></u9><u7 name="type">adc_bridge<field23 name="Enter value for in_low (default=1.0)" /><field24 name="Enter value for in_high (default=2.0)" /><field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /></u7></model><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\MC14076B</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">1</field2><field3 name="Stop Time">10</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">us</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14076B/analysis b/library/SubcircuitLibrary/MC14076B/analysis
new file mode 100644
index 000000000..b21a9e13b
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14076B/analysis
@@ -0,0 +1 @@
+.tran 1e-06 10e-03 0e-03
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC3340/D.lib b/library/SubcircuitLibrary/MC3340/D.lib
new file mode 100644
index 000000000..f53bf3e03
--- /dev/null
+++ b/library/SubcircuitLibrary/MC3340/D.lib
@@ -0,0 +1,2 @@
+.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04)
+
diff --git a/library/SubcircuitLibrary/MC3340/MC3340-cache.lib b/library/SubcircuitLibrary/MC3340/MC3340-cache.lib
new file mode 100644
index 000000000..6615a3fcb
--- /dev/null
+++ b/library/SubcircuitLibrary/MC3340/MC3340-cache.lib
@@ -0,0 +1,120 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_Diode
+#
+DEF eSim_Diode D 0 40 N N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "eSim_Diode" 0 -100 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ TO-???*
+ *SingleDiode
+ *_Diode_*
+ *SingleDiode*
+ D_*
+$ENDFPLIST
+DRAW
+T 0 -100 50 60 0 0 0 A Normal 0 C C
+T 0 100 50 60 0 0 0 K Normal 0 C C
+P 2 0 1 6 50 50 50 -50 N
+P 3 0 1 0 -50 50 50 0 -50 -50 F
+X A 1 -150 0 100 R 40 40 1 1 P
+X K 2 150 0 100 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_GND
+#
+DEF eSim_GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "eSim_GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/MC3340/MC3340.cir b/library/SubcircuitLibrary/MC3340/MC3340.cir
new file mode 100644
index 000000000..04864799d
--- /dev/null
+++ b/library/SubcircuitLibrary/MC3340/MC3340.cir
@@ -0,0 +1,40 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\MC3340\MC3340.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/05/25 17:24:07
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+R1  Net-_Q1-Pad1_ Net-_Q1-Pad2_ 5.1K		
+R2  Net-_Q1-Pad2_ GND 4.7K		
+Q1  Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN		
+R3  Net-_Q1-Pad3_ Net-_Q2-Pad2_ 750		
+R4  Net-_Q2-Pad2_ GND 10K		
+Q2  Net-_Q1-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN		
+R6  Net-_Q1-Pad3_ Net-_Q3-Pad2_ 750		
+R7  Net-_Q3-Pad2_ Net-_R7-Pad2_ 3.9K		
+Q3  Net-_Q1-Pad1_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN		
+R8  Net-_Q1-Pad1_ Net-_R5-Pad2_ 5.1K		
+Q4  Net-_Q1-Pad1_ Net-_Q3-Pad3_ Net-_Q4-Pad3_ eSim_NPN		
+Q6  Net-_Q10-Pad2_ Net-_Q2-Pad3_ Net-_Q4-Pad3_ eSim_NPN		
+Q7  Net-_Q1-Pad1_ Net-_Q2-Pad3_ Net-_Q7-Pad3_ eSim_NPN		
+Q9  Net-_Q9-Pad1_ Net-_Q3-Pad3_ Net-_Q7-Pad3_ eSim_NPN		
+R13  Net-_Q1-Pad1_ Net-_Q9-Pad1_ 6.2k		
+Q10  Net-_Q1-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN		
+R15  Net-_Q10-Pad3_ GND 5.1k		
+R16  Net-_Q1-Pad1_ Net-_D1-Pad1_ 5.1k		
+R11  Net-_Q2-Pad3_ GND 5.1k		
+R14  Net-_Q3-Pad3_ GND 5.1k		
+R18  Net-_R18-Pad1_ Net-_Q10-Pad3_ 200		
+D1  Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode		
+R17  Net-_D1-Pad2_ GND 510		
+Q8  Net-_Q7-Pad3_ Net-_D1-Pad1_ Net-_Q8-Pad3_ eSim_NPN		
+R12  Net-_Q8-Pad3_ GND 1.5k		
+Q5  Net-_Q4-Pad3_ Net-_Q5-Pad2_ Net-_Q5-Pad3_ eSim_NPN		
+R10  Net-_Q5-Pad3_ GND 1.3k		
+R5  Net-_Q5-Pad2_ Net-_R5-Pad2_ 20K		
+R9  Net-_R5-Pad2_ GND 510		
+U1  Net-_Q5-Pad2_ Net-_R7-Pad2_ ? ? ? Net-_Q10-Pad2_ Net-_R18-Pad1_ Net-_Q1-Pad1_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/MC3340/MC3340.cir.out b/library/SubcircuitLibrary/MC3340/MC3340.cir.out
new file mode 100644
index 000000000..aaddad9d0
--- /dev/null
+++ b/library/SubcircuitLibrary/MC3340/MC3340.cir.out
@@ -0,0 +1,43 @@
+* c:\fossee\esim\library\subcircuitlibrary\mc3340\mc3340.cir
+
+.include D.lib
+.include NPN.lib
+r1  net-_q1-pad1_ net-_q1-pad2_ 5.1k
+r2  net-_q1-pad2_ gnd 4.7k
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222
+r3  net-_q1-pad3_ net-_q2-pad2_ 750
+r4  net-_q2-pad2_ gnd 10k
+q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222
+r6  net-_q1-pad3_ net-_q3-pad2_ 750
+r7  net-_q3-pad2_ net-_r7-pad2_ 3.9k
+q3 net-_q1-pad1_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222
+r8  net-_q1-pad1_ net-_r5-pad2_ 5.1k
+q4 net-_q1-pad1_ net-_q3-pad3_ net-_q4-pad3_ Q2N2222
+q6 net-_q10-pad2_ net-_q2-pad3_ net-_q4-pad3_ Q2N2222
+q7 net-_q1-pad1_ net-_q2-pad3_ net-_q7-pad3_ Q2N2222
+q9 net-_q9-pad1_ net-_q3-pad3_ net-_q7-pad3_ Q2N2222
+r13  net-_q1-pad1_ net-_q9-pad1_ 6.2k
+q10 net-_q1-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222
+r15  net-_q10-pad3_ gnd 5.1k
+r16  net-_q1-pad1_ net-_d1-pad1_ 5.1k
+r11  net-_q2-pad3_ gnd 5.1k
+r14  net-_q3-pad3_ gnd 5.1k
+r18  net-_r18-pad1_ net-_q10-pad3_ 200
+d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148
+r17  net-_d1-pad2_ gnd 510
+q8 net-_q7-pad3_ net-_d1-pad1_ net-_q8-pad3_ Q2N2222
+r12  net-_q8-pad3_ gnd 1.5k
+q5 net-_q4-pad3_ net-_q5-pad2_ net-_q5-pad3_ Q2N2222
+r10  net-_q5-pad3_ gnd 1.3k
+r5  net-_q5-pad2_ net-_r5-pad2_ 20k
+r9  net-_r5-pad2_ gnd 510
+* u1  net-_q5-pad2_ net-_r7-pad2_ ? ? ? net-_q10-pad2_ net-_r18-pad1_ net-_q1-pad1_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/MC3340/MC3340.pro b/library/SubcircuitLibrary/MC3340/MC3340.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/MC3340/MC3340.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/MC3340/MC3340.proj b/library/SubcircuitLibrary/MC3340/MC3340.proj
new file mode 100644
index 000000000..8ac98f15e
--- /dev/null
+++ b/library/SubcircuitLibrary/MC3340/MC3340.proj
@@ -0,0 +1 @@
+schematicFile MC3340.sch
diff --git a/library/SubcircuitLibrary/MC3340/MC3340.sch b/library/SubcircuitLibrary/MC3340/MC3340.sch
new file mode 100644
index 000000000..9a72dc614
--- /dev/null
+++ b/library/SubcircuitLibrary/MC3340/MC3340.sch
@@ -0,0 +1,715 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
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+U 1 1 6840219C
+P 1900 1850
+F 0 "R1" H 1950 1980 50  0000 C CNN
+F 1 "5.1K" H 1950 1800 50  0000 C CNN
+F 2 "" H 1950 1830 30  0000 C CNN
+F 3 "" V 1950 1900 30  0000 C CNN
+	1    1900 1850
+	0    1    1    0   
+$EndComp
+$Comp
+L resistor R2
+U 1 1 684022BB
+P 1900 2400
+F 0 "R2" H 1950 2530 50  0000 C CNN
+F 1 "4.7K" H 1950 2350 50  0000 C CNN
+F 2 "" H 1950 2380 30  0000 C CNN
+F 3 "" V 1950 2450 30  0000 C CNN
+	1    1900 2400
+	0    1    1    0   
+$EndComp
+$Comp
+L eSim_NPN Q1
+U 1 1 684022DD
+P 2500 2200
+F 0 "Q1" H 2400 2250 50  0000 R CNN
+F 1 "eSim_NPN" H 2450 2350 50  0000 R CNN
+F 2 "" H 2700 2300 29  0000 C CNN
+F 3 "" H 2500 2200 60  0000 C CNN
+	1    2500 2200
+	1    0    0    -1  
+$EndComp
+$Comp
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+U 1 1 68402320
+P 2800 2750
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+F 1 "750" H 2850 2700 50  0000 C CNN
+F 2 "" H 2850 2730 30  0000 C CNN
+F 3 "" V 2850 2800 30  0000 C CNN
+	1    2800 2750
+	0    1    1    0   
+$EndComp
+$Comp
+L resistor R4
+U 1 1 68402512
+P 2800 3300
+F 0 "R4" H 2850 3430 50  0000 C CNN
+F 1 "10K" H 2850 3250 50  0000 C CNN
+F 2 "" H 2850 3280 30  0000 C CNN
+F 3 "" V 2850 3350 30  0000 C CNN
+	1    2800 3300
+	0    1    1    0   
+$EndComp
+$Comp
+L eSim_GND #PWR01
+U 1 1 6840255A
+P 1950 2800
+F 0 "#PWR01" H 1950 2550 50  0001 C CNN
+F 1 "eSim_GND" H 1950 2650 50  0000 C CNN
+F 2 "" H 1950 2800 50  0001 C CNN
+F 3 "" H 1950 2800 50  0001 C CNN
+	1    1950 2800
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_GND #PWR02
+U 1 1 684025CC
+P 2850 3650
+F 0 "#PWR02" H 2850 3400 50  0001 C CNN
+F 1 "eSim_GND" H 2850 3500 50  0000 C CNN
+F 2 "" H 2850 3650 50  0001 C CNN
+F 3 "" H 2850 3650 50  0001 C CNN
+	1    2850 3650
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_NPN Q2
+U 1 1 684025F7
+P 3400 3100
+F 0 "Q2" H 3300 3150 50  0000 R CNN
+F 1 "eSim_NPN" H 3350 3250 50  0000 R CNN
+F 2 "" H 3600 3200 29  0000 C CNN
+F 3 "" H 3400 3100 60  0000 C CNN
+	1    3400 3100
+	1    0    0    -1  
+$EndComp
+$Comp
+L resistor R6
+U 1 1 684027FF
+P 3850 2750
+F 0 "R6" H 3900 2880 50  0000 C CNN
+F 1 "750" H 3900 2700 50  0000 C CNN
+F 2 "" H 3900 2730 30  0000 C CNN
+F 3 "" V 3900 2800 30  0000 C CNN
+	1    3850 2750
+	0    1    1    0   
+$EndComp
+$Comp
+L resistor R7
+U 1 1 6840283A
+P 3850 3350
+F 0 "R7" H 3900 3480 50  0000 C CNN
+F 1 "3.9K" H 3900 3300 50  0000 C CNN
+F 2 "" H 3900 3330 30  0000 C CNN
+F 3 "" V 3900 3400 30  0000 C CNN
+	1    3850 3350
+	0    1    1    0   
+$EndComp
+$Comp
+L eSim_NPN Q3
+U 1 1 684028AE
+P 4450 3050
+F 0 "Q3" H 4350 3100 50  0000 R CNN
+F 1 "eSim_NPN" H 4400 3200 50  0000 R CNN
+F 2 "" H 4650 3150 29  0000 C CNN
+F 3 "" H 4450 3050 60  0000 C CNN
+	1    4450 3050
+	1    0    0    -1  
+$EndComp
+$Comp
+L resistor R8
+U 1 1 6840290F
+P 4100 1650
+F 0 "R8" H 4150 1780 50  0000 C CNN
+F 1 "5.1K" H 4150 1600 50  0000 C CNN
+F 2 "" H 4150 1630 30  0000 C CNN
+F 3 "" V 4150 1700 30  0000 C CNN
+	1    4100 1650
+	0    1    1    0   
+$EndComp
+$Comp
+L eSim_NPN Q4
+U 1 1 68402ECE
+P 5000 3350
+F 0 "Q4" H 4900 3400 50  0000 R CNN
+F 1 "eSim_NPN" H 4950 3500 50  0000 R CNN
+F 2 "" H 5200 3450 29  0000 C CNN
+F 3 "" H 5000 3350 60  0000 C CNN
+	1    5000 3350
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_NPN Q6
+U 1 1 68402F17
+P 5650 3350
+F 0 "Q6" H 5550 3400 50  0000 R CNN
+F 1 "eSim_NPN" H 5600 3500 50  0000 R CNN
+F 2 "" H 5850 3450 29  0000 C CNN
+F 3 "" H 5650 3350 60  0000 C CNN
+	1    5650 3350
+	-1   0    0    -1  
+$EndComp
+$Comp
+L eSim_NPN Q7
+U 1 1 68403375
+P 6550 3350
+F 0 "Q7" H 6450 3400 50  0000 R CNN
+F 1 "eSim_NPN" H 6500 3500 50  0000 R CNN
+F 2 "" H 6750 3450 29  0000 C CNN
+F 3 "" H 6550 3350 60  0000 C CNN
+	1    6550 3350
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_NPN Q9
+U 1 1 6840337B
+P 7200 3350
+F 0 "Q9" H 7100 3400 50  0000 R CNN
+F 1 "eSim_NPN" H 7150 3500 50  0000 R CNN
+F 2 "" H 7400 3450 29  0000 C CNN
+F 3 "" H 7200 3350 60  0000 C CNN
+	1    7200 3350
+	-1   0    0    -1  
+$EndComp
+$Comp
+L resistor R13
+U 1 1 68403469
+P 7050 1550
+F 0 "R13" H 7100 1680 50  0000 C CNN
+F 1 "6.2k" H 7100 1500 50  0000 C CNN
+F 2 "" H 7100 1530 30  0000 C CNN
+F 3 "" V 7100 1600 30  0000 C CNN
+	1    7050 1550
+	0    1    1    0   
+$EndComp
+$Comp
+L eSim_NPN Q10
+U 1 1 6840352A
+P 7550 2050
+F 0 "Q10" H 7450 2100 50  0000 R CNN
+F 1 "eSim_NPN" H 7500 2200 50  0000 R CNN
+F 2 "" H 7750 2150 29  0000 C CNN
+F 3 "" H 7550 2050 60  0000 C CNN
+	1    7550 2050
+	1    0    0    -1  
+$EndComp
+$Comp
+L resistor R15
+U 1 1 68403613
+P 7600 2500
+F 0 "R15" H 7650 2630 50  0000 C CNN
+F 1 "5.1k" H 7650 2450 50  0000 C CNN
+F 2 "" H 7650 2480 30  0000 C CNN
+F 3 "" V 7650 2550 30  0000 C CNN
+	1    7600 2500
+	0    1    1    0   
+$EndComp
+$Comp
+L eSim_GND #PWR03
+U 1 1 684036A1
+P 7650 2850
+F 0 "#PWR03" H 7650 2600 50  0001 C CNN
+F 1 "eSim_GND" H 7650 2700 50  0000 C CNN
+F 2 "" H 7650 2850 50  0001 C CNN
+F 3 "" H 7650 2850 50  0001 C CNN
+	1    7650 2850
+	1    0    0    -1  
+$EndComp
+$Comp
+L resistor R16
+U 1 1 6840371B
+P 8000 1600
+F 0 "R16" H 8050 1730 50  0000 C CNN
+F 1 "5.1k" H 8050 1550 50  0000 C CNN
+F 2 "" H 8050 1580 30  0000 C CNN
+F 3 "" V 8050 1650 30  0000 C CNN
+	1    8000 1600
+	0    1    1    0   
+$EndComp
+$Comp
+L resistor R11
+U 1 1 68403A34
+P 6050 3800
+F 0 "R11" H 6100 3930 50  0000 C CNN
+F 1 "5.1k" H 6100 3750 50  0000 C CNN
+F 2 "" H 6100 3780 30  0000 C CNN
+F 3 "" V 6100 3850 30  0000 C CNN
+	1    6050 3800
+	0    1    1    0   
+$EndComp
+$Comp
+L eSim_GND #PWR04
+U 1 1 68403B9A
+P 6100 4200
+F 0 "#PWR04" H 6100 3950 50  0001 C CNN
+F 1 "eSim_GND" H 6100 4050 50  0000 C CNN
+F 2 "" H 6100 4200 50  0001 C CNN
+F 3 "" H 6100 4200 50  0001 C CNN
+	1    6100 4200
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
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+Wire Wire Line
+	2300 2200 1950 2200
+Connection ~ 1950 2200
+Wire Wire Line
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+Wire Wire Line
+	1950 1400 8250 1400
+Wire Wire Line
+	2600 1400 2600 2000
+Wire Wire Line
+	2600 2400 3900 2400
+Wire Wire Line
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+Wire Wire Line
+	2850 2950 2850 3200
+Wire Wire Line
+	1950 2600 1950 2800
+Wire Wire Line
+	2850 3500 2850 3650
+Wire Wire Line
+	3200 3100 2850 3100
+Connection ~ 2850 3100
+Wire Wire Line
+	3500 1400 3500 2900
+Connection ~ 2600 1400
+Wire Wire Line
+	3900 2400 3900 2650
+Connection ~ 2850 2400
+Wire Wire Line
+	3900 2950 3900 3250
+Wire Wire Line
+	4250 3050 3900 3050
+Connection ~ 3900 3050
+Wire Wire Line
+	4150 1400 4150 1550
+Connection ~ 3500 1400
+Wire Wire Line
+	4550 1400 4550 2850
+Connection ~ 4150 1400
+Wire Wire Line
+	4550 3250 4550 3600
+Wire Wire Line
+	4550 3350 4800 3350
+Wire Wire Line
+	5100 1400 5100 3150
+Connection ~ 4550 1400
+Wire Wire Line
+	5100 3550 5550 3550
+Wire Wire Line
+	6650 3550 7100 3550
+Wire Wire Line
+	5850 3350 6350 3350
+Wire Wire Line
+	6650 1400 6650 3150
+Connection ~ 5100 1400
+Wire Wire Line
+	7100 1750 7100 3150
+Wire Wire Line
+	7100 1400 7100 1450
+Connection ~ 6650 1400
+Wire Wire Line
+	5550 3150 5550 2050
+Wire Wire Line
+	5550 2050 7350 2050
+Wire Wire Line
+	7650 1400 7650 1850
+Connection ~ 7100 1400
+Wire Wire Line
+	7650 2250 7650 2400
+Wire Wire Line
+	7650 2700 7650 2850
+Wire Wire Line
+	8050 1400 8050 1500
+Connection ~ 7650 1400
+Wire Wire Line
+	6100 3350 6100 3700
+Connection ~ 6100 3350
+Wire Wire Line
+	6100 4000 6100 4200
+Wire Wire Line
+	3500 3300 3500 3650
+Wire Wire Line
+	3500 3650 6100 3650
+Connection ~ 6100 3650
+$Comp
+L resistor R14
+U 1 1 68403CD1
+P 7450 3800
+F 0 "R14" H 7500 3930 50  0000 C CNN
+F 1 "5.1k" H 7500 3750 50  0000 C CNN
+F 2 "" H 7500 3780 30  0000 C CNN
+F 3 "" V 7500 3850 30  0000 C CNN
+	1    7450 3800
+	0    1    1    0   
+$EndComp
+Wire Wire Line
+	7400 3350 7500 3350
+Wire Wire Line
+	7500 3350 7500 3700
+$Comp
+L eSim_GND #PWR05
+U 1 1 68403D83
+P 7500 4150
+F 0 "#PWR05" H 7500 3900 50  0001 C CNN
+F 1 "eSim_GND" H 7500 4000 50  0000 C CNN
+F 2 "" H 7500 4150 50  0001 C CNN
+F 3 "" H 7500 4150 50  0001 C CNN
+	1    7500 4150
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	7500 4000 7500 4150
+Wire Wire Line
+	4550 3600 7500 3600
+Connection ~ 7500 3600
+Connection ~ 4550 3350
+$Comp
+L resistor R18
+U 1 1 68403E61
+P 8050 2250
+F 0 "R18" H 8100 2380 50  0000 C CNN
+F 1 "200" H 8100 2200 50  0000 C CNN
+F 2 "" H 8100 2230 30  0000 C CNN
+F 3 "" V 8100 2300 30  0000 C CNN
+	1    8050 2250
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	7850 2300 7650 2300
+Connection ~ 7650 2300
+$Comp
+L eSim_Diode D1
+U 1 1 68403F41
+P 8050 4500
+F 0 "D1" H 8050 4600 50  0000 C CNN
+F 1 "eSim_Diode" H 8050 4400 50  0000 C CNN
+F 2 "" H 8050 4500 60  0000 C CNN
+F 3 "" H 8050 4500 60  0000 C CNN
+	1    8050 4500
+	0    1    1    0   
+$EndComp
+$Comp
+L resistor R17
+U 1 1 6840556F
+P 8000 5100
+F 0 "R17" H 8050 5230 50  0000 C CNN
+F 1 "510" H 8050 5050 50  0000 C CNN
+F 2 "" H 8050 5080 30  0000 C CNN
+F 3 "" V 8050 5150 30  0000 C CNN
+	1    8000 5100
+	0    1    1    0   
+$EndComp
+$Comp
+L eSim_GND #PWR06
+U 1 1 68405630
+P 8050 5550
+F 0 "#PWR06" H 8050 5300 50  0001 C CNN
+F 1 "eSim_GND" H 8050 5400 50  0000 C CNN
+F 2 "" H 8050 5550 50  0001 C CNN
+F 3 "" H 8050 5550 50  0001 C CNN
+	1    8050 5550
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_NPN Q8
+U 1 1 684056D5
+P 7000 4650
+F 0 "Q8" H 6900 4700 50  0000 R CNN
+F 1 "eSim_NPN" H 6950 4800 50  0000 R CNN
+F 2 "" H 7200 4750 29  0000 C CNN
+F 3 "" H 7000 4650 60  0000 C CNN
+	1    7000 4650
+	-1   0    0    -1  
+$EndComp
+Wire Wire Line
+	6900 4450 6900 3550
+Connection ~ 6900 3550
+$Comp
+L resistor R12
+U 1 1 68405826
+P 6850 5150
+F 0 "R12" H 6900 5280 50  0000 C CNN
+F 1 "1.5k" H 6900 5100 50  0000 C CNN
+F 2 "" H 6900 5130 30  0000 C CNN
+F 3 "" V 6900 5200 30  0000 C CNN
+	1    6850 5150
+	0    1    1    0   
+$EndComp
+$Comp
+L eSim_GND #PWR07
+U 1 1 68405897
+P 6900 5550
+F 0 "#PWR07" H 6900 5300 50  0001 C CNN
+F 1 "eSim_GND" H 6900 5400 50  0000 C CNN
+F 2 "" H 6900 5550 50  0001 C CNN
+F 3 "" H 6900 5550 50  0001 C CNN
+	1    6900 5550
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	6900 4850 6900 5050
+Wire Wire Line
+	6900 5350 6900 5550
+Wire Wire Line
+	8050 1800 8050 4350
+Wire Wire Line
+	8050 4650 8050 5000
+Wire Wire Line
+	8050 5300 8050 5550
+Wire Wire Line
+	7200 4650 7800 4650
+Wire Wire Line
+	7800 4650 7800 4050
+Wire Wire Line
+	7800 4050 8050 4050
+Connection ~ 8050 4050
+$Comp
+L eSim_NPN Q5
+U 1 1 68407F71
+P 5200 4900
+F 0 "Q5" H 5100 4950 50  0000 R CNN
+F 1 "eSim_NPN" H 5150 5050 50  0000 R CNN
+F 2 "" H 5400 5000 29  0000 C CNN
+F 3 "" H 5200 4900 60  0000 C CNN
+	1    5200 4900
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5300 4700 5300 3550
+Connection ~ 5300 3550
+$Comp
+L resistor R10
+U 1 1 684085F9
+P 5250 5400
+F 0 "R10" H 5300 5530 50  0000 C CNN
+F 1 "1.3k" H 5300 5350 50  0000 C CNN
+F 2 "" H 5300 5380 30  0000 C CNN
+F 3 "" V 5300 5450 30  0000 C CNN
+	1    5250 5400
+	0    1    1    0   
+$EndComp
+$Comp
+L eSim_GND #PWR08
+U 1 1 68408672
+P 5300 5800
+F 0 "#PWR08" H 5300 5550 50  0001 C CNN
+F 1 "eSim_GND" H 5300 5650 50  0000 C CNN
+F 2 "" H 5300 5800 50  0001 C CNN
+F 3 "" H 5300 5800 50  0001 C CNN
+	1    5300 5800
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5300 5600 5300 5800
+Wire Wire Line
+	5300 5100 5300 5300
+$Comp
+L resistor R5
+U 1 1 684087D0
+P 3650 5200
+F 0 "R5" H 3700 5330 50  0000 C CNN
+F 1 "20K" H 3700 5150 50  0000 C CNN
+F 2 "" H 3700 5180 30  0000 C CNN
+F 3 "" V 3700 5250 30  0000 C CNN
+	1    3650 5200
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	3550 5150 3550 4900
+Wire Wire Line
+	3350 4900 5000 4900
+Wire Wire Line
+	4150 1850 4150 5350
+Wire Wire Line
+	4150 5150 3850 5150
+$Comp
+L resistor R9
+U 1 1 6840B887
+P 4100 5450
+F 0 "R9" H 4150 5580 50  0000 C CNN
+F 1 "510" H 4150 5400 50  0000 C CNN
+F 2 "" H 4150 5430 30  0000 C CNN
+F 3 "" V 4150 5500 30  0000 C CNN
+	1    4100 5450
+	0    1    1    0   
+$EndComp
+Connection ~ 4150 5150
+$Comp
+L eSim_GND #PWR09
+U 1 1 6840B990
+P 4150 5800
+F 0 "#PWR09" H 4150 5550 50  0001 C CNN
+F 1 "eSim_GND" H 4150 5650 50  0000 C CNN
+F 2 "" H 4150 5800 50  0001 C CNN
+F 3 "" H 4150 5800 50  0001 C CNN
+	1    4150 5800
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4150 5650 4150 5800
+$Comp
+L PORT U1
+U 1 1 68417B8A
+P 3100 4900
+F 0 "U1" H 3150 5000 30  0000 C CNN
+F 1 "PORT" H 3100 4900 30  0000 C CNN
+F 2 "" H 3100 4900 60  0000 C CNN
+F 3 "" H 3100 4900 60  0000 C CNN
+	1    3100 4900
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 68417C0B
+P 3550 3850
+F 0 "U1" H 3600 3950 30  0000 C CNN
+F 1 "PORT" H 3550 3850 30  0000 C CNN
+F 2 "" H 3550 3850 60  0000 C CNN
+F 3 "" H 3550 3850 60  0000 C CNN
+	2    3550 3850
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 68417CA4
+P 2050 5250
+F 0 "U1" H 2100 5350 30  0000 C CNN
+F 1 "PORT" H 2050 5250 30  0000 C CNN
+F 2 "" H 2050 5250 60  0000 C CNN
+F 3 "" H 2050 5250 60  0000 C CNN
+	3    2050 5250
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 68417D3F
+P 2050 5500
+F 0 "U1" H 2100 5600 30  0000 C CNN
+F 1 "PORT" H 2050 5500 30  0000 C CNN
+F 2 "" H 2050 5500 60  0000 C CNN
+F 3 "" H 2050 5500 60  0000 C CNN
+	4    2050 5500
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 68417E3C
+P 2050 5750
+F 0 "U1" H 2100 5850 30  0000 C CNN
+F 1 "PORT" H 2050 5750 30  0000 C CNN
+F 2 "" H 2050 5750 60  0000 C CNN
+F 3 "" H 2050 5750 60  0000 C CNN
+	5    2050 5750
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 6 1 68417E9B
+P 8550 1900
+F 0 "U1" H 8600 2000 30  0000 C CNN
+F 1 "PORT" H 8550 1900 30  0000 C CNN
+F 2 "" H 8550 1900 60  0000 C CNN
+F 3 "" H 8550 1900 60  0000 C CNN
+	6    8550 1900
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 7 1 68417F12
+P 8550 2300
+F 0 "U1" H 8600 2400 30  0000 C CNN
+F 1 "PORT" H 8550 2300 30  0000 C CNN
+F 2 "" H 8550 2300 60  0000 C CNN
+F 3 "" H 8550 2300 60  0000 C CNN
+	7    8550 2300
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 8 1 68417F7D
+P 8500 1400
+F 0 "U1" H 8550 1500 30  0000 C CNN
+F 1 "PORT" H 8500 1400 30  0000 C CNN
+F 2 "" H 8500 1400 60  0000 C CNN
+F 3 "" H 8500 1400 60  0000 C CNN
+	8    8500 1400
+	-1   0    0    -1  
+$EndComp
+Connection ~ 3550 4900
+Wire Wire Line
+	3900 3550 3900 3850
+Wire Wire Line
+	3900 3850 3800 3850
+NoConn ~ 2300 5250
+NoConn ~ 2300 5500
+NoConn ~ 2300 5750
+Wire Wire Line
+	8300 1900 7200 1900
+Wire Wire Line
+	7200 1900 7200 2050
+Connection ~ 7200 2050
+Connection ~ 8050 1400
+Wire Wire Line
+	8300 2300 8150 2300
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/MC3340/MC3340.sub b/library/SubcircuitLibrary/MC3340/MC3340.sub
new file mode 100644
index 000000000..c36548bf1
--- /dev/null
+++ b/library/SubcircuitLibrary/MC3340/MC3340.sub
@@ -0,0 +1,37 @@
+* Subcircuit MC3340
+.subckt MC3340 net-_q5-pad2_ net-_r7-pad2_ ? ? ? net-_q10-pad2_ net-_r18-pad1_ net-_q1-pad1_ 
+* c:\fossee\esim\library\subcircuitlibrary\mc3340\mc3340.cir
+.include D.lib
+.include NPN.lib
+r1  net-_q1-pad1_ net-_q1-pad2_ 5.1k
+r2  net-_q1-pad2_ gnd 4.7k
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222
+r3  net-_q1-pad3_ net-_q2-pad2_ 750
+r4  net-_q2-pad2_ gnd 10k
+q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222
+r6  net-_q1-pad3_ net-_q3-pad2_ 750
+r7  net-_q3-pad2_ net-_r7-pad2_ 3.9k
+q3 net-_q1-pad1_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222
+r8  net-_q1-pad1_ net-_r5-pad2_ 5.1k
+q4 net-_q1-pad1_ net-_q3-pad3_ net-_q4-pad3_ Q2N2222
+q6 net-_q10-pad2_ net-_q2-pad3_ net-_q4-pad3_ Q2N2222
+q7 net-_q1-pad1_ net-_q2-pad3_ net-_q7-pad3_ Q2N2222
+q9 net-_q9-pad1_ net-_q3-pad3_ net-_q7-pad3_ Q2N2222
+r13  net-_q1-pad1_ net-_q9-pad1_ 6.2k
+q10 net-_q1-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222
+r15  net-_q10-pad3_ gnd 5.1k
+r16  net-_q1-pad1_ net-_d1-pad1_ 5.1k
+r11  net-_q2-pad3_ gnd 5.1k
+r14  net-_q3-pad3_ gnd 5.1k
+r18  net-_r18-pad1_ net-_q10-pad3_ 200
+d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148
+r17  net-_d1-pad2_ gnd 510
+q8 net-_q7-pad3_ net-_d1-pad1_ net-_q8-pad3_ Q2N2222
+r12  net-_q8-pad3_ gnd 1.5k
+q5 net-_q4-pad3_ net-_q5-pad2_ net-_q5-pad3_ Q2N2222
+r10  net-_q5-pad3_ gnd 1.3k
+r5  net-_q5-pad2_ net-_r5-pad2_ 20k
+r9  net-_r5-pad2_ gnd 510
+* Control Statements
+
+.ends MC3340
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC3340/MC3340_Previous_Values.xml b/library/SubcircuitLibrary/MC3340/MC3340_Previous_Values.xml
new file mode 100644
index 000000000..a4a0ecf99
--- /dev/null
+++ b/library/SubcircuitLibrary/MC3340/MC3340_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model /><devicemodel><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><q6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q6><q7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q7><q9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q9><q10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q10><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><q8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q8><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC3340/MC3340_test-cache.lib b/library/SubcircuitLibrary/MC3340/MC3340_test-cache.lib
new file mode 100644
index 000000000..2eee24ecb
--- /dev/null
+++ b/library/SubcircuitLibrary/MC3340/MC3340_test-cache.lib
@@ -0,0 +1,126 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# DC
+#
+DEF DC v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 w
+X - 2 0 -450 300 U 50 50 1 1 w
+ENDDRAW
+ENDDEF
+#
+# MC3340
+#
+DEF MC3340 X 0 40 Y Y 1 F N
+F0 "X" 0 -500 60 H V C CNN
+F1 "MC3340" 0 600 60 H V C CNN
+F2 "" 0 600 60 H I C CNN
+F3 "" 0 600 60 H I C CNN
+DRAW
+P 4 0 1 0 -250 300 -250 -350 500 0 -250 300 N
+X A 1 -450 0 200 R 50 50 1 1 I
+X B 2 -150 -500 200 U 50 50 1 1 I
+X C 3 0 -450 200 U 50 50 1 1 W
+X D 4 150 -350 200 U 50 50 1 1 N
+X E 5 300 -300 200 U 50 50 1 1 N
+X F 6 400 -250 200 U 50 50 1 1 P
+X G 7 700 0 200 L 50 50 1 1 O
+X H 8 50 350 200 D 50 50 1 1 W
+ENDDRAW
+ENDDEF
+#
+# eSim_CP1
+#
+DEF eSim_CP1 C 0 10 N N 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_CP1" 25 -100 50 H V L CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+ALIAS capacitor_polarised
+$FPLIST
+ CP_*
+$ENDFPLIST
+DRAW
+A 0 -150 128 1287 513 0 1 20 N -80 -50 80 -50
+P 2 0 1 20 -80 30 80 30 N
+P 2 0 1 0 -70 90 -30 90 N
+P 2 0 1 0 -50 70 -50 110 N
+X ~ 1 0 150 110 D 50 50 1 1 P
+X ~ 2 0 -150 130 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_GND
+#
+DEF eSim_GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "eSim_GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# sine
+#
+DEF sine v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "sine" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -50 0 50 1 1799 0 1 0 N 0 0 -100 0
+A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 0 1 1 I
+X - 2 0 -450 300 U 50 0 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/MC3340/MC3340_test.cir b/library/SubcircuitLibrary/MC3340/MC3340_test.cir
new file mode 100644
index 000000000..483510fe7
--- /dev/null
+++ b/library/SubcircuitLibrary/MC3340/MC3340_test.cir
@@ -0,0 +1,20 @@
+* C:\Users\pavithra\eSim-Workspace\MC3340_test\MC3340_test.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/05/25 11:08:05
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1  Net-_C1-Pad1_ Net-_C2-Pad1_ GND ? ? Net-_C3-Pad2_ out Net-_X1-Pad8_ MC3340		
+C1  Net-_C1-Pad1_ in 1u		
+v1  in GND sine		
+C2  Net-_C2-Pad1_ GND 50u		
+R1  Net-_C2-Pad1_ GND 50k		
+C3  GND Net-_C3-Pad2_ 620p		
+U1  out plot_v1		
+U2  in plot_v1		
+R2  Net-_C1-Pad1_ GND 100k		
+v2  Net-_X1-Pad8_ GND DC		
+
+.end
diff --git a/library/SubcircuitLibrary/MC3340/MC3340_test.cir.out b/library/SubcircuitLibrary/MC3340/MC3340_test.cir.out
new file mode 100644
index 000000000..37e8ac1a5
--- /dev/null
+++ b/library/SubcircuitLibrary/MC3340/MC3340_test.cir.out
@@ -0,0 +1,24 @@
+* c:\users\pavithra\esim-workspace\mc3340_test\mc3340_test.cir
+
+.include MC3340.sub
+x1 net-_c1-pad1_ net-_c2-pad1_ gnd ? ? net-_c3-pad2_ out net-_x1-pad8_ MC3340
+c1  net-_c1-pad1_ in 1u
+v1  in gnd sine(0 0.4 1000 0 0)
+c2  net-_c2-pad1_ gnd 50u
+r1  net-_c2-pad1_ gnd 50k
+c3  gnd net-_c3-pad2_ 620p
+* u1  out plot_v1
+* u2  in plot_v1
+r2  net-_c1-pad1_ gnd 100k
+v2 net-_x1-pad8_ gnd  dc 12
+.tran 1e-06 10e-03 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(out) 
+plot v(in)
+.endc
+.end
diff --git a/library/SubcircuitLibrary/MC3340/MC3340_test.pro b/library/SubcircuitLibrary/MC3340/MC3340_test.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/MC3340/MC3340_test.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/MC3340/MC3340_test.proj b/library/SubcircuitLibrary/MC3340/MC3340_test.proj
new file mode 100644
index 000000000..05f38fe8e
--- /dev/null
+++ b/library/SubcircuitLibrary/MC3340/MC3340_test.proj
@@ -0,0 +1 @@
+schematicFile MC3340_test.sch
diff --git a/library/SubcircuitLibrary/MC3340/MC3340_test.sch b/library/SubcircuitLibrary/MC3340/MC3340_test.sch
new file mode 100644
index 000000000..b3886f74b
--- /dev/null
+++ b/library/SubcircuitLibrary/MC3340/MC3340_test.sch
@@ -0,0 +1,257 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L MC3340 X1
+U 1 1 684032A2
+P 5400 3300
+F 0 "X1" H 5400 2800 60  0000 C CNN
+F 1 "MC3340" H 5750 3550 60  0000 C CNN
+F 2 "" H 5400 3900 60  0001 C CNN
+F 3 "" H 5400 3900 60  0001 C CNN
+	1    5400 3300
+	1    0    0    -1  
+$EndComp
+$Comp
+L capacitor_polarised C1
+U 1 1 68403397
+P 4400 3300
+F 0 "C1" H 4425 3400 50  0000 L CNN
+F 1 "1u" H 4425 3200 50  0000 L CNN
+F 2 "" H 4400 3300 50  0001 C CNN
+F 3 "" H 4400 3300 50  0001 C CNN
+	1    4400 3300
+	0    1    1    0   
+$EndComp
+$Comp
+L sine v1
+U 1 1 68403533
+P 4250 4100
+F 0 "v1" H 4050 4200 60  0000 C CNN
+F 1 "sine" H 4050 4050 60  0000 C CNN
+F 2 "R1" H 3950 4100 60  0000 C CNN
+F 3 "" H 4250 4100 60  0000 C CNN
+	1    4250 4100
+	1    0    0    -1  
+$EndComp
+$Comp
+L capacitor_polarised C2
+U 1 1 68403666
+P 5050 4250
+F 0 "C2" H 5075 4350 50  0000 L CNN
+F 1 "50u" H 5075 4150 50  0000 L CNN
+F 2 "" H 5050 4250 50  0001 C CNN
+F 3 "" H 5050 4250 50  0001 C CNN
+	1    5050 4250
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_GND #PWR01
+U 1 1 6840394D
+P 5400 4800
+F 0 "#PWR01" H 5400 4550 50  0001 C CNN
+F 1 "eSim_GND" H 5400 4650 50  0000 C CNN
+F 2 "" H 5400 4800 50  0001 C CNN
+F 3 "" H 5400 4800 50  0001 C CNN
+	1    5400 4800
+	1    0    0    -1  
+$EndComp
+$Comp
+L resistor R1
+U 1 1 68403F36
+P 5200 5000
+F 0 "R1" H 5250 5130 50  0000 C CNN
+F 1 "50k" H 5250 4950 50  0000 C CNN
+F 2 "" H 5250 4980 30  0000 C CNN
+F 3 "" V 5250 5050 30  0000 C CNN
+	1    5200 5000
+	0    1    1    0   
+$EndComp
+$Comp
+L eSim_GND #PWR02
+U 1 1 68403FF4
+P 5250 5300
+F 0 "#PWR02" H 5250 5050 50  0001 C CNN
+F 1 "eSim_GND" H 5250 5150 50  0000 C CNN
+F 2 "" H 5250 5300 50  0001 C CNN
+F 3 "" H 5250 5300 50  0001 C CNN
+	1    5250 5300
+	1    0    0    -1  
+$EndComp
+$Comp
+L capacitor_polarised C3
+U 1 1 6840431E
+P 5800 4150
+F 0 "C3" H 5825 4250 50  0000 L CNN
+F 1 "620p" H 5825 4050 50  0000 L CNN
+F 2 "" H 5800 4150 50  0001 C CNN
+F 3 "" H 5800 4150 50  0001 C CNN
+	1    5800 4150
+	1    0    0    1   
+$EndComp
+$Comp
+L plot_v1 U1
+U 1 1 68404541
+P 6250 3350
+F 0 "U1" H 6250 3850 60  0000 C CNN
+F 1 "plot_v1" H 6450 3700 60  0000 C CNN
+F 2 "" H 6250 3350 60  0000 C CNN
+F 3 "" H 6250 3350 60  0000 C CNN
+	1    6250 3350
+	1    0    0    -1  
+$EndComp
+Text GLabel 6450 3250 2    60   Input ~ 0
+out
+$Comp
+L plot_v1 U2
+U 1 1 68404A11
+P 3600 3800
+F 0 "U2" H 3600 4300 60  0000 C CNN
+F 1 "plot_v1" H 3800 4150 60  0000 C CNN
+F 2 "" H 3600 3800 60  0000 C CNN
+F 3 "" H 3600 3800 60  0000 C CNN
+	1    3600 3800
+	1    0    0    -1  
+$EndComp
+Text GLabel 3700 3800 0    60   Input ~ 0
+in
+Wire Wire Line
+	5450 2850 5450 2950
+Wire Wire Line
+	4550 3300 4950 3300
+Wire Wire Line
+	4250 3300 4250 3650
+Wire Wire Line
+	5050 4100 5250 4100
+Wire Wire Line
+	5250 3800 5250 4900
+Wire Wire Line
+	5050 4400 5050 4650
+Wire Wire Line
+	4250 4650 5800 4650
+Wire Wire Line
+	5400 3750 5400 4800
+Connection ~ 5400 4650
+Connection ~ 5250 4100
+Wire Wire Line
+	5250 5200 5250 5300
+Wire Wire Line
+	5800 4000 5800 3550
+Wire Wire Line
+	5800 4650 5800 4300
+Wire Wire Line
+	6250 3300 6100 3300
+Wire Wire Line
+	6250 3150 6250 3300
+Wire Wire Line
+	6250 3250 6450 3250
+Connection ~ 6250 3250
+Wire Wire Line
+	4250 4550 4250 4650
+Connection ~ 5050 4650
+Wire Wire Line
+	3600 3600 4250 3600
+Wire Wire Line
+	4250 3600 4250 3550
+Connection ~ 4250 3550
+Wire Wire Line
+	3700 3800 3850 3800
+Wire Wire Line
+	3850 3800 3850 3600
+Connection ~ 3850 3600
+$Comp
+L resistor R2
+U 1 1 68413101
+P 4650 4000
+F 0 "R2" H 4700 4130 50  0000 C CNN
+F 1 "100k" H 4700 3950 50  0000 C CNN
+F 2 "" H 4700 3980 30  0000 C CNN
+F 3 "" V 4700 4050 30  0000 C CNN
+	1    4650 4000
+	0    1    1    0   
+$EndComp
+Wire Wire Line
+	4700 3900 4700 3300
+Wire Wire Line
+	4700 3300 4750 3300
+Connection ~ 4750 3300
+Wire Wire Line
+	4700 4200 4700 4650
+Connection ~ 4700 4650
+$Comp
+L DC v2
+U 1 1 6841325C
+P 5450 2400
+F 0 "v2" H 5250 2500 60  0000 C CNN
+F 1 "DC" H 5250 2350 60  0000 C CNN
+F 2 "R1" H 5150 2400 60  0000 C CNN
+F 3 "" H 5450 2400 60  0000 C CNN
+	1    5450 2400
+	1    0    0    1   
+$EndComp
+$Comp
+L eSim_GND #PWR03
+U 1 1 6841330C
+P 5700 1950
+F 0 "#PWR03" H 5700 1700 50  0001 C CNN
+F 1 "eSim_GND" H 5700 1800 50  0000 C CNN
+F 2 "" H 5700 1950 50  0001 C CNN
+F 3 "" H 5700 1950 50  0001 C CNN
+	1    5700 1950
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5450 1950 5700 1950
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/MC3340/MC3340_test_Previous_Values.xml b/library/SubcircuitLibrary/MC3340/MC3340_test_Previous_Values.xml
new file mode 100644
index 000000000..825ffca38
--- /dev/null
+++ b/library/SubcircuitLibrary/MC3340/MC3340_test_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source><v1 name="Source type">sine<field1 name="Offset Value">0</field1><field2 name="Amplitude">0.4</field2><field3 name="Frequency">1000</field3><field4 name="Delay Time">0</field4><field5 name="Damping Factor">0</field5></v1><v2 name="Source type">dc<field1 name="Value">12</field1></v2></source><model /><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\MC3340</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">1</field2><field3 name="Stop Time">10</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">us</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC3340/NPN.lib b/library/SubcircuitLibrary/MC3340/NPN.lib
new file mode 100644
index 000000000..be5f3073a
--- /dev/null
+++ b/library/SubcircuitLibrary/MC3340/NPN.lib
@@ -0,0 +1,4 @@
+.model Q2N2222  NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 
++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p 
++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p 
++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10)
diff --git a/library/SubcircuitLibrary/MC3340/analysis b/library/SubcircuitLibrary/MC3340/analysis
new file mode 100644
index 000000000..4ccdff53b
--- /dev/null
+++ b/library/SubcircuitLibrary/MC3340/analysis
@@ -0,0 +1 @@
+.tran 1e-06 10e-03 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74LVC1G3157/NMOS-5um.lib b/library/SubcircuitLibrary/SN74LVC1G3157/NMOS-5um.lib
new file mode 100644
index 000000000..a237e1fe3
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G3157/NMOS-5um.lib
@@ -0,0 +1,5 @@
+* 5um technology
+
+.model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7 
++ Level=1
++ Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n  )
diff --git a/library/SubcircuitLibrary/SN74LVC1G3157/PMOS-5um.lib b/library/SubcircuitLibrary/SN74LVC1G3157/PMOS-5um.lib
new file mode 100644
index 000000000..9c3ed9760
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G3157/PMOS-5um.lib
@@ -0,0 +1,5 @@
+*5um technology
+
+.model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65
++ Level=1
++ Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n  )
diff --git a/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157-cache.lib b/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157-cache.lib
new file mode 100644
index 000000000..3b7d214a1
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157-cache.lib
@@ -0,0 +1,128 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_1
+#
+DEF dac_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_N
+#
+DEF eSim_MOS_N M 0 0 Y N 1 F N
+F0 "M" 0 -150 50 H V R CNN
+F1 "eSim_MOS_N" 100 -50 50 H V R CNN
+F2 "" 300 -300 29 H V C CNN
+F3 "" 100 -200 60 H V C CNN
+ALIAS mosfet_n
+DRAW
+C 150 -200 111 0 1 10 N
+P 2 0 1 10 130 -290 130 -250 N
+P 2 0 1 0 130 -270 200 -270 N
+P 2 0 1 10 130 -220 130 -180 N
+P 2 0 1 0 130 -200 200 -200 N
+P 2 0 1 10 130 -150 130 -110 N
+P 2 0 1 0 130 -130 200 -130 N
+P 2 0 1 0 200 -300 200 -270 N
+P 2 0 1 0 200 -130 200 -100 N
+P 3 0 1 10 110 -275 110 -125 110 -125 N
+P 3 0 1 0 200 -200 300 -200 300 -250 N
+P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F
+X D 1 200 0 100 D 50 50 1 1 P
+X G 2 -100 -200 210 R 50 50 1 1 P
+X S 3 200 -400 100 U 50 50 1 1 P
+X B 4 300 -350 98 U 47 47 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_P
+#
+DEF eSim_MOS_P M 0 0 Y N 1 F N
+F0 "M" -50 50 50 H V R CNN
+F1 "eSim_MOS_P" 50 150 50 H V R CNN
+F2 "" 250 100 29 H V C CNN
+F3 "" 50 0 60 H V C CNN
+ALIAS mosfet_p
+DRAW
+C 100 0 111 0 1 10 N
+P 2 0 1 0 80 -70 150 -70 N
+P 2 0 1 10 80 -50 80 -90 N
+P 2 0 1 0 80 0 150 0 N
+P 2 0 1 10 80 20 80 -20 N
+P 2 0 1 0 80 70 150 70 N
+P 2 0 1 10 80 90 80 50 N
+P 2 0 1 0 150 -70 150 -100 N
+P 2 0 1 0 150 100 150 70 N
+P 3 0 1 10 60 75 60 -75 60 -75 N
+P 3 0 1 0 150 0 250 0 250 -50 N
+P 4 0 1 0 140 0 100 -15 100 15 140 0 F
+X D 1 150 200 100 D 50 50 1 1 P
+X G 2 -150 0 210 R 50 50 1 1 P
+X S 3 150 -200 100 U 50 50 1 1 P
+X B 4 250 -150 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157.cir b/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157.cir
new file mode 100644
index 000000000..85fc047cf
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157.cir
@@ -0,0 +1,20 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN74LVC1G3157\SN74LVC1G3157.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/04/25 13:13:46
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ d_inverter		
+U2  Net-_U1-Pad2_ Net-_U2-Pad2_ d_inverter		
+U5  Net-_U2-Pad2_ Net-_M2-Pad2_ dac_bridge_1		
+M1  Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad4_ eSim_MOS_P		
+M3  Net-_M1-Pad1_ Net-_M2-Pad2_ Net-_M1-Pad3_ Net-_M3-Pad4_ eSim_MOS_N		
+M2  Net-_M1-Pad1_ Net-_M2-Pad2_ Net-_M2-Pad3_ Net-_M1-Pad4_ eSim_MOS_P		
+M4  Net-_M1-Pad1_ Net-_M4-Pad2_ Net-_M2-Pad3_ Net-_M3-Pad4_ eSim_MOS_N		
+U4  Net-_U1-Pad2_ Net-_M4-Pad2_ dac_bridge_1		
+U3  Net-_U1-Pad2_ Net-_M1-Pad2_ dac_bridge_1		
+U6  Net-_M1-Pad3_ Net-_M3-Pad4_ Net-_M2-Pad3_ Net-_M1-Pad1_ Net-_M1-Pad4_ Net-_U1-Pad1_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157.cir.out b/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157.cir.out
new file mode 100644
index 000000000..f29415042
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157.cir.out
@@ -0,0 +1,38 @@
+* c:\fossee\esim\library\subcircuitlibrary\sn74lvc1g3157\sn74lvc1g3157.cir
+
+.include NMOS-5um.lib
+.include PMOS-5um.lib
+* u1  net-_u1-pad1_ net-_u1-pad2_ d_inverter
+* u2  net-_u1-pad2_ net-_u2-pad2_ d_inverter
+* u5  net-_u2-pad2_ net-_m2-pad2_ dac_bridge_1
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad4_ mos_p W=100u L=100u M=1
+m3 net-_m1-pad1_ net-_m2-pad2_ net-_m1-pad3_ net-_m3-pad4_ mos_n W=100u L=100u M=1
+m2 net-_m1-pad1_ net-_m2-pad2_ net-_m2-pad3_ net-_m1-pad4_ mos_p W=100u L=100u M=1
+m4 net-_m1-pad1_ net-_m4-pad2_ net-_m2-pad3_ net-_m3-pad4_ mos_n W=100u L=100u M=1
+* u4  net-_u1-pad2_ net-_m4-pad2_ dac_bridge_1
+* u3  net-_u1-pad2_ net-_m1-pad2_ dac_bridge_1
+* u6  net-_m1-pad3_ net-_m3-pad4_ net-_m2-pad3_ net-_m1-pad1_ net-_m1-pad4_ net-_u1-pad1_ port
+a1 net-_u1-pad1_ net-_u1-pad2_ u1
+a2 net-_u1-pad2_ net-_u2-pad2_ u2
+a3 [net-_u2-pad2_ ] [net-_m2-pad2_ ] u5
+a4 [net-_u1-pad2_ ] [net-_m4-pad2_ ] u4
+a5 [net-_u1-pad2_ ] [net-_m1-pad2_ ] u3
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u5 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u4 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u3 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157.pro b/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157.proj b/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157.proj
new file mode 100644
index 000000000..14734c208
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157.proj
@@ -0,0 +1 @@
+schematicFile SN74LVC1G3157.sch
diff --git a/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157.sch b/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157.sch
new file mode 100644
index 000000000..40a02c9fc
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157.sch
@@ -0,0 +1,318 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:SN74LVC1G3157-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_inverter U1
+U 1 1 683FDC62
+P 3850 4350
+F 0 "U1" H 3850 4250 60  0000 C CNN
+F 1 "d_inverter" H 3850 4500 60  0000 C CNN
+F 2 "" H 3900 4300 60  0000 C CNN
+F 3 "" H 3900 4300 60  0000 C CNN
+	1    3850 4350
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_inverter U2
+U 1 1 683FDCF4
+P 4750 4350
+F 0 "U2" H 4750 4250 60  0000 C CNN
+F 1 "d_inverter" H 4750 4500 60  0000 C CNN
+F 2 "" H 4800 4300 60  0000 C CNN
+F 3 "" H 4800 4300 60  0000 C CNN
+	1    4750 4350
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4150 4350 4300 4350
+Wire Wire Line
+	4300 4350 4350 4350
+Wire Wire Line
+	4350 4350 4450 4350
+$Comp
+L dac_bridge_1 U5
+U 1 1 683FDDA0
+P 5850 4400
+F 0 "U5" H 5850 4400 60  0000 C CNN
+F 1 "dac_bridge_1" H 5850 4550 60  0000 C CNN
+F 2 "" H 5850 4400 60  0000 C CNN
+F 3 "" H 5850 4400 60  0000 C CNN
+	1    5850 4400
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5050 4350 5250 4350
+$Comp
+L eSim_MOS_P M1
+U 1 1 683FDDD1
+P 7000 3400
+F 0 "M1" H 6950 3450 50  0000 R CNN
+F 1 "eSim_MOS_P" H 7050 3550 50  0000 R CNN
+F 2 "" H 7250 3500 29  0000 C CNN
+F 3 "" H 7050 3400 60  0000 C CNN
+	1    7000 3400
+	0    1    1    0   
+$EndComp
+$Comp
+L eSim_MOS_N M3
+U 1 1 683FDE2F
+P 7200 4100
+F 0 "M3" H 7200 3950 50  0000 R CNN
+F 1 "eSim_MOS_N" H 7300 4050 50  0000 R CNN
+F 2 "" H 7500 3800 29  0000 C CNN
+F 3 "" H 7300 3900 60  0000 C CNN
+	1    7200 4100
+	0    1    -1   0   
+$EndComp
+Wire Wire Line
+	6800 3550 6800 3750
+Wire Wire Line
+	6800 3750 6800 3900
+Wire Wire Line
+	7200 3550 7200 3700
+Wire Wire Line
+	7200 3700 7200 3900
+$Comp
+L eSim_MOS_P M2
+U 1 1 683FDF1C
+P 7000 4700
+F 0 "M2" H 6950 4750 50  0000 R CNN
+F 1 "eSim_MOS_P" H 7050 4850 50  0000 R CNN
+F 2 "" H 7250 4800 29  0000 C CNN
+F 3 "" H 7050 4700 60  0000 C CNN
+	1    7000 4700
+	0    1    1    0   
+$EndComp
+$Comp
+L eSim_MOS_N M4
+U 1 1 683FDF22
+P 7200 5400
+F 0 "M4" H 7200 5250 50  0000 R CNN
+F 1 "eSim_MOS_N" H 7300 5350 50  0000 R CNN
+F 2 "" H 7500 5100 29  0000 C CNN
+F 3 "" H 7300 5200 60  0000 C CNN
+	1    7200 5400
+	0    1    -1   0   
+$EndComp
+Wire Wire Line
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+Wire Wire Line
+	6800 5050 6800 5200
+Wire Wire Line
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+Wire Wire Line
+	7200 5000 7200 5200
+Wire Wire Line
+	7000 4200 7000 4350
+Wire Wire Line
+	7000 4350 7000 4550
+Wire Wire Line
+	6400 4350 7000 4350
+Connection ~ 7000 4350
+$Comp
+L dac_bridge_1 U4
+U 1 1 683FE0BF
+P 5500 5350
+F 0 "U4" H 5500 5350 60  0000 C CNN
+F 1 "dac_bridge_1" H 5500 5500 60  0000 C CNN
+F 2 "" H 5500 5350 60  0000 C CNN
+F 3 "" H 5500 5350 60  0000 C CNN
+	1    5500 5350
+	1    0    0    -1  
+$EndComp
+$Comp
+L dac_bridge_1 U3
+U 1 1 683FE0F7
+P 5500 3400
+F 0 "U3" H 5500 3400 60  0000 C CNN
+F 1 "dac_bridge_1" H 5500 3550 60  0000 C CNN
+F 2 "" H 5500 3400 60  0000 C CNN
+F 3 "" H 5500 3400 60  0000 C CNN
+	1    5500 3400
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4300 4350 4300 3350
+Wire Wire Line
+	4300 3350 4900 3350
+Connection ~ 4300 4350
+Wire Wire Line
+	6050 3350 6900 3350
+Wire Wire Line
+	6900 3350 6900 3250
+Wire Wire Line
+	6900 3250 7000 3250
+Wire Wire Line
+	4350 4350 4350 5300
+Wire Wire Line
+	4350 5300 4900 5300
+Connection ~ 4350 4350
+Wire Wire Line
+	6050 5300 6500 5300
+Wire Wire Line
+	6500 5300 6500 5500
+Wire Wire Line
+	6500 5500 7000 5500
+Wire Wire Line
+	7200 3700 7650 3700
+Wire Wire Line
+	7650 3700 7650 4300
+Wire Wire Line
+	7650 4300 7650 4550
+Wire Wire Line
+	7650 4550 7650 5000
+Wire Wire Line
+	7650 5000 7200 5000
+Connection ~ 7200 5000
+Connection ~ 7200 3700
+$Comp
+L PORT U6
+U 4 1 683FE1B2
+P 8000 4300
+F 0 "U6" H 8050 4400 30  0000 C CNN
+F 1 "PORT" H 8000 4300 30  0000 C CNN
+F 2 "" H 8000 4300 60  0000 C CNN
+F 3 "" H 8000 4300 60  0000 C CNN
+	4    8000 4300
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U6
+U 2 1 683FE61F
+P 7850 5100
+F 0 "U6" H 7900 5200 30  0000 C CNN
+F 1 "PORT" H 7850 5100 30  0000 C CNN
+F 2 "" H 7850 5100 60  0000 C CNN
+F 3 "" H 7850 5100 60  0000 C CNN
+	2    7850 5100
+	-1   0    0    -1  
+$EndComp
+$Comp
+L PORT U6
+U 3 1 683FE668
+P 6400 5050
+F 0 "U6" H 6450 5150 30  0000 C CNN
+F 1 "PORT" H 6400 5050 30  0000 C CNN
+F 2 "" H 6400 5050 60  0000 C CNN
+F 3 "" H 6400 5050 60  0000 C CNN
+	3    6400 5050
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U6
+U 1 1 683FE6AD
+P 6250 3750
+F 0 "U6" H 6300 3850 30  0000 C CNN
+F 1 "PORT" H 6250 3750 30  0000 C CNN
+F 2 "" H 6250 3750 60  0000 C CNN
+F 3 "" H 6250 3750 60  0000 C CNN
+	1    6250 3750
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U6
+U 5 1 683FE6F2
+P 6250 4650
+F 0 "U6" H 6300 4750 30  0000 C CNN
+F 1 "PORT" H 6250 4650 30  0000 C CNN
+F 2 "" H 6250 4650 60  0000 C CNN
+F 3 "" H 6250 4650 60  0000 C CNN
+	5    6250 4650
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U6
+U 6 1 683FE73B
+P 3050 4350
+F 0 "U6" H 3100 4450 30  0000 C CNN
+F 1 "PORT" H 3050 4350 30  0000 C CNN
+F 2 "" H 3050 4350 60  0000 C CNN
+F 3 "" H 3050 4350 60  0000 C CNN
+	6    3050 4350
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	6850 3650 6650 3650
+Wire Wire Line
+	6650 3650 6650 4650
+Wire Wire Line
+	6650 4650 6650 4950
+Wire Wire Line
+	6650 4950 6850 4950
+Wire Wire Line
+	6500 4650 6650 4650
+Connection ~ 6650 4650
+Wire Wire Line
+	6850 3800 7500 3800
+Wire Wire Line
+	7500 3800 7500 5100
+Wire Wire Line
+	6850 5100 7500 5100
+Wire Wire Line
+	7500 5100 7600 5100
+Connection ~ 7500 5100
+Wire Wire Line
+	7750 4300 7650 4300
+Connection ~ 7650 4300
+Wire Wire Line
+	6500 3750 6800 3750
+Connection ~ 6800 3750
+Wire Wire Line
+	6650 5050 6800 5050
+Connection ~ 6800 5050
+Wire Wire Line
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+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157.sub b/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157.sub
new file mode 100644
index 000000000..58166855c
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157.sub
@@ -0,0 +1,32 @@
+* Subcircuit SN74LVC1G3157
+.subckt SN74LVC1G3157 net-_m1-pad3_ net-_m3-pad4_ net-_m2-pad3_ net-_m1-pad1_ net-_m1-pad4_ net-_u1-pad1_ 
+* c:\fossee\esim\library\subcircuitlibrary\sn74lvc1g3157\sn74lvc1g3157.cir
+.include NMOS-5um.lib
+.include PMOS-5um.lib
+* u1  net-_u1-pad1_ net-_u1-pad2_ d_inverter
+* u2  net-_u1-pad2_ net-_u2-pad2_ d_inverter
+* u5  net-_u2-pad2_ net-_m2-pad2_ dac_bridge_1
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad4_ mos_p W=100u L=100u M=1
+m3 net-_m1-pad1_ net-_m2-pad2_ net-_m1-pad3_ net-_m3-pad4_ mos_n W=100u L=100u M=1
+m2 net-_m1-pad1_ net-_m2-pad2_ net-_m2-pad3_ net-_m1-pad4_ mos_p W=100u L=100u M=1
+m4 net-_m1-pad1_ net-_m4-pad2_ net-_m2-pad3_ net-_m3-pad4_ mos_n W=100u L=100u M=1
+* u4  net-_u1-pad2_ net-_m4-pad2_ dac_bridge_1
+* u3  net-_u1-pad2_ net-_m1-pad2_ dac_bridge_1
+a1 net-_u1-pad1_ net-_u1-pad2_ u1
+a2 net-_u1-pad2_ net-_u2-pad2_ u2
+a3 [net-_u2-pad2_ ] [net-_m2-pad2_ ] u5
+a4 [net-_u1-pad2_ ] [net-_m4-pad2_ ] u4
+a5 [net-_u1-pad2_ ] [net-_m1-pad2_ ] u3
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u5 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u4 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
+.model u3 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Control Statements
+
+.ends SN74LVC1G3157
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157_Previous_Values.xml b/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157_Previous_Values.xml
new file mode 100644
index 000000000..46288713c
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u1 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u1><u2 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u2><u5 name="type">dac_bridge<field7 name="Enter value for out_low (default=0.0)" /><field8 name="Enter value for out_high (default=5.0)" /><field9 name="Enter value for out_undef (default=0.5)" /><field10 name="Enter value for input load (default=1.0e-12)" /><field11 name="Enter the Rise Time (default=1.0e-9)" /><field12 name="Enter the Fall Time (default=1.0e-9)" /></u5><u4 name="type">dac_bridge<field13 name="Enter value for out_low (default=0.0)" /><field14 name="Enter value for out_high (default=5.0)" /><field15 name="Enter value for out_undef (default=0.5)" /><field16 name="Enter value for input load (default=1.0e-12)" /><field17 name="Enter the Rise Time (default=1.0e-9)" /><field18 name="Enter the Fall Time (default=1.0e-9)" /></u4><u3 name="type">dac_bridge<field19 name="Enter value for out_low (default=0.0)" /><field20 name="Enter value for out_high (default=5.0)" /><field21 name="Enter value for out_undef (default=0.5)" /><field22 name="Enter value for input load (default=1.0e-12)" /><field23 name="Enter the Rise Time (default=1.0e-9)" /><field24 name="Enter the Fall Time (default=1.0e-9)" /></u3></model><devicemodel><m1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib</field><field /><field /><field /></m1><m3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib</field><field /><field /><field /></m3><m2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib</field><field /><field /><field /></m2><m4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib</field><field /><field /><field /></m4></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74LVC1G3157/SN74VC1G3157_test-cache.lib b/library/SubcircuitLibrary/SN74LVC1G3157/SN74VC1G3157_test-cache.lib
new file mode 100644
index 000000000..c99ca626e
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G3157/SN74VC1G3157_test-cache.lib
@@ -0,0 +1,117 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# DC
+#
+DEF DC v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 w
+X - 2 0 -450 300 U 50 50 1 1 w
+ENDDRAW
+ENDDEF
+#
+# SN74LVC1G3157
+#
+DEF SN74LVC1G3157 X 0 40 Y Y 1 F N
+F0 "X" 0 -600 60 H V C CNN
+F1 "SN74LVC1G3157" 50 650 60 H V C CNN
+F2 "" 0 -600 60 H I C CNN
+F3 "" 0 -600 60 H I C CNN
+DRAW
+S -400 500 400 -450 0 1 0 N
+S 400 -350 400 -350 0 1 0 N
+X B2 1 -600 300 200 R 50 50 1 1 I
+X Gnd 2 -600 0 200 R 50 50 1 1 I
+X B1 3 -600 -250 200 R 50 50 1 1 I
+X A 4 600 -300 200 L 50 50 1 1 O
+X Vcc 5 600 0 200 L 50 50 1 1 I
+X S 6 600 300 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_1
+#
+DEF adc_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_GND
+#
+DEF eSim_GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "eSim_GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# eSim_VCC
+#
+DEF eSim_VCC #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -150 50 H I C CNN
+F1 "eSim_VCC" 0 150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+C 0 75 25 0 1 0 N
+P 2 0 1 0 0 0 0 50 N
+X VCC 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# pulse
+#
+DEF pulse v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "pulse" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -25 -450 501 928 871 0 1 0 N -50 50 0 50
+A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50
+A 75 600 551 -926 -873 0 1 0 N 50 50 100 50
+A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50
+A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50
+A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74LVC1G3157/SN74VC1G3157_test.cir b/library/SubcircuitLibrary/SN74LVC1G3157/SN74VC1G3157_test.cir
new file mode 100644
index 000000000..35ab3cbc8
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G3157/SN74VC1G3157_test.cir
@@ -0,0 +1,17 @@
+* C:\Users\pavithra\eSim-Workspace\SN74VC1G3157_test\SN74VC1G3157_test.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/04/25 13:14:27
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+v1  Net-_X1-Pad3_ GND DC		
+v2  Net-_X1-Pad1_ GND DC		
+U2  S Net-_U2-Pad2_ adc_bridge_1		
+v3  S GND pulse		
+U3  Out plot_v1		
+U1  S plot_v1		
+X1  Net-_X1-Pad1_ GND Net-_X1-Pad3_ Out VCC Net-_U2-Pad2_ SN74LVC1G3157		
+
+.end
diff --git a/library/SubcircuitLibrary/SN74LVC1G3157/SN74VC1G3157_test.cir.out b/library/SubcircuitLibrary/SN74LVC1G3157/SN74VC1G3157_test.cir.out
new file mode 100644
index 000000000..d025cccff
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G3157/SN74VC1G3157_test.cir.out
@@ -0,0 +1,24 @@
+* c:\users\pavithra\esim-workspace\sn74vc1g3157_test\sn74vc1g3157_test.cir
+
+.include SN74LVC1G3157.sub
+v1 net-_x1-pad3_ gnd  dc 1
+v2 net-_x1-pad1_ gnd  dc 3
+* u2  s net-_u2-pad2_ adc_bridge_1
+v3  s gnd pulse(5 0 0 0.5n 0.5n 1m 2m)
+* u3  out plot_v1
+* u1  s plot_v1
+x1 net-_x1-pad1_ gnd net-_x1-pad3_ out vcc net-_u2-pad2_ SN74LVC1G3157
+a1 [s ] [net-_u2-pad2_ ] u2
+* Schematic Name:                             adc_bridge_1, NgSpice Name: adc_bridge
+.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+.tran 10e-06 10e-03 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+ 
+plot v(s) + 6 v(out)
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74LVC1G3157/SN74VC1G3157_test.pro b/library/SubcircuitLibrary/SN74LVC1G3157/SN74VC1G3157_test.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G3157/SN74VC1G3157_test.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74LVC1G3157/SN74VC1G3157_test.proj b/library/SubcircuitLibrary/SN74LVC1G3157/SN74VC1G3157_test.proj
new file mode 100644
index 000000000..1d4fe58e3
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G3157/SN74VC1G3157_test.proj
@@ -0,0 +1 @@
+schematicFile SN74VC1G3157_test.sch
diff --git a/library/SubcircuitLibrary/SN74LVC1G3157/SN74VC1G3157_test.sch b/library/SubcircuitLibrary/SN74LVC1G3157/SN74VC1G3157_test.sch
new file mode 100644
index 000000000..ad5a8b942
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G3157/SN74VC1G3157_test.sch
@@ -0,0 +1,230 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:SN74VC1G3157_test-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L eSim_GND #PWR01
+U 1 1 683FE1D3
+P 4950 3550
+F 0 "#PWR01" H 4950 3300 50  0001 C CNN
+F 1 "eSim_GND" H 4950 3400 50  0000 C CNN
+F 2 "" H 4950 3550 50  0001 C CNN
+F 3 "" H 4950 3550 50  0001 C CNN
+	1    4950 3550
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4950 3550 5100 3550
+$Comp
+L eSim_VCC #PWR02
+U 1 1 683FE1EC
+P 6450 3500
+F 0 "#PWR02" H 6450 3350 50  0001 C CNN
+F 1 "eSim_VCC" H 6450 3650 50  0000 C CNN
+F 2 "" H 6450 3500 50  0001 C CNN
+F 3 "" H 6450 3500 50  0001 C CNN
+	1    6450 3500
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	6450 3500 6450 3550
+Wire Wire Line
+	6450 3550 6300 3550
+$Comp
+L DC v1
+U 1 1 683FE208
+P 5000 4300
+F 0 "v1" H 4800 4400 60  0000 C CNN
+F 1 "DC" H 4800 4250 60  0000 C CNN
+F 2 "R1" H 4700 4300 60  0000 C CNN
+F 3 "" H 5000 4300 60  0000 C CNN
+	1    5000 4300
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4550 3250 5100 3250
+$Comp
+L eSim_GND #PWR03
+U 1 1 683FE254
+P 4550 4250
+F 0 "#PWR03" H 4550 4000 50  0001 C CNN
+F 1 "eSim_GND" H 4550 4100 50  0000 C CNN
+F 2 "" H 4550 4250 50  0001 C CNN
+F 3 "" H 4550 4250 50  0001 C CNN
+	1    4550 4250
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4550 4150 4550 4250
+$Comp
+L DC v2
+U 1 1 683FE26D
+P 4550 3700
+F 0 "v2" H 4350 3800 60  0000 C CNN
+F 1 "DC" H 4350 3650 60  0000 C CNN
+F 2 "R1" H 4250 3700 60  0000 C CNN
+F 3 "" H 4550 3700 60  0000 C CNN
+	1    4550 3700
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5000 3850 5000 3800
+Wire Wire Line
+	5000 3800 5100 3800
+$Comp
+L eSim_GND #PWR04
+U 1 1 683FE32A
+P 5000 4900
+F 0 "#PWR04" H 5000 4650 50  0001 C CNN
+F 1 "eSim_GND" H 5000 4750 50  0000 C CNN
+F 2 "" H 5000 4900 50  0001 C CNN
+F 3 "" H 5000 4900 50  0001 C CNN
+	1    5000 4900
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5000 4750 5000 4900
+$Comp
+L adc_bridge_1 U2
+U 1 1 683FE349
+P 7300 3300
+F 0 "U2" H 7300 3300 60  0000 C CNN
+F 1 "adc_bridge_1" H 7300 3450 60  0000 C CNN
+F 2 "" H 7300 3300 60  0000 C CNN
+F 3 "" H 7300 3300 60  0000 C CNN
+	1    7300 3300
+	-1   0    0    -1  
+$EndComp
+Wire Wire Line
+	6750 3250 6300 3250
+$Comp
+L pulse v3
+U 1 1 683FE3A5
+P 8150 3700
+F 0 "v3" H 7950 3800 60  0000 C CNN
+F 1 "pulse" H 7950 3650 60  0000 C CNN
+F 2 "R1" H 7850 3700 60  0000 C CNN
+F 3 "" H 8150 3700 60  0000 C CNN
+	1    8150 3700
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	7900 3250 8150 3250
+$Comp
+L eSim_GND #PWR05
+U 1 1 683FE58E
+P 8150 4300
+F 0 "#PWR05" H 8150 4050 50  0001 C CNN
+F 1 "eSim_GND" H 8150 4150 50  0000 C CNN
+F 2 "" H 8150 4300 50  0001 C CNN
+F 3 "" H 8150 4300 50  0001 C CNN
+	1    8150 4300
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	8150 4150 8150 4300
+$Comp
+L plot_v1 U3
+U 1 1 683FE5B6
+P 6700 4000
+F 0 "U3" H 6700 4500 60  0000 C CNN
+F 1 "plot_v1" H 6900 4350 60  0000 C CNN
+F 2 "" H 6700 4000 60  0000 C CNN
+F 3 "" H 6700 4000 60  0000 C CNN
+	1    6700 4000
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	6300 3850 6700 3850
+Text GLabel 6600 4000 2    60   Input ~ 0
+Out
+Wire Wire Line
+	6700 3850 6700 3800
+Wire Wire Line
+	6600 4000 6500 4000
+Wire Wire Line
+	6500 4000 6500 3850
+Connection ~ 6500 3850
+$Comp
+L plot_v1 U1
+U 1 1 683FE9E3
+P 8000 3300
+F 0 "U1" H 8000 3800 60  0000 C CNN
+F 1 "plot_v1" H 8200 3650 60  0000 C CNN
+F 2 "" H 8000 3300 60  0000 C CNN
+F 3 "" H 8000 3300 60  0000 C CNN
+	1    8000 3300
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	8000 3100 8000 3250
+Connection ~ 8000 3250
+Text GLabel 8150 3150 2    60   Input ~ 0
+S
+Wire Wire Line
+	8150 3150 8000 3150
+Connection ~ 8000 3150
+$Comp
+L SN74LVC1G3157 X1
+U 1 1 683FFB48
+P 5700 3550
+F 0 "X1" H 5700 2950 60  0000 C CNN
+F 1 "SN74LVC1G3157" H 5750 4200 60  0000 C CNN
+F 2 "" H 5700 2950 60  0001 C CNN
+F 3 "" H 5700 2950 60  0001 C CNN
+	1    5700 3550
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74LVC1G3157/SN74VC1G3157_test_Previous_Values.xml b/library/SubcircuitLibrary/SN74LVC1G3157/SN74VC1G3157_test_Previous_Values.xml
new file mode 100644
index 000000000..a07854b8e
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G3157/SN74VC1G3157_test_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source><v1 name="Source type">dc<field1 name="Value">1</field1></v1><v2 name="Source type">dc<field1 name="Value">3</field1></v2><v3 name="Source type">pulse<field1 name="Initial Value">5</field1><field2 name="Pulse Value">0</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">0.5n</field4><field5 name="Fall Time">0.5n</field5><field5 name="Pulse width">1m</field5><field5 name="Period">2m</field5></v3></source><model><u2 name="type">adc_bridge<field1 name="Enter value for in_low (default=1.0)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter Fall Delay (default=1.0e-9)" /></u2><u1 name="type">dac_bridge<field5 name="Enter value for out_low (default=0.0)" /><field6 name="Enter value for out_high (default=5.0)" /><field7 name="Enter value for out_undef (default=0.5)" /><field8 name="Enter value for input load (default=1.0e-12)" /><field9 name="Enter the Rise Time (default=1.0e-9)" /><field10 name="Enter the Fall Time (default=1.0e-9)" /></u1></model><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\SN74LVC1G3157</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">10</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">us</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74LVC1G3157/analysis b/library/SubcircuitLibrary/SN74LVC1G3157/analysis
new file mode 100644
index 000000000..f4bb3b56f
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G3157/analysis
@@ -0,0 +1 @@
+.tran 10e-06 10e-03 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/TA7642/NPN.lib b/library/SubcircuitLibrary/TA7642/NPN.lib
new file mode 100644
index 000000000..be5f3073a
--- /dev/null
+++ b/library/SubcircuitLibrary/TA7642/NPN.lib
@@ -0,0 +1,4 @@
+.model Q2N2222  NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 
++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p 
++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p 
++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10)
diff --git a/library/SubcircuitLibrary/TA7642/TA7642-cache.lib b/library/SubcircuitLibrary/TA7642/TA7642-cache.lib
new file mode 100644
index 000000000..d94d000cf
--- /dev/null
+++ b/library/SubcircuitLibrary/TA7642/TA7642-cache.lib
@@ -0,0 +1,102 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_C
+#
+DEF eSim_C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_C" 25 -100 50 H V L CNN
+F2 "" 38 -150 30 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS capacitor
+$FPLIST
+ C_*
+$ENDFPLIST
+DRAW
+P 2 0 1 20 -80 -30 80 -30 N
+P 2 0 1 20 -80 30 80 30 N
+X ~ 1 0 150 110 D 40 40 1 1 P
+X ~ 2 0 -150 110 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/TA7642/TA7642.cir b/library/SubcircuitLibrary/TA7642/TA7642.cir
new file mode 100644
index 000000000..9cec887be
--- /dev/null
+++ b/library/SubcircuitLibrary/TA7642/TA7642.cir
@@ -0,0 +1,40 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\TA7642\TA7642.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/03/25 11:57:32
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+Q1  Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_C1-Pad2_ eSim_NPN		
+Q2  Net-_C1-Pad2_ Net-_Q2-Pad2_ Net-_Q10-Pad3_ eSim_NPN		
+C1  Net-_C1-Pad1_ Net-_C1-Pad2_ 12p		
+R2  Net-_C1-Pad1_ Net-_Q4-Pad2_ 3.3k		
+R3  Net-_Q1-Pad1_ Net-_Q3-Pad1_ 12k		
+R4  Net-_Q3-Pad1_ Net-_Q4-Pad2_ 12k		
+Q3  Net-_Q3-Pad1_ Net-_Q2-Pad2_ Net-_Q10-Pad3_ eSim_NPN		
+R1  Net-_Q3-Pad1_ Net-_Q2-Pad2_ 5.6k		
+R5  Net-_Q1-Pad1_ Net-_C2-Pad2_ 12k		
+Q4  Net-_C2-Pad2_ Net-_Q4-Pad2_ Net-_Q10-Pad3_ eSim_NPN		
+C2  Net-_C2-Pad1_ Net-_C2-Pad2_ 12p		
+R6  Net-_Q1-Pad1_ Net-_C3-Pad2_ 12k		
+Q5  Net-_C3-Pad2_ Net-_C2-Pad1_ Net-_Q10-Pad3_ eSim_NPN		
+R9  Net-_Q1-Pad1_ Net-_Q6-Pad1_ 12k		
+R7  Net-_C2-Pad1_ Net-_Q6-Pad1_ 12k		
+Q6  Net-_Q6-Pad1_ Net-_Q6-Pad2_ Net-_Q10-Pad3_ eSim_NPN		
+R8  Net-_Q6-Pad1_ Net-_Q6-Pad2_ 12k		
+R10  Net-_Q6-Pad1_ Net-_C3-Pad1_ 12k		
+C3  Net-_C3-Pad1_ Net-_C3-Pad2_ 12p		
+R11  Net-_Q1-Pad1_ Net-_C4-Pad2_ 12k		
+Q7  Net-_C4-Pad2_ Net-_C3-Pad1_ Net-_Q10-Pad3_ eSim_NPN		
+R13  Net-_Q1-Pad1_ Net-_Q8-Pad1_ 12k		
+Q8  Net-_Q8-Pad1_ Net-_Q8-Pad2_ Net-_Q10-Pad3_ eSim_NPN		
+R12  Net-_Q8-Pad1_ Net-_Q8-Pad2_ 12k		
+C4  Net-_C4-Pad1_ Net-_C4-Pad2_ 23p		
+R14  Net-_Q8-Pad1_ Net-_C4-Pad1_ 74k		
+R15  Net-_Q1-Pad1_ Net-_Q10-Pad2_ 12k		
+Q9  Net-_Q10-Pad2_ Net-_C4-Pad1_ Net-_Q10-Pad3_ eSim_NPN		
+Q10  Net-_Q1-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN		
+U1  Net-_Q10-Pad3_ Net-_Q1-Pad2_ Net-_Q1-Pad1_ PORT		
+
+.end
diff --git a/library/SubcircuitLibrary/TA7642/TA7642.cir.out b/library/SubcircuitLibrary/TA7642/TA7642.cir.out
new file mode 100644
index 000000000..f595bee1c
--- /dev/null
+++ b/library/SubcircuitLibrary/TA7642/TA7642.cir.out
@@ -0,0 +1,42 @@
+* c:\fossee\esim\library\subcircuitlibrary\ta7642\ta7642.cir
+
+.include NPN.lib
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_c1-pad2_ Q2N2222
+q2 net-_c1-pad2_ net-_q2-pad2_ net-_q10-pad3_ Q2N2222
+c1  net-_c1-pad1_ net-_c1-pad2_ 12p
+r2  net-_c1-pad1_ net-_q4-pad2_ 3.3k
+r3  net-_q1-pad1_ net-_q3-pad1_ 12k
+r4  net-_q3-pad1_ net-_q4-pad2_ 12k
+q3 net-_q3-pad1_ net-_q2-pad2_ net-_q10-pad3_ Q2N2222
+r1  net-_q3-pad1_ net-_q2-pad2_ 5.6k
+r5  net-_q1-pad1_ net-_c2-pad2_ 12k
+q4 net-_c2-pad2_ net-_q4-pad2_ net-_q10-pad3_ Q2N2222
+c2  net-_c2-pad1_ net-_c2-pad2_ 12p
+r6  net-_q1-pad1_ net-_c3-pad2_ 12k
+q5 net-_c3-pad2_ net-_c2-pad1_ net-_q10-pad3_ Q2N2222
+r9  net-_q1-pad1_ net-_q6-pad1_ 12k
+r7  net-_c2-pad1_ net-_q6-pad1_ 12k
+q6 net-_q6-pad1_ net-_q6-pad2_ net-_q10-pad3_ Q2N2222
+r8  net-_q6-pad1_ net-_q6-pad2_ 12k
+r10  net-_q6-pad1_ net-_c3-pad1_ 12k
+c3  net-_c3-pad1_ net-_c3-pad2_ 12p
+r11  net-_q1-pad1_ net-_c4-pad2_ 12k
+q7 net-_c4-pad2_ net-_c3-pad1_ net-_q10-pad3_ Q2N2222
+r13  net-_q1-pad1_ net-_q8-pad1_ 12k
+q8 net-_q8-pad1_ net-_q8-pad2_ net-_q10-pad3_ Q2N2222
+r12  net-_q8-pad1_ net-_q8-pad2_ 12k
+c4  net-_c4-pad1_ net-_c4-pad2_ 23p
+r14  net-_q8-pad1_ net-_c4-pad1_ 74k
+r15  net-_q1-pad1_ net-_q10-pad2_ 12k
+q9 net-_q10-pad2_ net-_c4-pad1_ net-_q10-pad3_ Q2N2222
+q10 net-_q1-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222
+* u1  net-_q10-pad3_ net-_q1-pad2_ net-_q1-pad1_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/TA7642/TA7642.pro b/library/SubcircuitLibrary/TA7642/TA7642.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/TA7642/TA7642.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/TA7642/TA7642.proj b/library/SubcircuitLibrary/TA7642/TA7642.proj
new file mode 100644
index 000000000..ce13e5ae8
--- /dev/null
+++ b/library/SubcircuitLibrary/TA7642/TA7642.proj
@@ -0,0 +1 @@
+schematicFile TA7642.sch
diff --git a/library/SubcircuitLibrary/TA7642/TA7642.sch b/library/SubcircuitLibrary/TA7642/TA7642.sch
new file mode 100644
index 000000000..5d1b25184
--- /dev/null
+++ b/library/SubcircuitLibrary/TA7642/TA7642.sch
@@ -0,0 +1,553 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:TA7642-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L eSim_NPN Q?
+U 1 1 683E8F68
+P 1950 4400
+F 0 "Q?" H 1850 4450 50  0000 R CNN
+F 1 "eSim_NPN" H 1900 4550 50  0000 R CNN
+F 2 "" H 2150 4500 29  0000 C CNN
+F 3 "" H 1950 4400 60  0000 C CNN
+	1    1950 4400
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_NPN Q?
+U 1 1 683E8F97
+P 2150 5600
+F 0 "Q?" H 2050 5650 50  0000 R CNN
+F 1 "eSim_NPN" H 2100 5750 50  0000 R CNN
+F 2 "" H 2350 5700 29  0000 C CNN
+F 3 "" H 2150 5600 60  0000 C CNN
+	1    2150 5600
+	-1   0    0    -1  
+$EndComp
+$Comp
+L capacitor C?
+U 1 1 683E8FD6
+P 2350 4800
+F 0 "C?" H 2375 4900 50  0000 L CNN
+F 1 "12p" H 2375 4700 50  0000 L CNN
+F 2 "" H 2388 4650 30  0000 C CNN
+F 3 "" H 2350 4800 60  0000 C CNN
+	1    2350 4800
+	0    1    1    0   
+$EndComp
+$Comp
+L resistor R?
+U 1 1 683E9008
+P 2800 4850
+F 0 "R?" H 2850 4980 50  0000 C CNN
+F 1 "3.3k" H 2850 4800 50  0000 C CNN
+F 2 "" H 2850 4830 30  0000 C CNN
+F 3 "" V 2850 4900 30  0000 C CNN
+	1    2800 4850
+	1    0    0    -1  
+$EndComp
+$Comp
+L resistor R?
+U 1 1 683E903F
+P 2950 3750
+F 0 "R?" H 3000 3880 50  0000 C CNN
+F 1 "12k" H 3000 3700 50  0000 C CNN
+F 2 "" H 3000 3730 30  0000 C CNN
+F 3 "" V 3000 3800 30  0000 C CNN
+	1    2950 3750
+	0    1    1    0   
+$EndComp
+$Comp
+L resistor R?
+U 1 1 683E908F
+P 2950 4250
+F 0 "R?" H 3000 4380 50  0000 C CNN
+F 1 "12k" H 3000 4200 50  0000 C CNN
+F 2 "" H 3000 4230 30  0000 C CNN
+F 3 "" V 3000 4300 30  0000 C CNN
+	1    2950 4250
+	0    1    1    0   
+$EndComp
+$Comp
+L eSim_NPN Q?
+U 1 1 683E92CD
+P 2600 5600
+F 0 "Q?" H 2500 5650 50  0000 R CNN
+F 1 "eSim_NPN" H 2550 5400 50  0000 R CNN
+F 2 "" H 2800 5700 29  0000 C CNN
+F 3 "" H 2600 5600 60  0000 C CNN
+	1    2600 5600
+	1    0    0    -1  
+$EndComp
+$Comp
+L resistor R?
+U 1 1 683E946E
+P 2350 5250
+F 0 "R?" H 2400 5380 50  0000 C CNN
+F 1 "5.6k" H 2400 5200 50  0000 C CNN
+F 2 "" H 2400 5230 30  0000 C CNN
+F 3 "" V 2400 5300 30  0000 C CNN
+	1    2350 5250
+	0    1    1    0   
+$EndComp
+$Comp
+L resistor R?
+U 1 1 683E9744
+P 3300 4150
+F 0 "R?" H 3350 4280 50  0000 C CNN
+F 1 "12k" H 3350 4100 50  0000 C CNN
+F 2 "" H 3350 4130 30  0000 C CNN
+F 3 "" V 3350 4200 30  0000 C CNN
+	1    3300 4150
+	0    1    1    0   
+$EndComp
+$Comp
+L eSim_NPN Q?
+U 1 1 683E979C
+P 3250 4800
+F 0 "Q?" H 3150 4850 50  0000 R CNN
+F 1 "eSim_NPN" H 3200 4950 50  0000 R CNN
+F 2 "" H 3450 4900 29  0000 C CNN
+F 3 "" H 3250 4800 60  0000 C CNN
+	1    3250 4800
+	1    0    0    -1  
+$EndComp
+$Comp
+L capacitor C?
+U 1 1 683E9F5A
+P 3750 4450
+F 0 "C?" H 3775 4550 50  0000 L CNN
+F 1 "12p" H 3775 4350 50  0000 L CNN
+F 2 "" H 3788 4300 30  0000 C CNN
+F 3 "" H 3750 4450 60  0000 C CNN
+	1    3750 4450
+	0    1    1    0   
+$EndComp
+$Comp
+L resistor R?
+U 1 1 683EA32D
+P 4150 4050
+F 0 "R?" H 4200 4180 50  0000 C CNN
+F 1 "12k" H 4200 4000 50  0000 C CNN
+F 2 "" H 4200 4030 30  0000 C CNN
+F 3 "" V 4200 4100 30  0000 C CNN
+	1    4150 4050
+	0    1    1    0   
+$EndComp
+$Comp
+L eSim_NPN Q?
+U 1 1 683EA39C
+P 4100 4850
+F 0 "Q?" H 4000 4900 50  0000 R CNN
+F 1 "eSim_NPN" H 4050 5000 50  0000 R CNN
+F 2 "" H 4300 4950 29  0000 C CNN
+F 3 "" H 4100 4850 60  0000 C CNN
+	1    4100 4850
+	1    0    0    -1  
+$EndComp
+$Comp
+L resistor R?
+U 1 1 683EA79E
+P 4800 4050
+F 0 "R?" H 4850 4180 50  0000 C CNN
+F 1 "12k" H 4850 4000 50  0000 C CNN
+F 2 "" H 4850 4030 30  0000 C CNN
+F 3 "" V 4850 4100 30  0000 C CNN
+	1    4800 4050
+	0    1    1    0   
+$EndComp
+$Comp
+L resistor R?
+U 1 1 683EA821
+P 4450 4500
+F 0 "R?" H 4500 4630 50  0000 C CNN
+F 1 "12k" H 4500 4450 50  0000 C CNN
+F 2 "" H 4500 4480 30  0000 C CNN
+F 3 "" V 4500 4550 30  0000 C CNN
+	1    4450 4500
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_NPN Q?
+U 1 1 683EAA10
+P 4750 5050
+F 0 "Q?" H 4650 5100 50  0000 R CNN
+F 1 "eSim_NPN" H 4700 5200 50  0000 R CNN
+F 2 "" H 4950 5150 29  0000 C CNN
+F 3 "" H 4750 5050 60  0000 C CNN
+	1    4750 5050
+	1    0    0    -1  
+$EndComp
+$Comp
+L resistor R?
+U 1 1 683EABAB
+P 4500 4700
+F 0 "R?" H 4550 4830 50  0000 C CNN
+F 1 "12k" H 4550 4650 50  0000 C CNN
+F 2 "" H 4550 4680 30  0000 C CNN
+F 3 "" V 4550 4750 30  0000 C CNN
+	1    4500 4700
+	0    1    1    0   
+$EndComp
+$Comp
+L resistor R?
+U 1 1 683EAEC8
+P 5100 4500
+F 0 "R?" H 5150 4630 50  0000 C CNN
+F 1 "12k" H 5150 4450 50  0000 C CNN
+F 2 "" H 5150 4480 30  0000 C CNN
+F 3 "" V 5150 4550 30  0000 C CNN
+	1    5100 4500
+	1    0    0    -1  
+$EndComp
+$Comp
+L capacitor C?
+U 1 1 683EAF58
+P 5200 4250
+F 0 "C?" H 5225 4350 50  0000 L CNN
+F 1 "12p" H 5225 4150 50  0000 L CNN
+F 2 "" H 5238 4100 30  0000 C CNN
+F 3 "" H 5200 4250 60  0000 C CNN
+	1    5200 4250
+	0    1    1    0   
+$EndComp
+Wire Wire Line
+	2050 4600 2050 5400
+Wire Wire Line
+	2200 4800 2050 4800
+Connection ~ 2050 4800
+Wire Wire Line
+	2350 5600 2400 5600
+Wire Wire Line
+	2500 4800 2700 4800
+Wire Wire Line
+	3000 3950 3000 4150
+Wire Wire Line
+	2050 4200 2050 3500
+Wire Wire Line
+	2050 3500 7300 3500
+Wire Wire Line
+	3000 3500 3000 3650
+Wire Wire Line
+	2700 4050 2700 5400
+Wire Wire Line
+	2700 4050 3000 4050
+Connection ~ 3000 4050
+Wire Wire Line
+	2400 5600 2400 5450
+Wire Wire Line
+	2400 5150 2400 5100
+Wire Wire Line
+	2400 5100 2700 5100
+Connection ~ 2700 5100
+Wire Wire Line
+	3000 4800 3050 4800
+Wire Wire Line
+	3350 3500 3350 4050
+Connection ~ 3000 3500
+Wire Wire Line
+	3350 4350 3350 4600
+Wire Wire Line
+	2050 5800 7300 5800
+Wire Wire Line
+	3350 5800 3350 5000
+Connection ~ 2700 5800
+Wire Wire Line
+	3000 4450 3000 4800
+Wire Wire Line
+	3600 4450 3350 4450
+Connection ~ 3350 4450
+Wire Wire Line
+	4200 3500 4200 3950
+Connection ~ 3350 3500
+Wire Wire Line
+	4200 4250 4200 4650
+Wire Wire Line
+	3900 4850 3900 4450
+Wire Wire Line
+	4200 5800 4200 5050
+Connection ~ 3350 5800
+Wire Wire Line
+	4850 3500 4850 3950
+Connection ~ 4200 3500
+Wire Wire Line
+	3900 4450 4350 4450
+Wire Wire Line
+	4550 4900 4550 5050
+Wire Wire Line
+	4550 4600 4700 4600
+Wire Wire Line
+	4700 4600 4700 4450
+Wire Wire Line
+	4650 4450 5000 4450
+Connection ~ 4850 4450
+Connection ~ 4700 4450
+Wire Wire Line
+	4850 5800 4850 5250
+Connection ~ 4200 5800
+Wire Wire Line
+	4850 4250 4850 4850
+Wire Wire Line
+	5050 4250 4300 4250
+Wire Wire Line
+	4300 4250 4300 4350
+Wire Wire Line
+	4300 4350 4200 4350
+Connection ~ 4200 4350
+Wire Wire Line
+	5300 4450 5400 4450
+Wire Wire Line
+	5400 4250 5400 4650
+Wire Wire Line
+	5400 4250 5350 4250
+$Comp
+L resistor R?
+U 1 1 683EB199
+P 5500 3950
+F 0 "R?" H 5550 4080 50  0000 C CNN
+F 1 "12k" H 5550 3900 50  0000 C CNN
+F 2 "" H 5550 3930 30  0000 C CNN
+F 3 "" V 5550 4000 30  0000 C CNN
+	1    5500 3950
+	0    1    1    0   
+$EndComp
+Wire Wire Line
+	5550 3500 5550 3850
+Connection ~ 4850 3500
+$Comp
+L eSim_NPN Q?
+U 1 1 683EB23D
+P 5450 5050
+F 0 "Q?" H 5350 5100 50  0000 R CNN
+F 1 "eSim_NPN" H 5400 5200 50  0000 R CNN
+F 2 "" H 5650 5150 29  0000 C CNN
+F 3 "" H 5450 5050 60  0000 C CNN
+	1    5450 5050
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5250 5050 5250 4650
+Wire Wire Line
+	5250 4650 5400 4650
+Connection ~ 5400 4450
+Wire Wire Line
+	5550 4150 5550 4850
+Wire Wire Line
+	5550 5800 5550 5250
+Connection ~ 4850 5800
+$Comp
+L resistor R?
+U 1 1 683EC33E
+P 6100 3950
+F 0 "R?" H 6150 4080 50  0000 C CNN
+F 1 "12k" H 6150 3900 50  0000 C CNN
+F 2 "" H 6150 3930 30  0000 C CNN
+F 3 "" V 6150 4000 30  0000 C CNN
+	1    6100 3950
+	0    1    1    0   
+$EndComp
+Wire Wire Line
+	6150 3500 6150 3850
+Connection ~ 5550 3500
+$Comp
+L eSim_NPN Q?
+U 1 1 683EC87C
+P 6050 5000
+F 0 "Q?" H 5950 5050 50  0000 R CNN
+F 1 "eSim_NPN" H 6000 5150 50  0000 R CNN
+F 2 "" H 6250 5100 29  0000 C CNN
+F 3 "" H 6050 5000 60  0000 C CNN
+	1    6050 5000
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	6150 4150 6150 4800
+Wire Wire Line
+	6150 5800 6150 5200
+Connection ~ 5550 5800
+$Comp
+L resistor R?
+U 1 1 683ED134
+P 5800 4550
+F 0 "R?" H 5850 4680 50  0000 C CNN
+F 1 "12k" H 5850 4500 50  0000 C CNN
+F 2 "" H 5850 4530 30  0000 C CNN
+F 3 "" V 5850 4600 30  0000 C CNN
+	1    5800 4550
+	0    1    1    0   
+$EndComp
+Wire Wire Line
+	5850 4750 5850 5000
+Wire Wire Line
+	5850 4450 5850 4400
+Wire Wire Line
+	5850 4400 6300 4400
+Connection ~ 6150 4400
+$Comp
+L capacitor C?
+U 1 1 683EDB50
+P 6450 4200
+F 0 "C?" H 6475 4300 50  0000 L CNN
+F 1 "23p" H 6050 4100 50  0000 L CNN
+F 2 "" H 6488 4050 30  0000 C CNN
+F 3 "" H 6450 4200 60  0000 C CNN
+	1    6450 4200
+	0    1    1    0   
+$EndComp
+Wire Wire Line
+	6300 4200 5550 4200
+Connection ~ 5550 4200
+$Comp
+L resistor R?
+U 1 1 683EDC19
+P 6400 4450
+F 0 "R?" H 6450 4580 50  0000 C CNN
+F 1 "74k" H 6450 4400 50  0000 C CNN
+F 2 "" H 6450 4430 30  0000 C CNN
+F 3 "" V 6450 4500 30  0000 C CNN
+	1    6400 4450
+	1    0    0    -1  
+$EndComp
+$Comp
+L resistor R?
+U 1 1 683EDD49
+P 6750 3950
+F 0 "R?" H 6800 4080 50  0000 C CNN
+F 1 "12k" H 6800 3900 50  0000 C CNN
+F 2 "" H 6800 3930 30  0000 C CNN
+F 3 "" V 6800 4000 30  0000 C CNN
+	1    6750 3950
+	0    1    1    0   
+$EndComp
+$Comp
+L eSim_NPN Q?
+U 1 1 683EE23F
+P 6700 5000
+F 0 "Q?" H 6600 5050 50  0000 R CNN
+F 1 "eSim_NPN" H 6650 5150 50  0000 R CNN
+F 2 "" H 6900 5100 29  0000 C CNN
+F 3 "" H 6700 5000 60  0000 C CNN
+	1    6700 5000
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	6800 4150 6800 4800
+Wire Wire Line
+	6600 4200 6600 4600
+Wire Wire Line
+	6500 5000 6500 4600
+Wire Wire Line
+	6500 4600 6600 4600
+Connection ~ 6600 4400
+Wire Wire Line
+	6800 5800 6800 5200
+Connection ~ 6150 5800
+Wire Wire Line
+	6800 3500 6800 3850
+Connection ~ 6150 3500
+$Comp
+L eSim_NPN Q?
+U 1 1 683EF5C6
+P 7200 4400
+F 0 "Q?" H 7100 4450 50  0000 R CNN
+F 1 "eSim_NPN" H 7150 4550 50  0000 R CNN
+F 2 "" H 7400 4500 29  0000 C CNN
+F 3 "" H 7200 4400 60  0000 C CNN
+	1    7200 4400
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	7000 4400 6800 4400
+Connection ~ 6800 4400
+Wire Wire Line
+	7300 3500 7300 4200
+Connection ~ 6800 3500
+Wire Wire Line
+	7300 5800 7300 4600
+Connection ~ 6800 5800
+$Comp
+L PORT U?
+U 1 1 683F01D4
+P 8000 4850
+F 0 "U?" H 8050 4950 30  0000 C CNN
+F 1 "PORT" H 8000 4850 30  0000 C CNN
+F 2 "" H 8000 4850 60  0000 C CNN
+F 3 "" H 8000 4850 60  0000 C CNN
+	1    8000 4850
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U?
+U 2 1 683F022F
+P 8000 5150
+F 0 "U?" H 8050 5250 30  0000 C CNN
+F 1 "PORT" H 8000 5150 30  0000 C CNN
+F 2 "" H 8000 5150 60  0000 C CNN
+F 3 "" H 8000 5150 60  0000 C CNN
+	2    8000 5150
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U?
+U 3 1 683F0296
+P 7950 5400
+F 0 "U?" H 8000 5500 30  0000 C CNN
+F 1 "PORT" H 7950 5400 30  0000 C CNN
+F 2 "" H 7950 5400 60  0000 C CNN
+F 3 "" H 7950 5400 60  0000 C CNN
+	3    7950 5400
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/TA7642/TA7642.sub b/library/SubcircuitLibrary/TA7642/TA7642.sub
new file mode 100644
index 000000000..263c96295
--- /dev/null
+++ b/library/SubcircuitLibrary/TA7642/TA7642.sub
@@ -0,0 +1,36 @@
+* Subcircuit TA7642
+.subckt TA7642 net-_q10-pad3_ net-_q1-pad2_ net-_q1-pad1_ 
+* c:\fossee\esim\library\subcircuitlibrary\ta7642\ta7642.cir
+.include NPN.lib
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_c1-pad2_ Q2N2222
+q2 net-_c1-pad2_ net-_q2-pad2_ net-_q10-pad3_ Q2N2222
+c1  net-_c1-pad1_ net-_c1-pad2_ 12p
+r2  net-_c1-pad1_ net-_q4-pad2_ 3.3k
+r3  net-_q1-pad1_ net-_q3-pad1_ 12k
+r4  net-_q3-pad1_ net-_q4-pad2_ 12k
+q3 net-_q3-pad1_ net-_q2-pad2_ net-_q10-pad3_ Q2N2222
+r1  net-_q3-pad1_ net-_q2-pad2_ 5.6k
+r5  net-_q1-pad1_ net-_c2-pad2_ 12k
+q4 net-_c2-pad2_ net-_q4-pad2_ net-_q10-pad3_ Q2N2222
+c2  net-_c2-pad1_ net-_c2-pad2_ 12p
+r6  net-_q1-pad1_ net-_c3-pad2_ 12k
+q5 net-_c3-pad2_ net-_c2-pad1_ net-_q10-pad3_ Q2N2222
+r9  net-_q1-pad1_ net-_q6-pad1_ 12k
+r7  net-_c2-pad1_ net-_q6-pad1_ 12k
+q6 net-_q6-pad1_ net-_q6-pad2_ net-_q10-pad3_ Q2N2222
+r8  net-_q6-pad1_ net-_q6-pad2_ 12k
+r10  net-_q6-pad1_ net-_c3-pad1_ 12k
+c3  net-_c3-pad1_ net-_c3-pad2_ 12p
+r11  net-_q1-pad1_ net-_c4-pad2_ 12k
+q7 net-_c4-pad2_ net-_c3-pad1_ net-_q10-pad3_ Q2N2222
+r13  net-_q1-pad1_ net-_q8-pad1_ 12k
+q8 net-_q8-pad1_ net-_q8-pad2_ net-_q10-pad3_ Q2N2222
+r12  net-_q8-pad1_ net-_q8-pad2_ 12k
+c4  net-_c4-pad1_ net-_c4-pad2_ 23p
+r14  net-_q8-pad1_ net-_c4-pad1_ 74k
+r15  net-_q1-pad1_ net-_q10-pad2_ 12k
+q9 net-_q10-pad2_ net-_c4-pad1_ net-_q10-pad3_ Q2N2222
+q10 net-_q1-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222
+* Control Statements
+
+.ends TA7642
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/TA7642/TA7642_Previous_Values.xml b/library/SubcircuitLibrary/TA7642/TA7642_Previous_Values.xml
new file mode 100644
index 000000000..b3cf203cf
--- /dev/null
+++ b/library/SubcircuitLibrary/TA7642/TA7642_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model /><devicemodel><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><q6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q6><q7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q7><q8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q8><q9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q9><q10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q10></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/TA7642/TA7642_test-cache.lib b/library/SubcircuitLibrary/TA7642/TA7642_test-cache.lib
new file mode 100644
index 000000000..5cf84601c
--- /dev/null
+++ b/library/SubcircuitLibrary/TA7642/TA7642_test-cache.lib
@@ -0,0 +1,116 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# TA7642
+#
+DEF TA7642 X 0 40 Y Y 1 F N
+F0 "X" 0 -400 60 H V C CNN
+F1 "TA7642" 0 300 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -200 150 200 -100 0 1 0 N
+X A 1 0 -300 200 U 50 50 1 1 I
+X B 2 -400 0 200 R 50 50 1 1 I
+X C 3 400 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_C
+#
+DEF eSim_C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_C" 25 -100 50 H V L CNN
+F2 "" 38 -150 30 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS capacitor
+$FPLIST
+ C_*
+$ENDFPLIST
+DRAW
+P 2 0 1 20 -80 -30 80 -30 N
+P 2 0 1 20 -80 30 80 30 N
+X ~ 1 0 150 110 D 40 40 1 1 P
+X ~ 2 0 -150 110 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_GND
+#
+DEF eSim_GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "eSim_GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_VCC
+#
+DEF eSim_VCC #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -150 50 H I C CNN
+F1 "eSim_VCC" 0 150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+C 0 75 25 0 1 0 N
+P 2 0 1 0 0 0 0 50 N
+X VCC 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# sine
+#
+DEF sine v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "sine" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -50 0 50 1 1799 0 1 0 N 0 0 -100 0
+A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 0 1 1 I
+X - 2 0 -450 300 U 50 0 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/TA7642/TA7642_test.cir b/library/SubcircuitLibrary/TA7642/TA7642_test.cir
new file mode 100644
index 000000000..33a84c143
--- /dev/null
+++ b/library/SubcircuitLibrary/TA7642/TA7642_test.cir
@@ -0,0 +1,20 @@
+* C:\Users\pavithra\eSim-Workspace\TA7642_test\TA7642_test.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/03/25 13:07:35
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+C1  Net-_C1-Pad1_ in 0.01u		
+R1  in GND 75		
+C2  GND Vout 1u		
+R2  Net-_C1-Pad1_ Vout 100k		
+R3  Vout VCC 1.5k		
+U1  Vout plot_v1		
+v1  in GND sine		
+U2  in plot_v1		
+X1  GND Net-_C1-Pad1_ Vout TA7642		
+R4  Vout GND 100k		
+
+.end
diff --git a/library/SubcircuitLibrary/TA7642/TA7642_test.cir.out b/library/SubcircuitLibrary/TA7642/TA7642_test.cir.out
new file mode 100644
index 000000000..be0de6951
--- /dev/null
+++ b/library/SubcircuitLibrary/TA7642/TA7642_test.cir.out
@@ -0,0 +1,38 @@
+* c:\users\pavithra\esim-workspace\ta7642_test\ta7642_test.cir
+
+.include TA7642.sub
+
+* Input AM Signal (reduced amplitude)
+v1 in 0 AM(0.05 0.04 1k 1Meg 0 0)
+r1 in gnd 75
+c1 net-_c1-pad1_ in 0.01u
+
+* Power Supply (Safe for TA7642)
+v2 vcc gnd DC 1.4
+
+* TA7642 Instance
+x1 gnd net-_c1-pad1_ vout TA7642
+
+* Output stage
+r2 net-_c1-pad1_ vout 100k
+r3 vout vcc 1.5k
+r4 vout gnd 100k
+c2 gnd vout 1u
+
+* Probes
+* u1  vout plot_v1
+* u2  in plot_v1
+
+* Transient Analysis
+.tran 0.1u 10m 0
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(vout)
+plot v(in)
+.endc
+
+.end
diff --git a/library/SubcircuitLibrary/TA7642/TA7642_test.pro b/library/SubcircuitLibrary/TA7642/TA7642_test.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/TA7642/TA7642_test.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/TA7642/TA7642_test.proj b/library/SubcircuitLibrary/TA7642/TA7642_test.proj
new file mode 100644
index 000000000..15b792653
--- /dev/null
+++ b/library/SubcircuitLibrary/TA7642/TA7642_test.proj
@@ -0,0 +1 @@
+schematicFile TA7642_test.sch
diff --git a/library/SubcircuitLibrary/TA7642/TA7642_test.sch b/library/SubcircuitLibrary/TA7642/TA7642_test.sch
new file mode 100644
index 000000000..767bad85a
--- /dev/null
+++ b/library/SubcircuitLibrary/TA7642/TA7642_test.sch
@@ -0,0 +1,253 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:TA7642_test-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L capacitor C1
+U 1 1 683D76B8
+P 4400 3900
+F 0 "C1" H 4425 4000 50  0000 L CNN
+F 1 "0.01u" H 4425 3800 50  0000 L CNN
+F 2 "" H 4438 3750 30  0000 C CNN
+F 3 "" H 4400 3900 60  0000 C CNN
+	1    4400 3900
+	0    1    1    0   
+$EndComp
+$Comp
+L resistor R1
+U 1 1 683D76F0
+P 4100 4400
+F 0 "R1" H 4150 4530 50  0000 C CNN
+F 1 "75" H 4150 4350 50  0000 C CNN
+F 2 "" H 4150 4380 30  0000 C CNN
+F 3 "" V 4150 4450 30  0000 C CNN
+	1    4100 4400
+	0    1    1    0   
+$EndComp
+$Comp
+L capacitor C2
+U 1 1 683D775A
+P 5800 4200
+F 0 "C2" H 5825 4300 50  0000 L CNN
+F 1 "1u" H 5825 4100 50  0000 L CNN
+F 2 "" H 5838 4050 30  0000 C CNN
+F 3 "" H 5800 4200 60  0000 C CNN
+	1    5800 4200
+	-1   0    0    1   
+$EndComp
+$Comp
+L resistor R2
+U 1 1 683D77BE
+P 5350 3400
+F 0 "R2" H 5400 3530 50  0000 C CNN
+F 1 "100k" H 5400 3350 50  0000 C CNN
+F 2 "" H 5400 3380 30  0000 C CNN
+F 3 "" V 5400 3450 30  0000 C CNN
+	1    5350 3400
+	1    0    0    -1  
+$EndComp
+$Comp
+L resistor R3
+U 1 1 683D7822
+P 6100 3400
+F 0 "R3" H 6150 3530 50  0000 C CNN
+F 1 "1.5k" H 6150 3350 50  0000 C CNN
+F 2 "" H 6150 3380 30  0000 C CNN
+F 3 "" V 6150 3450 30  0000 C CNN
+	1    6100 3400
+	1    0    0    -1  
+$EndComp
+$Comp
+L eSim_GND #PWR01
+U 1 1 683D78A0
+P 6000 4800
+F 0 "#PWR01" H 6000 4550 50  0001 C CNN
+F 1 "eSim_GND" H 6000 4650 50  0000 C CNN
+F 2 "" H 6000 4800 50  0001 C CNN
+F 3 "" H 6000 4800 50  0001 C CNN
+	1    6000 4800
+	1    0    0    -1  
+$EndComp
+$Comp
+L plot_v1 U1
+U 1 1 683D78F9
+P 6100 4100
+F 0 "U1" H 6100 4600 60  0000 C CNN
+F 1 "plot_v1" H 6300 4450 60  0000 C CNN
+F 2 "" H 6100 4100 60  0000 C CNN
+F 3 "" H 6100 4100 60  0000 C CNN
+	1    6100 4100
+	1    0    0    -1  
+$EndComp
+Text GLabel 6500 4050 2    60   Input ~ 0
+Vout
+$Comp
+L sine v1
+U 1 1 683D79C7
+P 3750 4350
+F 0 "v1" H 3550 4450 60  0000 C CNN
+F 1 "sine" H 3550 4300 60  0000 C CNN
+F 2 "R1" H 3450 4350 60  0000 C CNN
+F 3 "" H 3750 4350 60  0000 C CNN
+	1    3750 4350
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4550 3900 4800 3900
+Wire Wire Line
+	4150 3900 4150 4300
+Wire Wire Line
+	3750 3900 4250 3900
+Wire Wire Line
+	5600 3900 6100 3900
+Wire Wire Line
+	5800 3350 5800 4050
+Wire Wire Line
+	4700 3900 4700 3350
+Wire Wire Line
+	4700 3350 5250 3350
+Connection ~ 4700 3900
+Wire Wire Line
+	5550 3350 6000 3350
+Connection ~ 5800 3900
+Connection ~ 5800 3350
+Wire Wire Line
+	5950 3900 5950 4050
+Wire Wire Line
+	5950 4050 6500 4050
+Connection ~ 5950 3900
+Connection ~ 4150 3900
+Wire Wire Line
+	3750 4800 6000 4800
+Wire Wire Line
+	4150 4800 4150 4600
+Wire Wire Line
+	5200 4800 5200 4200
+Connection ~ 4150 4800
+Wire Wire Line
+	5800 4800 5800 4350
+Connection ~ 5200 4800
+Connection ~ 5800 4800
+Text GLabel 3800 3800 0    60   Input ~ 0
+in
+$Comp
+L plot_v1 U2
+U 1 1 683DD3EC
+P 3950 3900
+F 0 "U2" H 3950 4400 60  0000 C CNN
+F 1 "plot_v1" H 4150 4250 60  0000 C CNN
+F 2 "" H 3950 3900 60  0000 C CNN
+F 3 "" H 3950 3900 60  0000 C CNN
+	1    3950 3900
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	3950 3700 3950 3900
+Connection ~ 3950 3900
+Wire Wire Line
+	3800 3800 3950 3800
+Connection ~ 3950 3800
+$Comp
+L eSim_VCC #PWR02
+U 1 1 683E8921
+P 6350 3250
+F 0 "#PWR02" H 6350 3100 50  0001 C CNN
+F 1 "eSim_VCC" H 6350 3400 50  0000 C CNN
+F 2 "" H 6350 3250 50  0001 C CNN
+F 3 "" H 6350 3250 50  0001 C CNN
+	1    6350 3250
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	6350 3250 6350 3350
+Wire Wire Line
+	6350 3350 6300 3350
+$Comp
+L TA7642 X1
+U 1 1 683E9609
+P 5200 3900
+F 0 "X1" H 5200 3500 60  0000 C CNN
+F 1 "TA7642" H 5200 4200 60  0000 C CNN
+F 2 "" H 5200 3900 60  0001 C CNN
+F 3 "" H 5200 3900 60  0001 C CNN
+	1    5200 3900
+	1    0    0    -1  
+$EndComp
+$Comp
+L resistor R4
+U 1 1 683EA678
+P 6000 4350
+F 0 "R4" V 6050 4480 50  0000 C CNN
+F 1 "100k" H 6050 4300 50  0000 C CNN
+F 2 "" H 6050 4330 30  0000 C CNN
+F 3 "" V 6050 4400 30  0000 C CNN
+	1    6000 4350
+	0    1    1    0   
+$EndComp
+Wire Wire Line
+	6050 4550 6050 4650
+Wire Wire Line
+	6050 4650 5900 4650
+Wire Wire Line
+	5900 4650 5900 4800
+Connection ~ 5900 4800
+Wire Wire Line
+	6050 4250 6050 4100
+Wire Wire Line
+	6050 4100 5900 4100
+Wire Wire Line
+	5900 4100 5900 3900
+Connection ~ 5900 3900
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/TA7642/TA7642_test_Previous_Values.xml b/library/SubcircuitLibrary/TA7642/TA7642_test_Previous_Values.xml
new file mode 100644
index 000000000..72957726d
--- /dev/null
+++ b/library/SubcircuitLibrary/TA7642/TA7642_test_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source><v1 name="Source type">sine<field1 name="Offset Value">0</field1><field2 name="Amplitude">300u</field2><field3 name="Frequency">1m</field3><field4 name="Delay Time">0</field4><field5 name="Damping Factor" /></v1><v2 name="Source type">dc<field1 name="Value">1.4</field1></v2></source><model /><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\TA7642</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">0.1</field2><field3 name="Stop Time">10</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">us</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/TA7642/analysis b/library/SubcircuitLibrary/TA7642/analysis
new file mode 100644
index 000000000..6dcba7452
--- /dev/null
+++ b/library/SubcircuitLibrary/TA7642/analysis
@@ -0,0 +1 @@
+.tran 0.1e-06 10e-03 0e-03
\ No newline at end of file
diff --git a/library/deviceModelLibrary/Diode/1N34A/1N34A.lib b/library/deviceModelLibrary/Diode/1N34A/1N34A.lib
new file mode 100644
index 000000000..f0dd46838
--- /dev/null
+++ b/library/deviceModelLibrary/Diode/1N34A/1N34A.lib
@@ -0,0 +1 @@
+.model 1N34A D(IS=2.6u RS=6.5 N=1.6 CJO=0.8p EG=0.67 BV=75 IBV=1m)
diff --git a/library/deviceModelLibrary/Diode/1N34A/1N34A.xml b/library/deviceModelLibrary/Diode/1N34A/1N34A.xml
new file mode 100644
index 000000000..b794cd96b
--- /dev/null
+++ b/library/deviceModelLibrary/Diode/1N34A/1N34A.xml
@@ -0,0 +1 @@
+<library><model_name>D</model_name><ref_model>1N34A</ref_model><param><IS>2.6u</IS><RS>6.5</RS><N>1.6</N><CJO>0.8p</CJO><EG>0.67</EG><BV>75</BV><IBV>1m</IBV></param></library>
\ No newline at end of file
diff --git a/library/deviceModelLibrary/JFET/2N4393/2N4393.lib b/library/deviceModelLibrary/JFET/2N4393/2N4393.lib
new file mode 100644
index 000000000..1d2d426f8
--- /dev/null
+++ b/library/deviceModelLibrary/JFET/2N4393/2N4393.lib
@@ -0,0 +1 @@
+.MODEL 2N4393 NJF (VTO=-1.4 BETA=0.0091 LAMBDA=0.006 RD=1 RS=1 CGS=4.1p CGD=4.6p PB=1 IS=205f AF=1 FC=0.5 BETATCE=-0.5 N=1 NR=2 XTI=3 VTOTC=-2.5m ALPHA=21u VK=1 ISR=10f KF=0.001f M=0.5)
diff --git a/library/deviceModelLibrary/JFET/2N4393/2N4393.xml b/library/deviceModelLibrary/JFET/2N4393/2N4393.xml
new file mode 100644
index 000000000..94a59a2da
--- /dev/null
+++ b/library/deviceModelLibrary/JFET/2N4393/2N4393.xml
@@ -0,0 +1 @@
+<library><model_name>NJF</model_name><ref_model>2N4393</ref_model><param><VTO>-1.4</VTO><BETA>0.0091</BETA><LAMBDA>0.006</LAMBDA><RD>1</RD><RS>1</RS><CGS>4.1p</CGS><CGD>4.6p</CGD><PB>1</PB><IS>205f</IS><AF>1</AF><FC>0.5</FC><BETATCE>-0.5</BETATCE><N>1</N><NR>2</NR><XTI>3</XTI><VTOTC>-2.5m</VTOTC><ALPHA>21u</ALPHA><VK>1</VK><ISR>10f</ISR><KF>0.001f</KF><M>0.5</M></param></library>
\ No newline at end of file
diff --git a/library/deviceModelLibrary/Transistor/2N3903/2N3903.lib b/library/deviceModelLibrary/Transistor/2N3903/2N3903.lib
new file mode 100644
index 000000000..8d0f57a3a
--- /dev/null
+++ b/library/deviceModelLibrary/Transistor/2N3903/2N3903.lib
@@ -0,0 +1,4 @@
+ .model 2N3903 NPN( Is=6.734f Xti=3 Eg=1.11 Vaf=74 Bf=200 Ne=1.5 
++ Ise=6.734f Ikf=0.284 Xtb=1.5 Br=3 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=3p 
++ Mjc=0.33 Vjc=0.75 Fc=0.5 Cje=4p Mje=0.33 Vje=0.75 Tr=100n Tf=350p 
++ Itf=0.1 Vtf=10 Xtf=1 Rb=0.56)
diff --git a/library/deviceModelLibrary/Transistor/2N3903/2N3903.xml b/library/deviceModelLibrary/Transistor/2N3903/2N3903.xml
new file mode 100644
index 000000000..7b48a6d2b
--- /dev/null
+++ b/library/deviceModelLibrary/Transistor/2N3903/2N3903.xml
@@ -0,0 +1 @@
+<library><model_name>NPN</model_name><ref_model>2N3903</ref_model><param><Is>6.734f</Is><Xti>3</Xti><Eg>1.11</Eg><Vaf>74</Vaf><Bf>200</Bf><Ne>1.5</Ne><Ise>6.734f</Ise><Ikf>0.284</Ikf><Xtb>1.5</Xtb><Br>3</Br><Nc>2</Nc><Isc>0</Isc><Ikr>0</Ikr><Rc>1</Rc><Cjc>3p</Cjc><Mjc>0.33</Mjc><Vjc>0.75</Vjc><Fc>0.5</Fc><Cje>4p</Cje><Mje>0.33</Mje><Vje>0.75</Vje><Tr>100n</Tr><Tf>350p</Tf><Itf>0.1</Itf><Vtf>10</Vtf><Xtf>1</Xtf><Rb>0.56</Rb></param></library>
\ No newline at end of file
diff --git a/library/deviceModelLibrary/Transistor/TIP41C/TIP41C.lib b/library/deviceModelLibrary/Transistor/TIP41C/TIP41C.lib
new file mode 100644
index 000000000..9660ac880
--- /dev/null
+++ b/library/deviceModelLibrary/Transistor/TIP41C/TIP41C.lib
@@ -0,0 +1,9 @@
+
+.model TIP41C NPN (
++ IS=1.0E-10 BF=100 NF=1.0 VAF=50 IKF=1.0
++ ISE=1.0E-11 NE=2.0 BR=1.0 NR=1.0 VAR=10 IKR=0.5
++ RE=0.5 RC=1.0 RB=1.0
++ CJE=30p VJE=0.75 MJE=0.33
++ CJC=10p VJC=0.5 MJC=0.33
++ TF=0.5n TR=1n
+)
diff --git a/library/deviceModelLibrary/Transistor/TIP41C/TIP41C.xml b/library/deviceModelLibrary/Transistor/TIP41C/TIP41C.xml
new file mode 100644
index 000000000..6cc915943
--- /dev/null
+++ b/library/deviceModelLibrary/Transistor/TIP41C/TIP41C.xml
@@ -0,0 +1 @@
+<library><model_name>NPN</model_name><ref_model>TIP41C</ref_model><param><IS>1.0E-10</IS><BF>100</BF><NF>1.0</NF><VAF>50</VAF><IKF>1.0</IKF><ISE>1.0E-11</ISE><NE>2.0</NE><BR>1.0</BR><NR>1.0</NR><VAR>10</VAR><IKR>0.5</IKR><RE>0.5</RE><RC>1.0</RC><RB>1.0</RB><CJE>30p</CJE><VJE>0.75</VJE><MJE>0.33</MJE><CJC>10p</CJC><VJC>0.5</VJC><MJC>0.33</MJC><TF>0.5n</TF><TR>1n</TR></param></library>
\ No newline at end of file