diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/3_and-cache.lib b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/3_and-cache.lib new file mode 100644 index 000000000..af0586415 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/3_and.cir b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/3_and.cir new file mode 100644 index 000000000..ba296cf01 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/3_and.cir.out b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/3_and.cir.out new file mode 100644 index 000000000..d7cf79a07 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/3_and.pro b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/3_and.pro new file mode 100644 index 000000000..00597a5ad --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/3_and.sch b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/3_and.sch new file mode 100644 index 000000000..d6ac89f95 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/3_and.sub b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/3_and.sub new file mode 100644 index 000000000..3d9120bb6 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/3_and_Previous_Values.xml b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/3_and_Previous_Values.xml new file mode 100644 index 000000000..abc5faaae --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/CD4095-cache.lib b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/CD4095-cache.lib new file mode 100644 index 000000000..c8dfbd26d --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/CD4095-cache.lib @@ -0,0 +1,227 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# adc_bridge_1 +# +DEF adc_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_buffer +# +DEF d_buffer U 0 40 Y Y 1 F N +F0 "U" 0 -50 60 H V C CNN +F1 "d_buffer" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N +X IN 1 -500 0 200 R 50 50 1 1 I +X OUT 2 650 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_1 +# +DEF dac_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/CD4095.cir b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/CD4095.cir new file mode 100644 index 000000000..3b14c0cc0 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/CD4095.cir @@ -0,0 +1,52 @@ +* C:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\CD4095\CD4095.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/08/25 19:10:18 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U6 Net-_U25-Pad13_ Net-_U16-Pad1_ d_inverter +X2 Net-_U25-Pad3_ Net-_U25-Pad4_ Net-_U25-Pad5_ Net-_U8-Pad1_ 3_and +U8 Net-_U8-Pad1_ Net-_U20-Pad3_ Net-_U11-Pad1_ d_or +U9 Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U11-Pad2_ d_or +U4 Net-_U20-Pad3_ Net-_U4-Pad2_ d_inverter +U5 Net-_U5-Pad1_ Net-_U5-Pad2_ d_inverter +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U10-Pad1_ d_and +U13 Net-_U12-Pad2_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_nand +U20 Net-_U18-Pad2_ Net-_U19-Pad2_ Net-_U20-Pad3_ d_or +U18 Net-_U16-Pad1_ Net-_U18-Pad2_ d_inverter +U19 Net-_U19-Pad1_ Net-_U19-Pad2_ d_inverter +U15 Net-_U14-Pad2_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_or +U14 Net-_U13-Pad3_ Net-_U14-Pad2_ d_inverter +U16 Net-_U16-Pad1_ Net-_U15-Pad2_ d_inverter +U21 Net-_U20-Pad3_ Net-_U13-Pad2_ Net-_U21-Pad3_ d_nand +U3 Net-_U25-Pad2_ Net-_U13-Pad2_ d_inverter +U7 Net-_U2-Pad2_ Net-_U32-Pad1_ d_inverter +X1 Net-_U25-Pad11_ Net-_U25-Pad10_ Net-_U25-Pad9_ Net-_U5-Pad1_ 3_and +U25 ? Net-_U25-Pad2_ Net-_U25-Pad3_ Net-_U25-Pad4_ Net-_U25-Pad5_ Net-_U23-Pad2_ GND Net-_U25-Pad8_ Net-_U25-Pad9_ Net-_U25-Pad10_ Net-_U25-Pad11_ Net-_U1-Pad1_ Net-_U25-Pad13_ VDD PORT +U26 Net-_U24-Pad2_ Net-_U25-Pad8_ d_buffer +U24 Net-_U21-Pad3_ Net-_U24-Pad2_ d_inverter +U23 Net-_U20-Pad3_ Net-_U23-Pad2_ d_inverter +M3 Net-_M1-Pad3_ CL Net-_M1-Pad1_ VDD mosfet_p +M1 Net-_M1-Pad1_ CL_BAR Net-_M1-Pad3_ GND mosfet_n +U10 Net-_U10-Pad1_ Net-_M1-Pad1_ dac_bridge_1 +U17 Net-_M1-Pad3_ Net-_U12-Pad2_ adc_bridge_1 +M6 Net-_M5-Pad3_ CL_BAR Net-_M5-Pad1_ VDD mosfet_p +M5 Net-_M5-Pad1_ CL_BAR Net-_M5-Pad3_ GND mosfet_n +U27 Net-_U13-Pad3_ Net-_M5-Pad1_ dac_bridge_1 +U29 Net-_M5-Pad3_ Net-_U19-Pad1_ adc_bridge_1 +M7 Net-_M7-Pad1_ CL Net-_M7-Pad3_ VDD mosfet_p +M8 Net-_M7-Pad3_ CL_BAR Net-_M7-Pad1_ GND mosfet_n +U30 Net-_U21-Pad3_ Net-_M7-Pad3_ dac_bridge_1 +U28 Net-_M7-Pad1_ Net-_U19-Pad1_ adc_bridge_1 +M2 Net-_M2-Pad1_ CL_BAR Net-_M2-Pad3_ VDD mosfet_p +M4 Net-_M2-Pad3_ CL Net-_M2-Pad1_ GND mosfet_n +U22 Net-_U15-Pad3_ Net-_M2-Pad3_ dac_bridge_1 +U12 Net-_M2-Pad1_ Net-_U12-Pad2_ adc_bridge_1 +U31 Net-_U2-Pad2_ CL dac_bridge_1 +U32 Net-_U32-Pad1_ CL_BAR dac_bridge_1 +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ d_inverter +U2 Net-_U1-Pad2_ Net-_U2-Pad2_ d_inverter + +.end diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/CD4095.cir.out b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/CD4095.cir.out new file mode 100644 index 000000000..25c3cb5fb --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/CD4095.cir.out @@ -0,0 +1,149 @@ +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\cd4095\cd4095.cir + +.include 3_and.sub +.include NMOS-180nm.lib +.include PMOS-180nm.lib +* u6 net-_u25-pad13_ net-_u16-pad1_ d_inverter +x2 net-_u25-pad3_ net-_u25-pad4_ net-_u25-pad5_ net-_u8-pad1_ 3_and +* u8 net-_u8-pad1_ net-_u20-pad3_ net-_u11-pad1_ d_or +* u9 net-_u4-pad2_ net-_u5-pad2_ net-_u11-pad2_ d_or +* u4 net-_u20-pad3_ net-_u4-pad2_ d_inverter +* u5 net-_u5-pad1_ net-_u5-pad2_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u10-pad1_ d_and +* u13 net-_u12-pad2_ net-_u13-pad2_ net-_u13-pad3_ d_nand +* u20 net-_u18-pad2_ net-_u19-pad2_ net-_u20-pad3_ d_or +* u18 net-_u16-pad1_ net-_u18-pad2_ d_inverter +* u19 net-_u19-pad1_ net-_u19-pad2_ d_inverter +* u15 net-_u14-pad2_ net-_u15-pad2_ net-_u15-pad3_ d_or +* u14 net-_u13-pad3_ net-_u14-pad2_ d_inverter +* u16 net-_u16-pad1_ net-_u15-pad2_ d_inverter +* u21 net-_u20-pad3_ net-_u13-pad2_ net-_u21-pad3_ d_nand +* u3 net-_u25-pad2_ net-_u13-pad2_ d_inverter +* u7 net-_u2-pad2_ net-_u32-pad1_ d_inverter +x1 net-_u25-pad11_ net-_u25-pad10_ net-_u25-pad9_ net-_u5-pad1_ 3_and +* u25 ? net-_u25-pad2_ net-_u25-pad3_ net-_u25-pad4_ net-_u25-pad5_ net-_u23-pad2_ gnd net-_u25-pad8_ net-_u25-pad9_ net-_u25-pad10_ net-_u25-pad11_ net-_u1-pad1_ net-_u25-pad13_ vdd port +* u26 net-_u24-pad2_ net-_u25-pad8_ d_buffer +* u24 net-_u21-pad3_ net-_u24-pad2_ d_inverter +* u23 net-_u20-pad3_ net-_u23-pad2_ d_inverter +m3 net-_m1-pad3_ cl net-_m1-pad1_ vdd CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ cl_bar net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1 +* u10 net-_u10-pad1_ net-_m1-pad1_ dac_bridge_1 +* u17 net-_m1-pad3_ net-_u12-pad2_ adc_bridge_1 +m6 net-_m5-pad3_ cl_bar net-_m5-pad1_ vdd CMOSP W=100u L=100u M=1 +m5 net-_m5-pad1_ cl_bar net-_m5-pad3_ gnd CMOSN W=100u L=100u M=1 +* u27 net-_u13-pad3_ net-_m5-pad1_ dac_bridge_1 +* u29 net-_m5-pad3_ net-_u19-pad1_ adc_bridge_1 +m7 net-_m7-pad1_ cl net-_m7-pad3_ vdd CMOSP W=100u L=100u M=1 +m8 net-_m7-pad3_ cl_bar net-_m7-pad1_ gnd CMOSN W=100u L=100u M=1 +* u30 net-_u21-pad3_ net-_m7-pad3_ dac_bridge_1 +* u28 net-_m7-pad1_ net-_u19-pad1_ adc_bridge_1 +m2 net-_m2-pad1_ cl_bar net-_m2-pad3_ vdd CMOSP W=100u L=100u M=1 +m4 net-_m2-pad3_ cl net-_m2-pad1_ gnd CMOSN W=100u L=100u M=1 +* u22 net-_u15-pad3_ net-_m2-pad3_ dac_bridge_1 +* u12 net-_m2-pad1_ net-_u12-pad2_ adc_bridge_1 +* u31 net-_u2-pad2_ cl dac_bridge_1 +* u32 net-_u32-pad1_ cl_bar dac_bridge_1 +* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter +* u2 net-_u1-pad2_ net-_u2-pad2_ d_inverter +a1 net-_u25-pad13_ net-_u16-pad1_ u6 +a2 [net-_u8-pad1_ net-_u20-pad3_ ] net-_u11-pad1_ u8 +a3 [net-_u4-pad2_ net-_u5-pad2_ ] net-_u11-pad2_ u9 +a4 net-_u20-pad3_ net-_u4-pad2_ u4 +a5 net-_u5-pad1_ net-_u5-pad2_ u5 +a6 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u10-pad1_ u11 +a7 [net-_u12-pad2_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a8 [net-_u18-pad2_ net-_u19-pad2_ ] net-_u20-pad3_ u20 +a9 net-_u16-pad1_ net-_u18-pad2_ u18 +a10 net-_u19-pad1_ net-_u19-pad2_ u19 +a11 [net-_u14-pad2_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a12 net-_u13-pad3_ net-_u14-pad2_ u14 +a13 net-_u16-pad1_ net-_u15-pad2_ u16 +a14 [net-_u20-pad3_ net-_u13-pad2_ ] net-_u21-pad3_ u21 +a15 net-_u25-pad2_ net-_u13-pad2_ u3 +a16 net-_u2-pad2_ net-_u32-pad1_ u7 +a17 net-_u24-pad2_ net-_u25-pad8_ u26 +a18 net-_u21-pad3_ net-_u24-pad2_ u24 +a19 net-_u20-pad3_ net-_u23-pad2_ u23 +a20 [net-_u10-pad1_ ] [net-_m1-pad1_ ] u10 +a21 [net-_m1-pad3_ ] [net-_u12-pad2_ ] u17 +a22 [net-_u13-pad3_ ] [net-_m5-pad1_ ] u27 +a23 [net-_m5-pad3_ ] [net-_u19-pad1_ ] u29 +a24 [net-_u21-pad3_ ] [net-_m7-pad3_ ] u30 +a25 [net-_m7-pad1_ ] [net-_u19-pad1_ ] u28 +a26 [net-_u15-pad3_ ] [net-_m2-pad3_ ] u22 +a27 [net-_m2-pad1_ ] [net-_u12-pad2_ ] u12 +a28 [net-_u2-pad2_ ] [cl ] u31 +a29 [net-_u32-pad1_ ] [cl_bar ] u32 +a30 net-_u1-pad1_ net-_u1-pad2_ u1 +a31 net-_u1-pad2_ net-_u2-pad2_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u8 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u9 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u20 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u15 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u21 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u26 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u10 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u17 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u27 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u29 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u30 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u28 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u22 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u12 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u31 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u32 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/CD4095.pro b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/CD4095.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/CD4095.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/CD4095.sch b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/CD4095.sch new file mode 100644 index 000000000..2daf72da7 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/CD4095.sch @@ -0,0 +1,1015 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:CD4095-cache +EELAYER 25 0 +EELAYER END +$Descr A2 23386 16535 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U6 +U 1 1 6864F6A8 +P 4750 2200 +F 0 "U6" H 4750 2100 60 0000 C CNN +F 1 "d_inverter" H 4750 2350 60 0000 C CNN +F 2 "" H 4800 2150 60 0000 C CNN +F 3 "" H 4800 2150 60 0000 C CNN + 1 4750 2200 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X2 +U 1 1 6864F6DE +P 3450 3150 +F 0 "X2" H 3550 3100 60 0000 C CNN +F 1 "3_and" H 3600 3300 60 0000 C CNN +F 2 "" H 3450 3150 60 0000 C CNN +F 3 "" H 3450 3150 60 0000 C CNN + 1 3450 3150 + 1 0 0 -1 +$EndComp +$Comp +L d_or U8 +U 1 1 6864F746 +P 4850 3150 +F 0 "U8" H 4850 3150 60 0000 C CNN +F 1 "d_or" H 4850 3250 60 0000 C CNN +F 2 "" H 4850 3150 60 0000 C CNN +F 3 "" H 4850 3150 60 0000 C CNN + 1 4850 3150 + 1 0 0 -1 +$EndComp +$Comp +L d_or U9 +U 1 1 6864F78C +P 5250 4200 +F 0 "U9" H 5250 4200 60 0000 C CNN +F 1 "d_or" H 5250 4300 60 0000 C CNN +F 2 "" H 5250 4200 60 0000 C CNN +F 3 "" H 5250 4200 60 0000 C CNN + 1 5250 4200 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 6864F808 +P 4400 4100 +F 0 "U4" H 4400 4000 60 0000 C CNN +F 1 "d_inverter" H 4400 4250 60 0000 C CNN +F 2 "" H 4450 4050 60 0000 C CNN +F 3 "" H 4450 4050 60 0000 C CNN + 1 4400 4100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 6864F861 +P 4400 4300 +F 0 "U5" H 4400 4200 60 0000 C CNN +F 1 "d_inverter" H 4400 4450 60 0000 C CNN +F 2 "" H 4450 4250 60 0000 C CNN +F 3 "" H 4450 4250 60 0000 C CNN + 1 4400 4300 + 1 0 0 -1 +$EndComp +$Comp +L d_and U11 +U 1 1 6864F89B +P 6600 3650 +F 0 "U11" H 6600 3650 60 0000 C CNN +F 1 "d_and" H 6650 3750 60 0000 C CNN +F 2 "" H 6600 3650 60 0000 C CNN +F 3 "" H 6600 3650 60 0000 C CNN + 1 6600 3650 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U13 +U 1 1 6864F9E7 +P 9750 3600 +F 0 "U13" H 9750 3600 60 0000 C CNN +F 1 "d_nand" H 9800 3700 60 0000 C CNN +F 2 "" H 9750 3600 60 0000 C CNN +F 3 "" H 9750 3600 60 0000 C CNN + 1 9750 3600 + 1 0 0 -1 +$EndComp +$Comp +L d_or U20 +U 1 1 6864FBFF +P 13650 3300 +F 0 "U20" H 13650 3300 60 0000 C CNN +F 1 "d_or" H 13650 3400 60 0000 C CNN +F 2 "" H 13650 3300 60 0000 C CNN +F 3 "" H 13650 3300 60 0000 C CNN + 1 13650 3300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U18 +U 1 1 6864FC05 +P 12800 3200 +F 0 "U18" H 12800 3100 60 0000 C CNN +F 1 "d_inverter" H 12800 3350 60 0000 C CNN +F 2 "" H 12850 3150 60 0000 C CNN +F 3 "" H 12850 3150 60 0000 C CNN + 1 12800 3200 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U19 +U 1 1 6864FC0B +P 12800 3400 +F 0 "U19" H 12800 3300 60 0000 C CNN +F 1 "d_inverter" H 12800 3550 60 0000 C CNN +F 2 "" H 12850 3350 60 0000 C CNN +F 3 "" H 12850 3350 60 0000 C CNN + 1 12800 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_or U15 +U 1 1 6864FE8E +P 10500 5800 +F 0 "U15" H 10500 5800 60 0000 C CNN +F 1 "d_or" H 10500 5900 60 0000 C CNN +F 2 "" H 10500 5800 60 0000 C CNN +F 3 "" H 10500 5800 60 0000 C CNN + 1 10500 5800 + 0 -1 1 0 +$EndComp +$Comp +L d_inverter U14 +U 1 1 6864FE94 +P 10400 4950 +F 0 "U14" H 10400 4850 60 0000 C CNN +F 1 "d_inverter" H 10400 5100 60 0000 C CNN +F 2 "" H 10450 4900 60 0000 C CNN +F 3 "" H 10450 4900 60 0000 C CNN + 1 10400 4950 + 0 -1 1 0 +$EndComp +$Comp +L d_inverter U16 +U 1 1 6864FE9A +P 10600 4950 +F 0 "U16" H 10600 4850 60 0000 C CNN +F 1 "d_inverter" H 10600 5100 60 0000 C CNN +F 2 "" H 10650 4900 60 0000 C CNN +F 3 "" H 10650 4900 60 0000 C CNN + 1 10600 4950 + 0 -1 1 0 +$EndComp +$Comp +L d_nand U21 +U 1 1 686500F2 +P 14100 4650 +F 0 "U21" H 14100 4650 60 0000 C CNN +F 1 "d_nand" H 14150 4750 60 0000 C CNN +F 2 "" H 14100 4650 60 0000 C CNN +F 3 "" H 14100 4650 60 0000 C CNN + 1 14100 4650 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U3 +U 1 1 686503B2 +P 3950 7300 +F 0 "U3" H 3950 7200 60 0000 C CNN +F 1 "d_inverter" H 3950 7450 60 0000 C CNN +F 2 "" H 4000 7250 60 0000 C CNN +F 3 "" H 4000 7250 60 0000 C CNN + 1 3950 7300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 68650940 +P 5050 8600 +F 0 "U7" H 5050 8500 60 0000 C CNN +F 1 "d_inverter" H 5050 8750 60 0000 C CNN +F 2 "" H 5100 8550 60 0000 C CNN +F 3 "" H 5100 8550 60 0000 C CNN + 1 5050 8600 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X1 +U 1 1 68651321 +P 3350 4800 +F 0 "X1" H 3450 4750 60 0000 C CNN +F 1 "3_and" H 3500 4950 60 0000 C CNN +F 2 "" H 3350 4800 60 0000 C CNN +F 3 "" H 3350 4800 60 0000 C CNN + 1 3350 4800 + 1 0 0 -1 +$EndComp +Text GLabel 6850 8600 2 60 Input ~ 0 +CL_BAR +Text GLabel 8250 7050 3 60 Input ~ 0 +CL +Text GLabel 8250 5800 1 60 Input ~ 0 +CL_BAR +$Comp +L PORT U25 +U 6 1 6865872B +P 15750 3250 +F 0 "U25" H 15800 3350 30 0000 C CNN +F 1 "PORT" H 15750 3250 30 0000 C CNN +F 2 "" H 15750 3250 60 0000 C CNN +F 3 "" H 15750 3250 60 0000 C CNN + 6 15750 3250 + -1 0 0 1 +$EndComp +$Comp +L PORT U25 +U 7 1 68658861 +P 9600 8000 +F 0 "U25" H 9650 8100 30 0000 C CNN +F 1 "PORT" H 9600 8000 30 0000 C CNN +F 2 "" H 9600 8000 60 0000 C CNN +F 3 "" H 9600 8000 60 0000 C CNN + 7 9600 8000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U25 +U 8 1 686589C6 +P 17200 5450 +F 0 "U25" H 17250 5550 30 0000 C CNN +F 1 "PORT" H 17200 5450 30 0000 C CNN +F 2 "" H 17200 5450 60 0000 C CNN +F 3 "" H 17200 5450 60 0000 C CNN + 8 17200 5450 + -1 0 0 1 +$EndComp +$Comp +L PORT U25 +U 9 1 68658A15 +P 2600 4850 +F 0 "U25" H 2650 4950 30 0000 C CNN +F 1 "PORT" H 2600 4850 30 0000 C CNN +F 2 "" H 2600 4850 60 0000 C CNN +F 3 "" H 2600 4850 60 0000 C CNN + 9 2600 4850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U25 +U 1 1 68658B76 +P 9550 9000 +F 0 "U25" H 9600 9100 30 0000 C CNN +F 1 "PORT" H 9550 9000 30 0000 C CNN +F 2 "" H 9550 9000 60 0000 C CNN +F 3 "" H 9550 9000 60 0000 C CNN + 1 9550 9000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U25 +U 2 1 68658CEA +P 3200 7300 +F 0 "U25" H 3250 7400 30 0000 C CNN +F 1 "PORT" H 3200 7300 30 0000 C CNN +F 2 "" H 3200 7300 60 0000 C CNN +F 3 "" H 3200 7300 60 0000 C CNN + 2 3200 7300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U25 +U 3 1 68658E87 +P 2550 3000 +F 0 "U25" H 2600 3100 30 0000 C CNN +F 1 "PORT" H 2550 3000 30 0000 C CNN +F 2 "" H 2550 3000 60 0000 C CNN +F 3 "" H 2550 3000 60 0000 C CNN + 3 2550 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U25 +U 4 1 68658F20 +P 2300 3100 +F 0 "U25" H 2350 3200 30 0000 C CNN +F 1 "PORT" H 2300 3100 30 0000 C CNN +F 2 "" H 2300 3100 60 0000 C CNN +F 3 "" H 2300 3100 60 0000 C CNN + 4 2300 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U25 +U 5 1 68658F79 +P 2550 3200 +F 0 "U25" H 2600 3300 30 0000 C CNN +F 1 "PORT" H 2550 3200 30 0000 C CNN +F 2 "" H 2550 3200 60 0000 C CNN +F 3 "" H 2550 3200 60 0000 C CNN + 5 2550 3200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U25 +U 11 1 68659227 +P 2600 4650 +F 0 "U25" H 2650 4750 30 0000 C CNN +F 1 "PORT" H 2600 4650 30 0000 C CNN +F 2 "" H 2600 4650 60 0000 C CNN +F 3 "" H 2600 4650 60 0000 C CNN + 11 2600 4650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U25 +U 12 1 6865928E +P 2500 8600 +F 0 "U25" H 2550 8700 30 0000 C CNN +F 1 "PORT" H 2500 8600 30 0000 C CNN +F 2 "" H 2500 8600 60 0000 C CNN +F 3 "" H 2500 8600 60 0000 C CNN + 12 2500 8600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U25 +U 13 1 686592ED +P 4000 2200 +F 0 "U25" H 4050 2300 30 0000 C CNN +F 1 "PORT" H 4000 2200 30 0000 C CNN +F 2 "" H 4000 2200 60 0000 C CNN +F 3 "" H 4000 2200 60 0000 C CNN + 13 4000 2200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U25 +U 10 1 6865934E +P 2350 4750 +F 0 "U25" H 2400 4850 30 0000 C CNN +F 1 "PORT" H 2350 4750 30 0000 C CNN +F 2 "" H 2350 4750 60 0000 C CNN +F 3 "" H 2350 4750 60 0000 C CNN + 10 2350 4750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U25 +U 14 1 6865943A +P 10950 9550 +F 0 "U25" H 11000 9650 30 0000 C CNN +F 1 "PORT" H 10950 9550 30 0000 C CNN +F 2 "" H 10950 9550 60 0000 C CNN +F 3 "" H 10950 9550 60 0000 C CNN + 14 10950 9550 + 1 0 0 -1 +$EndComp +NoConn ~ 9800 9000 +$Comp +L d_buffer U26 +U 1 1 68667A30 +P 16250 5450 +F 0 "U26" H 16250 5400 60 0000 C CNN +F 1 "d_buffer" H 16250 5500 60 0000 C CNN +F 2 "" H 16250 5450 60 0000 C CNN +F 3 "" H 16250 5450 60 0000 C CNN + 1 16250 5450 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U24 +U 1 1 686501DA +P 15100 5450 +F 0 "U24" H 15100 5350 60 0000 C CNN +F 1 "d_inverter" H 15100 5600 60 0000 C CNN +F 2 "" H 15150 5400 60 0000 C CNN +F 3 "" H 15150 5400 60 0000 C CNN + 1 15100 5450 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U23 +U 1 1 6864FC52 +P 14900 3250 +F 0 "U23" H 14900 3150 60 0000 C CNN +F 1 "d_inverter" H 14900 3400 60 0000 C CNN +F 2 "" H 14950 3200 60 0000 C CNN +F 3 "" H 14950 3200 60 0000 C CNN + 1 14900 3250 + 1 0 0 -1 +$EndComp +Text GLabel 9950 8000 2 60 Input ~ 0 +GND +Text GLabel 11250 9550 2 60 Input ~ 0 +VDD +$Comp +L mosfet_p M3 +U 1 1 68672F38 +P 8350 2900 +F 0 "M3" H 8300 2950 50 0000 R CNN +F 1 "mosfet_p" H 8400 3050 50 0000 R CNN +F 2 "" H 8600 3000 29 0000 C CNN +F 3 "" H 8400 2900 60 0000 C CNN + 1 8350 2900 + 0 1 1 0 +$EndComp +$Comp +L mosfet_n M1 +U 1 1 68672F3E +P 8150 3600 +F 0 "M1" H 8150 3450 50 0000 R CNN +F 1 "mosfet_n" H 8250 3550 50 0000 R CNN +F 2 "" H 8450 3300 29 0000 C CNN +F 3 "" H 8250 3400 60 0000 C CNN + 1 8150 3600 + 0 -1 -1 0 +$EndComp +Text GLabel 7900 3150 0 60 Input ~ 0 +VDD +Text GLabel 8650 3300 2 60 Input ~ 0 +GND +$Comp +L dac_bridge_1 U10 +U 1 1 68672F50 +P 7300 3350 +F 0 "U10" H 7300 3350 60 0000 C CNN +F 1 "dac_bridge_1" H 7300 3500 60 0000 C CNN +F 2 "" H 7300 3350 60 0000 C CNN +F 3 "" H 7300 3350 60 0000 C CNN + 1 7300 3350 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_1 U17 +U 1 1 68672F56 +P 9250 3150 +F 0 "U17" H 9250 3150 60 0000 C CNN +F 1 "adc_bridge_1" H 9250 3300 60 0000 C CNN +F 2 "" H 9250 3150 60 0000 C CNN +F 3 "" H 9250 3150 60 0000 C CNN + 1 9250 3150 + 1 0 0 -1 +$EndComp +Text GLabel 8350 2600 1 60 Input ~ 0 +CL +Text GLabel 8350 3850 3 60 Input ~ 0 +CL_BAR +$Comp +L mosfet_p M6 +U 1 1 68674966 +P 11350 3300 +F 0 "M6" H 11300 3350 50 0000 R CNN +F 1 "mosfet_p" H 11400 3450 50 0000 R CNN +F 2 "" H 11600 3400 29 0000 C CNN +F 3 "" H 11400 3300 60 0000 C CNN + 1 11350 3300 + 0 1 1 0 +$EndComp +$Comp +L mosfet_n M5 +U 1 1 6867496C +P 11150 4000 +F 0 "M5" H 11150 3850 50 0000 R CNN +F 1 "mosfet_n" H 11250 3950 50 0000 R CNN +F 2 "" H 11450 3700 29 0000 C CNN +F 3 "" H 11250 3800 60 0000 C CNN + 1 11150 4000 + 0 -1 -1 0 +$EndComp +Text GLabel 10900 3550 0 60 Input ~ 0 +VDD +$Comp +L dac_bridge_1 U27 +U 1 1 6867497E +P 10800 4250 +F 0 "U27" H 10800 4250 60 0000 C CNN +F 1 "dac_bridge_1" H 10800 4400 60 0000 C CNN +F 2 "" H 10800 4250 60 0000 C CNN +F 3 "" H 10800 4250 60 0000 C CNN + 1 10800 4250 + 0 1 -1 0 +$EndComp +$Comp +L adc_bridge_1 U29 +U 1 1 68674984 +P 11650 4200 +F 0 "U29" H 11650 4200 60 0000 C CNN +F 1 "adc_bridge_1" H 11650 4350 60 0000 C CNN +F 2 "" H 11650 4200 60 0000 C CNN +F 3 "" H 11650 4200 60 0000 C CNN + 1 11650 4200 + 0 1 1 0 +$EndComp +Text GLabel 11650 3500 2 60 Input ~ 0 +GND +Text GLabel 11350 3000 0 60 Input ~ 0 +CL_BAR +Text GLabel 11350 4250 3 60 Input ~ 0 +CL_BAR +$Comp +L mosfet_p M7 +U 1 1 686785A4 +P 12500 5800 +F 0 "M7" H 12450 5850 50 0000 R CNN +F 1 "mosfet_p" H 12550 5950 50 0000 R CNN +F 2 "" H 12750 5900 29 0000 C CNN +F 3 "" H 12550 5800 60 0000 C CNN + 1 12500 5800 + 0 -1 1 0 +$EndComp +$Comp +L mosfet_n M8 +U 1 1 686785AA +P 12700 6500 +F 0 "M8" H 12700 6350 50 0000 R CNN +F 1 "mosfet_n" H 12800 6450 50 0000 R CNN +F 2 "" H 13000 6200 29 0000 C CNN +F 3 "" H 12800 6300 60 0000 C CNN + 1 12700 6500 + 0 1 -1 0 +$EndComp +Text GLabel 12950 6050 2 60 Input ~ 0 +VDD +Text GLabel 12200 6200 0 60 Input ~ 0 +GND +$Comp +L dac_bridge_1 U30 +U 1 1 686785B2 +P 13550 6250 +F 0 "U30" H 13550 6250 60 0000 C CNN +F 1 "dac_bridge_1" H 13550 6400 60 0000 C CNN +F 2 "" H 13550 6250 60 0000 C CNN +F 3 "" H 13550 6250 60 0000 C CNN + 1 13550 6250 + -1 0 0 -1 +$EndComp +$Comp +L adc_bridge_1 U28 +U 1 1 686785B8 +P 11600 6050 +F 0 "U28" H 11600 6050 60 0000 C CNN +F 1 "adc_bridge_1" H 11600 6200 60 0000 C CNN +F 2 "" H 11600 6050 60 0000 C CNN +F 3 "" H 11600 6050 60 0000 C CNN + 1 11600 6050 + -1 0 0 -1 +$EndComp +Text GLabel 12500 5500 1 60 Input ~ 0 +CL +Text GLabel 12500 6750 3 60 Input ~ 0 +CL_BAR +$Comp +L mosfet_p M2 +U 1 1 6867A123 +P 8250 6100 +F 0 "M2" H 8200 6150 50 0000 R CNN +F 1 "mosfet_p" H 8300 6250 50 0000 R CNN +F 2 "" H 8500 6200 29 0000 C CNN +F 3 "" H 8300 6100 60 0000 C CNN + 1 8250 6100 + 0 -1 1 0 +$EndComp +$Comp +L mosfet_n M4 +U 1 1 6867A129 +P 8450 6800 +F 0 "M4" H 8450 6650 50 0000 R CNN +F 1 "mosfet_n" H 8550 6750 50 0000 R CNN +F 2 "" H 8750 6500 29 0000 C CNN +F 3 "" H 8550 6600 60 0000 C CNN + 1 8450 6800 + 0 1 -1 0 +$EndComp +Text GLabel 8700 6350 2 60 Input ~ 0 +VDD +Text GLabel 7950 6500 0 60 Input ~ 0 +GND +$Comp +L dac_bridge_1 U22 +U 1 1 6867A131 +P 9300 6550 +F 0 "U22" H 9300 6550 60 0000 C CNN +F 1 "dac_bridge_1" H 9300 6700 60 0000 C CNN +F 2 "" H 9300 6550 60 0000 C CNN +F 3 "" H 9300 6550 60 0000 C CNN + 1 9300 6550 + -1 0 0 -1 +$EndComp +$Comp +L adc_bridge_1 U12 +U 1 1 6867A137 +P 7350 6350 +F 0 "U12" H 7350 6350 60 0000 C CNN +F 1 "adc_bridge_1" H 7350 6500 60 0000 C CNN +F 2 "" H 7350 6350 60 0000 C CNN +F 3 "" H 7350 6350 60 0000 C CNN + 1 7350 6350 + -1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U31 +U 1 1 6867CDB0 +P 5550 8350 +F 0 "U31" H 5550 8350 60 0000 C CNN +F 1 "dac_bridge_1" H 5550 8500 60 0000 C CNN +F 2 "" H 5550 8350 60 0000 C CNN +F 3 "" H 5550 8350 60 0000 C CNN + 1 5550 8350 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U32 +U 1 1 6867D1AF +P 6200 8650 +F 0 "U32" H 6200 8650 60 0000 C CNN +F 1 "dac_bridge_1" H 6200 8800 60 0000 C CNN +F 2 "" H 6200 8650 60 0000 C CNN +F 3 "" H 6200 8650 60 0000 C CNN + 1 6200 8650 + 1 0 0 -1 +$EndComp +Text GLabel 6200 8300 2 60 Input ~ 0 +CL +Wire Wire Line + 3550 8600 3800 8600 +Wire Wire Line + 4400 8600 4750 8600 +Wire Wire Line + 3100 3000 2800 3000 +Wire Wire Line + 2550 3100 3100 3100 +Wire Wire Line + 3100 3200 2800 3200 +Wire Wire Line + 3950 3100 3950 3000 +Wire Wire Line + 3950 3000 4400 3000 +Wire Wire Line + 4400 3000 4400 3050 +Wire Wire Line + 4100 4300 3850 4300 +Wire Wire Line + 3850 4300 3850 4750 +Wire Wire Line + 4700 4100 4800 4100 +Wire Wire Line + 4800 4200 4700 4200 +Wire Wire Line + 4700 4200 4700 4300 +Wire Wire Line + 6150 3650 5700 3650 +Wire Wire Line + 5700 3650 5700 4150 +Wire Wire Line + 5300 3100 6150 3100 +Wire Wire Line + 6150 3100 6150 3550 +Wire Wire Line + 4100 4100 4100 2750 +Wire Wire Line + 4100 2750 14150 2750 +Wire Wire Line + 4400 3150 4100 3150 +Connection ~ 4100 3150 +Wire Wire Line + 4550 8600 4550 8300 +Wire Wire Line + 4550 8300 4950 8300 +Connection ~ 4550 8600 +Wire Wire Line + 5350 8600 5600 8600 +Wire Wire Line + 8800 3500 9300 3500 +Wire Wire Line + 12500 3450 12500 3400 +Wire Wire Line + 5050 2200 12200 2200 +Wire Wire Line + 12200 2200 12200 3200 +Wire Wire Line + 12200 3200 12500 3200 +Wire Wire Line + 13100 3200 13200 3200 +Wire Wire Line + 13200 3300 13200 3400 +Wire Wire Line + 13200 3400 13100 3400 +Wire Wire Line + 14100 3250 14600 3250 +Wire Wire Line + 14350 3250 14350 3850 +Wire Wire Line + 14350 3850 14200 3850 +Wire Wire Line + 14200 3850 14200 4200 +Connection ~ 14350 3250 +Wire Wire Line + 15200 3250 15500 3250 +Wire Wire Line + 14150 6200 14150 5100 +Wire Wire Line + 14150 5450 14800 5450 +Wire Wire Line + 15400 5450 15750 5450 +Wire Wire Line + 12400 3450 12400 5150 +Connection ~ 12400 3450 +Wire Wire Line + 13650 4000 14100 4000 +Wire Wire Line + 14100 4000 14100 4200 +Wire Wire Line + 10400 4650 10400 3650 +Wire Wire Line + 10400 3650 10250 3650 +Wire Wire Line + 10250 3650 10250 3550 +Connection ~ 10250 3550 +Wire Wire Line + 10400 5250 10400 5350 +Wire Wire Line + 10500 5350 10600 5350 +Wire Wire Line + 10600 5350 10600 5250 +Wire Wire Line + 10600 4650 10500 4650 +Wire Wire Line + 10500 4650 10500 2200 +Connection ~ 10500 2200 +Wire Wire Line + 8700 4050 8850 4050 +Wire Wire Line + 8850 4050 8850 3500 +Connection ~ 8850 3500 +Wire Wire Line + 10450 6550 10450 6250 +Connection ~ 14150 5450 +Wire Wire Line + 13650 4000 13650 7300 +Wire Wire Line + 13650 7300 4250 7300 +Wire Wire Line + 14150 2750 14150 3250 +Connection ~ 14150 3250 +Wire Wire Line + 3650 7300 3450 7300 +Wire Wire Line + 3000 4650 2850 4650 +Wire Wire Line + 2600 4750 3000 4750 +Wire Wire Line + 3000 4850 2850 4850 +Wire Wire Line + 4450 2200 4250 2200 +Wire Wire Line + 9300 3600 9200 3600 +Wire Wire Line + 9200 3600 9200 6000 +Wire Wire Line + 9200 6000 9500 6000 +Wire Wire Line + 9500 6000 9500 7300 +Connection ~ 9500 7300 +Wire Wire Line + 2750 8600 2950 8600 +Wire Wire Line + 8700 4750 8700 4050 +Wire Wire Line + 10200 3550 10600 3550 +Wire Wire Line + 16900 5450 16950 5450 +Wire Wire Line + 9850 8000 9950 8000 +Wire Wire Line + 11200 9550 11250 9550 +Wire Wire Line + 8150 3050 8050 3050 +Wire Wire Line + 8050 3050 8050 3400 +Wire Wire Line + 8050 3400 8150 3400 +Wire Wire Line + 8550 3050 8550 3400 +Wire Wire Line + 8350 3700 8350 3850 +Wire Wire Line + 8350 2600 8350 2750 +Wire Wire Line + 7900 3150 8200 3150 +Wire Wire Line + 8500 3300 8500 3250 +Wire Wire Line + 8500 3250 8650 3250 +Wire Wire Line + 8650 3250 8650 3300 +Wire Wire Line + 8650 3100 8650 3200 +Wire Wire Line + 8650 3200 8550 3200 +Connection ~ 8550 3200 +Wire Wire Line + 7850 3300 8050 3300 +Connection ~ 8050 3300 +Wire Wire Line + 6700 3300 6700 3450 +Wire Wire Line + 6700 3450 7050 3450 +Wire Wire Line + 7050 3450 7050 3600 +Wire Wire Line + 8800 3500 8800 3400 +Wire Wire Line + 8800 3400 9250 3400 +Wire Wire Line + 9250 3400 9250 3300 +Wire Wire Line + 9250 3300 9800 3300 +Wire Wire Line + 9800 3300 9800 3100 +Wire Wire Line + 11150 3450 11050 3450 +Wire Wire Line + 11050 3450 11050 3800 +Wire Wire Line + 11050 3800 11150 3800 +Wire Wire Line + 11550 3450 11550 3800 +Wire Wire Line + 11350 4100 11350 4250 +Wire Wire Line + 11350 3000 11350 3150 +Wire Wire Line + 10900 3550 11200 3550 +Wire Wire Line + 11500 3500 11500 3700 +Wire Wire Line + 11550 3600 11700 3600 +Connection ~ 11550 3600 +Wire Wire Line + 10850 3700 11050 3700 +Connection ~ 11050 3700 +Wire Wire Line + 10600 3550 10600 4550 +Wire Wire Line + 10600 4550 10700 4550 +Wire Wire Line + 10700 4550 10700 4850 +Wire Wire Line + 10700 4850 10850 4850 +Wire Wire Line + 11700 4750 11700 4800 +Wire Wire Line + 11700 4800 12000 4800 +Wire Wire Line + 12000 4800 12000 3450 +Wire Wire Line + 12000 3450 12500 3450 +Wire Wire Line + 11650 3500 11500 3500 +Wire Wire Line + 12700 5950 12800 5950 +Wire Wire Line + 12800 5950 12800 6300 +Wire Wire Line + 12800 6300 12700 6300 +Wire Wire Line + 12300 5950 12300 6300 +Wire Wire Line + 12500 6600 12500 6750 +Wire Wire Line + 12500 5500 12500 5650 +Wire Wire Line + 12950 6050 12650 6050 +Wire Wire Line + 12350 6200 12350 6150 +Wire Wire Line + 12350 6150 12200 6150 +Wire Wire Line + 12200 6150 12200 6200 +Wire Wire Line + 12200 6000 12200 6100 +Wire Wire Line + 12200 6100 12300 6100 +Connection ~ 12300 6100 +Wire Wire Line + 13000 6200 12800 6200 +Connection ~ 12800 6200 +Wire Wire Line + 12400 5150 10950 5150 +Wire Wire Line + 10950 5150 10950 6000 +Wire Wire Line + 10950 6000 11050 6000 +Wire Wire Line + 8450 6250 8550 6250 +Wire Wire Line + 8550 6250 8550 6600 +Wire Wire Line + 8550 6600 8450 6600 +Wire Wire Line + 8050 6250 8050 6600 +Wire Wire Line + 8250 6900 8250 7050 +Wire Wire Line + 8250 5800 8250 5950 +Wire Wire Line + 8700 6350 8400 6350 +Wire Wire Line + 8100 6500 8100 6450 +Wire Wire Line + 8100 6450 7950 6450 +Wire Wire Line + 7950 6450 7950 6500 +Wire Wire Line + 7950 6300 7950 6400 +Wire Wire Line + 7950 6400 8050 6400 +Connection ~ 8050 6400 +Wire Wire Line + 8750 6500 8550 6500 +Connection ~ 8550 6500 +Wire Wire Line + 9900 6500 10200 6500 +Wire Wire Line + 10200 6500 10200 6550 +Wire Wire Line + 10200 6550 10450 6550 +Wire Wire Line + 8700 4750 6800 4750 +Wire Wire Line + 6800 4750 6800 6300 +Wire Wire Line + 6100 8300 6200 8300 +Wire Wire Line + 6750 8600 6850 8600 +$Comp +L d_inverter U1 +U 1 1 6865067C +P 3250 8600 +F 0 "U1" H 3250 8500 60 0000 C CNN +F 1 "d_inverter" H 3250 8750 60 0000 C CNN +F 2 "" H 3300 8550 60 0000 C CNN +F 3 "" H 3300 8550 60 0000 C CNN + 1 3250 8600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 68650864 +P 4100 8600 +F 0 "U2" H 4100 8500 60 0000 C CNN +F 1 "d_inverter" H 4100 8750 60 0000 C CNN +F 2 "" H 4150 8550 60 0000 C CNN +F 3 "" H 4150 8550 60 0000 C CNN + 1 4100 8600 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/CD4095.sub b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/CD4095.sub new file mode 100644 index 000000000..60425c8ad --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/CD4095.sub @@ -0,0 +1,143 @@ +* Subcircuit CD4095 +.subckt CD4095 ? net-_u25-pad2_ net-_u25-pad3_ net-_u25-pad4_ net-_u25-pad5_ net-_u23-pad2_ gnd net-_u25-pad8_ net-_u25-pad9_ net-_u25-pad10_ net-_u25-pad11_ net-_u1-pad1_ net-_u25-pad13_ vdd +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\cd4095\cd4095.cir +.include 3_and.sub +.include NMOS-180nm.lib +.include PMOS-180nm.lib +* u6 net-_u25-pad13_ net-_u16-pad1_ d_inverter +x2 net-_u25-pad3_ net-_u25-pad4_ net-_u25-pad5_ net-_u8-pad1_ 3_and +* u8 net-_u8-pad1_ net-_u20-pad3_ net-_u11-pad1_ d_or +* u9 net-_u4-pad2_ net-_u5-pad2_ net-_u11-pad2_ d_or +* u4 net-_u20-pad3_ net-_u4-pad2_ d_inverter +* u5 net-_u5-pad1_ net-_u5-pad2_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u10-pad1_ d_and +* u13 net-_u12-pad2_ net-_u13-pad2_ net-_u13-pad3_ d_nand +* u20 net-_u18-pad2_ net-_u19-pad2_ net-_u20-pad3_ d_or +* u18 net-_u16-pad1_ net-_u18-pad2_ d_inverter +* u19 net-_u19-pad1_ net-_u19-pad2_ d_inverter +* u15 net-_u14-pad2_ net-_u15-pad2_ net-_u15-pad3_ d_or +* u14 net-_u13-pad3_ net-_u14-pad2_ d_inverter +* u16 net-_u16-pad1_ net-_u15-pad2_ d_inverter +* u21 net-_u20-pad3_ net-_u13-pad2_ net-_u21-pad3_ d_nand +* u3 net-_u25-pad2_ net-_u13-pad2_ d_inverter +* u7 net-_u2-pad2_ net-_u32-pad1_ d_inverter +x1 net-_u25-pad11_ net-_u25-pad10_ net-_u25-pad9_ net-_u5-pad1_ 3_and +* u26 net-_u24-pad2_ net-_u25-pad8_ d_buffer +* u24 net-_u21-pad3_ net-_u24-pad2_ d_inverter +* u23 net-_u20-pad3_ net-_u23-pad2_ d_inverter +m3 net-_m1-pad3_ cl net-_m1-pad1_ vdd CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ cl_bar net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1 +* u10 net-_u10-pad1_ net-_m1-pad1_ dac_bridge_1 +* u17 net-_m1-pad3_ net-_u12-pad2_ adc_bridge_1 +m6 net-_m5-pad3_ cl_bar net-_m5-pad1_ vdd CMOSP W=100u L=100u M=1 +m5 net-_m5-pad1_ cl_bar net-_m5-pad3_ gnd CMOSN W=100u L=100u M=1 +* u27 net-_u13-pad3_ net-_m5-pad1_ dac_bridge_1 +* u29 net-_m5-pad3_ net-_u19-pad1_ adc_bridge_1 +m7 net-_m7-pad1_ cl net-_m7-pad3_ vdd CMOSP W=100u L=100u M=1 +m8 net-_m7-pad3_ cl_bar net-_m7-pad1_ gnd CMOSN W=100u L=100u M=1 +* u30 net-_u21-pad3_ net-_m7-pad3_ dac_bridge_1 +* u28 net-_m7-pad1_ net-_u19-pad1_ adc_bridge_1 +m2 net-_m2-pad1_ cl_bar net-_m2-pad3_ vdd CMOSP W=100u L=100u M=1 +m4 net-_m2-pad3_ cl net-_m2-pad1_ gnd CMOSN W=100u L=100u M=1 +* u22 net-_u15-pad3_ net-_m2-pad3_ dac_bridge_1 +* u12 net-_m2-pad1_ net-_u12-pad2_ adc_bridge_1 +* u31 net-_u2-pad2_ cl dac_bridge_1 +* u32 net-_u32-pad1_ cl_bar dac_bridge_1 +* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter +* u2 net-_u1-pad2_ net-_u2-pad2_ d_inverter +a1 net-_u25-pad13_ net-_u16-pad1_ u6 +a2 [net-_u8-pad1_ net-_u20-pad3_ ] net-_u11-pad1_ u8 +a3 [net-_u4-pad2_ net-_u5-pad2_ ] net-_u11-pad2_ u9 +a4 net-_u20-pad3_ net-_u4-pad2_ u4 +a5 net-_u5-pad1_ net-_u5-pad2_ u5 +a6 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u10-pad1_ u11 +a7 [net-_u12-pad2_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a8 [net-_u18-pad2_ net-_u19-pad2_ ] net-_u20-pad3_ u20 +a9 net-_u16-pad1_ net-_u18-pad2_ u18 +a10 net-_u19-pad1_ net-_u19-pad2_ u19 +a11 [net-_u14-pad2_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a12 net-_u13-pad3_ net-_u14-pad2_ u14 +a13 net-_u16-pad1_ net-_u15-pad2_ u16 +a14 [net-_u20-pad3_ net-_u13-pad2_ ] net-_u21-pad3_ u21 +a15 net-_u25-pad2_ net-_u13-pad2_ u3 +a16 net-_u2-pad2_ net-_u32-pad1_ u7 +a17 net-_u24-pad2_ net-_u25-pad8_ u26 +a18 net-_u21-pad3_ net-_u24-pad2_ u24 +a19 net-_u20-pad3_ net-_u23-pad2_ u23 +a20 [net-_u10-pad1_ ] [net-_m1-pad1_ ] u10 +a21 [net-_m1-pad3_ ] [net-_u12-pad2_ ] u17 +a22 [net-_u13-pad3_ ] [net-_m5-pad1_ ] u27 +a23 [net-_m5-pad3_ ] [net-_u19-pad1_ ] u29 +a24 [net-_u21-pad3_ ] [net-_m7-pad3_ ] u30 +a25 [net-_m7-pad1_ ] [net-_u19-pad1_ ] u28 +a26 [net-_u15-pad3_ ] [net-_m2-pad3_ ] u22 +a27 [net-_m2-pad1_ ] [net-_u12-pad2_ ] u12 +a28 [net-_u2-pad2_ ] [cl ] u31 +a29 [net-_u32-pad1_ ] [cl_bar ] u32 +a30 net-_u1-pad1_ net-_u1-pad2_ u1 +a31 net-_u1-pad2_ net-_u2-pad2_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u8 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u9 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u20 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u15 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u21 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u26 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u10 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u17 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u27 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u29 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u30 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u28 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u22 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u12 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u31 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u32 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends CD4095 \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/CD4095_Previous_Values.xml b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/CD4095_Previous_Values.xml new file mode 100644 index 000000000..c815e0456 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/CD4095_Previous_Values.xml @@ -0,0 +1 @@ +d_inverterd_ord_ord_inverterd_inverterd_andtransmission_gated_nandtransmission_gated_ord_inverterd_inverterd_inverterd_ord_inverterd_inverterd_nandd_inverterd_inverterd_inverterd_inverterd_invertertransmission_gatetransmission_gated_bufferdac_bridgeadc_bridgedac_bridgeadc_bridgedac_bridgeadc_bridgedac_bridgeadc_bridgedac_bridgedac_bridgeC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/NMOS-180nm.lib b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/NMOS-180nm.lib new file mode 100644 index 000000000..51e9b1196 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/PMOS-180nm.lib b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/PMOS-180nm.lib new file mode 100644 index 000000000..032b5b95e --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/analysis b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4095/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4511B/CD4511B-cache.lib b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4511B/CD4511B-cache.lib new file mode 100644 index 000000000..78c5e878f --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4511B/CD4511B-cache.lib @@ -0,0 +1,211 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# adc_bridge_1 +# +DEF adc_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# dac_bridge_1 +# +DEF dac_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# nor_four +# +DEF nor_four U 0 40 Y Y 1 F N +F0 "U" 2850 1800 60 H V C CNN +F1 "nor_four" 2850 2000 60 H V C CNN +F2 "" 2850 1950 60 H V C CNN +F3 "" 2850 1950 60 H V C CNN +DRAW +S 2350 2100 3350 1400 0 1 0 N +X A0 1 2150 1900 200 R 50 50 1 1 I +X B0 2 2150 1800 200 R 50 50 1 1 I +X C0 3 2150 1700 200 R 50 50 1 1 I +X D0 4 2150 1600 200 R 50 50 1 1 I +X Y0 5 3550 1900 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# nor_thre +# +DEF nor_thre U 0 40 Y Y 1 F N +F0 "U" 2850 1800 60 H V C CNN +F1 "nor_thre" 2850 2000 60 H V C CNN +F2 "" 2850 1950 60 H V C CNN +F3 "" 2850 1950 60 H V C CNN +DRAW +S 2350 2100 3350 1500 0 1 0 N +X a0 1 2150 1900 200 R 50 50 1 1 I +X b0 2 2150 1800 200 R 50 50 1 1 I +X c0 3 2150 1700 200 R 50 50 1 1 I +X y0 4 3550 1900 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4511B/CD4511B.cir b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4511B/CD4511B.cir new file mode 100644 index 000000000..bc6ba0000 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4511B/CD4511B.cir @@ -0,0 +1,96 @@ +* C:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\CD4511B\CD4511B.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/26/25 22:17:26 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M3 Net-_M3-Pad1_ Net-_M3-Pad2_ Net-_M3-Pad3_ GND mosfet_n +M7 Net-_M3-Pad3_ Net-_M7-Pad2_ Net-_M3-Pad1_ VCC mosfet_p +U26 Net-_M3-Pad3_ Net-_U26-Pad2_ adc_bridge_1 +U22 Net-_U11-Pad2_ Net-_M7-Pad2_ dac_bridge_1 +U14 Net-_U14-Pad1_ Net-_M3-Pad1_ dac_bridge_1 +U9 Net-_U4-Pad2_ Net-_U14-Pad1_ d_inverter +U4 Net-_U106-Pad7_ Net-_U4-Pad2_ adc_bridge_1 +U30 Net-_U26-Pad2_ Net-_U30-Pad2_ d_inverter +U33 Net-_U30-Pad2_ Net-_U33-Pad2_ d_inverter +U18 Net-_U11-Pad1_ Net-_M3-Pad2_ dac_bridge_1 +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ GND mosfet_n +M5 Net-_M1-Pad3_ Net-_M5-Pad2_ Net-_M1-Pad1_ VCC mosfet_p +U24 Net-_M1-Pad3_ Net-_U24-Pad2_ adc_bridge_1 +U19 Net-_U11-Pad2_ Net-_M5-Pad2_ dac_bridge_1 +U12 Net-_U12-Pad1_ Net-_M1-Pad1_ dac_bridge_1 +U7 Net-_U2-Pad2_ Net-_U12-Pad1_ d_inverter +U2 Net-_U106-Pad1_ Net-_U2-Pad2_ adc_bridge_1 +U28 Net-_U24-Pad2_ Net-_U28-Pad2_ d_inverter +U32 Net-_U28-Pad2_ Net-_U32-Pad2_ d_inverter +U16 Net-_U11-Pad1_ Net-_M1-Pad2_ dac_bridge_1 +M4 Net-_M4-Pad1_ Net-_M4-Pad2_ Net-_M4-Pad3_ GND mosfet_n +M8 Net-_M4-Pad3_ Net-_M8-Pad2_ Net-_M4-Pad1_ VCC mosfet_p +U27 Net-_M4-Pad3_ Net-_U27-Pad2_ adc_bridge_1 +U23 Net-_U11-Pad2_ Net-_M8-Pad2_ dac_bridge_1 +U15 Net-_U10-Pad2_ Net-_M4-Pad1_ dac_bridge_1 +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter +U5 Net-_U106-Pad2_ Net-_U10-Pad1_ adc_bridge_1 +U31 Net-_U27-Pad2_ Net-_U31-Pad2_ d_inverter +U34 Net-_U31-Pad2_ Net-_U34-Pad2_ d_inverter +U20 Net-_U11-Pad1_ Net-_M4-Pad2_ dac_bridge_1 +M2 Net-_M2-Pad1_ Net-_M2-Pad2_ Net-_M2-Pad3_ GND mosfet_n +M6 Net-_M2-Pad3_ Net-_M6-Pad2_ Net-_M2-Pad1_ VCC mosfet_p +U25 Net-_M2-Pad3_ Net-_U25-Pad2_ adc_bridge_1 +U21 Net-_U11-Pad2_ Net-_M6-Pad2_ dac_bridge_1 +U13 Net-_U13-Pad1_ Net-_M2-Pad1_ dac_bridge_1 +U8 Net-_U3-Pad2_ Net-_U13-Pad1_ d_inverter +U3 Net-_U106-Pad6_ Net-_U3-Pad2_ adc_bridge_1 +U29 Net-_U25-Pad2_ Net-_U29-Pad2_ d_inverter +U17 Net-_U11-Pad1_ Net-_M2-Pad2_ dac_bridge_1 +U35 Net-_U34-Pad2_ Net-_U32-Pad2_ Net-_U35-Pad3_ d_nand +U51 Net-_U35-Pad3_ Net-_U29-Pad2_ Net-_U51-Pad3_ d_nand +U63 Net-_U48-Pad2_ Net-_U51-Pad3_ Net-_U45-Pad1_ d_nand +U37 Net-_U32-Pad2_ Net-_U31-Pad2_ Net-_U37-Pad3_ d_nor +U6 Net-_U1-Pad2_ Net-_U11-Pad1_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ adc_bridge_1 +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ d_inverter +U48 Net-_U106-Pad4_ Net-_U48-Pad2_ adc_bridge_1 +U72 Net-_U45-Pad1_ Net-_U40-Pad4_ Net-_U72-Pad3_ d_nor +U85 Net-_U45-Pad5_ Net-_U83-Pad2_ Net-_U85-Pad3_ d_nor +U86 Net-_U46-Pad4_ Net-_U83-Pad2_ Net-_U86-Pad3_ d_nor +U87 Net-_U72-Pad3_ Net-_U83-Pad2_ Net-_U87-Pad3_ d_nor +U88 Net-_U47-Pad5_ Net-_U83-Pad2_ Net-_U88-Pad3_ d_nor +U89 Net-_U49-Pad4_ Net-_U83-Pad2_ Net-_U89-Pad3_ d_nor +U90 Net-_U50-Pad5_ Net-_U83-Pad2_ Net-_U90-Pad3_ d_nor +U91 Net-_U52-Pad5_ Net-_U83-Pad2_ Net-_U91-Pad3_ d_nor +U83 Net-_U73-Pad2_ Net-_U83-Pad2_ d_inverter +U73 Net-_U106-Pad3_ Net-_U73-Pad2_ adc_bridge_1 +U92 Net-_U85-Pad3_ Net-_U92-Pad2_ d_inverter +U93 Net-_U86-Pad3_ Net-_U100-Pad1_ d_inverter +U99 Net-_U92-Pad2_ Net-_U106-Pad13_ dac_bridge_1 +U100 Net-_U100-Pad1_ Net-_U100-Pad2_ dac_bridge_1 +U94 Net-_U87-Pad3_ Net-_U101-Pad1_ d_inverter +U101 Net-_U101-Pad1_ Net-_U101-Pad2_ dac_bridge_1 +U95 Net-_U88-Pad3_ Net-_U102-Pad1_ d_inverter +U96 Net-_U89-Pad3_ Net-_U103-Pad1_ d_inverter +U102 Net-_U102-Pad1_ Net-_U102-Pad2_ dac_bridge_1 +U103 Net-_U103-Pad1_ Net-_U103-Pad2_ dac_bridge_1 +U98 Net-_U90-Pad3_ Net-_U105-Pad1_ d_inverter +U105 Net-_U105-Pad1_ Net-_U105-Pad2_ dac_bridge_1 +U97 Net-_U91-Pad3_ Net-_U104-Pad1_ d_inverter +U104 Net-_U104-Pad1_ Net-_U104-Pad2_ dac_bridge_1 +U106 Net-_U106-Pad1_ Net-_U106-Pad2_ Net-_U106-Pad3_ Net-_U106-Pad4_ Net-_U1-Pad1_ Net-_U106-Pad6_ Net-_U106-Pad7_ GND Net-_U103-Pad2_ Net-_U102-Pad2_ Net-_U101-Pad2_ Net-_U100-Pad2_ Net-_U106-Pad13_ Net-_U104-Pad2_ Net-_U105-Pad2_ VCC PORT +U40 Net-_U30-Pad2_ Net-_U32-Pad2_ Net-_U31-Pad2_ Net-_U40-Pad4_ nor_thre +U41 Net-_U33-Pad2_ Net-_U28-Pad2_ Net-_U31-Pad2_ Net-_U41-Pad4_ nor_thre +U42 Net-_U33-Pad2_ Net-_U32-Pad2_ Net-_U34-Pad2_ Net-_U42-Pad4_ nor_thre +U38 Net-_U33-Pad2_ Net-_U28-Pad2_ Net-_U34-Pad2_ Net-_U38-Pad4_ nor_thre +U39 Net-_U30-Pad2_ Net-_U34-Pad2_ Net-_U28-Pad2_ Net-_U39-Pad4_ nor_thre +U43 Net-_U30-Pad2_ Net-_U28-Pad2_ Net-_U31-Pad2_ Net-_U29-Pad2_ Net-_U43-Pad5_ nor_four +U44 Net-_U33-Pad2_ Net-_U28-Pad2_ Net-_U31-Pad2_ Net-_U29-Pad2_ Net-_U44-Pad5_ nor_four +U36 Net-_U30-Pad2_ Net-_U32-Pad2_ Net-_U34-Pad2_ Net-_U36-Pad4_ nor_thre +U45 Net-_U45-Pad1_ Net-_U36-Pad4_ Net-_U39-Pad4_ Net-_U44-Pad5_ Net-_U45-Pad5_ nor_four +U46 Net-_U45-Pad1_ Net-_U36-Pad4_ Net-_U38-Pad4_ Net-_U46-Pad4_ nor_thre +U47 Net-_U45-Pad1_ Net-_U42-Pad4_ Net-_U39-Pad4_ Net-_U41-Pad4_ Net-_U47-Pad5_ nor_four +U49 Net-_U45-Pad1_ Net-_U30-Pad2_ ? Net-_U49-Pad4_ nor_thre +U50 Net-_U45-Pad1_ Net-_U37-Pad3_ Net-_U42-Pad4_ Net-_U44-Pad5_ Net-_U50-Pad5_ nor_four +U52 Net-_U45-Pad1_ Net-_U42-Pad4_ Net-_U44-Pad5_ Net-_U43-Pad5_ Net-_U52-Pad5_ nor_four + +.end diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4511B/CD4511B.cir.out b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4511B/CD4511B.cir.out new file mode 100644 index 000000000..7c5c43595 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4511B/CD4511B.cir.out @@ -0,0 +1,330 @@ +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\cd4511b\cd4511b.cir + +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m3 net-_m3-pad1_ net-_m3-pad2_ net-_m3-pad3_ gnd CMOSN W=100u L=100u M=1 +m7 net-_m3-pad3_ net-_m7-pad2_ net-_m3-pad1_ vcc CMOSP W=100u L=100u M=1 +* u26 net-_m3-pad3_ net-_u26-pad2_ adc_bridge_1 +* u22 net-_u11-pad2_ net-_m7-pad2_ dac_bridge_1 +* u14 net-_u14-pad1_ net-_m3-pad1_ dac_bridge_1 +* u9 net-_u4-pad2_ net-_u14-pad1_ d_inverter +* u4 net-_u106-pad7_ net-_u4-pad2_ adc_bridge_1 +* u30 net-_u26-pad2_ net-_u30-pad2_ d_inverter +* u33 net-_u30-pad2_ net-_u33-pad2_ d_inverter +* u18 net-_u11-pad1_ net-_m3-pad2_ dac_bridge_1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1 +m5 net-_m1-pad3_ net-_m5-pad2_ net-_m1-pad1_ vcc CMOSP W=100u L=100u M=1 +* u24 net-_m1-pad3_ net-_u24-pad2_ adc_bridge_1 +* u19 net-_u11-pad2_ net-_m5-pad2_ dac_bridge_1 +* u12 net-_u12-pad1_ net-_m1-pad1_ dac_bridge_1 +* u7 net-_u2-pad2_ net-_u12-pad1_ d_inverter +* u2 net-_u106-pad1_ net-_u2-pad2_ adc_bridge_1 +* u28 net-_u24-pad2_ net-_u28-pad2_ d_inverter +* u32 net-_u28-pad2_ net-_u32-pad2_ d_inverter +* u16 net-_u11-pad1_ net-_m1-pad2_ dac_bridge_1 +m4 net-_m4-pad1_ net-_m4-pad2_ net-_m4-pad3_ gnd CMOSN W=100u L=100u M=1 +m8 net-_m4-pad3_ net-_m8-pad2_ net-_m4-pad1_ vcc CMOSP W=100u L=100u M=1 +* u27 net-_m4-pad3_ net-_u27-pad2_ adc_bridge_1 +* u23 net-_u11-pad2_ net-_m8-pad2_ dac_bridge_1 +* u15 net-_u10-pad2_ net-_m4-pad1_ dac_bridge_1 +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u5 net-_u106-pad2_ net-_u10-pad1_ adc_bridge_1 +* u31 net-_u27-pad2_ net-_u31-pad2_ d_inverter +* u34 net-_u31-pad2_ net-_u34-pad2_ d_inverter +* u20 net-_u11-pad1_ net-_m4-pad2_ dac_bridge_1 +m2 net-_m2-pad1_ net-_m2-pad2_ net-_m2-pad3_ gnd CMOSN W=100u L=100u M=1 +m6 net-_m2-pad3_ net-_m6-pad2_ net-_m2-pad1_ vcc CMOSP W=100u L=100u M=1 +* u25 net-_m2-pad3_ net-_u25-pad2_ adc_bridge_1 +* u21 net-_u11-pad2_ net-_m6-pad2_ dac_bridge_1 +* u13 net-_u13-pad1_ net-_m2-pad1_ dac_bridge_1 +* u8 net-_u3-pad2_ net-_u13-pad1_ d_inverter +* u3 net-_u106-pad6_ net-_u3-pad2_ adc_bridge_1 +* u29 net-_u25-pad2_ net-_u29-pad2_ d_inverter +* u17 net-_u11-pad1_ net-_m2-pad2_ dac_bridge_1 +* u35 net-_u34-pad2_ net-_u32-pad2_ net-_u35-pad3_ d_nand +* u51 net-_u35-pad3_ net-_u29-pad2_ net-_u51-pad3_ d_nand +* u63 net-_u48-pad2_ net-_u51-pad3_ net-_u45-pad1_ d_nand +* u37 net-_u32-pad2_ net-_u31-pad2_ net-_u37-pad3_ d_nor +* u6 net-_u1-pad2_ net-_u11-pad1_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ adc_bridge_1 +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +* u48 net-_u106-pad4_ net-_u48-pad2_ adc_bridge_1 +* u72 net-_u45-pad1_ net-_u40-pad4_ net-_u72-pad3_ d_nor +* u85 net-_u45-pad5_ net-_u83-pad2_ net-_u85-pad3_ d_nor +* u86 net-_u46-pad4_ net-_u83-pad2_ net-_u86-pad3_ d_nor +* u87 net-_u72-pad3_ net-_u83-pad2_ net-_u87-pad3_ d_nor +* u88 net-_u47-pad5_ net-_u83-pad2_ net-_u88-pad3_ d_nor +* u89 net-_u49-pad4_ net-_u83-pad2_ net-_u89-pad3_ d_nor +* u90 net-_u50-pad5_ net-_u83-pad2_ net-_u90-pad3_ d_nor +* u91 net-_u52-pad5_ net-_u83-pad2_ net-_u91-pad3_ d_nor +* u83 net-_u73-pad2_ net-_u83-pad2_ d_inverter +* u73 net-_u106-pad3_ net-_u73-pad2_ adc_bridge_1 +* u92 net-_u85-pad3_ net-_u92-pad2_ d_inverter +* u93 net-_u86-pad3_ net-_u100-pad1_ d_inverter +* u99 net-_u92-pad2_ net-_u106-pad13_ dac_bridge_1 +* u100 net-_u100-pad1_ net-_u100-pad2_ dac_bridge_1 +* u94 net-_u87-pad3_ net-_u101-pad1_ d_inverter +* u101 net-_u101-pad1_ net-_u101-pad2_ dac_bridge_1 +* u95 net-_u88-pad3_ net-_u102-pad1_ d_inverter +* u96 net-_u89-pad3_ net-_u103-pad1_ d_inverter +* u102 net-_u102-pad1_ net-_u102-pad2_ dac_bridge_1 +* u103 net-_u103-pad1_ net-_u103-pad2_ dac_bridge_1 +* u98 net-_u90-pad3_ net-_u105-pad1_ d_inverter +* u105 net-_u105-pad1_ net-_u105-pad2_ dac_bridge_1 +* u97 net-_u91-pad3_ net-_u104-pad1_ d_inverter +* u104 net-_u104-pad1_ net-_u104-pad2_ dac_bridge_1 +* u106 net-_u106-pad1_ net-_u106-pad2_ net-_u106-pad3_ net-_u106-pad4_ net-_u1-pad1_ net-_u106-pad6_ net-_u106-pad7_ gnd net-_u103-pad2_ net-_u102-pad2_ net-_u101-pad2_ net-_u100-pad2_ net-_u106-pad13_ net-_u104-pad2_ net-_u105-pad2_ vcc port +* u40 net-_u30-pad2_ net-_u32-pad2_ net-_u31-pad2_ net-_u40-pad4_ nor_thre +* u41 net-_u33-pad2_ net-_u28-pad2_ net-_u31-pad2_ net-_u41-pad4_ nor_thre +* u42 net-_u33-pad2_ net-_u32-pad2_ net-_u34-pad2_ net-_u42-pad4_ nor_thre +* u38 net-_u33-pad2_ net-_u28-pad2_ net-_u34-pad2_ net-_u38-pad4_ nor_thre +* u39 net-_u30-pad2_ net-_u34-pad2_ net-_u28-pad2_ net-_u39-pad4_ nor_thre +* u43 net-_u30-pad2_ net-_u28-pad2_ net-_u31-pad2_ net-_u29-pad2_ net-_u43-pad5_ nor_four +* u44 net-_u33-pad2_ net-_u28-pad2_ net-_u31-pad2_ net-_u29-pad2_ net-_u44-pad5_ nor_four +* u36 net-_u30-pad2_ net-_u32-pad2_ net-_u34-pad2_ net-_u36-pad4_ nor_thre +* u45 net-_u45-pad1_ net-_u36-pad4_ net-_u39-pad4_ net-_u44-pad5_ net-_u45-pad5_ nor_four +* u46 net-_u45-pad1_ net-_u36-pad4_ net-_u38-pad4_ net-_u46-pad4_ nor_thre +* u47 net-_u45-pad1_ net-_u42-pad4_ net-_u39-pad4_ net-_u41-pad4_ net-_u47-pad5_ nor_four +* u49 net-_u45-pad1_ net-_u30-pad2_ ? net-_u49-pad4_ nor_thre +* u50 net-_u45-pad1_ net-_u37-pad3_ net-_u42-pad4_ net-_u44-pad5_ net-_u50-pad5_ nor_four +* u52 net-_u45-pad1_ net-_u42-pad4_ net-_u44-pad5_ net-_u43-pad5_ net-_u52-pad5_ nor_four +a1 [net-_m3-pad3_ ] [net-_u26-pad2_ ] u26 +a2 [net-_u11-pad2_ ] [net-_m7-pad2_ ] u22 +a3 [net-_u14-pad1_ ] [net-_m3-pad1_ ] u14 +a4 net-_u4-pad2_ net-_u14-pad1_ u9 +a5 [net-_u106-pad7_ ] [net-_u4-pad2_ ] u4 +a6 net-_u26-pad2_ net-_u30-pad2_ u30 +a7 net-_u30-pad2_ net-_u33-pad2_ u33 +a8 [net-_u11-pad1_ ] [net-_m3-pad2_ ] u18 +a9 [net-_m1-pad3_ ] [net-_u24-pad2_ ] u24 +a10 [net-_u11-pad2_ ] [net-_m5-pad2_ ] u19 +a11 [net-_u12-pad1_ ] [net-_m1-pad1_ ] u12 +a12 net-_u2-pad2_ net-_u12-pad1_ u7 +a13 [net-_u106-pad1_ ] [net-_u2-pad2_ ] u2 +a14 net-_u24-pad2_ net-_u28-pad2_ u28 +a15 net-_u28-pad2_ net-_u32-pad2_ u32 +a16 [net-_u11-pad1_ ] [net-_m1-pad2_ ] u16 +a17 [net-_m4-pad3_ ] [net-_u27-pad2_ ] u27 +a18 [net-_u11-pad2_ ] [net-_m8-pad2_ ] u23 +a19 [net-_u10-pad2_ ] [net-_m4-pad1_ ] u15 +a20 net-_u10-pad1_ net-_u10-pad2_ u10 +a21 [net-_u106-pad2_ ] [net-_u10-pad1_ ] u5 +a22 net-_u27-pad2_ net-_u31-pad2_ u31 +a23 net-_u31-pad2_ net-_u34-pad2_ u34 +a24 [net-_u11-pad1_ ] [net-_m4-pad2_ ] u20 +a25 [net-_m2-pad3_ ] [net-_u25-pad2_ ] u25 +a26 [net-_u11-pad2_ ] [net-_m6-pad2_ ] u21 +a27 [net-_u13-pad1_ ] [net-_m2-pad1_ ] u13 +a28 net-_u3-pad2_ net-_u13-pad1_ u8 +a29 [net-_u106-pad6_ ] [net-_u3-pad2_ ] u3 +a30 net-_u25-pad2_ net-_u29-pad2_ u29 +a31 [net-_u11-pad1_ ] [net-_m2-pad2_ ] u17 +a32 [net-_u34-pad2_ net-_u32-pad2_ ] net-_u35-pad3_ u35 +a33 [net-_u35-pad3_ net-_u29-pad2_ ] net-_u51-pad3_ u51 +a34 [net-_u48-pad2_ net-_u51-pad3_ ] net-_u45-pad1_ u63 +a35 [net-_u32-pad2_ net-_u31-pad2_ ] net-_u37-pad3_ u37 +a36 net-_u1-pad2_ net-_u11-pad1_ u6 +a37 [net-_u1-pad1_ ] [net-_u1-pad2_ ] u1 +a38 net-_u11-pad1_ net-_u11-pad2_ u11 +a39 [net-_u106-pad4_ ] [net-_u48-pad2_ ] u48 +a40 [net-_u45-pad1_ net-_u40-pad4_ ] net-_u72-pad3_ u72 +a41 [net-_u45-pad5_ net-_u83-pad2_ ] net-_u85-pad3_ u85 +a42 [net-_u46-pad4_ net-_u83-pad2_ ] net-_u86-pad3_ u86 +a43 [net-_u72-pad3_ net-_u83-pad2_ ] net-_u87-pad3_ u87 +a44 [net-_u47-pad5_ net-_u83-pad2_ ] net-_u88-pad3_ u88 +a45 [net-_u49-pad4_ net-_u83-pad2_ ] net-_u89-pad3_ u89 +a46 [net-_u50-pad5_ net-_u83-pad2_ ] net-_u90-pad3_ u90 +a47 [net-_u52-pad5_ net-_u83-pad2_ ] net-_u91-pad3_ u91 +a48 net-_u73-pad2_ net-_u83-pad2_ u83 +a49 [net-_u106-pad3_ ] [net-_u73-pad2_ ] u73 +a50 net-_u85-pad3_ net-_u92-pad2_ u92 +a51 net-_u86-pad3_ net-_u100-pad1_ u93 +a52 [net-_u92-pad2_ ] [net-_u106-pad13_ ] u99 +a53 [net-_u100-pad1_ ] [net-_u100-pad2_ ] u100 +a54 net-_u87-pad3_ net-_u101-pad1_ u94 +a55 [net-_u101-pad1_ ] [net-_u101-pad2_ ] u101 +a56 net-_u88-pad3_ net-_u102-pad1_ u95 +a57 net-_u89-pad3_ net-_u103-pad1_ u96 +a58 [net-_u102-pad1_ ] [net-_u102-pad2_ ] u102 +a59 [net-_u103-pad1_ ] [net-_u103-pad2_ ] u103 +a60 net-_u90-pad3_ net-_u105-pad1_ u98 +a61 [net-_u105-pad1_ ] [net-_u105-pad2_ ] u105 +a62 net-_u91-pad3_ net-_u104-pad1_ u97 +a63 [net-_u104-pad1_ ] [net-_u104-pad2_ ] u104 +a64 [net-_u30-pad2_ ] [net-_u32-pad2_ ] [net-_u31-pad2_ ] [net-_u40-pad4_ ] u40 +a65 [net-_u33-pad2_ ] [net-_u28-pad2_ ] [net-_u31-pad2_ ] [net-_u41-pad4_ ] u41 +a66 [net-_u33-pad2_ ] [net-_u32-pad2_ ] [net-_u34-pad2_ ] [net-_u42-pad4_ ] u42 +a67 [net-_u33-pad2_ ] [net-_u28-pad2_ ] [net-_u34-pad2_ ] [net-_u38-pad4_ ] u38 +a68 [net-_u30-pad2_ ] [net-_u34-pad2_ ] [net-_u28-pad2_ ] [net-_u39-pad4_ ] u39 +a69 [net-_u30-pad2_ ] [net-_u28-pad2_ ] [net-_u31-pad2_ ] [net-_u29-pad2_ ] [net-_u43-pad5_ ] u43 +a70 [net-_u33-pad2_ ] [net-_u28-pad2_ ] [net-_u31-pad2_ ] [net-_u29-pad2_ ] [net-_u44-pad5_ ] u44 +a71 [net-_u30-pad2_ ] [net-_u32-pad2_ ] [net-_u34-pad2_ ] [net-_u36-pad4_ ] u36 +a72 [net-_u45-pad1_ ] [net-_u36-pad4_ ] [net-_u39-pad4_ ] [net-_u44-pad5_ ] [net-_u45-pad5_ ] u45 +a73 [net-_u45-pad1_ ] [net-_u36-pad4_ ] [net-_u38-pad4_ ] [net-_u46-pad4_ ] u46 +a74 [net-_u45-pad1_ ] [net-_u42-pad4_ ] [net-_u39-pad4_ ] [net-_u41-pad4_ ] [net-_u47-pad5_ ] u47 +a75 [net-_u45-pad1_ ] [net-_u30-pad2_ ] [? ] [net-_u49-pad4_ ] u49 +a76 [net-_u45-pad1_ ] [net-_u37-pad3_ ] [net-_u42-pad4_ ] [net-_u44-pad5_ ] [net-_u50-pad5_ ] u50 +a77 [net-_u45-pad1_ ] [net-_u42-pad4_ ] [net-_u44-pad5_ ] [net-_u43-pad5_ ] [net-_u52-pad5_ ] u52 +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u26 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u22 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u14 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u4 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u18 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u24 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u19 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u12 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u16 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u27 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u23 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u15 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u5 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u20 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u25 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u21 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u13 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u17 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u35 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u51 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u63 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u37 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u1 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u48 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u72 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u85 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u86 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u87 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u88 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u89 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u90 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u91 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u83 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u73 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u92 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u93 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u99 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u100 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u94 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u101 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u95 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u96 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u102 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u103 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u98 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u105 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u97 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u104 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: nor_thre, NgSpice Name: nor_thre +.model u40 nor_thre(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: nor_thre, NgSpice Name: nor_thre +.model u41 nor_thre(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: nor_thre, NgSpice Name: nor_thre +.model u42 nor_thre(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: nor_thre, NgSpice Name: nor_thre +.model u38 nor_thre(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: nor_thre, NgSpice Name: nor_thre +.model u39 nor_thre(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: nor_four, NgSpice Name: nor_four +.model u43 nor_four(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: nor_four, NgSpice Name: nor_four +.model u44 nor_four(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: nor_thre, NgSpice Name: nor_thre +.model u36 nor_thre(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: nor_four, NgSpice Name: nor_four +.model u45 nor_four(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: nor_thre, NgSpice Name: nor_thre +.model u46 nor_thre(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: nor_four, NgSpice Name: nor_four +.model u47 nor_four(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: nor_thre, NgSpice Name: nor_thre +.model u49 nor_thre(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: nor_four, NgSpice Name: nor_four +.model u50 nor_four(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: nor_four, NgSpice Name: nor_four +.model u52 nor_four(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4511B/CD4511B.pro b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4511B/CD4511B.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4511B/CD4511B.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4511B/CD4511B.sch b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4511B/CD4511B.sch new file mode 100644 index 000000000..3b4a47da9 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4511B/CD4511B.sch @@ -0,0 +1,1950 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:CD4511B-cache +EELAYER 25 0 +EELAYER END +$Descr A1 33110 23386 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L mosfet_n M3 +U 1 1 685CDD83 +P 9450 5300 +F 0 "M3" H 9450 5150 50 0000 R CNN +F 1 "mosfet_n" H 9550 5250 50 0000 R CNN +F 2 "" H 9750 5000 29 0000 C CNN +F 3 "" H 9550 5100 60 0000 C CNN + 1 9450 5300 + 0 -1 -1 0 +$EndComp +$Comp +L mosfet_p M7 +U 1 1 685CDDD0 +P 9650 4650 +F 0 "M7" H 9600 4700 50 0000 R CNN +F 1 "mosfet_p" H 9700 4800 50 0000 R CNN +F 2 "" H 9900 4750 29 0000 C CNN +F 3 "" H 9700 4650 60 0000 C CNN + 1 9650 4650 + 0 1 1 0 +$EndComp +Text GLabel 1200 950 0 60 Input ~ 0 +VCC +Text GLabel 1200 700 0 60 Input ~ 0 +GND +Text GLabel 9900 5150 3 60 Input ~ 0 +GND +Text GLabel 9850 4750 1 60 Input ~ 0 +VCC +$Comp +L adc_bridge_1 U26 +U 1 1 685CDF31 +P 10600 5000 +F 0 "U26" H 10600 5000 60 0000 C CNN +F 1 "adc_bridge_1" H 10600 5150 60 0000 C CNN +F 2 "" H 10600 5000 60 0000 C CNN +F 3 "" H 10600 5000 60 0000 C CNN + 1 10600 5000 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U22 +U 1 1 685CDF5C +P 10350 4400 +F 0 "U22" H 10350 4400 60 0000 C CNN +F 1 "dac_bridge_1" H 10350 4550 60 0000 C CNN +F 2 "" H 10350 4400 60 0000 C CNN +F 3 "" H 10350 4400 60 0000 C CNN + 1 10350 4400 + -1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U14 +U 1 1 685CE054 +P 8700 5000 +F 0 "U14" H 8700 5000 60 0000 C CNN +F 1 "dac_bridge_1" H 8700 5150 60 0000 C CNN +F 2 "" H 8700 5000 60 0000 C CNN +F 3 "" H 8700 5000 60 0000 C CNN + 1 8700 5000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U9 +U 1 1 685CE25D +P 7750 4950 +F 0 "U9" H 7750 4850 60 0000 C CNN +F 1 "d_inverter" H 7750 5100 60 0000 C CNN +F 2 "" H 7800 4900 60 0000 C CNN +F 3 "" H 7800 4900 60 0000 C CNN + 1 7750 4950 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_1 U4 +U 1 1 685CE2B0 +P 6800 5000 +F 0 "U4" H 6800 5000 60 0000 C CNN +F 1 "adc_bridge_1" H 6800 5150 60 0000 C CNN +F 2 "" H 6800 5000 60 0000 C CNN +F 3 "" H 6800 5000 60 0000 C CNN + 1 6800 5000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U30 +U 1 1 685CE40A +P 11600 4950 +F 0 "U30" H 11600 4850 60 0000 C CNN +F 1 "d_inverter" H 11600 5100 60 0000 C CNN +F 2 "" H 11650 4900 60 0000 C CNN +F 3 "" H 11650 4900 60 0000 C CNN + 1 11600 4950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U33 +U 1 1 685CE4C2 +P 12350 4950 +F 0 "U33" H 12350 4850 60 0000 C CNN +F 1 "d_inverter" H 12350 5100 60 0000 C CNN +F 2 "" H 12400 4900 60 0000 C CNN +F 3 "" H 12400 4900 60 0000 C CNN + 1 12350 4950 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U18 +U 1 1 685CE74D +P 10200 5650 +F 0 "U18" H 10200 5650 60 0000 C CNN +F 1 "dac_bridge_1" H 10200 5800 60 0000 C CNN +F 2 "" H 10200 5650 60 0000 C CNN +F 3 "" H 10200 5650 60 0000 C CNN + 1 10200 5650 + -1 0 0 -1 +$EndComp +$Comp +L mosfet_n M1 +U 1 1 685CEB0B +P 9300 8650 +F 0 "M1" H 9300 8500 50 0000 R CNN +F 1 "mosfet_n" H 9400 8600 50 0000 R CNN +F 2 "" H 9600 8350 29 0000 C CNN +F 3 "" H 9400 8450 60 0000 C CNN + 1 9300 8650 + 0 -1 -1 0 +$EndComp +$Comp +L mosfet_p M5 +U 1 1 685CEB11 +P 9500 8000 +F 0 "M5" H 9450 8050 50 0000 R CNN +F 1 "mosfet_p" H 9550 8150 50 0000 R CNN +F 2 "" H 9750 8100 29 0000 C CNN +F 3 "" H 9550 8000 60 0000 C CNN + 1 9500 8000 + 0 1 1 0 +$EndComp +Text GLabel 9750 8500 3 60 Input ~ 0 +GND +Text GLabel 9700 8100 1 60 Input ~ 0 +VCC +$Comp +L adc_bridge_1 U24 +U 1 1 685CEB23 +P 10450 8350 +F 0 "U24" H 10450 8350 60 0000 C CNN +F 1 "adc_bridge_1" H 10450 8500 60 0000 C CNN +F 2 "" H 10450 8350 60 0000 C CNN +F 3 "" H 10450 8350 60 0000 C CNN + 1 10450 8350 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U19 +U 1 1 685CEB29 +P 10200 7750 +F 0 "U19" H 10200 7750 60 0000 C CNN +F 1 "dac_bridge_1" H 10200 7900 60 0000 C CNN +F 2 "" H 10200 7750 60 0000 C CNN +F 3 "" H 10200 7750 60 0000 C CNN + 1 10200 7750 + -1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U12 +U 1 1 685CEB2F +P 8550 8350 +F 0 "U12" H 8550 8350 60 0000 C CNN +F 1 "dac_bridge_1" H 8550 8500 60 0000 C CNN +F 2 "" H 8550 8350 60 0000 C CNN +F 3 "" H 8550 8350 60 0000 C CNN + 1 8550 8350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 685CEB3C +P 7600 8300 +F 0 "U7" H 7600 8200 60 0000 C CNN +F 1 "d_inverter" H 7600 8450 60 0000 C CNN +F 2 "" H 7650 8250 60 0000 C CNN +F 3 "" H 7650 8250 60 0000 C CNN + 1 7600 8300 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_1 U2 +U 1 1 685CEB42 +P 6650 8350 +F 0 "U2" H 6650 8350 60 0000 C CNN +F 1 "adc_bridge_1" H 6650 8500 60 0000 C CNN +F 2 "" H 6650 8350 60 0000 C CNN +F 3 "" H 6650 8350 60 0000 C CNN + 1 6650 8350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U28 +U 1 1 685CEB4A +P 11450 8300 +F 0 "U28" H 11450 8200 60 0000 C CNN +F 1 "d_inverter" H 11450 8450 60 0000 C CNN +F 2 "" H 11500 8250 60 0000 C CNN +F 3 "" H 11500 8250 60 0000 C CNN + 1 11450 8300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U32 +U 1 1 685CEB50 +P 12200 8300 +F 0 "U32" H 12200 8200 60 0000 C CNN +F 1 "d_inverter" H 12200 8450 60 0000 C CNN +F 2 "" H 12250 8250 60 0000 C CNN +F 3 "" H 12250 8250 60 0000 C CNN + 1 12200 8300 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U16 +U 1 1 685CEB58 +P 10050 9000 +F 0 "U16" H 10050 9000 60 0000 C CNN +F 1 "dac_bridge_1" H 10050 9150 60 0000 C CNN +F 2 "" H 10050 9000 60 0000 C CNN +F 3 "" H 10050 9000 60 0000 C CNN + 1 10050 9000 + -1 0 0 -1 +$EndComp +$Comp +L mosfet_n M4 +U 1 1 685CF4F2 +P 9450 11800 +F 0 "M4" H 9450 11650 50 0000 R CNN +F 1 "mosfet_n" H 9550 11750 50 0000 R CNN +F 2 "" H 9750 11500 29 0000 C CNN +F 3 "" H 9550 11600 60 0000 C CNN + 1 9450 11800 + 0 -1 -1 0 +$EndComp +$Comp +L mosfet_p M8 +U 1 1 685CF4F8 +P 9650 11150 +F 0 "M8" H 9600 11200 50 0000 R CNN +F 1 "mosfet_p" H 9700 11300 50 0000 R CNN +F 2 "" H 9900 11250 29 0000 C CNN +F 3 "" H 9700 11150 60 0000 C CNN + 1 9650 11150 + 0 1 1 0 +$EndComp +Text GLabel 9900 11650 3 60 Input ~ 0 +GND +Text GLabel 9850 11250 1 60 Input ~ 0 +VCC +$Comp +L adc_bridge_1 U27 +U 1 1 685CF50A +P 10600 11500 +F 0 "U27" H 10600 11500 60 0000 C CNN +F 1 "adc_bridge_1" H 10600 11650 60 0000 C CNN +F 2 "" H 10600 11500 60 0000 C CNN +F 3 "" H 10600 11500 60 0000 C CNN + 1 10600 11500 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U23 +U 1 1 685CF510 +P 10350 10900 +F 0 "U23" H 10350 10900 60 0000 C CNN +F 1 "dac_bridge_1" H 10350 11050 60 0000 C CNN +F 2 "" H 10350 10900 60 0000 C CNN +F 3 "" H 10350 10900 60 0000 C CNN + 1 10350 10900 + -1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U15 +U 1 1 685CF516 +P 8700 11500 +F 0 "U15" H 8700 11500 60 0000 C CNN +F 1 "dac_bridge_1" H 8700 11650 60 0000 C CNN +F 2 "" H 8700 11500 60 0000 C CNN +F 3 "" H 8700 11500 60 0000 C CNN + 1 8700 11500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U10 +U 1 1 685CF523 +P 7750 11450 +F 0 "U10" H 7750 11350 60 0000 C CNN +F 1 "d_inverter" H 7750 11600 60 0000 C CNN +F 2 "" H 7800 11400 60 0000 C CNN +F 3 "" H 7800 11400 60 0000 C CNN + 1 7750 11450 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_1 U5 +U 1 1 685CF529 +P 6800 11500 +F 0 "U5" H 6800 11500 60 0000 C CNN +F 1 "adc_bridge_1" H 6800 11650 60 0000 C CNN +F 2 "" H 6800 11500 60 0000 C CNN +F 3 "" H 6800 11500 60 0000 C CNN + 1 6800 11500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U31 +U 1 1 685CF531 +P 11600 11450 +F 0 "U31" H 11600 11350 60 0000 C CNN +F 1 "d_inverter" H 11600 11600 60 0000 C CNN +F 2 "" H 11650 11400 60 0000 C CNN +F 3 "" H 11650 11400 60 0000 C CNN + 1 11600 11450 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U34 +U 1 1 685CF537 +P 12350 11450 +F 0 "U34" H 12350 11350 60 0000 C CNN +F 1 "d_inverter" H 12350 11600 60 0000 C CNN +F 2 "" H 12400 11400 60 0000 C CNN +F 3 "" H 12400 11400 60 0000 C CNN + 1 12350 11450 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U20 +U 1 1 685CF53F +P 10200 12150 +F 0 "U20" H 10200 12150 60 0000 C CNN +F 1 "dac_bridge_1" H 10200 12300 60 0000 C CNN +F 2 "" H 10200 12150 60 0000 C CNN +F 3 "" H 10200 12150 60 0000 C CNN + 1 10200 12150 + -1 0 0 -1 +$EndComp +$Comp +L mosfet_n M2 +U 1 1 685CF545 +P 9300 15150 +F 0 "M2" H 9300 15000 50 0000 R CNN +F 1 "mosfet_n" H 9400 15100 50 0000 R CNN +F 2 "" H 9600 14850 29 0000 C CNN +F 3 "" H 9400 14950 60 0000 C CNN + 1 9300 15150 + 0 -1 -1 0 +$EndComp +$Comp +L mosfet_p M6 +U 1 1 685CF54B +P 9500 14500 +F 0 "M6" H 9450 14550 50 0000 R CNN +F 1 "mosfet_p" H 9550 14650 50 0000 R CNN +F 2 "" H 9750 14600 29 0000 C CNN +F 3 "" H 9550 14500 60 0000 C CNN + 1 9500 14500 + 0 1 1 0 +$EndComp +Text GLabel 9750 15000 3 60 Input ~ 0 +GND +Text GLabel 9700 14600 1 60 Input ~ 0 +VCC +$Comp +L adc_bridge_1 U25 +U 1 1 685CF55D +P 10450 14850 +F 0 "U25" H 10450 14850 60 0000 C CNN +F 1 "adc_bridge_1" H 10450 15000 60 0000 C CNN +F 2 "" H 10450 14850 60 0000 C CNN +F 3 "" H 10450 14850 60 0000 C CNN + 1 10450 14850 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U21 +U 1 1 685CF563 +P 10200 14250 +F 0 "U21" H 10200 14250 60 0000 C CNN +F 1 "dac_bridge_1" H 10200 14400 60 0000 C CNN +F 2 "" H 10200 14250 60 0000 C CNN +F 3 "" H 10200 14250 60 0000 C CNN + 1 10200 14250 + -1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U13 +U 1 1 685CF569 +P 8550 14850 +F 0 "U13" H 8550 14850 60 0000 C CNN +F 1 "dac_bridge_1" H 8550 15000 60 0000 C CNN +F 2 "" H 8550 14850 60 0000 C CNN +F 3 "" H 8550 14850 60 0000 C CNN + 1 8550 14850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U8 +U 1 1 685CF576 +P 7600 14800 +F 0 "U8" H 7600 14700 60 0000 C CNN +F 1 "d_inverter" H 7600 14950 60 0000 C CNN +F 2 "" H 7650 14750 60 0000 C CNN +F 3 "" H 7650 14750 60 0000 C CNN + 1 7600 14800 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_1 U3 +U 1 1 685CF57C +P 6650 14850 +F 0 "U3" H 6650 14850 60 0000 C CNN +F 1 "adc_bridge_1" H 6650 15000 60 0000 C CNN +F 2 "" H 6650 14850 60 0000 C CNN +F 3 "" H 6650 14850 60 0000 C CNN + 1 6650 14850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U29 +U 1 1 685CF584 +P 11450 14800 +F 0 "U29" H 11450 14700 60 0000 C CNN +F 1 "d_inverter" H 11450 14950 60 0000 C CNN +F 2 "" H 11500 14750 60 0000 C CNN +F 3 "" H 11500 14750 60 0000 C CNN + 1 11450 14800 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U17 +U 1 1 685CF592 +P 10050 15500 +F 0 "U17" H 10050 15500 60 0000 C CNN +F 1 "dac_bridge_1" H 10050 15650 60 0000 C CNN +F 2 "" H 10050 15500 60 0000 C CNN +F 3 "" H 10050 15500 60 0000 C CNN + 1 10050 15500 + -1 0 0 -1 +$EndComp +$Comp +L d_nand U35 +U 1 1 685D0512 +P 15100 4100 +F 0 "U35" H 15100 4100 60 0000 C CNN +F 1 "d_nand" H 15150 4200 60 0000 C CNN +F 2 "" H 15100 4100 60 0000 C CNN +F 3 "" H 15100 4100 60 0000 C CNN + 1 15100 4100 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U51 +U 1 1 685D0787 +P 16100 4150 +F 0 "U51" H 16100 4150 60 0000 C CNN +F 1 "d_nand" H 16150 4250 60 0000 C CNN +F 2 "" H 16100 4150 60 0000 C CNN +F 3 "" H 16100 4150 60 0000 C CNN + 1 16100 4150 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U63 +U 1 1 685D0829 +P 17100 4100 +F 0 "U63" H 17100 4100 60 0000 C CNN +F 1 "d_nand" H 17150 4200 60 0000 C CNN +F 2 "" H 17100 4100 60 0000 C CNN +F 3 "" H 17100 4100 60 0000 C CNN + 1 17100 4100 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U37 +U 1 1 685D08F7 +P 15350 5000 +F 0 "U37" H 15350 5000 60 0000 C CNN +F 1 "d_nor" H 15400 5100 60 0000 C CNN +F 2 "" H 15350 5000 60 0000 C CNN +F 3 "" H 15350 5000 60 0000 C CNN + 1 15350 5000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9450 4800 9350 4800 +Wire Wire Line + 9350 4800 9350 5100 +Wire Wire Line + 9350 5100 9450 5100 +Wire Wire Line + 9850 4800 9950 4800 +Wire Wire Line + 9950 4800 9950 5100 +Wire Wire Line + 9950 5100 9850 5100 +Wire Wire Line + 9800 5000 9900 5000 +Wire Wire Line + 9900 5000 9900 5150 +Wire Wire Line + 9850 4750 9850 4900 +Wire Wire Line + 9850 4900 9800 4900 +Wire Wire Line + 9650 4500 9650 4350 +Wire Wire Line + 9650 4350 9800 4350 +Wire Wire Line + 10000 4950 9950 4950 +Connection ~ 9950 4950 +Wire Wire Line + 9250 4950 9350 4950 +Connection ~ 9350 4950 +Wire Wire Line + 9650 5400 9650 5600 +Wire Wire Line + 7350 4950 7450 4950 +Wire Wire Line + 8050 4950 8100 4950 +Wire Wire Line + 11900 4950 12050 4950 +Wire Wire Line + 11150 4950 11300 4950 +Wire Wire Line + 9300 8150 9200 8150 +Wire Wire Line + 9200 8150 9200 8450 +Wire Wire Line + 9200 8450 9300 8450 +Wire Wire Line + 9700 8150 9800 8150 +Wire Wire Line + 9800 8150 9800 8450 +Wire Wire Line + 9800 8450 9700 8450 +Wire Wire Line + 9650 8350 9750 8350 +Wire Wire Line + 9750 8350 9750 8500 +Wire Wire Line + 9700 8100 9700 8250 +Wire Wire Line + 9700 8250 9650 8250 +Wire Wire Line + 9500 7850 9500 7700 +Wire Wire Line + 9500 7700 9650 7700 +Wire Wire Line + 9850 8300 9800 8300 +Connection ~ 9800 8300 +Wire Wire Line + 9100 8300 9200 8300 +Connection ~ 9200 8300 +Wire Wire Line + 9500 8750 9500 8950 +Wire Wire Line + 7200 8300 7300 8300 +Wire Wire Line + 7900 8300 7950 8300 +Wire Wire Line + 11750 8300 11900 8300 +Wire Wire Line + 11000 8300 11150 8300 +Wire Wire Line + 9450 11300 9350 11300 +Wire Wire Line + 9350 11300 9350 11600 +Wire Wire Line + 9350 11600 9450 11600 +Wire Wire Line + 9850 11300 9950 11300 +Wire Wire Line + 9950 11300 9950 11600 +Wire Wire Line + 9950 11600 9850 11600 +Wire Wire Line + 9800 11500 9900 11500 +Wire Wire Line + 9900 11500 9900 11650 +Wire Wire Line + 9850 11250 9850 11400 +Wire Wire Line + 9850 11400 9800 11400 +Wire Wire Line + 9650 11000 9650 10850 +Wire Wire Line + 9650 10850 9800 10850 +Wire Wire Line + 10000 11450 9950 11450 +Connection ~ 9950 11450 +Wire Wire Line + 9250 11450 9350 11450 +Connection ~ 9350 11450 +Wire Wire Line + 9650 11900 9650 12100 +Wire Wire Line + 7350 11450 7450 11450 +Wire Wire Line + 8050 11450 8100 11450 +Wire Wire Line + 11900 11450 12050 11450 +Wire Wire Line + 11150 11450 11300 11450 +Wire Wire Line + 9300 14650 9200 14650 +Wire Wire Line + 9200 14650 9200 14950 +Wire Wire Line + 9200 14950 9300 14950 +Wire Wire Line + 9700 14650 9800 14650 +Wire Wire Line + 9800 14650 9800 14950 +Wire Wire Line + 9800 14950 9700 14950 +Wire Wire Line + 9650 14850 9750 14850 +Wire Wire Line + 9750 14850 9750 15000 +Wire Wire Line + 9700 14600 9700 14750 +Wire Wire Line + 9700 14750 9650 14750 +Wire Wire Line + 9500 14350 9500 14200 +Wire Wire Line + 9500 14200 9650 14200 +Wire Wire Line + 9850 14800 9800 14800 +Connection ~ 9800 14800 +Wire Wire Line + 9100 14800 9200 14800 +Connection ~ 9200 14800 +Wire Wire Line + 9500 15250 9500 15450 +Wire Wire Line + 7200 14800 7300 14800 +Wire Wire Line + 7900 14800 7950 14800 +Wire Wire Line + 11000 14800 11150 14800 +Wire Wire Line + 12650 4950 14150 4950 +Wire Wire Line + 14150 4950 14150 16000 +Wire Wire Line + 14150 16000 15600 16000 +Wire Wire Line + 14850 6000 14150 6000 +Connection ~ 14150 6000 +Wire Wire Line + 14150 9350 15000 9350 +Connection ~ 14150 9350 +Wire Wire Line + 15250 14600 14150 14600 +Connection ~ 14150 14600 +Wire Wire Line + 11950 4950 11950 5450 +Wire Wire Line + 11950 5450 14550 5450 +Wire Wire Line + 14550 5350 14550 17300 +Wire Wire Line + 14550 17300 15400 17300 +Connection ~ 11950 4950 +Wire Wire Line + 14550 5350 18400 5350 +Connection ~ 14550 5450 +Wire Wire Line + 14900 7700 14550 7700 +Connection ~ 14550 7700 +Wire Wire Line + 15000 11150 14550 11150 +Connection ~ 14550 11150 +Wire Wire Line + 15050 12700 14550 12700 +Connection ~ 14550 12700 +Wire Wire Line + 12500 8300 13650 8300 +Wire Wire Line + 13650 4100 13650 12800 +Wire Wire Line + 13650 4100 14650 4100 +Connection ~ 13650 8300 +Wire Wire Line + 14900 4900 13650 4900 +Connection ~ 13650 4900 +Wire Wire Line + 13650 6100 14950 6100 +Connection ~ 13650 6100 +Wire Wire Line + 14900 7800 13650 7800 +Connection ~ 13650 7800 +Wire Wire Line + 11800 8300 11800 8550 +Wire Wire Line + 11800 8550 13350 8550 +Wire Wire Line + 13350 8550 13350 17400 +Wire Wire Line + 13350 17400 15400 17400 +Connection ~ 11800 8300 +Wire Wire Line + 15300 16100 13350 16100 +Connection ~ 13350 16100 +Wire Wire Line + 15250 14700 13350 14700 +Connection ~ 13350 14700 +Wire Wire Line + 13350 9450 15000 9450 +Connection ~ 13350 9450 +Connection ~ 13350 11600 +Wire Wire Line + 13650 12800 15050 12800 +Wire Wire Line + 15000 11250 12800 11250 +Wire Wire Line + 12800 11250 12800 11450 +Wire Wire Line + 12800 11450 12650 11450 +Wire Wire Line + 13000 11250 13000 4000 +Wire Wire Line + 13000 4000 14650 4000 +Connection ~ 13000 11250 +Wire Wire Line + 15500 6450 13000 6450 +Connection ~ 13000 6450 +Connection ~ 13000 8150 +Connection ~ 13000 9800 +Wire Wire Line + 12000 11450 12000 11850 +Wire Wire Line + 12000 11850 13200 11850 +Wire Wire Line + 13000 11850 13000 17700 +Wire Wire Line + 13000 17700 15400 17700 +Connection ~ 12000 11450 +Wire Wire Line + 13200 11850 13200 5000 +Wire Wire Line + 13200 5000 14900 5000 +Wire Wire Line + 15300 16400 13000 16400 +Connection ~ 13000 16400 +Connection ~ 13000 15050 +Connection ~ 13000 13150 +Connection ~ 13000 11850 +Wire Wire Line + 12500 17800 15400 17800 +Wire Wire Line + 15550 4050 15650 4050 +Wire Wire Line + 15650 4150 15500 4150 +Wire Wire Line + 15500 4150 15500 4250 +Wire Wire Line + 15500 4250 12750 4250 +Wire Wire Line + 12750 4250 12750 15000 +Wire Wire Line + 12750 15000 11850 15000 +Wire Wire Line + 11850 15000 11850 14800 +Wire Wire Line + 12500 15000 12500 17800 +Connection ~ 12500 15000 +Wire Wire Line + 12500 16500 15600 16500 +Connection ~ 12500 16500 +$Comp +L d_inverter U6 +U 1 1 685EA1D9 +P 7550 17450 +F 0 "U6" H 7550 17350 60 0000 C CNN +F 1 "d_inverter" H 7550 17600 60 0000 C CNN +F 2 "" H 7600 17400 60 0000 C CNN +F 3 "" H 7600 17400 60 0000 C CNN + 1 7550 17450 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_1 U1 +U 1 1 685EA758 +P 6600 17500 +F 0 "U1" H 6600 17500 60 0000 C CNN +F 1 "adc_bridge_1" H 6600 17650 60 0000 C CNN +F 2 "" H 6600 17500 60 0000 C CNN +F 3 "" H 6600 17500 60 0000 C CNN + 1 6600 17500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U11 +U 1 1 685EB11C +P 8300 17450 +F 0 "U11" H 8300 17350 60 0000 C CNN +F 1 "d_inverter" H 8300 17600 60 0000 C CNN +F 2 "" H 8350 17400 60 0000 C CNN +F 3 "" H 8350 17400 60 0000 C CNN + 1 8300 17450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7850 17450 8000 17450 +Wire Wire Line + 7150 17450 7250 17450 +Wire Wire Line + 7900 17450 7900 5950 +Wire Wire Line + 7900 5950 10800 5950 +Wire Wire Line + 10800 5950 10800 5600 +Connection ~ 7900 17450 +Wire Wire Line + 10650 15450 10750 15450 +Wire Wire Line + 10750 15450 10750 16000 +Wire Wire Line + 10750 16000 7900 16000 +Connection ~ 7900 16000 +Wire Wire Line + 10800 12100 10850 12100 +Wire Wire Line + 10850 12100 10850 12450 +Wire Wire Line + 10850 12450 7900 12450 +Connection ~ 7900 12450 +Wire Wire Line + 10650 8950 10700 8950 +Wire Wire Line + 10700 8950 10700 9350 +Wire Wire Line + 10700 9350 7900 9350 +Connection ~ 7900 9350 +Wire Wire Line + 11050 17450 8600 17450 +Wire Wire Line + 11050 4350 11050 17450 +Wire Wire Line + 11050 4350 10950 4350 +Wire Wire Line + 10800 7700 11050 7700 +Connection ~ 11050 7700 +Wire Wire Line + 10950 10850 11050 10850 +Connection ~ 11050 10850 +Wire Wire Line + 10800 14200 11050 14200 +Connection ~ 11050 14200 +Wire Wire Line + 11850 14800 11750 14800 +Wire Wire Line + 16550 4100 16650 4100 +$Comp +L adc_bridge_1 U48 +U 1 1 685F3784 +P 16000 3500 +F 0 "U48" H 16000 3500 60 0000 C CNN +F 1 "adc_bridge_1" H 16000 3650 60 0000 C CNN +F 2 "" H 16000 3500 60 0000 C CNN +F 3 "" H 16000 3500 60 0000 C CNN + 1 16000 3500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 16550 3450 16550 4000 +Wire Wire Line + 16550 4000 16650 4000 +Wire Wire Line + 15400 3450 15250 3450 +$Comp +L d_nor U72 +U 1 1 685F5F5A +P 19650 8650 +F 0 "U72" H 19650 8650 60 0000 C CNN +F 1 "d_nor" H 19700 8750 60 0000 C CNN +F 2 "" H 19650 8650 60 0000 C CNN +F 3 "" H 19650 8650 60 0000 C CNN + 1 19650 8650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 17550 4050 18650 4050 +Wire Wire Line + 18650 4050 18650 15300 +Wire Wire Line + 18650 15300 19800 15300 +Wire Wire Line + 18650 13450 19500 13450 +Connection ~ 18650 13450 +Wire Wire Line + 18650 11900 19350 11900 +Connection ~ 18650 11900 +Wire Wire Line + 18650 10000 19350 10000 +Connection ~ 18650 10000 +Wire Wire Line + 19200 8550 18650 8550 +Connection ~ 18650 8550 +Wire Wire Line + 18800 6750 18650 6750 +Connection ~ 18650 6750 +Wire Wire Line + 18650 5200 19150 5200 +Connection ~ 18650 5200 +Wire Wire Line + 18400 5350 18400 12000 +Wire Wire Line + 18400 12000 19350 12000 +Wire Wire Line + 15800 4950 18100 4950 +Wire Wire Line + 18100 4950 18100 13550 +Wire Wire Line + 18100 13550 19100 13550 +Wire Wire Line + 16400 6400 17900 6400 +Wire Wire Line + 17900 6400 17900 15400 +Wire Wire Line + 17900 15400 19400 15400 +Wire Wire Line + 19100 13850 17900 13850 +Connection ~ 17900 13850 +Wire Wire Line + 19150 10100 17900 10100 +Connection ~ 17900 10100 +Wire Wire Line + 16450 8100 17700 8100 +Wire Wire Line + 17700 8100 17700 5300 +Wire Wire Line + 17700 5300 19050 5300 +Wire Wire Line + 17700 6850 18900 6850 +Connection ~ 17700 6850 +Wire Wire Line + 16400 9750 17550 9750 +Wire Wire Line + 17550 9750 17550 7200 +Wire Wire Line + 17550 7200 19450 7200 +Wire Wire Line + 16400 11550 17350 11550 +Wire Wire Line + 17350 5600 17350 12350 +Wire Wire Line + 17350 5600 19150 5600 +Connection ~ 17350 11550 +Wire Wire Line + 19150 10400 17350 10400 +Connection ~ 17350 10400 +Wire Wire Line + 16450 13100 17150 13100 +Wire Wire Line + 17150 13100 17150 8650 +Wire Wire Line + 17150 8650 19200 8650 +Wire Wire Line + 16800 15000 18350 15000 +Wire Wire Line + 18350 15000 18350 10500 +Wire Wire Line + 18350 10500 19350 10500 +Wire Wire Line + 17150 16250 17600 16250 +Wire Wire Line + 17600 16250 17600 5700 +Wire Wire Line + 17600 5700 19150 5700 +Wire Wire Line + 19400 15700 17600 15700 +Connection ~ 17600 15700 +Wire Wire Line + 17600 13950 19500 13950 +Connection ~ 17600 13950 +Wire Wire Line + 19400 15800 19400 17550 +Wire Wire Line + 19400 17550 17250 17550 +$Comp +L d_nor U85 +U 1 1 68609E04 +P 21650 5550 +F 0 "U85" H 21650 5550 60 0000 C CNN +F 1 "d_nor" H 21700 5650 60 0000 C CNN +F 2 "" H 21650 5550 60 0000 C CNN +F 3 "" H 21650 5550 60 0000 C CNN + 1 21650 5550 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U86 +U 1 1 6860A29E +P 21650 6900 +F 0 "U86" H 21650 6900 60 0000 C CNN +F 1 "d_nor" H 21700 7000 60 0000 C CNN +F 2 "" H 21650 6900 60 0000 C CNN +F 3 "" H 21650 6900 60 0000 C CNN + 1 21650 6900 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U87 +U 1 1 6860A4F2 +P 21800 8700 +F 0 "U87" H 21800 8700 60 0000 C CNN +F 1 "d_nor" H 21850 8800 60 0000 C CNN +F 2 "" H 21800 8700 60 0000 C CNN +F 3 "" H 21800 8700 60 0000 C CNN + 1 21800 8700 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U88 +U 1 1 6860AB71 +P 21850 10350 +F 0 "U88" H 21850 10350 60 0000 C CNN +F 1 "d_nor" H 21900 10450 60 0000 C CNN +F 2 "" H 21850 10350 60 0000 C CNN +F 3 "" H 21850 10350 60 0000 C CNN + 1 21850 10350 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U89 +U 1 1 6860AD7F +P 22000 12050 +F 0 "U89" H 22000 12050 60 0000 C CNN +F 1 "d_nor" H 22050 12150 60 0000 C CNN +F 2 "" H 22000 12050 60 0000 C CNN +F 3 "" H 22000 12050 60 0000 C CNN + 1 22000 12050 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U90 +U 1 1 6860B12C +P 22000 13800 +F 0 "U90" H 22000 13800 60 0000 C CNN +F 1 "d_nor" H 22050 13900 60 0000 C CNN +F 2 "" H 22000 13800 60 0000 C CNN +F 3 "" H 22000 13800 60 0000 C CNN + 1 22000 13800 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U91 +U 1 1 6860B4D0 +P 22150 15650 +F 0 "U91" H 22150 15650 60 0000 C CNN +F 1 "d_nor" H 22200 15750 60 0000 C CNN +F 2 "" H 22150 15650 60 0000 C CNN +F 3 "" H 22150 15650 60 0000 C CNN + 1 22150 15650 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U83 +U 1 1 6860C43E +P 20650 18100 +F 0 "U83" H 20650 18000 60 0000 C CNN +F 1 "d_inverter" H 20650 18250 60 0000 C CNN +F 2 "" H 20700 18050 60 0000 C CNN +F 3 "" H 20700 18050 60 0000 C CNN + 1 20650 18100 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_1 U73 +U 1 1 6860CD1A +P 19700 18150 +F 0 "U73" H 19700 18150 60 0000 C CNN +F 1 "adc_bridge_1" H 19700 18300 60 0000 C CNN +F 2 "" H 19700 18150 60 0000 C CNN +F 3 "" H 19700 18150 60 0000 C CNN + 1 19700 18150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 20250 18100 20350 18100 +Wire Wire Line + 21400 18100 20950 18100 +Wire Wire Line + 21400 11450 21400 18100 +Wire Wire Line + 21400 11450 21100 11450 +Wire Wire Line + 21100 11450 21100 5550 +Wire Wire Line + 21100 5550 21200 5550 +Wire Wire Line + 20750 5450 21200 5450 +Wire Wire Line + 20350 7150 20950 7150 +Wire Wire Line + 20950 7150 20950 6800 +Wire Wire Line + 20950 6800 21200 6800 +Wire Wire Line + 21200 6900 21100 6900 +Connection ~ 21100 6900 +Wire Wire Line + 20100 8600 21350 8600 +Wire Wire Line + 21350 8700 21100 8700 +Connection ~ 21100 8700 +Wire Wire Line + 20750 10250 21400 10250 +Wire Wire Line + 21400 10350 21100 10350 +Connection ~ 21100 10350 +Wire Wire Line + 20600 12300 21050 12300 +Wire Wire Line + 21050 12300 21050 11950 +Wire Wire Line + 21050 11950 21550 11950 +Wire Wire Line + 21550 12050 21400 12050 +Connection ~ 21400 12050 +Wire Wire Line + 20900 13700 21550 13700 +Wire Wire Line + 21550 13800 21400 13800 +Connection ~ 21400 13800 +Wire Wire Line + 21250 15550 21700 15550 +Wire Wire Line + 21700 15650 21400 15650 +Connection ~ 21400 15650 +$Comp +L d_inverter U92 +U 1 1 686145B3 +P 23050 5500 +F 0 "U92" H 23050 5400 60 0000 C CNN +F 1 "d_inverter" H 23050 5650 60 0000 C CNN +F 2 "" H 23100 5450 60 0000 C CNN +F 3 "" H 23100 5450 60 0000 C CNN + 1 23050 5500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U93 +U 1 1 68614ED5 +P 23050 6850 +F 0 "U93" H 23050 6750 60 0000 C CNN +F 1 "d_inverter" H 23050 7000 60 0000 C CNN +F 2 "" H 23100 6800 60 0000 C CNN +F 3 "" H 23100 6800 60 0000 C CNN + 1 23050 6850 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U99 +U 1 1 68615FEA +P 24150 5550 +F 0 "U99" H 24150 5550 60 0000 C CNN +F 1 "dac_bridge_1" H 24150 5700 60 0000 C CNN +F 2 "" H 24150 5550 60 0000 C CNN +F 3 "" H 24150 5550 60 0000 C CNN + 1 24150 5550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 23350 5500 23550 5500 +$Comp +L dac_bridge_1 U100 +U 1 1 6861731B +P 24250 6900 +F 0 "U100" H 24250 6900 60 0000 C CNN +F 1 "dac_bridge_1" H 24250 7050 60 0000 C CNN +F 2 "" H 24250 6900 60 0000 C CNN +F 3 "" H 24250 6900 60 0000 C CNN + 1 24250 6900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 23350 6850 23650 6850 +$Comp +L d_inverter U94 +U 1 1 68617F18 +P 23100 8650 +F 0 "U94" H 23100 8550 60 0000 C CNN +F 1 "d_inverter" H 23100 8800 60 0000 C CNN +F 2 "" H 23150 8600 60 0000 C CNN +F 3 "" H 23150 8600 60 0000 C CNN + 1 23100 8650 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U101 +U 1 1 68617F1E +P 24300 8700 +F 0 "U101" H 24300 8700 60 0000 C CNN +F 1 "dac_bridge_1" H 24300 8850 60 0000 C CNN +F 2 "" H 24300 8700 60 0000 C CNN +F 3 "" H 24300 8700 60 0000 C CNN + 1 24300 8700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 23400 8650 23700 8650 +$Comp +L d_inverter U95 +U 1 1 6861829D +P 23350 10300 +F 0 "U95" H 23350 10200 60 0000 C CNN +F 1 "d_inverter" H 23350 10450 60 0000 C CNN +F 2 "" H 23400 10250 60 0000 C CNN +F 3 "" H 23400 10250 60 0000 C CNN + 1 23350 10300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U96 +U 1 1 686182A3 +P 23350 12000 +F 0 "U96" H 23350 11900 60 0000 C CNN +F 1 "d_inverter" H 23350 12150 60 0000 C CNN +F 2 "" H 23400 11950 60 0000 C CNN +F 3 "" H 23400 11950 60 0000 C CNN + 1 23350 12000 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U102 +U 1 1 686182A9 +P 24450 10350 +F 0 "U102" H 24450 10350 60 0000 C CNN +F 1 "dac_bridge_1" H 24450 10500 60 0000 C CNN +F 2 "" H 24450 10350 60 0000 C CNN +F 3 "" H 24450 10350 60 0000 C CNN + 1 24450 10350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 23650 10300 23850 10300 +$Comp +L dac_bridge_1 U103 +U 1 1 686182B0 +P 24550 12050 +F 0 "U103" H 24550 12050 60 0000 C CNN +F 1 "dac_bridge_1" H 24550 12200 60 0000 C CNN +F 2 "" H 24550 12050 60 0000 C CNN +F 3 "" H 24550 12050 60 0000 C CNN + 1 24550 12050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 23650 12000 23950 12000 +$Comp +L d_inverter U98 +U 1 1 686182B7 +P 23500 13750 +F 0 "U98" H 23500 13650 60 0000 C CNN +F 1 "d_inverter" H 23500 13900 60 0000 C CNN +F 2 "" H 23550 13700 60 0000 C CNN +F 3 "" H 23550 13700 60 0000 C CNN + 1 23500 13750 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U105 +U 1 1 686182BD +P 24700 13800 +F 0 "U105" H 24700 13800 60 0000 C CNN +F 1 "dac_bridge_1" H 24700 13950 60 0000 C CNN +F 2 "" H 24700 13800 60 0000 C CNN +F 3 "" H 24700 13800 60 0000 C CNN + 1 24700 13800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 23800 13750 24100 13750 +$Comp +L d_inverter U97 +U 1 1 686199B2 +P 23450 15600 +F 0 "U97" H 23450 15500 60 0000 C CNN +F 1 "d_inverter" H 23450 15750 60 0000 C CNN +F 2 "" H 23500 15550 60 0000 C CNN +F 3 "" H 23500 15550 60 0000 C CNN + 1 23450 15600 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U104 +U 1 1 686199B8 +P 24550 15650 +F 0 "U104" H 24550 15650 60 0000 C CNN +F 1 "dac_bridge_1" H 24550 15800 60 0000 C CNN +F 2 "" H 24550 15650 60 0000 C CNN +F 3 "" H 24550 15650 60 0000 C CNN + 1 24550 15650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 23750 15600 23950 15600 +Wire Wire Line + 22100 5500 22750 5500 +Wire Wire Line + 22100 6850 22750 6850 +Wire Wire Line + 22250 8650 22800 8650 +Wire Wire Line + 22300 10300 23050 10300 +Wire Wire Line + 22450 12000 23050 12000 +Wire Wire Line + 22450 13750 23200 13750 +Wire Wire Line + 22600 15600 23150 15600 +Wire Wire Line + 19100 18100 18950 18100 +Wire Wire Line + 25100 15600 25250 15600 +Wire Wire Line + 25250 13750 25350 13750 +Wire Wire Line + 25100 12000 25200 12000 +Wire Wire Line + 25000 10300 25150 10300 +Wire Wire Line + 24850 8650 25000 8650 +Wire Wire Line + 24800 6850 25000 6850 +Wire Wire Line + 24700 5500 24850 5500 +Wire Wire Line + 6200 4950 6100 4950 +Wire Wire Line + 6050 8300 5950 8300 +Wire Wire Line + 6200 11450 6050 11450 +Wire Wire Line + 6050 14800 5900 14800 +Wire Wire Line + 1200 700 1400 700 +Wire Wire Line + 1200 950 1400 950 +Wire Wire Line + 6000 17450 5850 17450 +$Comp +L PORT U106 +U 1 1 6862A46F +P 5700 8300 +F 0 "U106" H 5750 8400 30 0000 C CNN +F 1 "PORT" H 5700 8300 30 0000 C CNN +F 2 "" H 5700 8300 60 0000 C CNN +F 3 "" H 5700 8300 60 0000 C CNN + 1 5700 8300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U106 +U 2 1 6862A972 +P 5800 11450 +F 0 "U106" H 5850 11550 30 0000 C CNN +F 1 "PORT" H 5800 11450 30 0000 C CNN +F 2 "" H 5800 11450 60 0000 C CNN +F 3 "" H 5800 11450 60 0000 C CNN + 2 5800 11450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U106 +U 3 1 6862AA95 +P 18700 18100 +F 0 "U106" H 18750 18200 30 0000 C CNN +F 1 "PORT" H 18700 18100 30 0000 C CNN +F 2 "" H 18700 18100 60 0000 C CNN +F 3 "" H 18700 18100 60 0000 C CNN + 3 18700 18100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U106 +U 4 1 6862ABC0 +P 15000 3450 +F 0 "U106" H 15050 3550 30 0000 C CNN +F 1 "PORT" H 15000 3450 30 0000 C CNN +F 2 "" H 15000 3450 60 0000 C CNN +F 3 "" H 15000 3450 60 0000 C CNN + 4 15000 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U106 +U 5 1 6862ACE5 +P 5600 17450 +F 0 "U106" H 5650 17550 30 0000 C CNN +F 1 "PORT" H 5600 17450 30 0000 C CNN +F 2 "" H 5600 17450 60 0000 C CNN +F 3 "" H 5600 17450 60 0000 C CNN + 5 5600 17450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U106 +U 6 1 6862ADEA +P 5650 14800 +F 0 "U106" H 5700 14900 30 0000 C CNN +F 1 "PORT" H 5650 14800 30 0000 C CNN +F 2 "" H 5650 14800 60 0000 C CNN +F 3 "" H 5650 14800 60 0000 C CNN + 6 5650 14800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U106 +U 7 1 6862AE78 +P 5850 4950 +F 0 "U106" H 5900 5050 30 0000 C CNN +F 1 "PORT" H 5850 4950 30 0000 C CNN +F 2 "" H 5850 4950 60 0000 C CNN +F 3 "" H 5850 4950 60 0000 C CNN + 7 5850 4950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U106 +U 8 1 6862B4B1 +P 1650 700 +F 0 "U106" H 1700 800 30 0000 C CNN +F 1 "PORT" H 1650 700 30 0000 C CNN +F 2 "" H 1650 700 60 0000 C CNN +F 3 "" H 1650 700 60 0000 C CNN + 8 1650 700 + -1 0 0 1 +$EndComp +$Comp +L PORT U106 +U 9 1 6862B60C +P 25450 12000 +F 0 "U106" H 25500 12100 30 0000 C CNN +F 1 "PORT" H 25450 12000 30 0000 C CNN +F 2 "" H 25450 12000 60 0000 C CNN +F 3 "" H 25450 12000 60 0000 C CNN + 9 25450 12000 + -1 0 0 -1 +$EndComp +$Comp +L PORT U106 +U 10 1 6862B8A7 +P 25400 10300 +F 0 "U106" H 25450 10400 30 0000 C CNN +F 1 "PORT" H 25400 10300 30 0000 C CNN +F 2 "" H 25400 10300 60 0000 C CNN +F 3 "" H 25400 10300 60 0000 C CNN + 10 25400 10300 + -1 0 0 -1 +$EndComp +$Comp +L PORT U106 +U 11 1 6862BAB2 +P 25250 8650 +F 0 "U106" H 25300 8750 30 0000 C CNN +F 1 "PORT" H 25250 8650 30 0000 C CNN +F 2 "" H 25250 8650 60 0000 C CNN +F 3 "" H 25250 8650 60 0000 C CNN + 11 25250 8650 + -1 0 0 -1 +$EndComp +$Comp +L PORT U106 +U 12 1 6862BF27 +P 25250 6850 +F 0 "U106" H 25300 6950 30 0000 C CNN +F 1 "PORT" H 25250 6850 30 0000 C CNN +F 2 "" H 25250 6850 60 0000 C CNN +F 3 "" H 25250 6850 60 0000 C CNN + 12 25250 6850 + -1 0 0 -1 +$EndComp +$Comp +L PORT U106 +U 13 1 6862C046 +P 25100 5500 +F 0 "U106" H 25150 5600 30 0000 C CNN +F 1 "PORT" H 25100 5500 30 0000 C CNN +F 2 "" H 25100 5500 60 0000 C CNN +F 3 "" H 25100 5500 60 0000 C CNN + 13 25100 5500 + -1 0 0 -1 +$EndComp +$Comp +L PORT U106 +U 14 1 6862C3D1 +P 25500 15600 +F 0 "U106" H 25550 15700 30 0000 C CNN +F 1 "PORT" H 25500 15600 30 0000 C CNN +F 2 "" H 25500 15600 60 0000 C CNN +F 3 "" H 25500 15600 60 0000 C CNN + 14 25500 15600 + -1 0 0 -1 +$EndComp +$Comp +L PORT U106 +U 15 1 6862C9DC +P 25600 13750 +F 0 "U106" H 25650 13850 30 0000 C CNN +F 1 "PORT" H 25600 13750 30 0000 C CNN +F 2 "" H 25600 13750 60 0000 C CNN +F 3 "" H 25600 13750 60 0000 C CNN + 15 25600 13750 + -1 0 0 -1 +$EndComp +$Comp +L PORT U106 +U 16 1 6862CAFB +P 1650 950 +F 0 "U106" H 1700 1050 30 0000 C CNN +F 1 "PORT" H 1650 950 30 0000 C CNN +F 2 "" H 1650 950 60 0000 C CNN +F 3 "" H 1650 950 60 0000 C CNN + 16 1650 950 + -1 0 0 -1 +$EndComp +Wire Wire Line + 9500 4900 9500 4950 +Wire Wire Line + 9500 4950 9800 4950 +Wire Wire Line + 9800 4950 9800 4900 +Wire Wire Line + 9350 8250 9350 8300 +Wire Wire Line + 9350 8300 9650 8300 +Wire Wire Line + 9650 8300 9650 8250 +Wire Wire Line + 9500 11400 9500 11450 +Wire Wire Line + 9500 11450 9800 11450 +Wire Wire Line + 9800 11450 9800 11400 +Wire Wire Line + 9350 14750 9350 14800 +Wire Wire Line + 9350 14800 9650 14800 +Wire Wire Line + 9650 14800 9650 14750 +$Comp +L nor_thre U40 +U 1 1 6867F661 +P 12900 14600 +F 0 "U40" H 15750 16400 60 0000 C CNN +F 1 "nor_thre" H 15750 16600 60 0000 C CNN +F 2 "" H 15750 16550 60 0000 C CNN +F 3 "" H 15750 16550 60 0000 C CNN + 1 12900 14600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 15050 12900 15050 13150 +Wire Wire Line + 15050 13150 13000 13150 +Wire Wire Line + 16450 12700 16450 13100 +$Comp +L nor_thre U41 +U 1 1 68681AAA +P 13100 16500 +F 0 "U41" H 15950 18300 60 0000 C CNN +F 1 "nor_thre" H 15950 18500 60 0000 C CNN +F 2 "" H 15950 18450 60 0000 C CNN +F 3 "" H 15950 18450 60 0000 C CNN + 1 13100 16500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 13000 15050 15250 15050 +Wire Wire Line + 15250 15050 15250 14800 +Wire Wire Line + 16650 14600 16800 14600 +Wire Wire Line + 16800 14600 16800 15000 +$Comp +L nor_thre U42 +U 1 1 68684545 +P 13200 7800 +F 0 "U42" H 16050 9600 60 0000 C CNN +F 1 "nor_thre" H 16050 9800 60 0000 C CNN +F 2 "" H 16050 9750 60 0000 C CNN +F 3 "" H 16050 9750 60 0000 C CNN + 1 13200 7800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 14850 6000 14850 5900 +Wire Wire Line + 14850 5900 15350 5900 +Wire Wire Line + 15350 6000 14950 6000 +Wire Wire Line + 14950 6000 14950 6100 +Wire Wire Line + 15350 6100 15350 6300 +Wire Wire Line + 15350 6300 15500 6300 +Wire Wire Line + 15500 6300 15500 6450 +Wire Wire Line + 16750 5900 16750 6350 +Wire Wire Line + 16400 6400 16400 6350 +Wire Wire Line + 16400 6350 16750 6350 +$Comp +L nor_thre U38 +U 1 1 68686AD0 +P 12850 11250 +F 0 "U38" H 15700 13050 60 0000 C CNN +F 1 "nor_thre" H 15700 13250 60 0000 C CNN +F 2 "" H 15700 13200 60 0000 C CNN +F 3 "" H 15700 13200 60 0000 C CNN + 1 12850 11250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 16400 9350 16400 9750 +Wire Wire Line + 15000 9550 15000 9800 +Wire Wire Line + 15000 9800 13000 9800 +$Comp +L nor_thre U39 +U 1 1 68688561 +P 12850 13050 +F 0 "U39" H 15700 14850 60 0000 C CNN +F 1 "nor_thre" H 15700 15050 60 0000 C CNN +F 2 "" H 15700 15000 60 0000 C CNN +F 3 "" H 15700 15000 60 0000 C CNN + 1 12850 13050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 13350 11600 15000 11600 +Wire Wire Line + 15000 11600 15000 11350 +Wire Wire Line + 16400 11150 16400 11550 +$Comp +L nor_four U43 +U 1 1 6868952E +P 13250 19200 +F 0 "U43" H 16100 21000 60 0000 C CNN +F 1 "nor_four" H 16100 21200 60 0000 C CNN +F 2 "" H 16100 21150 60 0000 C CNN +F 3 "" H 16100 21150 60 0000 C CNN + 1 13250 19200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 15400 17500 15300 17500 +Wire Wire Line + 15300 17500 15300 17650 +Wire Wire Line + 15300 17650 15400 17650 +Wire Wire Line + 15400 17650 15400 17700 +Wire Wire Line + 15400 17600 15400 17550 +Wire Wire Line + 15400 17550 15250 17550 +Wire Wire Line + 15250 17550 15250 17750 +Wire Wire Line + 15250 17750 15400 17750 +Wire Wire Line + 15400 17750 15400 17800 +Wire Wire Line + 16800 17300 17250 17300 +Wire Wire Line + 17250 17300 17250 17550 +$Comp +L nor_four U44 +U 1 1 6868C0E3 +P 13450 18000 +F 0 "U44" H 16300 19800 60 0000 C CNN +F 1 "nor_four" H 16300 20000 60 0000 C CNN +F 2 "" H 16300 19950 60 0000 C CNN +F 3 "" H 16300 19950 60 0000 C CNN + 1 13450 18000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 17000 16100 17150 16100 +Wire Wire Line + 17150 16100 17150 16250 +Wire Wire Line + 15600 16000 15600 16100 +Wire Wire Line + 15300 16100 15300 16200 +Wire Wire Line + 15300 16200 15600 16200 +Wire Wire Line + 15600 16300 15300 16300 +Wire Wire Line + 15300 16300 15300 16400 +Wire Wire Line + 15600 16500 15600 16400 +$Comp +L nor_thre U36 +U 1 1 6868F9C1 +P 12750 9600 +F 0 "U36" H 15600 11400 60 0000 C CNN +F 1 "nor_thre" H 15600 11600 60 0000 C CNN +F 2 "" H 15600 11550 60 0000 C CNN +F 3 "" H 15600 11550 60 0000 C CNN + 1 12750 9600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 16300 7700 16450 7700 +Wire Wire Line + 16450 7700 16450 8100 +Wire Wire Line + 14900 7900 14900 8150 +Wire Wire Line + 14900 8150 13000 8150 +$Comp +L nor_four U45 +U 1 1 685DB5E9 +P 17000 7300 +F 0 "U45" H 19850 9100 60 0000 C CNN +F 1 "nor_four" H 19850 9300 60 0000 C CNN +F 2 "" H 19850 9250 60 0000 C CNN +F 3 "" H 19850 9250 60 0000 C CNN + 1 17000 7300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 19150 5200 19150 5400 +Wire Wire Line + 19050 5300 19050 5500 +Wire Wire Line + 19050 5500 19150 5500 +Wire Wire Line + 20550 5400 20750 5400 +Wire Wire Line + 20750 5400 20750 5450 +$Comp +L nor_thre U46 +U 1 1 685DE966 +P 17000 8500 +F 0 "U46" H 19850 10300 60 0000 C CNN +F 1 "nor_thre" H 19850 10500 60 0000 C CNN +F 2 "" H 19850 10450 60 0000 C CNN +F 3 "" H 19850 10450 60 0000 C CNN + 1 17000 8500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 18800 6750 18800 6600 +Wire Wire Line + 18800 6600 19150 6600 +Wire Wire Line + 19150 6700 18900 6700 +Wire Wire Line + 18900 6700 18900 6850 +Wire Wire Line + 19150 6800 19050 6800 +Wire Wire Line + 19050 6800 19050 7100 +Wire Wire Line + 19050 7100 19450 7100 +Wire Wire Line + 19450 7100 19450 7200 +Wire Wire Line + 20550 6600 20700 6600 +Wire Wire Line + 20700 6600 20700 7050 +Wire Wire Line + 20700 7050 20350 7050 +Wire Wire Line + 20350 7050 20350 7150 +$Comp +L nor_four U47 +U 1 1 685E094C +P 17200 12000 +F 0 "U47" H 20050 13800 60 0000 C CNN +F 1 "nor_four" H 20050 14000 60 0000 C CNN +F 2 "" H 20050 13950 60 0000 C CNN +F 3 "" H 20050 13950 60 0000 C CNN + 1 17200 12000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 19350 10000 19350 10100 +Wire Wire Line + 19150 10100 19150 10200 +Wire Wire Line + 19150 10200 19350 10200 +Wire Wire Line + 19350 10300 19150 10300 +Wire Wire Line + 19150 10300 19150 10400 +Wire Wire Line + 19350 10500 19350 10400 +Wire Wire Line + 20750 10100 20750 10250 +$Comp +L nor_thre U49 +U 1 1 685E3E8A +P 17200 13800 +F 0 "U49" H 20050 15600 60 0000 C CNN +F 1 "nor_thre" H 20050 15800 60 0000 C CNN +F 2 "" H 20050 15750 60 0000 C CNN +F 3 "" H 20050 15750 60 0000 C CNN + 1 17200 13800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 20750 11900 20800 11900 +Wire Wire Line + 20800 11900 20800 12250 +Wire Wire Line + 20800 12250 20600 12250 +Wire Wire Line + 20600 12250 20600 12300 +Wire Wire Line + 17350 12400 19350 12400 +Wire Wire Line + 19350 12400 19350 12100 +$Comp +L nor_four U50 +U 1 1 685E6D64 +P 17350 15450 +F 0 "U50" H 20200 17250 60 0000 C CNN +F 1 "nor_four" H 20200 17450 60 0000 C CNN +F 2 "" H 20200 17400 60 0000 C CNN +F 3 "" H 20200 17400 60 0000 C CNN + 1 17350 15450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 19500 13450 19500 13550 +Wire Wire Line + 19100 13550 19100 13650 +Wire Wire Line + 19100 13650 19500 13650 +Wire Wire Line + 19500 13750 19100 13750 +Wire Wire Line + 19100 13750 19100 13850 +Wire Wire Line + 19500 13950 19500 13850 +Wire Wire Line + 20900 13550 20900 13700 +$Comp +L nor_four U52 +U 1 1 685E9313 +P 17650 17250 +F 0 "U52" H 20500 19050 60 0000 C CNN +F 1 "nor_four" H 20500 19250 60 0000 C CNN +F 2 "" H 20500 19200 60 0000 C CNN +F 3 "" H 20500 19200 60 0000 C CNN + 1 17650 17250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 19800 15300 19800 15350 +Wire Wire Line + 19400 15400 19400 15450 +Wire Wire Line + 19400 15450 19800 15450 +Wire Wire Line + 19800 15550 19400 15550 +Wire Wire Line + 19400 15550 19400 15700 +Wire Wire Line + 19400 15800 19800 15800 +Wire Wire Line + 19800 15800 19800 15650 +Wire Wire Line + 21200 15350 21250 15350 +Wire Wire Line + 21250 15350 21250 15550 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4511B/CD4511B.sub b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4511B/CD4511B.sub new file mode 100644 index 000000000..1344ac2f0 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4511B/CD4511B.sub @@ -0,0 +1,324 @@ +* Subcircuit CD4511B +.subckt CD4511B net-_u106-pad1_ net-_u106-pad2_ net-_u106-pad3_ net-_u106-pad4_ net-_u1-pad1_ net-_u106-pad6_ net-_u106-pad7_ gnd net-_u103-pad2_ net-_u102-pad2_ net-_u101-pad2_ net-_u100-pad2_ net-_u106-pad13_ net-_u104-pad2_ net-_u105-pad2_ vcc +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\cd4511b\cd4511b.cir +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m3 net-_m3-pad1_ net-_m3-pad2_ net-_m3-pad3_ gnd CMOSN W=100u L=100u M=1 +m7 net-_m3-pad3_ net-_m7-pad2_ net-_m3-pad1_ vcc CMOSP W=100u L=100u M=1 +* u26 net-_m3-pad3_ net-_u26-pad2_ adc_bridge_1 +* u22 net-_u11-pad2_ net-_m7-pad2_ dac_bridge_1 +* u14 net-_u14-pad1_ net-_m3-pad1_ dac_bridge_1 +* u9 net-_u4-pad2_ net-_u14-pad1_ d_inverter +* u4 net-_u106-pad7_ net-_u4-pad2_ adc_bridge_1 +* u30 net-_u26-pad2_ net-_u30-pad2_ d_inverter +* u33 net-_u30-pad2_ net-_u33-pad2_ d_inverter +* u18 net-_u11-pad1_ net-_m3-pad2_ dac_bridge_1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1 +m5 net-_m1-pad3_ net-_m5-pad2_ net-_m1-pad1_ vcc CMOSP W=100u L=100u M=1 +* u24 net-_m1-pad3_ net-_u24-pad2_ adc_bridge_1 +* u19 net-_u11-pad2_ net-_m5-pad2_ dac_bridge_1 +* u12 net-_u12-pad1_ net-_m1-pad1_ dac_bridge_1 +* u7 net-_u2-pad2_ net-_u12-pad1_ d_inverter +* u2 net-_u106-pad1_ net-_u2-pad2_ adc_bridge_1 +* u28 net-_u24-pad2_ net-_u28-pad2_ d_inverter +* u32 net-_u28-pad2_ net-_u32-pad2_ d_inverter +* u16 net-_u11-pad1_ net-_m1-pad2_ dac_bridge_1 +m4 net-_m4-pad1_ net-_m4-pad2_ net-_m4-pad3_ gnd CMOSN W=100u L=100u M=1 +m8 net-_m4-pad3_ net-_m8-pad2_ net-_m4-pad1_ vcc CMOSP W=100u L=100u M=1 +* u27 net-_m4-pad3_ net-_u27-pad2_ adc_bridge_1 +* u23 net-_u11-pad2_ net-_m8-pad2_ dac_bridge_1 +* u15 net-_u10-pad2_ net-_m4-pad1_ dac_bridge_1 +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u5 net-_u106-pad2_ net-_u10-pad1_ adc_bridge_1 +* u31 net-_u27-pad2_ net-_u31-pad2_ d_inverter +* u34 net-_u31-pad2_ net-_u34-pad2_ d_inverter +* u20 net-_u11-pad1_ net-_m4-pad2_ dac_bridge_1 +m2 net-_m2-pad1_ net-_m2-pad2_ net-_m2-pad3_ gnd CMOSN W=100u L=100u M=1 +m6 net-_m2-pad3_ net-_m6-pad2_ net-_m2-pad1_ vcc CMOSP W=100u L=100u M=1 +* u25 net-_m2-pad3_ net-_u25-pad2_ adc_bridge_1 +* u21 net-_u11-pad2_ net-_m6-pad2_ dac_bridge_1 +* u13 net-_u13-pad1_ net-_m2-pad1_ dac_bridge_1 +* u8 net-_u3-pad2_ net-_u13-pad1_ d_inverter +* u3 net-_u106-pad6_ net-_u3-pad2_ adc_bridge_1 +* u29 net-_u25-pad2_ net-_u29-pad2_ d_inverter +* u17 net-_u11-pad1_ net-_m2-pad2_ dac_bridge_1 +* u35 net-_u34-pad2_ net-_u32-pad2_ net-_u35-pad3_ d_nand +* u51 net-_u35-pad3_ net-_u29-pad2_ net-_u51-pad3_ d_nand +* u63 net-_u48-pad2_ net-_u51-pad3_ net-_u45-pad1_ d_nand +* u37 net-_u32-pad2_ net-_u31-pad2_ net-_u37-pad3_ d_nor +* u6 net-_u1-pad2_ net-_u11-pad1_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ adc_bridge_1 +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +* u48 net-_u106-pad4_ net-_u48-pad2_ adc_bridge_1 +* u72 net-_u45-pad1_ net-_u40-pad4_ net-_u72-pad3_ d_nor +* u85 net-_u45-pad5_ net-_u83-pad2_ net-_u85-pad3_ d_nor +* u86 net-_u46-pad4_ net-_u83-pad2_ net-_u86-pad3_ d_nor +* u87 net-_u72-pad3_ net-_u83-pad2_ net-_u87-pad3_ d_nor +* u88 net-_u47-pad5_ net-_u83-pad2_ net-_u88-pad3_ d_nor +* u89 net-_u49-pad4_ net-_u83-pad2_ net-_u89-pad3_ d_nor +* u90 net-_u50-pad5_ net-_u83-pad2_ net-_u90-pad3_ d_nor +* u91 net-_u52-pad5_ net-_u83-pad2_ net-_u91-pad3_ d_nor +* u83 net-_u73-pad2_ net-_u83-pad2_ d_inverter +* u73 net-_u106-pad3_ net-_u73-pad2_ adc_bridge_1 +* u92 net-_u85-pad3_ net-_u92-pad2_ d_inverter +* u93 net-_u86-pad3_ net-_u100-pad1_ d_inverter +* u99 net-_u92-pad2_ net-_u106-pad13_ dac_bridge_1 +* u100 net-_u100-pad1_ net-_u100-pad2_ dac_bridge_1 +* u94 net-_u87-pad3_ net-_u101-pad1_ d_inverter +* u101 net-_u101-pad1_ net-_u101-pad2_ dac_bridge_1 +* u95 net-_u88-pad3_ net-_u102-pad1_ d_inverter +* u96 net-_u89-pad3_ net-_u103-pad1_ d_inverter +* u102 net-_u102-pad1_ net-_u102-pad2_ dac_bridge_1 +* u103 net-_u103-pad1_ net-_u103-pad2_ dac_bridge_1 +* u98 net-_u90-pad3_ net-_u105-pad1_ d_inverter +* u105 net-_u105-pad1_ net-_u105-pad2_ dac_bridge_1 +* u97 net-_u91-pad3_ net-_u104-pad1_ d_inverter +* u104 net-_u104-pad1_ net-_u104-pad2_ dac_bridge_1 +* u40 net-_u30-pad2_ net-_u32-pad2_ net-_u31-pad2_ net-_u40-pad4_ nor_thre +* u41 net-_u33-pad2_ net-_u28-pad2_ net-_u31-pad2_ net-_u41-pad4_ nor_thre +* u42 net-_u33-pad2_ net-_u32-pad2_ net-_u34-pad2_ net-_u42-pad4_ nor_thre +* u38 net-_u33-pad2_ net-_u28-pad2_ net-_u34-pad2_ net-_u38-pad4_ nor_thre +* u39 net-_u30-pad2_ net-_u34-pad2_ net-_u28-pad2_ net-_u39-pad4_ nor_thre +* u43 net-_u30-pad2_ net-_u28-pad2_ net-_u31-pad2_ net-_u29-pad2_ net-_u43-pad5_ nor_four +* u44 net-_u33-pad2_ net-_u28-pad2_ net-_u31-pad2_ net-_u29-pad2_ net-_u44-pad5_ nor_four +* u36 net-_u30-pad2_ net-_u32-pad2_ net-_u34-pad2_ net-_u36-pad4_ nor_thre +* u45 net-_u45-pad1_ net-_u36-pad4_ net-_u39-pad4_ net-_u44-pad5_ net-_u45-pad5_ nor_four +* u46 net-_u45-pad1_ net-_u36-pad4_ net-_u38-pad4_ net-_u46-pad4_ nor_thre +* u47 net-_u45-pad1_ net-_u42-pad4_ net-_u39-pad4_ net-_u41-pad4_ net-_u47-pad5_ nor_four +* u49 net-_u45-pad1_ net-_u30-pad2_ ? net-_u49-pad4_ nor_thre +* u50 net-_u45-pad1_ net-_u37-pad3_ net-_u42-pad4_ net-_u44-pad5_ net-_u50-pad5_ nor_four +* u52 net-_u45-pad1_ net-_u42-pad4_ net-_u44-pad5_ net-_u43-pad5_ net-_u52-pad5_ nor_four +a1 [net-_m3-pad3_ ] [net-_u26-pad2_ ] u26 +a2 [net-_u11-pad2_ ] [net-_m7-pad2_ ] u22 +a3 [net-_u14-pad1_ ] [net-_m3-pad1_ ] u14 +a4 net-_u4-pad2_ net-_u14-pad1_ u9 +a5 [net-_u106-pad7_ ] [net-_u4-pad2_ ] u4 +a6 net-_u26-pad2_ net-_u30-pad2_ u30 +a7 net-_u30-pad2_ net-_u33-pad2_ u33 +a8 [net-_u11-pad1_ ] [net-_m3-pad2_ ] u18 +a9 [net-_m1-pad3_ ] [net-_u24-pad2_ ] u24 +a10 [net-_u11-pad2_ ] [net-_m5-pad2_ ] u19 +a11 [net-_u12-pad1_ ] [net-_m1-pad1_ ] u12 +a12 net-_u2-pad2_ net-_u12-pad1_ u7 +a13 [net-_u106-pad1_ ] [net-_u2-pad2_ ] u2 +a14 net-_u24-pad2_ net-_u28-pad2_ u28 +a15 net-_u28-pad2_ net-_u32-pad2_ u32 +a16 [net-_u11-pad1_ ] [net-_m1-pad2_ ] u16 +a17 [net-_m4-pad3_ ] [net-_u27-pad2_ ] u27 +a18 [net-_u11-pad2_ ] [net-_m8-pad2_ ] u23 +a19 [net-_u10-pad2_ ] [net-_m4-pad1_ ] u15 +a20 net-_u10-pad1_ net-_u10-pad2_ u10 +a21 [net-_u106-pad2_ ] [net-_u10-pad1_ ] u5 +a22 net-_u27-pad2_ net-_u31-pad2_ u31 +a23 net-_u31-pad2_ net-_u34-pad2_ u34 +a24 [net-_u11-pad1_ ] [net-_m4-pad2_ ] u20 +a25 [net-_m2-pad3_ ] [net-_u25-pad2_ ] u25 +a26 [net-_u11-pad2_ ] [net-_m6-pad2_ ] u21 +a27 [net-_u13-pad1_ ] [net-_m2-pad1_ ] u13 +a28 net-_u3-pad2_ net-_u13-pad1_ u8 +a29 [net-_u106-pad6_ ] [net-_u3-pad2_ ] u3 +a30 net-_u25-pad2_ net-_u29-pad2_ u29 +a31 [net-_u11-pad1_ ] [net-_m2-pad2_ ] u17 +a32 [net-_u34-pad2_ net-_u32-pad2_ ] net-_u35-pad3_ u35 +a33 [net-_u35-pad3_ net-_u29-pad2_ ] net-_u51-pad3_ u51 +a34 [net-_u48-pad2_ net-_u51-pad3_ ] net-_u45-pad1_ u63 +a35 [net-_u32-pad2_ net-_u31-pad2_ ] net-_u37-pad3_ u37 +a36 net-_u1-pad2_ net-_u11-pad1_ u6 +a37 [net-_u1-pad1_ ] [net-_u1-pad2_ ] u1 +a38 net-_u11-pad1_ net-_u11-pad2_ u11 +a39 [net-_u106-pad4_ ] [net-_u48-pad2_ ] u48 +a40 [net-_u45-pad1_ net-_u40-pad4_ ] net-_u72-pad3_ u72 +a41 [net-_u45-pad5_ net-_u83-pad2_ ] net-_u85-pad3_ u85 +a42 [net-_u46-pad4_ net-_u83-pad2_ ] net-_u86-pad3_ u86 +a43 [net-_u72-pad3_ net-_u83-pad2_ ] net-_u87-pad3_ u87 +a44 [net-_u47-pad5_ net-_u83-pad2_ ] net-_u88-pad3_ u88 +a45 [net-_u49-pad4_ net-_u83-pad2_ ] net-_u89-pad3_ u89 +a46 [net-_u50-pad5_ net-_u83-pad2_ ] net-_u90-pad3_ u90 +a47 [net-_u52-pad5_ net-_u83-pad2_ ] net-_u91-pad3_ u91 +a48 net-_u73-pad2_ net-_u83-pad2_ u83 +a49 [net-_u106-pad3_ ] [net-_u73-pad2_ ] u73 +a50 net-_u85-pad3_ net-_u92-pad2_ u92 +a51 net-_u86-pad3_ net-_u100-pad1_ u93 +a52 [net-_u92-pad2_ ] [net-_u106-pad13_ ] u99 +a53 [net-_u100-pad1_ ] [net-_u100-pad2_ ] u100 +a54 net-_u87-pad3_ net-_u101-pad1_ u94 +a55 [net-_u101-pad1_ ] [net-_u101-pad2_ ] u101 +a56 net-_u88-pad3_ net-_u102-pad1_ u95 +a57 net-_u89-pad3_ net-_u103-pad1_ u96 +a58 [net-_u102-pad1_ ] [net-_u102-pad2_ ] u102 +a59 [net-_u103-pad1_ ] [net-_u103-pad2_ ] u103 +a60 net-_u90-pad3_ net-_u105-pad1_ u98 +a61 [net-_u105-pad1_ ] [net-_u105-pad2_ ] u105 +a62 net-_u91-pad3_ net-_u104-pad1_ u97 +a63 [net-_u104-pad1_ ] [net-_u104-pad2_ ] u104 +a64 [net-_u30-pad2_ ] [net-_u32-pad2_ ] [net-_u31-pad2_ ] [net-_u40-pad4_ ] u40 +a65 [net-_u33-pad2_ ] [net-_u28-pad2_ ] [net-_u31-pad2_ ] [net-_u41-pad4_ ] u41 +a66 [net-_u33-pad2_ ] [net-_u32-pad2_ ] [net-_u34-pad2_ ] [net-_u42-pad4_ ] u42 +a67 [net-_u33-pad2_ ] [net-_u28-pad2_ ] [net-_u34-pad2_ ] [net-_u38-pad4_ ] u38 +a68 [net-_u30-pad2_ ] [net-_u34-pad2_ ] [net-_u28-pad2_ ] [net-_u39-pad4_ ] u39 +a69 [net-_u30-pad2_ ] [net-_u28-pad2_ ] [net-_u31-pad2_ ] [net-_u29-pad2_ ] [net-_u43-pad5_ ] u43 +a70 [net-_u33-pad2_ ] [net-_u28-pad2_ ] [net-_u31-pad2_ ] [net-_u29-pad2_ ] [net-_u44-pad5_ ] u44 +a71 [net-_u30-pad2_ ] [net-_u32-pad2_ ] [net-_u34-pad2_ ] [net-_u36-pad4_ ] u36 +a72 [net-_u45-pad1_ ] [net-_u36-pad4_ ] [net-_u39-pad4_ ] [net-_u44-pad5_ ] [net-_u45-pad5_ ] u45 +a73 [net-_u45-pad1_ ] [net-_u36-pad4_ ] [net-_u38-pad4_ ] [net-_u46-pad4_ ] u46 +a74 [net-_u45-pad1_ ] [net-_u42-pad4_ ] [net-_u39-pad4_ ] [net-_u41-pad4_ ] [net-_u47-pad5_ ] u47 +a75 [net-_u45-pad1_ ] [net-_u30-pad2_ ] [? ] [net-_u49-pad4_ ] u49 +a76 [net-_u45-pad1_ ] [net-_u37-pad3_ ] [net-_u42-pad4_ ] [net-_u44-pad5_ ] [net-_u50-pad5_ ] u50 +a77 [net-_u45-pad1_ ] [net-_u42-pad4_ ] [net-_u44-pad5_ ] [net-_u43-pad5_ ] [net-_u52-pad5_ ] u52 +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u26 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u22 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u14 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u4 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u18 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u24 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u19 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u12 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u16 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u27 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u23 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u15 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u5 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u20 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u25 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u21 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u13 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u17 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u35 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u51 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u63 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u37 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u1 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u48 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u72 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u85 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u86 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u87 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u88 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u89 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u90 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u91 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u83 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u73 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u92 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u93 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u99 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u100 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u94 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u101 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u95 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u96 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u102 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u103 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u98 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u105 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u97 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u104 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: nor_thre, NgSpice Name: nor_thre +.model u40 nor_thre(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: nor_thre, NgSpice Name: nor_thre +.model u41 nor_thre(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: nor_thre, NgSpice Name: nor_thre +.model u42 nor_thre(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: nor_thre, NgSpice Name: nor_thre +.model u38 nor_thre(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: nor_thre, NgSpice Name: nor_thre +.model u39 nor_thre(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: nor_four, NgSpice Name: nor_four +.model u43 nor_four(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: nor_four, NgSpice Name: nor_four +.model u44 nor_four(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: nor_thre, NgSpice Name: nor_thre +.model u36 nor_thre(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: nor_four, NgSpice Name: nor_four +.model u45 nor_four(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: nor_thre, NgSpice Name: nor_thre +.model u46 nor_thre(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: nor_four, NgSpice Name: nor_four +.model u47 nor_four(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: nor_thre, NgSpice Name: nor_thre +.model u49 nor_thre(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: nor_four, NgSpice Name: nor_four +.model u50 nor_four(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: nor_four, NgSpice Name: nor_four +.model u52 nor_four(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Control Statements + +.ends CD4511B \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4511B/CD4511B_Previous_Values.xml b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4511B/CD4511B_Previous_Values.xml new file mode 100644 index 000000000..3767c5d1d --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4511B/CD4511B_Previous_Values.xml @@ -0,0 +1 @@ +adc_bridgedac_bridgedac_bridged_inverteradc_bridged_inverterd_inverterdac_bridgeadc_bridgedac_bridgedac_bridged_inverteradc_bridged_inverterd_inverterdac_bridgeadc_bridgedac_bridgedac_bridged_inverteradc_bridged_inverterd_inverterdac_bridgeadc_bridgedac_bridgedac_bridged_inverteradc_bridged_inverterdac_bridged_nandd_nandd_nandd_nord_nord_nord_nord_nord_nord_nord_nord_nord_nord_nord_nord_nord_nord_nord_nord_nord_nord_nord_nord_nord_nord_nord_nord_nord_inverteradc_bridged_inverteradc_bridged_nord_nord_nord_nord_nord_nord_nord_nord_nord_nord_nord_nord_nord_nord_nord_nord_nord_nord_nord_nord_nord_nord_nord_nord_nord_nord_inverteradc_bridged_inverterd_inverterdac_bridgedac_bridged_inverterdac_bridged_inverterd_inverterdac_bridgedac_bridged_inverterdac_bridged_inverterdac_bridgenor_threnor_threnor_threnor_threnor_threnor_fournor_fournor_threnor_fournor_threnor_fournor_threnor_fournor_fourC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4511B/NMOS-180nm.lib b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4511B/NMOS-180nm.lib new file mode 100644 index 000000000..51e9b1196 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4511B/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4511B/PMOS-180nm.lib b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4511B/PMOS-180nm.lib new file mode 100644 index 000000000..032b5b95e --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4511B/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4511B/analysis b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4511B/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4511B/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4514BC/CD4514BC-cache.lib b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4514BC/CD4514BC-cache.lib new file mode 100644 index 000000000..9a416599f --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4514BC/CD4514BC-cache.lib @@ -0,0 +1,111 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_srff +# +DEF d_srff U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_srff" 50 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 600 550 -600 -600 0 1 0 N +X S 1 -800 400 200 R 50 50 1 1 I +X R 2 -800 -450 200 R 50 50 1 1 I +X Clk 3 -800 0 200 R 50 50 1 1 I C +X Set 4 0 750 200 D 50 50 1 1 I +X Reset 5 0 -800 200 U 50 50 1 1 I +X Out 6 800 400 200 L 50 50 1 1 O +X Nout 7 800 -450 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4514BC/CD4514BC.cir b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4514BC/CD4514BC.cir new file mode 100644 index 000000000..419e4c5ce --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4514BC/CD4514BC.cir @@ -0,0 +1,101 @@ +* C:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\CD4514BC\CD4514BC.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/08/25 18:14:37 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U24 Net-_U24-Pad1_ Net-_U24-Pad2_ Net-_U16-Pad1_ d_and +U8 Net-_U3-Pad2_ Net-_U24-Pad1_ d_inverter +U9 Net-_U11-Pad1_ Net-_U24-Pad2_ d_inverter +U28 Net-_U16-Pad2_ Net-_U17-Pad2_ Net-_U28-Pad3_ d_and +U16 Net-_U16-Pad1_ Net-_U16-Pad2_ d_inverter +U17 Net-_U11-Pad1_ Net-_U17-Pad2_ d_inverter +U3 Net-_U1-Pad4_ Net-_U3-Pad2_ d_inverter +U52 Net-_U36-Pad2_ Net-_U37-Pad2_ Net-_U52-Pad3_ d_and +U36 Net-_U32-Pad6_ Net-_U36-Pad2_ d_inverter +U37 Net-_U33-Pad6_ Net-_U37-Pad2_ d_inverter +U53 Net-_U38-Pad2_ Net-_U39-Pad2_ Net-_U53-Pad3_ d_and +U38 Net-_U32-Pad7_ Net-_U38-Pad2_ d_inverter +U39 Net-_U33-Pad6_ Net-_U39-Pad2_ d_inverter +U25 Net-_U10-Pad2_ Net-_U11-Pad2_ Net-_U18-Pad1_ d_and +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ d_inverter +U29 Net-_U18-Pad2_ Net-_U19-Pad2_ Net-_U29-Pad3_ d_and +U18 Net-_U18-Pad1_ Net-_U18-Pad2_ d_inverter +U19 Net-_U11-Pad1_ Net-_U19-Pad2_ d_inverter +U4 Net-_U1-Pad5_ Net-_U10-Pad1_ d_inverter +U54 Net-_U40-Pad2_ Net-_U41-Pad2_ Net-_U54-Pad3_ d_and +U40 Net-_U32-Pad6_ Net-_U40-Pad2_ d_inverter +U41 Net-_U33-Pad7_ Net-_U41-Pad2_ d_inverter +U55 Net-_U42-Pad2_ Net-_U43-Pad2_ Net-_U55-Pad3_ d_and +U42 Net-_U32-Pad7_ Net-_U42-Pad2_ d_inverter +U43 Net-_U33-Pad7_ Net-_U43-Pad2_ d_inverter +U26 Net-_U12-Pad2_ Net-_U13-Pad2_ Net-_U20-Pad1_ d_and +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_inverter +U13 Net-_U11-Pad1_ Net-_U13-Pad2_ d_inverter +U30 Net-_U20-Pad2_ Net-_U21-Pad2_ Net-_U30-Pad3_ d_and +U20 Net-_U20-Pad1_ Net-_U20-Pad2_ d_inverter +U21 Net-_U11-Pad1_ Net-_U21-Pad2_ d_inverter +U5 Net-_U1-Pad6_ Net-_U12-Pad1_ d_inverter +U56 Net-_U44-Pad2_ Net-_U45-Pad2_ Net-_U56-Pad3_ d_and +U44 Net-_U34-Pad6_ Net-_U44-Pad2_ d_inverter +U45 Net-_U35-Pad6_ Net-_U45-Pad2_ d_inverter +U57 Net-_U46-Pad2_ Net-_U47-Pad2_ Net-_U57-Pad3_ d_and +U46 Net-_U34-Pad7_ Net-_U46-Pad2_ d_inverter +U47 Net-_U35-Pad6_ Net-_U47-Pad2_ d_inverter +U27 Net-_U14-Pad2_ Net-_U15-Pad2_ Net-_U22-Pad1_ d_and +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ d_inverter +U15 Net-_U11-Pad1_ Net-_U15-Pad2_ d_inverter +U31 Net-_U22-Pad2_ Net-_U23-Pad2_ Net-_U31-Pad3_ d_and +U22 Net-_U22-Pad1_ Net-_U22-Pad2_ d_inverter +U23 Net-_U11-Pad1_ Net-_U23-Pad2_ d_inverter +U6 Net-_U1-Pad7_ Net-_U14-Pad1_ d_inverter +U58 Net-_U48-Pad2_ Net-_U49-Pad2_ Net-_U58-Pad3_ d_and +U48 Net-_U34-Pad6_ Net-_U48-Pad2_ d_inverter +U49 Net-_U35-Pad7_ Net-_U49-Pad2_ d_inverter +U59 Net-_U50-Pad2_ Net-_U51-Pad2_ Net-_U59-Pad3_ d_and +U50 Net-_U34-Pad7_ Net-_U50-Pad2_ d_inverter +U51 Net-_U35-Pad7_ Net-_U51-Pad2_ d_inverter +U61 Net-_U56-Pad3_ Net-_U53-Pad3_ Net-_U61-Pad3_ d_nand +U77 Net-_U61-Pad3_ Net-_U7-Pad2_ Net-_U1-Pad9_ d_nand +U60 Net-_U56-Pad3_ Net-_U52-Pad3_ Net-_U60-Pad3_ d_nand +U76 Net-_U60-Pad3_ Net-_U7-Pad2_ Net-_U1-Pad8_ d_nand +U63 Net-_U56-Pad3_ Net-_U55-Pad3_ Net-_U63-Pad3_ d_nand +U79 Net-_U63-Pad3_ Net-_U7-Pad2_ Net-_U1-Pad11_ d_nand +U62 Net-_U56-Pad3_ Net-_U54-Pad3_ Net-_U62-Pad3_ d_nand +U78 Net-_U62-Pad3_ Net-_U7-Pad2_ Net-_U1-Pad10_ d_nand +U65 Net-_U57-Pad3_ Net-_U53-Pad3_ Net-_U65-Pad3_ d_nand +U81 Net-_U65-Pad3_ Net-_U7-Pad2_ Net-_U1-Pad13_ d_nand +U64 Net-_U57-Pad3_ Net-_U52-Pad3_ Net-_U64-Pad3_ d_nand +U80 Net-_U64-Pad3_ Net-_U7-Pad2_ Net-_U1-Pad12_ d_nand +U67 Net-_U57-Pad3_ Net-_U55-Pad3_ Net-_U67-Pad3_ d_nand +U83 Net-_U67-Pad3_ Net-_U7-Pad2_ Net-_U1-Pad15_ d_nand +U66 Net-_U57-Pad3_ Net-_U54-Pad3_ Net-_U66-Pad3_ d_nand +U82 Net-_U66-Pad3_ Net-_U7-Pad2_ Net-_U1-Pad14_ d_nand +U69 Net-_U58-Pad3_ Net-_U53-Pad3_ Net-_U69-Pad3_ d_nand +U85 Net-_U69-Pad3_ Net-_U7-Pad2_ Net-_U1-Pad17_ d_nand +U68 Net-_U58-Pad3_ Net-_U52-Pad3_ Net-_U68-Pad3_ d_nand +U84 Net-_U68-Pad3_ Net-_U7-Pad2_ Net-_U1-Pad16_ d_nand +U71 Net-_U58-Pad3_ Net-_U55-Pad3_ Net-_U71-Pad3_ d_nand +U87 Net-_U71-Pad3_ Net-_U7-Pad2_ Net-_U1-Pad19_ d_nand +U70 Net-_U58-Pad3_ Net-_U54-Pad3_ Net-_U70-Pad3_ d_nand +U86 Net-_U70-Pad3_ Net-_U7-Pad2_ Net-_U1-Pad18_ d_nand +U73 Net-_U59-Pad3_ Net-_U53-Pad3_ Net-_U73-Pad3_ d_nand +U89 Net-_U73-Pad3_ Net-_U7-Pad2_ Net-_U1-Pad21_ d_nand +U72 Net-_U59-Pad3_ Net-_U52-Pad3_ Net-_U72-Pad3_ d_nand +U88 Net-_U72-Pad3_ Net-_U7-Pad2_ Net-_U1-Pad20_ d_nand +U75 Net-_U59-Pad3_ Net-_U55-Pad3_ Net-_U75-Pad3_ d_nand +U91 Net-_U75-Pad3_ Net-_U7-Pad2_ Net-_U1-Pad23_ d_nand +U74 Net-_U59-Pad3_ Net-_U54-Pad3_ Net-_U74-Pad3_ d_nand +U90 Net-_U74-Pad3_ Net-_U7-Pad2_ Net-_U1-Pad22_ d_nand +U7 Net-_U1-Pad3_ Net-_U7-Pad2_ d_inverter +U2 Net-_U1-Pad2_ Net-_U11-Pad1_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ Net-_U1-Pad19_ Net-_U1-Pad20_ Net-_U1-Pad21_ Net-_U1-Pad22_ Net-_U1-Pad23_ ? PORT +U35 Net-_U22-Pad1_ Net-_U31-Pad3_ Net-_U1-Pad1_ ? ? Net-_U35-Pad6_ Net-_U35-Pad7_ d_srff +U34 Net-_U20-Pad1_ Net-_U30-Pad3_ Net-_U1-Pad1_ ? ? Net-_U34-Pad6_ Net-_U34-Pad7_ d_srff +U33 Net-_U18-Pad1_ Net-_U29-Pad3_ Net-_U1-Pad1_ ? ? Net-_U33-Pad6_ Net-_U33-Pad7_ d_srff +U32 Net-_U16-Pad1_ Net-_U28-Pad3_ Net-_U1-Pad1_ ? ? Net-_U32-Pad6_ Net-_U32-Pad7_ d_srff + +.end diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4514BC/CD4514BC.cir.out b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4514BC/CD4514BC.cir.out new file mode 100644 index 000000000..fb7e5b6e8 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4514BC/CD4514BC.cir.out @@ -0,0 +1,372 @@ +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\cd4514bc\cd4514bc.cir + +* u24 net-_u24-pad1_ net-_u24-pad2_ net-_u16-pad1_ d_and +* u8 net-_u3-pad2_ net-_u24-pad1_ d_inverter +* u9 net-_u11-pad1_ net-_u24-pad2_ d_inverter +* u28 net-_u16-pad2_ net-_u17-pad2_ net-_u28-pad3_ d_and +* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter +* u17 net-_u11-pad1_ net-_u17-pad2_ d_inverter +* u32 net-_u16-pad1_ net-_u28-pad3_ net-_u1-pad1_ ? ? net-_u32-pad6_ net-_u32-pad7_ d_srff +* u3 net-_u1-pad4_ net-_u3-pad2_ d_inverter +* u52 net-_u36-pad2_ net-_u37-pad2_ net-_u52-pad3_ d_and +* u36 net-_u32-pad6_ net-_u36-pad2_ d_inverter +* u37 net-_u33-pad6_ net-_u37-pad2_ d_inverter +* u53 net-_u38-pad2_ net-_u39-pad2_ net-_u53-pad3_ d_and +* u38 net-_u32-pad7_ net-_u38-pad2_ d_inverter +* u39 net-_u33-pad6_ net-_u39-pad2_ d_inverter +* u25 net-_u10-pad2_ net-_u11-pad2_ net-_u18-pad1_ d_and +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +* u29 net-_u18-pad2_ net-_u19-pad2_ net-_u29-pad3_ d_and +* u18 net-_u18-pad1_ net-_u18-pad2_ d_inverter +* u19 net-_u11-pad1_ net-_u19-pad2_ d_inverter +* u33 net-_u18-pad1_ net-_u29-pad3_ net-_u1-pad1_ ? ? net-_u33-pad6_ net-_u33-pad7_ d_srff +* u4 net-_u1-pad5_ net-_u10-pad1_ d_inverter +* u54 net-_u40-pad2_ net-_u41-pad2_ net-_u54-pad3_ d_and +* u40 net-_u32-pad6_ net-_u40-pad2_ d_inverter +* u41 net-_u33-pad7_ net-_u41-pad2_ d_inverter +* u55 net-_u42-pad2_ net-_u43-pad2_ net-_u55-pad3_ d_and +* u42 net-_u32-pad7_ net-_u42-pad2_ d_inverter +* u43 net-_u33-pad7_ net-_u43-pad2_ d_inverter +* u26 net-_u12-pad2_ net-_u13-pad2_ net-_u20-pad1_ d_and +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u13 net-_u11-pad1_ net-_u13-pad2_ d_inverter +* u30 net-_u20-pad2_ net-_u21-pad2_ net-_u30-pad3_ d_and +* u20 net-_u20-pad1_ net-_u20-pad2_ d_inverter +* u21 net-_u11-pad1_ net-_u21-pad2_ d_inverter +* u34 net-_u20-pad1_ net-_u30-pad3_ net-_u1-pad1_ ? ? net-_u34-pad6_ net-_u34-pad7_ d_srff +* u5 net-_u1-pad6_ net-_u12-pad1_ d_inverter +* u56 net-_u44-pad2_ net-_u45-pad2_ net-_u56-pad3_ d_and +* u44 net-_u34-pad6_ net-_u44-pad2_ d_inverter +* u45 net-_u35-pad6_ net-_u45-pad2_ d_inverter +* u57 net-_u46-pad2_ net-_u47-pad2_ net-_u57-pad3_ d_and +* u46 net-_u34-pad7_ net-_u46-pad2_ d_inverter +* u47 net-_u35-pad6_ net-_u47-pad2_ d_inverter +* u27 net-_u14-pad2_ net-_u15-pad2_ net-_u22-pad1_ d_and +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +* u15 net-_u11-pad1_ net-_u15-pad2_ d_inverter +* u31 net-_u22-pad2_ net-_u23-pad2_ net-_u31-pad3_ d_and +* u22 net-_u22-pad1_ net-_u22-pad2_ d_inverter +* u23 net-_u11-pad1_ net-_u23-pad2_ d_inverter +* u35 net-_u22-pad1_ net-_u31-pad3_ net-_u1-pad1_ ? ? net-_u35-pad6_ net-_u35-pad7_ d_srff +* u6 net-_u1-pad7_ net-_u14-pad1_ d_inverter +* u58 net-_u48-pad2_ net-_u49-pad2_ net-_u58-pad3_ d_and +* u48 net-_u34-pad6_ net-_u48-pad2_ d_inverter +* u49 net-_u35-pad7_ net-_u49-pad2_ d_inverter +* u59 net-_u50-pad2_ net-_u51-pad2_ net-_u59-pad3_ d_and +* u50 net-_u34-pad7_ net-_u50-pad2_ d_inverter +* u51 net-_u35-pad7_ net-_u51-pad2_ d_inverter +* u61 net-_u56-pad3_ net-_u53-pad3_ net-_u61-pad3_ d_nand +* u77 net-_u61-pad3_ net-_u7-pad2_ net-_u1-pad9_ d_nand +* u60 net-_u56-pad3_ net-_u52-pad3_ net-_u60-pad3_ d_nand +* u76 net-_u60-pad3_ net-_u7-pad2_ net-_u1-pad8_ d_nand +* u63 net-_u56-pad3_ net-_u55-pad3_ net-_u63-pad3_ d_nand +* u79 net-_u63-pad3_ net-_u7-pad2_ net-_u1-pad11_ d_nand +* u62 net-_u56-pad3_ net-_u54-pad3_ net-_u62-pad3_ d_nand +* u78 net-_u62-pad3_ net-_u7-pad2_ net-_u1-pad10_ d_nand +* u65 net-_u57-pad3_ net-_u53-pad3_ net-_u65-pad3_ d_nand +* u81 net-_u65-pad3_ net-_u7-pad2_ net-_u1-pad13_ d_nand +* u64 net-_u57-pad3_ net-_u52-pad3_ net-_u64-pad3_ d_nand +* u80 net-_u64-pad3_ net-_u7-pad2_ net-_u1-pad12_ d_nand +* u67 net-_u57-pad3_ net-_u55-pad3_ net-_u67-pad3_ d_nand +* u83 net-_u67-pad3_ net-_u7-pad2_ net-_u1-pad15_ d_nand +* u66 net-_u57-pad3_ net-_u54-pad3_ net-_u66-pad3_ d_nand +* u82 net-_u66-pad3_ net-_u7-pad2_ net-_u1-pad14_ d_nand +* u69 net-_u58-pad3_ net-_u53-pad3_ net-_u69-pad3_ d_nand +* u85 net-_u69-pad3_ net-_u7-pad2_ net-_u1-pad17_ d_nand +* u68 net-_u58-pad3_ net-_u52-pad3_ net-_u68-pad3_ d_nand +* u84 net-_u68-pad3_ net-_u7-pad2_ net-_u1-pad16_ d_nand +* u71 net-_u58-pad3_ net-_u55-pad3_ net-_u71-pad3_ d_nand +* u87 net-_u71-pad3_ net-_u7-pad2_ net-_u1-pad19_ d_nand +* u70 net-_u58-pad3_ net-_u54-pad3_ net-_u70-pad3_ d_nand +* u86 net-_u70-pad3_ net-_u7-pad2_ net-_u1-pad18_ d_nand +* u73 net-_u59-pad3_ net-_u53-pad3_ net-_u73-pad3_ d_nand +* u89 net-_u73-pad3_ net-_u7-pad2_ net-_u1-pad21_ d_nand +* u72 net-_u59-pad3_ net-_u52-pad3_ net-_u72-pad3_ d_nand +* u88 net-_u72-pad3_ net-_u7-pad2_ net-_u1-pad20_ d_nand +* u75 net-_u59-pad3_ net-_u55-pad3_ net-_u75-pad3_ d_nand +* u91 net-_u75-pad3_ net-_u7-pad2_ net-_u1-pad23_ d_nand +* u74 net-_u59-pad3_ net-_u54-pad3_ net-_u74-pad3_ d_nand +* u90 net-_u74-pad3_ net-_u7-pad2_ net-_u1-pad22_ d_nand +* u7 net-_u1-pad3_ net-_u7-pad2_ d_inverter +* u2 net-_u1-pad2_ net-_u11-pad1_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ ? port +a1 [net-_u24-pad1_ net-_u24-pad2_ ] net-_u16-pad1_ u24 +a2 net-_u3-pad2_ net-_u24-pad1_ u8 +a3 net-_u11-pad1_ net-_u24-pad2_ u9 +a4 [net-_u16-pad2_ net-_u17-pad2_ ] net-_u28-pad3_ u28 +a5 net-_u16-pad1_ net-_u16-pad2_ u16 +a6 net-_u11-pad1_ net-_u17-pad2_ u17 +a7 net-_u16-pad1_ net-_u28-pad3_ net-_u1-pad1_ ? ? net-_u32-pad6_ net-_u32-pad7_ u32 +a8 net-_u1-pad4_ net-_u3-pad2_ u3 +a9 [net-_u36-pad2_ net-_u37-pad2_ ] net-_u52-pad3_ u52 +a10 net-_u32-pad6_ net-_u36-pad2_ u36 +a11 net-_u33-pad6_ net-_u37-pad2_ u37 +a12 [net-_u38-pad2_ net-_u39-pad2_ ] net-_u53-pad3_ u53 +a13 net-_u32-pad7_ net-_u38-pad2_ u38 +a14 net-_u33-pad6_ net-_u39-pad2_ u39 +a15 [net-_u10-pad2_ net-_u11-pad2_ ] net-_u18-pad1_ u25 +a16 net-_u10-pad1_ net-_u10-pad2_ u10 +a17 net-_u11-pad1_ net-_u11-pad2_ u11 +a18 [net-_u18-pad2_ net-_u19-pad2_ ] net-_u29-pad3_ u29 +a19 net-_u18-pad1_ net-_u18-pad2_ u18 +a20 net-_u11-pad1_ net-_u19-pad2_ u19 +a21 net-_u18-pad1_ net-_u29-pad3_ net-_u1-pad1_ ? ? net-_u33-pad6_ net-_u33-pad7_ u33 +a22 net-_u1-pad5_ net-_u10-pad1_ u4 +a23 [net-_u40-pad2_ net-_u41-pad2_ ] net-_u54-pad3_ u54 +a24 net-_u32-pad6_ net-_u40-pad2_ u40 +a25 net-_u33-pad7_ net-_u41-pad2_ u41 +a26 [net-_u42-pad2_ net-_u43-pad2_ ] net-_u55-pad3_ u55 +a27 net-_u32-pad7_ net-_u42-pad2_ u42 +a28 net-_u33-pad7_ net-_u43-pad2_ u43 +a29 [net-_u12-pad2_ net-_u13-pad2_ ] net-_u20-pad1_ u26 +a30 net-_u12-pad1_ net-_u12-pad2_ u12 +a31 net-_u11-pad1_ net-_u13-pad2_ u13 +a32 [net-_u20-pad2_ net-_u21-pad2_ ] net-_u30-pad3_ u30 +a33 net-_u20-pad1_ net-_u20-pad2_ u20 +a34 net-_u11-pad1_ net-_u21-pad2_ u21 +a35 net-_u20-pad1_ net-_u30-pad3_ net-_u1-pad1_ ? ? net-_u34-pad6_ net-_u34-pad7_ u34 +a36 net-_u1-pad6_ net-_u12-pad1_ u5 +a37 [net-_u44-pad2_ net-_u45-pad2_ ] net-_u56-pad3_ u56 +a38 net-_u34-pad6_ net-_u44-pad2_ u44 +a39 net-_u35-pad6_ net-_u45-pad2_ u45 +a40 [net-_u46-pad2_ net-_u47-pad2_ ] net-_u57-pad3_ u57 +a41 net-_u34-pad7_ net-_u46-pad2_ u46 +a42 net-_u35-pad6_ net-_u47-pad2_ u47 +a43 [net-_u14-pad2_ net-_u15-pad2_ ] net-_u22-pad1_ u27 +a44 net-_u14-pad1_ net-_u14-pad2_ u14 +a45 net-_u11-pad1_ net-_u15-pad2_ u15 +a46 [net-_u22-pad2_ net-_u23-pad2_ ] net-_u31-pad3_ u31 +a47 net-_u22-pad1_ net-_u22-pad2_ u22 +a48 net-_u11-pad1_ net-_u23-pad2_ u23 +a49 net-_u22-pad1_ net-_u31-pad3_ net-_u1-pad1_ ? ? net-_u35-pad6_ net-_u35-pad7_ u35 +a50 net-_u1-pad7_ net-_u14-pad1_ u6 +a51 [net-_u48-pad2_ net-_u49-pad2_ ] net-_u58-pad3_ u58 +a52 net-_u34-pad6_ net-_u48-pad2_ u48 +a53 net-_u35-pad7_ net-_u49-pad2_ u49 +a54 [net-_u50-pad2_ net-_u51-pad2_ ] net-_u59-pad3_ u59 +a55 net-_u34-pad7_ net-_u50-pad2_ u50 +a56 net-_u35-pad7_ net-_u51-pad2_ u51 +a57 [net-_u56-pad3_ net-_u53-pad3_ ] net-_u61-pad3_ u61 +a58 [net-_u61-pad3_ net-_u7-pad2_ ] net-_u1-pad9_ u77 +a59 [net-_u56-pad3_ net-_u52-pad3_ ] net-_u60-pad3_ u60 +a60 [net-_u60-pad3_ net-_u7-pad2_ ] net-_u1-pad8_ u76 +a61 [net-_u56-pad3_ net-_u55-pad3_ ] net-_u63-pad3_ u63 +a62 [net-_u63-pad3_ net-_u7-pad2_ ] net-_u1-pad11_ u79 +a63 [net-_u56-pad3_ net-_u54-pad3_ ] net-_u62-pad3_ u62 +a64 [net-_u62-pad3_ net-_u7-pad2_ ] net-_u1-pad10_ u78 +a65 [net-_u57-pad3_ net-_u53-pad3_ ] net-_u65-pad3_ u65 +a66 [net-_u65-pad3_ net-_u7-pad2_ ] net-_u1-pad13_ u81 +a67 [net-_u57-pad3_ net-_u52-pad3_ ] net-_u64-pad3_ u64 +a68 [net-_u64-pad3_ net-_u7-pad2_ ] net-_u1-pad12_ u80 +a69 [net-_u57-pad3_ net-_u55-pad3_ ] net-_u67-pad3_ u67 +a70 [net-_u67-pad3_ net-_u7-pad2_ ] net-_u1-pad15_ u83 +a71 [net-_u57-pad3_ net-_u54-pad3_ ] net-_u66-pad3_ u66 +a72 [net-_u66-pad3_ net-_u7-pad2_ ] net-_u1-pad14_ u82 +a73 [net-_u58-pad3_ net-_u53-pad3_ ] net-_u69-pad3_ u69 +a74 [net-_u69-pad3_ net-_u7-pad2_ ] net-_u1-pad17_ u85 +a75 [net-_u58-pad3_ net-_u52-pad3_ ] net-_u68-pad3_ u68 +a76 [net-_u68-pad3_ net-_u7-pad2_ ] net-_u1-pad16_ u84 +a77 [net-_u58-pad3_ net-_u55-pad3_ ] net-_u71-pad3_ u71 +a78 [net-_u71-pad3_ net-_u7-pad2_ ] net-_u1-pad19_ u87 +a79 [net-_u58-pad3_ net-_u54-pad3_ ] net-_u70-pad3_ u70 +a80 [net-_u70-pad3_ net-_u7-pad2_ ] net-_u1-pad18_ u86 +a81 [net-_u59-pad3_ net-_u53-pad3_ ] net-_u73-pad3_ u73 +a82 [net-_u73-pad3_ net-_u7-pad2_ ] net-_u1-pad21_ u89 +a83 [net-_u59-pad3_ net-_u52-pad3_ ] net-_u72-pad3_ u72 +a84 [net-_u72-pad3_ net-_u7-pad2_ ] net-_u1-pad20_ u88 +a85 [net-_u59-pad3_ net-_u55-pad3_ ] net-_u75-pad3_ u75 +a86 [net-_u75-pad3_ net-_u7-pad2_ ] net-_u1-pad23_ u91 +a87 [net-_u59-pad3_ net-_u54-pad3_ ] net-_u74-pad3_ u74 +a88 [net-_u74-pad3_ net-_u7-pad2_ ] net-_u1-pad22_ u90 +a89 net-_u1-pad3_ net-_u7-pad2_ u7 +a90 net-_u1-pad2_ net-_u11-pad1_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_srff, NgSpice Name: d_srff +.model u32 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u52 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u53 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u38 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u39 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_srff, NgSpice Name: d_srff +.model u33 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u54 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u40 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u41 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u55 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u42 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u43 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_srff, NgSpice Name: d_srff +.model u34 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u56 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u44 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u45 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u57 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u46 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u47 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_srff, NgSpice Name: d_srff +.model u35 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u58 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u48 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u49 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u59 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u50 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u51 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u61 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u77 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u60 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u76 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u63 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u79 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u62 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u78 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u65 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u81 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u64 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u80 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u67 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u83 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u66 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u82 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u69 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u85 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u68 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u84 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u71 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u87 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u70 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u86 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u73 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u89 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u72 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u88 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u75 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u91 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u74 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u90 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4514BC/CD4514BC.pro b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4514BC/CD4514BC.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4514BC/CD4514BC.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4514BC/CD4514BC.sch b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4514BC/CD4514BC.sch new file mode 100644 index 000000000..908ad1fcb --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4514BC/CD4514BC.sch @@ -0,0 +1,1865 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:CD4514BC-cache +EELAYER 25 0 +EELAYER END +$Descr A2 23386 16535 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U24 +U 1 1 6842CEDD +P 7300 3850 +F 0 "U24" H 7300 3850 60 0000 C CNN +F 1 "d_and" H 7350 3950 60 0000 C CNN +F 2 "" H 7300 3850 60 0000 C CNN +F 3 "" H 7300 3850 60 0000 C CNN + 1 7300 3850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U8 +U 1 1 6842CF20 +P 6450 3750 +F 0 "U8" H 6450 3650 60 0000 C CNN +F 1 "d_inverter" H 6450 3900 60 0000 C CNN +F 2 "" H 6500 3700 60 0000 C CNN +F 3 "" H 6500 3700 60 0000 C CNN + 1 6450 3750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U9 +U 1 1 6842CF59 +P 6450 3850 +F 0 "U9" H 6450 3750 60 0000 C CNN +F 1 "d_inverter" H 6450 4000 60 0000 C CNN +F 2 "" H 6500 3800 60 0000 C CNN +F 3 "" H 6500 3800 60 0000 C CNN + 1 6450 3850 + 1 0 0 -1 +$EndComp +$Comp +L d_and U28 +U 1 1 6842D021 +P 7800 4700 +F 0 "U28" H 7800 4700 60 0000 C CNN +F 1 "d_and" H 7850 4800 60 0000 C CNN +F 2 "" H 7800 4700 60 0000 C CNN +F 3 "" H 7800 4700 60 0000 C CNN + 1 7800 4700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U16 +U 1 1 6842D027 +P 6950 4600 +F 0 "U16" H 6950 4500 60 0000 C CNN +F 1 "d_inverter" H 6950 4750 60 0000 C CNN +F 2 "" H 7000 4550 60 0000 C CNN +F 3 "" H 7000 4550 60 0000 C CNN + 1 6950 4600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U17 +U 1 1 6842D02D +P 6950 4700 +F 0 "U17" H 6950 4600 60 0000 C CNN +F 1 "d_inverter" H 6950 4850 60 0000 C CNN +F 2 "" H 7000 4650 60 0000 C CNN +F 3 "" H 7000 4650 60 0000 C CNN + 1 6950 4700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 6842D1BE +P 5200 3750 +F 0 "U3" H 5200 3650 60 0000 C CNN +F 1 "d_inverter" H 5200 3900 60 0000 C CNN +F 2 "" H 5250 3700 60 0000 C CNN +F 3 "" H 5250 3700 60 0000 C CNN + 1 5200 3750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U52 +U 1 1 6842D2FA +P 11700 4200 +F 0 "U52" H 11700 4200 60 0000 C CNN +F 1 "d_and" H 11750 4300 60 0000 C CNN +F 2 "" H 11700 4200 60 0000 C CNN +F 3 "" H 11700 4200 60 0000 C CNN + 1 11700 4200 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U36 +U 1 1 6842D300 +P 10850 4100 +F 0 "U36" H 10850 4000 60 0000 C CNN +F 1 "d_inverter" H 10850 4250 60 0000 C CNN +F 2 "" H 10900 4050 60 0000 C CNN +F 3 "" H 10900 4050 60 0000 C CNN + 1 10850 4100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U37 +U 1 1 6842D306 +P 10850 4200 +F 0 "U37" H 10850 4100 60 0000 C CNN +F 1 "d_inverter" H 10850 4350 60 0000 C CNN +F 2 "" H 10900 4150 60 0000 C CNN +F 3 "" H 10900 4150 60 0000 C CNN + 1 10850 4200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U53 +U 1 1 6842D37D +P 11700 4950 +F 0 "U53" H 11700 4950 60 0000 C CNN +F 1 "d_and" H 11750 5050 60 0000 C CNN +F 2 "" H 11700 4950 60 0000 C CNN +F 3 "" H 11700 4950 60 0000 C CNN + 1 11700 4950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U38 +U 1 1 6842D383 +P 10850 4850 +F 0 "U38" H 10850 4750 60 0000 C CNN +F 1 "d_inverter" H 10850 5000 60 0000 C CNN +F 2 "" H 10900 4800 60 0000 C CNN +F 3 "" H 10900 4800 60 0000 C CNN + 1 10850 4850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U39 +U 1 1 6842D389 +P 10850 4950 +F 0 "U39" H 10850 4850 60 0000 C CNN +F 1 "d_inverter" H 10850 5100 60 0000 C CNN +F 2 "" H 10900 4900 60 0000 C CNN +F 3 "" H 10900 4900 60 0000 C CNN + 1 10850 4950 + 1 0 0 -1 +$EndComp +$Comp +L d_and U25 +U 1 1 6842D607 +P 7300 5650 +F 0 "U25" H 7300 5650 60 0000 C CNN +F 1 "d_and" H 7350 5750 60 0000 C CNN +F 2 "" H 7300 5650 60 0000 C CNN +F 3 "" H 7300 5650 60 0000 C CNN + 1 7300 5650 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U10 +U 1 1 6842D60D +P 6450 5550 +F 0 "U10" H 6450 5450 60 0000 C CNN +F 1 "d_inverter" H 6450 5700 60 0000 C CNN +F 2 "" H 6500 5500 60 0000 C CNN +F 3 "" H 6500 5500 60 0000 C CNN + 1 6450 5550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U11 +U 1 1 6842D613 +P 6450 5650 +F 0 "U11" H 6450 5550 60 0000 C CNN +F 1 "d_inverter" H 6450 5800 60 0000 C CNN +F 2 "" H 6500 5600 60 0000 C CNN +F 3 "" H 6500 5600 60 0000 C CNN + 1 6450 5650 + 1 0 0 -1 +$EndComp +$Comp +L d_and U29 +U 1 1 6842D61B +P 7800 6500 +F 0 "U29" H 7800 6500 60 0000 C CNN +F 1 "d_and" H 7850 6600 60 0000 C CNN +F 2 "" H 7800 6500 60 0000 C CNN +F 3 "" H 7800 6500 60 0000 C CNN + 1 7800 6500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U18 +U 1 1 6842D621 +P 6950 6400 +F 0 "U18" H 6950 6300 60 0000 C CNN +F 1 "d_inverter" H 6950 6550 60 0000 C CNN +F 2 "" H 7000 6350 60 0000 C CNN +F 3 "" H 7000 6350 60 0000 C CNN + 1 6950 6400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U19 +U 1 1 6842D627 +P 6950 6500 +F 0 "U19" H 6950 6400 60 0000 C CNN +F 1 "d_inverter" H 6950 6650 60 0000 C CNN +F 2 "" H 7000 6450 60 0000 C CNN +F 3 "" H 7000 6450 60 0000 C CNN + 1 6950 6500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 6842D637 +P 5200 5550 +F 0 "U4" H 5200 5450 60 0000 C CNN +F 1 "d_inverter" H 5200 5700 60 0000 C CNN +F 2 "" H 5250 5500 60 0000 C CNN +F 3 "" H 5250 5500 60 0000 C CNN + 1 5200 5550 + 1 0 0 -1 +$EndComp +$Comp +L d_and U54 +U 1 1 6842D63E +P 11700 6000 +F 0 "U54" H 11700 6000 60 0000 C CNN +F 1 "d_and" H 11750 6100 60 0000 C CNN +F 2 "" H 11700 6000 60 0000 C CNN +F 3 "" H 11700 6000 60 0000 C CNN + 1 11700 6000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U40 +U 1 1 6842D644 +P 10850 5900 +F 0 "U40" H 10850 5800 60 0000 C CNN +F 1 "d_inverter" H 10850 6050 60 0000 C CNN +F 2 "" H 10900 5850 60 0000 C CNN +F 3 "" H 10900 5850 60 0000 C CNN + 1 10850 5900 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U41 +U 1 1 6842D64A +P 10850 6000 +F 0 "U41" H 10850 5900 60 0000 C CNN +F 1 "d_inverter" H 10850 6150 60 0000 C CNN +F 2 "" H 10900 5950 60 0000 C CNN +F 3 "" H 10900 5950 60 0000 C CNN + 1 10850 6000 + 1 0 0 -1 +$EndComp +$Comp +L d_and U55 +U 1 1 6842D652 +P 11700 6750 +F 0 "U55" H 11700 6750 60 0000 C CNN +F 1 "d_and" H 11750 6850 60 0000 C CNN +F 2 "" H 11700 6750 60 0000 C CNN +F 3 "" H 11700 6750 60 0000 C CNN + 1 11700 6750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U42 +U 1 1 6842D658 +P 10850 6650 +F 0 "U42" H 10850 6550 60 0000 C CNN +F 1 "d_inverter" H 10850 6800 60 0000 C CNN +F 2 "" H 10900 6600 60 0000 C CNN +F 3 "" H 10900 6600 60 0000 C CNN + 1 10850 6650 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U43 +U 1 1 6842D65E +P 10850 6750 +F 0 "U43" H 10850 6650 60 0000 C CNN +F 1 "d_inverter" H 10850 6900 60 0000 C CNN +F 2 "" H 10900 6700 60 0000 C CNN +F 3 "" H 10900 6700 60 0000 C CNN + 1 10850 6750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U26 +U 1 1 6842E78D +P 7300 7350 +F 0 "U26" H 7300 7350 60 0000 C CNN +F 1 "d_and" H 7350 7450 60 0000 C CNN +F 2 "" H 7300 7350 60 0000 C CNN +F 3 "" H 7300 7350 60 0000 C CNN + 1 7300 7350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U12 +U 1 1 6842E793 +P 6450 7250 +F 0 "U12" H 6450 7150 60 0000 C CNN +F 1 "d_inverter" H 6450 7400 60 0000 C CNN +F 2 "" H 6500 7200 60 0000 C CNN +F 3 "" H 6500 7200 60 0000 C CNN + 1 6450 7250 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U13 +U 1 1 6842E799 +P 6450 7350 +F 0 "U13" H 6450 7250 60 0000 C CNN +F 1 "d_inverter" H 6450 7500 60 0000 C CNN +F 2 "" H 6500 7300 60 0000 C CNN +F 3 "" H 6500 7300 60 0000 C CNN + 1 6450 7350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U30 +U 1 1 6842E7A1 +P 7800 8200 +F 0 "U30" H 7800 8200 60 0000 C CNN +F 1 "d_and" H 7850 8300 60 0000 C CNN +F 2 "" H 7800 8200 60 0000 C CNN +F 3 "" H 7800 8200 60 0000 C CNN + 1 7800 8200 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U20 +U 1 1 6842E7A7 +P 6950 8100 +F 0 "U20" H 6950 8000 60 0000 C CNN +F 1 "d_inverter" H 6950 8250 60 0000 C CNN +F 2 "" H 7000 8050 60 0000 C CNN +F 3 "" H 7000 8050 60 0000 C CNN + 1 6950 8100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U21 +U 1 1 6842E7AD +P 6950 8200 +F 0 "U21" H 6950 8100 60 0000 C CNN +F 1 "d_inverter" H 6950 8350 60 0000 C CNN +F 2 "" H 7000 8150 60 0000 C CNN +F 3 "" H 7000 8150 60 0000 C CNN + 1 6950 8200 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 6842E7BD +P 5200 7250 +F 0 "U5" H 5200 7150 60 0000 C CNN +F 1 "d_inverter" H 5200 7400 60 0000 C CNN +F 2 "" H 5250 7200 60 0000 C CNN +F 3 "" H 5250 7200 60 0000 C CNN + 1 5200 7250 + 1 0 0 -1 +$EndComp +$Comp +L d_and U56 +U 1 1 6842E7C4 +P 11700 7700 +F 0 "U56" H 11700 7700 60 0000 C CNN +F 1 "d_and" H 11750 7800 60 0000 C CNN +F 2 "" H 11700 7700 60 0000 C CNN +F 3 "" H 11700 7700 60 0000 C CNN + 1 11700 7700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U44 +U 1 1 6842E7CA +P 10850 7600 +F 0 "U44" H 10850 7500 60 0000 C CNN +F 1 "d_inverter" H 10850 7750 60 0000 C CNN +F 2 "" H 10900 7550 60 0000 C CNN +F 3 "" H 10900 7550 60 0000 C CNN + 1 10850 7600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U45 +U 1 1 6842E7D0 +P 10850 7700 +F 0 "U45" H 10850 7600 60 0000 C CNN +F 1 "d_inverter" H 10850 7850 60 0000 C CNN +F 2 "" H 10900 7650 60 0000 C CNN +F 3 "" H 10900 7650 60 0000 C CNN + 1 10850 7700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U57 +U 1 1 6842E7D8 +P 11700 8450 +F 0 "U57" H 11700 8450 60 0000 C CNN +F 1 "d_and" H 11750 8550 60 0000 C CNN +F 2 "" H 11700 8450 60 0000 C CNN +F 3 "" H 11700 8450 60 0000 C CNN + 1 11700 8450 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U46 +U 1 1 6842E7DE +P 10850 8350 +F 0 "U46" H 10850 8250 60 0000 C CNN +F 1 "d_inverter" H 10850 8500 60 0000 C CNN +F 2 "" H 10900 8300 60 0000 C CNN +F 3 "" H 10900 8300 60 0000 C CNN + 1 10850 8350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U47 +U 1 1 6842E7E4 +P 10850 8450 +F 0 "U47" H 10850 8350 60 0000 C CNN +F 1 "d_inverter" H 10850 8600 60 0000 C CNN +F 2 "" H 10900 8400 60 0000 C CNN +F 3 "" H 10900 8400 60 0000 C CNN + 1 10850 8450 + 1 0 0 -1 +$EndComp +$Comp +L d_and U27 +U 1 1 6842E7EC +P 7300 9150 +F 0 "U27" H 7300 9150 60 0000 C CNN +F 1 "d_and" H 7350 9250 60 0000 C CNN +F 2 "" H 7300 9150 60 0000 C CNN +F 3 "" H 7300 9150 60 0000 C CNN + 1 7300 9150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U14 +U 1 1 6842E7F2 +P 6450 9050 +F 0 "U14" H 6450 8950 60 0000 C CNN +F 1 "d_inverter" H 6450 9200 60 0000 C CNN +F 2 "" H 6500 9000 60 0000 C CNN +F 3 "" H 6500 9000 60 0000 C CNN + 1 6450 9050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U15 +U 1 1 6842E7F8 +P 6450 9150 +F 0 "U15" H 6450 9050 60 0000 C CNN +F 1 "d_inverter" H 6450 9300 60 0000 C CNN +F 2 "" H 6500 9100 60 0000 C CNN +F 3 "" H 6500 9100 60 0000 C CNN + 1 6450 9150 + 1 0 0 -1 +$EndComp +$Comp +L d_and U31 +U 1 1 6842E800 +P 7800 10000 +F 0 "U31" H 7800 10000 60 0000 C CNN +F 1 "d_and" H 7850 10100 60 0000 C CNN +F 2 "" H 7800 10000 60 0000 C CNN +F 3 "" H 7800 10000 60 0000 C CNN + 1 7800 10000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U22 +U 1 1 6842E806 +P 6950 9900 +F 0 "U22" H 6950 9800 60 0000 C CNN +F 1 "d_inverter" H 6950 10050 60 0000 C CNN +F 2 "" H 7000 9850 60 0000 C CNN +F 3 "" H 7000 9850 60 0000 C CNN + 1 6950 9900 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U23 +U 1 1 6842E80C +P 6950 10000 +F 0 "U23" H 6950 9900 60 0000 C CNN +F 1 "d_inverter" H 6950 10150 60 0000 C CNN +F 2 "" H 7000 9950 60 0000 C CNN +F 3 "" H 7000 9950 60 0000 C CNN + 1 6950 10000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 6842E81C +P 5200 9050 +F 0 "U6" H 5200 8950 60 0000 C CNN +F 1 "d_inverter" H 5200 9200 60 0000 C CNN +F 2 "" H 5250 9000 60 0000 C CNN +F 3 "" H 5250 9000 60 0000 C CNN + 1 5200 9050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U58 +U 1 1 6842E823 +P 11700 9500 +F 0 "U58" H 11700 9500 60 0000 C CNN +F 1 "d_and" H 11750 9600 60 0000 C CNN +F 2 "" H 11700 9500 60 0000 C CNN +F 3 "" H 11700 9500 60 0000 C CNN + 1 11700 9500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U48 +U 1 1 6842E829 +P 10850 9400 +F 0 "U48" H 10850 9300 60 0000 C CNN +F 1 "d_inverter" H 10850 9550 60 0000 C CNN +F 2 "" H 10900 9350 60 0000 C CNN +F 3 "" H 10900 9350 60 0000 C CNN + 1 10850 9400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U49 +U 1 1 6842E82F +P 10850 9500 +F 0 "U49" H 10850 9400 60 0000 C CNN +F 1 "d_inverter" H 10850 9650 60 0000 C CNN +F 2 "" H 10900 9450 60 0000 C CNN +F 3 "" H 10900 9450 60 0000 C CNN + 1 10850 9500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U59 +U 1 1 6842E837 +P 11700 10250 +F 0 "U59" H 11700 10250 60 0000 C CNN +F 1 "d_and" H 11750 10350 60 0000 C CNN +F 2 "" H 11700 10250 60 0000 C CNN +F 3 "" H 11700 10250 60 0000 C CNN + 1 11700 10250 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U50 +U 1 1 6842E83D +P 10850 10150 +F 0 "U50" H 10850 10050 60 0000 C CNN +F 1 "d_inverter" H 10850 10300 60 0000 C CNN +F 2 "" H 10900 10100 60 0000 C CNN +F 3 "" H 10900 10100 60 0000 C CNN + 1 10850 10150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U51 +U 1 1 6842E843 +P 10850 10250 +F 0 "U51" H 10850 10150 60 0000 C CNN +F 1 "d_inverter" H 10850 10400 60 0000 C CNN +F 2 "" H 10900 10200 60 0000 C CNN +F 3 "" H 10900 10200 60 0000 C CNN + 1 10850 10250 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U61 +U 1 1 684302D9 +P 15450 4550 +F 0 "U61" H 15450 4550 60 0000 C CNN +F 1 "d_nand" H 15500 4650 60 0000 C CNN +F 2 "" H 15450 4550 60 0000 C CNN +F 3 "" H 15450 4550 60 0000 C CNN + 1 15450 4550 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U77 +U 1 1 684304AD +P 16450 4500 +F 0 "U77" H 16450 4500 60 0000 C CNN +F 1 "d_nand" H 16500 4600 60 0000 C CNN +F 2 "" H 16450 4500 60 0000 C CNN +F 3 "" H 16450 4500 60 0000 C CNN + 1 16450 4500 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U60 +U 1 1 684309C9 +P 15450 4100 +F 0 "U60" H 15450 4100 60 0000 C CNN +F 1 "d_nand" H 15500 4200 60 0000 C CNN +F 2 "" H 15450 4100 60 0000 C CNN +F 3 "" H 15450 4100 60 0000 C CNN + 1 15450 4100 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U76 +U 1 1 684309CF +P 16450 4050 +F 0 "U76" H 16450 4050 60 0000 C CNN +F 1 "d_nand" H 16500 4150 60 0000 C CNN +F 2 "" H 16450 4050 60 0000 C CNN +F 3 "" H 16450 4050 60 0000 C CNN + 1 16450 4050 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U63 +U 1 1 68430AF7 +P 15500 5350 +F 0 "U63" H 15500 5350 60 0000 C CNN +F 1 "d_nand" H 15550 5450 60 0000 C CNN +F 2 "" H 15500 5350 60 0000 C CNN +F 3 "" H 15500 5350 60 0000 C CNN + 1 15500 5350 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U79 +U 1 1 68430AFD +P 16500 5300 +F 0 "U79" H 16500 5300 60 0000 C CNN +F 1 "d_nand" H 16550 5400 60 0000 C CNN +F 2 "" H 16500 5300 60 0000 C CNN +F 3 "" H 16500 5300 60 0000 C CNN + 1 16500 5300 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U62 +U 1 1 68430B05 +P 15500 4900 +F 0 "U62" H 15500 4900 60 0000 C CNN +F 1 "d_nand" H 15550 5000 60 0000 C CNN +F 2 "" H 15500 4900 60 0000 C CNN +F 3 "" H 15500 4900 60 0000 C CNN + 1 15500 4900 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U78 +U 1 1 68430B0B +P 16500 4850 +F 0 "U78" H 16500 4850 60 0000 C CNN +F 1 "d_nand" H 16550 4950 60 0000 C CNN +F 2 "" H 16500 4850 60 0000 C CNN +F 3 "" H 16500 4850 60 0000 C CNN + 1 16500 4850 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U65 +U 1 1 68430CC3 +P 15500 6150 +F 0 "U65" H 15500 6150 60 0000 C CNN +F 1 "d_nand" H 15550 6250 60 0000 C CNN +F 2 "" H 15500 6150 60 0000 C CNN +F 3 "" H 15500 6150 60 0000 C CNN + 1 15500 6150 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U81 +U 1 1 68430CC9 +P 16500 6100 +F 0 "U81" H 16500 6100 60 0000 C CNN +F 1 "d_nand" H 16550 6200 60 0000 C CNN +F 2 "" H 16500 6100 60 0000 C CNN +F 3 "" H 16500 6100 60 0000 C CNN + 1 16500 6100 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U64 +U 1 1 68430CD1 +P 15500 5700 +F 0 "U64" H 15500 5700 60 0000 C CNN +F 1 "d_nand" H 15550 5800 60 0000 C CNN +F 2 "" H 15500 5700 60 0000 C CNN +F 3 "" H 15500 5700 60 0000 C CNN + 1 15500 5700 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U80 +U 1 1 68430CD7 +P 16500 5650 +F 0 "U80" H 16500 5650 60 0000 C CNN +F 1 "d_nand" H 16550 5750 60 0000 C CNN +F 2 "" H 16500 5650 60 0000 C CNN +F 3 "" H 16500 5650 60 0000 C CNN + 1 16500 5650 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U67 +U 1 1 68430CDF +P 15550 6950 +F 0 "U67" H 15550 6950 60 0000 C CNN +F 1 "d_nand" H 15600 7050 60 0000 C CNN +F 2 "" H 15550 6950 60 0000 C CNN +F 3 "" H 15550 6950 60 0000 C CNN + 1 15550 6950 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U83 +U 1 1 68430CE5 +P 16550 6900 +F 0 "U83" H 16550 6900 60 0000 C CNN +F 1 "d_nand" H 16600 7000 60 0000 C CNN +F 2 "" H 16550 6900 60 0000 C CNN +F 3 "" H 16550 6900 60 0000 C CNN + 1 16550 6900 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U66 +U 1 1 68430CED +P 15550 6500 +F 0 "U66" H 15550 6500 60 0000 C CNN +F 1 "d_nand" H 15600 6600 60 0000 C CNN +F 2 "" H 15550 6500 60 0000 C CNN +F 3 "" H 15550 6500 60 0000 C CNN + 1 15550 6500 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U82 +U 1 1 68430CF3 +P 16550 6450 +F 0 "U82" H 16550 6450 60 0000 C CNN +F 1 "d_nand" H 16600 6550 60 0000 C CNN +F 2 "" H 16550 6450 60 0000 C CNN +F 3 "" H 16550 6450 60 0000 C CNN + 1 16550 6450 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U69 +U 1 1 6843121B +P 15550 7800 +F 0 "U69" H 15550 7800 60 0000 C CNN +F 1 "d_nand" H 15600 7900 60 0000 C CNN +F 2 "" H 15550 7800 60 0000 C CNN +F 3 "" H 15550 7800 60 0000 C CNN + 1 15550 7800 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U85 +U 1 1 68431221 +P 16550 7750 +F 0 "U85" H 16550 7750 60 0000 C CNN +F 1 "d_nand" H 16600 7850 60 0000 C CNN +F 2 "" H 16550 7750 60 0000 C CNN +F 3 "" H 16550 7750 60 0000 C CNN + 1 16550 7750 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U68 +U 1 1 68431229 +P 15550 7350 +F 0 "U68" H 15550 7350 60 0000 C CNN +F 1 "d_nand" H 15600 7450 60 0000 C CNN +F 2 "" H 15550 7350 60 0000 C CNN +F 3 "" H 15550 7350 60 0000 C CNN + 1 15550 7350 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U84 +U 1 1 6843122F +P 16550 7300 +F 0 "U84" H 16550 7300 60 0000 C CNN +F 1 "d_nand" H 16600 7400 60 0000 C CNN +F 2 "" H 16550 7300 60 0000 C CNN +F 3 "" H 16550 7300 60 0000 C CNN + 1 16550 7300 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U71 +U 1 1 68431237 +P 15600 8600 +F 0 "U71" H 15600 8600 60 0000 C CNN +F 1 "d_nand" H 15650 8700 60 0000 C CNN +F 2 "" H 15600 8600 60 0000 C CNN +F 3 "" H 15600 8600 60 0000 C CNN + 1 15600 8600 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U87 +U 1 1 6843123D +P 16600 8550 +F 0 "U87" H 16600 8550 60 0000 C CNN +F 1 "d_nand" H 16650 8650 60 0000 C CNN +F 2 "" H 16600 8550 60 0000 C CNN +F 3 "" H 16600 8550 60 0000 C CNN + 1 16600 8550 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U70 +U 1 1 68431245 +P 15600 8150 +F 0 "U70" H 15600 8150 60 0000 C CNN +F 1 "d_nand" H 15650 8250 60 0000 C CNN +F 2 "" H 15600 8150 60 0000 C CNN +F 3 "" H 15600 8150 60 0000 C CNN + 1 15600 8150 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U86 +U 1 1 6843124B +P 16600 8100 +F 0 "U86" H 16600 8100 60 0000 C CNN +F 1 "d_nand" H 16650 8200 60 0000 C CNN +F 2 "" H 16600 8100 60 0000 C CNN +F 3 "" H 16600 8100 60 0000 C CNN + 1 16600 8100 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U73 +U 1 1 68431253 +P 15600 9400 +F 0 "U73" H 15600 9400 60 0000 C CNN +F 1 "d_nand" H 15650 9500 60 0000 C CNN +F 2 "" H 15600 9400 60 0000 C CNN +F 3 "" H 15600 9400 60 0000 C CNN + 1 15600 9400 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U89 +U 1 1 68431259 +P 16600 9350 +F 0 "U89" H 16600 9350 60 0000 C CNN +F 1 "d_nand" H 16650 9450 60 0000 C CNN +F 2 "" H 16600 9350 60 0000 C CNN +F 3 "" H 16600 9350 60 0000 C CNN + 1 16600 9350 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U72 +U 1 1 68431261 +P 15600 8950 +F 0 "U72" H 15600 8950 60 0000 C CNN +F 1 "d_nand" H 15650 9050 60 0000 C CNN +F 2 "" H 15600 8950 60 0000 C CNN +F 3 "" H 15600 8950 60 0000 C CNN + 1 15600 8950 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U88 +U 1 1 68431267 +P 16600 8900 +F 0 "U88" H 16600 8900 60 0000 C CNN +F 1 "d_nand" H 16650 9000 60 0000 C CNN +F 2 "" H 16600 8900 60 0000 C CNN +F 3 "" H 16600 8900 60 0000 C CNN + 1 16600 8900 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U75 +U 1 1 6843126F +P 15650 10200 +F 0 "U75" H 15650 10200 60 0000 C CNN +F 1 "d_nand" H 15700 10300 60 0000 C CNN +F 2 "" H 15650 10200 60 0000 C CNN +F 3 "" H 15650 10200 60 0000 C CNN + 1 15650 10200 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U91 +U 1 1 68431275 +P 16650 10150 +F 0 "U91" H 16650 10150 60 0000 C CNN +F 1 "d_nand" H 16700 10250 60 0000 C CNN +F 2 "" H 16650 10150 60 0000 C CNN +F 3 "" H 16650 10150 60 0000 C CNN + 1 16650 10150 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U74 +U 1 1 6843127D +P 15650 9750 +F 0 "U74" H 15650 9750 60 0000 C CNN +F 1 "d_nand" H 15700 9850 60 0000 C CNN +F 2 "" H 15650 9750 60 0000 C CNN +F 3 "" H 15650 9750 60 0000 C CNN + 1 15650 9750 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U90 +U 1 1 68431283 +P 16650 9700 +F 0 "U90" H 16650 9700 60 0000 C CNN +F 1 "d_nand" H 16700 9800 60 0000 C CNN +F 2 "" H 16650 9700 60 0000 C CNN +F 3 "" H 16650 9700 60 0000 C CNN + 1 16650 9700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 6846F941 +P 5350 10600 +F 0 "U7" H 5350 10500 60 0000 C CNN +F 1 "d_inverter" H 5350 10750 60 0000 C CNN +F 2 "" H 5400 10550 60 0000 C CNN +F 3 "" H 5400 10550 60 0000 C CNN + 1 5350 10600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 68470940 +P 5100 10000 +F 0 "U2" H 5100 9900 60 0000 C CNN +F 1 "d_inverter" H 5100 10150 60 0000 C CNN +F 2 "" H 5150 9950 60 0000 C CNN +F 3 "" H 5150 9950 60 0000 C CNN + 1 5100 10000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 6847CB7E +P 4400 9050 +F 0 "U1" H 4450 9150 30 0000 C CNN +F 1 "PORT" H 4400 9050 30 0000 C CNN +F 2 "" H 4400 9050 60 0000 C CNN +F 3 "" H 4400 9050 60 0000 C CNN + 7 4400 9050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 6847CCA3 +P 4400 7250 +F 0 "U1" H 4450 7350 30 0000 C CNN +F 1 "PORT" H 4400 7250 30 0000 C CNN +F 2 "" H 4400 7250 60 0000 C CNN +F 3 "" H 4400 7250 60 0000 C CNN + 6 4400 7250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 6847D3D0 +P 4550 3600 +F 0 "U1" H 4600 3700 30 0000 C CNN +F 1 "PORT" H 4550 3600 30 0000 C CNN +F 2 "" H 4550 3600 60 0000 C CNN +F 3 "" H 4550 3600 60 0000 C CNN + 4 4550 3600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 6847D7CA +P 4250 8600 +F 0 "U1" H 4300 8700 30 0000 C CNN +F 1 "PORT" H 4250 8600 30 0000 C CNN +F 2 "" H 4250 8600 60 0000 C CNN +F 3 "" H 4250 8600 60 0000 C CNN + 1 4250 8600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 6847D8DD +P 4450 5550 +F 0 "U1" H 4500 5650 30 0000 C CNN +F 1 "PORT" H 4450 5550 30 0000 C CNN +F 2 "" H 4450 5550 60 0000 C CNN +F 3 "" H 4450 5550 60 0000 C CNN + 5 4450 5550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 6847D9E8 +P 4250 10000 +F 0 "U1" H 4300 10100 30 0000 C CNN +F 1 "PORT" H 4250 10000 30 0000 C CNN +F 2 "" H 4250 10000 60 0000 C CNN +F 3 "" H 4250 10000 60 0000 C CNN + 2 4250 10000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 6847DCAD +P 4350 10600 +F 0 "U1" H 4400 10700 30 0000 C CNN +F 1 "PORT" H 4350 10600 30 0000 C CNN +F 2 "" H 4350 10600 60 0000 C CNN +F 3 "" H 4350 10600 60 0000 C CNN + 3 4350 10600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 23 1 6847E07C +P 18500 10100 +F 0 "U1" H 18550 10200 30 0000 C CNN +F 1 "PORT" H 18500 10100 30 0000 C CNN +F 2 "" H 18500 10100 60 0000 C CNN +F 3 "" H 18500 10100 60 0000 C CNN + 23 18500 10100 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 22 1 6847E4A1 +P 18500 9650 +F 0 "U1" H 18550 9750 30 0000 C CNN +F 1 "PORT" H 18500 9650 30 0000 C CNN +F 2 "" H 18500 9650 60 0000 C CNN +F 3 "" H 18500 9650 60 0000 C CNN + 22 18500 9650 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 24 1 6847E690 +P 19150 9800 +F 0 "U1" H 19200 9900 30 0000 C CNN +F 1 "PORT" H 19150 9800 30 0000 C CNN +F 2 "" H 19150 9800 60 0000 C CNN +F 3 "" H 19150 9800 60 0000 C CNN + 24 19150 9800 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 21 1 6847F20F +P 18550 9300 +F 0 "U1" H 18600 9400 30 0000 C CNN +F 1 "PORT" H 18550 9300 30 0000 C CNN +F 2 "" H 18550 9300 60 0000 C CNN +F 3 "" H 18550 9300 60 0000 C CNN + 21 18550 9300 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 20 1 68480BF0 +P 18500 8850 +F 0 "U1" H 18550 8950 30 0000 C CNN +F 1 "PORT" H 18500 8850 30 0000 C CNN +F 2 "" H 18500 8850 60 0000 C CNN +F 3 "" H 18500 8850 60 0000 C CNN + 20 18500 8850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 19 1 68480D75 +P 18500 8500 +F 0 "U1" H 18550 8600 30 0000 C CNN +F 1 "PORT" H 18500 8500 30 0000 C CNN +F 2 "" H 18500 8500 60 0000 C CNN +F 3 "" H 18500 8500 60 0000 C CNN + 19 18500 8500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 18 1 68480E88 +P 18450 8050 +F 0 "U1" H 18500 8150 30 0000 C CNN +F 1 "PORT" H 18450 8050 30 0000 C CNN +F 2 "" H 18450 8050 60 0000 C CNN +F 3 "" H 18450 8050 60 0000 C CNN + 18 18450 8050 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 17 1 6848108B +P 18400 7700 +F 0 "U1" H 18450 7800 30 0000 C CNN +F 1 "PORT" H 18400 7700 30 0000 C CNN +F 2 "" H 18400 7700 60 0000 C CNN +F 3 "" H 18400 7700 60 0000 C CNN + 17 18400 7700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 16 1 684811A2 +P 18350 7250 +F 0 "U1" H 18400 7350 30 0000 C CNN +F 1 "PORT" H 18350 7250 30 0000 C CNN +F 2 "" H 18350 7250 60 0000 C CNN +F 3 "" H 18350 7250 60 0000 C CNN + 16 18350 7250 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 15 1 684812B7 +P 18300 6850 +F 0 "U1" H 18350 6950 30 0000 C CNN +F 1 "PORT" H 18300 6850 30 0000 C CNN +F 2 "" H 18300 6850 60 0000 C CNN +F 3 "" H 18300 6850 60 0000 C CNN + 15 18300 6850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 684813E2 +P 18300 6400 +F 0 "U1" H 18350 6500 30 0000 C CNN +F 1 "PORT" H 18300 6400 30 0000 C CNN +F 2 "" H 18300 6400 60 0000 C CNN +F 3 "" H 18300 6400 60 0000 C CNN + 14 18300 6400 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 68481577 +P 18300 6050 +F 0 "U1" H 18350 6150 30 0000 C CNN +F 1 "PORT" H 18300 6050 30 0000 C CNN +F 2 "" H 18300 6050 60 0000 C CNN +F 3 "" H 18300 6050 60 0000 C CNN + 13 18300 6050 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 68481982 +P 18250 5600 +F 0 "U1" H 18300 5700 30 0000 C CNN +F 1 "PORT" H 18250 5600 30 0000 C CNN +F 2 "" H 18250 5600 60 0000 C CNN +F 3 "" H 18250 5600 60 0000 C CNN + 12 18250 5600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 68481A9B +P 18200 5250 +F 0 "U1" H 18250 5350 30 0000 C CNN +F 1 "PORT" H 18200 5250 30 0000 C CNN +F 2 "" H 18200 5250 60 0000 C CNN +F 3 "" H 18200 5250 60 0000 C CNN + 11 18200 5250 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 10 1 68481CC0 +P 18150 4800 +F 0 "U1" H 18200 4900 30 0000 C CNN +F 1 "PORT" H 18150 4800 30 0000 C CNN +F 2 "" H 18150 4800 60 0000 C CNN +F 3 "" H 18150 4800 60 0000 C CNN + 10 18150 4800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 68481DE1 +P 18100 4450 +F 0 "U1" H 18150 4550 30 0000 C CNN +F 1 "PORT" H 18100 4450 30 0000 C CNN +F 2 "" H 18100 4450 60 0000 C CNN +F 3 "" H 18100 4450 60 0000 C CNN + 9 18100 4450 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 68482FA5 +P 18050 4000 +F 0 "U1" H 18100 4100 30 0000 C CNN +F 1 "PORT" H 18050 4000 30 0000 C CNN +F 2 "" H 18050 4000 60 0000 C CNN +F 3 "" H 18050 4000 60 0000 C CNN + 8 18050 4000 + -1 0 0 1 +$EndComp +NoConn ~ 18900 9800 +NoConn ~ 9350 3450 +NoConn ~ 9350 5000 +NoConn ~ 9350 5250 +NoConn ~ 9350 6950 +NoConn ~ 9350 6800 +NoConn ~ 9350 10300 +NoConn ~ 9350 8750 +NoConn ~ 9350 8500 +$Comp +L d_srff U35 +U 1 1 6842E814 +P 9350 9500 +F 0 "U35" H 9350 9500 60 0000 C CNN +F 1 "d_srff" H 9400 9650 60 0000 C CNN +F 2 "" H 9350 9500 60 0000 C CNN +F 3 "" H 9350 9500 60 0000 C CNN + 1 9350 9500 + 1 0 0 -1 +$EndComp +$Comp +L d_srff U34 +U 1 1 6842E7B5 +P 9350 7700 +F 0 "U34" H 9350 7700 60 0000 C CNN +F 1 "d_srff" H 9400 7850 60 0000 C CNN +F 2 "" H 9350 7700 60 0000 C CNN +F 3 "" H 9350 7700 60 0000 C CNN + 1 9350 7700 + 1 0 0 -1 +$EndComp +$Comp +L d_srff U33 +U 1 1 6842D62F +P 9350 6000 +F 0 "U33" H 9350 6000 60 0000 C CNN +F 1 "d_srff" H 9400 6150 60 0000 C CNN +F 2 "" H 9350 6000 60 0000 C CNN +F 3 "" H 9350 6000 60 0000 C CNN + 1 9350 6000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 16900 4000 17800 4000 +Wire Wire Line + 16900 4450 17850 4450 +Wire Wire Line + 16950 4800 17900 4800 +Wire Wire Line + 16950 5250 17950 5250 +Wire Wire Line + 16950 5600 18000 5600 +Wire Wire Line + 16950 6050 18050 6050 +Wire Wire Line + 17000 6400 18050 6400 +Wire Wire Line + 4600 10600 5050 10600 +Wire Wire Line + 4500 10000 4800 10000 +Wire Wire Line + 4650 9050 4900 9050 +Wire Wire Line + 4650 7250 4900 7250 +Wire Wire Line + 4700 5550 4900 5550 +Wire Wire Line + 4850 3750 4900 3750 +Wire Wire Line + 4850 3600 4850 3750 +Wire Wire Line + 4800 3600 4850 3600 +Connection ~ 8300 8600 +Wire Wire Line + 4500 8600 8300 8600 +Connection ~ 8300 6000 +Wire Wire Line + 8550 6000 8300 6000 +Connection ~ 8300 7700 +Wire Wire Line + 8550 7700 8300 7700 +Wire Wire Line + 8300 9500 8550 9500 +Wire Wire Line + 8300 4200 8300 9500 +Wire Wire Line + 8550 4200 8300 4200 +Connection ~ 7800 9100 +Wire Wire Line + 7800 9550 7800 9100 +Wire Wire Line + 6400 9550 7800 9550 +Wire Wire Line + 6400 9900 6400 9550 +Wire Wire Line + 6650 9900 6400 9900 +Connection ~ 5700 8200 +Wire Wire Line + 6650 8200 5700 8200 +Connection ~ 7850 7300 +Wire Wire Line + 7850 7750 7850 7300 +Wire Wire Line + 6450 7750 7850 7750 +Wire Wire Line + 6450 8100 6450 7750 +Wire Wire Line + 6650 8100 6450 8100 +Connection ~ 5700 6500 +Wire Wire Line + 6650 6500 5700 6500 +Connection ~ 7950 5600 +Wire Wire Line + 7950 6100 7950 5600 +Wire Wire Line + 6350 6100 7950 6100 +Wire Wire Line + 6350 6400 6350 6100 +Wire Wire Line + 6650 6400 6350 6400 +Connection ~ 5700 4700 +Wire Wire Line + 6650 4700 5700 4700 +Connection ~ 7850 3800 +Wire Wire Line + 6600 4600 6650 4600 +Wire Wire Line + 6600 4250 6600 4600 +Wire Wire Line + 7850 4250 6600 4250 +Wire Wire Line + 7850 3800 7850 4250 +Connection ~ 5700 9150 +Wire Wire Line + 6150 9150 5700 9150 +Connection ~ 5700 7350 +Wire Wire Line + 6150 7350 5700 7350 +Connection ~ 5700 5650 +Wire Wire Line + 6150 5650 5700 5650 +Connection ~ 5700 10000 +Wire Wire Line + 5700 3850 6150 3850 +Wire Wire Line + 5700 10000 5700 3850 +Wire Wire Line + 5400 10000 6650 10000 +Connection ~ 16150 10150 +Wire Wire Line + 16150 10600 5650 10600 +Connection ~ 14900 6700 +Wire Wire Line + 12150 6700 14900 6700 +Connection ~ 14900 8600 +Wire Wire Line + 14900 10200 15200 10200 +Connection ~ 14900 6950 +Wire Wire Line + 14900 8600 15150 8600 +Wire Wire Line + 14900 6950 15100 6950 +Wire Wire Line + 14900 5350 14900 10200 +Wire Wire Line + 15050 5350 14900 5350 +Connection ~ 13650 5950 +Wire Wire Line + 12150 5950 13650 5950 +Connection ~ 13650 8150 +Wire Wire Line + 13650 9750 15200 9750 +Connection ~ 13650 6500 +Wire Wire Line + 13650 8150 15150 8150 +Wire Wire Line + 13650 6500 15100 6500 +Wire Wire Line + 13650 5100 13650 9750 +Wire Wire Line + 14850 5100 13650 5100 +Wire Wire Line + 14850 4900 14850 5100 +Wire Wire Line + 15050 4900 14850 4900 +Connection ~ 14050 4900 +Wire Wire Line + 12150 4900 14050 4900 +Connection ~ 14050 7800 +Wire Wire Line + 14050 9400 15150 9400 +Connection ~ 14050 6150 +Wire Wire Line + 14050 7800 15100 7800 +Wire Wire Line + 14050 6150 15050 6150 +Wire Wire Line + 14050 4550 14050 9400 +Wire Wire Line + 15000 4550 14050 4550 +Connection ~ 14400 4150 +Wire Wire Line + 12150 4150 14400 4150 +Connection ~ 14400 7350 +Wire Wire Line + 14400 8950 15150 8950 +Connection ~ 14400 5700 +Wire Wire Line + 14400 7350 15100 7350 +Wire Wire Line + 14400 5700 15050 5700 +Wire Wire Line + 14400 4100 14400 8950 +Wire Wire Line + 15000 4100 14400 4100 +Connection ~ 14650 10100 +Wire Wire Line + 12150 10100 12150 10200 +Connection ~ 14650 8500 +Wire Wire Line + 14000 9450 12150 9450 +Wire Wire Line + 14000 8500 14000 9450 +Connection ~ 14650 6850 +Wire Wire Line + 13800 8400 13800 6850 +Wire Wire Line + 12150 8400 13800 8400 +Connection ~ 14650 5250 +Wire Wire Line + 13500 7650 13500 5250 +Wire Wire Line + 12150 7650 13500 7650 +Connection ~ 14650 9300 +Wire Wire Line + 15150 9300 14650 9300 +Connection ~ 14650 9650 +Wire Wire Line + 15200 9650 14650 9650 +Wire Wire Line + 12150 10100 15200 10100 +Wire Wire Line + 14650 8850 14650 10100 +Wire Wire Line + 15150 8850 14650 8850 +Connection ~ 14650 8050 +Wire Wire Line + 15150 8050 14650 8050 +Connection ~ 14650 7700 +Wire Wire Line + 15100 7700 14650 7700 +Wire Wire Line + 14000 8500 15150 8500 +Wire Wire Line + 14650 7250 14650 8500 +Wire Wire Line + 15100 7250 14650 7250 +Connection ~ 14650 6400 +Wire Wire Line + 15100 6400 14650 6400 +Connection ~ 14650 6050 +Wire Wire Line + 15050 6050 14650 6050 +Wire Wire Line + 13800 6850 15100 6850 +Wire Wire Line + 14650 5600 14650 6850 +Wire Wire Line + 15050 5600 14650 5600 +Connection ~ 14650 4800 +Wire Wire Line + 15050 4800 14650 4800 +Connection ~ 14650 4450 +Wire Wire Line + 15000 4450 14650 4450 +Wire Wire Line + 13500 5250 15050 5250 +Wire Wire Line + 14650 4000 14650 5250 +Wire Wire Line + 15000 4000 14650 4000 +Connection ~ 16050 7300 +Wire Wire Line + 16100 7300 16050 7300 +Connection ~ 16050 6900 +Wire Wire Line + 16100 6900 16050 6900 +Connection ~ 16050 6450 +Wire Wire Line + 16100 6450 16050 6450 +Connection ~ 16000 6100 +Wire Wire Line + 16050 6100 16000 6100 +Connection ~ 16000 5650 +Wire Wire Line + 16050 5650 16000 5650 +Connection ~ 16000 5300 +Wire Wire Line + 16050 5300 16000 5300 +Connection ~ 16000 4850 +Wire Wire Line + 16050 4850 16000 4850 +Connection ~ 15950 4500 +Wire Wire Line + 16000 4500 15950 4500 +Connection ~ 16050 7750 +Wire Wire Line + 16100 7750 16050 7750 +Connection ~ 16100 8100 +Wire Wire Line + 16150 8100 16100 8100 +Connection ~ 16100 8550 +Wire Wire Line + 16150 8550 16100 8550 +Connection ~ 16100 8900 +Wire Wire Line + 16150 8900 16100 8900 +Connection ~ 16100 9350 +Wire Wire Line + 16150 9350 16100 9350 +Connection ~ 16150 9700 +Wire Wire Line + 16200 9700 16150 9700 +Wire Wire Line + 16150 10150 16200 10150 +Wire Wire Line + 16150 9550 16150 10600 +Wire Wire Line + 16100 9550 16150 9550 +Wire Wire Line + 16100 7950 16100 9550 +Wire Wire Line + 16050 7950 16100 7950 +Wire Wire Line + 16050 6300 16050 7950 +Wire Wire Line + 16000 6300 16050 6300 +Wire Wire Line + 16000 4600 16000 6300 +Wire Wire Line + 15950 4600 16000 4600 +Wire Wire Line + 15950 4050 15950 4600 +Wire Wire Line + 16000 4050 15950 4050 +Wire Wire Line + 17100 10100 18250 10100 +Wire Wire Line + 17100 9650 18250 9650 +Wire Wire Line + 17050 9300 18300 9300 +Wire Wire Line + 17050 8850 18250 8850 +Wire Wire Line + 17050 8500 18250 8500 +Wire Wire Line + 17050 8050 18200 8050 +Wire Wire Line + 17000 7700 18150 7700 +Wire Wire Line + 17000 7250 18100 7250 +Wire Wire Line + 17000 6850 18050 6850 +Wire Wire Line + 16100 9600 16200 9600 +Wire Wire Line + 16100 9700 16100 9600 +Wire Wire Line + 16100 10050 16200 10050 +Wire Wire Line + 16100 10150 16100 10050 +Wire Wire Line + 16050 8800 16150 8800 +Wire Wire Line + 16050 8900 16050 8800 +Wire Wire Line + 16050 9250 16150 9250 +Wire Wire Line + 16050 9350 16050 9250 +Wire Wire Line + 16050 8000 16150 8000 +Wire Wire Line + 16050 8100 16050 8000 +Wire Wire Line + 16050 8450 16150 8450 +Wire Wire Line + 16050 8550 16050 8450 +Wire Wire Line + 16000 7200 16100 7200 +Wire Wire Line + 16000 7300 16000 7200 +Wire Wire Line + 16000 7650 16100 7650 +Wire Wire Line + 16000 7750 16000 7650 +Wire Wire Line + 16000 6350 16100 6350 +Wire Wire Line + 16000 6450 16000 6350 +Wire Wire Line + 16000 6800 16100 6800 +Wire Wire Line + 16000 6900 16000 6800 +Wire Wire Line + 15950 5550 16050 5550 +Wire Wire Line + 15950 5650 15950 5550 +Wire Wire Line + 15950 6000 16050 6000 +Wire Wire Line + 15950 6100 15950 6000 +Wire Wire Line + 15950 4750 16050 4750 +Wire Wire Line + 15950 4850 15950 4750 +Wire Wire Line + 15950 5200 16050 5200 +Wire Wire Line + 15950 5300 15950 5200 +Wire Wire Line + 15900 3950 16000 3950 +Wire Wire Line + 15900 4050 15900 3950 +Wire Wire Line + 15900 4400 16000 4400 +Wire Wire Line + 15900 4500 15900 4400 +Connection ~ 10300 8450 +Wire Wire Line + 10550 8450 10300 8450 +Connection ~ 10350 8150 +Wire Wire Line + 10350 10150 10550 10150 +Wire Wire Line + 10350 8150 10350 10150 +Connection ~ 10300 10250 +Wire Wire Line + 10300 9500 10300 10250 +Wire Wire Line + 10550 9500 10300 9500 +Wire Wire Line + 10150 10250 10550 10250 +Wire Wire Line + 10150 9950 10150 10250 +Wire Wire Line + 10550 8150 10550 8350 +Wire Wire Line + 10150 8150 10550 8150 +Connection ~ 10400 7600 +Wire Wire Line + 10550 7600 10400 7600 +Wire Wire Line + 10300 7700 10550 7700 +Wire Wire Line + 10300 9100 10300 7700 +Wire Wire Line + 10150 9100 10300 9100 +Wire Wire Line + 10400 9400 10550 9400 +Wire Wire Line + 10400 7300 10400 9400 +Wire Wire Line + 10150 7300 10400 7300 +Wire Wire Line + 11150 10250 11250 10250 +Wire Wire Line + 11150 10150 11250 10150 +Wire Wire Line + 11150 9500 11250 9500 +Wire Wire Line + 11150 9400 11250 9400 +Wire Wire Line + 5500 9050 6150 9050 +Wire Wire Line + 8250 9950 8550 9950 +Wire Wire Line + 7750 9100 8550 9100 +Wire Wire Line + 7250 10000 7350 10000 +Wire Wire Line + 7250 9900 7350 9900 +Wire Wire Line + 6750 9150 6850 9150 +Wire Wire Line + 6750 9050 6850 9050 +Wire Wire Line + 11150 8450 11250 8450 +Wire Wire Line + 11150 8350 11250 8350 +Wire Wire Line + 11150 7700 11250 7700 +Wire Wire Line + 11150 7600 11250 7600 +Wire Wire Line + 5500 7250 6150 7250 +Wire Wire Line + 8250 8150 8550 8150 +Wire Wire Line + 7750 7300 8550 7300 +Wire Wire Line + 7250 8200 7350 8200 +Wire Wire Line + 7250 8100 7350 8100 +Wire Wire Line + 6750 7350 6850 7350 +Wire Wire Line + 6750 7250 6850 7250 +Connection ~ 10300 4950 +Wire Wire Line + 10550 4950 10300 4950 +Connection ~ 10350 4650 +Wire Wire Line + 10350 6650 10550 6650 +Wire Wire Line + 10350 4650 10350 6650 +Connection ~ 10300 6750 +Wire Wire Line + 10300 6000 10300 6750 +Wire Wire Line + 10550 6000 10300 6000 +Wire Wire Line + 10150 6750 10550 6750 +Wire Wire Line + 10150 6450 10150 6750 +Wire Wire Line + 10550 4650 10550 4850 +Wire Wire Line + 10150 4650 10550 4650 +Connection ~ 10400 4100 +Wire Wire Line + 10550 4100 10400 4100 +Wire Wire Line + 10300 4200 10550 4200 +Wire Wire Line + 10300 5600 10300 4200 +Wire Wire Line + 10150 5600 10300 5600 +Wire Wire Line + 10400 5900 10550 5900 +Wire Wire Line + 10400 3800 10400 5900 +Wire Wire Line + 10150 3800 10400 3800 +Wire Wire Line + 11150 6750 11250 6750 +Wire Wire Line + 11150 6650 11250 6650 +Wire Wire Line + 11150 6000 11250 6000 +Wire Wire Line + 11150 5900 11250 5900 +Wire Wire Line + 5500 5550 6150 5550 +Wire Wire Line + 8250 6450 8550 6450 +Wire Wire Line + 7750 5600 8550 5600 +Wire Wire Line + 7250 6500 7350 6500 +Wire Wire Line + 7250 6400 7350 6400 +Wire Wire Line + 6750 5650 6850 5650 +Wire Wire Line + 6750 5550 6850 5550 +Wire Wire Line + 11150 4950 11250 4950 +Wire Wire Line + 11150 4850 11250 4850 +Wire Wire Line + 11150 4200 11250 4200 +Wire Wire Line + 11150 4100 11250 4100 +Wire Wire Line + 5500 3750 6150 3750 +Wire Wire Line + 8250 4650 8550 4650 +Wire Wire Line + 7750 3800 8550 3800 +Wire Wire Line + 7250 4700 7350 4700 +Wire Wire Line + 7250 4600 7350 4600 +Wire Wire Line + 6750 3850 6850 3850 +Wire Wire Line + 6750 3750 6850 3750 +$Comp +L d_srff U32 +U 1 1 6842D03D +P 9350 4200 +F 0 "U32" H 9350 4200 60 0000 C CNN +F 1 "d_srff" H 9400 4350 60 0000 C CNN +F 2 "" H 9350 4200 60 0000 C CNN +F 3 "" H 9350 4200 60 0000 C CNN + 1 9350 4200 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4514BC/CD4514BC.sub b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4514BC/CD4514BC.sub new file mode 100644 index 000000000..e78d2e95d --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4514BC/CD4514BC.sub @@ -0,0 +1,366 @@ +* Subcircuit CD4514BC +.subckt CD4514BC net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ ? +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\cd4514bc\cd4514bc.cir +* u24 net-_u24-pad1_ net-_u24-pad2_ net-_u16-pad1_ d_and +* u8 net-_u3-pad2_ net-_u24-pad1_ d_inverter +* u9 net-_u11-pad1_ net-_u24-pad2_ d_inverter +* u28 net-_u16-pad2_ net-_u17-pad2_ net-_u28-pad3_ d_and +* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter +* u17 net-_u11-pad1_ net-_u17-pad2_ d_inverter +* u32 net-_u16-pad1_ net-_u28-pad3_ net-_u1-pad1_ ? ? net-_u32-pad6_ net-_u32-pad7_ d_srff +* u3 net-_u1-pad4_ net-_u3-pad2_ d_inverter +* u52 net-_u36-pad2_ net-_u37-pad2_ net-_u52-pad3_ d_and +* u36 net-_u32-pad6_ net-_u36-pad2_ d_inverter +* u37 net-_u33-pad6_ net-_u37-pad2_ d_inverter +* u53 net-_u38-pad2_ net-_u39-pad2_ net-_u53-pad3_ d_and +* u38 net-_u32-pad7_ net-_u38-pad2_ d_inverter +* u39 net-_u33-pad6_ net-_u39-pad2_ d_inverter +* u25 net-_u10-pad2_ net-_u11-pad2_ net-_u18-pad1_ d_and +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +* u29 net-_u18-pad2_ net-_u19-pad2_ net-_u29-pad3_ d_and +* u18 net-_u18-pad1_ net-_u18-pad2_ d_inverter +* u19 net-_u11-pad1_ net-_u19-pad2_ d_inverter +* u33 net-_u18-pad1_ net-_u29-pad3_ net-_u1-pad1_ ? ? net-_u33-pad6_ net-_u33-pad7_ d_srff +* u4 net-_u1-pad5_ net-_u10-pad1_ d_inverter +* u54 net-_u40-pad2_ net-_u41-pad2_ net-_u54-pad3_ d_and +* u40 net-_u32-pad6_ net-_u40-pad2_ d_inverter +* u41 net-_u33-pad7_ net-_u41-pad2_ d_inverter +* u55 net-_u42-pad2_ net-_u43-pad2_ net-_u55-pad3_ d_and +* u42 net-_u32-pad7_ net-_u42-pad2_ d_inverter +* u43 net-_u33-pad7_ net-_u43-pad2_ d_inverter +* u26 net-_u12-pad2_ net-_u13-pad2_ net-_u20-pad1_ d_and +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u13 net-_u11-pad1_ net-_u13-pad2_ d_inverter +* u30 net-_u20-pad2_ net-_u21-pad2_ net-_u30-pad3_ d_and +* u20 net-_u20-pad1_ net-_u20-pad2_ d_inverter +* u21 net-_u11-pad1_ net-_u21-pad2_ d_inverter +* u34 net-_u20-pad1_ net-_u30-pad3_ net-_u1-pad1_ ? ? net-_u34-pad6_ net-_u34-pad7_ d_srff +* u5 net-_u1-pad6_ net-_u12-pad1_ d_inverter +* u56 net-_u44-pad2_ net-_u45-pad2_ net-_u56-pad3_ d_and +* u44 net-_u34-pad6_ net-_u44-pad2_ d_inverter +* u45 net-_u35-pad6_ net-_u45-pad2_ d_inverter +* u57 net-_u46-pad2_ net-_u47-pad2_ net-_u57-pad3_ d_and +* u46 net-_u34-pad7_ net-_u46-pad2_ d_inverter +* u47 net-_u35-pad6_ net-_u47-pad2_ d_inverter +* u27 net-_u14-pad2_ net-_u15-pad2_ net-_u22-pad1_ d_and +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +* u15 net-_u11-pad1_ net-_u15-pad2_ d_inverter +* u31 net-_u22-pad2_ net-_u23-pad2_ net-_u31-pad3_ d_and +* u22 net-_u22-pad1_ net-_u22-pad2_ d_inverter +* u23 net-_u11-pad1_ net-_u23-pad2_ d_inverter +* u35 net-_u22-pad1_ net-_u31-pad3_ net-_u1-pad1_ ? ? net-_u35-pad6_ net-_u35-pad7_ d_srff +* u6 net-_u1-pad7_ net-_u14-pad1_ d_inverter +* u58 net-_u48-pad2_ net-_u49-pad2_ net-_u58-pad3_ d_and +* u48 net-_u34-pad6_ net-_u48-pad2_ d_inverter +* u49 net-_u35-pad7_ net-_u49-pad2_ d_inverter +* u59 net-_u50-pad2_ net-_u51-pad2_ net-_u59-pad3_ d_and +* u50 net-_u34-pad7_ net-_u50-pad2_ d_inverter +* u51 net-_u35-pad7_ net-_u51-pad2_ d_inverter +* u61 net-_u56-pad3_ net-_u53-pad3_ net-_u61-pad3_ d_nand +* u77 net-_u61-pad3_ net-_u7-pad2_ net-_u1-pad9_ d_nand +* u60 net-_u56-pad3_ net-_u52-pad3_ net-_u60-pad3_ d_nand +* u76 net-_u60-pad3_ net-_u7-pad2_ net-_u1-pad8_ d_nand +* u63 net-_u56-pad3_ net-_u55-pad3_ net-_u63-pad3_ d_nand +* u79 net-_u63-pad3_ net-_u7-pad2_ net-_u1-pad11_ d_nand +* u62 net-_u56-pad3_ net-_u54-pad3_ net-_u62-pad3_ d_nand +* u78 net-_u62-pad3_ net-_u7-pad2_ net-_u1-pad10_ d_nand +* u65 net-_u57-pad3_ net-_u53-pad3_ net-_u65-pad3_ d_nand +* u81 net-_u65-pad3_ net-_u7-pad2_ net-_u1-pad13_ d_nand +* u64 net-_u57-pad3_ net-_u52-pad3_ net-_u64-pad3_ d_nand +* u80 net-_u64-pad3_ net-_u7-pad2_ net-_u1-pad12_ d_nand +* u67 net-_u57-pad3_ net-_u55-pad3_ net-_u67-pad3_ d_nand +* u83 net-_u67-pad3_ net-_u7-pad2_ net-_u1-pad15_ d_nand +* u66 net-_u57-pad3_ net-_u54-pad3_ net-_u66-pad3_ d_nand +* u82 net-_u66-pad3_ net-_u7-pad2_ net-_u1-pad14_ d_nand +* u69 net-_u58-pad3_ net-_u53-pad3_ net-_u69-pad3_ d_nand +* u85 net-_u69-pad3_ net-_u7-pad2_ net-_u1-pad17_ d_nand +* u68 net-_u58-pad3_ net-_u52-pad3_ net-_u68-pad3_ d_nand +* u84 net-_u68-pad3_ net-_u7-pad2_ net-_u1-pad16_ d_nand +* u71 net-_u58-pad3_ net-_u55-pad3_ net-_u71-pad3_ d_nand +* u87 net-_u71-pad3_ net-_u7-pad2_ net-_u1-pad19_ d_nand +* u70 net-_u58-pad3_ net-_u54-pad3_ net-_u70-pad3_ d_nand +* u86 net-_u70-pad3_ net-_u7-pad2_ net-_u1-pad18_ d_nand +* u73 net-_u59-pad3_ net-_u53-pad3_ net-_u73-pad3_ d_nand +* u89 net-_u73-pad3_ net-_u7-pad2_ net-_u1-pad21_ d_nand +* u72 net-_u59-pad3_ net-_u52-pad3_ net-_u72-pad3_ d_nand +* u88 net-_u72-pad3_ net-_u7-pad2_ net-_u1-pad20_ d_nand +* u75 net-_u59-pad3_ net-_u55-pad3_ net-_u75-pad3_ d_nand +* u91 net-_u75-pad3_ net-_u7-pad2_ net-_u1-pad23_ d_nand +* u74 net-_u59-pad3_ net-_u54-pad3_ net-_u74-pad3_ d_nand +* u90 net-_u74-pad3_ net-_u7-pad2_ net-_u1-pad22_ d_nand +* u7 net-_u1-pad3_ net-_u7-pad2_ d_inverter +* u2 net-_u1-pad2_ net-_u11-pad1_ d_inverter +a1 [net-_u24-pad1_ net-_u24-pad2_ ] net-_u16-pad1_ u24 +a2 net-_u3-pad2_ net-_u24-pad1_ u8 +a3 net-_u11-pad1_ net-_u24-pad2_ u9 +a4 [net-_u16-pad2_ net-_u17-pad2_ ] net-_u28-pad3_ u28 +a5 net-_u16-pad1_ net-_u16-pad2_ u16 +a6 net-_u11-pad1_ net-_u17-pad2_ u17 +a7 net-_u16-pad1_ net-_u28-pad3_ net-_u1-pad1_ ? ? net-_u32-pad6_ net-_u32-pad7_ u32 +a8 net-_u1-pad4_ net-_u3-pad2_ u3 +a9 [net-_u36-pad2_ net-_u37-pad2_ ] net-_u52-pad3_ u52 +a10 net-_u32-pad6_ net-_u36-pad2_ u36 +a11 net-_u33-pad6_ net-_u37-pad2_ u37 +a12 [net-_u38-pad2_ net-_u39-pad2_ ] net-_u53-pad3_ u53 +a13 net-_u32-pad7_ net-_u38-pad2_ u38 +a14 net-_u33-pad6_ net-_u39-pad2_ u39 +a15 [net-_u10-pad2_ net-_u11-pad2_ ] net-_u18-pad1_ u25 +a16 net-_u10-pad1_ net-_u10-pad2_ u10 +a17 net-_u11-pad1_ net-_u11-pad2_ u11 +a18 [net-_u18-pad2_ net-_u19-pad2_ ] net-_u29-pad3_ u29 +a19 net-_u18-pad1_ net-_u18-pad2_ u18 +a20 net-_u11-pad1_ net-_u19-pad2_ u19 +a21 net-_u18-pad1_ net-_u29-pad3_ net-_u1-pad1_ ? ? net-_u33-pad6_ net-_u33-pad7_ u33 +a22 net-_u1-pad5_ net-_u10-pad1_ u4 +a23 [net-_u40-pad2_ net-_u41-pad2_ ] net-_u54-pad3_ u54 +a24 net-_u32-pad6_ net-_u40-pad2_ u40 +a25 net-_u33-pad7_ net-_u41-pad2_ u41 +a26 [net-_u42-pad2_ net-_u43-pad2_ ] net-_u55-pad3_ u55 +a27 net-_u32-pad7_ net-_u42-pad2_ u42 +a28 net-_u33-pad7_ net-_u43-pad2_ u43 +a29 [net-_u12-pad2_ net-_u13-pad2_ ] net-_u20-pad1_ u26 +a30 net-_u12-pad1_ net-_u12-pad2_ u12 +a31 net-_u11-pad1_ net-_u13-pad2_ u13 +a32 [net-_u20-pad2_ net-_u21-pad2_ ] net-_u30-pad3_ u30 +a33 net-_u20-pad1_ net-_u20-pad2_ u20 +a34 net-_u11-pad1_ net-_u21-pad2_ u21 +a35 net-_u20-pad1_ net-_u30-pad3_ net-_u1-pad1_ ? ? net-_u34-pad6_ net-_u34-pad7_ u34 +a36 net-_u1-pad6_ net-_u12-pad1_ u5 +a37 [net-_u44-pad2_ net-_u45-pad2_ ] net-_u56-pad3_ u56 +a38 net-_u34-pad6_ net-_u44-pad2_ u44 +a39 net-_u35-pad6_ net-_u45-pad2_ u45 +a40 [net-_u46-pad2_ net-_u47-pad2_ ] net-_u57-pad3_ u57 +a41 net-_u34-pad7_ net-_u46-pad2_ u46 +a42 net-_u35-pad6_ net-_u47-pad2_ u47 +a43 [net-_u14-pad2_ net-_u15-pad2_ ] net-_u22-pad1_ u27 +a44 net-_u14-pad1_ net-_u14-pad2_ u14 +a45 net-_u11-pad1_ net-_u15-pad2_ u15 +a46 [net-_u22-pad2_ net-_u23-pad2_ ] net-_u31-pad3_ u31 +a47 net-_u22-pad1_ net-_u22-pad2_ u22 +a48 net-_u11-pad1_ net-_u23-pad2_ u23 +a49 net-_u22-pad1_ net-_u31-pad3_ net-_u1-pad1_ ? ? net-_u35-pad6_ net-_u35-pad7_ u35 +a50 net-_u1-pad7_ net-_u14-pad1_ u6 +a51 [net-_u48-pad2_ net-_u49-pad2_ ] net-_u58-pad3_ u58 +a52 net-_u34-pad6_ net-_u48-pad2_ u48 +a53 net-_u35-pad7_ net-_u49-pad2_ u49 +a54 [net-_u50-pad2_ net-_u51-pad2_ ] net-_u59-pad3_ u59 +a55 net-_u34-pad7_ net-_u50-pad2_ u50 +a56 net-_u35-pad7_ net-_u51-pad2_ u51 +a57 [net-_u56-pad3_ net-_u53-pad3_ ] net-_u61-pad3_ u61 +a58 [net-_u61-pad3_ net-_u7-pad2_ ] net-_u1-pad9_ u77 +a59 [net-_u56-pad3_ net-_u52-pad3_ ] net-_u60-pad3_ u60 +a60 [net-_u60-pad3_ net-_u7-pad2_ ] net-_u1-pad8_ u76 +a61 [net-_u56-pad3_ net-_u55-pad3_ ] net-_u63-pad3_ u63 +a62 [net-_u63-pad3_ net-_u7-pad2_ ] net-_u1-pad11_ u79 +a63 [net-_u56-pad3_ net-_u54-pad3_ ] net-_u62-pad3_ u62 +a64 [net-_u62-pad3_ net-_u7-pad2_ ] net-_u1-pad10_ u78 +a65 [net-_u57-pad3_ net-_u53-pad3_ ] net-_u65-pad3_ u65 +a66 [net-_u65-pad3_ net-_u7-pad2_ ] net-_u1-pad13_ u81 +a67 [net-_u57-pad3_ net-_u52-pad3_ ] net-_u64-pad3_ u64 +a68 [net-_u64-pad3_ net-_u7-pad2_ ] net-_u1-pad12_ u80 +a69 [net-_u57-pad3_ net-_u55-pad3_ ] net-_u67-pad3_ u67 +a70 [net-_u67-pad3_ net-_u7-pad2_ ] net-_u1-pad15_ u83 +a71 [net-_u57-pad3_ net-_u54-pad3_ ] net-_u66-pad3_ u66 +a72 [net-_u66-pad3_ net-_u7-pad2_ ] net-_u1-pad14_ u82 +a73 [net-_u58-pad3_ net-_u53-pad3_ ] net-_u69-pad3_ u69 +a74 [net-_u69-pad3_ net-_u7-pad2_ ] net-_u1-pad17_ u85 +a75 [net-_u58-pad3_ net-_u52-pad3_ ] net-_u68-pad3_ u68 +a76 [net-_u68-pad3_ net-_u7-pad2_ ] net-_u1-pad16_ u84 +a77 [net-_u58-pad3_ net-_u55-pad3_ ] net-_u71-pad3_ u71 +a78 [net-_u71-pad3_ net-_u7-pad2_ ] net-_u1-pad19_ u87 +a79 [net-_u58-pad3_ net-_u54-pad3_ ] net-_u70-pad3_ u70 +a80 [net-_u70-pad3_ net-_u7-pad2_ ] net-_u1-pad18_ u86 +a81 [net-_u59-pad3_ net-_u53-pad3_ ] net-_u73-pad3_ u73 +a82 [net-_u73-pad3_ net-_u7-pad2_ ] net-_u1-pad21_ u89 +a83 [net-_u59-pad3_ net-_u52-pad3_ ] net-_u72-pad3_ u72 +a84 [net-_u72-pad3_ net-_u7-pad2_ ] net-_u1-pad20_ u88 +a85 [net-_u59-pad3_ net-_u55-pad3_ ] net-_u75-pad3_ u75 +a86 [net-_u75-pad3_ net-_u7-pad2_ ] net-_u1-pad23_ u91 +a87 [net-_u59-pad3_ net-_u54-pad3_ ] net-_u74-pad3_ u74 +a88 [net-_u74-pad3_ net-_u7-pad2_ ] net-_u1-pad22_ u90 +a89 net-_u1-pad3_ net-_u7-pad2_ u7 +a90 net-_u1-pad2_ net-_u11-pad1_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_srff, NgSpice Name: d_srff +.model u32 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u52 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u53 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u38 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u39 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_srff, NgSpice Name: d_srff +.model u33 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u54 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u40 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u41 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u55 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u42 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u43 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_srff, NgSpice Name: d_srff +.model u34 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u56 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u44 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u45 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u57 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u46 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u47 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_srff, NgSpice Name: d_srff +.model u35 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u58 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u48 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u49 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u59 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u50 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u51 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u61 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u77 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u60 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u76 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u63 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u79 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u62 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u78 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u65 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u81 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u64 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u80 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u67 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u83 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u66 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u82 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u69 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u85 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u68 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u84 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u71 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u87 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u70 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u86 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u73 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u89 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u72 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u88 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u75 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u91 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u74 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u90 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends CD4514BC \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4514BC/CD4514BC_Previous_Values.xml b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4514BC/CD4514BC_Previous_Values.xml new file mode 100644 index 000000000..28d799409 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4514BC/CD4514BC_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_inverterd_inverterd_andd_inverterd_inverterd_srffd_inverterd_andd_inverterd_inverterd_andd_inverterd_inverterd_andd_inverterd_inverterd_andd_inverterd_inverterd_srffd_inverterd_andd_inverterd_inverterd_andd_inverterd_inverterd_andd_inverterd_inverterd_andd_inverterd_inverterd_srffd_inverterd_andd_inverterd_inverterd_andd_inverterd_inverterd_andd_inverterd_inverterd_andd_inverterd_inverterd_srffd_inverterd_andd_inverterd_inverterd_andd_inverterd_inverterd_nandd_nandd_nandd_nandd_nandd_nandd_nandd_nandd_nandd_nandd_nandd_nandd_nandd_nandd_nandd_nandd_nandd_nandd_nandd_nandd_nandd_nandd_nandd_nandd_nandd_nandd_nandd_nandd_nandd_nandd_nandd_nandd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_invertertruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4514BC/analysis b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4514BC/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4514BC/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4518/CD4518-cache.lib b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4518/CD4518-cache.lib new file mode 100644 index 000000000..c54a21ce2 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4518/CD4518-cache.lib @@ -0,0 +1,142 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_buffer +# +DEF d_buffer U 0 40 Y Y 1 F N +F0 "U" 0 -50 60 H V C CNN +F1 "d_buffer" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N +X IN 1 -500 0 200 R 50 50 1 1 I +X OUT 2 650 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_flip_flop +# +DEF d_flip_flop U 0 40 Y Y 1 F N +F0 "U" 2850 1800 60 H V C CNN +F1 "d_flip_flop" 2850 2000 60 H V C CNN +F2 "" 2850 1950 60 H V C CNN +F3 "" 2850 1950 60 H V C CNN +DRAW +S 2350 2100 3350 1500 0 1 0 N +X clk0 1 2150 1900 200 R 50 50 1 1 I +X d0 2 2150 1800 200 R 50 50 1 1 I +X reset0 3 2150 1700 200 R 50 50 1 1 I +X q0 4 3550 1900 200 L 50 50 1 1 O +X q_bar0 5 3550 1800 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4518/CD4518.cir b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4518/CD4518.cir new file mode 100644 index 000000000..9d56c2559 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4518/CD4518.cir @@ -0,0 +1,60 @@ +* C:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\CD4518\CD4518.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/30/25 13:46:23 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U7 Net-_U1-Pad2_ Net-_U4-Pad2_ Net-_U34-Pad1_ d_nand +U8 Net-_U34-Pad1_ Net-_U16-Pad1_ d_inverter +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_and +U30 Net-_U27-Pad2_ Net-_U28-Pad2_ Net-_U30-Pad3_ d_and +U27 Net-_U25-Pad2_ Net-_U27-Pad2_ d_inverter +U28 Net-_U18-Pad2_ Net-_U28-Pad2_ d_inverter +U22 Net-_U22-Pad1_ Net-_U22-Pad2_ Net-_U22-Pad3_ d_and +U23 Net-_U23-Pad1_ Net-_U23-Pad2_ Net-_U22-Pad1_ d_and +U26 Net-_U18-Pad2_ Net-_U23-Pad1_ d_inverter +U24 Net-_U10-Pad1_ Net-_U23-Pad2_ d_inverter +U38 Net-_U36-Pad3_ Net-_U38-Pad2_ Net-_U38-Pad3_ d_and +U36 Net-_U34-Pad2_ Net-_U36-Pad2_ Net-_U36-Pad3_ d_and +U34 Net-_U34-Pad1_ Net-_U34-Pad2_ d_inverter +U37 Net-_U10-Pad1_ Net-_U36-Pad2_ d_inverter +U39 Net-_U30-Pad3_ Net-_U17-Pad1_ Net-_U39-Pad3_ d_nor +U42 Net-_U41-Pad2_ Net-_U17-Pad1_ d_buffer +U41 Net-_U29-Pad2_ Net-_U41-Pad2_ d_inverter +U6 Net-_U5-Pad2_ Net-_U18-Pad3_ d_buffer +U5 Net-_U3-Pad2_ Net-_U5-Pad2_ d_inverter +U3 Net-_U1-Pad3_ Net-_U3-Pad2_ d_inverter +U10 Net-_U10-Pad1_ Net-_U1-Pad8_ d_buffer +U11 Net-_U11-Pad1_ Net-_U10-Pad1_ d_inverter +U12 Net-_U12-Pad1_ Net-_U11-Pad1_ d_inverter +U19 Net-_U19-Pad1_ Net-_U1-Pad7_ d_buffer +U20 Net-_U20-Pad1_ Net-_U19-Pad1_ d_inverter +U21 Net-_U18-Pad4_ Net-_U20-Pad1_ d_inverter +U31 Net-_U31-Pad1_ Net-_U1-Pad6_ d_buffer +U32 Net-_U32-Pad1_ Net-_U31-Pad1_ d_inverter +U33 Net-_U25-Pad4_ Net-_U32-Pad1_ d_inverter +U43 Net-_U43-Pad1_ Net-_U1-Pad5_ d_buffer +U44 Net-_U44-Pad1_ Net-_U43-Pad1_ d_inverter +U45 Net-_U29-Pad4_ Net-_U44-Pad1_ d_inverter +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U13-Pad1_ d_and +U17 Net-_U17-Pad1_ Net-_U14-Pad1_ d_inverter +U15 Net-_U10-Pad1_ Net-_U14-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ ? Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ PORT +U4 Net-_U2-Pad2_ Net-_U4-Pad2_ d_buffer +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter +U46 Net-_U34-Pad1_ Net-_U13-Pad2_ d_inverter +U47 Net-_U34-Pad1_ Net-_U22-Pad2_ d_inverter +U48 Net-_U39-Pad3_ Net-_U38-Pad2_ d_inverter +U16 Net-_U16-Pad1_ Net-_U16-Pad2_ d_buffer +U9 Net-_U35-Pad2_ Net-_U9-Pad2_ Net-_U18-Pad3_ Net-_U12-Pad1_ Net-_U9-Pad2_ d_flip_flop +U18 Net-_U18-Pad1_ Net-_U18-Pad2_ Net-_U18-Pad3_ Net-_U18-Pad4_ Net-_U18-Pad2_ d_flip_flop +U25 Net-_U25-Pad1_ Net-_U25-Pad2_ Net-_U18-Pad3_ Net-_U25-Pad4_ Net-_U25-Pad2_ d_flip_flop +U29 Net-_U29-Pad1_ Net-_U29-Pad2_ Net-_U18-Pad3_ Net-_U29-Pad4_ Net-_U29-Pad2_ d_flip_flop +U35 Net-_U16-Pad2_ Net-_U35-Pad2_ d_inverter +U40 Net-_U13-Pad3_ Net-_U18-Pad1_ d_inverter +U49 Net-_U22-Pad3_ Net-_U25-Pad1_ d_inverter +U50 Net-_U38-Pad3_ Net-_U29-Pad1_ d_inverter + +.end diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4518/CD4518.cir.out b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4518/CD4518.cir.out new file mode 100644 index 000000000..4e9208f33 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4518/CD4518.cir.out @@ -0,0 +1,188 @@ +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\cd4518\cd4518.cir + +* u9 net-_u9-pad1_ net-_u8-pad2_ net-_u1-pad4_ net-_u18-pad4_ net-_u12-pad1_ net-_u9-pad1_ d_dff +* u18 net-_u18-pad1_ net-_u13-pad3_ net-_u1-pad4_ net-_u18-pad4_ net-_u18-pad5_ net-_u18-pad1_ d_dff +* u29 net-_u27-pad1_ net-_u22-pad3_ net-_u1-pad4_ net-_u18-pad4_ net-_u29-pad5_ net-_u27-pad1_ d_dff +* u40 net-_u40-pad1_ net-_u38-pad3_ net-_u1-pad4_ net-_u18-pad4_ net-_u40-pad5_ net-_u40-pad1_ d_dff +* u7 net-_u1-pad3_ net-_u4-pad2_ net-_u13-pad2_ d_nand +* u8 net-_u13-pad2_ net-_u8-pad2_ d_inverter +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_and +* u30 net-_u27-pad2_ net-_u28-pad2_ net-_u30-pad3_ d_and +* u16 net-_u14-pad3_ net-_u13-pad1_ d_inverter +* u27 net-_u27-pad1_ net-_u27-pad2_ d_inverter +* u28 net-_u18-pad1_ net-_u28-pad2_ d_inverter +* u22 net-_u22-pad1_ net-_u13-pad2_ net-_u22-pad3_ d_and +* u23 net-_u23-pad1_ net-_u23-pad2_ net-_u23-pad3_ d_and +* u25 net-_u23-pad3_ net-_u22-pad1_ d_inverter +* u26 net-_u18-pad1_ net-_u23-pad1_ d_inverter +* u24 net-_u10-pad1_ net-_u23-pad2_ d_inverter +* u38 net-_u35-pad2_ net-_u38-pad2_ net-_u38-pad3_ d_and +* u36 net-_u34-pad2_ net-_u36-pad2_ net-_u35-pad1_ d_and +* u35 net-_u35-pad1_ net-_u35-pad2_ d_inverter +* u34 net-_u13-pad2_ net-_u34-pad2_ d_inverter +* u37 net-_u10-pad1_ net-_u36-pad2_ d_inverter +* u39 net-_u30-pad3_ net-_u17-pad1_ net-_u38-pad2_ d_nor +* u42 net-_u41-pad2_ net-_u17-pad1_ d_buffer +* u41 net-_u40-pad1_ net-_u41-pad2_ d_inverter +* u6 net-_u5-pad2_ net-_u18-pad4_ d_buffer +* u5 net-_u3-pad2_ net-_u5-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u10 net-_u10-pad1_ net-_u1-pad5_ d_buffer +* u11 net-_u11-pad1_ net-_u10-pad1_ d_inverter +* u12 net-_u12-pad1_ net-_u11-pad1_ d_inverter +* u19 net-_u19-pad1_ net-_u1-pad6_ d_buffer +* u20 net-_u20-pad1_ net-_u19-pad1_ d_inverter +* u21 net-_u18-pad5_ net-_u20-pad1_ d_inverter +* u31 net-_u31-pad1_ net-_u1-pad7_ d_buffer +* u32 net-_u32-pad1_ net-_u31-pad1_ d_inverter +* u33 net-_u29-pad5_ net-_u32-pad1_ d_inverter +* u43 net-_u43-pad1_ net-_u1-pad8_ d_buffer +* u44 net-_u44-pad1_ net-_u43-pad1_ d_inverter +* u45 net-_u40-pad5_ net-_u44-pad1_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_and +* u17 net-_u17-pad1_ net-_u14-pad1_ d_inverter +* u15 net-_u10-pad1_ net-_u14-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ port +* u4 net-_u2-pad2_ net-_u4-pad2_ d_buffer +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +a1 net-_u9-pad1_ net-_u8-pad2_ net-_u1-pad4_ net-_u18-pad4_ net-_u12-pad1_ net-_u9-pad1_ u9 +a2 net-_u18-pad1_ net-_u13-pad3_ net-_u1-pad4_ net-_u18-pad4_ net-_u18-pad5_ net-_u18-pad1_ u18 +a3 net-_u27-pad1_ net-_u22-pad3_ net-_u1-pad4_ net-_u18-pad4_ net-_u29-pad5_ net-_u27-pad1_ u29 +a4 net-_u40-pad1_ net-_u38-pad3_ net-_u1-pad4_ net-_u18-pad4_ net-_u40-pad5_ net-_u40-pad1_ u40 +a5 [net-_u1-pad3_ net-_u4-pad2_ ] net-_u13-pad2_ u7 +a6 net-_u13-pad2_ net-_u8-pad2_ u8 +a7 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a8 [net-_u27-pad2_ net-_u28-pad2_ ] net-_u30-pad3_ u30 +a9 net-_u14-pad3_ net-_u13-pad1_ u16 +a10 net-_u27-pad1_ net-_u27-pad2_ u27 +a11 net-_u18-pad1_ net-_u28-pad2_ u28 +a12 [net-_u22-pad1_ net-_u13-pad2_ ] net-_u22-pad3_ u22 +a13 [net-_u23-pad1_ net-_u23-pad2_ ] net-_u23-pad3_ u23 +a14 net-_u23-pad3_ net-_u22-pad1_ u25 +a15 net-_u18-pad1_ net-_u23-pad1_ u26 +a16 net-_u10-pad1_ net-_u23-pad2_ u24 +a17 [net-_u35-pad2_ net-_u38-pad2_ ] net-_u38-pad3_ u38 +a18 [net-_u34-pad2_ net-_u36-pad2_ ] net-_u35-pad1_ u36 +a19 net-_u35-pad1_ net-_u35-pad2_ u35 +a20 net-_u13-pad2_ net-_u34-pad2_ u34 +a21 net-_u10-pad1_ net-_u36-pad2_ u37 +a22 [net-_u30-pad3_ net-_u17-pad1_ ] net-_u38-pad2_ u39 +a23 net-_u41-pad2_ net-_u17-pad1_ u42 +a24 net-_u40-pad1_ net-_u41-pad2_ u41 +a25 net-_u5-pad2_ net-_u18-pad4_ u6 +a26 net-_u3-pad2_ net-_u5-pad2_ u5 +a27 net-_u1-pad2_ net-_u3-pad2_ u3 +a28 net-_u10-pad1_ net-_u1-pad5_ u10 +a29 net-_u11-pad1_ net-_u10-pad1_ u11 +a30 net-_u12-pad1_ net-_u11-pad1_ u12 +a31 net-_u19-pad1_ net-_u1-pad6_ u19 +a32 net-_u20-pad1_ net-_u19-pad1_ u20 +a33 net-_u18-pad5_ net-_u20-pad1_ u21 +a34 net-_u31-pad1_ net-_u1-pad7_ u31 +a35 net-_u32-pad1_ net-_u31-pad1_ u32 +a36 net-_u29-pad5_ net-_u32-pad1_ u33 +a37 net-_u43-pad1_ net-_u1-pad8_ u43 +a38 net-_u44-pad1_ net-_u43-pad1_ u44 +a39 net-_u40-pad5_ net-_u44-pad1_ u45 +a40 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a41 net-_u17-pad1_ net-_u14-pad1_ u17 +a42 net-_u10-pad1_ net-_u14-pad2_ u15 +a43 net-_u2-pad2_ net-_u4-pad2_ u4 +a44 net-_u1-pad1_ net-_u2-pad2_ u2 +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u9 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u18 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u29 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u40 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u38 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u39 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u42 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u41 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u6 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u10 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u19 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u31 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u43 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u44 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u45 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u4 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4518/CD4518.pro b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4518/CD4518.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4518/CD4518.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4518/CD4518.sch b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4518/CD4518.sch new file mode 100644 index 000000000..c75c77d51 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4518/CD4518.sch @@ -0,0 +1,984 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:CD4518-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_nand U7 +U 1 1 682DA47C +P 2550 4350 +F 0 "U7" H 2550 4350 60 0000 C CNN +F 1 "d_nand" H 2600 4450 60 0000 C CNN +F 2 "" H 2550 4350 60 0000 C CNN +F 3 "" H 2550 4350 60 0000 C CNN + 1 2550 4350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U8 +U 1 1 682DA642 +P 3000 3800 +F 0 "U8" H 3000 3700 60 0000 C CNN +F 1 "d_inverter" H 3000 3950 60 0000 C CNN +F 2 "" H 3050 3750 60 0000 C CNN +F 3 "" H 3050 3750 60 0000 C CNN + 1 3000 3800 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U13 +U 1 1 682DA6A6 +P 4150 3200 +F 0 "U13" H 4150 3200 60 0000 C CNN +F 1 "d_and" H 4200 3300 60 0000 C CNN +F 2 "" H 4150 3200 60 0000 C CNN +F 3 "" H 4150 3200 60 0000 C CNN + 1 4150 3200 + 0 1 -1 0 +$EndComp +$Comp +L d_and U30 +U 1 1 682DA719 +P 7350 6450 +F 0 "U30" H 7350 6450 60 0000 C CNN +F 1 "d_and" H 7400 6550 60 0000 C CNN +F 2 "" H 7350 6450 60 0000 C CNN +F 3 "" H 7350 6450 60 0000 C CNN + 1 7350 6450 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U27 +U 1 1 682DAA95 +P 6550 6350 +F 0 "U27" H 6550 6250 60 0000 C CNN +F 1 "d_inverter" H 6550 6500 60 0000 C CNN +F 2 "" H 6600 6300 60 0000 C CNN +F 3 "" H 6600 6300 60 0000 C CNN + 1 6550 6350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U28 +U 1 1 682DAAFE +P 6550 6450 +F 0 "U28" H 6550 6350 60 0000 C CNN +F 1 "d_inverter" H 6550 6600 60 0000 C CNN +F 2 "" H 6600 6400 60 0000 C CNN +F 3 "" H 6600 6400 60 0000 C CNN + 1 6550 6450 + 1 0 0 -1 +$EndComp +$Comp +L d_and U22 +U 1 1 682DAC97 +P 6050 3250 +F 0 "U22" H 6050 3250 60 0000 C CNN +F 1 "d_and" H 6100 3350 60 0000 C CNN +F 2 "" H 6050 3250 60 0000 C CNN +F 3 "" H 6050 3250 60 0000 C CNN + 1 6050 3250 + 0 1 -1 0 +$EndComp +$Comp +L d_and U23 +U 1 1 682DAC9D +P 6100 4900 +F 0 "U23" H 6100 4900 60 0000 C CNN +F 1 "d_and" H 6150 5000 60 0000 C CNN +F 2 "" H 6100 4900 60 0000 C CNN +F 3 "" H 6100 4900 60 0000 C CNN + 1 6100 4900 + 0 1 -1 0 +$EndComp +$Comp +L d_inverter U26 +U 1 1 682DACA9 +P 6200 5700 +F 0 "U26" H 6200 5600 60 0000 C CNN +F 1 "d_inverter" H 6200 5850 60 0000 C CNN +F 2 "" H 6250 5650 60 0000 C CNN +F 3 "" H 6250 5650 60 0000 C CNN + 1 6200 5700 + 0 1 -1 0 +$EndComp +$Comp +L d_inverter U24 +U 1 1 682DACAF +P 6100 5700 +F 0 "U24" H 6100 5600 60 0000 C CNN +F 1 "d_inverter" H 6100 5850 60 0000 C CNN +F 2 "" H 6150 5650 60 0000 C CNN +F 3 "" H 6150 5650 60 0000 C CNN + 1 6100 5700 + 0 1 -1 0 +$EndComp +$Comp +L d_and U38 +U 1 1 682DB12B +P 8000 3200 +F 0 "U38" H 8000 3200 60 0000 C CNN +F 1 "d_and" H 8050 3300 60 0000 C CNN +F 2 "" H 8000 3200 60 0000 C CNN +F 3 "" H 8000 3200 60 0000 C CNN + 1 8000 3200 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U36 +U 1 1 682DB131 +P 7950 4850 +F 0 "U36" H 7950 4850 60 0000 C CNN +F 1 "d_and" H 8000 4950 60 0000 C CNN +F 2 "" H 7950 4850 60 0000 C CNN +F 3 "" H 7950 4850 60 0000 C CNN + 1 7950 4850 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U34 +U 1 1 682DB13D +P 7850 5650 +F 0 "U34" H 7850 5550 60 0000 C CNN +F 1 "d_inverter" H 7850 5800 60 0000 C CNN +F 2 "" H 7900 5600 60 0000 C CNN +F 3 "" H 7900 5600 60 0000 C CNN + 1 7850 5650 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U37 +U 1 1 682DB143 +P 7950 5650 +F 0 "U37" H 7950 5550 60 0000 C CNN +F 1 "d_inverter" H 7950 5800 60 0000 C CNN +F 2 "" H 8000 5600 60 0000 C CNN +F 3 "" H 8000 5600 60 0000 C CNN + 1 7950 5650 + 0 -1 -1 0 +$EndComp +$Comp +L d_nor U39 +U 1 1 682DB1C3 +P 8550 5850 +F 0 "U39" H 8550 5850 60 0000 C CNN +F 1 "d_nor" H 8600 5950 60 0000 C CNN +F 2 "" H 8550 5850 60 0000 C CNN +F 3 "" H 8550 5850 60 0000 C CNN + 1 8550 5850 + 0 -1 -1 0 +$EndComp +$Comp +L d_buffer U42 +U 1 1 682DBC67 +P 9400 4800 +F 0 "U42" H 9400 4750 60 0000 C CNN +F 1 "d_buffer" H 9400 4850 60 0000 C CNN +F 2 "" H 9400 4800 60 0000 C CNN +F 3 "" H 9400 4800 60 0000 C CNN + 1 9400 4800 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U41 +U 1 1 682DBD2C +P 9400 3900 +F 0 "U41" H 9400 3800 60 0000 C CNN +F 1 "d_inverter" H 9400 4050 60 0000 C CNN +F 2 "" H 9450 3850 60 0000 C CNN +F 3 "" H 9450 3850 60 0000 C CNN + 1 9400 3900 + 0 1 1 0 +$EndComp +$Comp +L d_buffer U6 +U 1 1 682DC256 +P 1900 2650 +F 0 "U6" H 1900 2600 60 0000 C CNN +F 1 "d_buffer" H 1900 2700 60 0000 C CNN +F 2 "" H 1900 2650 60 0000 C CNN +F 3 "" H 1900 2650 60 0000 C CNN + 1 1900 2650 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 682DC25C +P 1000 2650 +F 0 "U5" H 1000 2550 60 0000 C CNN +F 1 "d_inverter" H 1000 2800 60 0000 C CNN +F 2 "" H 1050 2600 60 0000 C CNN +F 3 "" H 1050 2600 60 0000 C CNN + 1 1000 2650 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 682DC298 +P 300 2650 +F 0 "U3" H 300 2550 60 0000 C CNN +F 1 "d_inverter" H 300 2800 60 0000 C CNN +F 2 "" H 350 2600 60 0000 C CNN +F 3 "" H 350 2600 60 0000 C CNN + 1 300 2650 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U10 +U 1 1 682DCB9E +P 4000 -500 +F 0 "U10" H 4000 -550 60 0000 C CNN +F 1 "d_buffer" H 4000 -450 60 0000 C CNN +F 2 "" H 4000 -500 60 0000 C CNN +F 3 "" H 4000 -500 60 0000 C CNN + 1 4000 -500 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U11 +U 1 1 682DCBA4 +P 4000 400 +F 0 "U11" H 4000 300 60 0000 C CNN +F 1 "d_inverter" H 4000 550 60 0000 C CNN +F 2 "" H 4050 350 60 0000 C CNN +F 3 "" H 4050 350 60 0000 C CNN + 1 4000 400 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U12 +U 1 1 682DCBAA +P 4000 1100 +F 0 "U12" H 4000 1000 60 0000 C CNN +F 1 "d_inverter" H 4000 1250 60 0000 C CNN +F 2 "" H 4050 1050 60 0000 C CNN +F 3 "" H 4050 1050 60 0000 C CNN + 1 4000 1100 + 0 -1 -1 0 +$EndComp +$Comp +L d_buffer U19 +U 1 1 682DCF41 +P 5800 -550 +F 0 "U19" H 5800 -600 60 0000 C CNN +F 1 "d_buffer" H 5800 -500 60 0000 C CNN +F 2 "" H 5800 -550 60 0000 C CNN +F 3 "" H 5800 -550 60 0000 C CNN + 1 5800 -550 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U20 +U 1 1 682DCF47 +P 5800 350 +F 0 "U20" H 5800 250 60 0000 C CNN +F 1 "d_inverter" H 5800 500 60 0000 C CNN +F 2 "" H 5850 300 60 0000 C CNN +F 3 "" H 5850 300 60 0000 C CNN + 1 5800 350 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U21 +U 1 1 682DCF4D +P 5800 1050 +F 0 "U21" H 5800 950 60 0000 C CNN +F 1 "d_inverter" H 5800 1200 60 0000 C CNN +F 2 "" H 5850 1000 60 0000 C CNN +F 3 "" H 5850 1000 60 0000 C CNN + 1 5800 1050 + 0 -1 -1 0 +$EndComp +$Comp +L d_buffer U31 +U 1 1 682DCFB8 +P 7750 -700 +F 0 "U31" H 7750 -750 60 0000 C CNN +F 1 "d_buffer" H 7750 -650 60 0000 C CNN +F 2 "" H 7750 -700 60 0000 C CNN +F 3 "" H 7750 -700 60 0000 C CNN + 1 7750 -700 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U32 +U 1 1 682DCFBE +P 7750 200 +F 0 "U32" H 7750 100 60 0000 C CNN +F 1 "d_inverter" H 7750 350 60 0000 C CNN +F 2 "" H 7800 150 60 0000 C CNN +F 3 "" H 7800 150 60 0000 C CNN + 1 7750 200 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U33 +U 1 1 682DCFC4 +P 7750 900 +F 0 "U33" H 7750 800 60 0000 C CNN +F 1 "d_inverter" H 7750 1050 60 0000 C CNN +F 2 "" H 7800 850 60 0000 C CNN +F 3 "" H 7800 850 60 0000 C CNN + 1 7750 900 + 0 -1 -1 0 +$EndComp +$Comp +L d_buffer U43 +U 1 1 682DD089 +P 9450 -600 +F 0 "U43" H 9450 -650 60 0000 C CNN +F 1 "d_buffer" H 9450 -550 60 0000 C CNN +F 2 "" H 9450 -600 60 0000 C CNN +F 3 "" H 9450 -600 60 0000 C CNN + 1 9450 -600 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U44 +U 1 1 682DD08F +P 9450 300 +F 0 "U44" H 9450 200 60 0000 C CNN +F 1 "d_inverter" H 9450 450 60 0000 C CNN +F 2 "" H 9500 250 60 0000 C CNN +F 3 "" H 9500 250 60 0000 C CNN + 1 9450 300 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U45 +U 1 1 682DD095 +P 9450 1000 +F 0 "U45" H 9450 900 60 0000 C CNN +F 1 "d_inverter" H 9450 1150 60 0000 C CNN +F 2 "" H 9500 950 60 0000 C CNN +F 3 "" H 9500 950 60 0000 C CNN + 1 9450 1000 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U14 +U 1 1 682DE652 +P 4200 4850 +F 0 "U14" H 4200 4850 60 0000 C CNN +F 1 "d_and" H 4250 4950 60 0000 C CNN +F 2 "" H 4200 4850 60 0000 C CNN +F 3 "" H 4200 4850 60 0000 C CNN + 1 4200 4850 + 0 1 -1 0 +$EndComp +$Comp +L d_inverter U17 +U 1 1 682DE658 +P 4300 5650 +F 0 "U17" H 4300 5550 60 0000 C CNN +F 1 "d_inverter" H 4300 5800 60 0000 C CNN +F 2 "" H 4350 5600 60 0000 C CNN +F 3 "" H 4350 5600 60 0000 C CNN + 1 4300 5650 + 0 1 -1 0 +$EndComp +$Comp +L d_inverter U15 +U 1 1 682DE65E +P 4200 5650 +F 0 "U15" H 4200 5550 60 0000 C CNN +F 1 "d_inverter" H 4200 5800 60 0000 C CNN +F 2 "" H 4250 5600 60 0000 C CNN +F 3 "" H 4250 5600 60 0000 C CNN + 1 4200 5650 + 0 1 -1 0 +$EndComp +$Comp +L PORT U1 +U 1 1 682E8A0B +P -1000 4350 +F 0 "U1" H -950 4450 30 0000 C CNN +F 1 "PORT" H -1000 4350 30 0000 C CNN +F 2 "" H -1000 4350 60 0000 C CNN +F 3 "" H -1000 4350 60 0000 C CNN + 1 -1000 4350 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U4 +U 1 1 682E917E +P 600 4350 +F 0 "U4" H 600 4300 60 0000 C CNN +F 1 "d_buffer" H 600 4400 60 0000 C CNN +F 2 "" H 600 4350 60 0000 C CNN +F 3 "" H 600 4350 60 0000 C CNN + 1 600 4350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 682E9184 +P -300 4350 +F 0 "U2" H -300 4250 60 0000 C CNN +F 1 "d_inverter" H -300 4500 60 0000 C CNN +F 2 "" H -250 4300 60 0000 C CNN +F 3 "" H -250 4300 60 0000 C CNN + 1 -300 4350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 682E97F6 +P -400 2650 +F 0 "U1" H -350 2750 30 0000 C CNN +F 1 "PORT" H -400 2650 30 0000 C CNN +F 2 "" H -400 2650 60 0000 C CNN +F 3 "" H -400 2650 60 0000 C CNN + 3 -400 2650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 682E997D +P 1700 4250 +F 0 "U1" H 1750 4350 30 0000 C CNN +F 1 "PORT" H 1700 4250 30 0000 C CNN +F 2 "" H 1700 4250 60 0000 C CNN +F 3 "" H 1700 4250 60 0000 C CNN + 2 1700 4250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 682E9C26 +P 4000 -1550 +F 0 "U1" H 4050 -1450 30 0000 C CNN +F 1 "PORT" H 4000 -1550 30 0000 C CNN +F 2 "" H 4000 -1550 60 0000 C CNN +F 3 "" H 4000 -1550 60 0000 C CNN + 8 4000 -1550 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 682EA353 +P 5800 -1650 +F 0 "U1" H 5850 -1550 30 0000 C CNN +F 1 "PORT" H 5800 -1650 30 0000 C CNN +F 2 "" H 5800 -1650 60 0000 C CNN +F 3 "" H 5800 -1650 60 0000 C CNN + 7 5800 -1650 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 6 1 682EA45C +P 7750 -1700 +F 0 "U1" H 7800 -1600 30 0000 C CNN +F 1 "PORT" H 7750 -1700 30 0000 C CNN +F 2 "" H 7750 -1700 60 0000 C CNN +F 3 "" H 7750 -1700 60 0000 C CNN + 6 7750 -1700 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 5 1 682EA703 +P 9450 -1600 +F 0 "U1" H 9500 -1500 30 0000 C CNN +F 1 "PORT" H 9450 -1600 30 0000 C CNN +F 2 "" H 9450 -1600 60 0000 C CNN +F 3 "" H 9450 -1600 60 0000 C CNN + 5 9450 -1600 + 0 1 1 0 +$EndComp +NoConn ~ 5050 1200 +NoConn ~ 3100 1250 +NoConn ~ 6950 1200 +NoConn ~ 8750 1200 +$Comp +L d_inverter U46 +U 1 1 6834DAB8 +P 4100 3950 +F 0 "U46" H 4100 3850 60 0000 C CNN +F 1 "d_inverter" H 4100 4100 60 0000 C CNN +F 2 "" H 4150 3900 60 0000 C CNN +F 3 "" H 4150 3900 60 0000 C CNN + 1 4100 3950 + 0 1 -1 0 +$EndComp +$Comp +L d_inverter U47 +U 1 1 6834DF55 +P 5900 4000 +F 0 "U47" H 5900 3900 60 0000 C CNN +F 1 "d_inverter" H 5900 4150 60 0000 C CNN +F 2 "" H 5950 3950 60 0000 C CNN +F 3 "" H 5950 3950 60 0000 C CNN + 1 5900 4000 + 0 1 -1 0 +$EndComp +$Comp +L d_inverter U48 +U 1 1 6834E641 +P 8500 4250 +F 0 "U48" H 8500 4150 60 0000 C CNN +F 1 "d_inverter" H 8500 4400 60 0000 C CNN +F 2 "" H 8550 4200 60 0000 C CNN +F 3 "" H 8550 4200 60 0000 C CNN + 1 8500 4250 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 2550 2650 8750 2650 +Wire Wire Line + 8750 2650 8750 2450 +Wire Wire Line + 3100 2400 3100 2650 +Connection ~ 3100 2650 +Wire Wire Line + 5050 2450 5050 2650 +Connection ~ 5050 2650 +Wire Wire Line + 6950 2450 6950 2650 +Connection ~ 6950 2650 +Wire Wire Line + 2550 1550 2500 1550 +Wire Wire Line + 5650 1800 5650 5850 +Wire Wire Line + 7500 2100 7500 3200 +Wire Wire Line + 9400 1800 9400 3600 +Wire Wire Line + 4000 1550 4000 1400 +Wire Wire Line + 5600 1500 5800 1500 +Wire Wire Line + 5800 1500 5800 1350 +Wire Wire Line + 7750 1500 7750 1200 +Wire Wire Line + 9450 1300 9450 1700 +Wire Wire Line + 1250 4350 2100 4350 +Wire Wire Line + 3000 4100 3000 4300 +Wire Wire Line + 3000 4300 4150 4300 +Wire Wire Line + 4150 4350 7550 4350 +Connection ~ 4150 4300 +Wire Wire Line + 4250 3650 4250 4400 +Wire Wire Line + 6150 3700 6150 4450 +Wire Wire Line + 7900 3650 7900 4400 +Wire Wire Line + 9400 4200 9400 4300 +Wire Wire Line + 4000 0 4000 100 +Wire Wire Line + 5800 -50 5800 50 +Wire Wire Line + 7750 -200 7750 -100 +Wire Wire Line + 9450 -100 9450 0 +Wire Wire Line + 4000 700 4000 800 +Connection ~ 4000 50 +Wire Wire Line + 4000 50 4150 50 +Wire Wire Line + 4150 50 4150 1700 +Wire Wire Line + 4150 1700 3850 1700 +Wire Wire Line + 3850 1700 3850 6050 +Wire Wire Line + 3850 6050 7950 6050 +Wire Wire Line + 7950 6050 7950 5950 +Wire Wire Line + 7550 4350 7550 5950 +Wire Wire Line + 7550 5950 7850 5950 +Connection ~ 6050 4350 +Wire Wire Line + 4200 5950 4200 6050 +Connection ~ 4200 6050 +Wire Wire Line + 6100 6000 6100 6050 +Connection ~ 6100 6050 +Wire Wire Line + 5650 5850 5200 5850 +Wire Wire Line + 5200 6450 6250 6450 +Wire Wire Line + 5200 5850 5200 6450 +Wire Wire Line + 7500 3200 6700 3200 +Wire Wire Line + 6700 3200 6700 6150 +Wire Wire Line + 6700 6150 6150 6150 +Wire Wire Line + 6150 6150 6150 6350 +Wire Wire Line + 6150 6350 6250 6350 +Wire Wire Line + 7800 6400 8450 6400 +Wire Wire Line + 8450 6400 8450 6300 +Wire Wire Line + 8000 3650 8500 3650 +Wire Wire Line + 4300 5950 4300 6650 +Wire Wire Line + 4300 6650 9400 6650 +Wire Wire Line + 9400 6650 9400 5450 +Wire Wire Line + 8550 6300 8550 6650 +Connection ~ 8550 6650 +Wire Wire Line + 6850 6350 6900 6350 +Wire Wire Line + 6900 6450 6850 6450 +Wire Wire Line + 5800 650 5800 750 +Wire Wire Line + 7750 500 7750 600 +Wire Wire Line + 9450 600 9450 700 +Wire Wire Line + 600 2650 700 2650 +Wire Wire Line + 1300 2650 1400 2650 +Wire Wire Line + 0 4350 100 4350 +Wire Wire Line + -750 4350 -600 4350 +Wire Wire Line + 4000 -1300 4000 -1150 +Wire Wire Line + 5800 -1400 5800 -1200 +Wire Wire Line + 7750 -1450 7750 -1350 +Wire Wire Line + 9450 -1350 9450 -1250 +Wire Wire Line + -150 2650 0 2650 +Wire Wire Line + 1950 4250 2100 4250 +Wire Wire Line + 4200 5300 4200 5350 +Wire Wire Line + 4300 5300 4300 5350 +Wire Wire Line + 6100 5350 6100 5400 +Wire Wire Line + 6200 5350 6200 5400 +Wire Wire Line + 7850 5300 7850 5350 +Wire Wire Line + 7950 5300 7950 5350 +Wire Wire Line + 6200 6000 6300 6000 +Wire Wire Line + 6300 6000 6300 6100 +Wire Wire Line + 6300 6100 6050 6100 +Wire Wire Line + 6050 6100 6050 6450 +Connection ~ 6050 6450 +Wire Wire Line + 4100 4250 4150 4250 +Wire Wire Line + 4150 4250 4150 4350 +Wire Wire Line + 4100 3650 4150 3650 +Wire Wire Line + 5900 3700 6050 3700 +Wire Wire Line + 5900 4300 6050 4300 +Wire Wire Line + 6050 4300 6050 4350 +Wire Wire Line + 8500 3650 8500 3950 +Wire Wire Line + 8500 4550 8500 5400 +Connection ~ 3000 4300 +Wire Wire Line + 1950 2450 2650 2450 +Connection ~ 2000 4250 +$Comp +L d_buffer U16 +U 1 1 6835A4D0 +P 2400 3400 +F 0 "U16" H 2400 3350 60 0000 C CNN +F 1 "d_buffer" H 2400 3450 60 0000 C CNN +F 2 "" H 2400 3400 60 0000 C CNN +F 3 "" H 2400 3400 60 0000 C CNN + 1 2400 3400 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 3000 3500 2750 3500 +Wire Wire Line + 2750 3500 2750 3950 +Wire Wire Line + 2750 3950 2400 3950 +Wire Wire Line + 2400 3950 2400 3900 +Wire Wire Line + 2400 2750 2400 2550 +Wire Wire Line + 2400 2550 2650 2550 +Wire Wire Line + 2650 2550 2650 2450 +$Comp +L PORT U1 +U 4 1 6835BD99 +P 1700 6300 +F 0 "U1" H 1750 6400 30 0000 C CNN +F 1 "PORT" H 1700 6300 30 0000 C CNN +F 2 "" H 1700 6300 60 0000 C CNN +F 3 "" H 1700 6300 60 0000 C CNN + 4 1700 6300 + 1 0 0 -1 +$EndComp +NoConn ~ 1950 6300 +$Comp +L d_flip_flop U9 +U 1 1 6835FA13 +P 200 3700 +F 0 "U9" H 3050 5500 60 0000 C CNN +F 1 "d_flip_flop" H 3050 5700 60 0000 C CNN +F 2 "" H 3050 5650 60 0000 C CNN +F 3 "" H 3050 5650 60 0000 C CNN + 1 200 3700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2350 1900 2200 1900 +Wire Wire Line + 2200 1900 2200 2350 +Wire Wire Line + 2200 2350 3750 2350 +Wire Wire Line + 3750 2350 3750 1900 +Wire Wire Line + 2350 2000 2350 2400 +Wire Wire Line + 2350 2400 3100 2400 +$Comp +L d_flip_flop U18 +U 1 1 683605BA +P 2100 3600 +F 0 "U18" H 4950 5400 60 0000 C CNN +F 1 "d_flip_flop" H 4950 5600 60 0000 C CNN +F 2 "" H 4950 5550 60 0000 C CNN +F 3 "" H 4950 5550 60 0000 C CNN + 1 2100 3600 + 1 0 0 -1 +$EndComp +$Comp +L d_flip_flop U25 +U 1 1 6836072E +P 4050 3600 +F 0 "U25" H 6900 5400 60 0000 C CNN +F 1 "d_flip_flop" H 6900 5600 60 0000 C CNN +F 2 "" H 6900 5550 60 0000 C CNN +F 3 "" H 6900 5550 60 0000 C CNN + 1 4050 3600 + 1 0 0 -1 +$EndComp +$Comp +L d_flip_flop U29 +U 1 1 6836091E +P 5800 3600 +F 0 "U29" H 8650 5400 60 0000 C CNN +F 1 "d_flip_flop" H 8650 5600 60 0000 C CNN +F 2 "" H 8650 5550 60 0000 C CNN +F 3 "" H 8650 5550 60 0000 C CNN + 1 5800 3600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4000 1550 3750 1550 +Wire Wire Line + 3750 1550 3750 1800 +Wire Wire Line + 4250 1900 4250 2450 +Wire Wire Line + 4250 2450 5050 2450 +Wire Wire Line + 4250 1800 4050 1800 +Wire Wire Line + 4050 1800 4050 2350 +Wire Wire Line + 4050 2350 5650 2350 +Connection ~ 5650 2350 +Wire Wire Line + 4250 1700 4200 1700 +Wire Wire Line + 6200 1700 6100 1700 +Wire Wire Line + 7950 1700 7850 1700 +Wire Wire Line + 5600 1500 5600 1600 +Wire Wire Line + 5600 1600 5650 1600 +Wire Wire Line + 5650 1600 5650 1700 +Wire Wire Line + 7600 1700 7600 1500 +Wire Wire Line + 7600 1500 7750 1500 +Wire Wire Line + 9450 1700 9350 1700 +Wire Wire Line + 9350 1800 9400 1800 +Wire Wire Line + 7600 1800 7600 2100 +Wire Wire Line + 7600 2100 7500 2100 +Wire Wire Line + 6200 1900 6200 2450 +Wire Wire Line + 6200 2450 6950 2450 +Wire Wire Line + 6200 1800 6000 1800 +Wire Wire Line + 6000 1800 6000 2350 +Wire Wire Line + 6000 2350 7500 2350 +Connection ~ 7500 2350 +Wire Wire Line + 7950 1900 7950 2050 +Wire Wire Line + 7950 2050 8050 2050 +Wire Wire Line + 8050 2050 8050 2450 +Wire Wire Line + 8050 2450 8750 2450 +Wire Wire Line + 7950 1800 7750 1800 +Wire Wire Line + 7750 1800 7750 2300 +Wire Wire Line + 7750 2300 9400 2300 +Connection ~ 9400 2300 +$Comp +L d_inverter U35 +U 1 1 6839826D +P 1950 2150 +F 0 "U35" H 1950 2050 60 0000 C CNN +F 1 "d_inverter" H 1950 2300 60 0000 C CNN +F 2 "" H 2000 2100 60 0000 C CNN +F 3 "" H 2000 2100 60 0000 C CNN + 1 1950 2150 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 1950 1850 1950 1800 +Wire Wire Line + 1950 1800 2350 1800 +$Comp +L d_inverter U40 +U 1 1 683986FB +P 4200 2150 +F 0 "U40" H 4200 2050 60 0000 C CNN +F 1 "d_inverter" H 4200 2300 60 0000 C CNN +F 2 "" H 4250 2100 60 0000 C CNN +F 3 "" H 4250 2100 60 0000 C CNN + 1 4200 2150 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 4200 1700 4200 1850 +Wire Wire Line + 4200 2450 4200 2750 +$Comp +L d_inverter U49 +U 1 1 68398C38 +P 6100 2300 +F 0 "U49" H 6100 2200 60 0000 C CNN +F 1 "d_inverter" H 6100 2450 60 0000 C CNN +F 2 "" H 6150 2250 60 0000 C CNN +F 3 "" H 6150 2250 60 0000 C CNN + 1 6100 2300 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 6100 1700 6100 2000 +Wire Wire Line + 6100 2600 6100 2800 +$Comp +L d_inverter U50 +U 1 1 68399141 +P 7850 2050 +F 0 "U50" H 7850 1950 60 0000 C CNN +F 1 "d_inverter" H 7850 2200 60 0000 C CNN +F 2 "" H 7900 2000 60 0000 C CNN +F 3 "" H 7900 2000 60 0000 C CNN + 1 7850 2050 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 7850 2350 7850 2550 +Wire Wire Line + 7850 2550 7950 2550 +Wire Wire Line + 7950 2550 7950 2750 +Wire Wire Line + 7850 1700 7850 1750 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4518/CD4518.sub b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4518/CD4518.sub new file mode 100644 index 000000000..d4756c76c --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4518/CD4518.sub @@ -0,0 +1,182 @@ +* Subcircuit CD4518 +.subckt CD4518 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\cd4518\cd4518.cir +* u9 net-_u9-pad1_ net-_u8-pad2_ net-_u1-pad4_ net-_u18-pad4_ net-_u12-pad1_ net-_u9-pad1_ d_dff +* u18 net-_u18-pad1_ net-_u13-pad3_ net-_u1-pad4_ net-_u18-pad4_ net-_u18-pad5_ net-_u18-pad1_ d_dff +* u29 net-_u27-pad1_ net-_u22-pad3_ net-_u1-pad4_ net-_u18-pad4_ net-_u29-pad5_ net-_u27-pad1_ d_dff +* u40 net-_u40-pad1_ net-_u38-pad3_ net-_u1-pad4_ net-_u18-pad4_ net-_u40-pad5_ net-_u40-pad1_ d_dff +* u7 net-_u1-pad3_ net-_u4-pad2_ net-_u13-pad2_ d_nand +* u8 net-_u13-pad2_ net-_u8-pad2_ d_inverter +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_and +* u30 net-_u27-pad2_ net-_u28-pad2_ net-_u30-pad3_ d_and +* u16 net-_u14-pad3_ net-_u13-pad1_ d_inverter +* u27 net-_u27-pad1_ net-_u27-pad2_ d_inverter +* u28 net-_u18-pad1_ net-_u28-pad2_ d_inverter +* u22 net-_u22-pad1_ net-_u13-pad2_ net-_u22-pad3_ d_and +* u23 net-_u23-pad1_ net-_u23-pad2_ net-_u23-pad3_ d_and +* u25 net-_u23-pad3_ net-_u22-pad1_ d_inverter +* u26 net-_u18-pad1_ net-_u23-pad1_ d_inverter +* u24 net-_u10-pad1_ net-_u23-pad2_ d_inverter +* u38 net-_u35-pad2_ net-_u38-pad2_ net-_u38-pad3_ d_and +* u36 net-_u34-pad2_ net-_u36-pad2_ net-_u35-pad1_ d_and +* u35 net-_u35-pad1_ net-_u35-pad2_ d_inverter +* u34 net-_u13-pad2_ net-_u34-pad2_ d_inverter +* u37 net-_u10-pad1_ net-_u36-pad2_ d_inverter +* u39 net-_u30-pad3_ net-_u17-pad1_ net-_u38-pad2_ d_nor +* u42 net-_u41-pad2_ net-_u17-pad1_ d_buffer +* u41 net-_u40-pad1_ net-_u41-pad2_ d_inverter +* u6 net-_u5-pad2_ net-_u18-pad4_ d_buffer +* u5 net-_u3-pad2_ net-_u5-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u10 net-_u10-pad1_ net-_u1-pad5_ d_buffer +* u11 net-_u11-pad1_ net-_u10-pad1_ d_inverter +* u12 net-_u12-pad1_ net-_u11-pad1_ d_inverter +* u19 net-_u19-pad1_ net-_u1-pad6_ d_buffer +* u20 net-_u20-pad1_ net-_u19-pad1_ d_inverter +* u21 net-_u18-pad5_ net-_u20-pad1_ d_inverter +* u31 net-_u31-pad1_ net-_u1-pad7_ d_buffer +* u32 net-_u32-pad1_ net-_u31-pad1_ d_inverter +* u33 net-_u29-pad5_ net-_u32-pad1_ d_inverter +* u43 net-_u43-pad1_ net-_u1-pad8_ d_buffer +* u44 net-_u44-pad1_ net-_u43-pad1_ d_inverter +* u45 net-_u40-pad5_ net-_u44-pad1_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_and +* u17 net-_u17-pad1_ net-_u14-pad1_ d_inverter +* u15 net-_u10-pad1_ net-_u14-pad2_ d_inverter +* u4 net-_u2-pad2_ net-_u4-pad2_ d_buffer +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +a1 net-_u9-pad1_ net-_u8-pad2_ net-_u1-pad4_ net-_u18-pad4_ net-_u12-pad1_ net-_u9-pad1_ u9 +a2 net-_u18-pad1_ net-_u13-pad3_ net-_u1-pad4_ net-_u18-pad4_ net-_u18-pad5_ net-_u18-pad1_ u18 +a3 net-_u27-pad1_ net-_u22-pad3_ net-_u1-pad4_ net-_u18-pad4_ net-_u29-pad5_ net-_u27-pad1_ u29 +a4 net-_u40-pad1_ net-_u38-pad3_ net-_u1-pad4_ net-_u18-pad4_ net-_u40-pad5_ net-_u40-pad1_ u40 +a5 [net-_u1-pad3_ net-_u4-pad2_ ] net-_u13-pad2_ u7 +a6 net-_u13-pad2_ net-_u8-pad2_ u8 +a7 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a8 [net-_u27-pad2_ net-_u28-pad2_ ] net-_u30-pad3_ u30 +a9 net-_u14-pad3_ net-_u13-pad1_ u16 +a10 net-_u27-pad1_ net-_u27-pad2_ u27 +a11 net-_u18-pad1_ net-_u28-pad2_ u28 +a12 [net-_u22-pad1_ net-_u13-pad2_ ] net-_u22-pad3_ u22 +a13 [net-_u23-pad1_ net-_u23-pad2_ ] net-_u23-pad3_ u23 +a14 net-_u23-pad3_ net-_u22-pad1_ u25 +a15 net-_u18-pad1_ net-_u23-pad1_ u26 +a16 net-_u10-pad1_ net-_u23-pad2_ u24 +a17 [net-_u35-pad2_ net-_u38-pad2_ ] net-_u38-pad3_ u38 +a18 [net-_u34-pad2_ net-_u36-pad2_ ] net-_u35-pad1_ u36 +a19 net-_u35-pad1_ net-_u35-pad2_ u35 +a20 net-_u13-pad2_ net-_u34-pad2_ u34 +a21 net-_u10-pad1_ net-_u36-pad2_ u37 +a22 [net-_u30-pad3_ net-_u17-pad1_ ] net-_u38-pad2_ u39 +a23 net-_u41-pad2_ net-_u17-pad1_ u42 +a24 net-_u40-pad1_ net-_u41-pad2_ u41 +a25 net-_u5-pad2_ net-_u18-pad4_ u6 +a26 net-_u3-pad2_ net-_u5-pad2_ u5 +a27 net-_u1-pad2_ net-_u3-pad2_ u3 +a28 net-_u10-pad1_ net-_u1-pad5_ u10 +a29 net-_u11-pad1_ net-_u10-pad1_ u11 +a30 net-_u12-pad1_ net-_u11-pad1_ u12 +a31 net-_u19-pad1_ net-_u1-pad6_ u19 +a32 net-_u20-pad1_ net-_u19-pad1_ u20 +a33 net-_u18-pad5_ net-_u20-pad1_ u21 +a34 net-_u31-pad1_ net-_u1-pad7_ u31 +a35 net-_u32-pad1_ net-_u31-pad1_ u32 +a36 net-_u29-pad5_ net-_u32-pad1_ u33 +a37 net-_u43-pad1_ net-_u1-pad8_ u43 +a38 net-_u44-pad1_ net-_u43-pad1_ u44 +a39 net-_u40-pad5_ net-_u44-pad1_ u45 +a40 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a41 net-_u17-pad1_ net-_u14-pad1_ u17 +a42 net-_u10-pad1_ net-_u14-pad2_ u15 +a43 net-_u2-pad2_ net-_u4-pad2_ u4 +a44 net-_u1-pad1_ net-_u2-pad2_ u2 +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u9 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u18 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u29 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u40 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u38 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u39 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u42 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u41 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u6 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u10 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u19 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u31 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u43 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u44 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u45 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u4 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends CD4518 \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4518/CD4518_Previous_Values.xml b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4518/CD4518_Previous_Values.xml new file mode 100644 index 000000000..7430d1541 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4518/CD4518_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_dffd_dffd_dffd_dffd_nandd_inverterd_andd_andd_inverterd_inverterd_inverterd_andd_andd_inverterd_inverterd_inverterd_andd_andd_inverterd_inverterd_inverterd_nord_bufferd_inverterd_bufferd_inverterd_inverterd_bufferd_inverterd_inverterd_bufferd_inverterd_inverterd_bufferd_inverterd_inverterd_bufferd_inverterd_inverterd_andd_inverterd_inverterd_bufferd_inverter \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4518/analysis b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4518/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD4518/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC374/CD54HC374-cache.lib b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC374/CD54HC374-cache.lib new file mode 100644 index 000000000..305362263 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC374/CD54HC374-cache.lib @@ -0,0 +1,91 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_dff +# +DEF d_dff U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_dff" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 350 450 -350 -400 0 1 0 N +X Din 1 -550 350 200 R 50 50 1 1 I +X Clk 2 -550 -300 200 R 50 50 1 1 I C +X Set 3 0 650 200 D 50 50 1 1 I +X Reset 4 0 -600 200 U 50 50 1 1 I +X Dout 5 550 350 200 L 50 50 1 1 O +X Ndout 6 550 -300 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_tristate +# +DEF d_tristate U 0 40 Y Y 1 F N +F0 "U" -250 250 60 H V C CNN +F1 "d_tristate" -200 450 60 H V C CNN +F2 "" -100 350 60 H V C CNN +F3 "" -100 350 60 H V C CNN +DRAW +P 4 0 1 0 -400 550 -400 150 350 350 -400 550 N +X IN 1 -600 350 200 R 50 50 1 1 I +X EN 2 -50 50 193 U 50 50 1 1 I +X OUT 3 550 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC374/CD54HC374.cir b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC374/CD54HC374.cir new file mode 100644 index 000000000..f50464021 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC374/CD54HC374.cir @@ -0,0 +1,45 @@ +* C:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\CD54HC374\CD54HC374.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/06/25 14:02:08 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U5 Net-_U1-Pad2_ Net-_U3-Pad2_ ? ? ? Net-_U5-Pad6_ d_dff +U6 Net-_U6-Pad1_ Net-_U10-Pad2_ Net-_U1-Pad10_ d_tristate +U3 Net-_U12-Pad1_ Net-_U3-Pad2_ d_inverter +U7 Net-_U5-Pad6_ Net-_U6-Pad1_ d_inverter +U4 Net-_U1-Pad18_ Net-_U10-Pad2_ d_inverter +U9 Net-_U1-Pad3_ Net-_U8-Pad2_ ? ? ? Net-_U11-Pad1_ d_dff +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U1-Pad11_ d_tristate +U8 Net-_U12-Pad1_ Net-_U8-Pad2_ d_inverter +U11 Net-_U11-Pad1_ Net-_U10-Pad1_ d_inverter +U13 Net-_U1-Pad4_ Net-_U12-Pad2_ ? ? ? Net-_U13-Pad6_ d_dff +U14 Net-_U14-Pad1_ Net-_U10-Pad2_ Net-_U1-Pad12_ d_tristate +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_inverter +U15 Net-_U13-Pad6_ Net-_U14-Pad1_ d_inverter +U17 Net-_U1-Pad5_ Net-_U16-Pad2_ ? ? ? Net-_U17-Pad6_ d_dff +U18 Net-_U18-Pad1_ Net-_U10-Pad2_ Net-_U1-Pad13_ d_tristate +U16 Net-_U12-Pad1_ Net-_U16-Pad2_ d_inverter +U19 Net-_U17-Pad6_ Net-_U18-Pad1_ d_inverter +U21 Net-_U1-Pad6_ Net-_U20-Pad2_ ? ? ? Net-_U21-Pad6_ d_dff +U22 Net-_U22-Pad1_ Net-_U10-Pad2_ Net-_U1-Pad14_ d_tristate +U20 Net-_U12-Pad1_ Net-_U20-Pad2_ d_inverter +U23 Net-_U21-Pad6_ Net-_U22-Pad1_ d_inverter +U25 Net-_U1-Pad7_ Net-_U24-Pad2_ ? ? ? Net-_U25-Pad6_ d_dff +U26 Net-_U26-Pad1_ Net-_U10-Pad2_ Net-_U1-Pad15_ d_tristate +U24 Net-_U12-Pad1_ Net-_U24-Pad2_ d_inverter +U27 Net-_U25-Pad6_ Net-_U26-Pad1_ d_inverter +U29 Net-_U1-Pad8_ Net-_U28-Pad2_ ? ? ? Net-_U29-Pad6_ d_dff +U30 Net-_U30-Pad1_ Net-_U10-Pad2_ Net-_U1-Pad16_ d_tristate +U28 Net-_U12-Pad1_ Net-_U28-Pad2_ d_inverter +U31 Net-_U29-Pad6_ Net-_U30-Pad1_ d_inverter +U33 Net-_U1-Pad9_ Net-_U32-Pad2_ ? ? ? Net-_U33-Pad6_ d_dff +U34 Net-_U34-Pad1_ Net-_U10-Pad2_ Net-_U1-Pad17_ d_tristate +U32 Net-_U12-Pad1_ Net-_U32-Pad2_ d_inverter +U35 Net-_U33-Pad6_ Net-_U34-Pad1_ d_inverter +U2 Net-_U1-Pad1_ Net-_U12-Pad1_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ PORT + +.end diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC374/CD54HC374.cir.out b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC374/CD54HC374.cir.out new file mode 100644 index 000000000..97169d65f --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC374/CD54HC374.cir.out @@ -0,0 +1,148 @@ +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\cd54hc374\cd54hc374.cir + +* u5 net-_u1-pad2_ net-_u3-pad2_ ? ? ? net-_u5-pad6_ d_dff +* u6 net-_u6-pad1_ net-_u10-pad2_ net-_u1-pad10_ d_tristate +* u3 net-_u12-pad1_ net-_u3-pad2_ d_inverter +* u7 net-_u5-pad6_ net-_u6-pad1_ d_inverter +* u4 net-_u1-pad18_ net-_u10-pad2_ d_inverter +* u9 net-_u1-pad3_ net-_u8-pad2_ ? ? ? net-_u11-pad1_ d_dff +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad11_ d_tristate +* u8 net-_u12-pad1_ net-_u8-pad2_ d_inverter +* u11 net-_u11-pad1_ net-_u10-pad1_ d_inverter +* u13 net-_u1-pad4_ net-_u12-pad2_ ? ? ? net-_u13-pad6_ d_dff +* u14 net-_u14-pad1_ net-_u10-pad2_ net-_u1-pad12_ d_tristate +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u15 net-_u13-pad6_ net-_u14-pad1_ d_inverter +* u17 net-_u1-pad5_ net-_u16-pad2_ ? ? ? net-_u17-pad6_ d_dff +* u18 net-_u18-pad1_ net-_u10-pad2_ net-_u1-pad13_ d_tristate +* u16 net-_u12-pad1_ net-_u16-pad2_ d_inverter +* u19 net-_u17-pad6_ net-_u18-pad1_ d_inverter +* u21 net-_u1-pad6_ net-_u20-pad2_ ? ? ? net-_u21-pad6_ d_dff +* u22 net-_u22-pad1_ net-_u10-pad2_ net-_u1-pad14_ d_tristate +* u20 net-_u12-pad1_ net-_u20-pad2_ d_inverter +* u23 net-_u21-pad6_ net-_u22-pad1_ d_inverter +* u25 net-_u1-pad7_ net-_u24-pad2_ ? ? ? net-_u25-pad6_ d_dff +* u26 net-_u26-pad1_ net-_u10-pad2_ net-_u1-pad15_ d_tristate +* u24 net-_u12-pad1_ net-_u24-pad2_ d_inverter +* u27 net-_u25-pad6_ net-_u26-pad1_ d_inverter +* u29 net-_u1-pad8_ net-_u28-pad2_ ? ? ? net-_u29-pad6_ d_dff +* u30 net-_u30-pad1_ net-_u10-pad2_ net-_u1-pad16_ d_tristate +* u28 net-_u12-pad1_ net-_u28-pad2_ d_inverter +* u31 net-_u29-pad6_ net-_u30-pad1_ d_inverter +* u33 net-_u1-pad9_ net-_u32-pad2_ ? ? ? net-_u33-pad6_ d_dff +* u34 net-_u34-pad1_ net-_u10-pad2_ net-_u1-pad17_ d_tristate +* u32 net-_u12-pad1_ net-_u32-pad2_ d_inverter +* u35 net-_u33-pad6_ net-_u34-pad1_ d_inverter +* u2 net-_u1-pad1_ net-_u12-pad1_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ port +a1 net-_u1-pad2_ net-_u3-pad2_ ? ? ? net-_u5-pad6_ u5 +a2 net-_u6-pad1_ net-_u10-pad2_ net-_u1-pad10_ u6 +a3 net-_u12-pad1_ net-_u3-pad2_ u3 +a4 net-_u5-pad6_ net-_u6-pad1_ u7 +a5 net-_u1-pad18_ net-_u10-pad2_ u4 +a6 net-_u1-pad3_ net-_u8-pad2_ ? ? ? net-_u11-pad1_ u9 +a7 net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad11_ u10 +a8 net-_u12-pad1_ net-_u8-pad2_ u8 +a9 net-_u11-pad1_ net-_u10-pad1_ u11 +a10 net-_u1-pad4_ net-_u12-pad2_ ? ? ? net-_u13-pad6_ u13 +a11 net-_u14-pad1_ net-_u10-pad2_ net-_u1-pad12_ u14 +a12 net-_u12-pad1_ net-_u12-pad2_ u12 +a13 net-_u13-pad6_ net-_u14-pad1_ u15 +a14 net-_u1-pad5_ net-_u16-pad2_ ? ? ? net-_u17-pad6_ u17 +a15 net-_u18-pad1_ net-_u10-pad2_ net-_u1-pad13_ u18 +a16 net-_u12-pad1_ net-_u16-pad2_ u16 +a17 net-_u17-pad6_ net-_u18-pad1_ u19 +a18 net-_u1-pad6_ net-_u20-pad2_ ? ? ? net-_u21-pad6_ u21 +a19 net-_u22-pad1_ net-_u10-pad2_ net-_u1-pad14_ u22 +a20 net-_u12-pad1_ net-_u20-pad2_ u20 +a21 net-_u21-pad6_ net-_u22-pad1_ u23 +a22 net-_u1-pad7_ net-_u24-pad2_ ? ? ? net-_u25-pad6_ u25 +a23 net-_u26-pad1_ net-_u10-pad2_ net-_u1-pad15_ u26 +a24 net-_u12-pad1_ net-_u24-pad2_ u24 +a25 net-_u25-pad6_ net-_u26-pad1_ u27 +a26 net-_u1-pad8_ net-_u28-pad2_ ? ? ? net-_u29-pad6_ u29 +a27 net-_u30-pad1_ net-_u10-pad2_ net-_u1-pad16_ u30 +a28 net-_u12-pad1_ net-_u28-pad2_ u28 +a29 net-_u29-pad6_ net-_u30-pad1_ u31 +a30 net-_u1-pad9_ net-_u32-pad2_ ? ? ? net-_u33-pad6_ u33 +a31 net-_u34-pad1_ net-_u10-pad2_ net-_u1-pad17_ u34 +a32 net-_u12-pad1_ net-_u32-pad2_ u32 +a33 net-_u33-pad6_ net-_u34-pad1_ u35 +a34 net-_u1-pad1_ net-_u12-pad1_ u2 +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u5 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u6 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u9 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u10 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u13 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u14 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u17 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u18 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u21 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u22 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u25 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u26 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u29 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u30 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u33 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u34 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC374/CD54HC374.pro b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC374/CD54HC374.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC374/CD54HC374.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC374/CD54HC374.sch b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC374/CD54HC374.sch new file mode 100644 index 000000000..fd663acd8 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC374/CD54HC374.sch @@ -0,0 +1,834 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_dff U5 +U 1 1 68427E74 +P 2250 1900 +F 0 "U5" H 2250 1900 60 0000 C CNN +F 1 "d_dff" H 2250 2050 60 0000 C CNN +F 2 "" H 2250 1900 60 0000 C CNN +F 3 "" H 2250 1900 60 0000 C CNN + 1 2250 1900 + 1 0 0 -1 +$EndComp +$Comp +L d_tristate U6 +U 1 1 68427EEB +P 2800 4400 +F 0 "U6" H 2550 4650 60 0000 C CNN +F 1 "d_tristate" H 2600 4850 60 0000 C CNN +F 2 "" H 2700 4750 60 0000 C CNN +F 3 "" H 2700 4750 60 0000 C CNN + 1 2800 4400 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U3 +U 1 1 68427F4E +P 1500 2500 +F 0 "U3" H 1500 2400 60 0000 C CNN +F 1 "d_inverter" H 1500 2650 60 0000 C CNN +F 2 "" H 1550 2450 60 0000 C CNN +F 3 "" H 1550 2450 60 0000 C CNN + 1 1500 2500 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U7 +U 1 1 68427FE5 +P 3150 3350 +F 0 "U7" H 3150 3250 60 0000 C CNN +F 1 "d_inverter" H 3150 3500 60 0000 C CNN +F 2 "" H 3200 3300 60 0000 C CNN +F 3 "" H 3200 3300 60 0000 C CNN + 1 3150 3350 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U4 +U 1 1 68428025 +P 2050 5200 +F 0 "U4" H 2050 5100 60 0000 C CNN +F 1 "d_inverter" H 2050 5350 60 0000 C CNN +F 2 "" H 2100 5150 60 0000 C CNN +F 3 "" H 2100 5150 60 0000 C CNN + 1 2050 5200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2800 2200 3150 2200 +Wire Wire Line + 3150 2200 3150 3050 +Wire Wire Line + 1500 2200 1700 2200 +Wire Wire Line + 3150 3650 3150 3800 +Wire Wire Line + 2850 4350 2550 4350 +Wire Wire Line + 3150 4950 3150 5850 +NoConn ~ 2800 1550 +NoConn ~ 2250 1250 +NoConn ~ 2250 2500 +Wire Wire Line + 1700 1550 1350 1550 +Wire Wire Line + 1350 1550 1350 900 +$Comp +L d_dff U9 +U 1 1 684284C9 +P 4600 1900 +F 0 "U9" H 4600 1900 60 0000 C CNN +F 1 "d_dff" H 4600 2050 60 0000 C CNN +F 2 "" H 4600 1900 60 0000 C CNN +F 3 "" H 4600 1900 60 0000 C CNN + 1 4600 1900 + 1 0 0 -1 +$EndComp +$Comp +L d_tristate U10 +U 1 1 684284CF +P 5150 4400 +F 0 "U10" H 4900 4650 60 0000 C CNN +F 1 "d_tristate" H 4950 4850 60 0000 C CNN +F 2 "" H 5050 4750 60 0000 C CNN +F 3 "" H 5050 4750 60 0000 C CNN + 1 5150 4400 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U8 +U 1 1 684284D5 +P 3850 2500 +F 0 "U8" H 3850 2400 60 0000 C CNN +F 1 "d_inverter" H 3850 2650 60 0000 C CNN +F 2 "" H 3900 2450 60 0000 C CNN +F 3 "" H 3900 2450 60 0000 C CNN + 1 3850 2500 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U11 +U 1 1 684284DB +P 5500 3350 +F 0 "U11" H 5500 3250 60 0000 C CNN +F 1 "d_inverter" H 5500 3500 60 0000 C CNN +F 2 "" H 5550 3300 60 0000 C CNN +F 3 "" H 5550 3300 60 0000 C CNN + 1 5500 3350 + 0 1 1 0 +$EndComp +Wire Wire Line + 5150 2200 5500 2200 +Wire Wire Line + 5500 2200 5500 3050 +Wire Wire Line + 3850 2200 4050 2200 +Wire Wire Line + 5500 3650 5500 3800 +Wire Wire Line + 5200 4350 4900 4350 +Wire Wire Line + 5500 4950 5500 5850 +NoConn ~ 5150 1550 +NoConn ~ 4600 1250 +NoConn ~ 4600 2500 +Wire Wire Line + 4050 1550 3700 1550 +Wire Wire Line + 3700 1550 3700 900 +$Comp +L d_dff U13 +U 1 1 6842883A +P 6700 1850 +F 0 "U13" H 6700 1850 60 0000 C CNN +F 1 "d_dff" H 6700 2000 60 0000 C CNN +F 2 "" H 6700 1850 60 0000 C CNN +F 3 "" H 6700 1850 60 0000 C CNN + 1 6700 1850 + 1 0 0 -1 +$EndComp +$Comp +L d_tristate U14 +U 1 1 68428840 +P 7250 4350 +F 0 "U14" H 7000 4600 60 0000 C CNN +F 1 "d_tristate" H 7050 4800 60 0000 C CNN +F 2 "" H 7150 4700 60 0000 C CNN +F 3 "" H 7150 4700 60 0000 C CNN + 1 7250 4350 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U12 +U 1 1 68428846 +P 5950 2450 +F 0 "U12" H 5950 2350 60 0000 C CNN +F 1 "d_inverter" H 5950 2600 60 0000 C CNN +F 2 "" H 6000 2400 60 0000 C CNN +F 3 "" H 6000 2400 60 0000 C CNN + 1 5950 2450 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U15 +U 1 1 6842884C +P 7600 3300 +F 0 "U15" H 7600 3200 60 0000 C CNN +F 1 "d_inverter" H 7600 3450 60 0000 C CNN +F 2 "" H 7650 3250 60 0000 C CNN +F 3 "" H 7650 3250 60 0000 C CNN + 1 7600 3300 + 0 1 1 0 +$EndComp +Wire Wire Line + 7250 2150 7600 2150 +Wire Wire Line + 7600 2150 7600 3000 +Wire Wire Line + 5950 2150 6150 2150 +Wire Wire Line + 7600 3600 7600 3750 +Wire Wire Line + 7300 4300 7000 4300 +Wire Wire Line + 7600 4900 7600 5800 +NoConn ~ 7250 1500 +NoConn ~ 6700 1200 +NoConn ~ 6700 2450 +Wire Wire Line + 6150 1500 5800 1500 +Wire Wire Line + 5800 1500 5800 850 +$Comp +L d_dff U17 +U 1 1 68428863 +P 9050 1850 +F 0 "U17" H 9050 1850 60 0000 C CNN +F 1 "d_dff" H 9050 2000 60 0000 C CNN +F 2 "" H 9050 1850 60 0000 C CNN +F 3 "" H 9050 1850 60 0000 C CNN + 1 9050 1850 + 1 0 0 -1 +$EndComp +$Comp +L d_tristate U18 +U 1 1 68428869 +P 9600 4350 +F 0 "U18" H 9350 4600 60 0000 C CNN +F 1 "d_tristate" H 9400 4800 60 0000 C CNN +F 2 "" H 9500 4700 60 0000 C CNN +F 3 "" H 9500 4700 60 0000 C CNN + 1 9600 4350 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U16 +U 1 1 6842886F +P 8300 2450 +F 0 "U16" H 8300 2350 60 0000 C CNN +F 1 "d_inverter" H 8300 2600 60 0000 C CNN +F 2 "" H 8350 2400 60 0000 C CNN +F 3 "" H 8350 2400 60 0000 C CNN + 1 8300 2450 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U19 +U 1 1 68428875 +P 9950 3300 +F 0 "U19" H 9950 3200 60 0000 C CNN +F 1 "d_inverter" H 9950 3450 60 0000 C CNN +F 2 "" H 10000 3250 60 0000 C CNN +F 3 "" H 10000 3250 60 0000 C CNN + 1 9950 3300 + 0 1 1 0 +$EndComp +Wire Wire Line + 9600 2150 9950 2150 +Wire Wire Line + 9950 2150 9950 3000 +Wire Wire Line + 8300 2150 8500 2150 +Wire Wire Line + 9950 3600 9950 3750 +Wire Wire Line + 9650 4300 9350 4300 +Wire Wire Line + 9950 4900 9950 5800 +NoConn ~ 9600 1500 +NoConn ~ 9050 1200 +NoConn ~ 9050 2450 +Wire Wire Line + 8500 1500 8150 1500 +Wire Wire Line + 8150 1500 8150 850 +$Comp +L d_dff U21 +U 1 1 68429600 +P 11550 1850 +F 0 "U21" H 11550 1850 60 0000 C CNN +F 1 "d_dff" H 11550 2000 60 0000 C CNN +F 2 "" H 11550 1850 60 0000 C CNN +F 3 "" H 11550 1850 60 0000 C CNN + 1 11550 1850 + 1 0 0 -1 +$EndComp +$Comp +L d_tristate U22 +U 1 1 68429606 +P 12100 4350 +F 0 "U22" H 11850 4600 60 0000 C CNN +F 1 "d_tristate" H 11900 4800 60 0000 C CNN +F 2 "" H 12000 4700 60 0000 C CNN +F 3 "" H 12000 4700 60 0000 C CNN + 1 12100 4350 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U20 +U 1 1 6842960C +P 10800 2450 +F 0 "U20" H 10800 2350 60 0000 C CNN +F 1 "d_inverter" H 10800 2600 60 0000 C CNN +F 2 "" H 10850 2400 60 0000 C CNN +F 3 "" H 10850 2400 60 0000 C CNN + 1 10800 2450 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U23 +U 1 1 68429612 +P 12450 3300 +F 0 "U23" H 12450 3200 60 0000 C CNN +F 1 "d_inverter" H 12450 3450 60 0000 C CNN +F 2 "" H 12500 3250 60 0000 C CNN +F 3 "" H 12500 3250 60 0000 C CNN + 1 12450 3300 + 0 1 1 0 +$EndComp +Wire Wire Line + 12100 2150 12450 2150 +Wire Wire Line + 12450 2150 12450 3000 +Wire Wire Line + 10800 2150 11000 2150 +Wire Wire Line + 12450 3600 12450 3750 +Wire Wire Line + 12150 4300 11850 4300 +Wire Wire Line + 12450 4900 12450 5800 +NoConn ~ 12100 1500 +NoConn ~ 11550 1200 +NoConn ~ 11550 2450 +Wire Wire Line + 11000 1500 10650 1500 +Wire Wire Line + 10650 1500 10650 850 +$Comp +L d_dff U25 +U 1 1 68429629 +P 13900 1850 +F 0 "U25" H 13900 1850 60 0000 C CNN +F 1 "d_dff" H 13900 2000 60 0000 C CNN +F 2 "" H 13900 1850 60 0000 C CNN +F 3 "" H 13900 1850 60 0000 C CNN + 1 13900 1850 + 1 0 0 -1 +$EndComp +$Comp +L d_tristate U26 +U 1 1 6842962F +P 14450 4350 +F 0 "U26" H 14200 4600 60 0000 C CNN +F 1 "d_tristate" H 14250 4800 60 0000 C CNN +F 2 "" H 14350 4700 60 0000 C CNN +F 3 "" H 14350 4700 60 0000 C CNN + 1 14450 4350 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U24 +U 1 1 68429635 +P 13150 2450 +F 0 "U24" H 13150 2350 60 0000 C CNN +F 1 "d_inverter" H 13150 2600 60 0000 C CNN +F 2 "" H 13200 2400 60 0000 C CNN +F 3 "" H 13200 2400 60 0000 C CNN + 1 13150 2450 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U27 +U 1 1 6842963B +P 14800 3300 +F 0 "U27" H 14800 3200 60 0000 C CNN +F 1 "d_inverter" H 14800 3450 60 0000 C CNN +F 2 "" H 14850 3250 60 0000 C CNN +F 3 "" H 14850 3250 60 0000 C CNN + 1 14800 3300 + 0 1 1 0 +$EndComp +Wire Wire Line + 14450 2150 14800 2150 +Wire Wire Line + 14800 2150 14800 3000 +Wire Wire Line + 13150 2150 13350 2150 +Wire Wire Line + 14800 3600 14800 3750 +Wire Wire Line + 14000 4300 14500 4300 +Wire Wire Line + 14800 4900 14800 5800 +NoConn ~ 14450 1500 +NoConn ~ 13900 1200 +NoConn ~ 13900 2450 +Wire Wire Line + 13350 1500 13000 1500 +Wire Wire Line + 13000 1500 13000 850 +$Comp +L d_dff U29 +U 1 1 68429652 +P 16000 1800 +F 0 "U29" H 16000 1800 60 0000 C CNN +F 1 "d_dff" H 16000 1950 60 0000 C CNN +F 2 "" H 16000 1800 60 0000 C CNN +F 3 "" H 16000 1800 60 0000 C CNN + 1 16000 1800 + 1 0 0 -1 +$EndComp +$Comp +L d_tristate U30 +U 1 1 68429658 +P 16550 4300 +F 0 "U30" H 16300 4550 60 0000 C CNN +F 1 "d_tristate" H 16350 4750 60 0000 C CNN +F 2 "" H 16450 4650 60 0000 C CNN +F 3 "" H 16450 4650 60 0000 C CNN + 1 16550 4300 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U28 +U 1 1 6842965E +P 15250 2400 +F 0 "U28" H 15250 2300 60 0000 C CNN +F 1 "d_inverter" H 15250 2550 60 0000 C CNN +F 2 "" H 15300 2350 60 0000 C CNN +F 3 "" H 15300 2350 60 0000 C CNN + 1 15250 2400 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U31 +U 1 1 68429664 +P 16900 3250 +F 0 "U31" H 16900 3150 60 0000 C CNN +F 1 "d_inverter" H 16900 3400 60 0000 C CNN +F 2 "" H 16950 3200 60 0000 C CNN +F 3 "" H 16950 3200 60 0000 C CNN + 1 16900 3250 + 0 1 1 0 +$EndComp +Wire Wire Line + 16550 2100 16900 2100 +Wire Wire Line + 16900 2100 16900 2950 +Wire Wire Line + 15250 2100 15450 2100 +Wire Wire Line + 16900 3550 16900 3700 +Wire Wire Line + 16250 4250 16600 4250 +Wire Wire Line + 16900 4850 16900 5750 +NoConn ~ 16550 1450 +NoConn ~ 16000 1150 +NoConn ~ 16000 2400 +Wire Wire Line + 15450 1450 15100 1450 +Wire Wire Line + 15100 1450 15100 800 +$Comp +L d_dff U33 +U 1 1 6842967B +P 18350 1800 +F 0 "U33" H 18350 1800 60 0000 C CNN +F 1 "d_dff" H 18350 1950 60 0000 C CNN +F 2 "" H 18350 1800 60 0000 C CNN +F 3 "" H 18350 1800 60 0000 C CNN + 1 18350 1800 + 1 0 0 -1 +$EndComp +$Comp +L d_tristate U34 +U 1 1 68429681 +P 18900 4300 +F 0 "U34" H 18650 4550 60 0000 C CNN +F 1 "d_tristate" H 18700 4750 60 0000 C CNN +F 2 "" H 18800 4650 60 0000 C CNN +F 3 "" H 18800 4650 60 0000 C CNN + 1 18900 4300 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U32 +U 1 1 68429687 +P 17600 2400 +F 0 "U32" H 17600 2300 60 0000 C CNN +F 1 "d_inverter" H 17600 2550 60 0000 C CNN +F 2 "" H 17650 2350 60 0000 C CNN +F 3 "" H 17650 2350 60 0000 C CNN + 1 17600 2400 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U35 +U 1 1 6842968D +P 19250 3250 +F 0 "U35" H 19250 3150 60 0000 C CNN +F 1 "d_inverter" H 19250 3400 60 0000 C CNN +F 2 "" H 19300 3200 60 0000 C CNN +F 3 "" H 19300 3200 60 0000 C CNN + 1 19250 3250 + 0 1 1 0 +$EndComp +Wire Wire Line + 18900 2100 19250 2100 +Wire Wire Line + 19250 2100 19250 2950 +Wire Wire Line + 17600 2100 17800 2100 +Wire Wire Line + 19250 3550 19250 3700 +Wire Wire Line + 18950 4250 18650 4250 +Wire Wire Line + 19250 4850 19250 5750 +NoConn ~ 18900 1450 +NoConn ~ 18350 1150 +NoConn ~ 18350 2400 +Wire Wire Line + 17800 1450 17450 1450 +Wire Wire Line + 17450 1450 17450 800 +$Comp +L d_inverter U2 +U 1 1 68429D28 +P 900 3050 +F 0 "U2" H 900 2950 60 0000 C CNN +F 1 "d_inverter" H 900 3200 60 0000 C CNN +F 2 "" H 950 3000 60 0000 C CNN +F 3 "" H 950 3000 60 0000 C CNN + 1 900 3050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1200 3050 17600 3050 +Wire Wire Line + 1500 3050 1500 2800 +Wire Wire Line + 17600 3050 17600 2700 +Connection ~ 1500 3050 +Wire Wire Line + 15250 2700 15250 3050 +Connection ~ 15250 3050 +Wire Wire Line + 13150 2750 13150 3050 +Connection ~ 13150 3050 +Wire Wire Line + 10800 2750 10800 3050 +Connection ~ 10800 3050 +Wire Wire Line + 8300 2750 8300 3050 +Connection ~ 8300 3050 +Wire Wire Line + 5950 2750 5950 3050 +Connection ~ 5950 3050 +Wire Wire Line + 3850 2800 3850 3050 +Connection ~ 3850 3050 +Wire Wire Line + 2350 5200 18650 5200 +Wire Wire Line + 18650 5200 18650 4250 +Wire Wire Line + 16250 4250 16250 5200 +Connection ~ 16250 5200 +Wire Wire Line + 14000 4300 14000 5200 +Connection ~ 14000 5200 +Wire Wire Line + 11850 4300 11850 5200 +Connection ~ 11850 5200 +Wire Wire Line + 9350 4300 9350 5200 +Connection ~ 9350 5200 +Wire Wire Line + 7000 4300 7000 5200 +Connection ~ 7000 5200 +Wire Wire Line + 4900 4350 4900 5200 +Connection ~ 4900 5200 +Wire Wire Line + 2550 4350 2550 5200 +Connection ~ 2550 5200 +$Comp +L PORT U1 +U 3 1 6842B98A +P 3700 650 +F 0 "U1" H 3750 750 30 0000 C CNN +F 1 "PORT" H 3700 650 30 0000 C CNN +F 2 "" H 3700 650 60 0000 C CNN +F 3 "" H 3700 650 60 0000 C CNN + 3 3700 650 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 5 1 6842BBB8 +P 8150 600 +F 0 "U1" H 8200 700 30 0000 C CNN +F 1 "PORT" H 8150 600 30 0000 C CNN +F 2 "" H 8150 600 60 0000 C CNN +F 3 "" H 8150 600 60 0000 C CNN + 5 8150 600 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 6842BD7B +P 13000 600 +F 0 "U1" H 13050 700 30 0000 C CNN +F 1 "PORT" H 13000 600 30 0000 C CNN +F 2 "" H 13000 600 60 0000 C CNN +F 3 "" H 13000 600 60 0000 C CNN + 7 13000 600 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 9 1 6842BF26 +P 17450 550 +F 0 "U1" H 17500 650 30 0000 C CNN +F 1 "PORT" H 17450 550 30 0000 C CNN +F 2 "" H 17450 550 60 0000 C CNN +F 3 "" H 17450 550 60 0000 C CNN + 9 17450 550 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 11 1 6842C09D +P 5500 6100 +F 0 "U1" H 5550 6200 30 0000 C CNN +F 1 "PORT" H 5500 6100 30 0000 C CNN +F 2 "" H 5500 6100 60 0000 C CNN +F 3 "" H 5500 6100 60 0000 C CNN + 11 5500 6100 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 13 1 6842C216 +P 9950 6050 +F 0 "U1" H 10000 6150 30 0000 C CNN +F 1 "PORT" H 9950 6050 30 0000 C CNN +F 2 "" H 9950 6050 60 0000 C CNN +F 3 "" H 9950 6050 60 0000 C CNN + 13 9950 6050 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 15 1 6842C39D +P 14800 6050 +F 0 "U1" H 14850 6150 30 0000 C CNN +F 1 "PORT" H 14800 6050 30 0000 C CNN +F 2 "" H 14800 6050 60 0000 C CNN +F 3 "" H 14800 6050 60 0000 C CNN + 15 14800 6050 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 17 1 6842C426 +P 19250 6000 +F 0 "U1" H 19300 6100 30 0000 C CNN +F 1 "PORT" H 19250 6000 30 0000 C CNN +F 2 "" H 19250 6000 60 0000 C CNN +F 3 "" H 19250 6000 60 0000 C CNN + 17 19250 6000 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 1 1 6842C759 +P 100 3050 +F 0 "U1" H 150 3150 30 0000 C CNN +F 1 "PORT" H 100 3050 30 0000 C CNN +F 2 "" H 100 3050 60 0000 C CNN +F 3 "" H 100 3050 60 0000 C CNN + 1 100 3050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 6842C9BF +P 1350 650 +F 0 "U1" H 1400 750 30 0000 C CNN +F 1 "PORT" H 1350 650 30 0000 C CNN +F 2 "" H 1350 650 60 0000 C CNN +F 3 "" H 1350 650 60 0000 C CNN + 2 1350 650 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 6842CA46 +P 5800 600 +F 0 "U1" H 5850 700 30 0000 C CNN +F 1 "PORT" H 5800 600 30 0000 C CNN +F 2 "" H 5800 600 60 0000 C CNN +F 3 "" H 5800 600 60 0000 C CNN + 4 5800 600 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 6 1 6842CB21 +P 10650 600 +F 0 "U1" H 10700 700 30 0000 C CNN +F 1 "PORT" H 10650 600 30 0000 C CNN +F 2 "" H 10650 600 60 0000 C CNN +F 3 "" H 10650 600 60 0000 C CNN + 6 10650 600 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 8 1 6842CD1E +P 15100 550 +F 0 "U1" H 15150 650 30 0000 C CNN +F 1 "PORT" H 15100 550 30 0000 C CNN +F 2 "" H 15100 550 60 0000 C CNN +F 3 "" H 15100 550 60 0000 C CNN + 8 15100 550 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 10 1 6842CEEC +P 3150 6100 +F 0 "U1" H 3200 6200 30 0000 C CNN +F 1 "PORT" H 3150 6100 30 0000 C CNN +F 2 "" H 3150 6100 60 0000 C CNN +F 3 "" H 3150 6100 60 0000 C CNN + 10 3150 6100 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 12 1 6842D121 +P 7600 6050 +F 0 "U1" H 7650 6150 30 0000 C CNN +F 1 "PORT" H 7600 6050 30 0000 C CNN +F 2 "" H 7600 6050 60 0000 C CNN +F 3 "" H 7600 6050 60 0000 C CNN + 12 7600 6050 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 14 1 6842D340 +P 12450 6050 +F 0 "U1" H 12500 6150 30 0000 C CNN +F 1 "PORT" H 12450 6050 30 0000 C CNN +F 2 "" H 12450 6050 60 0000 C CNN +F 3 "" H 12450 6050 60 0000 C CNN + 14 12450 6050 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 16 1 6842D56B +P 16900 6000 +F 0 "U1" H 16950 6100 30 0000 C CNN +F 1 "PORT" H 16900 6000 30 0000 C CNN +F 2 "" H 16900 6000 60 0000 C CNN +F 3 "" H 16900 6000 60 0000 C CNN + 16 16900 6000 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 18 1 6842D746 +P 1150 5200 +F 0 "U1" H 1200 5300 30 0000 C CNN +F 1 "PORT" H 1150 5200 30 0000 C CNN +F 2 "" H 1150 5200 60 0000 C CNN +F 3 "" H 1150 5200 60 0000 C CNN + 18 1150 5200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1400 5200 1750 5200 +Wire Wire Line + 350 3050 600 3050 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC374/CD54HC374.sub b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC374/CD54HC374.sub new file mode 100644 index 000000000..2243794d6 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC374/CD54HC374.sub @@ -0,0 +1,142 @@ +* Subcircuit CD54HC374 +.subckt CD54HC374 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\cd54hc374\cd54hc374.cir +* u5 net-_u1-pad2_ net-_u3-pad2_ ? ? ? net-_u5-pad6_ d_dff +* u6 net-_u6-pad1_ net-_u10-pad2_ net-_u1-pad10_ d_tristate +* u3 net-_u12-pad1_ net-_u3-pad2_ d_inverter +* u7 net-_u5-pad6_ net-_u6-pad1_ d_inverter +* u4 net-_u1-pad18_ net-_u10-pad2_ d_inverter +* u9 net-_u1-pad3_ net-_u8-pad2_ ? ? ? net-_u11-pad1_ d_dff +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad11_ d_tristate +* u8 net-_u12-pad1_ net-_u8-pad2_ d_inverter +* u11 net-_u11-pad1_ net-_u10-pad1_ d_inverter +* u13 net-_u1-pad4_ net-_u12-pad2_ ? ? ? net-_u13-pad6_ d_dff +* u14 net-_u14-pad1_ net-_u10-pad2_ net-_u1-pad12_ d_tristate +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u15 net-_u13-pad6_ net-_u14-pad1_ d_inverter +* u17 net-_u1-pad5_ net-_u16-pad2_ ? ? ? net-_u17-pad6_ d_dff +* u18 net-_u18-pad1_ net-_u10-pad2_ net-_u1-pad13_ d_tristate +* u16 net-_u12-pad1_ net-_u16-pad2_ d_inverter +* u19 net-_u17-pad6_ net-_u18-pad1_ d_inverter +* u21 net-_u1-pad6_ net-_u20-pad2_ ? ? ? net-_u21-pad6_ d_dff +* u22 net-_u22-pad1_ net-_u10-pad2_ net-_u1-pad14_ d_tristate +* u20 net-_u12-pad1_ net-_u20-pad2_ d_inverter +* u23 net-_u21-pad6_ net-_u22-pad1_ d_inverter +* u25 net-_u1-pad7_ net-_u24-pad2_ ? ? ? net-_u25-pad6_ d_dff +* u26 net-_u26-pad1_ net-_u10-pad2_ net-_u1-pad15_ d_tristate +* u24 net-_u12-pad1_ net-_u24-pad2_ d_inverter +* u27 net-_u25-pad6_ net-_u26-pad1_ d_inverter +* u29 net-_u1-pad8_ net-_u28-pad2_ ? ? ? net-_u29-pad6_ d_dff +* u30 net-_u30-pad1_ net-_u10-pad2_ net-_u1-pad16_ d_tristate +* u28 net-_u12-pad1_ net-_u28-pad2_ d_inverter +* u31 net-_u29-pad6_ net-_u30-pad1_ d_inverter +* u33 net-_u1-pad9_ net-_u32-pad2_ ? ? ? net-_u33-pad6_ d_dff +* u34 net-_u34-pad1_ net-_u10-pad2_ net-_u1-pad17_ d_tristate +* u32 net-_u12-pad1_ net-_u32-pad2_ d_inverter +* u35 net-_u33-pad6_ net-_u34-pad1_ d_inverter +* u2 net-_u1-pad1_ net-_u12-pad1_ d_inverter +a1 net-_u1-pad2_ net-_u3-pad2_ ? ? ? net-_u5-pad6_ u5 +a2 net-_u6-pad1_ net-_u10-pad2_ net-_u1-pad10_ u6 +a3 net-_u12-pad1_ net-_u3-pad2_ u3 +a4 net-_u5-pad6_ net-_u6-pad1_ u7 +a5 net-_u1-pad18_ net-_u10-pad2_ u4 +a6 net-_u1-pad3_ net-_u8-pad2_ ? ? ? net-_u11-pad1_ u9 +a7 net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad11_ u10 +a8 net-_u12-pad1_ net-_u8-pad2_ u8 +a9 net-_u11-pad1_ net-_u10-pad1_ u11 +a10 net-_u1-pad4_ net-_u12-pad2_ ? ? ? net-_u13-pad6_ u13 +a11 net-_u14-pad1_ net-_u10-pad2_ net-_u1-pad12_ u14 +a12 net-_u12-pad1_ net-_u12-pad2_ u12 +a13 net-_u13-pad6_ net-_u14-pad1_ u15 +a14 net-_u1-pad5_ net-_u16-pad2_ ? ? ? net-_u17-pad6_ u17 +a15 net-_u18-pad1_ net-_u10-pad2_ net-_u1-pad13_ u18 +a16 net-_u12-pad1_ net-_u16-pad2_ u16 +a17 net-_u17-pad6_ net-_u18-pad1_ u19 +a18 net-_u1-pad6_ net-_u20-pad2_ ? ? ? net-_u21-pad6_ u21 +a19 net-_u22-pad1_ net-_u10-pad2_ net-_u1-pad14_ u22 +a20 net-_u12-pad1_ net-_u20-pad2_ u20 +a21 net-_u21-pad6_ net-_u22-pad1_ u23 +a22 net-_u1-pad7_ net-_u24-pad2_ ? ? ? net-_u25-pad6_ u25 +a23 net-_u26-pad1_ net-_u10-pad2_ net-_u1-pad15_ u26 +a24 net-_u12-pad1_ net-_u24-pad2_ u24 +a25 net-_u25-pad6_ net-_u26-pad1_ u27 +a26 net-_u1-pad8_ net-_u28-pad2_ ? ? ? net-_u29-pad6_ u29 +a27 net-_u30-pad1_ net-_u10-pad2_ net-_u1-pad16_ u30 +a28 net-_u12-pad1_ net-_u28-pad2_ u28 +a29 net-_u29-pad6_ net-_u30-pad1_ u31 +a30 net-_u1-pad9_ net-_u32-pad2_ ? ? ? net-_u33-pad6_ u33 +a31 net-_u34-pad1_ net-_u10-pad2_ net-_u1-pad17_ u34 +a32 net-_u12-pad1_ net-_u32-pad2_ u32 +a33 net-_u33-pad6_ net-_u34-pad1_ u35 +a34 net-_u1-pad1_ net-_u12-pad1_ u2 +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u5 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u6 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u9 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u10 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u13 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u14 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u17 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u18 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u21 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u22 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u25 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u26 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u29 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u30 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u33 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_tristate, NgSpice Name: d_tristate +.model u34 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends CD54HC374 \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC374/CD54HC374_Previous_Values.xml b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC374/CD54HC374_Previous_Values.xml new file mode 100644 index 000000000..4680b7ff6 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC374/CD54HC374_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_dffd_tristated_inverterd_inverterd_inverterd_dffd_tristated_inverterd_inverterd_dffd_tristated_inverterd_inverterd_dffd_tristated_inverterd_inverterd_dffd_tristated_inverterd_inverterd_dffd_tristated_inverterd_inverterd_dffd_tristated_inverterd_inverterd_dffd_tristated_inverterd_inverterd_inverter \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC374/analysis b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC374/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC374/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC377/CD54HC377-cache.lib b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC377/CD54HC377-cache.lib new file mode 100644 index 000000000..deaa58ca4 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC377/CD54HC377-cache.lib @@ -0,0 +1,123 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_buffer +# +DEF d_buffer U 0 40 Y Y 1 F N +F0 "U" 0 -50 60 H V C CNN +F1 "d_buffer" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N +X IN 1 -500 0 200 R 50 50 1 1 I +X OUT 2 650 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# risingedge_dflipflop +# +DEF risingedge_dflipflop U 0 40 Y Y 1 F N +F0 "U" 2850 1800 60 H V C CNN +F1 "risingedge_dflipflop" 2850 2000 60 H V C CNN +F2 "" 2850 1950 60 H V C CNN +F3 "" 2850 1950 60 H V C CNN +DRAW +S 2350 2100 3350 1600 0 1 0 N +X D0 1 2150 1900 200 R 50 50 1 1 I +X clk0 2 2150 1800 200 R 50 50 1 1 I +X Q0 3 3550 1900 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC377/CD54HC377.cir b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC377/CD54HC377.cir new file mode 100644 index 000000000..2fc73a6a9 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC377/CD54HC377.cir @@ -0,0 +1,54 @@ +* C:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\CD54HC377\CD54HC377.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/29/25 11:28:30 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U2-Pad1_ Net-_U3-Pad2_ d_inverter +U8 Net-_U2-Pad2_ Net-_U10-Pad1_ Net-_U8-Pad3_ d_and +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter +U11 Net-_U1-Pad3_ Net-_U10-Pad2_ Net-_U11-Pad3_ d_and +U12 Net-_U12-Pad1_ Net-_U10-Pad1_ Net-_U12-Pad3_ d_and +U15 Net-_U10-Pad1_ Net-_U15-Pad2_ d_inverter +U16 Net-_U16-Pad1_ Net-_U15-Pad2_ Net-_U13-Pad1_ d_and +U17 Net-_U17-Pad1_ Net-_U10-Pad1_ Net-_U17-Pad3_ d_and +U19 Net-_U10-Pad1_ Net-_U19-Pad2_ d_inverter +U20 Net-_U2-Pad12_ Net-_U19-Pad2_ Net-_U18-Pad1_ d_and +U21 Net-_U2-Pad5_ Net-_U10-Pad1_ Net-_U21-Pad3_ d_and +U24 Net-_U10-Pad1_ Net-_U24-Pad2_ d_inverter +U25 Net-_U14-Pad3_ Net-_U24-Pad2_ Net-_U22-Pad1_ d_and +U26 Net-_U2-Pad6_ Net-_U10-Pad1_ Net-_U26-Pad3_ d_and +U28 Net-_U10-Pad1_ Net-_U28-Pad2_ d_inverter +U29 Net-_U2-Pad14_ Net-_U28-Pad2_ Net-_U27-Pad1_ d_and +U30 Net-_U2-Pad7_ Net-_U10-Pad1_ Net-_U30-Pad3_ d_and +U33 Net-_U10-Pad1_ Net-_U33-Pad2_ d_inverter +U34 Net-_U2-Pad15_ Net-_U33-Pad2_ Net-_U31-Pad1_ d_and +U35 Net-_U2-Pad8_ Net-_U10-Pad1_ Net-_U35-Pad3_ d_and +U37 Net-_U10-Pad1_ Net-_U37-Pad2_ d_inverter +U38 Net-_U2-Pad16_ Net-_U37-Pad2_ Net-_U36-Pad1_ d_and +U40 Net-_U2-Pad9_ Net-_U10-Pad1_ Net-_U40-Pad3_ d_and +U43 Net-_U10-Pad1_ Net-_U43-Pad2_ d_inverter +U44 Net-_U2-Pad17_ Net-_U43-Pad2_ Net-_U42-Pad1_ d_and +U9 Net-_U11-Pad3_ Net-_U8-Pad3_ Net-_U1-Pad1_ d_or +U13 Net-_U13-Pad1_ Net-_U12-Pad3_ Net-_U13-Pad3_ d_or +U18 Net-_U18-Pad1_ Net-_U17-Pad3_ Net-_U18-Pad3_ d_or +U22 Net-_U22-Pad1_ Net-_U21-Pad3_ Net-_U14-Pad1_ d_or +U27 Net-_U27-Pad1_ Net-_U26-Pad3_ Net-_U23-Pad1_ d_or +U31 Net-_U31-Pad1_ Net-_U30-Pad3_ Net-_U31-Pad3_ d_or +U36 Net-_U36-Pad1_ Net-_U35-Pad3_ Net-_U36-Pad3_ d_or +U42 Net-_U42-Pad1_ Net-_U40-Pad3_ Net-_U39-Pad1_ d_or +U6 Net-_U3-Pad2_ Net-_U10-Pad1_ d_buffer +U5 Net-_U2-Pad18_ Net-_U1-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ risingedge_dflipflop +U7 Net-_U18-Pad3_ Net-_U1-Pad2_ Net-_U2-Pad12_ risingedge_dflipflop +U14 Net-_U14-Pad1_ Net-_U1-Pad2_ Net-_U14-Pad3_ risingedge_dflipflop +U23 Net-_U23-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad14_ risingedge_dflipflop +U32 Net-_U31-Pad3_ Net-_U1-Pad2_ Net-_U2-Pad15_ risingedge_dflipflop +U4 Net-_U13-Pad3_ Net-_U1-Pad2_ Net-_U16-Pad1_ risingedge_dflipflop +U41 Net-_U36-Pad3_ Net-_U1-Pad2_ Net-_U2-Pad16_ risingedge_dflipflop +U39 Net-_U39-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad17_ risingedge_dflipflop +U2 Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U12-Pad1_ Net-_U17-Pad1_ Net-_U2-Pad5_ Net-_U2-Pad6_ Net-_U2-Pad7_ Net-_U2-Pad8_ Net-_U2-Pad9_ Net-_U1-Pad3_ Net-_U16-Pad1_ Net-_U2-Pad12_ Net-_U14-Pad3_ Net-_U2-Pad14_ Net-_U2-Pad15_ Net-_U2-Pad16_ Net-_U2-Pad17_ Net-_U2-Pad18_ PORT + +.end diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC377/CD54HC377.cir.out b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC377/CD54HC377.cir.out new file mode 100644 index 000000000..03fe7c48c --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC377/CD54HC377.cir.out @@ -0,0 +1,184 @@ +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\cd54hc377\cd54hc377.cir + +* u3 net-_u2-pad1_ net-_u3-pad2_ d_inverter +* u8 net-_u2-pad2_ net-_u10-pad1_ net-_u8-pad3_ d_and +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u11 net-_u1-pad3_ net-_u10-pad2_ net-_u11-pad3_ d_and +* u12 net-_u12-pad1_ net-_u10-pad1_ net-_u12-pad3_ d_and +* u15 net-_u10-pad1_ net-_u15-pad2_ d_inverter +* u16 net-_u16-pad1_ net-_u15-pad2_ net-_u13-pad1_ d_and +* u17 net-_u17-pad1_ net-_u10-pad1_ net-_u17-pad3_ d_and +* u19 net-_u10-pad1_ net-_u19-pad2_ d_inverter +* u20 net-_u2-pad12_ net-_u19-pad2_ net-_u18-pad1_ d_and +* u21 net-_u2-pad5_ net-_u10-pad1_ net-_u21-pad3_ d_and +* u24 net-_u10-pad1_ net-_u24-pad2_ d_inverter +* u25 net-_u14-pad3_ net-_u24-pad2_ net-_u22-pad1_ d_and +* u26 net-_u2-pad6_ net-_u10-pad1_ net-_u26-pad3_ d_and +* u28 net-_u10-pad1_ net-_u28-pad2_ d_inverter +* u29 net-_u2-pad14_ net-_u28-pad2_ net-_u27-pad1_ d_and +* u30 net-_u2-pad7_ net-_u10-pad1_ net-_u30-pad3_ d_and +* u33 net-_u10-pad1_ net-_u33-pad2_ d_inverter +* u34 net-_u2-pad15_ net-_u33-pad2_ net-_u31-pad1_ d_and +* u35 net-_u2-pad8_ net-_u10-pad1_ net-_u35-pad3_ d_and +* u37 net-_u10-pad1_ net-_u37-pad2_ d_inverter +* u38 net-_u2-pad16_ net-_u37-pad2_ net-_u36-pad1_ d_and +* u40 net-_u2-pad9_ net-_u10-pad1_ net-_u40-pad3_ d_and +* u43 net-_u10-pad1_ net-_u43-pad2_ d_inverter +* u44 net-_u2-pad17_ net-_u43-pad2_ net-_u42-pad1_ d_and +* u9 net-_u11-pad3_ net-_u8-pad3_ net-_u1-pad1_ d_or +* u13 net-_u13-pad1_ net-_u12-pad3_ net-_u13-pad3_ d_or +* u18 net-_u18-pad1_ net-_u17-pad3_ net-_u18-pad3_ d_or +* u22 net-_u22-pad1_ net-_u21-pad3_ net-_u14-pad1_ d_or +* u27 net-_u27-pad1_ net-_u26-pad3_ net-_u23-pad1_ d_or +* u31 net-_u31-pad1_ net-_u30-pad3_ net-_u31-pad3_ d_or +* u36 net-_u36-pad1_ net-_u35-pad3_ net-_u36-pad3_ d_or +* u42 net-_u42-pad1_ net-_u40-pad3_ net-_u39-pad1_ d_or +* u6 net-_u3-pad2_ net-_u10-pad1_ d_buffer +* u5 net-_u2-pad18_ net-_u1-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ risingedge_dflipflop +* u7 net-_u18-pad3_ net-_u1-pad2_ net-_u2-pad12_ risingedge_dflipflop +* u14 net-_u14-pad1_ net-_u1-pad2_ net-_u14-pad3_ risingedge_dflipflop +* u23 net-_u23-pad1_ net-_u1-pad2_ net-_u2-pad14_ risingedge_dflipflop +* u32 net-_u31-pad3_ net-_u1-pad2_ net-_u2-pad15_ risingedge_dflipflop +* u4 net-_u13-pad3_ net-_u1-pad2_ net-_u16-pad1_ risingedge_dflipflop +* u41 net-_u36-pad3_ net-_u1-pad2_ net-_u2-pad16_ risingedge_dflipflop +* u39 net-_u39-pad1_ net-_u1-pad2_ net-_u2-pad17_ risingedge_dflipflop +* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u12-pad1_ net-_u17-pad1_ net-_u2-pad5_ net-_u2-pad6_ net-_u2-pad7_ net-_u2-pad8_ net-_u2-pad9_ net-_u1-pad3_ net-_u16-pad1_ net-_u2-pad12_ net-_u14-pad3_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ net-_u2-pad17_ net-_u2-pad18_ port +a1 net-_u2-pad1_ net-_u3-pad2_ u3 +a2 [net-_u2-pad2_ net-_u10-pad1_ ] net-_u8-pad3_ u8 +a3 net-_u10-pad1_ net-_u10-pad2_ u10 +a4 [net-_u1-pad3_ net-_u10-pad2_ ] net-_u11-pad3_ u11 +a5 [net-_u12-pad1_ net-_u10-pad1_ ] net-_u12-pad3_ u12 +a6 net-_u10-pad1_ net-_u15-pad2_ u15 +a7 [net-_u16-pad1_ net-_u15-pad2_ ] net-_u13-pad1_ u16 +a8 [net-_u17-pad1_ net-_u10-pad1_ ] net-_u17-pad3_ u17 +a9 net-_u10-pad1_ net-_u19-pad2_ u19 +a10 [net-_u2-pad12_ net-_u19-pad2_ ] net-_u18-pad1_ u20 +a11 [net-_u2-pad5_ net-_u10-pad1_ ] net-_u21-pad3_ u21 +a12 net-_u10-pad1_ net-_u24-pad2_ u24 +a13 [net-_u14-pad3_ net-_u24-pad2_ ] net-_u22-pad1_ u25 +a14 [net-_u2-pad6_ net-_u10-pad1_ ] net-_u26-pad3_ u26 +a15 net-_u10-pad1_ net-_u28-pad2_ u28 +a16 [net-_u2-pad14_ net-_u28-pad2_ ] net-_u27-pad1_ u29 +a17 [net-_u2-pad7_ net-_u10-pad1_ ] net-_u30-pad3_ u30 +a18 net-_u10-pad1_ net-_u33-pad2_ u33 +a19 [net-_u2-pad15_ net-_u33-pad2_ ] net-_u31-pad1_ u34 +a20 [net-_u2-pad8_ net-_u10-pad1_ ] net-_u35-pad3_ u35 +a21 net-_u10-pad1_ net-_u37-pad2_ u37 +a22 [net-_u2-pad16_ net-_u37-pad2_ ] net-_u36-pad1_ u38 +a23 [net-_u2-pad9_ net-_u10-pad1_ ] net-_u40-pad3_ u40 +a24 net-_u10-pad1_ net-_u43-pad2_ u43 +a25 [net-_u2-pad17_ net-_u43-pad2_ ] net-_u42-pad1_ u44 +a26 [net-_u11-pad3_ net-_u8-pad3_ ] net-_u1-pad1_ u9 +a27 [net-_u13-pad1_ net-_u12-pad3_ ] net-_u13-pad3_ u13 +a28 [net-_u18-pad1_ net-_u17-pad3_ ] net-_u18-pad3_ u18 +a29 [net-_u22-pad1_ net-_u21-pad3_ ] net-_u14-pad1_ u22 +a30 [net-_u27-pad1_ net-_u26-pad3_ ] net-_u23-pad1_ u27 +a31 [net-_u31-pad1_ net-_u30-pad3_ ] net-_u31-pad3_ u31 +a32 [net-_u36-pad1_ net-_u35-pad3_ ] net-_u36-pad3_ u36 +a33 [net-_u42-pad1_ net-_u40-pad3_ ] net-_u39-pad1_ u42 +a34 net-_u3-pad2_ net-_u10-pad1_ u6 +a35 net-_u2-pad18_ net-_u1-pad2_ u5 +a36 [net-_u1-pad1_ ] [net-_u1-pad2_ ] [net-_u1-pad3_ ] u1 +a37 [net-_u18-pad3_ ] [net-_u1-pad2_ ] [net-_u2-pad12_ ] u7 +a38 [net-_u14-pad1_ ] [net-_u1-pad2_ ] [net-_u14-pad3_ ] u14 +a39 [net-_u23-pad1_ ] [net-_u1-pad2_ ] [net-_u2-pad14_ ] u23 +a40 [net-_u31-pad3_ ] [net-_u1-pad2_ ] [net-_u2-pad15_ ] u32 +a41 [net-_u13-pad3_ ] [net-_u1-pad2_ ] [net-_u16-pad1_ ] u4 +a42 [net-_u36-pad3_ ] [net-_u1-pad2_ ] [net-_u2-pad16_ ] u41 +a43 [net-_u39-pad1_ ] [net-_u1-pad2_ ] [net-_u2-pad17_ ] u39 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u34 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u35 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u38 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u40 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u43 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u44 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u9 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u13 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u18 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u22 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u27 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u31 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u36 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u42 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u6 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u1 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u7 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u14 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u23 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u32 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u4 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u41 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u39 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC377/CD54HC377.pro b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC377/CD54HC377.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC377/CD54HC377.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC377/CD54HC377.sch b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC377/CD54HC377.sch new file mode 100644 index 000000000..7cb3b5b14 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC377/CD54HC377.sch @@ -0,0 +1,1039 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:CD54HC377-cache +EELAYER 25 0 +EELAYER END +$Descr A3 16535 11693 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U3 +U 1 1 6836986D +P 2650 2050 +F 0 "U3" H 2650 1950 60 0000 C CNN +F 1 "d_inverter" H 2650 2200 60 0000 C CNN +F 2 "" H 2700 2000 60 0000 C CNN +F 3 "" H 2700 2000 60 0000 C CNN + 1 2650 2050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U8 +U 1 1 6836994E +P 4400 2700 +F 0 "U8" H 4400 2700 60 0000 C CNN +F 1 "d_and" H 4450 2800 60 0000 C CNN +F 2 "" H 4400 2700 60 0000 C CNN +F 3 "" H 4400 2700 60 0000 C CNN + 1 4400 2700 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U10 +U 1 1 68369A15 +P 4900 2550 +F 0 "U10" H 4900 2450 60 0000 C CNN +F 1 "d_inverter" H 4900 2700 60 0000 C CNN +F 2 "" H 4950 2500 60 0000 C CNN +F 3 "" H 4950 2500 60 0000 C CNN + 1 4900 2550 + 0 1 1 0 +$EndComp +$Comp +L d_and U11 +U 1 1 68369A4A +P 4900 3400 +F 0 "U11" H 4900 3400 60 0000 C CNN +F 1 "d_and" H 4950 3500 60 0000 C CNN +F 2 "" H 4900 3400 60 0000 C CNN +F 3 "" H 4900 3400 60 0000 C CNN + 1 4900 3400 + 0 1 1 0 +$EndComp +$Comp +L d_and U12 +U 1 1 68369AF0 +P 5250 2750 +F 0 "U12" H 5250 2750 60 0000 C CNN +F 1 "d_and" H 5300 2850 60 0000 C CNN +F 2 "" H 5250 2750 60 0000 C CNN +F 3 "" H 5250 2750 60 0000 C CNN + 1 5250 2750 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U15 +U 1 1 68369AF6 +P 5750 2600 +F 0 "U15" H 5750 2500 60 0000 C CNN +F 1 "d_inverter" H 5750 2750 60 0000 C CNN +F 2 "" H 5800 2550 60 0000 C CNN +F 3 "" H 5800 2550 60 0000 C CNN + 1 5750 2600 + 0 1 1 0 +$EndComp +$Comp +L d_and U16 +U 1 1 68369AFC +P 5750 3450 +F 0 "U16" H 5750 3450 60 0000 C CNN +F 1 "d_and" H 5800 3550 60 0000 C CNN +F 2 "" H 5750 3450 60 0000 C CNN +F 3 "" H 5750 3450 60 0000 C CNN + 1 5750 3450 + 0 1 1 0 +$EndComp +$Comp +L d_and U17 +U 1 1 68369B50 +P 6050 2750 +F 0 "U17" H 6050 2750 60 0000 C CNN +F 1 "d_and" H 6100 2850 60 0000 C CNN +F 2 "" H 6050 2750 60 0000 C CNN +F 3 "" H 6050 2750 60 0000 C CNN + 1 6050 2750 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U19 +U 1 1 68369B56 +P 6550 2600 +F 0 "U19" H 6550 2500 60 0000 C CNN +F 1 "d_inverter" H 6550 2750 60 0000 C CNN +F 2 "" H 6600 2550 60 0000 C CNN +F 3 "" H 6600 2550 60 0000 C CNN + 1 6550 2600 + 0 1 1 0 +$EndComp +$Comp +L d_and U20 +U 1 1 68369B5C +P 6550 3450 +F 0 "U20" H 6550 3450 60 0000 C CNN +F 1 "d_and" H 6600 3550 60 0000 C CNN +F 2 "" H 6550 3450 60 0000 C CNN +F 3 "" H 6550 3450 60 0000 C CNN + 1 6550 3450 + 0 1 1 0 +$EndComp +$Comp +L d_and U21 +U 1 1 68369BD5 +P 6850 2750 +F 0 "U21" H 6850 2750 60 0000 C CNN +F 1 "d_and" H 6900 2850 60 0000 C CNN +F 2 "" H 6850 2750 60 0000 C CNN +F 3 "" H 6850 2750 60 0000 C CNN + 1 6850 2750 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U24 +U 1 1 68369BDB +P 7350 2600 +F 0 "U24" H 7350 2500 60 0000 C CNN +F 1 "d_inverter" H 7350 2750 60 0000 C CNN +F 2 "" H 7400 2550 60 0000 C CNN +F 3 "" H 7400 2550 60 0000 C CNN + 1 7350 2600 + 0 1 1 0 +$EndComp +$Comp +L d_and U25 +U 1 1 68369BE1 +P 7350 3450 +F 0 "U25" H 7350 3450 60 0000 C CNN +F 1 "d_and" H 7400 3550 60 0000 C CNN +F 2 "" H 7350 3450 60 0000 C CNN +F 3 "" H 7350 3450 60 0000 C CNN + 1 7350 3450 + 0 1 1 0 +$EndComp +$Comp +L d_and U26 +U 1 1 68369DE2 +P 7650 2750 +F 0 "U26" H 7650 2750 60 0000 C CNN +F 1 "d_and" H 7700 2850 60 0000 C CNN +F 2 "" H 7650 2750 60 0000 C CNN +F 3 "" H 7650 2750 60 0000 C CNN + 1 7650 2750 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U28 +U 1 1 68369DE8 +P 8150 2600 +F 0 "U28" H 8150 2500 60 0000 C CNN +F 1 "d_inverter" H 8150 2750 60 0000 C CNN +F 2 "" H 8200 2550 60 0000 C CNN +F 3 "" H 8200 2550 60 0000 C CNN + 1 8150 2600 + 0 1 1 0 +$EndComp +$Comp +L d_and U29 +U 1 1 68369DEE +P 8150 3450 +F 0 "U29" H 8150 3450 60 0000 C CNN +F 1 "d_and" H 8200 3550 60 0000 C CNN +F 2 "" H 8150 3450 60 0000 C CNN +F 3 "" H 8150 3450 60 0000 C CNN + 1 8150 3450 + 0 1 1 0 +$EndComp +$Comp +L d_and U30 +U 1 1 68369DF4 +P 8500 2800 +F 0 "U30" H 8500 2800 60 0000 C CNN +F 1 "d_and" H 8550 2900 60 0000 C CNN +F 2 "" H 8500 2800 60 0000 C CNN +F 3 "" H 8500 2800 60 0000 C CNN + 1 8500 2800 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U33 +U 1 1 68369DFA +P 9000 2650 +F 0 "U33" H 9000 2550 60 0000 C CNN +F 1 "d_inverter" H 9000 2800 60 0000 C CNN +F 2 "" H 9050 2600 60 0000 C CNN +F 3 "" H 9050 2600 60 0000 C CNN + 1 9000 2650 + 0 1 1 0 +$EndComp +$Comp +L d_and U34 +U 1 1 68369E00 +P 9000 3500 +F 0 "U34" H 9000 3500 60 0000 C CNN +F 1 "d_and" H 9050 3600 60 0000 C CNN +F 2 "" H 9000 3500 60 0000 C CNN +F 3 "" H 9000 3500 60 0000 C CNN + 1 9000 3500 + 0 1 1 0 +$EndComp +$Comp +L d_and U35 +U 1 1 68369E06 +P 9300 2800 +F 0 "U35" H 9300 2800 60 0000 C CNN +F 1 "d_and" H 9350 2900 60 0000 C CNN +F 2 "" H 9300 2800 60 0000 C CNN +F 3 "" H 9300 2800 60 0000 C CNN + 1 9300 2800 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U37 +U 1 1 68369E0C +P 9800 2650 +F 0 "U37" H 9800 2550 60 0000 C CNN +F 1 "d_inverter" H 9800 2800 60 0000 C CNN +F 2 "" H 9850 2600 60 0000 C CNN +F 3 "" H 9850 2600 60 0000 C CNN + 1 9800 2650 + 0 1 1 0 +$EndComp +$Comp +L d_and U38 +U 1 1 68369E12 +P 9800 3500 +F 0 "U38" H 9800 3500 60 0000 C CNN +F 1 "d_and" H 9850 3600 60 0000 C CNN +F 2 "" H 9800 3500 60 0000 C CNN +F 3 "" H 9800 3500 60 0000 C CNN + 1 9800 3500 + 0 1 1 0 +$EndComp +$Comp +L d_and U40 +U 1 1 68369E18 +P 10100 2800 +F 0 "U40" H 10100 2800 60 0000 C CNN +F 1 "d_and" H 10150 2900 60 0000 C CNN +F 2 "" H 10100 2800 60 0000 C CNN +F 3 "" H 10100 2800 60 0000 C CNN + 1 10100 2800 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U43 +U 1 1 68369E1E +P 10600 2650 +F 0 "U43" H 10600 2550 60 0000 C CNN +F 1 "d_inverter" H 10600 2800 60 0000 C CNN +F 2 "" H 10650 2600 60 0000 C CNN +F 3 "" H 10650 2600 60 0000 C CNN + 1 10600 2650 + 0 1 1 0 +$EndComp +$Comp +L d_and U44 +U 1 1 68369E24 +P 10600 3500 +F 0 "U44" H 10600 3500 60 0000 C CNN +F 1 "d_and" H 10650 3600 60 0000 C CNN +F 2 "" H 10600 3500 60 0000 C CNN +F 3 "" H 10600 3500 60 0000 C CNN + 1 10600 3500 + 0 1 1 0 +$EndComp +$Comp +L d_or U9 +U 1 1 68369EF4 +P 4650 4300 +F 0 "U9" H 4650 4300 60 0000 C CNN +F 1 "d_or" H 4650 4400 60 0000 C CNN +F 2 "" H 4650 4300 60 0000 C CNN +F 3 "" H 4650 4300 60 0000 C CNN + 1 4650 4300 + 0 1 1 0 +$EndComp +$Comp +L d_or U13 +U 1 1 6836A25D +P 5500 4350 +F 0 "U13" H 5500 4350 60 0000 C CNN +F 1 "d_or" H 5500 4450 60 0000 C CNN +F 2 "" H 5500 4350 60 0000 C CNN +F 3 "" H 5500 4350 60 0000 C CNN + 1 5500 4350 + 0 1 1 0 +$EndComp +$Comp +L d_or U18 +U 1 1 6836A30E +P 6250 4400 +F 0 "U18" H 6250 4400 60 0000 C CNN +F 1 "d_or" H 6250 4500 60 0000 C CNN +F 2 "" H 6250 4400 60 0000 C CNN +F 3 "" H 6250 4400 60 0000 C CNN + 1 6250 4400 + 0 1 1 0 +$EndComp +$Comp +L d_or U22 +U 1 1 6836A392 +P 7050 4400 +F 0 "U22" H 7050 4400 60 0000 C CNN +F 1 "d_or" H 7050 4500 60 0000 C CNN +F 2 "" H 7050 4400 60 0000 C CNN +F 3 "" H 7050 4400 60 0000 C CNN + 1 7050 4400 + 0 1 1 0 +$EndComp +$Comp +L d_or U27 +U 1 1 6836A5B5 +P 7800 4400 +F 0 "U27" H 7800 4400 60 0000 C CNN +F 1 "d_or" H 7800 4500 60 0000 C CNN +F 2 "" H 7800 4400 60 0000 C CNN +F 3 "" H 7800 4400 60 0000 C CNN + 1 7800 4400 + 0 1 1 0 +$EndComp +$Comp +L d_or U31 +U 1 1 6836A5BB +P 8650 4450 +F 0 "U31" H 8650 4450 60 0000 C CNN +F 1 "d_or" H 8650 4550 60 0000 C CNN +F 2 "" H 8650 4450 60 0000 C CNN +F 3 "" H 8650 4450 60 0000 C CNN + 1 8650 4450 + 0 1 1 0 +$EndComp +$Comp +L d_or U36 +U 1 1 6836A5C1 +P 9400 4500 +F 0 "U36" H 9400 4500 60 0000 C CNN +F 1 "d_or" H 9400 4600 60 0000 C CNN +F 2 "" H 9400 4500 60 0000 C CNN +F 3 "" H 9400 4500 60 0000 C CNN + 1 9400 4500 + 0 1 1 0 +$EndComp +$Comp +L d_or U42 +U 1 1 6836A5C7 +P 10200 4500 +F 0 "U42" H 10200 4500 60 0000 C CNN +F 1 "d_or" H 10200 4600 60 0000 C CNN +F 2 "" H 10200 4500 60 0000 C CNN +F 3 "" H 10200 4500 60 0000 C CNN + 1 10200 4500 + 0 1 1 0 +$EndComp +$Comp +L d_buffer U6 +U 1 1 6836B4DF +P 3500 2050 +F 0 "U6" H 3500 2000 60 0000 C CNN +F 1 "d_buffer" H 3500 2100 60 0000 C CNN +F 2 "" H 3500 2050 60 0000 C CNN +F 3 "" H 3500 2050 60 0000 C CNN + 1 3500 2050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 6836B7A4 +P 3000 6450 +F 0 "U5" H 3000 6350 60 0000 C CNN +F 1 "d_inverter" H 3000 6600 60 0000 C CNN +F 2 "" H 3050 6400 60 0000 C CNN +F 3 "" H 3050 6400 60 0000 C CNN + 1 3000 6450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4150 2050 10600 2050 +Wire Wire Line + 10600 2050 10600 2350 +Wire Wire Line + 4400 2250 4400 2050 +Connection ~ 4400 2050 +Wire Wire Line + 4900 2250 4900 2050 +Connection ~ 4900 2050 +Wire Wire Line + 5750 2300 5750 2050 +Connection ~ 5750 2050 +Wire Wire Line + 6550 2300 6550 2050 +Connection ~ 6550 2050 +Wire Wire Line + 7350 2300 7350 2050 +Connection ~ 7350 2050 +Wire Wire Line + 8150 2300 8150 2050 +Connection ~ 8150 2050 +Wire Wire Line + 9000 2350 9000 2050 +Connection ~ 9000 2050 +Wire Wire Line + 9800 2350 9800 2050 +Connection ~ 9800 2050 +Wire Wire Line + 4450 3150 4450 3850 +Wire Wire Line + 4450 3850 4650 3850 +Wire Wire Line + 4750 3850 4950 3850 +Wire Wire Line + 4900 2850 4900 2950 +Wire Wire Line + 5300 3200 5300 3900 +Wire Wire Line + 5300 3900 5500 3900 +Wire Wire Line + 5600 3900 5800 3900 +Wire Wire Line + 5750 2900 5750 3000 +Wire Wire Line + 6100 3200 6100 3950 +Wire Wire Line + 6100 3950 6250 3950 +$Comp +L risingedge_dflipflop U1 +U 1 1 6836CC04 +P 1150 7250 +F 0 "U1" H 4000 9050 60 0000 C CNN +F 1 "risingedge_dflipflop" H 4000 9250 60 0000 C CNN +F 2 "" H 4000 9200 60 0000 C CNN +F 3 "" H 4000 9200 60 0000 C CNN + 1 1150 7250 + 1 0 0 -1 +$EndComp +$Comp +L risingedge_dflipflop U7 +U 1 1 6836D02E +P 4150 7250 +F 0 "U7" H 7000 9050 60 0000 C CNN +F 1 "risingedge_dflipflop" H 7000 9250 60 0000 C CNN +F 2 "" H 7000 9200 60 0000 C CNN +F 3 "" H 7000 9200 60 0000 C CNN + 1 4150 7250 + 1 0 0 -1 +$EndComp +$Comp +L risingedge_dflipflop U14 +U 1 1 6836D16C +P 5650 7250 +F 0 "U14" H 8500 9050 60 0000 C CNN +F 1 "risingedge_dflipflop" H 8500 9250 60 0000 C CNN +F 2 "" H 8500 9200 60 0000 C CNN +F 3 "" H 8500 9200 60 0000 C CNN + 1 5650 7250 + 1 0 0 -1 +$EndComp +$Comp +L risingedge_dflipflop U23 +U 1 1 6836D2DE +P 7150 7250 +F 0 "U23" H 10000 9050 60 0000 C CNN +F 1 "risingedge_dflipflop" H 10000 9250 60 0000 C CNN +F 2 "" H 10000 9200 60 0000 C CNN +F 3 "" H 10000 9200 60 0000 C CNN + 1 7150 7250 + 1 0 0 -1 +$EndComp +$Comp +L risingedge_dflipflop U32 +U 1 1 6836D4C8 +P 8650 7250 +F 0 "U32" H 11500 9050 60 0000 C CNN +F 1 "risingedge_dflipflop" H 11500 9250 60 0000 C CNN +F 2 "" H 11500 9200 60 0000 C CNN +F 3 "" H 11500 9200 60 0000 C CNN + 1 8650 7250 + 1 0 0 -1 +$EndComp +$Comp +L risingedge_dflipflop U4 +U 1 1 6836D686 +P 2650 7250 +F 0 "U4" H 5500 9050 60 0000 C CNN +F 1 "risingedge_dflipflop" H 5500 9250 60 0000 C CNN +F 2 "" H 5500 9200 60 0000 C CNN +F 3 "" H 5500 9200 60 0000 C CNN + 1 2650 7250 + 1 0 0 -1 +$EndComp +$Comp +L risingedge_dflipflop U41 +U 1 1 6836DC67 +P 10150 7250 +F 0 "U41" H 13000 9050 60 0000 C CNN +F 1 "risingedge_dflipflop" H 13000 9250 60 0000 C CNN +F 2 "" H 13000 9200 60 0000 C CNN +F 3 "" H 13000 9200 60 0000 C CNN + 1 10150 7250 + 1 0 0 -1 +$EndComp +$Comp +L risingedge_dflipflop U39 +U 1 1 6836DF5B +P 10000 6500 +F 0 "U39" H 12850 8300 60 0000 C CNN +F 1 "risingedge_dflipflop" H 12850 8500 60 0000 C CNN +F 2 "" H 12850 8450 60 0000 C CNN +F 3 "" H 12850 8450 60 0000 C CNN + 1 10000 6500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4700 4750 3200 4750 +Wire Wire Line + 3200 4750 3200 5350 +Wire Wire Line + 3200 5350 3300 5350 +Wire Wire Line + 5550 4800 4800 4800 +Wire Wire Line + 4800 4800 4800 5350 +Wire Wire Line + 6300 4850 6300 5350 +Wire Wire Line + 7100 4850 7800 4850 +Wire Wire Line + 7800 4850 7800 5350 +Wire Wire Line + 7850 4850 7850 5100 +Wire Wire Line + 7850 5100 9300 5100 +Wire Wire Line + 9300 5100 9300 5350 +Wire Wire Line + 8700 4900 8700 5050 +Wire Wire Line + 8700 5050 10800 5050 +Wire Wire Line + 10800 5050 10800 5350 +Wire Wire Line + 9450 4950 9450 5000 +Wire Wire Line + 9450 5000 12300 5000 +Wire Wire Line + 12300 5000 12300 5350 +Wire Wire Line + 10250 4950 12000 4950 +Wire Wire Line + 12000 4950 12000 4600 +Wire Wire Line + 12000 4600 12150 4600 +Wire Wire Line + 3300 6450 13850 6450 +Wire Wire Line + 10800 6450 10800 5450 +Wire Wire Line + 9300 5450 9300 6450 +Connection ~ 9300 6450 +Wire Wire Line + 7800 5450 7800 6450 +Connection ~ 7800 6450 +Wire Wire Line + 6300 5450 6300 6450 +Connection ~ 6300 6450 +Wire Wire Line + 4800 5450 4800 6450 +Connection ~ 4800 6450 +Wire Wire Line + 3300 5450 3300 6450 +Wire Wire Line + 5000 2950 5200 2950 +Wire Wire Line + 5200 2950 5200 5050 +Wire Wire Line + 5200 5050 4700 5050 +Wire Wire Line + 4700 5050 4700 6850 +Connection ~ 4700 5350 +Wire Wire Line + 5250 2300 5250 2050 +Connection ~ 5250 2050 +Wire Wire Line + 6050 2300 6050 2050 +Connection ~ 6050 2050 +Wire Wire Line + 6850 2300 6850 2050 +Connection ~ 6850 2050 +Wire Wire Line + 7650 2300 7650 2050 +Connection ~ 7650 2050 +Wire Wire Line + 9300 2350 9300 2050 +Connection ~ 9300 2050 +Wire Wire Line + 10100 2350 10100 2050 +Connection ~ 10100 2050 +Wire Wire Line + 8500 2350 8500 2050 +Wire Wire Line + 8500 2050 8550 2050 +Connection ~ 8550 2050 +Wire Wire Line + 6550 2900 6550 3000 +Wire Wire Line + 7350 2900 7350 3000 +Wire Wire Line + 8150 2900 8150 3000 +Wire Wire Line + 9000 2950 9000 3050 +Wire Wire Line + 9800 2950 9800 3050 +Wire Wire Line + 10600 2950 10600 3050 +Wire Wire Line + 5850 3000 6000 3000 +Wire Wire Line + 6000 3000 6000 5100 +Wire Wire Line + 6000 5100 6200 5100 +Wire Wire Line + 6200 5100 6200 6850 +Connection ~ 6200 5350 +Wire Wire Line + 6600 3900 6350 3900 +Wire Wire Line + 6350 3900 6350 3950 +Wire Wire Line + 6900 3200 6900 3950 +Wire Wire Line + 6900 3950 7050 3950 +Wire Wire Line + 7150 3950 7400 3950 +Wire Wire Line + 7400 3950 7400 3900 +Wire Wire Line + 7700 3200 7700 3950 +Wire Wire Line + 7700 3950 7800 3950 +Wire Wire Line + 7900 3950 8200 3950 +Wire Wire Line + 8200 3950 8200 3900 +Wire Wire Line + 8550 3250 8550 4000 +Wire Wire Line + 8550 4000 8650 4000 +Wire Wire Line + 8750 4000 9050 4000 +Wire Wire Line + 9050 4000 9050 3950 +Wire Wire Line + 9350 3250 9350 4050 +Wire Wire Line + 9350 4050 9400 4050 +Wire Wire Line + 9500 4050 9850 4050 +Wire Wire Line + 9850 4050 9850 3950 +Wire Wire Line + 10150 3250 10150 4050 +Wire Wire Line + 10150 4050 10200 4050 +Wire Wire Line + 10300 4050 10650 4050 +Wire Wire Line + 10650 4050 10650 3950 +Wire Wire Line + 6650 3000 6750 3000 +Wire Wire Line + 6750 3000 6750 5100 +Wire Wire Line + 6750 5100 7700 5100 +Wire Wire Line + 7700 5100 7700 6850 +Wire Wire Line + 7450 3000 7550 3000 +Wire Wire Line + 7550 3000 7550 5000 +Wire Wire Line + 7550 5000 9200 5000 +Wire Wire Line + 9200 5000 9200 6850 +Wire Wire Line + 8250 3000 8250 2900 +Wire Wire Line + 8250 2900 8350 2900 +Wire Wire Line + 8350 2900 8350 4850 +Wire Wire Line + 8350 4850 10700 4850 +Wire Wire Line + 10700 4850 10700 6850 +Wire Wire Line + 9100 3050 9100 3000 +Wire Wire Line + 9100 3000 9250 3000 +Wire Wire Line + 9250 3000 9250 4950 +Wire Wire Line + 9250 4950 10150 4950 +Wire Wire Line + 10150 4950 10150 4900 +Wire Wire Line + 10150 4900 12200 4900 +Wire Wire Line + 12200 4900 12200 6800 +Wire Wire Line + 9900 3050 9900 3000 +Wire Wire Line + 9900 3000 10000 3000 +Wire Wire Line + 10000 3000 10000 4800 +Wire Wire Line + 10000 4800 12250 4800 +Wire Wire Line + 12250 4800 12250 4950 +Wire Wire Line + 12250 4950 13700 4950 +Wire Wire Line + 13700 4950 13700 5800 +Wire Wire Line + 10700 3050 13850 3050 +Connection ~ 9200 5350 +Connection ~ 10700 5350 +Connection ~ 12200 5350 +Wire Wire Line + 13700 5800 13350 5800 +Wire Wire Line + 13350 5800 13350 6800 +Connection ~ 13700 5350 +Wire Wire Line + 13550 4600 14400 4600 +Wire Wire Line + 14400 4600 14400 6800 +$Comp +L PORT U2 +U 1 1 68373509 +P 2000 2050 +F 0 "U2" H 2050 2150 30 0000 C CNN +F 1 "PORT" H 2000 2050 30 0000 C CNN +F 2 "" H 2000 2050 60 0000 C CNN +F 3 "" H 2000 2050 60 0000 C CNN + 1 2000 2050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U2 +U 2 1 68373892 +P 4500 1600 +F 0 "U2" H 4550 1700 30 0000 C CNN +F 1 "PORT" H 4500 1600 30 0000 C CNN +F 2 "" H 4500 1600 60 0000 C CNN +F 3 "" H 4500 1600 60 0000 C CNN + 2 4500 1600 + 0 1 1 0 +$EndComp +$Comp +L PORT U2 +U 3 1 68373B14 +P 5350 1600 +F 0 "U2" H 5400 1700 30 0000 C CNN +F 1 "PORT" H 5350 1600 30 0000 C CNN +F 2 "" H 5350 1600 60 0000 C CNN +F 3 "" H 5350 1600 60 0000 C CNN + 3 5350 1600 + 0 1 1 0 +$EndComp +$Comp +L PORT U2 +U 5 1 68373D3F +P 6950 1600 +F 0 "U2" H 7000 1700 30 0000 C CNN +F 1 "PORT" H 6950 1600 30 0000 C CNN +F 2 "" H 6950 1600 60 0000 C CNN +F 3 "" H 6950 1600 60 0000 C CNN + 5 6950 1600 + 0 1 1 0 +$EndComp +$Comp +L PORT U2 +U 6 1 68374028 +P 7750 1600 +F 0 "U2" H 7800 1700 30 0000 C CNN +F 1 "PORT" H 7750 1600 30 0000 C CNN +F 2 "" H 7750 1600 60 0000 C CNN +F 3 "" H 7750 1600 60 0000 C CNN + 6 7750 1600 + 0 1 1 0 +$EndComp +$Comp +L PORT U2 +U 8 1 68374159 +P 9400 1600 +F 0 "U2" H 9450 1700 30 0000 C CNN +F 1 "PORT" H 9400 1600 30 0000 C CNN +F 2 "" H 9400 1600 60 0000 C CNN +F 3 "" H 9400 1600 60 0000 C CNN + 8 9400 1600 + 0 1 1 0 +$EndComp +$Comp +L PORT U2 +U 9 1 68374345 +P 10150 1650 +F 0 "U2" H 10200 1750 30 0000 C CNN +F 1 "PORT" H 10150 1650 30 0000 C CNN +F 2 "" H 10150 1650 60 0000 C CNN +F 3 "" H 10150 1650 60 0000 C CNN + 9 10150 1650 + 0 1 1 0 +$EndComp +$Comp +L PORT U2 +U 11 1 683744E6 +P 6200 7100 +F 0 "U2" H 6250 7200 30 0000 C CNN +F 1 "PORT" H 6200 7100 30 0000 C CNN +F 2 "" H 6200 7100 60 0000 C CNN +F 3 "" H 6200 7100 60 0000 C CNN + 11 6200 7100 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U2 +U 13 1 683746E7 +P 9200 7100 +F 0 "U2" H 9250 7200 30 0000 C CNN +F 1 "PORT" H 9200 7100 30 0000 C CNN +F 2 "" H 9200 7100 60 0000 C CNN +F 3 "" H 9200 7100 60 0000 C CNN + 13 9200 7100 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U2 +U 14 1 683748F4 +P 10700 7100 +F 0 "U2" H 10750 7200 30 0000 C CNN +F 1 "PORT" H 10700 7100 30 0000 C CNN +F 2 "" H 10700 7100 60 0000 C CNN +F 3 "" H 10700 7100 60 0000 C CNN + 14 10700 7100 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U2 +U 4 1 68374E68 +P 6150 1600 +F 0 "U2" H 6200 1700 30 0000 C CNN +F 1 "PORT" H 6150 1600 30 0000 C CNN +F 2 "" H 6150 1600 60 0000 C CNN +F 3 "" H 6150 1600 60 0000 C CNN + 4 6150 1600 + 0 1 1 0 +$EndComp +$Comp +L PORT U2 +U 7 1 6837525F +P 8600 1650 +F 0 "U2" H 8650 1750 30 0000 C CNN +F 1 "PORT" H 8600 1650 30 0000 C CNN +F 2 "" H 8600 1650 60 0000 C CNN +F 3 "" H 8600 1650 60 0000 C CNN + 7 8600 1650 + 0 1 1 0 +$EndComp +$Comp +L PORT U2 +U 10 1 683754F7 +P 4700 7100 +F 0 "U2" H 4750 7200 30 0000 C CNN +F 1 "PORT" H 4700 7100 30 0000 C CNN +F 2 "" H 4700 7100 60 0000 C CNN +F 3 "" H 4700 7100 60 0000 C CNN + 10 4700 7100 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U2 +U 12 1 68375756 +P 7700 7100 +F 0 "U2" H 7750 7200 30 0000 C CNN +F 1 "PORT" H 7700 7100 30 0000 C CNN +F 2 "" H 7700 7100 60 0000 C CNN +F 3 "" H 7700 7100 60 0000 C CNN + 12 7700 7100 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U2 +U 15 1 68375A74 +P 12200 7050 +F 0 "U2" H 12250 7150 30 0000 C CNN +F 1 "PORT" H 12200 7050 30 0000 C CNN +F 2 "" H 12200 7050 60 0000 C CNN +F 3 "" H 12200 7050 60 0000 C CNN + 15 12200 7050 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U2 +U 16 1 68375D31 +P 13350 7050 +F 0 "U2" H 13400 7150 30 0000 C CNN +F 1 "PORT" H 13350 7050 30 0000 C CNN +F 2 "" H 13350 7050 60 0000 C CNN +F 3 "" H 13350 7050 60 0000 C CNN + 16 13350 7050 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U2 +U 17 1 68375E56 +P 14400 7050 +F 0 "U2" H 14450 7150 30 0000 C CNN +F 1 "PORT" H 14400 7050 30 0000 C CNN +F 2 "" H 14400 7050 60 0000 C CNN +F 3 "" H 14400 7050 60 0000 C CNN + 17 14400 7050 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U2 +U 18 1 683760B1 +P 2250 6450 +F 0 "U2" H 2300 6550 30 0000 C CNN +F 1 "PORT" H 2250 6450 30 0000 C CNN +F 2 "" H 2250 6450 60 0000 C CNN +F 3 "" H 2250 6450 60 0000 C CNN + 18 2250 6450 + 1 0 0 -1 +$EndComp +Connection ~ 7700 5350 +Wire Wire Line + 4500 1850 4500 2250 +Wire Wire Line + 5350 1850 5350 2300 +Wire Wire Line + 6150 1850 6150 2300 +Wire Wire Line + 6950 1850 6950 2300 +Wire Wire Line + 7750 1850 7750 2300 +Wire Wire Line + 8600 1900 8600 2350 +Wire Wire Line + 9400 1850 9400 2350 +Wire Wire Line + 10150 1900 10150 2350 +Wire Wire Line + 10150 2350 10200 2350 +Wire Wire Line + 2250 2050 2350 2050 +Wire Wire Line + 2950 2050 3000 2050 +Wire Wire Line + 2500 6450 2700 6450 +Wire Wire Line + 12300 6450 12300 5450 +Connection ~ 10800 6450 +Wire Wire Line + 13850 6450 13850 5050 +Wire Wire Line + 13850 5050 12100 5050 +Wire Wire Line + 12100 5050 12100 4700 +Wire Wire Line + 12100 4700 12150 4700 +Connection ~ 12300 6450 +Wire Wire Line + 13850 3050 13850 4600 +Connection ~ 13850 4600 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC377/CD54HC377.sub b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC377/CD54HC377.sub new file mode 100644 index 000000000..d7715a793 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC377/CD54HC377.sub @@ -0,0 +1,178 @@ +* Subcircuit CD54HC377 +.subckt CD54HC377 net-_u2-pad1_ net-_u2-pad2_ net-_u12-pad1_ net-_u17-pad1_ net-_u2-pad5_ net-_u2-pad6_ net-_u2-pad7_ net-_u2-pad8_ net-_u2-pad9_ net-_u1-pad3_ net-_u16-pad1_ net-_u2-pad12_ net-_u14-pad3_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ net-_u2-pad17_ net-_u2-pad18_ +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\cd54hc377\cd54hc377.cir +* u3 net-_u2-pad1_ net-_u3-pad2_ d_inverter +* u8 net-_u2-pad2_ net-_u10-pad1_ net-_u8-pad3_ d_and +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u11 net-_u1-pad3_ net-_u10-pad2_ net-_u11-pad3_ d_and +* u12 net-_u12-pad1_ net-_u10-pad1_ net-_u12-pad3_ d_and +* u15 net-_u10-pad1_ net-_u15-pad2_ d_inverter +* u16 net-_u16-pad1_ net-_u15-pad2_ net-_u13-pad1_ d_and +* u17 net-_u17-pad1_ net-_u10-pad1_ net-_u17-pad3_ d_and +* u19 net-_u10-pad1_ net-_u19-pad2_ d_inverter +* u20 net-_u2-pad12_ net-_u19-pad2_ net-_u18-pad1_ d_and +* u21 net-_u2-pad5_ net-_u10-pad1_ net-_u21-pad3_ d_and +* u24 net-_u10-pad1_ net-_u24-pad2_ d_inverter +* u25 net-_u14-pad3_ net-_u24-pad2_ net-_u22-pad1_ d_and +* u26 net-_u2-pad6_ net-_u10-pad1_ net-_u26-pad3_ d_and +* u28 net-_u10-pad1_ net-_u28-pad2_ d_inverter +* u29 net-_u2-pad14_ net-_u28-pad2_ net-_u27-pad1_ d_and +* u30 net-_u2-pad7_ net-_u10-pad1_ net-_u30-pad3_ d_and +* u33 net-_u10-pad1_ net-_u33-pad2_ d_inverter +* u34 net-_u2-pad15_ net-_u33-pad2_ net-_u31-pad1_ d_and +* u35 net-_u2-pad8_ net-_u10-pad1_ net-_u35-pad3_ d_and +* u37 net-_u10-pad1_ net-_u37-pad2_ d_inverter +* u38 net-_u2-pad16_ net-_u37-pad2_ net-_u36-pad1_ d_and +* u40 net-_u2-pad9_ net-_u10-pad1_ net-_u40-pad3_ d_and +* u43 net-_u10-pad1_ net-_u43-pad2_ d_inverter +* u44 net-_u2-pad17_ net-_u43-pad2_ net-_u42-pad1_ d_and +* u9 net-_u11-pad3_ net-_u8-pad3_ net-_u1-pad1_ d_or +* u13 net-_u13-pad1_ net-_u12-pad3_ net-_u13-pad3_ d_or +* u18 net-_u18-pad1_ net-_u17-pad3_ net-_u18-pad3_ d_or +* u22 net-_u22-pad1_ net-_u21-pad3_ net-_u14-pad1_ d_or +* u27 net-_u27-pad1_ net-_u26-pad3_ net-_u23-pad1_ d_or +* u31 net-_u31-pad1_ net-_u30-pad3_ net-_u31-pad3_ d_or +* u36 net-_u36-pad1_ net-_u35-pad3_ net-_u36-pad3_ d_or +* u42 net-_u42-pad1_ net-_u40-pad3_ net-_u39-pad1_ d_or +* u6 net-_u3-pad2_ net-_u10-pad1_ d_buffer +* u5 net-_u2-pad18_ net-_u1-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ risingedge_dflipflop +* u7 net-_u18-pad3_ net-_u1-pad2_ net-_u2-pad12_ risingedge_dflipflop +* u14 net-_u14-pad1_ net-_u1-pad2_ net-_u14-pad3_ risingedge_dflipflop +* u23 net-_u23-pad1_ net-_u1-pad2_ net-_u2-pad14_ risingedge_dflipflop +* u32 net-_u31-pad3_ net-_u1-pad2_ net-_u2-pad15_ risingedge_dflipflop +* u4 net-_u13-pad3_ net-_u1-pad2_ net-_u16-pad1_ risingedge_dflipflop +* u41 net-_u36-pad3_ net-_u1-pad2_ net-_u2-pad16_ risingedge_dflipflop +* u39 net-_u39-pad1_ net-_u1-pad2_ net-_u2-pad17_ risingedge_dflipflop +a1 net-_u2-pad1_ net-_u3-pad2_ u3 +a2 [net-_u2-pad2_ net-_u10-pad1_ ] net-_u8-pad3_ u8 +a3 net-_u10-pad1_ net-_u10-pad2_ u10 +a4 [net-_u1-pad3_ net-_u10-pad2_ ] net-_u11-pad3_ u11 +a5 [net-_u12-pad1_ net-_u10-pad1_ ] net-_u12-pad3_ u12 +a6 net-_u10-pad1_ net-_u15-pad2_ u15 +a7 [net-_u16-pad1_ net-_u15-pad2_ ] net-_u13-pad1_ u16 +a8 [net-_u17-pad1_ net-_u10-pad1_ ] net-_u17-pad3_ u17 +a9 net-_u10-pad1_ net-_u19-pad2_ u19 +a10 [net-_u2-pad12_ net-_u19-pad2_ ] net-_u18-pad1_ u20 +a11 [net-_u2-pad5_ net-_u10-pad1_ ] net-_u21-pad3_ u21 +a12 net-_u10-pad1_ net-_u24-pad2_ u24 +a13 [net-_u14-pad3_ net-_u24-pad2_ ] net-_u22-pad1_ u25 +a14 [net-_u2-pad6_ net-_u10-pad1_ ] net-_u26-pad3_ u26 +a15 net-_u10-pad1_ net-_u28-pad2_ u28 +a16 [net-_u2-pad14_ net-_u28-pad2_ ] net-_u27-pad1_ u29 +a17 [net-_u2-pad7_ net-_u10-pad1_ ] net-_u30-pad3_ u30 +a18 net-_u10-pad1_ net-_u33-pad2_ u33 +a19 [net-_u2-pad15_ net-_u33-pad2_ ] net-_u31-pad1_ u34 +a20 [net-_u2-pad8_ net-_u10-pad1_ ] net-_u35-pad3_ u35 +a21 net-_u10-pad1_ net-_u37-pad2_ u37 +a22 [net-_u2-pad16_ net-_u37-pad2_ ] net-_u36-pad1_ u38 +a23 [net-_u2-pad9_ net-_u10-pad1_ ] net-_u40-pad3_ u40 +a24 net-_u10-pad1_ net-_u43-pad2_ u43 +a25 [net-_u2-pad17_ net-_u43-pad2_ ] net-_u42-pad1_ u44 +a26 [net-_u11-pad3_ net-_u8-pad3_ ] net-_u1-pad1_ u9 +a27 [net-_u13-pad1_ net-_u12-pad3_ ] net-_u13-pad3_ u13 +a28 [net-_u18-pad1_ net-_u17-pad3_ ] net-_u18-pad3_ u18 +a29 [net-_u22-pad1_ net-_u21-pad3_ ] net-_u14-pad1_ u22 +a30 [net-_u27-pad1_ net-_u26-pad3_ ] net-_u23-pad1_ u27 +a31 [net-_u31-pad1_ net-_u30-pad3_ ] net-_u31-pad3_ u31 +a32 [net-_u36-pad1_ net-_u35-pad3_ ] net-_u36-pad3_ u36 +a33 [net-_u42-pad1_ net-_u40-pad3_ ] net-_u39-pad1_ u42 +a34 net-_u3-pad2_ net-_u10-pad1_ u6 +a35 net-_u2-pad18_ net-_u1-pad2_ u5 +a36 [net-_u1-pad1_ ] [net-_u1-pad2_ ] [net-_u1-pad3_ ] u1 +a37 [net-_u18-pad3_ ] [net-_u1-pad2_ ] [net-_u2-pad12_ ] u7 +a38 [net-_u14-pad1_ ] [net-_u1-pad2_ ] [net-_u14-pad3_ ] u14 +a39 [net-_u23-pad1_ ] [net-_u1-pad2_ ] [net-_u2-pad14_ ] u23 +a40 [net-_u31-pad3_ ] [net-_u1-pad2_ ] [net-_u2-pad15_ ] u32 +a41 [net-_u13-pad3_ ] [net-_u1-pad2_ ] [net-_u16-pad1_ ] u4 +a42 [net-_u36-pad3_ ] [net-_u1-pad2_ ] [net-_u2-pad16_ ] u41 +a43 [net-_u39-pad1_ ] [net-_u1-pad2_ ] [net-_u2-pad17_ ] u39 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u34 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u35 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u38 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u40 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u43 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u44 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u9 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u13 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u18 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u22 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u27 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u31 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u36 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u42 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u6 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u1 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u7 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u14 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u23 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u32 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u4 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u41 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u39 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Control Statements + +.ends CD54HC377 \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC377/CD54HC377_Previous_Values.xml b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC377/CD54HC377_Previous_Values.xml new file mode 100644 index 000000000..124952cf3 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC377/CD54HC377_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_inverterd_andd_inverterd_andd_andd_inverterd_andd_andd_inverterd_andd_andd_inverterd_andd_andd_inverterd_andd_andd_inverterd_andd_andd_inverterd_andd_andd_inverterd_andd_ord_ord_ord_ord_ord_ord_ord_ord_bufferd_inverterrisingedge_dflipfloprisingedge_dflipfloprisingedge_dflipfloprisingedge_dflipfloprisingedge_dflipfloprisingedge_dflipfloprisingedge_dflipfloprisingedge_dflipflop \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC377/analysis b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC377/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD54HC377/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD74FCT827T/CD74FCT827T-cache.lib b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD74FCT827T/CD74FCT827T-cache.lib new file mode 100644 index 000000000..a896e07fd --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD74FCT827T/CD74FCT827T-cache.lib @@ -0,0 +1,90 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# one_input_tristate_buffer +# +DEF one_input_tristate_buffer U 0 40 Y Y 1 F N +F0 "U" 2850 1800 60 H V C CNN +F1 "one_input_tristate_buffer" 2850 2000 60 H V C CNN +F2 "" 2850 1950 60 H V C CNN +F3 "" 2850 1950 60 H V C CNN +DRAW +S 2350 2100 3350 1600 0 1 0 N +X A0 1 2150 1900 200 R 50 50 1 1 I +X EN0 2 2150 1800 200 R 50 50 1 1 I +X Y0 3 3550 1900 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD74FCT827T/CD74FCT827T.cir b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD74FCT827T/CD74FCT827T.cir new file mode 100644 index 000000000..e9ba28b7b --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD74FCT827T/CD74FCT827T.cir @@ -0,0 +1,24 @@ +* C:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\CD74FCT827T\CD74FCT827T.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/26/25 23:36:08 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ one_input_tristate_buffer +U2 Net-_U14-Pad3_ Net-_U1-Pad2_ Net-_U14-Pad22_ one_input_tristate_buffer +U3 Net-_U14-Pad4_ Net-_U1-Pad2_ Net-_U14-Pad21_ one_input_tristate_buffer +U4 Net-_U14-Pad5_ Net-_U1-Pad2_ Net-_U14-Pad20_ one_input_tristate_buffer +U5 Net-_U14-Pad6_ Net-_U1-Pad2_ Net-_U14-Pad19_ one_input_tristate_buffer +U6 Net-_U14-Pad7_ Net-_U1-Pad2_ Net-_U14-Pad18_ one_input_tristate_buffer +U7 Net-_U14-Pad8_ Net-_U1-Pad2_ Net-_U14-Pad17_ one_input_tristate_buffer +U8 Net-_U14-Pad9_ Net-_U1-Pad2_ Net-_U14-Pad16_ one_input_tristate_buffer +U9 Net-_U14-Pad10_ Net-_U1-Pad2_ Net-_U14-Pad15_ one_input_tristate_buffer +U10 Net-_U10-Pad1_ Net-_U1-Pad2_ Net-_U10-Pad3_ one_input_tristate_buffer +U13 Net-_U11-Pad2_ Net-_U12-Pad2_ Net-_U1-Pad2_ d_and +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ d_inverter +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_inverter +U14 Net-_U11-Pad1_ Net-_U1-Pad1_ Net-_U14-Pad3_ Net-_U14-Pad4_ Net-_U14-Pad5_ Net-_U14-Pad6_ Net-_U14-Pad7_ Net-_U14-Pad8_ Net-_U14-Pad9_ Net-_U14-Pad10_ Net-_U10-Pad1_ ? Net-_U12-Pad1_ Net-_U10-Pad3_ Net-_U14-Pad15_ Net-_U14-Pad16_ Net-_U14-Pad17_ Net-_U14-Pad18_ Net-_U14-Pad19_ Net-_U14-Pad20_ Net-_U14-Pad21_ Net-_U14-Pad22_ Net-_U1-Pad3_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD74FCT827T/CD74FCT827T.cir.out b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD74FCT827T/CD74FCT827T.cir.out new file mode 100644 index 000000000..df3bc0573 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD74FCT827T/CD74FCT827T.cir.out @@ -0,0 +1,64 @@ +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\cd74fct827t\cd74fct827t.cir + +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ one_input_tristate_buffer +* u2 net-_u14-pad3_ net-_u1-pad2_ net-_u14-pad22_ one_input_tristate_buffer +* u3 net-_u14-pad4_ net-_u1-pad2_ net-_u14-pad21_ one_input_tristate_buffer +* u4 net-_u14-pad5_ net-_u1-pad2_ net-_u14-pad20_ one_input_tristate_buffer +* u5 net-_u14-pad6_ net-_u1-pad2_ net-_u14-pad19_ one_input_tristate_buffer +* u6 net-_u14-pad7_ net-_u1-pad2_ net-_u14-pad18_ one_input_tristate_buffer +* u7 net-_u14-pad8_ net-_u1-pad2_ net-_u14-pad17_ one_input_tristate_buffer +* u8 net-_u14-pad9_ net-_u1-pad2_ net-_u14-pad16_ one_input_tristate_buffer +* u9 net-_u14-pad10_ net-_u1-pad2_ net-_u14-pad15_ one_input_tristate_buffer +* u10 net-_u10-pad1_ net-_u1-pad2_ net-_u10-pad3_ one_input_tristate_buffer +* u13 net-_u11-pad2_ net-_u12-pad2_ net-_u1-pad2_ d_and +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u14 net-_u11-pad1_ net-_u1-pad1_ net-_u14-pad3_ net-_u14-pad4_ net-_u14-pad5_ net-_u14-pad6_ net-_u14-pad7_ net-_u14-pad8_ net-_u14-pad9_ net-_u14-pad10_ net-_u10-pad1_ ? net-_u12-pad1_ net-_u10-pad3_ net-_u14-pad15_ net-_u14-pad16_ net-_u14-pad17_ net-_u14-pad18_ net-_u14-pad19_ net-_u14-pad20_ net-_u14-pad21_ net-_u14-pad22_ net-_u1-pad3_ ? port +a1 [net-_u1-pad1_ ] [net-_u1-pad2_ ] [net-_u1-pad3_ ] u1 +a2 [net-_u14-pad3_ ] [net-_u1-pad2_ ] [net-_u14-pad22_ ] u2 +a3 [net-_u14-pad4_ ] [net-_u1-pad2_ ] [net-_u14-pad21_ ] u3 +a4 [net-_u14-pad5_ ] [net-_u1-pad2_ ] [net-_u14-pad20_ ] u4 +a5 [net-_u14-pad6_ ] [net-_u1-pad2_ ] [net-_u14-pad19_ ] u5 +a6 [net-_u14-pad7_ ] [net-_u1-pad2_ ] [net-_u14-pad18_ ] u6 +a7 [net-_u14-pad8_ ] [net-_u1-pad2_ ] [net-_u14-pad17_ ] u7 +a8 [net-_u14-pad9_ ] [net-_u1-pad2_ ] [net-_u14-pad16_ ] u8 +a9 [net-_u14-pad10_ ] [net-_u1-pad2_ ] [net-_u14-pad15_ ] u9 +a10 [net-_u10-pad1_ ] [net-_u1-pad2_ ] [net-_u10-pad3_ ] u10 +a11 [net-_u11-pad2_ net-_u12-pad2_ ] net-_u1-pad2_ u13 +a12 net-_u11-pad1_ net-_u11-pad2_ u11 +a13 net-_u12-pad1_ net-_u12-pad2_ u12 +* Schematic Name: one_input_tristate_buffer, NgSpice Name: one_input_tristate_buffer +.model u1 one_input_tristate_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: one_input_tristate_buffer, NgSpice Name: one_input_tristate_buffer +.model u2 one_input_tristate_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: one_input_tristate_buffer, NgSpice Name: one_input_tristate_buffer +.model u3 one_input_tristate_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: one_input_tristate_buffer, NgSpice Name: one_input_tristate_buffer +.model u4 one_input_tristate_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: one_input_tristate_buffer, NgSpice Name: one_input_tristate_buffer +.model u5 one_input_tristate_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: one_input_tristate_buffer, NgSpice Name: one_input_tristate_buffer +.model u6 one_input_tristate_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: one_input_tristate_buffer, NgSpice Name: one_input_tristate_buffer +.model u7 one_input_tristate_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: one_input_tristate_buffer, NgSpice Name: one_input_tristate_buffer +.model u8 one_input_tristate_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: one_input_tristate_buffer, NgSpice Name: one_input_tristate_buffer +.model u9 one_input_tristate_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: one_input_tristate_buffer, NgSpice Name: one_input_tristate_buffer +.model u10 one_input_tristate_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD74FCT827T/CD74FCT827T.pro b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD74FCT827T/CD74FCT827T.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD74FCT827T/CD74FCT827T.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD74FCT827T/CD74FCT827T.sch b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD74FCT827T/CD74FCT827T.sch new file mode 100644 index 000000000..0185ddf24 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD74FCT827T/CD74FCT827T.sch @@ -0,0 +1,552 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A3 16535 11693 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L one_input_tristate_buffer U1 +U 1 1 685D8B3F +P 5350 4000 +F 0 "U1" H 8200 5800 60 0000 C CNN +F 1 "one_input_tristate_buffer" H 8200 6000 60 0000 C CNN +F 2 "" H 8200 5950 60 0000 C CNN +F 3 "" H 8200 5950 60 0000 C CNN + 1 5350 4000 + 1 0 0 -1 +$EndComp +$Comp +L one_input_tristate_buffer U2 +U 1 1 685D8BF4 +P 5350 4650 +F 0 "U2" H 8200 6450 60 0000 C CNN +F 1 "one_input_tristate_buffer" H 8200 6650 60 0000 C CNN +F 2 "" H 8200 6600 60 0000 C CNN +F 3 "" H 8200 6600 60 0000 C CNN + 1 5350 4650 + 1 0 0 -1 +$EndComp +$Comp +L one_input_tristate_buffer U3 +U 1 1 685D8C5A +P 5350 5300 +F 0 "U3" H 8200 7100 60 0000 C CNN +F 1 "one_input_tristate_buffer" H 8200 7300 60 0000 C CNN +F 2 "" H 8200 7250 60 0000 C CNN +F 3 "" H 8200 7250 60 0000 C CNN + 1 5350 5300 + 1 0 0 -1 +$EndComp +$Comp +L one_input_tristate_buffer U4 +U 1 1 685D8C60 +P 5350 5950 +F 0 "U4" H 8200 7750 60 0000 C CNN +F 1 "one_input_tristate_buffer" H 8200 7950 60 0000 C CNN +F 2 "" H 8200 7900 60 0000 C CNN +F 3 "" H 8200 7900 60 0000 C CNN + 1 5350 5950 + 1 0 0 -1 +$EndComp +$Comp +L one_input_tristate_buffer U5 +U 1 1 685D8D5E +P 5350 6600 +F 0 "U5" H 8200 8400 60 0000 C CNN +F 1 "one_input_tristate_buffer" H 8200 8600 60 0000 C CNN +F 2 "" H 8200 8550 60 0000 C CNN +F 3 "" H 8200 8550 60 0000 C CNN + 1 5350 6600 + 1 0 0 -1 +$EndComp +$Comp +L one_input_tristate_buffer U6 +U 1 1 685D8D64 +P 5350 7250 +F 0 "U6" H 8200 9050 60 0000 C CNN +F 1 "one_input_tristate_buffer" H 8200 9250 60 0000 C CNN +F 2 "" H 8200 9200 60 0000 C CNN +F 3 "" H 8200 9200 60 0000 C CNN + 1 5350 7250 + 1 0 0 -1 +$EndComp +$Comp +L one_input_tristate_buffer U7 +U 1 1 685D8D6A +P 5350 7900 +F 0 "U7" H 8200 9700 60 0000 C CNN +F 1 "one_input_tristate_buffer" H 8200 9900 60 0000 C CNN +F 2 "" H 8200 9850 60 0000 C CNN +F 3 "" H 8200 9850 60 0000 C CNN + 1 5350 7900 + 1 0 0 -1 +$EndComp +$Comp +L one_input_tristate_buffer U8 +U 1 1 685D8D70 +P 5350 8550 +F 0 "U8" H 8200 10350 60 0000 C CNN +F 1 "one_input_tristate_buffer" H 8200 10550 60 0000 C CNN +F 2 "" H 8200 10500 60 0000 C CNN +F 3 "" H 8200 10500 60 0000 C CNN + 1 5350 8550 + 1 0 0 -1 +$EndComp +$Comp +L one_input_tristate_buffer U9 +U 1 1 685D8E30 +P 5400 9250 +F 0 "U9" H 8250 11050 60 0000 C CNN +F 1 "one_input_tristate_buffer" H 8250 11250 60 0000 C CNN +F 2 "" H 8250 11200 60 0000 C CNN +F 3 "" H 8250 11200 60 0000 C CNN + 1 5400 9250 + 1 0 0 -1 +$EndComp +$Comp +L one_input_tristate_buffer U10 +U 1 1 685D8E36 +P 5400 9900 +F 0 "U10" H 8250 11700 60 0000 C CNN +F 1 "one_input_tristate_buffer" H 8250 11900 60 0000 C CNN +F 2 "" H 8250 11850 60 0000 C CNN +F 3 "" H 8250 11850 60 0000 C CNN + 1 5400 9900 + 1 0 0 -1 +$EndComp +$Comp +L d_and U13 +U 1 1 685D8E52 +P 6850 8700 +F 0 "U13" H 6850 8700 60 0000 C CNN +F 1 "d_and" H 6900 8800 60 0000 C CNN +F 2 "" H 6850 8700 60 0000 C CNN +F 3 "" H 6850 8700 60 0000 C CNN + 1 6850 8700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U11 +U 1 1 685D8F33 +P 5900 8550 +F 0 "U11" H 5900 8450 60 0000 C CNN +F 1 "d_inverter" H 5900 8700 60 0000 C CNN +F 2 "" H 5950 8500 60 0000 C CNN +F 3 "" H 5950 8500 60 0000 C CNN + 1 5900 8550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U12 +U 1 1 685D8F86 +P 5900 8800 +F 0 "U12" H 5900 8700 60 0000 C CNN +F 1 "d_inverter" H 5900 8950 60 0000 C CNN +F 2 "" H 5950 8750 60 0000 C CNN +F 3 "" H 5950 8750 60 0000 C CNN + 1 5900 8800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6200 8550 6400 8550 +Wire Wire Line + 6400 8550 6400 8600 +Wire Wire Line + 6400 8700 6400 8800 +Wire Wire Line + 6400 8800 6200 8800 +Wire Wire Line + 5600 8550 5500 8550 +Wire Wire Line + 5600 8800 5500 8800 +Wire Wire Line + 7350 8650 7300 8650 +Wire Wire Line + 7350 2200 7350 8650 +Wire Wire Line + 7350 2850 7500 2850 +Wire Wire Line + 7500 3500 7350 3500 +Connection ~ 7350 3500 +Wire Wire Line + 7500 4150 7350 4150 +Connection ~ 7350 4150 +Wire Wire Line + 7500 4800 7350 4800 +Connection ~ 7350 4800 +Wire Wire Line + 7500 5450 7350 5450 +Connection ~ 7350 5450 +Wire Wire Line + 7500 6100 7350 6100 +Connection ~ 7350 6100 +Wire Wire Line + 7500 6750 7350 6750 +Connection ~ 7350 6750 +Wire Wire Line + 7550 7450 7350 7450 +Connection ~ 7350 7450 +Wire Wire Line + 7550 8100 7350 8100 +Connection ~ 7350 8100 +Wire Wire Line + 7350 2200 7500 2200 +Connection ~ 7350 2850 +Wire Wire Line + 7550 8000 7250 8000 +Wire Wire Line + 7550 7350 7200 7350 +Wire Wire Line + 7500 6650 7200 6650 +Wire Wire Line + 7500 6000 7150 6000 +Wire Wire Line + 7500 5350 7150 5350 +Wire Wire Line + 7500 4700 7150 4700 +Wire Wire Line + 7500 4050 7150 4050 +Wire Wire Line + 7500 3400 7000 3400 +Wire Wire Line + 7500 2750 7000 2750 +Wire Wire Line + 7500 2100 6950 2100 +Wire Wire Line + 8900 2100 9050 2100 +Wire Wire Line + 8900 2750 9100 2750 +Wire Wire Line + 8900 3400 9050 3400 +Wire Wire Line + 8900 4050 9000 4050 +Wire Wire Line + 8900 4700 9050 4700 +Wire Wire Line + 8900 5350 9050 5350 +Wire Wire Line + 8900 6000 9050 6000 +Wire Wire Line + 8900 6650 9050 6650 +Wire Wire Line + 8950 7350 9100 7350 +Wire Wire Line + 8950 8000 9150 8000 +$Comp +L PORT U14 +U 10 1 685DA750 +P 6950 7350 +F 0 "U14" H 7000 7450 30 0000 C CNN +F 1 "PORT" H 6950 7350 30 0000 C CNN +F 2 "" H 6950 7350 60 0000 C CNN +F 3 "" H 6950 7350 60 0000 C CNN + 10 6950 7350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U14 +U 11 1 685DA813 +P 7000 8000 +F 0 "U14" H 7050 8100 30 0000 C CNN +F 1 "PORT" H 7000 8000 30 0000 C CNN +F 2 "" H 7000 8000 60 0000 C CNN +F 3 "" H 7000 8000 60 0000 C CNN + 11 7000 8000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U14 +U 13 1 685DA862 +P 5250 8800 +F 0 "U14" H 5300 8900 30 0000 C CNN +F 1 "PORT" H 5250 8800 30 0000 C CNN +F 2 "" H 5250 8800 60 0000 C CNN +F 3 "" H 5250 8800 60 0000 C CNN + 13 5250 8800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U14 +U 8 1 685DA89F +P 6900 6000 +F 0 "U14" H 6950 6100 30 0000 C CNN +F 1 "PORT" H 6900 6000 30 0000 C CNN +F 2 "" H 6900 6000 60 0000 C CNN +F 3 "" H 6900 6000 60 0000 C CNN + 8 6900 6000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U14 +U 5 1 685DA96A +P 6900 4050 +F 0 "U14" H 6950 4150 30 0000 C CNN +F 1 "PORT" H 6900 4050 30 0000 C CNN +F 2 "" H 6900 4050 60 0000 C CNN +F 3 "" H 6900 4050 60 0000 C CNN + 5 6900 4050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U14 +U 9 1 685DAA51 +P 6950 6650 +F 0 "U14" H 7000 6750 30 0000 C CNN +F 1 "PORT" H 6950 6650 30 0000 C CNN +F 2 "" H 6950 6650 60 0000 C CNN +F 3 "" H 6950 6650 60 0000 C CNN + 9 6950 6650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U14 +U 12 1 685DAB2C +P 5950 8650 +F 0 "U14" H 6000 8750 30 0000 C CNN +F 1 "PORT" H 5950 8650 30 0000 C CNN +F 2 "" H 5950 8650 60 0000 C CNN +F 3 "" H 5950 8650 60 0000 C CNN + 12 5950 8650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U14 +U 1 1 685DAC35 +P 5250 8550 +F 0 "U14" H 5300 8650 30 0000 C CNN +F 1 "PORT" H 5250 8550 30 0000 C CNN +F 2 "" H 5250 8550 60 0000 C CNN +F 3 "" H 5250 8550 60 0000 C CNN + 1 5250 8550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U14 +U 2 1 685DAD0B +P 6700 2100 +F 0 "U14" H 6750 2200 30 0000 C CNN +F 1 "PORT" H 6700 2100 30 0000 C CNN +F 2 "" H 6700 2100 60 0000 C CNN +F 3 "" H 6700 2100 60 0000 C CNN + 2 6700 2100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U14 +U 3 1 685DAE06 +P 6750 2750 +F 0 "U14" H 6800 2850 30 0000 C CNN +F 1 "PORT" H 6750 2750 30 0000 C CNN +F 2 "" H 6750 2750 60 0000 C CNN +F 3 "" H 6750 2750 60 0000 C CNN + 3 6750 2750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U14 +U 4 1 685DAF37 +P 6750 3400 +F 0 "U14" H 6800 3500 30 0000 C CNN +F 1 "PORT" H 6750 3400 30 0000 C CNN +F 2 "" H 6750 3400 60 0000 C CNN +F 3 "" H 6750 3400 60 0000 C CNN + 4 6750 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U14 +U 6 1 685DAFF4 +P 6900 4700 +F 0 "U14" H 6950 4800 30 0000 C CNN +F 1 "PORT" H 6900 4700 30 0000 C CNN +F 2 "" H 6900 4700 60 0000 C CNN +F 3 "" H 6900 4700 60 0000 C CNN + 6 6900 4700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U14 +U 7 1 685DB124 +P 6900 5350 +F 0 "U14" H 6950 5450 30 0000 C CNN +F 1 "PORT" H 6900 5350 30 0000 C CNN +F 2 "" H 6900 5350 60 0000 C CNN +F 3 "" H 6900 5350 60 0000 C CNN + 7 6900 5350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U14 +U 16 1 685DB347 +P 9300 6650 +F 0 "U14" H 9350 6750 30 0000 C CNN +F 1 "PORT" H 9300 6650 30 0000 C CNN +F 2 "" H 9300 6650 60 0000 C CNN +F 3 "" H 9300 6650 60 0000 C CNN + 16 9300 6650 + -1 0 0 -1 +$EndComp +$Comp +L PORT U14 +U 17 1 685DB392 +P 9300 6000 +F 0 "U14" H 9350 6100 30 0000 C CNN +F 1 "PORT" H 9300 6000 30 0000 C CNN +F 2 "" H 9300 6000 60 0000 C CNN +F 3 "" H 9300 6000 60 0000 C CNN + 17 9300 6000 + -1 0 0 -1 +$EndComp +$Comp +L PORT U14 +U 18 1 685DB4DB +P 9300 5350 +F 0 "U14" H 9350 5450 30 0000 C CNN +F 1 "PORT" H 9300 5350 30 0000 C CNN +F 2 "" H 9300 5350 60 0000 C CNN +F 3 "" H 9300 5350 60 0000 C CNN + 18 9300 5350 + -1 0 0 -1 +$EndComp +$Comp +L PORT U14 +U 19 1 685DB601 +P 9300 4700 +F 0 "U14" H 9350 4800 30 0000 C CNN +F 1 "PORT" H 9300 4700 30 0000 C CNN +F 2 "" H 9300 4700 60 0000 C CNN +F 3 "" H 9300 4700 60 0000 C CNN + 19 9300 4700 + -1 0 0 -1 +$EndComp +$Comp +L PORT U14 +U 14 1 685DB6AC +P 9400 8000 +F 0 "U14" H 9450 8100 30 0000 C CNN +F 1 "PORT" H 9400 8000 30 0000 C CNN +F 2 "" H 9400 8000 60 0000 C CNN +F 3 "" H 9400 8000 60 0000 C CNN + 14 9400 8000 + -1 0 0 -1 +$EndComp +$Comp +L PORT U14 +U 15 1 685DB820 +P 9350 7350 +F 0 "U14" H 9400 7450 30 0000 C CNN +F 1 "PORT" H 9350 7350 30 0000 C CNN +F 2 "" H 9350 7350 60 0000 C CNN +F 3 "" H 9350 7350 60 0000 C CNN + 15 9350 7350 + -1 0 0 -1 +$EndComp +$Comp +L PORT U14 +U 23 1 685DBA3D +P 9300 2100 +F 0 "U14" H 9350 2200 30 0000 C CNN +F 1 "PORT" H 9300 2100 30 0000 C CNN +F 2 "" H 9300 2100 60 0000 C CNN +F 3 "" H 9300 2100 60 0000 C CNN + 23 9300 2100 + -1 0 0 -1 +$EndComp +$Comp +L PORT U14 +U 20 1 685DBB39 +P 9250 4050 +F 0 "U14" H 9300 4150 30 0000 C CNN +F 1 "PORT" H 9250 4050 30 0000 C CNN +F 2 "" H 9250 4050 60 0000 C CNN +F 3 "" H 9250 4050 60 0000 C CNN + 20 9250 4050 + -1 0 0 -1 +$EndComp +$Comp +L PORT U14 +U 24 1 685DBC1E +P 6900 8650 +F 0 "U14" H 6950 8750 30 0000 C CNN +F 1 "PORT" H 6900 8650 30 0000 C CNN +F 2 "" H 6900 8650 60 0000 C CNN +F 3 "" H 6900 8650 60 0000 C CNN + 24 6900 8650 + -1 0 0 -1 +$EndComp +$Comp +L PORT U14 +U 21 1 685DBD6E +P 9300 3400 +F 0 "U14" H 9350 3500 30 0000 C CNN +F 1 "PORT" H 9300 3400 30 0000 C CNN +F 2 "" H 9300 3400 60 0000 C CNN +F 3 "" H 9300 3400 60 0000 C CNN + 21 9300 3400 + -1 0 0 -1 +$EndComp +$Comp +L PORT U14 +U 22 1 685DBEEF +P 9350 2750 +F 0 "U14" H 9400 2850 30 0000 C CNN +F 1 "PORT" H 9350 2750 30 0000 C CNN +F 2 "" H 9350 2750 60 0000 C CNN +F 3 "" H 9350 2750 60 0000 C CNN + 22 9350 2750 + -1 0 0 -1 +$EndComp +NoConn ~ 11800 2500 +NoConn ~ 13300 3050 +NoConn ~ 6200 8650 +NoConn ~ 6650 8650 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD74FCT827T/CD74FCT827T.sub b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD74FCT827T/CD74FCT827T.sub new file mode 100644 index 000000000..94cd08c5e --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD74FCT827T/CD74FCT827T.sub @@ -0,0 +1,58 @@ +* Subcircuit CD74FCT827T +.subckt CD74FCT827T net-_u11-pad1_ net-_u1-pad1_ net-_u14-pad3_ net-_u14-pad4_ net-_u14-pad5_ net-_u14-pad6_ net-_u14-pad7_ net-_u14-pad8_ net-_u14-pad9_ net-_u14-pad10_ net-_u10-pad1_ ? net-_u12-pad1_ net-_u10-pad3_ net-_u14-pad15_ net-_u14-pad16_ net-_u14-pad17_ net-_u14-pad18_ net-_u14-pad19_ net-_u14-pad20_ net-_u14-pad21_ net-_u14-pad22_ net-_u1-pad3_ ? +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\cd74fct827t\cd74fct827t.cir +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ one_input_tristate_buffer +* u2 net-_u14-pad3_ net-_u1-pad2_ net-_u14-pad22_ one_input_tristate_buffer +* u3 net-_u14-pad4_ net-_u1-pad2_ net-_u14-pad21_ one_input_tristate_buffer +* u4 net-_u14-pad5_ net-_u1-pad2_ net-_u14-pad20_ one_input_tristate_buffer +* u5 net-_u14-pad6_ net-_u1-pad2_ net-_u14-pad19_ one_input_tristate_buffer +* u6 net-_u14-pad7_ net-_u1-pad2_ net-_u14-pad18_ one_input_tristate_buffer +* u7 net-_u14-pad8_ net-_u1-pad2_ net-_u14-pad17_ one_input_tristate_buffer +* u8 net-_u14-pad9_ net-_u1-pad2_ net-_u14-pad16_ one_input_tristate_buffer +* u9 net-_u14-pad10_ net-_u1-pad2_ net-_u14-pad15_ one_input_tristate_buffer +* u10 net-_u10-pad1_ net-_u1-pad2_ net-_u10-pad3_ one_input_tristate_buffer +* u13 net-_u11-pad2_ net-_u12-pad2_ net-_u1-pad2_ d_and +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +a1 [net-_u1-pad1_ ] [net-_u1-pad2_ ] [net-_u1-pad3_ ] u1 +a2 [net-_u14-pad3_ ] [net-_u1-pad2_ ] [net-_u14-pad22_ ] u2 +a3 [net-_u14-pad4_ ] [net-_u1-pad2_ ] [net-_u14-pad21_ ] u3 +a4 [net-_u14-pad5_ ] [net-_u1-pad2_ ] [net-_u14-pad20_ ] u4 +a5 [net-_u14-pad6_ ] [net-_u1-pad2_ ] [net-_u14-pad19_ ] u5 +a6 [net-_u14-pad7_ ] [net-_u1-pad2_ ] [net-_u14-pad18_ ] u6 +a7 [net-_u14-pad8_ ] [net-_u1-pad2_ ] [net-_u14-pad17_ ] u7 +a8 [net-_u14-pad9_ ] [net-_u1-pad2_ ] [net-_u14-pad16_ ] u8 +a9 [net-_u14-pad10_ ] [net-_u1-pad2_ ] [net-_u14-pad15_ ] u9 +a10 [net-_u10-pad1_ ] [net-_u1-pad2_ ] [net-_u10-pad3_ ] u10 +a11 [net-_u11-pad2_ net-_u12-pad2_ ] net-_u1-pad2_ u13 +a12 net-_u11-pad1_ net-_u11-pad2_ u11 +a13 net-_u12-pad1_ net-_u12-pad2_ u12 +* Schematic Name: one_input_tristate_buffer, NgSpice Name: one_input_tristate_buffer +.model u1 one_input_tristate_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: one_input_tristate_buffer, NgSpice Name: one_input_tristate_buffer +.model u2 one_input_tristate_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: one_input_tristate_buffer, NgSpice Name: one_input_tristate_buffer +.model u3 one_input_tristate_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: one_input_tristate_buffer, NgSpice Name: one_input_tristate_buffer +.model u4 one_input_tristate_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: one_input_tristate_buffer, NgSpice Name: one_input_tristate_buffer +.model u5 one_input_tristate_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: one_input_tristate_buffer, NgSpice Name: one_input_tristate_buffer +.model u6 one_input_tristate_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: one_input_tristate_buffer, NgSpice Name: one_input_tristate_buffer +.model u7 one_input_tristate_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: one_input_tristate_buffer, NgSpice Name: one_input_tristate_buffer +.model u8 one_input_tristate_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: one_input_tristate_buffer, NgSpice Name: one_input_tristate_buffer +.model u9 one_input_tristate_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: one_input_tristate_buffer, NgSpice Name: one_input_tristate_buffer +.model u10 one_input_tristate_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends CD74FCT827T \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD74FCT827T/CD74FCT827T_Previous_Values.xml b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD74FCT827T/CD74FCT827T_Previous_Values.xml new file mode 100644 index 000000000..d78c35068 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD74FCT827T/CD74FCT827T_Previous_Values.xml @@ -0,0 +1 @@ +one_input_tristate_bufferone_input_tristate_bufferone_input_tristate_bufferone_input_tristate_bufferone_input_tristate_bufferone_input_tristate_bufferone_input_tristate_bufferone_input_tristate_bufferone_input_tristate_bufferone_input_tristate_bufferd_andd_inverterd_invertertruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD74FCT827T/analysis b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD74FCT827T/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/CD74FCT827T/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3306C/NMOS-180nm.lib b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3306C/NMOS-180nm.lib new file mode 100644 index 000000000..51e9b1196 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3306C/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3306C/PMOS-180nm.lib b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3306C/PMOS-180nm.lib new file mode 100644 index 000000000..032b5b95e --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3306C/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3306C/SN74CBT3306C-cache.lib b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3306C/SN74CBT3306C-cache.lib new file mode 100644 index 000000000..1efb9919a --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3306C/SN74CBT3306C-cache.lib @@ -0,0 +1,156 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# adc_bridge_1 +# +DEF adc_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_buffer +# +DEF d_buffer U 0 40 Y Y 1 F N +F0 "U" 0 -50 60 H V C CNN +F1 "d_buffer" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N +X IN 1 -500 0 200 R 50 50 1 1 I +X OUT 2 650 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# dac_bridge_1 +# +DEF dac_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3306C/SN74CBT3306C.cir b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3306C/SN74CBT3306C.cir new file mode 100644 index 000000000..57e55ab62 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3306C/SN74CBT3306C.cir @@ -0,0 +1,22 @@ +* C:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\SN74CBT3306C\SN74CBT3306C.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/25/25 17:10:43 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U1-Pad2_ Net-_M2-Pad2_ dac_bridge_1 +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ d_inverter +U2 Net-_U2-Pad1_ Net-_U1-Pad1_ adc_bridge_1 +U4 Net-_U2-Pad1_ Net-_M2-Pad1_ Net-_U4-Pad3_ GND Net-_M1-Pad1_ Net-_U4-Pad6_ Net-_M1-Pad2_ VCC PORT +M2 Net-_M2-Pad1_ Net-_M2-Pad2_ Net-_M2-Pad3_ GND mosfet_n +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ VCC mosfet_p +U5 Net-_U5-Pad1_ Net-_U4-Pad6_ dac_bridge_1 +U7 Net-_U7-Pad1_ Net-_U5-Pad1_ d_buffer +U9 Net-_M1-Pad3_ Net-_U7-Pad1_ adc_bridge_1 +U6 Net-_U6-Pad1_ Net-_U4-Pad3_ dac_bridge_1 +U8 Net-_U10-Pad2_ Net-_U6-Pad1_ d_buffer +U10 Net-_M2-Pad3_ Net-_U10-Pad2_ adc_bridge_1 + +.end diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3306C/SN74CBT3306C.cir.out b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3306C/SN74CBT3306C.cir.out new file mode 100644 index 000000000..98e159fb7 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3306C/SN74CBT3306C.cir.out @@ -0,0 +1,52 @@ +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\sn74cbt3306c\sn74cbt3306c.cir + +.include PMOS-180nm.lib +.include NMOS-180nm.lib +* u3 net-_u1-pad2_ net-_m2-pad2_ dac_bridge_1 +* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter +* u2 net-_u2-pad1_ net-_u1-pad1_ adc_bridge_1 +* u4 net-_u2-pad1_ net-_m2-pad1_ net-_u4-pad3_ gnd net-_m1-pad1_ net-_u4-pad6_ net-_m1-pad2_ vcc port +m2 net-_m2-pad1_ net-_m2-pad2_ net-_m2-pad3_ gnd CMOSN W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ vcc CMOSP W=100u L=100u M=1 +* u5 net-_u5-pad1_ net-_u4-pad6_ dac_bridge_1 +* u7 net-_u7-pad1_ net-_u5-pad1_ d_buffer +* u9 net-_m1-pad3_ net-_u7-pad1_ adc_bridge_1 +* u6 net-_u6-pad1_ net-_u4-pad3_ dac_bridge_1 +* u8 net-_u10-pad2_ net-_u6-pad1_ d_buffer +* u10 net-_m2-pad3_ net-_u10-pad2_ adc_bridge_1 +a1 [net-_u1-pad2_ ] [net-_m2-pad2_ ] u3 +a2 net-_u1-pad1_ net-_u1-pad2_ u1 +a3 [net-_u2-pad1_ ] [net-_u1-pad1_ ] u2 +a4 [net-_u5-pad1_ ] [net-_u4-pad6_ ] u5 +a5 net-_u7-pad1_ net-_u5-pad1_ u7 +a6 [net-_m1-pad3_ ] [net-_u7-pad1_ ] u9 +a7 [net-_u6-pad1_ ] [net-_u4-pad3_ ] u6 +a8 net-_u10-pad2_ net-_u6-pad1_ u8 +a9 [net-_m2-pad3_ ] [net-_u10-pad2_ ] u10 +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u3 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u5 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u7 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u9 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u6 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u8 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u10 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3306C/SN74CBT3306C.pro b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3306C/SN74CBT3306C.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3306C/SN74CBT3306C.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3306C/SN74CBT3306C.sch b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3306C/SN74CBT3306C.sch new file mode 100644 index 000000000..aec0f4aff --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3306C/SN74CBT3306C.sch @@ -0,0 +1,316 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN74CBT3306C-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 4350 2350 4550 2350 +Wire Wire Line + 5050 2350 4950 2350 +Text GLabel 5950 3150 0 60 Input ~ 0 +VCC +Text GLabel 5950 3400 0 60 Input ~ 0 +GND +$Comp +L dac_bridge_1 U3 +U 1 1 685BD8DE +P 4200 2850 +F 0 "U3" H 4200 2850 60 0000 C CNN +F 1 "dac_bridge_1" H 4200 3000 60 0000 C CNN +F 2 "" H 4200 2850 60 0000 C CNN +F 3 "" H 4200 2850 60 0000 C CNN + 1 4200 2850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U1 +U 1 1 685BDB46 +P 3500 3250 +F 0 "U1" H 3500 3150 60 0000 C CNN +F 1 "d_inverter" H 3500 3400 60 0000 C CNN +F 2 "" H 3550 3200 60 0000 C CNN +F 3 "" H 3550 3200 60 0000 C CNN + 1 3500 3250 + 0 -1 -1 0 +$EndComp +Text GLabel 4500 4450 1 60 Input ~ 0 +VCC +Text GLabel 5000 2200 2 60 Input ~ 0 +GND +Wire Wire Line + 4500 4450 4500 4600 +Wire Wire Line + 4750 2650 4750 2800 +Wire Wire Line + 3500 2950 3500 2800 +Wire Wire Line + 3500 2800 3600 2800 +$Comp +L adc_bridge_1 U2 +U 1 1 685BDDD9 +P 4100 3500 +F 0 "U2" H 4100 3500 60 0000 C CNN +F 1 "adc_bridge_1" H 4100 3650 60 0000 C CNN +F 2 "" H 4100 3500 60 0000 C CNN +F 3 "" H 4100 3500 60 0000 C CNN + 1 4100 3500 + -1 0 0 1 +$EndComp +Wire Wire Line + 3550 3550 3500 3550 +Wire Wire Line + 4150 4700 4000 4700 +Wire Wire Line + 4550 4700 4650 4700 +$Comp +L PORT U4 +U 1 1 685BDEB6 +P 5100 3550 +F 0 "U4" H 5150 3650 30 0000 C CNN +F 1 "PORT" H 5100 3550 30 0000 C CNN +F 2 "" H 5100 3550 60 0000 C CNN +F 3 "" H 5100 3550 60 0000 C CNN + 1 5100 3550 + -1 0 0 1 +$EndComp +$Comp +L PORT U4 +U 2 1 685BDF15 +P 4100 2350 +F 0 "U4" H 4150 2450 30 0000 C CNN +F 1 "PORT" H 4100 2350 30 0000 C CNN +F 2 "" H 4100 2350 60 0000 C CNN +F 3 "" H 4100 2350 60 0000 C CNN + 2 4100 2350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U4 +U 3 1 685BDF66 +P 8950 2350 +F 0 "U4" H 9000 2450 30 0000 C CNN +F 1 "PORT" H 8950 2350 30 0000 C CNN +F 2 "" H 8950 2350 60 0000 C CNN +F 3 "" H 8950 2350 60 0000 C CNN + 3 8950 2350 + -1 0 0 1 +$EndComp +$Comp +L PORT U4 +U 4 1 685BDF97 +P 6350 3400 +F 0 "U4" H 6400 3500 30 0000 C CNN +F 1 "PORT" H 6350 3400 30 0000 C CNN +F 2 "" H 6350 3400 60 0000 C CNN +F 3 "" H 6350 3400 60 0000 C CNN + 4 6350 3400 + -1 0 0 1 +$EndComp +$Comp +L PORT U4 +U 5 1 685BDFEC +P 4000 4450 +F 0 "U4" H 4050 4550 30 0000 C CNN +F 1 "PORT" H 4000 4450 30 0000 C CNN +F 2 "" H 4000 4450 60 0000 C CNN +F 3 "" H 4000 4450 60 0000 C CNN + 5 4000 4450 + 0 1 1 0 +$EndComp +$Comp +L PORT U4 +U 7 1 685BE0BE +P 4350 5450 +F 0 "U4" H 4400 5550 30 0000 C CNN +F 1 "PORT" H 4350 5450 30 0000 C CNN +F 2 "" H 4350 5450 60 0000 C CNN +F 3 "" H 4350 5450 60 0000 C CNN + 7 4350 5450 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U4 +U 8 1 685BE0F9 +P 6350 3150 +F 0 "U4" H 6400 3250 30 0000 C CNN +F 1 "PORT" H 6350 3150 30 0000 C CNN +F 2 "" H 6350 3150 60 0000 C CNN +F 3 "" H 6350 3150 60 0000 C CNN + 8 6350 3150 + -1 0 0 1 +$EndComp +Wire Wire Line + 5950 3150 6100 3150 +Wire Wire Line + 4350 5000 4350 5200 +Wire Wire Line + 4700 3550 4850 3550 +$Comp +L mosfet_n M2 +U 1 1 685BDC29 +P 4550 2550 +F 0 "M2" H 4550 2400 50 0000 R CNN +F 1 "mosfet_n" H 4650 2500 50 0000 R CNN +F 2 "" H 4850 2250 29 0000 C CNN +F 3 "" H 4650 2350 60 0000 C CNN + 1 4550 2550 + 0 -1 -1 0 +$EndComp +$Comp +L mosfet_p M1 +U 1 1 685BDA1A +P 4350 4850 +F 0 "M1" H 4300 4900 50 0000 R CNN +F 1 "mosfet_p" H 4400 5000 50 0000 R CNN +F 2 "" H 4600 4950 29 0000 C CNN +F 3 "" H 4400 4850 60 0000 C CNN + 1 4350 4850 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 4900 2250 4900 2200 +Wire Wire Line + 4900 2200 5000 2200 +Wire Wire Line + 6100 3400 5950 3400 +$Comp +L PORT U4 +U 6 1 685BE04D +P 8550 4700 +F 0 "U4" H 8600 4800 30 0000 C CNN +F 1 "PORT" H 8550 4700 30 0000 C CNN +F 2 "" H 8550 4700 60 0000 C CNN +F 3 "" H 8550 4700 60 0000 C CNN + 6 8550 4700 + -1 0 0 1 +$EndComp +$Comp +L dac_bridge_1 U5 +U 1 1 685C05B4 +P 7650 4750 +F 0 "U5" H 7650 4750 60 0000 C CNN +F 1 "dac_bridge_1" H 7650 4900 60 0000 C CNN +F 2 "" H 7650 4750 60 0000 C CNN +F 3 "" H 7650 4750 60 0000 C CNN + 1 7650 4750 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U7 +U 1 1 685C069C +P 6350 4700 +F 0 "U7" H 6350 4650 60 0000 C CNN +F 1 "d_buffer" H 6350 4750 60 0000 C CNN +F 2 "" H 6350 4700 60 0000 C CNN +F 3 "" H 6350 4700 60 0000 C CNN + 1 6350 4700 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_1 U9 +U 1 1 685C07CD +P 5250 4650 +F 0 "U9" H 5250 4650 60 0000 C CNN +F 1 "adc_bridge_1" H 5250 4800 60 0000 C CNN +F 2 "" H 5250 4650 60 0000 C CNN +F 3 "" H 5250 4650 60 0000 C CNN + 1 5250 4650 + 1 0 0 1 +$EndComp +$Comp +L dac_bridge_1 U6 +U 1 1 685C0BC5 +P 8050 2400 +F 0 "U6" H 8050 2400 60 0000 C CNN +F 1 "dac_bridge_1" H 8050 2550 60 0000 C CNN +F 2 "" H 8050 2400 60 0000 C CNN +F 3 "" H 8050 2400 60 0000 C CNN + 1 8050 2400 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U8 +U 1 1 685C0BCB +P 6750 2350 +F 0 "U8" H 6750 2300 60 0000 C CNN +F 1 "d_buffer" H 6750 2400 60 0000 C CNN +F 2 "" H 6750 2350 60 0000 C CNN +F 3 "" H 6750 2350 60 0000 C CNN + 1 6750 2350 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_1 U10 +U 1 1 685C0BD1 +P 5650 2300 +F 0 "U10" H 5650 2300 60 0000 C CNN +F 1 "adc_bridge_1" H 5650 2450 60 0000 C CNN +F 2 "" H 5650 2300 60 0000 C CNN +F 3 "" H 5650 2300 60 0000 C CNN + 1 5650 2300 + 1 0 0 1 +$EndComp +Wire Wire Line + 6200 2350 6250 2350 +Wire Wire Line + 7400 2350 7450 2350 +Wire Wire Line + 8600 2350 8700 2350 +Wire Wire Line + 5800 4700 5850 4700 +Wire Wire Line + 7000 4700 7050 4700 +Wire Wire Line + 8200 4700 8300 4700 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3306C/SN74CBT3306C.sub b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3306C/SN74CBT3306C.sub new file mode 100644 index 000000000..3ce264ec6 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3306C/SN74CBT3306C.sub @@ -0,0 +1,46 @@ +* Subcircuit SN74CBT3306C +.subckt SN74CBT3306C net-_u2-pad1_ net-_m2-pad1_ net-_u4-pad3_ gnd net-_m1-pad1_ net-_u4-pad6_ net-_m1-pad2_ vcc +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\sn74cbt3306c\sn74cbt3306c.cir +.include PMOS-180nm.lib +.include NMOS-180nm.lib +* u3 net-_u1-pad2_ net-_m2-pad2_ dac_bridge_1 +* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter +* u2 net-_u2-pad1_ net-_u1-pad1_ adc_bridge_1 +m2 net-_m2-pad1_ net-_m2-pad2_ net-_m2-pad3_ gnd CMOSN W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ vcc CMOSP W=100u L=100u M=1 +* u5 net-_u5-pad1_ net-_u4-pad6_ dac_bridge_1 +* u7 net-_u7-pad1_ net-_u5-pad1_ d_buffer +* u9 net-_m1-pad3_ net-_u7-pad1_ adc_bridge_1 +* u6 net-_u6-pad1_ net-_u4-pad3_ dac_bridge_1 +* u8 net-_u10-pad2_ net-_u6-pad1_ d_buffer +* u10 net-_m2-pad3_ net-_u10-pad2_ adc_bridge_1 +a1 [net-_u1-pad2_ ] [net-_m2-pad2_ ] u3 +a2 net-_u1-pad1_ net-_u1-pad2_ u1 +a3 [net-_u2-pad1_ ] [net-_u1-pad1_ ] u2 +a4 [net-_u5-pad1_ ] [net-_u4-pad6_ ] u5 +a5 net-_u7-pad1_ net-_u5-pad1_ u7 +a6 [net-_m1-pad3_ ] [net-_u7-pad1_ ] u9 +a7 [net-_u6-pad1_ ] [net-_u4-pad3_ ] u6 +a8 net-_u10-pad2_ net-_u6-pad1_ u8 +a9 [net-_m2-pad3_ ] [net-_u10-pad2_ ] u10 +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u3 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u5 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u7 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u9 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u6 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u8 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u10 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Control Statements + +.ends SN74CBT3306C \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3306C/SN74CBT3306C_Previous_Values.xml b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3306C/SN74CBT3306C_Previous_Values.xml new file mode 100644 index 000000000..12408bfbb --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3306C/SN74CBT3306C_Previous_Values.xml @@ -0,0 +1 @@ +dac_bridged_inverteradc_bridgedac_bridged_bufferadc_bridgedac_bridged_bufferadc_bridgeC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3306C/analysis b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3306C/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3306C/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3384A/NMOS-180nm.lib b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3384A/NMOS-180nm.lib new file mode 100644 index 000000000..51e9b1196 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3384A/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3384A/SN74CBT3384A-cache.lib b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3384A/SN74CBT3384A-cache.lib new file mode 100644 index 000000000..8ff81d329 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3384A/SN74CBT3384A-cache.lib @@ -0,0 +1,128 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# adc_bridge_1 +# +DEF adc_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_buffer +# +DEF d_buffer U 0 40 Y Y 1 F N +F0 "U" 0 -50 60 H V C CNN +F1 "d_buffer" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N +X IN 1 -500 0 200 R 50 50 1 1 I +X OUT 2 650 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# dac_bridge_1 +# +DEF dac_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3384A/SN74CBT3384A.cir b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3384A/SN74CBT3384A.cir new file mode 100644 index 000000000..3da70a8e9 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3384A/SN74CBT3384A.cir @@ -0,0 +1,55 @@ +* C:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\SN74CBT3384A\SN74CBT3384A.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/25/25 14:51:03 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ GND mosfet_n +M3 Net-_M3-Pad1_ Net-_M1-Pad2_ Net-_M3-Pad3_ GND mosfet_n +M5 Net-_M5-Pad1_ Net-_M1-Pad2_ Net-_M5-Pad3_ GND mosfet_n +M7 Net-_M7-Pad1_ Net-_M1-Pad2_ Net-_M7-Pad3_ GND mosfet_n +M9 Net-_M9-Pad1_ Net-_M1-Pad2_ Net-_M9-Pad3_ GND mosfet_n +M2 Net-_M2-Pad1_ Net-_M10-Pad2_ Net-_M2-Pad3_ GND mosfet_n +M4 Net-_M4-Pad1_ Net-_M10-Pad2_ Net-_M4-Pad3_ GND mosfet_n +M6 Net-_M6-Pad1_ Net-_M10-Pad2_ Net-_M6-Pad3_ GND mosfet_n +M8 Net-_M8-Pad1_ Net-_M10-Pad2_ Net-_M8-Pad3_ GND mosfet_n +M10 Net-_M10-Pad1_ Net-_M10-Pad2_ Net-_M10-Pad3_ GND mosfet_n +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_M1-Pad1_ Net-_M3-Pad1_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_M5-Pad1_ Net-_M7-Pad1_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_M9-Pad1_ GND Net-_U1-Pad13_ Net-_M2-Pad1_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_M4-Pad1_ Net-_M6-Pad1_ Net-_U1-Pad19_ Net-_U1-Pad20_ Net-_M8-Pad1_ Net-_M10-Pad1_ Net-_U1-Pad23_ ? PORT +U4 Net-_U2-Pad2_ Net-_M1-Pad2_ dac_bridge_1 +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter +U5 Net-_U3-Pad2_ Net-_M10-Pad2_ dac_bridge_1 +U3 Net-_U1-Pad13_ Net-_U3-Pad2_ d_inverter +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_buffer +U18 Net-_U18-Pad1_ Net-_U18-Pad2_ d_buffer +U20 Net-_U10-Pad2_ Net-_U20-Pad2_ d_buffer +U22 Net-_U13-Pad2_ Net-_U22-Pad2_ d_buffer +U24 Net-_U15-Pad2_ Net-_U24-Pad2_ d_buffer +U17 Net-_U17-Pad1_ Net-_U17-Pad2_ d_buffer +U19 Net-_U19-Pad1_ Net-_U19-Pad2_ d_buffer +U21 Net-_U11-Pad2_ Net-_U21-Pad2_ d_buffer +U23 Net-_U14-Pad2_ Net-_U23-Pad2_ d_buffer +U25 Net-_U16-Pad2_ Net-_U25-Pad2_ d_buffer +U6 Net-_M1-Pad3_ Net-_U12-Pad1_ adc_bridge_1 +U8 Net-_M3-Pad3_ Net-_U18-Pad1_ adc_bridge_1 +U10 Net-_M5-Pad3_ Net-_U10-Pad2_ adc_bridge_1 +U13 Net-_M7-Pad3_ Net-_U13-Pad2_ adc_bridge_1 +U15 Net-_M9-Pad3_ Net-_U15-Pad2_ adc_bridge_1 +U7 Net-_M2-Pad3_ Net-_U17-Pad1_ adc_bridge_1 +U9 Net-_M4-Pad3_ Net-_U19-Pad1_ adc_bridge_1 +U11 Net-_M6-Pad3_ Net-_U11-Pad2_ adc_bridge_1 +U14 Net-_M8-Pad3_ Net-_U14-Pad2_ adc_bridge_1 +U16 Net-_M10-Pad3_ Net-_U16-Pad2_ adc_bridge_1 +U28 Net-_U18-Pad2_ Net-_U1-Pad5_ dac_bridge_1 +U26 Net-_U12-Pad2_ Net-_U1-Pad2_ dac_bridge_1 +U31 Net-_U20-Pad2_ Net-_U1-Pad6_ dac_bridge_1 +U33 Net-_U22-Pad2_ Net-_U1-Pad9_ dac_bridge_1 +U35 Net-_U24-Pad2_ Net-_U1-Pad10_ dac_bridge_1 +U27 Net-_U17-Pad2_ Net-_U1-Pad15_ dac_bridge_1 +U29 Net-_U19-Pad2_ Net-_U1-Pad16_ dac_bridge_1 +U30 Net-_U21-Pad2_ Net-_U1-Pad19_ dac_bridge_1 +U32 Net-_U23-Pad2_ Net-_U1-Pad20_ dac_bridge_1 +U34 Net-_U25-Pad2_ Net-_U1-Pad23_ dac_bridge_1 + +.end diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3384A/SN74CBT3384A.cir.out b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3384A/SN74CBT3384A.cir.out new file mode 100644 index 000000000..b721ac748 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3384A/SN74CBT3384A.cir.out @@ -0,0 +1,159 @@ +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\sn74cbt3384a\sn74cbt3384a.cir + +.include NMOS-180nm.lib +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1 +m3 net-_m3-pad1_ net-_m1-pad2_ net-_m3-pad3_ gnd CMOSN W=100u L=100u M=1 +m5 net-_m5-pad1_ net-_m1-pad2_ net-_m5-pad3_ gnd CMOSN W=100u L=100u M=1 +m7 net-_m7-pad1_ net-_m1-pad2_ net-_m7-pad3_ gnd CMOSN W=100u L=100u M=1 +m9 net-_m9-pad1_ net-_m1-pad2_ net-_m9-pad3_ gnd CMOSN W=100u L=100u M=1 +m2 net-_m2-pad1_ net-_m10-pad2_ net-_m2-pad3_ gnd CMOSN W=100u L=100u M=1 +m4 net-_m4-pad1_ net-_m10-pad2_ net-_m4-pad3_ gnd CMOSN W=100u L=100u M=1 +m6 net-_m6-pad1_ net-_m10-pad2_ net-_m6-pad3_ gnd CMOSN W=100u L=100u M=1 +m8 net-_m8-pad1_ net-_m10-pad2_ net-_m8-pad3_ gnd CMOSN W=100u L=100u M=1 +m10 net-_m10-pad1_ net-_m10-pad2_ net-_m10-pad3_ gnd CMOSN W=100u L=100u M=1 +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_m1-pad1_ net-_m3-pad1_ net-_u1-pad5_ net-_u1-pad6_ net-_m5-pad1_ net-_m7-pad1_ net-_u1-pad9_ net-_u1-pad10_ net-_m9-pad1_ gnd net-_u1-pad13_ net-_m2-pad1_ net-_u1-pad15_ net-_u1-pad16_ net-_m4-pad1_ net-_m6-pad1_ net-_u1-pad19_ net-_u1-pad20_ net-_m8-pad1_ net-_m10-pad1_ net-_u1-pad23_ ? port +* u4 net-_u2-pad2_ net-_m1-pad2_ dac_bridge_1 +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u5 net-_u3-pad2_ net-_m10-pad2_ dac_bridge_1 +* u3 net-_u1-pad13_ net-_u3-pad2_ d_inverter +* u12 net-_u12-pad1_ net-_u12-pad2_ d_buffer +* u18 net-_u18-pad1_ net-_u18-pad2_ d_buffer +* u20 net-_u10-pad2_ net-_u20-pad2_ d_buffer +* u22 net-_u13-pad2_ net-_u22-pad2_ d_buffer +* u24 net-_u15-pad2_ net-_u24-pad2_ d_buffer +* u17 net-_u17-pad1_ net-_u17-pad2_ d_buffer +* u19 net-_u19-pad1_ net-_u19-pad2_ d_buffer +* u21 net-_u11-pad2_ net-_u21-pad2_ d_buffer +* u23 net-_u14-pad2_ net-_u23-pad2_ d_buffer +* u25 net-_u16-pad2_ net-_u25-pad2_ d_buffer +* u6 net-_m1-pad3_ net-_u12-pad1_ adc_bridge_1 +* u8 net-_m3-pad3_ net-_u18-pad1_ adc_bridge_1 +* u10 net-_m5-pad3_ net-_u10-pad2_ adc_bridge_1 +* u13 net-_m7-pad3_ net-_u13-pad2_ adc_bridge_1 +* u15 net-_m9-pad3_ net-_u15-pad2_ adc_bridge_1 +* u7 net-_m2-pad3_ net-_u17-pad1_ adc_bridge_1 +* u9 net-_m4-pad3_ net-_u19-pad1_ adc_bridge_1 +* u11 net-_m6-pad3_ net-_u11-pad2_ adc_bridge_1 +* u14 net-_m8-pad3_ net-_u14-pad2_ adc_bridge_1 +* u16 net-_m10-pad3_ net-_u16-pad2_ adc_bridge_1 +* u28 net-_u18-pad2_ net-_u1-pad5_ dac_bridge_1 +* u26 net-_u12-pad2_ net-_u1-pad2_ dac_bridge_1 +* u31 net-_u20-pad2_ net-_u1-pad6_ dac_bridge_1 +* u33 net-_u22-pad2_ net-_u1-pad9_ dac_bridge_1 +* u35 net-_u24-pad2_ net-_u1-pad10_ dac_bridge_1 +* u27 net-_u17-pad2_ net-_u1-pad15_ dac_bridge_1 +* u29 net-_u19-pad2_ net-_u1-pad16_ dac_bridge_1 +* u30 net-_u21-pad2_ net-_u1-pad19_ dac_bridge_1 +* u32 net-_u23-pad2_ net-_u1-pad20_ dac_bridge_1 +* u34 net-_u25-pad2_ net-_u1-pad23_ dac_bridge_1 +a1 [net-_u2-pad2_ ] [net-_m1-pad2_ ] u4 +a2 net-_u1-pad1_ net-_u2-pad2_ u2 +a3 [net-_u3-pad2_ ] [net-_m10-pad2_ ] u5 +a4 net-_u1-pad13_ net-_u3-pad2_ u3 +a5 net-_u12-pad1_ net-_u12-pad2_ u12 +a6 net-_u18-pad1_ net-_u18-pad2_ u18 +a7 net-_u10-pad2_ net-_u20-pad2_ u20 +a8 net-_u13-pad2_ net-_u22-pad2_ u22 +a9 net-_u15-pad2_ net-_u24-pad2_ u24 +a10 net-_u17-pad1_ net-_u17-pad2_ u17 +a11 net-_u19-pad1_ net-_u19-pad2_ u19 +a12 net-_u11-pad2_ net-_u21-pad2_ u21 +a13 net-_u14-pad2_ net-_u23-pad2_ u23 +a14 net-_u16-pad2_ net-_u25-pad2_ u25 +a15 [net-_m1-pad3_ ] [net-_u12-pad1_ ] u6 +a16 [net-_m3-pad3_ ] [net-_u18-pad1_ ] u8 +a17 [net-_m5-pad3_ ] [net-_u10-pad2_ ] u10 +a18 [net-_m7-pad3_ ] [net-_u13-pad2_ ] u13 +a19 [net-_m9-pad3_ ] [net-_u15-pad2_ ] u15 +a20 [net-_m2-pad3_ ] [net-_u17-pad1_ ] u7 +a21 [net-_m4-pad3_ ] [net-_u19-pad1_ ] u9 +a22 [net-_m6-pad3_ ] [net-_u11-pad2_ ] u11 +a23 [net-_m8-pad3_ ] [net-_u14-pad2_ ] u14 +a24 [net-_m10-pad3_ ] [net-_u16-pad2_ ] u16 +a25 [net-_u18-pad2_ ] [net-_u1-pad5_ ] u28 +a26 [net-_u12-pad2_ ] [net-_u1-pad2_ ] u26 +a27 [net-_u20-pad2_ ] [net-_u1-pad6_ ] u31 +a28 [net-_u22-pad2_ ] [net-_u1-pad9_ ] u33 +a29 [net-_u24-pad2_ ] [net-_u1-pad10_ ] u35 +a30 [net-_u17-pad2_ ] [net-_u1-pad15_ ] u27 +a31 [net-_u19-pad2_ ] [net-_u1-pad16_ ] u29 +a32 [net-_u21-pad2_ ] [net-_u1-pad19_ ] u30 +a33 [net-_u23-pad2_ ] [net-_u1-pad20_ ] u32 +a34 [net-_u25-pad2_ ] [net-_u1-pad23_ ] u34 +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u4 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u5 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u12 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u18 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u20 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u22 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u24 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u17 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u19 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u21 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u23 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u25 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u6 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u8 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u10 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u13 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u15 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u7 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u9 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u11 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u14 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u16 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u28 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u26 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u31 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u33 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u35 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u27 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u29 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u30 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u32 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u34 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3384A/SN74CBT3384A.pro b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3384A/SN74CBT3384A.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3384A/SN74CBT3384A.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3384A/SN74CBT3384A.sch b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3384A/SN74CBT3384A.sch new file mode 100644 index 000000000..f2edccd28 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3384A/SN74CBT3384A.sch @@ -0,0 +1,994 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN74CBT3384A-cache +EELAYER 25 0 +EELAYER END +$Descr A3 16535 11693 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L mosfet_n M1 +U 1 1 685B918C +P 5850 2200 +F 0 "M1" H 5850 2050 50 0000 R CNN +F 1 "mosfet_n" H 5950 2150 50 0000 R CNN +F 2 "" H 6150 1900 29 0000 C CNN +F 3 "" H 5950 2000 60 0000 C CNN + 1 5850 2200 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 6200 1900 6300 1900 +Wire Wire Line + 6300 1900 6300 1850 +$Comp +L mosfet_n M3 +U 1 1 685B920F +P 6250 2600 +F 0 "M3" H 6250 2450 50 0000 R CNN +F 1 "mosfet_n" H 6350 2550 50 0000 R CNN +F 2 "" H 6550 2300 29 0000 C CNN +F 3 "" H 6350 2400 60 0000 C CNN + 1 6250 2600 + 0 -1 -1 0 +$EndComp +$Comp +L mosfet_n M5 +U 1 1 685B9249 +P 6650 3050 +F 0 "M5" H 6650 2900 50 0000 R CNN +F 1 "mosfet_n" H 6750 3000 50 0000 R CNN +F 2 "" H 6950 2750 29 0000 C CNN +F 3 "" H 6750 2850 60 0000 C CNN + 1 6650 3050 + 0 -1 -1 0 +$EndComp +$Comp +L mosfet_n M7 +U 1 1 685B92D3 +P 7000 3500 +F 0 "M7" H 7000 3350 50 0000 R CNN +F 1 "mosfet_n" H 7100 3450 50 0000 R CNN +F 2 "" H 7300 3200 29 0000 C CNN +F 3 "" H 7100 3300 60 0000 C CNN + 1 7000 3500 + 0 -1 -1 0 +$EndComp +$Comp +L mosfet_n M9 +U 1 1 685B9318 +P 7300 3900 +F 0 "M9" H 7300 3750 50 0000 R CNN +F 1 "mosfet_n" H 7400 3850 50 0000 R CNN +F 2 "" H 7600 3600 29 0000 C CNN +F 3 "" H 7400 3700 60 0000 C CNN + 1 7300 3900 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 7500 4400 7500 4000 +Wire Wire Line + 7200 3600 7200 4400 +Connection ~ 7200 4400 +Wire Wire Line + 6850 3150 6850 4400 +Connection ~ 6850 4400 +Wire Wire Line + 6450 2700 6450 4400 +Connection ~ 6450 4400 +Wire Wire Line + 6050 2300 6050 4400 +Connection ~ 6050 4400 +Wire Wire Line + 5850 2000 5100 2000 +Wire Wire Line + 6250 2400 5100 2400 +Wire Wire Line + 6650 2850 5100 2850 +Wire Wire Line + 6600 2200 6600 2300 +Wire Wire Line + 6650 2400 7050 2400 +Wire Wire Line + 7000 2650 7000 2750 +Wire Wire Line + 7050 2850 7300 2850 +Wire Wire Line + 7350 3050 7350 3200 +Wire Wire Line + 7400 3300 7850 3300 +Wire Wire Line + 7650 3500 7650 3600 +Wire Wire Line + 7700 3700 8000 3700 +Wire Wire Line + 7300 3700 5100 3700 +Wire Wire Line + 7000 3300 5150 3300 +$Comp +L mosfet_n M2 +U 1 1 685B9B81 +P 5850 5200 +F 0 "M2" H 5850 5050 50 0000 R CNN +F 1 "mosfet_n" H 5950 5150 50 0000 R CNN +F 2 "" H 6150 4900 29 0000 C CNN +F 3 "" H 5950 5000 60 0000 C CNN + 1 5850 5200 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 6200 4900 6300 4900 +Wire Wire Line + 6300 4900 6300 4850 +$Comp +L mosfet_n M4 +U 1 1 685B9B89 +P 6250 5600 +F 0 "M4" H 6250 5450 50 0000 R CNN +F 1 "mosfet_n" H 6350 5550 50 0000 R CNN +F 2 "" H 6550 5300 29 0000 C CNN +F 3 "" H 6350 5400 60 0000 C CNN + 1 6250 5600 + 0 -1 -1 0 +$EndComp +$Comp +L mosfet_n M6 +U 1 1 685B9B8F +P 6650 6050 +F 0 "M6" H 6650 5900 50 0000 R CNN +F 1 "mosfet_n" H 6750 6000 50 0000 R CNN +F 2 "" H 6950 5750 29 0000 C CNN +F 3 "" H 6750 5850 60 0000 C CNN + 1 6650 6050 + 0 -1 -1 0 +$EndComp +$Comp +L mosfet_n M8 +U 1 1 685B9B95 +P 7000 6500 +F 0 "M8" H 7000 6350 50 0000 R CNN +F 1 "mosfet_n" H 7100 6450 50 0000 R CNN +F 2 "" H 7300 6200 29 0000 C CNN +F 3 "" H 7100 6300 60 0000 C CNN + 1 7000 6500 + 0 -1 -1 0 +$EndComp +$Comp +L mosfet_n M10 +U 1 1 685B9B9B +P 7300 6900 +F 0 "M10" H 7300 6750 50 0000 R CNN +F 1 "mosfet_n" H 7400 6850 50 0000 R CNN +F 2 "" H 7600 6600 29 0000 C CNN +F 3 "" H 7400 6700 60 0000 C CNN + 1 7300 6900 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 7500 7400 7500 7000 +Wire Wire Line + 7200 6600 7200 7400 +Connection ~ 7200 7400 +Wire Wire Line + 6850 6150 6850 7400 +Connection ~ 6850 7400 +Wire Wire Line + 6450 5700 6450 7400 +Connection ~ 6450 7400 +Wire Wire Line + 6050 5300 6050 7400 +Connection ~ 6050 7400 +Wire Wire Line + 5850 5000 5100 5000 +Wire Wire Line + 6250 5400 5100 5400 +Wire Wire Line + 6650 5850 5100 5850 +Wire Wire Line + 6600 5200 6600 5300 +Wire Wire Line + 6250 5000 6950 5000 +Wire Wire Line + 6650 5400 7050 5400 +Wire Wire Line + 7000 5650 7000 5750 +Wire Wire Line + 7050 5850 7300 5850 +Wire Wire Line + 7350 6050 7350 6200 +Wire Wire Line + 7400 6300 7850 6300 +Wire Wire Line + 7650 6500 7650 6600 +Wire Wire Line + 7700 6700 8000 6700 +Wire Wire Line + 7300 6700 5100 6700 +Wire Wire Line + 7000 6300 5150 6300 +Text GLabel 950 1200 0 60 Input ~ 0 +GND +$Comp +L PORT U1 +U 24 1 685B9E3C +P 1450 750 +F 0 "U1" H 1500 850 30 0000 C CNN +F 1 "PORT" H 1450 750 30 0000 C CNN +F 2 "" H 1450 750 60 0000 C CNN +F 3 "" H 1450 750 60 0000 C CNN + 24 1450 750 + -1 0 0 1 +$EndComp +Wire Wire Line + 950 1200 1150 1200 +Text GLabel 6300 1850 2 60 Input ~ 0 +GND +Text GLabel 6600 2200 2 60 Input ~ 0 +GND +Text GLabel 7000 2650 2 60 Input ~ 0 +GND +Text GLabel 7350 3050 2 60 Input ~ 0 +GND +Text GLabel 7650 3500 2 60 Input ~ 0 +GND +$Comp +L PORT U1 +U 3 1 685BA224 +P 4850 2000 +F 0 "U1" H 4900 2100 30 0000 C CNN +F 1 "PORT" H 4850 2000 30 0000 C CNN +F 2 "" H 4850 2000 60 0000 C CNN +F 3 "" H 4850 2000 60 0000 C CNN + 3 4850 2000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 685BA30F +P 4850 2400 +F 0 "U1" H 4900 2500 30 0000 C CNN +F 1 "PORT" H 4850 2400 30 0000 C CNN +F 2 "" H 4850 2400 60 0000 C CNN +F 3 "" H 4850 2400 60 0000 C CNN + 4 4850 2400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 685BA39B +P 10950 2400 +F 0 "U1" H 11000 2500 30 0000 C CNN +F 1 "PORT" H 10950 2400 30 0000 C CNN +F 2 "" H 10950 2400 60 0000 C CNN +F 3 "" H 10950 2400 60 0000 C CNN + 5 10950 2400 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 685BA458 +P 4850 3700 +F 0 "U1" H 4900 3800 30 0000 C CNN +F 1 "PORT" H 4850 3700 30 0000 C CNN +F 2 "" H 4850 3700 60 0000 C CNN +F 3 "" H 4850 3700 60 0000 C CNN + 11 4850 3700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 685BA50F +P 11300 2850 +F 0 "U1" H 11350 2950 30 0000 C CNN +F 1 "PORT" H 11300 2850 30 0000 C CNN +F 2 "" H 11300 2850 60 0000 C CNN +F 3 "" H 11300 2850 60 0000 C CNN + 6 11300 2850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 685BA59A +P 3500 7400 +F 0 "U1" H 3550 7500 30 0000 C CNN +F 1 "PORT" H 3500 7400 30 0000 C CNN +F 2 "" H 3500 7400 60 0000 C CNN +F 3 "" H 3500 7400 60 0000 C CNN + 13 3500 7400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 15 1 685BA5DD +P 10900 5000 +F 0 "U1" H 10950 5100 30 0000 C CNN +F 1 "PORT" H 10900 5000 30 0000 C CNN +F 2 "" H 10900 5000 60 0000 C CNN +F 3 "" H 10900 5000 60 0000 C CNN + 15 10900 5000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 17 1 685BA636 +P 4850 5400 +F 0 "U1" H 4900 5500 30 0000 C CNN +F 1 "PORT" H 4850 5400 30 0000 C CNN +F 2 "" H 4850 5400 60 0000 C CNN +F 3 "" H 4850 5400 60 0000 C CNN + 17 4850 5400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 19 1 685BA691 +P 11250 5850 +F 0 "U1" H 11300 5950 30 0000 C CNN +F 1 "PORT" H 11250 5850 30 0000 C CNN +F 2 "" H 11250 5850 60 0000 C CNN +F 3 "" H 11250 5850 60 0000 C CNN + 19 11250 5850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 21 1 685BA77C +P 4900 6300 +F 0 "U1" H 4950 6400 30 0000 C CNN +F 1 "PORT" H 4900 6300 30 0000 C CNN +F 2 "" H 4900 6300 60 0000 C CNN +F 3 "" H 4900 6300 60 0000 C CNN + 21 4900 6300 + 1 0 0 -1 +$EndComp +Text GLabel 6300 4850 2 60 Input ~ 0 +GND +Text GLabel 6600 5200 2 60 Input ~ 0 +GND +Text GLabel 7000 5650 2 60 Input ~ 0 +GND +Text GLabel 7350 6050 2 60 Input ~ 0 +GND +Text GLabel 7650 6500 2 60 Input ~ 0 +GND +$Comp +L PORT U1 +U 1 1 685BAE23 +P 3500 4400 +F 0 "U1" H 3550 4500 30 0000 C CNN +F 1 "PORT" H 3500 4400 30 0000 C CNN +F 2 "" H 3500 4400 60 0000 C CNN +F 3 "" H 3500 4400 60 0000 C CNN + 1 3500 4400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 685BAEBC +P 4850 2850 +F 0 "U1" H 4900 2950 30 0000 C CNN +F 1 "PORT" H 4850 2850 30 0000 C CNN +F 2 "" H 4850 2850 60 0000 C CNN +F 3 "" H 4850 2850 60 0000 C CNN + 7 4850 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 685BAF98 +P 4900 3300 +F 0 "U1" H 4950 3400 30 0000 C CNN +F 1 "PORT" H 4900 3300 30 0000 C CNN +F 2 "" H 4900 3300 60 0000 C CNN +F 3 "" H 4900 3300 60 0000 C CNN + 8 4900 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 685BB06D +P 11850 3300 +F 0 "U1" H 11900 3400 30 0000 C CNN +F 1 "PORT" H 11850 3300 30 0000 C CNN +F 2 "" H 11850 3300 60 0000 C CNN +F 3 "" H 11850 3300 60 0000 C CNN + 9 11850 3300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 685BB147 +P 1400 1200 +F 0 "U1" H 1450 1300 30 0000 C CNN +F 1 "PORT" H 1400 1200 30 0000 C CNN +F 2 "" H 1400 1200 60 0000 C CNN +F 3 "" H 1400 1200 60 0000 C CNN + 12 1400 1200 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 10 1 685BB196 +P 12000 3700 +F 0 "U1" H 12050 3800 30 0000 C CNN +F 1 "PORT" H 12000 3700 30 0000 C CNN +F 2 "" H 12000 3700 60 0000 C CNN +F 3 "" H 12000 3700 60 0000 C CNN + 10 12000 3700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 685BB261 +P 10500 2000 +F 0 "U1" H 10550 2100 30 0000 C CNN +F 1 "PORT" H 10500 2000 30 0000 C CNN +F 2 "" H 10500 2000 60 0000 C CNN +F 3 "" H 10500 2000 60 0000 C CNN + 2 10500 2000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 685BB41E +P 4850 5000 +F 0 "U1" H 4900 5100 30 0000 C CNN +F 1 "PORT" H 4850 5000 30 0000 C CNN +F 2 "" H 4850 5000 60 0000 C CNN +F 3 "" H 4850 5000 60 0000 C CNN + 14 4850 5000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 685BB4E4 +P 11050 5400 +F 0 "U1" H 11100 5500 30 0000 C CNN +F 1 "PORT" H 11050 5400 30 0000 C CNN +F 2 "" H 11050 5400 60 0000 C CNN +F 3 "" H 11050 5400 60 0000 C CNN + 16 11050 5400 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 18 1 685BB583 +P 4850 5850 +F 0 "U1" H 4900 5950 30 0000 C CNN +F 1 "PORT" H 4850 5850 30 0000 C CNN +F 2 "" H 4850 5850 60 0000 C CNN +F 3 "" H 4850 5850 60 0000 C CNN + 18 4850 5850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 20 1 685BB687 +P 11850 6300 +F 0 "U1" H 11900 6400 30 0000 C CNN +F 1 "PORT" H 11850 6300 30 0000 C CNN +F 2 "" H 11850 6300 60 0000 C CNN +F 3 "" H 11850 6300 60 0000 C CNN + 20 11850 6300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 22 1 685BB79A +P 4850 6700 +F 0 "U1" H 4900 6800 30 0000 C CNN +F 1 "PORT" H 4850 6700 30 0000 C CNN +F 2 "" H 4850 6700 60 0000 C CNN +F 3 "" H 4850 6700 60 0000 C CNN + 22 4850 6700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 23 1 685BB95B +P 12000 6700 +F 0 "U1" H 12050 6800 30 0000 C CNN +F 1 "PORT" H 12000 6700 30 0000 C CNN +F 2 "" H 12000 6700 60 0000 C CNN +F 3 "" H 12000 6700 60 0000 C CNN + 23 12000 6700 + -1 0 0 1 +$EndComp +NoConn ~ 1200 750 +$Comp +L dac_bridge_1 U4 +U 1 1 685C2A8F +P 5350 4450 +F 0 "U4" H 5350 4450 60 0000 C CNN +F 1 "dac_bridge_1" H 5350 4600 60 0000 C CNN +F 2 "" H 5350 4450 60 0000 C CNN +F 3 "" H 5350 4450 60 0000 C CNN + 1 5350 4450 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 685C2BF2 +P 4200 4400 +F 0 "U2" H 4200 4300 60 0000 C CNN +F 1 "d_inverter" H 4200 4550 60 0000 C CNN +F 2 "" H 4250 4350 60 0000 C CNN +F 3 "" H 4250 4350 60 0000 C CNN + 1 4200 4400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3750 4400 3900 4400 +Wire Wire Line + 4500 4400 4750 4400 +Wire Wire Line + 5900 4400 7500 4400 +$Comp +L dac_bridge_1 U5 +U 1 1 685C3784 +P 5400 7450 +F 0 "U5" H 5400 7450 60 0000 C CNN +F 1 "dac_bridge_1" H 5400 7600 60 0000 C CNN +F 2 "" H 5400 7450 60 0000 C CNN +F 3 "" H 5400 7450 60 0000 C CNN + 1 5400 7450 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 685C378A +P 4250 7400 +F 0 "U3" H 4250 7300 60 0000 C CNN +F 1 "d_inverter" H 4250 7550 60 0000 C CNN +F 2 "" H 4300 7350 60 0000 C CNN +F 3 "" H 4300 7350 60 0000 C CNN + 1 4250 7400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4550 7400 4800 7400 +Wire Wire Line + 3750 7400 3950 7400 +Wire Wire Line + 5950 7400 7500 7400 +$Comp +L d_buffer U12 +U 1 1 685C492D +P 8350 2000 +F 0 "U12" H 8350 1950 60 0000 C CNN +F 1 "d_buffer" H 8350 2050 60 0000 C CNN +F 2 "" H 8350 2000 60 0000 C CNN +F 3 "" H 8350 2000 60 0000 C CNN + 1 8350 2000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7750 2000 7850 2000 +$Comp +L d_buffer U18 +U 1 1 685C5561 +P 8800 2400 +F 0 "U18" H 8800 2350 60 0000 C CNN +F 1 "d_buffer" H 8800 2450 60 0000 C CNN +F 2 "" H 8800 2400 60 0000 C CNN +F 3 "" H 8800 2400 60 0000 C CNN + 1 8800 2400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8200 2400 8300 2400 +$Comp +L d_buffer U20 +U 1 1 685C562E +P 9050 2850 +F 0 "U20" H 9050 2800 60 0000 C CNN +F 1 "d_buffer" H 9050 2900 60 0000 C CNN +F 2 "" H 9050 2850 60 0000 C CNN +F 3 "" H 9050 2850 60 0000 C CNN + 1 9050 2850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8450 2850 8550 2850 +$Comp +L d_buffer U22 +U 1 1 685C563B +P 9600 3300 +F 0 "U22" H 9600 3250 60 0000 C CNN +F 1 "d_buffer" H 9600 3350 60 0000 C CNN +F 2 "" H 9600 3300 60 0000 C CNN +F 3 "" H 9600 3300 60 0000 C CNN + 1 9600 3300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9000 3300 9100 3300 +$Comp +L d_buffer U24 +U 1 1 685C583E +P 9750 3700 +F 0 "U24" H 9750 3650 60 0000 C CNN +F 1 "d_buffer" H 9750 3750 60 0000 C CNN +F 2 "" H 9750 3700 60 0000 C CNN +F 3 "" H 9750 3700 60 0000 C CNN + 1 9750 3700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9150 3700 9250 3700 +$Comp +L d_buffer U17 +U 1 1 685C584B +P 8700 5000 +F 0 "U17" H 8700 4950 60 0000 C CNN +F 1 "d_buffer" H 8700 5050 60 0000 C CNN +F 2 "" H 8700 5000 60 0000 C CNN +F 3 "" H 8700 5000 60 0000 C CNN + 1 8700 5000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8100 5000 8200 5000 +$Comp +L d_buffer U19 +U 1 1 685C5858 +P 8800 5400 +F 0 "U19" H 8800 5350 60 0000 C CNN +F 1 "d_buffer" H 8800 5450 60 0000 C CNN +F 2 "" H 8800 5400 60 0000 C CNN +F 3 "" H 8800 5400 60 0000 C CNN + 1 8800 5400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8200 5400 8300 5400 +$Comp +L d_buffer U21 +U 1 1 685C5865 +P 9050 5850 +F 0 "U21" H 9050 5800 60 0000 C CNN +F 1 "d_buffer" H 9050 5900 60 0000 C CNN +F 2 "" H 9050 5850 60 0000 C CNN +F 3 "" H 9050 5850 60 0000 C CNN + 1 9050 5850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9000 2000 9050 2000 +Wire Wire Line + 9450 2400 9500 2400 +Wire Wire Line + 9700 2850 9850 2850 +Wire Wire Line + 10250 3300 10400 3300 +Wire Wire Line + 10400 3700 10550 3700 +$Comp +L d_buffer U23 +U 1 1 685C7FB6 +P 9600 6300 +F 0 "U23" H 9600 6250 60 0000 C CNN +F 1 "d_buffer" H 9600 6350 60 0000 C CNN +F 2 "" H 9600 6300 60 0000 C CNN +F 3 "" H 9600 6300 60 0000 C CNN + 1 9600 6300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9000 6300 9100 6300 +$Comp +L d_buffer U25 +U 1 1 685C7FC3 +P 9750 6700 +F 0 "U25" H 9750 6650 60 0000 C CNN +F 1 "d_buffer" H 9750 6750 60 0000 C CNN +F 2 "" H 9750 6700 60 0000 C CNN +F 3 "" H 9750 6700 60 0000 C CNN + 1 9750 6700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9150 6700 9250 6700 +Wire Wire Line + 8450 5850 8550 5850 +Wire Wire Line + 9350 5000 9400 5000 +Wire Wire Line + 9550 5400 9450 5400 +Wire Wire Line + 9700 5850 9750 5850 +Wire Wire Line + 10250 6300 10300 6300 +Wire Wire Line + 10400 6700 10450 6700 +Wire Wire Line + 6600 2000 6250 2000 +$Comp +L adc_bridge_1 U6 +U 1 1 685CAA27 +P 7200 2050 +F 0 "U6" H 7200 2050 60 0000 C CNN +F 1 "adc_bridge_1" H 7200 2200 60 0000 C CNN +F 2 "" H 7200 2050 60 0000 C CNN +F 3 "" H 7200 2050 60 0000 C CNN + 1 7200 2050 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_1 U8 +U 1 1 685CAAE1 +P 7650 2450 +F 0 "U8" H 7650 2450 60 0000 C CNN +F 1 "adc_bridge_1" H 7650 2600 60 0000 C CNN +F 2 "" H 7650 2450 60 0000 C CNN +F 3 "" H 7650 2450 60 0000 C CNN + 1 7650 2450 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_1 U10 +U 1 1 685CAB93 +P 7900 2900 +F 0 "U10" H 7900 2900 60 0000 C CNN +F 1 "adc_bridge_1" H 7900 3050 60 0000 C CNN +F 2 "" H 7900 2900 60 0000 C CNN +F 3 "" H 7900 2900 60 0000 C CNN + 1 7900 2900 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_1 U13 +U 1 1 685CAC4A +P 8450 3350 +F 0 "U13" H 8450 3350 60 0000 C CNN +F 1 "adc_bridge_1" H 8450 3500 60 0000 C CNN +F 2 "" H 8450 3350 60 0000 C CNN +F 3 "" H 8450 3350 60 0000 C CNN + 1 8450 3350 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_1 U15 +U 1 1 685CAD04 +P 8600 3750 +F 0 "U15" H 8600 3750 60 0000 C CNN +F 1 "adc_bridge_1" H 8600 3900 60 0000 C CNN +F 2 "" H 8600 3750 60 0000 C CNN +F 3 "" H 8600 3750 60 0000 C CNN + 1 8600 3750 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_1 U7 +U 1 1 685CADB7 +P 7550 5050 +F 0 "U7" H 7550 5050 60 0000 C CNN +F 1 "adc_bridge_1" H 7550 5200 60 0000 C CNN +F 2 "" H 7550 5050 60 0000 C CNN +F 3 "" H 7550 5050 60 0000 C CNN + 1 7550 5050 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_1 U9 +U 1 1 685CAF65 +P 7650 5450 +F 0 "U9" H 7650 5450 60 0000 C CNN +F 1 "adc_bridge_1" H 7650 5600 60 0000 C CNN +F 2 "" H 7650 5450 60 0000 C CNN +F 3 "" H 7650 5450 60 0000 C CNN + 1 7650 5450 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_1 U11 +U 1 1 685CB02C +P 7900 5900 +F 0 "U11" H 7900 5900 60 0000 C CNN +F 1 "adc_bridge_1" H 7900 6050 60 0000 C CNN +F 2 "" H 7900 5900 60 0000 C CNN +F 3 "" H 7900 5900 60 0000 C CNN + 1 7900 5900 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_1 U14 +U 1 1 685CB27E +P 8450 6350 +F 0 "U14" H 8450 6350 60 0000 C CNN +F 1 "adc_bridge_1" H 8450 6500 60 0000 C CNN +F 2 "" H 8450 6350 60 0000 C CNN +F 3 "" H 8450 6350 60 0000 C CNN + 1 8450 6350 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_1 U16 +U 1 1 685CB3F8 +P 8600 6750 +F 0 "U16" H 8600 6750 60 0000 C CNN +F 1 "adc_bridge_1" H 8600 6900 60 0000 C CNN +F 2 "" H 8600 6750 60 0000 C CNN +F 3 "" H 8600 6750 60 0000 C CNN + 1 8600 6750 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U28 +U 1 1 685CC0BE +P 10100 2450 +F 0 "U28" H 10100 2450 60 0000 C CNN +F 1 "dac_bridge_1" H 10100 2600 60 0000 C CNN +F 2 "" H 10100 2450 60 0000 C CNN +F 3 "" H 10100 2450 60 0000 C CNN + 1 10100 2450 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U26 +U 1 1 685CC504 +P 9650 2050 +F 0 "U26" H 9650 2050 60 0000 C CNN +F 1 "dac_bridge_1" H 9650 2200 60 0000 C CNN +F 2 "" H 9650 2050 60 0000 C CNN +F 3 "" H 9650 2050 60 0000 C CNN + 1 9650 2050 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U31 +U 1 1 685CC64C +P 10450 2900 +F 0 "U31" H 10450 2900 60 0000 C CNN +F 1 "dac_bridge_1" H 10450 3050 60 0000 C CNN +F 2 "" H 10450 2900 60 0000 C CNN +F 3 "" H 10450 2900 60 0000 C CNN + 1 10450 2900 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U33 +U 1 1 685CC84C +P 11000 3350 +F 0 "U33" H 11000 3350 60 0000 C CNN +F 1 "dac_bridge_1" H 11000 3500 60 0000 C CNN +F 2 "" H 11000 3350 60 0000 C CNN +F 3 "" H 11000 3350 60 0000 C CNN + 1 11000 3350 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U35 +U 1 1 685CC9DC +P 11150 3750 +F 0 "U35" H 11150 3750 60 0000 C CNN +F 1 "dac_bridge_1" H 11150 3900 60 0000 C CNN +F 2 "" H 11150 3750 60 0000 C CNN +F 3 "" H 11150 3750 60 0000 C CNN + 1 11150 3750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10200 2000 10250 2000 +Wire Wire Line + 10650 2400 10700 2400 +Wire Wire Line + 11050 2850 11000 2850 +Wire Wire Line + 11550 3300 11600 3300 +Wire Wire Line + 11700 3700 11750 3700 +$Comp +L dac_bridge_1 U27 +U 1 1 685CE492 +P 10000 5050 +F 0 "U27" H 10000 5050 60 0000 C CNN +F 1 "dac_bridge_1" H 10000 5200 60 0000 C CNN +F 2 "" H 10000 5050 60 0000 C CNN +F 3 "" H 10000 5050 60 0000 C CNN + 1 10000 5050 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U29 +U 1 1 685CE706 +P 10150 5450 +F 0 "U29" H 10150 5450 60 0000 C CNN +F 1 "dac_bridge_1" H 10150 5600 60 0000 C CNN +F 2 "" H 10150 5450 60 0000 C CNN +F 3 "" H 10150 5450 60 0000 C CNN + 1 10150 5450 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U30 +U 1 1 685CE7E5 +P 10350 5900 +F 0 "U30" H 10350 5900 60 0000 C CNN +F 1 "dac_bridge_1" H 10350 6050 60 0000 C CNN +F 2 "" H 10350 5900 60 0000 C CNN +F 3 "" H 10350 5900 60 0000 C CNN + 1 10350 5900 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U32 +U 1 1 685CE8CF +P 10900 6350 +F 0 "U32" H 10900 6350 60 0000 C CNN +F 1 "dac_bridge_1" H 10900 6500 60 0000 C CNN +F 2 "" H 10900 6350 60 0000 C CNN +F 3 "" H 10900 6350 60 0000 C CNN + 1 10900 6350 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U34 +U 1 1 685CE9BA +P 11050 6750 +F 0 "U34" H 11050 6750 60 0000 C CNN +F 1 "dac_bridge_1" H 11050 6900 60 0000 C CNN +F 2 "" H 11050 6750 60 0000 C CNN +F 3 "" H 11050 6750 60 0000 C CNN + 1 11050 6750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10550 5000 10650 5000 +Wire Wire Line + 10800 5400 10700 5400 +Wire Wire Line + 10900 5850 11000 5850 +Wire Wire Line + 11600 6300 11450 6300 +Wire Wire Line + 11600 6700 11750 6700 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3384A/SN74CBT3384A.sub b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3384A/SN74CBT3384A.sub new file mode 100644 index 000000000..197d5d0e9 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3384A/SN74CBT3384A.sub @@ -0,0 +1,153 @@ +* Subcircuit SN74CBT3384A +.subckt SN74CBT3384A net-_u1-pad1_ net-_u1-pad2_ net-_m1-pad1_ net-_m3-pad1_ net-_u1-pad5_ net-_u1-pad6_ net-_m5-pad1_ net-_m7-pad1_ net-_u1-pad9_ net-_u1-pad10_ net-_m9-pad1_ gnd net-_u1-pad13_ net-_m2-pad1_ net-_u1-pad15_ net-_u1-pad16_ net-_m4-pad1_ net-_m6-pad1_ net-_u1-pad19_ net-_u1-pad20_ net-_m8-pad1_ net-_m10-pad1_ net-_u1-pad23_ ? +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\sn74cbt3384a\sn74cbt3384a.cir +.include NMOS-180nm.lib +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1 +m3 net-_m3-pad1_ net-_m1-pad2_ net-_m3-pad3_ gnd CMOSN W=100u L=100u M=1 +m5 net-_m5-pad1_ net-_m1-pad2_ net-_m5-pad3_ gnd CMOSN W=100u L=100u M=1 +m7 net-_m7-pad1_ net-_m1-pad2_ net-_m7-pad3_ gnd CMOSN W=100u L=100u M=1 +m9 net-_m9-pad1_ net-_m1-pad2_ net-_m9-pad3_ gnd CMOSN W=100u L=100u M=1 +m2 net-_m2-pad1_ net-_m10-pad2_ net-_m2-pad3_ gnd CMOSN W=100u L=100u M=1 +m4 net-_m4-pad1_ net-_m10-pad2_ net-_m4-pad3_ gnd CMOSN W=100u L=100u M=1 +m6 net-_m6-pad1_ net-_m10-pad2_ net-_m6-pad3_ gnd CMOSN W=100u L=100u M=1 +m8 net-_m8-pad1_ net-_m10-pad2_ net-_m8-pad3_ gnd CMOSN W=100u L=100u M=1 +m10 net-_m10-pad1_ net-_m10-pad2_ net-_m10-pad3_ gnd CMOSN W=100u L=100u M=1 +* u4 net-_u2-pad2_ net-_m1-pad2_ dac_bridge_1 +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u5 net-_u3-pad2_ net-_m10-pad2_ dac_bridge_1 +* u3 net-_u1-pad13_ net-_u3-pad2_ d_inverter +* u12 net-_u12-pad1_ net-_u12-pad2_ d_buffer +* u18 net-_u18-pad1_ net-_u18-pad2_ d_buffer +* u20 net-_u10-pad2_ net-_u20-pad2_ d_buffer +* u22 net-_u13-pad2_ net-_u22-pad2_ d_buffer +* u24 net-_u15-pad2_ net-_u24-pad2_ d_buffer +* u17 net-_u17-pad1_ net-_u17-pad2_ d_buffer +* u19 net-_u19-pad1_ net-_u19-pad2_ d_buffer +* u21 net-_u11-pad2_ net-_u21-pad2_ d_buffer +* u23 net-_u14-pad2_ net-_u23-pad2_ d_buffer +* u25 net-_u16-pad2_ net-_u25-pad2_ d_buffer +* u6 net-_m1-pad3_ net-_u12-pad1_ adc_bridge_1 +* u8 net-_m3-pad3_ net-_u18-pad1_ adc_bridge_1 +* u10 net-_m5-pad3_ net-_u10-pad2_ adc_bridge_1 +* u13 net-_m7-pad3_ net-_u13-pad2_ adc_bridge_1 +* u15 net-_m9-pad3_ net-_u15-pad2_ adc_bridge_1 +* u7 net-_m2-pad3_ net-_u17-pad1_ adc_bridge_1 +* u9 net-_m4-pad3_ net-_u19-pad1_ adc_bridge_1 +* u11 net-_m6-pad3_ net-_u11-pad2_ adc_bridge_1 +* u14 net-_m8-pad3_ net-_u14-pad2_ adc_bridge_1 +* u16 net-_m10-pad3_ net-_u16-pad2_ adc_bridge_1 +* u28 net-_u18-pad2_ net-_u1-pad5_ dac_bridge_1 +* u26 net-_u12-pad2_ net-_u1-pad2_ dac_bridge_1 +* u31 net-_u20-pad2_ net-_u1-pad6_ dac_bridge_1 +* u33 net-_u22-pad2_ net-_u1-pad9_ dac_bridge_1 +* u35 net-_u24-pad2_ net-_u1-pad10_ dac_bridge_1 +* u27 net-_u17-pad2_ net-_u1-pad15_ dac_bridge_1 +* u29 net-_u19-pad2_ net-_u1-pad16_ dac_bridge_1 +* u30 net-_u21-pad2_ net-_u1-pad19_ dac_bridge_1 +* u32 net-_u23-pad2_ net-_u1-pad20_ dac_bridge_1 +* u34 net-_u25-pad2_ net-_u1-pad23_ dac_bridge_1 +a1 [net-_u2-pad2_ ] [net-_m1-pad2_ ] u4 +a2 net-_u1-pad1_ net-_u2-pad2_ u2 +a3 [net-_u3-pad2_ ] [net-_m10-pad2_ ] u5 +a4 net-_u1-pad13_ net-_u3-pad2_ u3 +a5 net-_u12-pad1_ net-_u12-pad2_ u12 +a6 net-_u18-pad1_ net-_u18-pad2_ u18 +a7 net-_u10-pad2_ net-_u20-pad2_ u20 +a8 net-_u13-pad2_ net-_u22-pad2_ u22 +a9 net-_u15-pad2_ net-_u24-pad2_ u24 +a10 net-_u17-pad1_ net-_u17-pad2_ u17 +a11 net-_u19-pad1_ net-_u19-pad2_ u19 +a12 net-_u11-pad2_ net-_u21-pad2_ u21 +a13 net-_u14-pad2_ net-_u23-pad2_ u23 +a14 net-_u16-pad2_ net-_u25-pad2_ u25 +a15 [net-_m1-pad3_ ] [net-_u12-pad1_ ] u6 +a16 [net-_m3-pad3_ ] [net-_u18-pad1_ ] u8 +a17 [net-_m5-pad3_ ] [net-_u10-pad2_ ] u10 +a18 [net-_m7-pad3_ ] [net-_u13-pad2_ ] u13 +a19 [net-_m9-pad3_ ] [net-_u15-pad2_ ] u15 +a20 [net-_m2-pad3_ ] [net-_u17-pad1_ ] u7 +a21 [net-_m4-pad3_ ] [net-_u19-pad1_ ] u9 +a22 [net-_m6-pad3_ ] [net-_u11-pad2_ ] u11 +a23 [net-_m8-pad3_ ] [net-_u14-pad2_ ] u14 +a24 [net-_m10-pad3_ ] [net-_u16-pad2_ ] u16 +a25 [net-_u18-pad2_ ] [net-_u1-pad5_ ] u28 +a26 [net-_u12-pad2_ ] [net-_u1-pad2_ ] u26 +a27 [net-_u20-pad2_ ] [net-_u1-pad6_ ] u31 +a28 [net-_u22-pad2_ ] [net-_u1-pad9_ ] u33 +a29 [net-_u24-pad2_ ] [net-_u1-pad10_ ] u35 +a30 [net-_u17-pad2_ ] [net-_u1-pad15_ ] u27 +a31 [net-_u19-pad2_ ] [net-_u1-pad16_ ] u29 +a32 [net-_u21-pad2_ ] [net-_u1-pad19_ ] u30 +a33 [net-_u23-pad2_ ] [net-_u1-pad20_ ] u32 +a34 [net-_u25-pad2_ ] [net-_u1-pad23_ ] u34 +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u4 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u5 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u12 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u18 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u20 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u22 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u24 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u17 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u19 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u21 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u23 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u25 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u6 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u8 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u10 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u13 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u15 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u7 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u9 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u11 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u14 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u16 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u28 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u26 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u31 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u33 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u35 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u27 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u29 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u30 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u32 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u34 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Control Statements + +.ends SN74CBT3384A \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3384A/SN74CBT3384A_Previous_Values.xml b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3384A/SN74CBT3384A_Previous_Values.xml new file mode 100644 index 000000000..35685d87a --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3384A/SN74CBT3384A_Previous_Values.xml @@ -0,0 +1 @@ +d_inverterd_inverterdac_bridgedac_bridgedac_bridged_bufferdac_bridged_bufferdac_bridged_bufferdac_bridged_bufferdac_bridged_bufferdac_bridged_bufferdac_bridged_bufferdac_bridged_bufferdac_bridged_bufferdac_bridged_bufferadc_bridgeadc_bridgeadc_bridgeadc_bridgeadc_bridgeadc_bridgeadc_bridgeadc_bridgeadc_bridgeadc_bridgedac_bridgedac_bridgedac_bridgedac_bridgedac_bridgedac_bridgedac_bridgedac_bridgedac_bridgedac_bridgeC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3384A/analysis b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3384A/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBT3384A/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3126/NMOS-180nm.lib b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3126/NMOS-180nm.lib new file mode 100644 index 000000000..51e9b1196 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3126/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3126/PMOS-180nm.lib b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3126/PMOS-180nm.lib new file mode 100644 index 000000000..032b5b95e --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3126/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3126/SN74CBTLV3126-cache.lib b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3126/SN74CBTLV3126-cache.lib new file mode 100644 index 000000000..1efb9919a --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3126/SN74CBTLV3126-cache.lib @@ -0,0 +1,156 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# adc_bridge_1 +# +DEF adc_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_buffer +# +DEF d_buffer U 0 40 Y Y 1 F N +F0 "U" 0 -50 60 H V C CNN +F1 "d_buffer" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N +X IN 1 -500 0 200 R 50 50 1 1 I +X OUT 2 650 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# dac_bridge_1 +# +DEF dac_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3126/SN74CBTLV3126.cir b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3126/SN74CBTLV3126.cir new file mode 100644 index 000000000..6d956c27d --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3126/SN74CBTLV3126.cir @@ -0,0 +1,43 @@ +* C:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\SN74CBTLV3126\SN74CBTLV3126.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/25/25 22:15:21 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ GND mosfet_n +M3 Net-_M1-Pad1_ Net-_M3-Pad2_ Net-_M1-Pad3_ VCC mosfet_p +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ d_inverter +U7 Net-_M1-Pad2_ Net-_U1-Pad1_ adc_bridge_1 +U3 Net-_U1-Pad2_ Net-_M3-Pad2_ dac_bridge_1 +U13 Net-_M1-Pad3_ Net-_U13-Pad2_ adc_bridge_1 +U17 Net-_U13-Pad2_ Net-_U17-Pad2_ d_buffer +U21 Net-_U17-Pad2_ Net-_U21-Pad2_ dac_bridge_1 +M4 Net-_M4-Pad1_ Net-_M4-Pad2_ Net-_M4-Pad3_ GND mosfet_n +M6 Net-_M4-Pad1_ Net-_M6-Pad2_ Net-_M4-Pad3_ VCC mosfet_p +U4 Net-_U11-Pad2_ Net-_U4-Pad2_ d_inverter +U11 Net-_M4-Pad2_ Net-_U11-Pad2_ adc_bridge_1 +U8 Net-_U4-Pad2_ Net-_M6-Pad2_ dac_bridge_1 +U15 Net-_M4-Pad3_ Net-_U15-Pad2_ adc_bridge_1 +U19 Net-_U15-Pad2_ Net-_U19-Pad2_ d_buffer +U23 Net-_U19-Pad2_ Net-_U23-Pad2_ dac_bridge_1 +M7 Net-_M7-Pad1_ Net-_M7-Pad2_ Net-_M7-Pad3_ GND mosfet_n +M8 Net-_M7-Pad1_ Net-_M8-Pad2_ Net-_M7-Pad3_ VCC mosfet_p +U6 Net-_U12-Pad2_ Net-_U10-Pad1_ d_inverter +U12 Net-_M7-Pad2_ Net-_U12-Pad2_ adc_bridge_1 +U10 Net-_U10-Pad1_ Net-_M8-Pad2_ dac_bridge_1 +U16 Net-_M7-Pad3_ Net-_U16-Pad2_ adc_bridge_1 +U20 Net-_U16-Pad2_ Net-_U20-Pad2_ d_buffer +U24 Net-_U20-Pad2_ Net-_U24-Pad2_ dac_bridge_1 +M2 Net-_M2-Pad1_ Net-_M2-Pad2_ Net-_M2-Pad3_ GND mosfet_n +M5 Net-_M2-Pad1_ Net-_M5-Pad2_ Net-_M2-Pad3_ VCC mosfet_p +U2 Net-_U2-Pad1_ Net-_U2-Pad2_ d_inverter +U9 Net-_M2-Pad2_ Net-_U2-Pad1_ adc_bridge_1 +U5 Net-_U2-Pad2_ Net-_M5-Pad2_ dac_bridge_1 +U14 Net-_M2-Pad3_ Net-_U14-Pad2_ adc_bridge_1 +U18 Net-_U14-Pad2_ Net-_U18-Pad2_ d_buffer +U22 Net-_U18-Pad2_ Net-_U22-Pad2_ dac_bridge_1 +U25 Net-_M1-Pad2_ Net-_M1-Pad1_ Net-_U21-Pad2_ Net-_M4-Pad2_ Net-_M4-Pad1_ Net-_U23-Pad2_ GND Net-_U24-Pad2_ Net-_M7-Pad1_ Net-_M7-Pad2_ Net-_U22-Pad2_ Net-_M2-Pad1_ Net-_M2-Pad2_ VCC PORT + +.end diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3126/SN74CBTLV3126.cir.out b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3126/SN74CBTLV3126.cir.out new file mode 100644 index 000000000..a8f306ccd --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3126/SN74CBTLV3126.cir.out @@ -0,0 +1,118 @@ +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\sn74cbtlv3126\sn74cbtlv3126.cir + +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1 +m3 net-_m1-pad1_ net-_m3-pad2_ net-_m1-pad3_ vcc CMOSP W=100u L=100u M=1 +* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter +* u7 net-_m1-pad2_ net-_u1-pad1_ adc_bridge_1 +* u3 net-_u1-pad2_ net-_m3-pad2_ dac_bridge_1 +* u13 net-_m1-pad3_ net-_u13-pad2_ adc_bridge_1 +* u17 net-_u13-pad2_ net-_u17-pad2_ d_buffer +* u21 net-_u17-pad2_ net-_u21-pad2_ dac_bridge_1 +m4 net-_m4-pad1_ net-_m4-pad2_ net-_m4-pad3_ gnd CMOSN W=100u L=100u M=1 +m6 net-_m4-pad1_ net-_m6-pad2_ net-_m4-pad3_ vcc CMOSP W=100u L=100u M=1 +* u4 net-_u11-pad2_ net-_u4-pad2_ d_inverter +* u11 net-_m4-pad2_ net-_u11-pad2_ adc_bridge_1 +* u8 net-_u4-pad2_ net-_m6-pad2_ dac_bridge_1 +* u15 net-_m4-pad3_ net-_u15-pad2_ adc_bridge_1 +* u19 net-_u15-pad2_ net-_u19-pad2_ d_buffer +* u23 net-_u19-pad2_ net-_u23-pad2_ dac_bridge_1 +m7 net-_m7-pad1_ net-_m7-pad2_ net-_m7-pad3_ gnd CMOSN W=100u L=100u M=1 +m8 net-_m7-pad1_ net-_m8-pad2_ net-_m7-pad3_ vcc CMOSP W=100u L=100u M=1 +* u6 net-_u12-pad2_ net-_u10-pad1_ d_inverter +* u12 net-_m7-pad2_ net-_u12-pad2_ adc_bridge_1 +* u10 net-_u10-pad1_ net-_m8-pad2_ dac_bridge_1 +* u16 net-_m7-pad3_ net-_u16-pad2_ adc_bridge_1 +* u20 net-_u16-pad2_ net-_u20-pad2_ d_buffer +* u24 net-_u20-pad2_ net-_u24-pad2_ dac_bridge_1 +m2 net-_m2-pad1_ net-_m2-pad2_ net-_m2-pad3_ gnd CMOSN W=100u L=100u M=1 +m5 net-_m2-pad1_ net-_m5-pad2_ net-_m2-pad3_ vcc CMOSP W=100u L=100u M=1 +* u2 net-_u2-pad1_ net-_u2-pad2_ d_inverter +* u9 net-_m2-pad2_ net-_u2-pad1_ adc_bridge_1 +* u5 net-_u2-pad2_ net-_m5-pad2_ dac_bridge_1 +* u14 net-_m2-pad3_ net-_u14-pad2_ adc_bridge_1 +* u18 net-_u14-pad2_ net-_u18-pad2_ d_buffer +* u22 net-_u18-pad2_ net-_u22-pad2_ dac_bridge_1 +* u25 net-_m1-pad2_ net-_m1-pad1_ net-_u21-pad2_ net-_m4-pad2_ net-_m4-pad1_ net-_u23-pad2_ gnd net-_u24-pad2_ net-_m7-pad1_ net-_m7-pad2_ net-_u22-pad2_ net-_m2-pad1_ net-_m2-pad2_ vcc port +a1 net-_u1-pad1_ net-_u1-pad2_ u1 +a2 [net-_m1-pad2_ ] [net-_u1-pad1_ ] u7 +a3 [net-_u1-pad2_ ] [net-_m3-pad2_ ] u3 +a4 [net-_m1-pad3_ ] [net-_u13-pad2_ ] u13 +a5 net-_u13-pad2_ net-_u17-pad2_ u17 +a6 [net-_u17-pad2_ ] [net-_u21-pad2_ ] u21 +a7 net-_u11-pad2_ net-_u4-pad2_ u4 +a8 [net-_m4-pad2_ ] [net-_u11-pad2_ ] u11 +a9 [net-_u4-pad2_ ] [net-_m6-pad2_ ] u8 +a10 [net-_m4-pad3_ ] [net-_u15-pad2_ ] u15 +a11 net-_u15-pad2_ net-_u19-pad2_ u19 +a12 [net-_u19-pad2_ ] [net-_u23-pad2_ ] u23 +a13 net-_u12-pad2_ net-_u10-pad1_ u6 +a14 [net-_m7-pad2_ ] [net-_u12-pad2_ ] u12 +a15 [net-_u10-pad1_ ] [net-_m8-pad2_ ] u10 +a16 [net-_m7-pad3_ ] [net-_u16-pad2_ ] u16 +a17 net-_u16-pad2_ net-_u20-pad2_ u20 +a18 [net-_u20-pad2_ ] [net-_u24-pad2_ ] u24 +a19 net-_u2-pad1_ net-_u2-pad2_ u2 +a20 [net-_m2-pad2_ ] [net-_u2-pad1_ ] u9 +a21 [net-_u2-pad2_ ] [net-_m5-pad2_ ] u5 +a22 [net-_m2-pad3_ ] [net-_u14-pad2_ ] u14 +a23 net-_u14-pad2_ net-_u18-pad2_ u18 +a24 [net-_u18-pad2_ ] [net-_u22-pad2_ ] u22 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u7 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u3 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u13 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u17 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u21 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u11 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u8 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u15 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u19 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u23 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u12 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u10 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u16 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u20 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u24 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u9 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u5 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u14 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u18 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u22 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3126/SN74CBTLV3126.pro b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3126/SN74CBTLV3126.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3126/SN74CBTLV3126.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3126/SN74CBTLV3126.sch b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3126/SN74CBTLV3126.sch new file mode 100644 index 000000000..b5e00ee72 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3126/SN74CBTLV3126.sch @@ -0,0 +1,775 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN74CBTLV3126-cache +EELAYER 25 0 +EELAYER END +$Descr A2 23386 16535 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L mosfet_n M1 +U 1 1 685C2315 +P 9400 3600 +F 0 "M1" H 9400 3450 50 0000 R CNN +F 1 "mosfet_n" H 9500 3550 50 0000 R CNN +F 2 "" H 9700 3300 29 0000 C CNN +F 3 "" H 9500 3400 60 0000 C CNN + 1 9400 3600 + 0 -1 -1 0 +$EndComp +$Comp +L mosfet_p M3 +U 1 1 685C2394 +P 9600 2850 +F 0 "M3" H 9550 2900 50 0000 R CNN +F 1 "mosfet_p" H 9650 3000 50 0000 R CNN +F 2 "" H 9850 2950 29 0000 C CNN +F 3 "" H 9650 2850 60 0000 C CNN + 1 9600 2850 + 0 -1 1 0 +$EndComp +Wire Wire Line + 9400 3000 9350 3000 +Wire Wire Line + 9350 3000 9350 3400 +Wire Wire Line + 9350 3400 9400 3400 +Wire Wire Line + 9800 3000 9900 3000 +Wire Wire Line + 9900 3000 9900 3400 +Wire Wire Line + 9900 3400 9800 3400 +Text GLabel 6650 700 0 60 Input ~ 0 +VCC +Text GLabel 6650 900 0 60 Input ~ 0 +GND +Text GLabel 9950 3100 2 60 Input ~ 0 +VCC +Text GLabel 9950 3300 2 60 Input ~ 0 +GND +Wire Wire Line + 9750 3100 9950 3100 +Wire Wire Line + 9950 3300 9750 3300 +$Comp +L d_inverter U1 +U 1 1 685C252A +P 8800 3350 +F 0 "U1" H 8800 3250 60 0000 C CNN +F 1 "d_inverter" H 8800 3500 60 0000 C CNN +F 2 "" H 8850 3300 60 0000 C CNN +F 3 "" H 8850 3300 60 0000 C CNN + 1 8800 3350 + 0 -1 -1 0 +$EndComp +$Comp +L adc_bridge_1 U7 +U 1 1 685C258B +P 9350 4000 +F 0 "U7" H 9350 4000 60 0000 C CNN +F 1 "adc_bridge_1" H 9350 4150 60 0000 C CNN +F 2 "" H 9350 4000 60 0000 C CNN +F 3 "" H 9350 4000 60 0000 C CNN + 1 9350 4000 + -1 0 0 1 +$EndComp +$Comp +L dac_bridge_1 U3 +U 1 1 685C25DE +P 9050 2500 +F 0 "U3" H 9050 2500 60 0000 C CNN +F 1 "dac_bridge_1" H 9050 2650 60 0000 C CNN +F 2 "" H 9050 2500 60 0000 C CNN +F 3 "" H 9050 2500 60 0000 C CNN + 1 9050 2500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8450 2450 8400 2450 +Wire Wire Line + 8400 2450 8400 3050 +Wire Wire Line + 8400 3050 8800 3050 +Wire Wire Line + 9600 2450 9600 2700 +Wire Wire Line + 9600 3700 9600 3800 +Wire Wire Line + 9600 3800 10000 3800 +Wire Wire Line + 10000 3800 10000 4350 +$Comp +L adc_bridge_1 U13 +U 1 1 685C26D0 +P 10800 3150 +F 0 "U13" H 10800 3150 60 0000 C CNN +F 1 "adc_bridge_1" H 10800 3300 60 0000 C CNN +F 2 "" H 10800 3150 60 0000 C CNN +F 3 "" H 10800 3150 60 0000 C CNN + 1 10800 3150 + 1 0 0 1 +$EndComp +$Comp +L d_buffer U17 +U 1 1 685C274A +P 11950 3200 +F 0 "U17" H 11950 3150 60 0000 C CNN +F 1 "d_buffer" H 11950 3250 60 0000 C CNN +F 2 "" H 11950 3200 60 0000 C CNN +F 3 "" H 11950 3200 60 0000 C CNN + 1 11950 3200 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U21 +U 1 1 685C277E +P 13250 3250 +F 0 "U21" H 13250 3250 60 0000 C CNN +F 1 "dac_bridge_1" H 13250 3400 60 0000 C CNN +F 2 "" H 13250 3250 60 0000 C CNN +F 3 "" H 13250 3250 60 0000 C CNN + 1 13250 3250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 11350 3200 11450 3200 +Wire Wire Line + 12600 3200 12650 3200 +Wire Wire Line + 13800 3200 13900 3200 +Wire Wire Line + 10200 3200 9900 3200 +Connection ~ 9900 3200 +Wire Wire Line + 9350 3200 9250 3200 +Connection ~ 9350 3200 +Connection ~ 10000 4050 +Wire Wire Line + 9950 4050 10000 4050 +Wire Wire Line + 8800 3650 8800 4050 +$Comp +L mosfet_n M4 +U 1 1 685C2DE3 +P 9700 6000 +F 0 "M4" H 9700 5850 50 0000 R CNN +F 1 "mosfet_n" H 9800 5950 50 0000 R CNN +F 2 "" H 10000 5700 29 0000 C CNN +F 3 "" H 9800 5800 60 0000 C CNN + 1 9700 6000 + 0 -1 -1 0 +$EndComp +$Comp +L mosfet_p M6 +U 1 1 685C2DE9 +P 9900 5250 +F 0 "M6" H 9850 5300 50 0000 R CNN +F 1 "mosfet_p" H 9950 5400 50 0000 R CNN +F 2 "" H 10150 5350 29 0000 C CNN +F 3 "" H 9950 5250 60 0000 C CNN + 1 9900 5250 + 0 -1 1 0 +$EndComp +Wire Wire Line + 9700 5400 9650 5400 +Wire Wire Line + 9650 5400 9650 5800 +Wire Wire Line + 9650 5800 9700 5800 +Wire Wire Line + 10100 5400 10200 5400 +Wire Wire Line + 10200 5400 10200 5800 +Wire Wire Line + 10200 5800 10100 5800 +Text GLabel 10250 5500 2 60 Input ~ 0 +VCC +Text GLabel 10250 5700 2 60 Input ~ 0 +GND +Wire Wire Line + 10050 5500 10250 5500 +Wire Wire Line + 10250 5700 10050 5700 +$Comp +L d_inverter U4 +U 1 1 685C2DF9 +P 9100 5750 +F 0 "U4" H 9100 5650 60 0000 C CNN +F 1 "d_inverter" H 9100 5900 60 0000 C CNN +F 2 "" H 9150 5700 60 0000 C CNN +F 3 "" H 9150 5700 60 0000 C CNN + 1 9100 5750 + 0 -1 -1 0 +$EndComp +$Comp +L adc_bridge_1 U11 +U 1 1 685C2DFF +P 9650 6400 +F 0 "U11" H 9650 6400 60 0000 C CNN +F 1 "adc_bridge_1" H 9650 6550 60 0000 C CNN +F 2 "" H 9650 6400 60 0000 C CNN +F 3 "" H 9650 6400 60 0000 C CNN + 1 9650 6400 + -1 0 0 1 +$EndComp +$Comp +L dac_bridge_1 U8 +U 1 1 685C2E05 +P 9350 4900 +F 0 "U8" H 9350 4900 60 0000 C CNN +F 1 "dac_bridge_1" H 9350 5050 60 0000 C CNN +F 2 "" H 9350 4900 60 0000 C CNN +F 3 "" H 9350 4900 60 0000 C CNN + 1 9350 4900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8750 4850 8700 4850 +Wire Wire Line + 8700 4850 8700 5450 +Wire Wire Line + 8700 5450 9100 5450 +Wire Wire Line + 9900 4850 9900 5100 +Wire Wire Line + 9900 6100 9900 6200 +Wire Wire Line + 9900 6200 10300 6200 +Wire Wire Line + 10300 6200 10300 6750 +$Comp +L adc_bridge_1 U15 +U 1 1 685C2E12 +P 11100 5550 +F 0 "U15" H 11100 5550 60 0000 C CNN +F 1 "adc_bridge_1" H 11100 5700 60 0000 C CNN +F 2 "" H 11100 5550 60 0000 C CNN +F 3 "" H 11100 5550 60 0000 C CNN + 1 11100 5550 + 1 0 0 1 +$EndComp +$Comp +L d_buffer U19 +U 1 1 685C2E18 +P 12250 5600 +F 0 "U19" H 12250 5550 60 0000 C CNN +F 1 "d_buffer" H 12250 5650 60 0000 C CNN +F 2 "" H 12250 5600 60 0000 C CNN +F 3 "" H 12250 5600 60 0000 C CNN + 1 12250 5600 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U23 +U 1 1 685C2E1E +P 13550 5650 +F 0 "U23" H 13550 5650 60 0000 C CNN +F 1 "dac_bridge_1" H 13550 5800 60 0000 C CNN +F 2 "" H 13550 5650 60 0000 C CNN +F 3 "" H 13550 5650 60 0000 C CNN + 1 13550 5650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 11650 5600 11750 5600 +Wire Wire Line + 12900 5600 12950 5600 +Wire Wire Line + 14100 5600 14200 5600 +Wire Wire Line + 10500 5600 10200 5600 +Connection ~ 10200 5600 +Wire Wire Line + 9650 5600 9550 5600 +Connection ~ 9650 5600 +Connection ~ 10300 6450 +Wire Wire Line + 10250 6450 10300 6450 +Wire Wire Line + 9100 6050 9100 6450 +$Comp +L mosfet_n M7 +U 1 1 685C2FB6 +P 9900 8350 +F 0 "M7" H 9900 8200 50 0000 R CNN +F 1 "mosfet_n" H 10000 8300 50 0000 R CNN +F 2 "" H 10200 8050 29 0000 C CNN +F 3 "" H 10000 8150 60 0000 C CNN + 1 9900 8350 + 0 -1 -1 0 +$EndComp +$Comp +L mosfet_p M8 +U 1 1 685C2FBC +P 10100 7600 +F 0 "M8" H 10050 7650 50 0000 R CNN +F 1 "mosfet_p" H 10150 7750 50 0000 R CNN +F 2 "" H 10350 7700 29 0000 C CNN +F 3 "" H 10150 7600 60 0000 C CNN + 1 10100 7600 + 0 -1 1 0 +$EndComp +Wire Wire Line + 9900 7750 9850 7750 +Wire Wire Line + 9850 7750 9850 8150 +Wire Wire Line + 9850 8150 9900 8150 +Wire Wire Line + 10300 7750 10400 7750 +Wire Wire Line + 10400 7750 10400 8150 +Wire Wire Line + 10400 8150 10300 8150 +Text GLabel 10450 7850 2 60 Input ~ 0 +VCC +Text GLabel 10450 8050 2 60 Input ~ 0 +GND +Wire Wire Line + 10250 7850 10450 7850 +Wire Wire Line + 10450 8050 10250 8050 +$Comp +L d_inverter U6 +U 1 1 685C2FCC +P 9300 8100 +F 0 "U6" H 9300 8000 60 0000 C CNN +F 1 "d_inverter" H 9300 8250 60 0000 C CNN +F 2 "" H 9350 8050 60 0000 C CNN +F 3 "" H 9350 8050 60 0000 C CNN + 1 9300 8100 + 0 -1 -1 0 +$EndComp +$Comp +L adc_bridge_1 U12 +U 1 1 685C2FD2 +P 9850 8750 +F 0 "U12" H 9850 8750 60 0000 C CNN +F 1 "adc_bridge_1" H 9850 8900 60 0000 C CNN +F 2 "" H 9850 8750 60 0000 C CNN +F 3 "" H 9850 8750 60 0000 C CNN + 1 9850 8750 + -1 0 0 1 +$EndComp +$Comp +L dac_bridge_1 U10 +U 1 1 685C2FD8 +P 9550 7250 +F 0 "U10" H 9550 7250 60 0000 C CNN +F 1 "dac_bridge_1" H 9550 7400 60 0000 C CNN +F 2 "" H 9550 7250 60 0000 C CNN +F 3 "" H 9550 7250 60 0000 C CNN + 1 9550 7250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8950 7200 8900 7200 +Wire Wire Line + 8900 7200 8900 7800 +Wire Wire Line + 8900 7800 9300 7800 +Wire Wire Line + 10100 7200 10100 7450 +Wire Wire Line + 10100 8450 10100 8550 +Wire Wire Line + 10100 8550 10500 8550 +Wire Wire Line + 10500 8550 10500 9100 +$Comp +L adc_bridge_1 U16 +U 1 1 685C2FE5 +P 11300 7900 +F 0 "U16" H 11300 7900 60 0000 C CNN +F 1 "adc_bridge_1" H 11300 8050 60 0000 C CNN +F 2 "" H 11300 7900 60 0000 C CNN +F 3 "" H 11300 7900 60 0000 C CNN + 1 11300 7900 + 1 0 0 1 +$EndComp +$Comp +L d_buffer U20 +U 1 1 685C2FEB +P 12450 7950 +F 0 "U20" H 12450 7900 60 0000 C CNN +F 1 "d_buffer" H 12450 8000 60 0000 C CNN +F 2 "" H 12450 7950 60 0000 C CNN +F 3 "" H 12450 7950 60 0000 C CNN + 1 12450 7950 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U24 +U 1 1 685C2FF1 +P 13750 8000 +F 0 "U24" H 13750 8000 60 0000 C CNN +F 1 "dac_bridge_1" H 13750 8150 60 0000 C CNN +F 2 "" H 13750 8000 60 0000 C CNN +F 3 "" H 13750 8000 60 0000 C CNN + 1 13750 8000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 11850 7950 11950 7950 +Wire Wire Line + 13100 7950 13150 7950 +Wire Wire Line + 14300 7950 14400 7950 +Wire Wire Line + 10700 7950 10400 7950 +Connection ~ 10400 7950 +Wire Wire Line + 9850 7950 9750 7950 +Connection ~ 9850 7950 +Connection ~ 10500 8800 +Wire Wire Line + 10450 8800 10500 8800 +Wire Wire Line + 9300 8400 9300 8800 +$Comp +L mosfet_n M2 +U 1 1 685C31C1 +P 9500 10600 +F 0 "M2" H 9500 10450 50 0000 R CNN +F 1 "mosfet_n" H 9600 10550 50 0000 R CNN +F 2 "" H 9800 10300 29 0000 C CNN +F 3 "" H 9600 10400 60 0000 C CNN + 1 9500 10600 + 0 -1 -1 0 +$EndComp +$Comp +L mosfet_p M5 +U 1 1 685C31C7 +P 9700 9850 +F 0 "M5" H 9650 9900 50 0000 R CNN +F 1 "mosfet_p" H 9750 10000 50 0000 R CNN +F 2 "" H 9950 9950 29 0000 C CNN +F 3 "" H 9750 9850 60 0000 C CNN + 1 9700 9850 + 0 -1 1 0 +$EndComp +Wire Wire Line + 9500 10000 9450 10000 +Wire Wire Line + 9450 10000 9450 10400 +Wire Wire Line + 9450 10400 9500 10400 +Wire Wire Line + 9900 10000 10000 10000 +Wire Wire Line + 10000 10000 10000 10400 +Wire Wire Line + 10000 10400 9900 10400 +Text GLabel 10050 10100 2 60 Input ~ 0 +VCC +Text GLabel 10050 10300 2 60 Input ~ 0 +GND +Wire Wire Line + 9850 10100 10050 10100 +Wire Wire Line + 10050 10300 9850 10300 +$Comp +L d_inverter U2 +U 1 1 685C31D7 +P 8900 10350 +F 0 "U2" H 8900 10250 60 0000 C CNN +F 1 "d_inverter" H 8900 10500 60 0000 C CNN +F 2 "" H 8950 10300 60 0000 C CNN +F 3 "" H 8950 10300 60 0000 C CNN + 1 8900 10350 + 0 -1 -1 0 +$EndComp +$Comp +L adc_bridge_1 U9 +U 1 1 685C31DD +P 9450 11000 +F 0 "U9" H 9450 11000 60 0000 C CNN +F 1 "adc_bridge_1" H 9450 11150 60 0000 C CNN +F 2 "" H 9450 11000 60 0000 C CNN +F 3 "" H 9450 11000 60 0000 C CNN + 1 9450 11000 + -1 0 0 1 +$EndComp +$Comp +L dac_bridge_1 U5 +U 1 1 685C31E3 +P 9150 9500 +F 0 "U5" H 9150 9500 60 0000 C CNN +F 1 "dac_bridge_1" H 9150 9650 60 0000 C CNN +F 2 "" H 9150 9500 60 0000 C CNN +F 3 "" H 9150 9500 60 0000 C CNN + 1 9150 9500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8550 9450 8500 9450 +Wire Wire Line + 8500 9450 8500 10050 +Wire Wire Line + 8500 10050 8900 10050 +Wire Wire Line + 9700 9450 9700 9700 +Wire Wire Line + 9700 10700 9700 10800 +Wire Wire Line + 9700 10800 10100 10800 +Wire Wire Line + 10100 10800 10100 11350 +$Comp +L adc_bridge_1 U14 +U 1 1 685C31F0 +P 10900 10150 +F 0 "U14" H 10900 10150 60 0000 C CNN +F 1 "adc_bridge_1" H 10900 10300 60 0000 C CNN +F 2 "" H 10900 10150 60 0000 C CNN +F 3 "" H 10900 10150 60 0000 C CNN + 1 10900 10150 + 1 0 0 1 +$EndComp +$Comp +L d_buffer U18 +U 1 1 685C31F6 +P 12050 10200 +F 0 "U18" H 12050 10150 60 0000 C CNN +F 1 "d_buffer" H 12050 10250 60 0000 C CNN +F 2 "" H 12050 10200 60 0000 C CNN +F 3 "" H 12050 10200 60 0000 C CNN + 1 12050 10200 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U22 +U 1 1 685C31FC +P 13350 10250 +F 0 "U22" H 13350 10250 60 0000 C CNN +F 1 "dac_bridge_1" H 13350 10400 60 0000 C CNN +F 2 "" H 13350 10250 60 0000 C CNN +F 3 "" H 13350 10250 60 0000 C CNN + 1 13350 10250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 11450 10200 11550 10200 +Wire Wire Line + 12700 10200 12750 10200 +Wire Wire Line + 10300 10200 10000 10200 +Connection ~ 10000 10200 +Wire Wire Line + 9450 10200 9350 10200 +Connection ~ 9450 10200 +Connection ~ 10100 11050 +Wire Wire Line + 10050 11050 10100 11050 +Wire Wire Line + 8900 10650 8900 11050 +$Comp +L PORT U25 +U 1 1 685C32CF +P 10000 4600 +F 0 "U25" H 10050 4700 30 0000 C CNN +F 1 "PORT" H 10000 4600 30 0000 C CNN +F 2 "" H 10000 4600 60 0000 C CNN +F 3 "" H 10000 4600 60 0000 C CNN + 1 10000 4600 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U25 +U 2 1 685C3401 +P 9000 3200 +F 0 "U25" H 9050 3300 30 0000 C CNN +F 1 "PORT" H 9000 3200 30 0000 C CNN +F 2 "" H 9000 3200 60 0000 C CNN +F 3 "" H 9000 3200 60 0000 C CNN + 2 9000 3200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U25 +U 3 1 685C3472 +P 14150 3200 +F 0 "U25" H 14200 3300 30 0000 C CNN +F 1 "PORT" H 14150 3200 30 0000 C CNN +F 2 "" H 14150 3200 60 0000 C CNN +F 3 "" H 14150 3200 60 0000 C CNN + 3 14150 3200 + -1 0 0 1 +$EndComp +$Comp +L PORT U25 +U 4 1 685C34E9 +P 10300 7000 +F 0 "U25" H 10350 7100 30 0000 C CNN +F 1 "PORT" H 10300 7000 30 0000 C CNN +F 2 "" H 10300 7000 60 0000 C CNN +F 3 "" H 10300 7000 60 0000 C CNN + 4 10300 7000 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U25 +U 5 1 685C3564 +P 9300 5600 +F 0 "U25" H 9350 5700 30 0000 C CNN +F 1 "PORT" H 9300 5600 30 0000 C CNN +F 2 "" H 9300 5600 60 0000 C CNN +F 3 "" H 9300 5600 60 0000 C CNN + 5 9300 5600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U25 +U 6 1 685C36A2 +P 14450 5600 +F 0 "U25" H 14500 5700 30 0000 C CNN +F 1 "PORT" H 14450 5600 30 0000 C CNN +F 2 "" H 14450 5600 60 0000 C CNN +F 3 "" H 14450 5600 60 0000 C CNN + 6 14450 5600 + -1 0 0 1 +$EndComp +$Comp +L PORT U25 +U 7 1 685C3707 +P 7050 900 +F 0 "U25" H 7100 1000 30 0000 C CNN +F 1 "PORT" H 7050 900 30 0000 C CNN +F 2 "" H 7050 900 60 0000 C CNN +F 3 "" H 7050 900 60 0000 C CNN + 7 7050 900 + -1 0 0 1 +$EndComp +$Comp +L PORT U25 +U 8 1 685C3917 +P 14650 7950 +F 0 "U25" H 14700 8050 30 0000 C CNN +F 1 "PORT" H 14650 7950 30 0000 C CNN +F 2 "" H 14650 7950 60 0000 C CNN +F 3 "" H 14650 7950 60 0000 C CNN + 8 14650 7950 + -1 0 0 1 +$EndComp +$Comp +L PORT U25 +U 9 1 685C3A66 +P 9500 7950 +F 0 "U25" H 9550 8050 30 0000 C CNN +F 1 "PORT" H 9500 7950 30 0000 C CNN +F 2 "" H 9500 7950 60 0000 C CNN +F 3 "" H 9500 7950 60 0000 C CNN + 9 9500 7950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U25 +U 10 1 685C3B29 +P 10500 9350 +F 0 "U25" H 10550 9450 30 0000 C CNN +F 1 "PORT" H 10500 9350 30 0000 C CNN +F 2 "" H 10500 9350 60 0000 C CNN +F 3 "" H 10500 9350 60 0000 C CNN + 10 10500 9350 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U25 +U 11 1 685C3C66 +P 14250 10200 +F 0 "U25" H 14300 10300 30 0000 C CNN +F 1 "PORT" H 14250 10200 30 0000 C CNN +F 2 "" H 14250 10200 60 0000 C CNN +F 3 "" H 14250 10200 60 0000 C CNN + 11 14250 10200 + -1 0 0 1 +$EndComp +$Comp +L PORT U25 +U 12 1 685C3E2F +P 9100 10200 +F 0 "U25" H 9150 10300 30 0000 C CNN +F 1 "PORT" H 9100 10200 30 0000 C CNN +F 2 "" H 9100 10200 60 0000 C CNN +F 3 "" H 9100 10200 60 0000 C CNN + 12 9100 10200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U25 +U 13 1 685C3EA8 +P 10100 11600 +F 0 "U25" H 10150 11700 30 0000 C CNN +F 1 "PORT" H 10100 11600 30 0000 C CNN +F 2 "" H 10100 11600 60 0000 C CNN +F 3 "" H 10100 11600 60 0000 C CNN + 13 10100 11600 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U25 +U 14 1 685C3F1F +P 7050 700 +F 0 "U25" H 7100 800 30 0000 C CNN +F 1 "PORT" H 7050 700 30 0000 C CNN +F 2 "" H 7050 700 60 0000 C CNN +F 3 "" H 7050 700 60 0000 C CNN + 14 7050 700 + -1 0 0 1 +$EndComp +Wire Wire Line + 6650 700 6800 700 +Wire Wire Line + 6800 900 6650 900 +Wire Wire Line + 13900 10200 14000 10200 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3126/SN74CBTLV3126.sub b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3126/SN74CBTLV3126.sub new file mode 100644 index 000000000..d0d0d3bd0 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3126/SN74CBTLV3126.sub @@ -0,0 +1,112 @@ +* Subcircuit SN74CBTLV3126 +.subckt SN74CBTLV3126 net-_m1-pad2_ net-_m1-pad1_ net-_u21-pad2_ net-_m4-pad2_ net-_m4-pad1_ net-_u23-pad2_ gnd net-_u24-pad2_ net-_m7-pad1_ net-_m7-pad2_ net-_u22-pad2_ net-_m2-pad1_ net-_m2-pad2_ vcc +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\sn74cbtlv3126\sn74cbtlv3126.cir +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1 +m3 net-_m1-pad1_ net-_m3-pad2_ net-_m1-pad3_ vcc CMOSP W=100u L=100u M=1 +* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter +* u7 net-_m1-pad2_ net-_u1-pad1_ adc_bridge_1 +* u3 net-_u1-pad2_ net-_m3-pad2_ dac_bridge_1 +* u13 net-_m1-pad3_ net-_u13-pad2_ adc_bridge_1 +* u17 net-_u13-pad2_ net-_u17-pad2_ d_buffer +* u21 net-_u17-pad2_ net-_u21-pad2_ dac_bridge_1 +m4 net-_m4-pad1_ net-_m4-pad2_ net-_m4-pad3_ gnd CMOSN W=100u L=100u M=1 +m6 net-_m4-pad1_ net-_m6-pad2_ net-_m4-pad3_ vcc CMOSP W=100u L=100u M=1 +* u4 net-_u11-pad2_ net-_u4-pad2_ d_inverter +* u11 net-_m4-pad2_ net-_u11-pad2_ adc_bridge_1 +* u8 net-_u4-pad2_ net-_m6-pad2_ dac_bridge_1 +* u15 net-_m4-pad3_ net-_u15-pad2_ adc_bridge_1 +* u19 net-_u15-pad2_ net-_u19-pad2_ d_buffer +* u23 net-_u19-pad2_ net-_u23-pad2_ dac_bridge_1 +m7 net-_m7-pad1_ net-_m7-pad2_ net-_m7-pad3_ gnd CMOSN W=100u L=100u M=1 +m8 net-_m7-pad1_ net-_m8-pad2_ net-_m7-pad3_ vcc CMOSP W=100u L=100u M=1 +* u6 net-_u12-pad2_ net-_u10-pad1_ d_inverter +* u12 net-_m7-pad2_ net-_u12-pad2_ adc_bridge_1 +* u10 net-_u10-pad1_ net-_m8-pad2_ dac_bridge_1 +* u16 net-_m7-pad3_ net-_u16-pad2_ adc_bridge_1 +* u20 net-_u16-pad2_ net-_u20-pad2_ d_buffer +* u24 net-_u20-pad2_ net-_u24-pad2_ dac_bridge_1 +m2 net-_m2-pad1_ net-_m2-pad2_ net-_m2-pad3_ gnd CMOSN W=100u L=100u M=1 +m5 net-_m2-pad1_ net-_m5-pad2_ net-_m2-pad3_ vcc CMOSP W=100u L=100u M=1 +* u2 net-_u2-pad1_ net-_u2-pad2_ d_inverter +* u9 net-_m2-pad2_ net-_u2-pad1_ adc_bridge_1 +* u5 net-_u2-pad2_ net-_m5-pad2_ dac_bridge_1 +* u14 net-_m2-pad3_ net-_u14-pad2_ adc_bridge_1 +* u18 net-_u14-pad2_ net-_u18-pad2_ d_buffer +* u22 net-_u18-pad2_ net-_u22-pad2_ dac_bridge_1 +a1 net-_u1-pad1_ net-_u1-pad2_ u1 +a2 [net-_m1-pad2_ ] [net-_u1-pad1_ ] u7 +a3 [net-_u1-pad2_ ] [net-_m3-pad2_ ] u3 +a4 [net-_m1-pad3_ ] [net-_u13-pad2_ ] u13 +a5 net-_u13-pad2_ net-_u17-pad2_ u17 +a6 [net-_u17-pad2_ ] [net-_u21-pad2_ ] u21 +a7 net-_u11-pad2_ net-_u4-pad2_ u4 +a8 [net-_m4-pad2_ ] [net-_u11-pad2_ ] u11 +a9 [net-_u4-pad2_ ] [net-_m6-pad2_ ] u8 +a10 [net-_m4-pad3_ ] [net-_u15-pad2_ ] u15 +a11 net-_u15-pad2_ net-_u19-pad2_ u19 +a12 [net-_u19-pad2_ ] [net-_u23-pad2_ ] u23 +a13 net-_u12-pad2_ net-_u10-pad1_ u6 +a14 [net-_m7-pad2_ ] [net-_u12-pad2_ ] u12 +a15 [net-_u10-pad1_ ] [net-_m8-pad2_ ] u10 +a16 [net-_m7-pad3_ ] [net-_u16-pad2_ ] u16 +a17 net-_u16-pad2_ net-_u20-pad2_ u20 +a18 [net-_u20-pad2_ ] [net-_u24-pad2_ ] u24 +a19 net-_u2-pad1_ net-_u2-pad2_ u2 +a20 [net-_m2-pad2_ ] [net-_u2-pad1_ ] u9 +a21 [net-_u2-pad2_ ] [net-_m5-pad2_ ] u5 +a22 [net-_m2-pad3_ ] [net-_u14-pad2_ ] u14 +a23 net-_u14-pad2_ net-_u18-pad2_ u18 +a24 [net-_u18-pad2_ ] [net-_u22-pad2_ ] u22 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u7 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u3 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u13 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u17 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u21 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u11 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u8 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u15 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u19 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u23 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u12 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u10 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u16 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u20 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u24 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u9 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u5 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u14 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u18 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u22 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Control Statements + +.ends SN74CBTLV3126 \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3126/SN74CBTLV3126_Previous_Values.xml b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3126/SN74CBTLV3126_Previous_Values.xml new file mode 100644 index 000000000..21dbdd0ac --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3126/SN74CBTLV3126_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_inverteradc_bridgedac_bridgeadc_bridged_bufferdac_bridged_inverteradc_bridgedac_bridgeadc_bridged_bufferdac_bridged_inverteradc_bridgedac_bridgeadc_bridged_bufferdac_bridged_inverteradc_bridgedac_bridgeadc_bridged_bufferdac_bridgeC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3126/analysis b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3126/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3126/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3257/NMOS-180nm.lib b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3257/NMOS-180nm.lib new file mode 100644 index 000000000..51e9b1196 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3257/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3257/PMOS-180nm.lib b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3257/PMOS-180nm.lib new file mode 100644 index 000000000..032b5b95e --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3257/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3257/SN74CBTLV3257-cache.lib b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3257/SN74CBTLV3257-cache.lib new file mode 100644 index 000000000..234336a37 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3257/SN74CBTLV3257-cache.lib @@ -0,0 +1,189 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# adc_bridge_1 +# +DEF adc_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# adc_bridge_2 +# +DEF adc_bridge_2 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_2" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -100 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X OUT1 3 550 50 200 L 50 50 1 1 O +X OUT2 4 550 -50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_buffer +# +DEF d_buffer U 0 40 Y Y 1 F N +F0 "U" 0 -50 60 H V C CNN +F1 "d_buffer" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N +X IN 1 -500 0 200 R 50 50 1 1 I +X OUT 2 650 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# dac_bridge_1 +# +DEF dac_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3257/SN74CBTLV3257.cir b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3257/SN74CBTLV3257.cir new file mode 100644 index 000000000..789392d00 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3257/SN74CBTLV3257.cir @@ -0,0 +1,68 @@ +* C:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\SN74CBTLV3257\SN74CBTLV3257.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/24/25 23:39:48 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ GND mosfet_n +M3 Net-_M1-Pad3_ Net-_M3-Pad2_ Net-_M1-Pad1_ VCC mosfet_p +U1 Net-_U1-Pad1_ Net-_M1-Pad1_ Net-_M11-Pad3_ Net-_U1-Pad4_ Net-_M2-Pad1_ Net-_M10-Pad1_ Net-_U1-Pad7_ GND Net-_U1-Pad9_ Net-_M12-Pad1_ Net-_M4-Pad1_ Net-_U1-Pad12_ Net-_M14-Pad1_ Net-_M6-Pad1_ Net-_U1-Pad15_ VCC PORT +U3 Net-_U13-Pad1_ Net-_U3-Pad2_ d_inverter +U4 Net-_U3-Pad2_ Net-_M3-Pad2_ dac_bridge_1 +U13 Net-_U13-Pad1_ Net-_M1-Pad2_ dac_bridge_1 +M9 Net-_M11-Pad3_ Net-_M9-Pad2_ Net-_M1-Pad3_ GND mosfet_n +M11 Net-_M1-Pad3_ Net-_M11-Pad2_ Net-_M11-Pad3_ VCC mosfet_p +U19 Net-_U18-Pad3_ Net-_U19-Pad2_ d_inverter +U20 Net-_U19-Pad2_ Net-_M11-Pad2_ dac_bridge_1 +U27 Net-_U18-Pad3_ Net-_M9-Pad2_ dac_bridge_1 +M2 Net-_M2-Pad1_ Net-_M2-Pad2_ Net-_M10-Pad3_ GND mosfet_n +M5 Net-_M10-Pad3_ Net-_M5-Pad2_ Net-_M2-Pad1_ VCC mosfet_p +U5 Net-_U13-Pad1_ Net-_U5-Pad2_ d_inverter +U7 Net-_U5-Pad2_ Net-_M5-Pad2_ dac_bridge_1 +U14 Net-_U13-Pad1_ Net-_M2-Pad2_ dac_bridge_1 +M10 Net-_M10-Pad1_ Net-_M10-Pad2_ Net-_M10-Pad3_ GND mosfet_n +M13 Net-_M10-Pad3_ Net-_M13-Pad2_ Net-_M10-Pad1_ VCC mosfet_p +U21 Net-_U18-Pad3_ Net-_U21-Pad2_ d_inverter +U23 Net-_U21-Pad2_ Net-_M13-Pad2_ dac_bridge_1 +U28 Net-_U18-Pad3_ Net-_M10-Pad2_ dac_bridge_1 +M4 Net-_M4-Pad1_ Net-_M4-Pad2_ Net-_M12-Pad3_ GND mosfet_n +M7 Net-_M12-Pad3_ Net-_M7-Pad2_ Net-_M4-Pad1_ VCC mosfet_p +U6 Net-_U13-Pad1_ Net-_U6-Pad2_ d_inverter +U8 Net-_U6-Pad2_ Net-_M7-Pad2_ dac_bridge_1 +U15 Net-_U13-Pad1_ Net-_M4-Pad2_ dac_bridge_1 +M12 Net-_M12-Pad1_ Net-_M12-Pad2_ Net-_M12-Pad3_ GND mosfet_n +M15 Net-_M12-Pad3_ Net-_M15-Pad2_ Net-_M12-Pad1_ VCC mosfet_p +U22 Net-_U18-Pad3_ Net-_U22-Pad2_ d_inverter +U24 Net-_U22-Pad2_ Net-_M15-Pad2_ dac_bridge_1 +U29 Net-_U18-Pad3_ Net-_M12-Pad2_ dac_bridge_1 +M6 Net-_M6-Pad1_ Net-_M6-Pad2_ Net-_M14-Pad3_ GND mosfet_n +M8 Net-_M14-Pad3_ Net-_M8-Pad2_ Net-_M6-Pad1_ VCC mosfet_p +U9 Net-_U13-Pad1_ Net-_U10-Pad1_ d_inverter +U10 Net-_U10-Pad1_ Net-_M8-Pad2_ dac_bridge_1 +U16 Net-_U13-Pad1_ Net-_M6-Pad2_ dac_bridge_1 +M14 Net-_M14-Pad1_ Net-_M14-Pad2_ Net-_M14-Pad3_ GND mosfet_n +M16 Net-_M14-Pad3_ Net-_M16-Pad2_ Net-_M14-Pad1_ VCC mosfet_p +U25 Net-_U18-Pad3_ Net-_U25-Pad2_ d_inverter +U26 Net-_U25-Pad2_ Net-_M16-Pad2_ dac_bridge_1 +U30 Net-_U18-Pad3_ Net-_M14-Pad2_ dac_bridge_1 +U17 Net-_U11-Pad2_ Net-_U12-Pad2_ Net-_U13-Pad1_ d_and +U18 Net-_U11-Pad1_ Net-_U12-Pad2_ Net-_U18-Pad3_ d_and +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ d_inverter +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_inverter +U2 Net-_U1-Pad1_ Net-_U1-Pad15_ Net-_U11-Pad1_ Net-_U12-Pad1_ adc_bridge_2 +U35 Net-_U31-Pad2_ Net-_U35-Pad2_ d_buffer +U31 Net-_M1-Pad3_ Net-_U31-Pad2_ adc_bridge_1 +U39 Net-_U35-Pad2_ Net-_U1-Pad4_ dac_bridge_1 +U38 Net-_U34-Pad2_ Net-_U38-Pad2_ d_buffer +U34 Net-_M10-Pad3_ Net-_U34-Pad2_ adc_bridge_1 +U42 Net-_U38-Pad2_ Net-_U1-Pad7_ dac_bridge_1 +U36 Net-_U32-Pad2_ Net-_U36-Pad2_ d_buffer +U32 Net-_M12-Pad3_ Net-_U32-Pad2_ adc_bridge_1 +U40 Net-_U36-Pad2_ Net-_U1-Pad9_ dac_bridge_1 +U37 Net-_U33-Pad2_ Net-_U37-Pad2_ d_buffer +U33 Net-_M14-Pad3_ Net-_U33-Pad2_ adc_bridge_1 +U41 Net-_U37-Pad2_ Net-_U1-Pad12_ dac_bridge_1 + +.end diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3257/SN74CBTLV3257.cir.out b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3257/SN74CBTLV3257.cir.out new file mode 100644 index 000000000..fd8c67b72 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3257/SN74CBTLV3257.cir.out @@ -0,0 +1,194 @@ +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\sn74cbtlv3257\sn74cbtlv3257.cir + +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1 +m3 net-_m1-pad3_ net-_m3-pad2_ net-_m1-pad1_ vcc CMOSP W=100u L=100u M=1 +* u1 net-_u1-pad1_ net-_m1-pad1_ net-_m11-pad3_ net-_u1-pad4_ net-_m2-pad1_ net-_m10-pad1_ net-_u1-pad7_ gnd net-_u1-pad9_ net-_m12-pad1_ net-_m4-pad1_ net-_u1-pad12_ net-_m14-pad1_ net-_m6-pad1_ net-_u1-pad15_ vcc port +* u3 net-_u13-pad1_ net-_u3-pad2_ d_inverter +* u4 net-_u3-pad2_ net-_m3-pad2_ dac_bridge_1 +* u13 net-_u13-pad1_ net-_m1-pad2_ dac_bridge_1 +m9 net-_m11-pad3_ net-_m9-pad2_ net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1 +m11 net-_m1-pad3_ net-_m11-pad2_ net-_m11-pad3_ vcc CMOSP W=100u L=100u M=1 +* u19 net-_u18-pad3_ net-_u19-pad2_ d_inverter +* u20 net-_u19-pad2_ net-_m11-pad2_ dac_bridge_1 +* u27 net-_u18-pad3_ net-_m9-pad2_ dac_bridge_1 +m2 net-_m2-pad1_ net-_m2-pad2_ net-_m10-pad3_ gnd CMOSN W=100u L=100u M=1 +m5 net-_m10-pad3_ net-_m5-pad2_ net-_m2-pad1_ vcc CMOSP W=100u L=100u M=1 +* u5 net-_u13-pad1_ net-_u5-pad2_ d_inverter +* u7 net-_u5-pad2_ net-_m5-pad2_ dac_bridge_1 +* u14 net-_u13-pad1_ net-_m2-pad2_ dac_bridge_1 +m10 net-_m10-pad1_ net-_m10-pad2_ net-_m10-pad3_ gnd CMOSN W=100u L=100u M=1 +m13 net-_m10-pad3_ net-_m13-pad2_ net-_m10-pad1_ vcc CMOSP W=100u L=100u M=1 +* u21 net-_u18-pad3_ net-_u21-pad2_ d_inverter +* u23 net-_u21-pad2_ net-_m13-pad2_ dac_bridge_1 +* u28 net-_u18-pad3_ net-_m10-pad2_ dac_bridge_1 +m4 net-_m4-pad1_ net-_m4-pad2_ net-_m12-pad3_ gnd CMOSN W=100u L=100u M=1 +m7 net-_m12-pad3_ net-_m7-pad2_ net-_m4-pad1_ vcc CMOSP W=100u L=100u M=1 +* u6 net-_u13-pad1_ net-_u6-pad2_ d_inverter +* u8 net-_u6-pad2_ net-_m7-pad2_ dac_bridge_1 +* u15 net-_u13-pad1_ net-_m4-pad2_ dac_bridge_1 +m12 net-_m12-pad1_ net-_m12-pad2_ net-_m12-pad3_ gnd CMOSN W=100u L=100u M=1 +m15 net-_m12-pad3_ net-_m15-pad2_ net-_m12-pad1_ vcc CMOSP W=100u L=100u M=1 +* u22 net-_u18-pad3_ net-_u22-pad2_ d_inverter +* u24 net-_u22-pad2_ net-_m15-pad2_ dac_bridge_1 +* u29 net-_u18-pad3_ net-_m12-pad2_ dac_bridge_1 +m6 net-_m6-pad1_ net-_m6-pad2_ net-_m14-pad3_ gnd CMOSN W=100u L=100u M=1 +m8 net-_m14-pad3_ net-_m8-pad2_ net-_m6-pad1_ vcc CMOSP W=100u L=100u M=1 +* u9 net-_u13-pad1_ net-_u10-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_m8-pad2_ dac_bridge_1 +* u16 net-_u13-pad1_ net-_m6-pad2_ dac_bridge_1 +m14 net-_m14-pad1_ net-_m14-pad2_ net-_m14-pad3_ gnd CMOSN W=100u L=100u M=1 +m16 net-_m14-pad3_ net-_m16-pad2_ net-_m14-pad1_ vcc CMOSP W=100u L=100u M=1 +* u25 net-_u18-pad3_ net-_u25-pad2_ d_inverter +* u26 net-_u25-pad2_ net-_m16-pad2_ dac_bridge_1 +* u30 net-_u18-pad3_ net-_m14-pad2_ dac_bridge_1 +* u17 net-_u11-pad2_ net-_u12-pad2_ net-_u13-pad1_ d_and +* u18 net-_u11-pad1_ net-_u12-pad2_ net-_u18-pad3_ d_and +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u2 net-_u1-pad1_ net-_u1-pad15_ net-_u11-pad1_ net-_u12-pad1_ adc_bridge_2 +* u35 net-_u31-pad2_ net-_u35-pad2_ d_buffer +* u31 net-_m1-pad3_ net-_u31-pad2_ adc_bridge_1 +* u39 net-_u35-pad2_ net-_u1-pad4_ dac_bridge_1 +* u38 net-_u34-pad2_ net-_u38-pad2_ d_buffer +* u34 net-_m10-pad3_ net-_u34-pad2_ adc_bridge_1 +* u42 net-_u38-pad2_ net-_u1-pad7_ dac_bridge_1 +* u36 net-_u32-pad2_ net-_u36-pad2_ d_buffer +* u32 net-_m12-pad3_ net-_u32-pad2_ adc_bridge_1 +* u40 net-_u36-pad2_ net-_u1-pad9_ dac_bridge_1 +* u37 net-_u33-pad2_ net-_u37-pad2_ d_buffer +* u33 net-_m14-pad3_ net-_u33-pad2_ adc_bridge_1 +* u41 net-_u37-pad2_ net-_u1-pad12_ dac_bridge_1 +a1 net-_u13-pad1_ net-_u3-pad2_ u3 +a2 [net-_u3-pad2_ ] [net-_m3-pad2_ ] u4 +a3 [net-_u13-pad1_ ] [net-_m1-pad2_ ] u13 +a4 net-_u18-pad3_ net-_u19-pad2_ u19 +a5 [net-_u19-pad2_ ] [net-_m11-pad2_ ] u20 +a6 [net-_u18-pad3_ ] [net-_m9-pad2_ ] u27 +a7 net-_u13-pad1_ net-_u5-pad2_ u5 +a8 [net-_u5-pad2_ ] [net-_m5-pad2_ ] u7 +a9 [net-_u13-pad1_ ] [net-_m2-pad2_ ] u14 +a10 net-_u18-pad3_ net-_u21-pad2_ u21 +a11 [net-_u21-pad2_ ] [net-_m13-pad2_ ] u23 +a12 [net-_u18-pad3_ ] [net-_m10-pad2_ ] u28 +a13 net-_u13-pad1_ net-_u6-pad2_ u6 +a14 [net-_u6-pad2_ ] [net-_m7-pad2_ ] u8 +a15 [net-_u13-pad1_ ] [net-_m4-pad2_ ] u15 +a16 net-_u18-pad3_ net-_u22-pad2_ u22 +a17 [net-_u22-pad2_ ] [net-_m15-pad2_ ] u24 +a18 [net-_u18-pad3_ ] [net-_m12-pad2_ ] u29 +a19 net-_u13-pad1_ net-_u10-pad1_ u9 +a20 [net-_u10-pad1_ ] [net-_m8-pad2_ ] u10 +a21 [net-_u13-pad1_ ] [net-_m6-pad2_ ] u16 +a22 net-_u18-pad3_ net-_u25-pad2_ u25 +a23 [net-_u25-pad2_ ] [net-_m16-pad2_ ] u26 +a24 [net-_u18-pad3_ ] [net-_m14-pad2_ ] u30 +a25 [net-_u11-pad2_ net-_u12-pad2_ ] net-_u13-pad1_ u17 +a26 [net-_u11-pad1_ net-_u12-pad2_ ] net-_u18-pad3_ u18 +a27 net-_u11-pad1_ net-_u11-pad2_ u11 +a28 net-_u12-pad1_ net-_u12-pad2_ u12 +a29 [net-_u1-pad1_ net-_u1-pad15_ ] [net-_u11-pad1_ net-_u12-pad1_ ] u2 +a30 net-_u31-pad2_ net-_u35-pad2_ u35 +a31 [net-_m1-pad3_ ] [net-_u31-pad2_ ] u31 +a32 [net-_u35-pad2_ ] [net-_u1-pad4_ ] u39 +a33 net-_u34-pad2_ net-_u38-pad2_ u38 +a34 [net-_m10-pad3_ ] [net-_u34-pad2_ ] u34 +a35 [net-_u38-pad2_ ] [net-_u1-pad7_ ] u42 +a36 net-_u32-pad2_ net-_u36-pad2_ u36 +a37 [net-_m12-pad3_ ] [net-_u32-pad2_ ] u32 +a38 [net-_u36-pad2_ ] [net-_u1-pad9_ ] u40 +a39 net-_u33-pad2_ net-_u37-pad2_ u37 +a40 [net-_m14-pad3_ ] [net-_u33-pad2_ ] u33 +a41 [net-_u37-pad2_ ] [net-_u1-pad12_ ] u41 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u4 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u13 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u20 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u27 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u7 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u14 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u23 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u28 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u8 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u15 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u24 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u29 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u10 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u16 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u26 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u30 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u35 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u31 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u39 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u38 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u34 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u42 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u36 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u32 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u40 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u37 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u33 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u41 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3257/SN74CBTLV3257.pro b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3257/SN74CBTLV3257.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3257/SN74CBTLV3257.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3257/SN74CBTLV3257.sch b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3257/SN74CBTLV3257.sch new file mode 100644 index 000000000..62eb3d20b --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3257/SN74CBTLV3257.sch @@ -0,0 +1,1356 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN74CBTLV3257-cache +EELAYER 25 0 +EELAYER END +$Descr A2 23386 16535 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L mosfet_n M1 +U 1 1 685ADE26 +P 7200 3550 +F 0 "M1" H 7200 3400 50 0000 R CNN +F 1 "mosfet_n" H 7300 3500 50 0000 R CNN +F 2 "" H 7500 3250 29 0000 C CNN +F 3 "" H 7300 3350 60 0000 C CNN + 1 7200 3550 + 0 -1 -1 0 +$EndComp +$Comp +L mosfet_p M3 +U 1 1 685ADEFF +P 7400 2850 +F 0 "M3" H 7350 2900 50 0000 R CNN +F 1 "mosfet_p" H 7450 3000 50 0000 R CNN +F 2 "" H 7650 2950 29 0000 C CNN +F 3 "" H 7450 2850 60 0000 C CNN + 1 7400 2850 + 0 1 1 0 +$EndComp +Text GLabel 5100 4150 0 60 Input ~ 0 +VCC +$Comp +L PORT U1 +U 1 1 685ADFFF +P 5400 11800 +F 0 "U1" H 5450 11900 30 0000 C CNN +F 1 "PORT" H 5400 11800 30 0000 C CNN +F 2 "" H 5400 11800 60 0000 C CNN +F 3 "" H 5400 11800 60 0000 C CNN + 1 5400 11800 + 1 0 0 -1 +$EndComp +Text GLabel 7100 3100 0 60 Input ~ 0 +VCC +Text GLabel 5050 4450 0 60 Input ~ 0 +GND +$Comp +L PORT U1 +U 2 1 685AE10A +P 6500 3250 +F 0 "U1" H 6550 3350 30 0000 C CNN +F 1 "PORT" H 6500 3250 30 0000 C CNN +F 2 "" H 6500 3250 60 0000 C CNN +F 3 "" H 6500 3250 60 0000 C CNN + 2 6500 3250 + 1 0 0 -1 +$EndComp +Text GLabel 7750 3250 2 60 Input ~ 0 +GND +$Comp +L d_inverter U3 +U 1 1 685AE1E2 +P 6700 3700 +F 0 "U3" H 6700 3600 60 0000 C CNN +F 1 "d_inverter" H 6700 3850 60 0000 C CNN +F 2 "" H 6750 3650 60 0000 C CNN +F 3 "" H 6750 3650 60 0000 C CNN + 1 6700 3700 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 7200 3000 7150 3000 +Wire Wire Line + 7150 3000 7150 3350 +Wire Wire Line + 7150 3350 7200 3350 +Wire Wire Line + 7600 3000 7650 3000 +Wire Wire Line + 7650 3000 7650 3350 +Wire Wire Line + 7650 3350 7600 3350 +Wire Wire Line + 5100 4150 5300 4150 +Wire Wire Line + 7100 3100 7250 3100 +Wire Wire Line + 5050 4450 5300 4450 +Wire Wire Line + 7550 3250 7750 3250 +Wire Wire Line + 7400 2600 7400 2700 +Wire Wire Line + 6250 2600 6200 2600 +Wire Wire Line + 7400 3650 7400 3800 +Connection ~ 7150 3250 +Wire Wire Line + 6200 3400 6700 3400 +Wire Wire Line + 6200 2600 6200 3400 +$Comp +L dac_bridge_1 U4 +U 1 1 685AE24E +P 6850 2650 +F 0 "U4" H 6850 2650 60 0000 C CNN +F 1 "dac_bridge_1" H 6850 2800 60 0000 C CNN +F 2 "" H 6850 2650 60 0000 C CNN +F 3 "" H 6850 2650 60 0000 C CNN + 1 6850 2650 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U13 +U 1 1 685AE2FA +P 7650 4100 +F 0 "U13" H 7650 4100 60 0000 C CNN +F 1 "dac_bridge_1" H 7650 4250 60 0000 C CNN +F 2 "" H 7650 4100 60 0000 C CNN +F 3 "" H 7650 4100 60 0000 C CNN + 1 7650 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7400 3800 8200 3800 +Wire Wire Line + 8200 3800 8200 4050 +Wire Wire Line + 6700 4000 6700 4050 +Wire Wire Line + 6200 4050 7050 4050 +$Comp +L mosfet_n M9 +U 1 1 685B0CCD +P 10150 3550 +F 0 "M9" H 10150 3400 50 0000 R CNN +F 1 "mosfet_n" H 10250 3500 50 0000 R CNN +F 2 "" H 10450 3250 29 0000 C CNN +F 3 "" H 10250 3350 60 0000 C CNN + 1 10150 3550 + 0 -1 -1 0 +$EndComp +$Comp +L mosfet_p M11 +U 1 1 685B0CD3 +P 10350 2850 +F 0 "M11" H 10300 2900 50 0000 R CNN +F 1 "mosfet_p" H 10400 3000 50 0000 R CNN +F 2 "" H 10600 2950 29 0000 C CNN +F 3 "" H 10400 2850 60 0000 C CNN + 1 10350 2850 + 0 1 1 0 +$EndComp +Text GLabel 10050 3100 0 60 Input ~ 0 +VCC +Text GLabel 10700 3250 2 60 Input ~ 0 +GND +$Comp +L d_inverter U19 +U 1 1 685B0CDB +P 9650 3700 +F 0 "U19" H 9650 3600 60 0000 C CNN +F 1 "d_inverter" H 9650 3850 60 0000 C CNN +F 2 "" H 9700 3650 60 0000 C CNN +F 3 "" H 9700 3650 60 0000 C CNN + 1 9650 3700 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 10150 3000 10100 3000 +Wire Wire Line + 10100 3000 10100 3350 +Wire Wire Line + 10100 3350 10150 3350 +Wire Wire Line + 10550 3000 10600 3000 +Wire Wire Line + 10600 3000 10600 3350 +Wire Wire Line + 10600 3350 10550 3350 +Wire Wire Line + 10050 3100 10200 3100 +Wire Wire Line + 10500 3250 10700 3250 +Wire Wire Line + 10350 2600 10350 2700 +Wire Wire Line + 9200 2600 9150 2600 +Wire Wire Line + 10350 3650 10350 3800 +Connection ~ 10100 3250 +Wire Wire Line + 9150 3400 9650 3400 +Wire Wire Line + 9150 2600 9150 3400 +$Comp +L dac_bridge_1 U20 +U 1 1 685B0CF0 +P 9800 2650 +F 0 "U20" H 9800 2650 60 0000 C CNN +F 1 "dac_bridge_1" H 9800 2800 60 0000 C CNN +F 2 "" H 9800 2650 60 0000 C CNN +F 3 "" H 9800 2650 60 0000 C CNN + 1 9800 2650 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U27 +U 1 1 685B0CF6 +P 10600 4100 +F 0 "U27" H 10600 4100 60 0000 C CNN +F 1 "dac_bridge_1" H 10600 4250 60 0000 C CNN +F 2 "" H 10600 4100 60 0000 C CNN +F 3 "" H 10600 4100 60 0000 C CNN + 1 10600 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10350 3800 11150 3800 +Wire Wire Line + 11150 3800 11150 4050 +Wire Wire Line + 9650 4000 9650 4050 +Wire Wire Line + 9100 4050 10000 4050 +$Comp +L mosfet_n M2 +U 1 1 685B102A +P 7350 5550 +F 0 "M2" H 7350 5400 50 0000 R CNN +F 1 "mosfet_n" H 7450 5500 50 0000 R CNN +F 2 "" H 7650 5250 29 0000 C CNN +F 3 "" H 7450 5350 60 0000 C CNN + 1 7350 5550 + 0 -1 -1 0 +$EndComp +$Comp +L mosfet_p M5 +U 1 1 685B1030 +P 7550 4850 +F 0 "M5" H 7500 4900 50 0000 R CNN +F 1 "mosfet_p" H 7600 5000 50 0000 R CNN +F 2 "" H 7800 4950 29 0000 C CNN +F 3 "" H 7600 4850 60 0000 C CNN + 1 7550 4850 + 0 1 1 0 +$EndComp +Text GLabel 7250 5100 0 60 Input ~ 0 +VCC +Text GLabel 7900 5250 2 60 Input ~ 0 +GND +$Comp +L d_inverter U5 +U 1 1 685B1038 +P 6850 5700 +F 0 "U5" H 6850 5600 60 0000 C CNN +F 1 "d_inverter" H 6850 5850 60 0000 C CNN +F 2 "" H 6900 5650 60 0000 C CNN +F 3 "" H 6900 5650 60 0000 C CNN + 1 6850 5700 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 7350 5000 7300 5000 +Wire Wire Line + 7300 5000 7300 5350 +Wire Wire Line + 7300 5350 7350 5350 +Wire Wire Line + 7750 5000 7800 5000 +Wire Wire Line + 7800 5000 7800 5350 +Wire Wire Line + 7800 5350 7750 5350 +Wire Wire Line + 7250 5100 7400 5100 +Wire Wire Line + 7700 5250 7900 5250 +Wire Wire Line + 7550 4600 7550 4700 +Wire Wire Line + 6400 4600 6350 4600 +Wire Wire Line + 7550 5650 7550 5800 +Connection ~ 7300 5250 +Wire Wire Line + 6350 5400 6850 5400 +Wire Wire Line + 6350 4600 6350 5400 +$Comp +L dac_bridge_1 U7 +U 1 1 685B104D +P 7000 4650 +F 0 "U7" H 7000 4650 60 0000 C CNN +F 1 "dac_bridge_1" H 7000 4800 60 0000 C CNN +F 2 "" H 7000 4650 60 0000 C CNN +F 3 "" H 7000 4650 60 0000 C CNN + 1 7000 4650 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U14 +U 1 1 685B1053 +P 7800 6100 +F 0 "U14" H 7800 6100 60 0000 C CNN +F 1 "dac_bridge_1" H 7800 6250 60 0000 C CNN +F 2 "" H 7800 6100 60 0000 C CNN +F 3 "" H 7800 6100 60 0000 C CNN + 1 7800 6100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7550 5800 8350 5800 +Wire Wire Line + 8350 5800 8350 6050 +Wire Wire Line + 6850 6000 6850 6050 +Wire Wire Line + 6850 6050 7200 6050 +$Comp +L mosfet_n M10 +U 1 1 685B105D +P 10300 5550 +F 0 "M10" H 10300 5400 50 0000 R CNN +F 1 "mosfet_n" H 10400 5500 50 0000 R CNN +F 2 "" H 10600 5250 29 0000 C CNN +F 3 "" H 10400 5350 60 0000 C CNN + 1 10300 5550 + 0 -1 -1 0 +$EndComp +$Comp +L mosfet_p M13 +U 1 1 685B1063 +P 10500 4850 +F 0 "M13" H 10450 4900 50 0000 R CNN +F 1 "mosfet_p" H 10550 5000 50 0000 R CNN +F 2 "" H 10750 4950 29 0000 C CNN +F 3 "" H 10550 4850 60 0000 C CNN + 1 10500 4850 + 0 1 1 0 +$EndComp +Text GLabel 10200 5100 0 60 Input ~ 0 +VCC +Text GLabel 10850 5250 2 60 Input ~ 0 +GND +$Comp +L d_inverter U21 +U 1 1 685B106B +P 9800 5700 +F 0 "U21" H 9800 5600 60 0000 C CNN +F 1 "d_inverter" H 9800 5850 60 0000 C CNN +F 2 "" H 9850 5650 60 0000 C CNN +F 3 "" H 9850 5650 60 0000 C CNN + 1 9800 5700 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 10300 5000 10250 5000 +Wire Wire Line + 10250 5000 10250 5350 +Wire Wire Line + 10250 5350 10300 5350 +Wire Wire Line + 10700 5000 10750 5000 +Wire Wire Line + 10750 5000 10750 5350 +Wire Wire Line + 10750 5350 10700 5350 +Wire Wire Line + 10200 5100 10350 5100 +Wire Wire Line + 10650 5250 10850 5250 +Wire Wire Line + 10500 4600 10500 4700 +Wire Wire Line + 9350 4600 9300 4600 +Wire Wire Line + 10500 5650 10500 5800 +Connection ~ 10250 5250 +Wire Wire Line + 9300 5400 9800 5400 +Wire Wire Line + 9300 4600 9300 5400 +$Comp +L dac_bridge_1 U23 +U 1 1 685B1080 +P 9950 4650 +F 0 "U23" H 9950 4650 60 0000 C CNN +F 1 "dac_bridge_1" H 9950 4800 60 0000 C CNN +F 2 "" H 9950 4650 60 0000 C CNN +F 3 "" H 9950 4650 60 0000 C CNN + 1 9950 4650 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U28 +U 1 1 685B1086 +P 10750 6100 +F 0 "U28" H 10750 6100 60 0000 C CNN +F 1 "dac_bridge_1" H 10750 6250 60 0000 C CNN +F 2 "" H 10750 6100 60 0000 C CNN +F 3 "" H 10750 6100 60 0000 C CNN + 1 10750 6100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10500 5800 11300 5800 +Wire Wire Line + 11300 5800 11300 6050 +Wire Wire Line + 9800 6000 9800 6050 +Wire Wire Line + 9800 6050 10150 6050 +$Comp +L mosfet_n M4 +U 1 1 685B1548 +P 7400 7600 +F 0 "M4" H 7400 7450 50 0000 R CNN +F 1 "mosfet_n" H 7500 7550 50 0000 R CNN +F 2 "" H 7700 7300 29 0000 C CNN +F 3 "" H 7500 7400 60 0000 C CNN + 1 7400 7600 + 0 -1 -1 0 +$EndComp +$Comp +L mosfet_p M7 +U 1 1 685B154E +P 7600 6900 +F 0 "M7" H 7550 6950 50 0000 R CNN +F 1 "mosfet_p" H 7650 7050 50 0000 R CNN +F 2 "" H 7850 7000 29 0000 C CNN +F 3 "" H 7650 6900 60 0000 C CNN + 1 7600 6900 + 0 1 1 0 +$EndComp +Text GLabel 7300 7150 0 60 Input ~ 0 +VCC +Text GLabel 7950 7300 2 60 Input ~ 0 +GND +$Comp +L d_inverter U6 +U 1 1 685B1556 +P 6900 7750 +F 0 "U6" H 6900 7650 60 0000 C CNN +F 1 "d_inverter" H 6900 7900 60 0000 C CNN +F 2 "" H 6950 7700 60 0000 C CNN +F 3 "" H 6950 7700 60 0000 C CNN + 1 6900 7750 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 7400 7050 7350 7050 +Wire Wire Line + 7350 7050 7350 7400 +Wire Wire Line + 7350 7400 7400 7400 +Wire Wire Line + 7800 7050 7850 7050 +Wire Wire Line + 7850 7050 7850 7400 +Wire Wire Line + 7850 7400 7800 7400 +Wire Wire Line + 7300 7150 7450 7150 +Wire Wire Line + 7750 7300 7950 7300 +Wire Wire Line + 7600 6650 7600 6750 +Wire Wire Line + 6450 6650 6400 6650 +Wire Wire Line + 7600 7700 7600 7850 +Connection ~ 7350 7300 +Wire Wire Line + 7350 7300 6950 7300 +Wire Wire Line + 6400 7450 6900 7450 +Wire Wire Line + 6400 6650 6400 7450 +$Comp +L dac_bridge_1 U8 +U 1 1 685B156B +P 7050 6700 +F 0 "U8" H 7050 6700 60 0000 C CNN +F 1 "dac_bridge_1" H 7050 6850 60 0000 C CNN +F 2 "" H 7050 6700 60 0000 C CNN +F 3 "" H 7050 6700 60 0000 C CNN + 1 7050 6700 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U15 +U 1 1 685B1571 +P 7850 8150 +F 0 "U15" H 7850 8150 60 0000 C CNN +F 1 "dac_bridge_1" H 7850 8300 60 0000 C CNN +F 2 "" H 7850 8150 60 0000 C CNN +F 3 "" H 7850 8150 60 0000 C CNN + 1 7850 8150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7600 7850 8400 7850 +Wire Wire Line + 8400 7850 8400 8100 +Wire Wire Line + 6900 8050 6900 8100 +Wire Wire Line + 6900 8100 7250 8100 +$Comp +L mosfet_n M12 +U 1 1 685B157B +P 10350 7600 +F 0 "M12" H 10350 7450 50 0000 R CNN +F 1 "mosfet_n" H 10450 7550 50 0000 R CNN +F 2 "" H 10650 7300 29 0000 C CNN +F 3 "" H 10450 7400 60 0000 C CNN + 1 10350 7600 + 0 -1 -1 0 +$EndComp +$Comp +L mosfet_p M15 +U 1 1 685B1581 +P 10550 6900 +F 0 "M15" H 10500 6950 50 0000 R CNN +F 1 "mosfet_p" H 10600 7050 50 0000 R CNN +F 2 "" H 10800 7000 29 0000 C CNN +F 3 "" H 10600 6900 60 0000 C CNN + 1 10550 6900 + 0 1 1 0 +$EndComp +Text GLabel 10250 7150 0 60 Input ~ 0 +VCC +Text GLabel 10900 7300 2 60 Input ~ 0 +GND +$Comp +L d_inverter U22 +U 1 1 685B1589 +P 9850 7750 +F 0 "U22" H 9850 7650 60 0000 C CNN +F 1 "d_inverter" H 9850 7900 60 0000 C CNN +F 2 "" H 9900 7700 60 0000 C CNN +F 3 "" H 9900 7700 60 0000 C CNN + 1 9850 7750 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 10350 7050 10300 7050 +Wire Wire Line + 10300 7050 10300 7400 +Wire Wire Line + 10300 7400 10350 7400 +Wire Wire Line + 10750 7050 10800 7050 +Wire Wire Line + 10800 7050 10800 7400 +Wire Wire Line + 10800 7400 10750 7400 +Wire Wire Line + 10250 7150 10400 7150 +Wire Wire Line + 10700 7300 10900 7300 +Wire Wire Line + 10550 6650 10550 6750 +Wire Wire Line + 9400 6650 9350 6650 +Wire Wire Line + 10550 7700 10550 7850 +Connection ~ 10300 7300 +Wire Wire Line + 10300 7300 9900 7300 +Wire Wire Line + 9350 7450 9850 7450 +Wire Wire Line + 9350 6650 9350 7450 +$Comp +L dac_bridge_1 U24 +U 1 1 685B159E +P 10000 6700 +F 0 "U24" H 10000 6700 60 0000 C CNN +F 1 "dac_bridge_1" H 10000 6850 60 0000 C CNN +F 2 "" H 10000 6700 60 0000 C CNN +F 3 "" H 10000 6700 60 0000 C CNN + 1 10000 6700 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U29 +U 1 1 685B15A4 +P 10800 8150 +F 0 "U29" H 10800 8150 60 0000 C CNN +F 1 "dac_bridge_1" H 10800 8300 60 0000 C CNN +F 2 "" H 10800 8150 60 0000 C CNN +F 3 "" H 10800 8150 60 0000 C CNN + 1 10800 8150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10550 7850 11350 7850 +Wire Wire Line + 11350 7850 11350 8100 +Wire Wire Line + 9850 8050 9850 8100 +Wire Wire Line + 9850 8100 10200 8100 +$Comp +L mosfet_n M6 +U 1 1 685B15AE +P 7550 9600 +F 0 "M6" H 7550 9450 50 0000 R CNN +F 1 "mosfet_n" H 7650 9550 50 0000 R CNN +F 2 "" H 7850 9300 29 0000 C CNN +F 3 "" H 7650 9400 60 0000 C CNN + 1 7550 9600 + 0 -1 -1 0 +$EndComp +$Comp +L mosfet_p M8 +U 1 1 685B15B4 +P 7750 8900 +F 0 "M8" H 7700 8950 50 0000 R CNN +F 1 "mosfet_p" H 7800 9050 50 0000 R CNN +F 2 "" H 8000 9000 29 0000 C CNN +F 3 "" H 7800 8900 60 0000 C CNN + 1 7750 8900 + 0 1 1 0 +$EndComp +Text GLabel 7450 9150 0 60 Input ~ 0 +VCC +Text GLabel 8100 9300 2 60 Input ~ 0 +GND +$Comp +L d_inverter U9 +U 1 1 685B15BC +P 7050 9750 +F 0 "U9" H 7050 9650 60 0000 C CNN +F 1 "d_inverter" H 7050 9900 60 0000 C CNN +F 2 "" H 7100 9700 60 0000 C CNN +F 3 "" H 7100 9700 60 0000 C CNN + 1 7050 9750 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 7550 9050 7500 9050 +Wire Wire Line + 7500 9050 7500 9400 +Wire Wire Line + 7500 9400 7550 9400 +Wire Wire Line + 7950 9050 8000 9050 +Wire Wire Line + 8000 9050 8000 9400 +Wire Wire Line + 8000 9400 7950 9400 +Wire Wire Line + 7450 9150 7600 9150 +Wire Wire Line + 7900 9300 8100 9300 +Wire Wire Line + 7750 8650 7750 8750 +Wire Wire Line + 6600 8650 6550 8650 +Wire Wire Line + 7750 9700 7750 9850 +Connection ~ 7500 9300 +Wire Wire Line + 7500 9300 7100 9300 +Wire Wire Line + 6550 9450 7050 9450 +Wire Wire Line + 6550 8650 6550 9450 +$Comp +L dac_bridge_1 U10 +U 1 1 685B15D1 +P 7200 8700 +F 0 "U10" H 7200 8700 60 0000 C CNN +F 1 "dac_bridge_1" H 7200 8850 60 0000 C CNN +F 2 "" H 7200 8700 60 0000 C CNN +F 3 "" H 7200 8700 60 0000 C CNN + 1 7200 8700 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U16 +U 1 1 685B15D7 +P 8000 10150 +F 0 "U16" H 8000 10150 60 0000 C CNN +F 1 "dac_bridge_1" H 8000 10300 60 0000 C CNN +F 2 "" H 8000 10150 60 0000 C CNN +F 3 "" H 8000 10150 60 0000 C CNN + 1 8000 10150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7750 9850 8550 9850 +Wire Wire Line + 8550 9850 8550 10100 +Wire Wire Line + 7050 10050 7050 10100 +Wire Wire Line + 7050 10100 7400 10100 +$Comp +L mosfet_n M14 +U 1 1 685B15E1 +P 10500 9600 +F 0 "M14" H 10500 9450 50 0000 R CNN +F 1 "mosfet_n" H 10600 9550 50 0000 R CNN +F 2 "" H 10800 9300 29 0000 C CNN +F 3 "" H 10600 9400 60 0000 C CNN + 1 10500 9600 + 0 -1 -1 0 +$EndComp +$Comp +L mosfet_p M16 +U 1 1 685B15E7 +P 10700 8900 +F 0 "M16" H 10650 8950 50 0000 R CNN +F 1 "mosfet_p" H 10750 9050 50 0000 R CNN +F 2 "" H 10950 9000 29 0000 C CNN +F 3 "" H 10750 8900 60 0000 C CNN + 1 10700 8900 + 0 1 1 0 +$EndComp +Text GLabel 10400 9150 0 60 Input ~ 0 +VCC +Text GLabel 11050 9300 2 60 Input ~ 0 +GND +$Comp +L d_inverter U25 +U 1 1 685B15EF +P 10000 9750 +F 0 "U25" H 10000 9650 60 0000 C CNN +F 1 "d_inverter" H 10000 9900 60 0000 C CNN +F 2 "" H 10050 9700 60 0000 C CNN +F 3 "" H 10050 9700 60 0000 C CNN + 1 10000 9750 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 10500 9050 10450 9050 +Wire Wire Line + 10450 9050 10450 9400 +Wire Wire Line + 10450 9400 10500 9400 +Wire Wire Line + 10900 9050 10950 9050 +Wire Wire Line + 10950 9050 10950 9400 +Wire Wire Line + 10950 9400 10900 9400 +Wire Wire Line + 10400 9150 10550 9150 +Wire Wire Line + 10850 9300 11050 9300 +Wire Wire Line + 10700 8650 10700 8750 +Wire Wire Line + 9550 8650 9500 8650 +Wire Wire Line + 10700 9700 10700 9850 +Connection ~ 10450 9300 +Wire Wire Line + 10450 9300 10050 9300 +Wire Wire Line + 9500 9450 10000 9450 +Wire Wire Line + 9500 8650 9500 9450 +$Comp +L dac_bridge_1 U26 +U 1 1 685B1604 +P 10150 8700 +F 0 "U26" H 10150 8700 60 0000 C CNN +F 1 "dac_bridge_1" H 10150 8850 60 0000 C CNN +F 2 "" H 10150 8700 60 0000 C CNN +F 3 "" H 10150 8700 60 0000 C CNN + 1 10150 8700 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U30 +U 1 1 685B160A +P 10950 10150 +F 0 "U30" H 10950 10150 60 0000 C CNN +F 1 "dac_bridge_1" H 10950 10300 60 0000 C CNN +F 2 "" H 10950 10150 60 0000 C CNN +F 3 "" H 10950 10150 60 0000 C CNN + 1 10950 10150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10700 9850 11500 9850 +Wire Wire Line + 11500 9850 11500 10100 +Wire Wire Line + 10000 10050 10000 10100 +Wire Wire Line + 10000 10100 10350 10100 +$Comp +L d_and U17 +U 1 1 685B173C +P 8550 10950 +F 0 "U17" H 8550 10950 60 0000 C CNN +F 1 "d_and" H 8600 11050 60 0000 C CNN +F 2 "" H 8550 10950 60 0000 C CNN +F 3 "" H 8550 10950 60 0000 C CNN + 1 8550 10950 + 0 -1 -1 0 +$EndComp +$Comp +L d_and U18 +U 1 1 685B18F2 +P 9550 10900 +F 0 "U18" H 9550 10900 60 0000 C CNN +F 1 "d_and" H 9600 11000 60 0000 C CNN +F 2 "" H 9550 10900 60 0000 C CNN +F 3 "" H 9550 10900 60 0000 C CNN + 1 9550 10900 + 0 -1 -1 0 +$EndComp +$Comp +L d_inverter U11 +U 1 1 685B1A2A +P 7600 11600 +F 0 "U11" H 7600 11500 60 0000 C CNN +F 1 "d_inverter" H 7600 11750 60 0000 C CNN +F 2 "" H 7650 11550 60 0000 C CNN +F 3 "" H 7650 11550 60 0000 C CNN + 1 7600 11600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U12 +U 1 1 685B1C6E +P 7600 12100 +F 0 "U12" H 7600 12000 60 0000 C CNN +F 1 "d_inverter" H 7600 12250 60 0000 C CNN +F 2 "" H 7650 12050 60 0000 C CNN +F 3 "" H 7650 12050 60 0000 C CNN + 1 7600 12100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7900 12100 9550 12100 +Wire Wire Line + 9550 12100 9550 11350 +Wire Wire Line + 8550 11400 8550 12100 +Connection ~ 8550 12100 +Wire Wire Line + 7900 11600 8450 11600 +Wire Wire Line + 8450 11600 8450 11400 +Wire Wire Line + 7050 11600 7300 11600 +Wire Wire Line + 7250 11600 7250 11800 +Wire Wire Line + 7250 11800 9450 11800 +Wire Wire Line + 9450 11800 9450 11350 +Connection ~ 7250 11600 +$Comp +L adc_bridge_2 U2 +U 1 1 685B2D14 +P 6500 11850 +F 0 "U2" H 6500 11850 60 0000 C CNN +F 1 "adc_bridge_2" H 6500 12000 60 0000 C CNN +F 2 "" H 6500 11850 60 0000 C CNN +F 3 "" H 6500 11850 60 0000 C CNN + 1 6500 11850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7050 11800 7050 11600 +Wire Wire Line + 7050 11900 7050 12100 +Wire Wire Line + 7050 12100 7300 12100 +Wire Wire Line + 7250 10100 7250 10500 +Wire Wire Line + 6200 10500 8500 10500 +Connection ~ 7250 10100 +Wire Wire Line + 6200 10500 6200 4050 +Connection ~ 6700 4050 +Connection ~ 7250 10500 +Wire Wire Line + 7000 6050 7000 6250 +Wire Wire Line + 7000 6250 6200 6250 +Connection ~ 6200 6250 +Connection ~ 7000 6050 +Wire Wire Line + 7050 8100 7050 8350 +Wire Wire Line + 7050 8350 6200 8350 +Connection ~ 6200 8350 +Connection ~ 7050 8100 +Wire Wire Line + 9500 10450 9500 9900 +Wire Wire Line + 9500 9900 9100 9900 +Wire Wire Line + 9100 9900 9100 4050 +Connection ~ 9650 4050 +Wire Wire Line + 9900 6050 9900 6250 +Wire Wire Line + 9900 6250 9100 6250 +Connection ~ 9100 6250 +Connection ~ 9900 6050 +Wire Wire Line + 10000 8100 10000 8250 +Wire Wire Line + 10000 8250 9100 8250 +Connection ~ 9100 8250 +Connection ~ 10000 8100 +Wire Wire Line + 10100 10100 10100 10250 +Wire Wire Line + 10100 10250 9500 10250 +Connection ~ 9500 10250 +Connection ~ 10100 10100 +Wire Wire Line + 5900 11800 5650 11800 +Wire Wire Line + 5900 11900 5650 11900 +$Comp +L d_buffer U35 +U 1 1 685B5C93 +P 12750 3100 +F 0 "U35" H 12750 3050 60 0000 C CNN +F 1 "d_buffer" H 12750 3150 60 0000 C CNN +F 2 "" H 12750 3100 60 0000 C CNN +F 3 "" H 12750 3100 60 0000 C CNN + 1 12750 3100 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_1 U31 +U 1 1 685B5D63 +P 11650 3150 +F 0 "U31" H 11650 3150 60 0000 C CNN +F 1 "adc_bridge_1" H 11650 3300 60 0000 C CNN +F 2 "" H 11650 3150 60 0000 C CNN +F 3 "" H 11650 3150 60 0000 C CNN + 1 11650 3150 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U39 +U 1 1 685B5DEA +P 14050 3150 +F 0 "U39" H 14050 3150 60 0000 C CNN +F 1 "dac_bridge_1" H 14050 3300 60 0000 C CNN +F 2 "" H 14050 3150 60 0000 C CNN +F 3 "" H 14050 3150 60 0000 C CNN + 1 14050 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 12200 3100 12250 3100 +Wire Wire Line + 13400 3100 13450 3100 +$Comp +L d_buffer U38 +U 1 1 685B6D2E +P 12850 5000 +F 0 "U38" H 12850 4950 60 0000 C CNN +F 1 "d_buffer" H 12850 5050 60 0000 C CNN +F 2 "" H 12850 5000 60 0000 C CNN +F 3 "" H 12850 5000 60 0000 C CNN + 1 12850 5000 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_1 U34 +U 1 1 685B6D34 +P 11750 5050 +F 0 "U34" H 11750 5050 60 0000 C CNN +F 1 "adc_bridge_1" H 11750 5200 60 0000 C CNN +F 2 "" H 11750 5050 60 0000 C CNN +F 3 "" H 11750 5050 60 0000 C CNN + 1 11750 5050 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U42 +U 1 1 685B6D3A +P 14150 5050 +F 0 "U42" H 14150 5050 60 0000 C CNN +F 1 "dac_bridge_1" H 14150 5200 60 0000 C CNN +F 2 "" H 14150 5050 60 0000 C CNN +F 3 "" H 14150 5050 60 0000 C CNN + 1 14150 5050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 12300 5000 12350 5000 +Wire Wire Line + 13500 5000 13550 5000 +$Comp +L d_buffer U36 +U 1 1 685B7CEC +P 12750 7050 +F 0 "U36" H 12750 7000 60 0000 C CNN +F 1 "d_buffer" H 12750 7100 60 0000 C CNN +F 2 "" H 12750 7050 60 0000 C CNN +F 3 "" H 12750 7050 60 0000 C CNN + 1 12750 7050 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_1 U32 +U 1 1 685B7CF2 +P 11650 7100 +F 0 "U32" H 11650 7100 60 0000 C CNN +F 1 "adc_bridge_1" H 11650 7250 60 0000 C CNN +F 2 "" H 11650 7100 60 0000 C CNN +F 3 "" H 11650 7100 60 0000 C CNN + 1 11650 7100 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U40 +U 1 1 685B7CF8 +P 14050 7100 +F 0 "U40" H 14050 7100 60 0000 C CNN +F 1 "dac_bridge_1" H 14050 7250 60 0000 C CNN +F 2 "" H 14050 7100 60 0000 C CNN +F 3 "" H 14050 7100 60 0000 C CNN + 1 14050 7100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 12200 7050 12250 7050 +Wire Wire Line + 13400 7050 13450 7050 +$Comp +L d_buffer U37 +U 1 1 685B816E +P 12800 9050 +F 0 "U37" H 12800 9000 60 0000 C CNN +F 1 "d_buffer" H 12800 9100 60 0000 C CNN +F 2 "" H 12800 9050 60 0000 C CNN +F 3 "" H 12800 9050 60 0000 C CNN + 1 12800 9050 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_1 U33 +U 1 1 685B8174 +P 11700 9100 +F 0 "U33" H 11700 9100 60 0000 C CNN +F 1 "adc_bridge_1" H 11700 9250 60 0000 C CNN +F 2 "" H 11700 9100 60 0000 C CNN +F 3 "" H 11700 9100 60 0000 C CNN + 1 11700 9100 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U41 +U 1 1 685B817A +P 14100 9100 +F 0 "U41" H 14100 9100 60 0000 C CNN +F 1 "dac_bridge_1" H 14100 9250 60 0000 C CNN +F 2 "" H 14100 9100 60 0000 C CNN +F 3 "" H 14100 9100 60 0000 C CNN + 1 14100 9100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 12250 9050 12300 9050 +Wire Wire Line + 13450 9050 13500 9050 +Wire Wire Line + 11050 3100 10600 3100 +Connection ~ 10600 3100 +Wire Wire Line + 11150 5000 10950 5000 +Wire Wire Line + 10950 5000 10950 5100 +Wire Wire Line + 10950 5100 10750 5100 +Connection ~ 10750 5100 +Wire Wire Line + 11050 7050 11050 7150 +Wire Wire Line + 11050 7150 10800 7150 +Connection ~ 10800 7150 +Wire Wire Line + 11100 9050 11100 9150 +Wire Wire Line + 11100 9150 10950 9150 +Connection ~ 10950 9150 +Wire Wire Line + 10900 3100 10900 2350 +Wire Wire Line + 10900 2350 7850 2350 +Wire Wire Line + 7850 2350 7850 3150 +Wire Wire Line + 7850 3150 7650 3150 +Connection ~ 7650 3150 +Connection ~ 10900 3100 +Wire Wire Line + 11050 5000 11050 4350 +Wire Wire Line + 11050 4350 8100 4350 +Wire Wire Line + 8100 4350 8100 5100 +Wire Wire Line + 8100 5100 7800 5100 +Connection ~ 7800 5100 +Connection ~ 11050 5000 +Wire Wire Line + 10950 7150 10950 6350 +Wire Wire Line + 10950 6350 8100 6350 +Wire Wire Line + 8100 6350 8100 7150 +Wire Wire Line + 8100 7150 7850 7150 +Connection ~ 7850 7150 +Connection ~ 10950 7150 +Wire Wire Line + 11050 9150 11050 8400 +Wire Wire Line + 11050 8400 8200 8400 +Wire Wire Line + 8200 8400 8200 9150 +Wire Wire Line + 8200 9150 8000 9150 +Connection ~ 8000 9150 +Connection ~ 11050 9150 +Wire Wire Line + 10250 5250 9850 5250 +Wire Wire Line + 7300 5250 6900 5250 +Wire Wire Line + 10100 3250 9700 3250 +Wire Wire Line + 7150 3250 6750 3250 +$Comp +L PORT U1 +U 5 1 685BC890 +P 6650 5250 +F 0 "U1" H 6700 5350 30 0000 C CNN +F 1 "PORT" H 6650 5250 30 0000 C CNN +F 2 "" H 6650 5250 60 0000 C CNN +F 3 "" H 6650 5250 60 0000 C CNN + 5 6650 5250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 685BC931 +P 15000 7050 +F 0 "U1" H 15050 7150 30 0000 C CNN +F 1 "PORT" H 15000 7050 30 0000 C CNN +F 2 "" H 15000 7050 60 0000 C CNN +F 3 "" H 15000 7050 60 0000 C CNN + 9 15000 7050 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 685BCB1F +P 9600 5250 +F 0 "U1" H 9650 5350 30 0000 C CNN +F 1 "PORT" H 9600 5250 30 0000 C CNN +F 2 "" H 9600 5250 60 0000 C CNN +F 3 "" H 9600 5250 60 0000 C CNN + 6 9600 5250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 685BCC3C +P 9650 7300 +F 0 "U1" H 9700 7400 30 0000 C CNN +F 1 "PORT" H 9650 7300 30 0000 C CNN +F 2 "" H 9650 7300 60 0000 C CNN +F 3 "" H 9650 7300 60 0000 C CNN + 10 9650 7300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 685BCF32 +P 15050 5000 +F 0 "U1" H 15100 5100 30 0000 C CNN +F 1 "PORT" H 15050 5000 30 0000 C CNN +F 2 "" H 15050 5000 60 0000 C CNN +F 3 "" H 15050 5000 60 0000 C CNN + 7 15050 5000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 685BD1B5 +P 6700 7300 +F 0 "U1" H 6750 7400 30 0000 C CNN +F 1 "PORT" H 6700 7300 30 0000 C CNN +F 2 "" H 6700 7300 60 0000 C CNN +F 3 "" H 6700 7300 60 0000 C CNN + 11 6700 7300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 685BD619 +P 5550 4450 +F 0 "U1" H 5600 4550 30 0000 C CNN +F 1 "PORT" H 5550 4450 30 0000 C CNN +F 2 "" H 5550 4450 60 0000 C CNN +F 3 "" H 5550 4450 60 0000 C CNN + 8 5550 4450 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 685BD820 +P 15000 9050 +F 0 "U1" H 15050 9150 30 0000 C CNN +F 1 "PORT" H 15000 9050 30 0000 C CNN +F 2 "" H 15000 9050 60 0000 C CNN +F 3 "" H 15000 9050 60 0000 C CNN + 12 15000 9050 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 685BDC4E +P 9450 3250 +F 0 "U1" H 9500 3350 30 0000 C CNN +F 1 "PORT" H 9450 3250 30 0000 C CNN +F 2 "" H 9450 3250 60 0000 C CNN +F 3 "" H 9450 3250 60 0000 C CNN + 3 9450 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 685BDE89 +P 14950 3100 +F 0 "U1" H 15000 3200 30 0000 C CNN +F 1 "PORT" H 14950 3100 30 0000 C CNN +F 2 "" H 14950 3100 60 0000 C CNN +F 3 "" H 14950 3100 60 0000 C CNN + 4 14950 3100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 685BE422 +P 9800 9300 +F 0 "U1" H 9850 9400 30 0000 C CNN +F 1 "PORT" H 9800 9300 30 0000 C CNN +F 2 "" H 9800 9300 60 0000 C CNN +F 3 "" H 9800 9300 60 0000 C CNN + 13 9800 9300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 685BE4EF +P 5550 4150 +F 0 "U1" H 5600 4250 30 0000 C CNN +F 1 "PORT" H 5550 4150 30 0000 C CNN +F 2 "" H 5550 4150 60 0000 C CNN +F 3 "" H 5550 4150 60 0000 C CNN + 16 5550 4150 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 15 1 685BE5C2 +P 5650 12150 +F 0 "U1" H 5700 12250 30 0000 C CNN +F 1 "PORT" H 5650 12150 30 0000 C CNN +F 2 "" H 5650 12150 60 0000 C CNN +F 3 "" H 5650 12150 60 0000 C CNN + 15 5650 12150 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 14 1 685BEEF7 +P 6850 9300 +F 0 "U1" H 6900 9400 30 0000 C CNN +F 1 "PORT" H 6850 9300 30 0000 C CNN +F 2 "" H 6850 9300 60 0000 C CNN +F 3 "" H 6850 9300 60 0000 C CNN + 14 6850 9300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 14600 3100 14700 3100 +Wire Wire Line + 14700 5000 14800 5000 +Wire Wire Line + 14600 7050 14750 7050 +Wire Wire Line + 14650 9050 14750 9050 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3257/SN74CBTLV3257.sub b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3257/SN74CBTLV3257.sub new file mode 100644 index 000000000..f35f21e40 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3257/SN74CBTLV3257.sub @@ -0,0 +1,188 @@ +* Subcircuit SN74CBTLV3257 +.subckt SN74CBTLV3257 net-_u1-pad1_ net-_m1-pad1_ net-_m11-pad3_ net-_u1-pad4_ net-_m2-pad1_ net-_m10-pad1_ net-_u1-pad7_ gnd net-_u1-pad9_ net-_m12-pad1_ net-_m4-pad1_ net-_u1-pad12_ net-_m14-pad1_ net-_m6-pad1_ net-_u1-pad15_ vcc +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\sn74cbtlv3257\sn74cbtlv3257.cir +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1 +m3 net-_m1-pad3_ net-_m3-pad2_ net-_m1-pad1_ vcc CMOSP W=100u L=100u M=1 +* u3 net-_u13-pad1_ net-_u3-pad2_ d_inverter +* u4 net-_u3-pad2_ net-_m3-pad2_ dac_bridge_1 +* u13 net-_u13-pad1_ net-_m1-pad2_ dac_bridge_1 +m9 net-_m11-pad3_ net-_m9-pad2_ net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1 +m11 net-_m1-pad3_ net-_m11-pad2_ net-_m11-pad3_ vcc CMOSP W=100u L=100u M=1 +* u19 net-_u18-pad3_ net-_u19-pad2_ d_inverter +* u20 net-_u19-pad2_ net-_m11-pad2_ dac_bridge_1 +* u27 net-_u18-pad3_ net-_m9-pad2_ dac_bridge_1 +m2 net-_m2-pad1_ net-_m2-pad2_ net-_m10-pad3_ gnd CMOSN W=100u L=100u M=1 +m5 net-_m10-pad3_ net-_m5-pad2_ net-_m2-pad1_ vcc CMOSP W=100u L=100u M=1 +* u5 net-_u13-pad1_ net-_u5-pad2_ d_inverter +* u7 net-_u5-pad2_ net-_m5-pad2_ dac_bridge_1 +* u14 net-_u13-pad1_ net-_m2-pad2_ dac_bridge_1 +m10 net-_m10-pad1_ net-_m10-pad2_ net-_m10-pad3_ gnd CMOSN W=100u L=100u M=1 +m13 net-_m10-pad3_ net-_m13-pad2_ net-_m10-pad1_ vcc CMOSP W=100u L=100u M=1 +* u21 net-_u18-pad3_ net-_u21-pad2_ d_inverter +* u23 net-_u21-pad2_ net-_m13-pad2_ dac_bridge_1 +* u28 net-_u18-pad3_ net-_m10-pad2_ dac_bridge_1 +m4 net-_m4-pad1_ net-_m4-pad2_ net-_m12-pad3_ gnd CMOSN W=100u L=100u M=1 +m7 net-_m12-pad3_ net-_m7-pad2_ net-_m4-pad1_ vcc CMOSP W=100u L=100u M=1 +* u6 net-_u13-pad1_ net-_u6-pad2_ d_inverter +* u8 net-_u6-pad2_ net-_m7-pad2_ dac_bridge_1 +* u15 net-_u13-pad1_ net-_m4-pad2_ dac_bridge_1 +m12 net-_m12-pad1_ net-_m12-pad2_ net-_m12-pad3_ gnd CMOSN W=100u L=100u M=1 +m15 net-_m12-pad3_ net-_m15-pad2_ net-_m12-pad1_ vcc CMOSP W=100u L=100u M=1 +* u22 net-_u18-pad3_ net-_u22-pad2_ d_inverter +* u24 net-_u22-pad2_ net-_m15-pad2_ dac_bridge_1 +* u29 net-_u18-pad3_ net-_m12-pad2_ dac_bridge_1 +m6 net-_m6-pad1_ net-_m6-pad2_ net-_m14-pad3_ gnd CMOSN W=100u L=100u M=1 +m8 net-_m14-pad3_ net-_m8-pad2_ net-_m6-pad1_ vcc CMOSP W=100u L=100u M=1 +* u9 net-_u13-pad1_ net-_u10-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_m8-pad2_ dac_bridge_1 +* u16 net-_u13-pad1_ net-_m6-pad2_ dac_bridge_1 +m14 net-_m14-pad1_ net-_m14-pad2_ net-_m14-pad3_ gnd CMOSN W=100u L=100u M=1 +m16 net-_m14-pad3_ net-_m16-pad2_ net-_m14-pad1_ vcc CMOSP W=100u L=100u M=1 +* u25 net-_u18-pad3_ net-_u25-pad2_ d_inverter +* u26 net-_u25-pad2_ net-_m16-pad2_ dac_bridge_1 +* u30 net-_u18-pad3_ net-_m14-pad2_ dac_bridge_1 +* u17 net-_u11-pad2_ net-_u12-pad2_ net-_u13-pad1_ d_and +* u18 net-_u11-pad1_ net-_u12-pad2_ net-_u18-pad3_ d_and +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u2 net-_u1-pad1_ net-_u1-pad15_ net-_u11-pad1_ net-_u12-pad1_ adc_bridge_2 +* u35 net-_u31-pad2_ net-_u35-pad2_ d_buffer +* u31 net-_m1-pad3_ net-_u31-pad2_ adc_bridge_1 +* u39 net-_u35-pad2_ net-_u1-pad4_ dac_bridge_1 +* u38 net-_u34-pad2_ net-_u38-pad2_ d_buffer +* u34 net-_m10-pad3_ net-_u34-pad2_ adc_bridge_1 +* u42 net-_u38-pad2_ net-_u1-pad7_ dac_bridge_1 +* u36 net-_u32-pad2_ net-_u36-pad2_ d_buffer +* u32 net-_m12-pad3_ net-_u32-pad2_ adc_bridge_1 +* u40 net-_u36-pad2_ net-_u1-pad9_ dac_bridge_1 +* u37 net-_u33-pad2_ net-_u37-pad2_ d_buffer +* u33 net-_m14-pad3_ net-_u33-pad2_ adc_bridge_1 +* u41 net-_u37-pad2_ net-_u1-pad12_ dac_bridge_1 +a1 net-_u13-pad1_ net-_u3-pad2_ u3 +a2 [net-_u3-pad2_ ] [net-_m3-pad2_ ] u4 +a3 [net-_u13-pad1_ ] [net-_m1-pad2_ ] u13 +a4 net-_u18-pad3_ net-_u19-pad2_ u19 +a5 [net-_u19-pad2_ ] [net-_m11-pad2_ ] u20 +a6 [net-_u18-pad3_ ] [net-_m9-pad2_ ] u27 +a7 net-_u13-pad1_ net-_u5-pad2_ u5 +a8 [net-_u5-pad2_ ] [net-_m5-pad2_ ] u7 +a9 [net-_u13-pad1_ ] [net-_m2-pad2_ ] u14 +a10 net-_u18-pad3_ net-_u21-pad2_ u21 +a11 [net-_u21-pad2_ ] [net-_m13-pad2_ ] u23 +a12 [net-_u18-pad3_ ] [net-_m10-pad2_ ] u28 +a13 net-_u13-pad1_ net-_u6-pad2_ u6 +a14 [net-_u6-pad2_ ] [net-_m7-pad2_ ] u8 +a15 [net-_u13-pad1_ ] [net-_m4-pad2_ ] u15 +a16 net-_u18-pad3_ net-_u22-pad2_ u22 +a17 [net-_u22-pad2_ ] [net-_m15-pad2_ ] u24 +a18 [net-_u18-pad3_ ] [net-_m12-pad2_ ] u29 +a19 net-_u13-pad1_ net-_u10-pad1_ u9 +a20 [net-_u10-pad1_ ] [net-_m8-pad2_ ] u10 +a21 [net-_u13-pad1_ ] [net-_m6-pad2_ ] u16 +a22 net-_u18-pad3_ net-_u25-pad2_ u25 +a23 [net-_u25-pad2_ ] [net-_m16-pad2_ ] u26 +a24 [net-_u18-pad3_ ] [net-_m14-pad2_ ] u30 +a25 [net-_u11-pad2_ net-_u12-pad2_ ] net-_u13-pad1_ u17 +a26 [net-_u11-pad1_ net-_u12-pad2_ ] net-_u18-pad3_ u18 +a27 net-_u11-pad1_ net-_u11-pad2_ u11 +a28 net-_u12-pad1_ net-_u12-pad2_ u12 +a29 [net-_u1-pad1_ net-_u1-pad15_ ] [net-_u11-pad1_ net-_u12-pad1_ ] u2 +a30 net-_u31-pad2_ net-_u35-pad2_ u35 +a31 [net-_m1-pad3_ ] [net-_u31-pad2_ ] u31 +a32 [net-_u35-pad2_ ] [net-_u1-pad4_ ] u39 +a33 net-_u34-pad2_ net-_u38-pad2_ u38 +a34 [net-_m10-pad3_ ] [net-_u34-pad2_ ] u34 +a35 [net-_u38-pad2_ ] [net-_u1-pad7_ ] u42 +a36 net-_u32-pad2_ net-_u36-pad2_ u36 +a37 [net-_m12-pad3_ ] [net-_u32-pad2_ ] u32 +a38 [net-_u36-pad2_ ] [net-_u1-pad9_ ] u40 +a39 net-_u33-pad2_ net-_u37-pad2_ u37 +a40 [net-_m14-pad3_ ] [net-_u33-pad2_ ] u33 +a41 [net-_u37-pad2_ ] [net-_u1-pad12_ ] u41 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u4 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u13 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u20 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u27 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u7 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u14 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u23 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u28 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u8 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u15 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u24 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u29 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u10 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u16 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u26 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u30 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u35 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u31 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u39 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u38 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u34 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u42 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u36 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u32 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u40 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u37 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u33 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u41 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Control Statements + +.ends SN74CBTLV3257 \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3257/SN74CBTLV3257_Previous_Values.xml b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3257/SN74CBTLV3257_Previous_Values.xml new file mode 100644 index 000000000..125a6153a --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3257/SN74CBTLV3257_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_inverterdac_bridgedac_bridged_inverterdac_bridgedac_bridged_inverterdac_bridgedac_bridged_inverterdac_bridgedac_bridged_inverterdac_bridgedac_bridged_inverterdac_bridgedac_bridged_inverterdac_bridgedac_bridged_inverterdac_bridgedac_bridged_andd_andd_inverterd_inverteradc_bridged_bufferadc_bridgedac_bridged_bufferadc_bridgedac_bridged_bufferadc_bridgedac_bridged_bufferadc_bridgedac_bridgeC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3257/analysis b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3257/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74CBTLV3257/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74HC377/SN74HC377-cache.lib b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74HC377/SN74HC377-cache.lib new file mode 100644 index 000000000..c1edd7a32 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74HC377/SN74HC377-cache.lib @@ -0,0 +1,123 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_buffer +# +DEF d_buffer U 0 40 Y Y 1 F N +F0 "U" 0 -50 60 H V C CNN +F1 "d_buffer" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N +X IN 1 -500 0 200 R 50 50 1 1 I +X OUT 2 650 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# risingedge_dflipflop +# +DEF risingedge_dflipflop U 0 40 Y Y 1 F N +F0 "U" 2850 1800 60 H V C CNN +F1 "risingedge_dflipflop" 2850 2000 60 H V C CNN +F2 "" 2850 1950 60 H V C CNN +F3 "" 2850 1950 60 H V C CNN +DRAW +S 2350 2100 3350 1600 0 1 0 N +X D0 1 2150 1900 200 R 50 50 1 1 I +X clk0 2 2150 1800 200 R 50 50 1 1 I +X Q0 3 3550 1900 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74HC377/SN74HC377.cir b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74HC377/SN74HC377.cir new file mode 100644 index 000000000..574327140 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74HC377/SN74HC377.cir @@ -0,0 +1,26 @@ +* C:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\SN74HC377\SN74HC377.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/02/25 14:55:03 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U10 Net-_U1-Pad1_ Net-_U10-Pad2_ d_inverter +U12 Net-_U10-Pad2_ Net-_U12-Pad2_ d_inverter +U14 Net-_U12-Pad2_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_nor +U11 Net-_U1-Pad18_ Net-_U11-Pad2_ d_inverter +U13 Net-_U11-Pad2_ Net-_U13-Pad2_ d_buffer +U15 Net-_U14-Pad3_ Net-_U13-Pad2_ Net-_U14-Pad2_ d_nor +U16 Net-_U14-Pad3_ Net-_U1-Pad18_ Net-_U16-Pad3_ d_and +U2 Net-_U1-Pad2_ Net-_U16-Pad3_ Net-_U1-Pad17_ risingedge_dflipflop +U3 Net-_U1-Pad3_ Net-_U16-Pad3_ Net-_U1-Pad16_ risingedge_dflipflop +U4 Net-_U1-Pad4_ Net-_U16-Pad3_ Net-_U1-Pad15_ risingedge_dflipflop +U5 Net-_U1-Pad5_ Net-_U16-Pad3_ Net-_U1-Pad14_ risingedge_dflipflop +U6 Net-_U1-Pad6_ Net-_U16-Pad3_ Net-_U1-Pad13_ risingedge_dflipflop +U7 Net-_U1-Pad7_ Net-_U16-Pad3_ Net-_U1-Pad12_ risingedge_dflipflop +U8 Net-_U1-Pad8_ Net-_U16-Pad3_ Net-_U1-Pad11_ risingedge_dflipflop +U9 Net-_U1-Pad9_ Net-_U16-Pad3_ Net-_U1-Pad10_ risingedge_dflipflop +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ PORT + +.end diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74HC377/SN74HC377.cir.out b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74HC377/SN74HC377.cir.out new file mode 100644 index 000000000..23a4f2852 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74HC377/SN74HC377.cir.out @@ -0,0 +1,72 @@ +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\sn74hc377\sn74hc377.cir + +* u10 net-_u1-pad1_ net-_u10-pad2_ d_inverter +* u12 net-_u10-pad2_ net-_u12-pad2_ d_inverter +* u14 net-_u12-pad2_ net-_u14-pad2_ net-_u14-pad3_ d_nor +* u11 net-_u1-pad18_ net-_u11-pad2_ d_inverter +* u13 net-_u11-pad2_ net-_u13-pad2_ d_buffer +* u15 net-_u14-pad3_ net-_u13-pad2_ net-_u14-pad2_ d_nor +* u16 net-_u14-pad3_ net-_u1-pad18_ net-_u16-pad3_ d_and +* u2 net-_u1-pad2_ net-_u16-pad3_ net-_u1-pad17_ risingedge_dflipflop +* u3 net-_u1-pad3_ net-_u16-pad3_ net-_u1-pad16_ risingedge_dflipflop +* u4 net-_u1-pad4_ net-_u16-pad3_ net-_u1-pad15_ risingedge_dflipflop +* u5 net-_u1-pad5_ net-_u16-pad3_ net-_u1-pad14_ risingedge_dflipflop +* u6 net-_u1-pad6_ net-_u16-pad3_ net-_u1-pad13_ risingedge_dflipflop +* u7 net-_u1-pad7_ net-_u16-pad3_ net-_u1-pad12_ risingedge_dflipflop +* u8 net-_u1-pad8_ net-_u16-pad3_ net-_u1-pad11_ risingedge_dflipflop +* u9 net-_u1-pad9_ net-_u16-pad3_ net-_u1-pad10_ risingedge_dflipflop +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ port +a1 net-_u1-pad1_ net-_u10-pad2_ u10 +a2 net-_u10-pad2_ net-_u12-pad2_ u12 +a3 [net-_u12-pad2_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a4 net-_u1-pad18_ net-_u11-pad2_ u11 +a5 net-_u11-pad2_ net-_u13-pad2_ u13 +a6 [net-_u14-pad3_ net-_u13-pad2_ ] net-_u14-pad2_ u15 +a7 [net-_u14-pad3_ net-_u1-pad18_ ] net-_u16-pad3_ u16 +a8 [net-_u1-pad2_ ] [net-_u16-pad3_ ] [net-_u1-pad17_ ] u2 +a9 [net-_u1-pad3_ ] [net-_u16-pad3_ ] [net-_u1-pad16_ ] u3 +a10 [net-_u1-pad4_ ] [net-_u16-pad3_ ] [net-_u1-pad15_ ] u4 +a11 [net-_u1-pad5_ ] [net-_u16-pad3_ ] [net-_u1-pad14_ ] u5 +a12 [net-_u1-pad6_ ] [net-_u16-pad3_ ] [net-_u1-pad13_ ] u6 +a13 [net-_u1-pad7_ ] [net-_u16-pad3_ ] [net-_u1-pad12_ ] u7 +a14 [net-_u1-pad8_ ] [net-_u16-pad3_ ] [net-_u1-pad11_ ] u8 +a15 [net-_u1-pad9_ ] [net-_u16-pad3_ ] [net-_u1-pad10_ ] u9 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u14 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u13 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u15 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u2 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u3 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u4 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u5 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u6 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u7 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u8 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u9 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74HC377/SN74HC377.pro b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74HC377/SN74HC377.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74HC377/SN74HC377.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74HC377/SN74HC377.sch b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74HC377/SN74HC377.sch new file mode 100644 index 000000000..ee033d08e --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74HC377/SN74HC377.sch @@ -0,0 +1,530 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U10 +U 1 1 683D649F +P 3200 700 +F 0 "U10" H 3200 600 60 0000 C CNN +F 1 "d_inverter" H 3200 850 60 0000 C CNN +F 2 "" H 3250 650 60 0000 C CNN +F 3 "" H 3250 650 60 0000 C CNN + 1 3200 700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U12 +U 1 1 683D64E2 +P 4000 700 +F 0 "U12" H 4000 600 60 0000 C CNN +F 1 "d_inverter" H 4000 850 60 0000 C CNN +F 2 "" H 4050 650 60 0000 C CNN +F 3 "" H 4050 650 60 0000 C CNN + 1 4000 700 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U14 +U 1 1 683D650C +P 5350 800 +F 0 "U14" H 5350 800 60 0000 C CNN +F 1 "d_nor" H 5400 900 60 0000 C CNN +F 2 "" H 5350 800 60 0000 C CNN +F 3 "" H 5350 800 60 0000 C CNN + 1 5350 800 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U11 +U 1 1 683D6572 +P 3250 1750 +F 0 "U11" H 3250 1650 60 0000 C CNN +F 1 "d_inverter" H 3250 1900 60 0000 C CNN +F 2 "" H 3300 1700 60 0000 C CNN +F 3 "" H 3300 1700 60 0000 C CNN + 1 3250 1750 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U13 +U 1 1 683D65CE +P 4250 1750 +F 0 "U13" H 4250 1700 60 0000 C CNN +F 1 "d_buffer" H 4250 1800 60 0000 C CNN +F 2 "" H 4250 1750 60 0000 C CNN +F 3 "" H 4250 1750 60 0000 C CNN + 1 4250 1750 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U15 +U 1 1 683D6644 +P 5750 1750 +F 0 "U15" H 5750 1750 60 0000 C CNN +F 1 "d_nor" H 5800 1850 60 0000 C CNN +F 2 "" H 5750 1750 60 0000 C CNN +F 3 "" H 5750 1750 60 0000 C CNN + 1 5750 1750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U16 +U 1 1 683D66AA +P 6750 850 +F 0 "U16" H 6750 850 60 0000 C CNN +F 1 "d_and" H 6800 950 60 0000 C CNN +F 2 "" H 6750 850 60 0000 C CNN +F 3 "" H 6750 850 60 0000 C CNN + 1 6750 850 + 1 0 0 -1 +$EndComp +$Comp +L risingedge_dflipflop U2 +U 1 1 683D692D +P 2450 4350 +F 0 "U2" H 5300 6150 60 0000 C CNN +F 1 "risingedge_dflipflop" H 5300 6350 60 0000 C CNN +F 2 "" H 5300 6300 60 0000 C CNN +F 3 "" H 5300 6300 60 0000 C CNN + 1 2450 4350 + 1 0 0 -1 +$EndComp +$Comp +L risingedge_dflipflop U3 +U 1 1 683D6A64 +P 2450 4900 +F 0 "U3" H 5300 6700 60 0000 C CNN +F 1 "risingedge_dflipflop" H 5300 6900 60 0000 C CNN +F 2 "" H 5300 6850 60 0000 C CNN +F 3 "" H 5300 6850 60 0000 C CNN + 1 2450 4900 + 1 0 0 -1 +$EndComp +$Comp +L risingedge_dflipflop U4 +U 1 1 683D6AAF +P 2450 5450 +F 0 "U4" H 5300 7250 60 0000 C CNN +F 1 "risingedge_dflipflop" H 5300 7450 60 0000 C CNN +F 2 "" H 5300 7400 60 0000 C CNN +F 3 "" H 5300 7400 60 0000 C CNN + 1 2450 5450 + 1 0 0 -1 +$EndComp +$Comp +L risingedge_dflipflop U5 +U 1 1 683D6B63 +P 2450 6000 +F 0 "U5" H 5300 7800 60 0000 C CNN +F 1 "risingedge_dflipflop" H 5300 8000 60 0000 C CNN +F 2 "" H 5300 7950 60 0000 C CNN +F 3 "" H 5300 7950 60 0000 C CNN + 1 2450 6000 + 1 0 0 -1 +$EndComp +$Comp +L risingedge_dflipflop U6 +U 1 1 683D6F0D +P 2450 6600 +F 0 "U6" H 5300 8400 60 0000 C CNN +F 1 "risingedge_dflipflop" H 5300 8600 60 0000 C CNN +F 2 "" H 5300 8550 60 0000 C CNN +F 3 "" H 5300 8550 60 0000 C CNN + 1 2450 6600 + 1 0 0 -1 +$EndComp +$Comp +L risingedge_dflipflop U7 +U 1 1 683D6F13 +P 2450 7150 +F 0 "U7" H 5300 8950 60 0000 C CNN +F 1 "risingedge_dflipflop" H 5300 9150 60 0000 C CNN +F 2 "" H 5300 9100 60 0000 C CNN +F 3 "" H 5300 9100 60 0000 C CNN + 1 2450 7150 + 1 0 0 -1 +$EndComp +$Comp +L risingedge_dflipflop U8 +U 1 1 683D6F19 +P 2450 7700 +F 0 "U8" H 5300 9500 60 0000 C CNN +F 1 "risingedge_dflipflop" H 5300 9700 60 0000 C CNN +F 2 "" H 5300 9650 60 0000 C CNN +F 3 "" H 5300 9650 60 0000 C CNN + 1 2450 7700 + 1 0 0 -1 +$EndComp +$Comp +L risingedge_dflipflop U9 +U 1 1 683D6F1F +P 2450 8250 +F 0 "U9" H 5300 10050 60 0000 C CNN +F 1 "risingedge_dflipflop" H 5300 10250 60 0000 C CNN +F 2 "" H 5300 10200 60 0000 C CNN +F 3 "" H 5300 10200 60 0000 C CNN + 1 2450 8250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3500 700 3700 700 +Wire Wire Line + 4300 700 4900 700 +Wire Wire Line + 3550 1750 3750 1750 +Wire Wire Line + 4900 1750 5300 1750 +Wire Wire Line + 4900 800 4650 800 +Wire Wire Line + 4650 800 4650 1300 +Wire Wire Line + 4650 1300 6250 1300 +Wire Wire Line + 6250 1300 6250 1700 +Wire Wire Line + 6250 1700 6200 1700 +Wire Wire Line + 5800 750 6300 750 +Wire Wire Line + 5300 1650 5000 1650 +Wire Wire Line + 5000 1650 5000 1050 +Wire Wire Line + 5000 1050 6000 1050 +Wire Wire Line + 6000 1050 6000 750 +Connection ~ 6000 750 +Wire Wire Line + 7200 800 7200 2150 +Wire Wire Line + 7200 2150 4300 2150 +Wire Wire Line + 4300 2150 4300 6450 +Wire Wire Line + 4600 5350 4300 5350 +Connection ~ 4300 5350 +Wire Wire Line + 4600 4800 4300 4800 +Connection ~ 4300 4800 +Wire Wire Line + 4600 4200 4300 4200 +Connection ~ 4300 4200 +Wire Wire Line + 4600 3650 4300 3650 +Connection ~ 4300 3650 +Wire Wire Line + 4600 3100 4300 3100 +Connection ~ 4300 3100 +Wire Wire Line + 4600 2550 4300 2550 +Connection ~ 4300 2550 +Wire Wire Line + 4300 6450 4600 6450 +Wire Wire Line + 4600 5900 4300 5900 +Connection ~ 4300 5900 +$Comp +L PORT U1 +U 1 1 683D7938 +P 2350 700 +F 0 "U1" H 2400 800 30 0000 C CNN +F 1 "PORT" H 2350 700 30 0000 C CNN +F 2 "" H 2350 700 60 0000 C CNN +F 3 "" H 2350 700 60 0000 C CNN + 1 2350 700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 683D79D9 +P 3550 2450 +F 0 "U1" H 3600 2550 30 0000 C CNN +F 1 "PORT" H 3550 2450 30 0000 C CNN +F 2 "" H 3550 2450 60 0000 C CNN +F 3 "" H 3550 2450 60 0000 C CNN + 2 3550 2450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 683D7A72 +P 3500 5250 +F 0 "U1" H 3550 5350 30 0000 C CNN +F 1 "PORT" H 3500 5250 30 0000 C CNN +F 2 "" H 3500 5250 60 0000 C CNN +F 3 "" H 3500 5250 60 0000 C CNN + 7 3500 5250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 683D7AD5 +P 3500 5850 +F 0 "U1" H 3550 5950 30 0000 C CNN +F 1 "PORT" H 3500 5850 30 0000 C CNN +F 2 "" H 3500 5850 60 0000 C CNN +F 3 "" H 3500 5850 60 0000 C CNN + 8 3500 5850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 683D7B26 +P 3500 6350 +F 0 "U1" H 3550 6450 30 0000 C CNN +F 1 "PORT" H 3500 6350 30 0000 C CNN +F 2 "" H 3500 6350 60 0000 C CNN +F 3 "" H 3500 6350 60 0000 C CNN + 9 3500 6350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 683D7BF7 +P 6550 6350 +F 0 "U1" H 6600 6450 30 0000 C CNN +F 1 "PORT" H 6550 6350 30 0000 C CNN +F 2 "" H 6550 6350 60 0000 C CNN +F 3 "" H 6550 6350 60 0000 C CNN + 10 6550 6350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 683D7CD7 +P 3550 2950 +F 0 "U1" H 3600 3050 30 0000 C CNN +F 1 "PORT" H 3550 2950 30 0000 C CNN +F 2 "" H 3550 2950 60 0000 C CNN +F 3 "" H 3550 2950 60 0000 C CNN + 3 3550 2950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 683D7DFC +P 3550 3550 +F 0 "U1" H 3600 3650 30 0000 C CNN +F 1 "PORT" H 3550 3550 30 0000 C CNN +F 2 "" H 3550 3550 60 0000 C CNN +F 3 "" H 3550 3550 60 0000 C CNN + 4 3550 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 683D8010 +P 3550 4100 +F 0 "U1" H 3600 4200 30 0000 C CNN +F 1 "PORT" H 3550 4100 30 0000 C CNN +F 2 "" H 3550 4100 60 0000 C CNN +F 3 "" H 3550 4100 60 0000 C CNN + 5 3550 4100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 683D8063 +P 3500 4700 +F 0 "U1" H 3550 4800 30 0000 C CNN +F 1 "PORT" H 3500 4700 30 0000 C CNN +F 2 "" H 3500 4700 60 0000 C CNN +F 3 "" H 3500 4700 60 0000 C CNN + 6 3500 4700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 683D828E +P 6600 5800 +F 0 "U1" H 6650 5900 30 0000 C CNN +F 1 "PORT" H 6600 5800 30 0000 C CNN +F 2 "" H 6600 5800 60 0000 C CNN +F 3 "" H 6600 5800 60 0000 C CNN + 11 6600 5800 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 17 1 683D8353 +P 6550 2450 +F 0 "U1" H 6600 2550 30 0000 C CNN +F 1 "PORT" H 6550 2450 30 0000 C CNN +F 2 "" H 6550 2450 60 0000 C CNN +F 3 "" H 6550 2450 60 0000 C CNN + 17 6550 2450 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 683D83B4 +P 6550 5250 +F 0 "U1" H 6600 5350 30 0000 C CNN +F 1 "PORT" H 6550 5250 30 0000 C CNN +F 2 "" H 6550 5250 60 0000 C CNN +F 3 "" H 6550 5250 60 0000 C CNN + 12 6550 5250 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 683D8437 +P 6550 4700 +F 0 "U1" H 6600 4800 30 0000 C CNN +F 1 "PORT" H 6550 4700 30 0000 C CNN +F 2 "" H 6550 4700 60 0000 C CNN +F 3 "" H 6550 4700 60 0000 C CNN + 13 6550 4700 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 683D84D8 +P 6550 4100 +F 0 "U1" H 6600 4200 30 0000 C CNN +F 1 "PORT" H 6550 4100 30 0000 C CNN +F 2 "" H 6550 4100 60 0000 C CNN +F 3 "" H 6550 4100 60 0000 C CNN + 14 6550 4100 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 15 1 683D8681 +P 6550 3550 +F 0 "U1" H 6600 3650 30 0000 C CNN +F 1 "PORT" H 6550 3550 30 0000 C CNN +F 2 "" H 6550 3550 60 0000 C CNN +F 3 "" H 6550 3550 60 0000 C CNN + 15 6550 3550 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 18 1 683D87A4 +P 2500 1750 +F 0 "U1" H 2550 1850 30 0000 C CNN +F 1 "PORT" H 2500 1750 30 0000 C CNN +F 2 "" H 2500 1750 60 0000 C CNN +F 3 "" H 2500 1750 60 0000 C CNN + 18 2500 1750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 683D8833 +P 6600 3000 +F 0 "U1" H 6650 3100 30 0000 C CNN +F 1 "PORT" H 6600 3000 30 0000 C CNN +F 2 "" H 6600 3000 60 0000 C CNN +F 3 "" H 6600 3000 60 0000 C CNN + 16 6600 3000 + -1 0 0 -1 +$EndComp +Wire Wire Line + 2600 700 2900 700 +Wire Wire Line + 2750 1750 2950 1750 +Wire Wire Line + 3800 2450 4600 2450 +Wire Wire Line + 3800 2950 4600 2950 +Wire Wire Line + 4600 2950 4600 3000 +Wire Wire Line + 3800 3550 4600 3550 +Wire Wire Line + 3800 4100 4600 4100 +Wire Wire Line + 3750 4700 4600 4700 +Wire Wire Line + 3750 5250 4600 5250 +Wire Wire Line + 3750 5850 4600 5850 +Wire Wire Line + 4600 5850 4600 5800 +Wire Wire Line + 3750 6350 4600 6350 +Wire Wire Line + 6000 6350 6300 6350 +Wire Wire Line + 6000 5800 6350 5800 +Wire Wire Line + 6000 5250 6300 5250 +Wire Wire Line + 6000 4700 6300 4700 +Wire Wire Line + 6000 4100 6300 4100 +Wire Wire Line + 6000 3550 6300 3550 +Wire Wire Line + 6000 3000 6350 3000 +Wire Wire Line + 6000 2450 6300 2450 +Wire Wire Line + 6300 850 6150 850 +Wire Wire Line + 6150 850 6150 1200 +Wire Wire Line + 6150 1200 6400 1200 +Wire Wire Line + 6400 1200 6400 2050 +Wire Wire Line + 6400 2050 2850 2050 +Wire Wire Line + 2850 2050 2850 1750 +Connection ~ 2850 1750 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74HC377/SN74HC377.sub b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74HC377/SN74HC377.sub new file mode 100644 index 000000000..3be61862e --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74HC377/SN74HC377.sub @@ -0,0 +1,66 @@ +* Subcircuit SN74HC377 +.subckt SN74HC377 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\sn74hc377\sn74hc377.cir +* u10 net-_u1-pad1_ net-_u10-pad2_ d_inverter +* u12 net-_u10-pad2_ net-_u12-pad2_ d_inverter +* u14 net-_u12-pad2_ net-_u14-pad2_ net-_u14-pad3_ d_nor +* u11 net-_u1-pad18_ net-_u11-pad2_ d_inverter +* u13 net-_u11-pad2_ net-_u13-pad2_ d_buffer +* u15 net-_u14-pad3_ net-_u13-pad2_ net-_u14-pad2_ d_nor +* u16 net-_u14-pad3_ net-_u1-pad18_ net-_u16-pad3_ d_and +* u2 net-_u1-pad2_ net-_u16-pad3_ net-_u1-pad17_ risingedge_dflipflop +* u3 net-_u1-pad3_ net-_u16-pad3_ net-_u1-pad16_ risingedge_dflipflop +* u4 net-_u1-pad4_ net-_u16-pad3_ net-_u1-pad15_ risingedge_dflipflop +* u5 net-_u1-pad5_ net-_u16-pad3_ net-_u1-pad14_ risingedge_dflipflop +* u6 net-_u1-pad6_ net-_u16-pad3_ net-_u1-pad13_ risingedge_dflipflop +* u7 net-_u1-pad7_ net-_u16-pad3_ net-_u1-pad12_ risingedge_dflipflop +* u8 net-_u1-pad8_ net-_u16-pad3_ net-_u1-pad11_ risingedge_dflipflop +* u9 net-_u1-pad9_ net-_u16-pad3_ net-_u1-pad10_ risingedge_dflipflop +a1 net-_u1-pad1_ net-_u10-pad2_ u10 +a2 net-_u10-pad2_ net-_u12-pad2_ u12 +a3 [net-_u12-pad2_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a4 net-_u1-pad18_ net-_u11-pad2_ u11 +a5 net-_u11-pad2_ net-_u13-pad2_ u13 +a6 [net-_u14-pad3_ net-_u13-pad2_ ] net-_u14-pad2_ u15 +a7 [net-_u14-pad3_ net-_u1-pad18_ ] net-_u16-pad3_ u16 +a8 [net-_u1-pad2_ ] [net-_u16-pad3_ ] [net-_u1-pad17_ ] u2 +a9 [net-_u1-pad3_ ] [net-_u16-pad3_ ] [net-_u1-pad16_ ] u3 +a10 [net-_u1-pad4_ ] [net-_u16-pad3_ ] [net-_u1-pad15_ ] u4 +a11 [net-_u1-pad5_ ] [net-_u16-pad3_ ] [net-_u1-pad14_ ] u5 +a12 [net-_u1-pad6_ ] [net-_u16-pad3_ ] [net-_u1-pad13_ ] u6 +a13 [net-_u1-pad7_ ] [net-_u16-pad3_ ] [net-_u1-pad12_ ] u7 +a14 [net-_u1-pad8_ ] [net-_u16-pad3_ ] [net-_u1-pad11_ ] u8 +a15 [net-_u1-pad9_ ] [net-_u16-pad3_ ] [net-_u1-pad10_ ] u9 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u14 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u13 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u15 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u2 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u3 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u4 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u5 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u6 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u7 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u8 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u9 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Control Statements + +.ends SN74HC377 \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74HC377/SN74HC377_Previous_Values.xml b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74HC377/SN74HC377_Previous_Values.xml new file mode 100644 index 000000000..6abcc2117 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74HC377/SN74HC377_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_inverterd_inverterd_nord_inverterd_bufferd_nord_andrisingedge_dflipfloprisingedge_dflipfloprisingedge_dflipfloprisingedge_dflipfloprisingedge_dflipfloprisingedge_dflipfloprisingedge_dflipfloprisingedge_dflipflop \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74HC377/analysis b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74HC377/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74HC377/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS298/SN74LS298-cache.lib b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS298/SN74LS298-cache.lib new file mode 100644 index 000000000..2a7c785ed --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS298/SN74LS298-cache.lib @@ -0,0 +1,168 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# adc_bridge_2 +# +DEF adc_bridge_2 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_2" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -100 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X OUT1 3 550 50 200 L 50 50 1 1 O +X OUT2 4 550 -50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# adc_bridge_8 +# +DEF adc_bridge_8 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_8" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -700 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X IN6 6 -600 -450 200 R 50 50 1 1 I +X IN7 7 -600 -550 200 R 50 50 1 1 I +X IN8 8 -600 -650 200 R 50 50 1 1 I +X OUT1 9 550 50 200 L 50 50 1 1 O +X OUT2 10 550 -50 200 L 50 50 1 1 O +X OUT3 11 550 -150 200 L 50 50 1 1 O +X OUT4 12 550 -250 200 L 50 50 1 1 O +X OUT5 13 550 -350 200 L 50 50 1 1 O +X OUT6 14 550 -450 200 L 50 50 1 1 O +X OUT7 15 550 -550 200 L 50 50 1 1 O +X OUT8 16 550 -650 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# dac_bridge_1 +# +DEF dac_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# sr_flipflop +# +DEF sr_flipflop U 0 40 Y Y 1 F N +F0 "U" 2850 1800 60 H V C CNN +F1 "sr_flipflop" 2850 2000 60 H V C CNN +F2 "" 2850 1950 60 H V C CNN +F3 "" 2850 1950 60 H V C CNN +DRAW +S 2350 2100 3350 1500 0 1 0 N +X clk0 1 2150 1900 200 R 50 50 1 1 I +X S0 2 2150 1800 200 R 50 50 1 1 I +X R0 3 2150 1700 200 R 50 50 1 1 I +X Q0 4 3550 1900 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS298/SN74LS298.cir b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS298/SN74LS298.cir new file mode 100644 index 000000000..30392135f --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS298/SN74LS298.cir @@ -0,0 +1,44 @@ +* C:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\SN74LS298\SN74LS298.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/25/25 16:07:06 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U8 Net-_U3-Pad10_ Net-_U10-Pad2_ Net-_U19-Pad1_ d_and +U9 Net-_U11-Pad1_ Net-_U3-Pad11_ Net-_U19-Pad2_ d_and +U19 Net-_U19-Pad1_ Net-_U19-Pad2_ Net-_U15-Pad3_ d_nor +U23 Net-_U15-Pad3_ Net-_U15-Pad2_ d_inverter +U15 Net-_U14-Pad1_ Net-_U15-Pad2_ Net-_U15-Pad3_ Net-_U15-Pad4_ sr_flipflop +U6 Net-_U3-Pad12_ Net-_U10-Pad2_ Net-_U18-Pad1_ d_and +U7 Net-_U11-Pad1_ Net-_U3-Pad13_ Net-_U18-Pad2_ d_and +U18 Net-_U18-Pad1_ Net-_U18-Pad2_ Net-_U14-Pad3_ d_nor +U22 Net-_U14-Pad3_ Net-_U14-Pad2_ d_inverter +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U14-Pad3_ Net-_U14-Pad4_ sr_flipflop +U12 Net-_U12-Pad1_ Net-_U10-Pad2_ Net-_U12-Pad3_ d_and +U13 Net-_U11-Pad1_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_and +U21 Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U17-Pad3_ d_nor +U25 Net-_U17-Pad3_ Net-_U17-Pad2_ d_inverter +U17 Net-_U14-Pad1_ Net-_U17-Pad2_ Net-_U17-Pad3_ Net-_U17-Pad4_ sr_flipflop +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_and +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_and +U20 Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_U16-Pad3_ d_nor +U24 Net-_U16-Pad3_ Net-_U16-Pad2_ d_inverter +U16 Net-_U14-Pad1_ Net-_U16-Pad2_ Net-_U16-Pad3_ Net-_U16-Pad4_ sr_flipflop +U5 Net-_U3-Pad9_ Net-_U10-Pad2_ d_inverter +U4 Net-_U10-Pad2_ Net-_U11-Pad1_ d_inverter +U27 Net-_U27-Pad1_ Net-_U1-Pad15_ dac_bridge_1 +U26 Net-_U26-Pad1_ Net-_U1-Pad14_ dac_bridge_1 +U28 Net-_U28-Pad1_ Net-_U1-Pad13_ dac_bridge_1 +U29 Net-_U29-Pad1_ Net-_U1-Pad12_ dac_bridge_1 +U3 Net-_U1-Pad10_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad9_ Net-_U1-Pad6_ Net-_U3-Pad9_ Net-_U3-Pad10_ Net-_U3-Pad11_ Net-_U3-Pad12_ Net-_U3-Pad13_ Net-_U12-Pad1_ Net-_U13-Pad2_ Net-_U10-Pad1_ adc_bridge_8 +U2 Net-_U1-Pad7_ Net-_U1-Pad11_ Net-_U11-Pad2_ Net-_U2-Pad4_ adc_bridge_2 +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT +U30 Net-_U2-Pad4_ Net-_U14-Pad1_ d_inverter +U32 Net-_U15-Pad4_ Net-_U27-Pad1_ d_inverter +U31 Net-_U14-Pad4_ Net-_U26-Pad1_ d_inverter +U33 Net-_U17-Pad4_ Net-_U28-Pad1_ d_inverter +U34 Net-_U16-Pad4_ Net-_U29-Pad1_ d_inverter + +.end diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS298/SN74LS298.cir.out b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS298/SN74LS298.cir.out new file mode 100644 index 000000000..81be7a72f --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS298/SN74LS298.cir.out @@ -0,0 +1,144 @@ +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\sn74ls298\sn74ls298.cir + +* u8 net-_u3-pad10_ net-_u10-pad2_ net-_u19-pad1_ d_and +* u9 net-_u11-pad1_ net-_u3-pad11_ net-_u19-pad2_ d_and +* u19 net-_u19-pad1_ net-_u19-pad2_ net-_u15-pad3_ d_nor +* u23 net-_u15-pad3_ net-_u15-pad2_ d_inverter +* u15 net-_u14-pad1_ net-_u15-pad2_ net-_u15-pad3_ net-_u15-pad4_ sr_flipflop +* u6 net-_u3-pad12_ net-_u10-pad2_ net-_u18-pad1_ d_and +* u7 net-_u11-pad1_ net-_u3-pad13_ net-_u18-pad2_ d_and +* u18 net-_u18-pad1_ net-_u18-pad2_ net-_u14-pad3_ d_nor +* u22 net-_u14-pad3_ net-_u14-pad2_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ net-_u14-pad4_ sr_flipflop +* u12 net-_u12-pad1_ net-_u10-pad2_ net-_u12-pad3_ d_and +* u13 net-_u11-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_and +* u21 net-_u12-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_nor +* u25 net-_u17-pad3_ net-_u17-pad2_ d_inverter +* u17 net-_u14-pad1_ net-_u17-pad2_ net-_u17-pad3_ net-_u17-pad4_ sr_flipflop +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and +* u20 net-_u10-pad3_ net-_u11-pad3_ net-_u16-pad3_ d_nor +* u24 net-_u16-pad3_ net-_u16-pad2_ d_inverter +* u16 net-_u14-pad1_ net-_u16-pad2_ net-_u16-pad3_ net-_u16-pad4_ sr_flipflop +* u5 net-_u3-pad9_ net-_u10-pad2_ d_inverter +* u4 net-_u10-pad2_ net-_u11-pad1_ d_inverter +* u27 net-_u27-pad1_ net-_u1-pad15_ dac_bridge_1 +* u26 net-_u26-pad1_ net-_u1-pad14_ dac_bridge_1 +* u28 net-_u28-pad1_ net-_u1-pad13_ dac_bridge_1 +* u29 net-_u29-pad1_ net-_u1-pad12_ dac_bridge_1 +* u3 net-_u1-pad10_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad9_ net-_u1-pad6_ net-_u3-pad9_ net-_u3-pad10_ net-_u3-pad11_ net-_u3-pad12_ net-_u3-pad13_ net-_u12-pad1_ net-_u13-pad2_ net-_u10-pad1_ adc_bridge_8 +* u2 net-_u1-pad7_ net-_u1-pad11_ net-_u11-pad2_ net-_u2-pad4_ adc_bridge_2 +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port +* u30 net-_u2-pad4_ net-_u14-pad1_ d_inverter +* u32 net-_u15-pad4_ net-_u27-pad1_ d_inverter +* u31 net-_u14-pad4_ net-_u26-pad1_ d_inverter +* u33 net-_u17-pad4_ net-_u28-pad1_ d_inverter +* u34 net-_u16-pad4_ net-_u29-pad1_ d_inverter +a1 [net-_u3-pad10_ net-_u10-pad2_ ] net-_u19-pad1_ u8 +a2 [net-_u11-pad1_ net-_u3-pad11_ ] net-_u19-pad2_ u9 +a3 [net-_u19-pad1_ net-_u19-pad2_ ] net-_u15-pad3_ u19 +a4 net-_u15-pad3_ net-_u15-pad2_ u23 +a5 [net-_u14-pad1_ ] [net-_u15-pad2_ ] [net-_u15-pad3_ ] [net-_u15-pad4_ ] u15 +a6 [net-_u3-pad12_ net-_u10-pad2_ ] net-_u18-pad1_ u6 +a7 [net-_u11-pad1_ net-_u3-pad13_ ] net-_u18-pad2_ u7 +a8 [net-_u18-pad1_ net-_u18-pad2_ ] net-_u14-pad3_ u18 +a9 net-_u14-pad3_ net-_u14-pad2_ u22 +a10 [net-_u14-pad1_ ] [net-_u14-pad2_ ] [net-_u14-pad3_ ] [net-_u14-pad4_ ] u14 +a11 [net-_u12-pad1_ net-_u10-pad2_ ] net-_u12-pad3_ u12 +a12 [net-_u11-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a13 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u21 +a14 net-_u17-pad3_ net-_u17-pad2_ u25 +a15 [net-_u14-pad1_ ] [net-_u17-pad2_ ] [net-_u17-pad3_ ] [net-_u17-pad4_ ] u17 +a16 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a17 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a18 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u16-pad3_ u20 +a19 net-_u16-pad3_ net-_u16-pad2_ u24 +a20 [net-_u14-pad1_ ] [net-_u16-pad2_ ] [net-_u16-pad3_ ] [net-_u16-pad4_ ] u16 +a21 net-_u3-pad9_ net-_u10-pad2_ u5 +a22 net-_u10-pad2_ net-_u11-pad1_ u4 +a23 [net-_u27-pad1_ ] [net-_u1-pad15_ ] u27 +a24 [net-_u26-pad1_ ] [net-_u1-pad14_ ] u26 +a25 [net-_u28-pad1_ ] [net-_u1-pad13_ ] u28 +a26 [net-_u29-pad1_ ] [net-_u1-pad12_ ] u29 +a27 [net-_u1-pad10_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad9_ net-_u1-pad6_ ] [net-_u3-pad9_ net-_u3-pad10_ net-_u3-pad11_ net-_u3-pad12_ net-_u3-pad13_ net-_u12-pad1_ net-_u13-pad2_ net-_u10-pad1_ ] u3 +a28 [net-_u1-pad7_ net-_u1-pad11_ ] [net-_u11-pad2_ net-_u2-pad4_ ] u2 +a29 net-_u2-pad4_ net-_u14-pad1_ u30 +a30 net-_u15-pad4_ net-_u27-pad1_ u32 +a31 net-_u14-pad4_ net-_u26-pad1_ u31 +a32 net-_u17-pad4_ net-_u28-pad1_ u33 +a33 net-_u16-pad4_ net-_u29-pad1_ u34 +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u19 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: sr_flipflop, NgSpice Name: sr_flipflop +.model u15 sr_flipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u18 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: sr_flipflop, NgSpice Name: sr_flipflop +.model u14 sr_flipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u21 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: sr_flipflop, NgSpice Name: sr_flipflop +.model u17 sr_flipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u20 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: sr_flipflop, NgSpice Name: sr_flipflop +.model u16 sr_flipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u27 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u26 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u28 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u29 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_8, NgSpice Name: adc_bridge +.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS298/SN74LS298.pro b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS298/SN74LS298.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS298/SN74LS298.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS298/SN74LS298.sch b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS298/SN74LS298.sch new file mode 100644 index 000000000..dd2e23b03 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS298/SN74LS298.sch @@ -0,0 +1,846 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN74LS298-cache +EELAYER 25 0 +EELAYER END +$Descr A3 16535 11693 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U8 +U 1 1 685BC0E5 +P 6450 2250 +F 0 "U8" H 6450 2250 60 0000 C CNN +F 1 "d_and" H 6500 2350 60 0000 C CNN +F 2 "" H 6450 2250 60 0000 C CNN +F 3 "" H 6450 2250 60 0000 C CNN + 1 6450 2250 + 1 0 0 -1 +$EndComp +$Comp +L d_and U9 +U 1 1 685BC14D +P 6450 2700 +F 0 "U9" H 6450 2700 60 0000 C CNN +F 1 "d_and" H 6500 2800 60 0000 C CNN +F 2 "" H 6450 2700 60 0000 C CNN +F 3 "" H 6450 2700 60 0000 C CNN + 1 6450 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U19 +U 1 1 685BC16B +P 7550 2450 +F 0 "U19" H 7550 2450 60 0000 C CNN +F 1 "d_nor" H 7600 2550 60 0000 C CNN +F 2 "" H 7550 2450 60 0000 C CNN +F 3 "" H 7550 2450 60 0000 C CNN + 1 7550 2450 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U23 +U 1 1 685BC1AE +P 8450 2400 +F 0 "U23" H 8450 2300 60 0000 C CNN +F 1 "d_inverter" H 8450 2550 60 0000 C CNN +F 2 "" H 8500 2350 60 0000 C CNN +F 3 "" H 8500 2350 60 0000 C CNN + 1 8450 2400 + 1 0 0 -1 +$EndComp +$Comp +L sr_flipflop U15 +U 1 1 685BC1EF +P 6850 4300 +F 0 "U15" H 9700 6100 60 0000 C CNN +F 1 "sr_flipflop" H 9700 6300 60 0000 C CNN +F 2 "" H 9700 6250 60 0000 C CNN +F 3 "" H 9700 6250 60 0000 C CNN + 1 6850 4300 + 1 0 0 -1 +$EndComp +$Comp +L d_and U6 +U 1 1 685BC6D0 +P 6400 3800 +F 0 "U6" H 6400 3800 60 0000 C CNN +F 1 "d_and" H 6450 3900 60 0000 C CNN +F 2 "" H 6400 3800 60 0000 C CNN +F 3 "" H 6400 3800 60 0000 C CNN + 1 6400 3800 + 1 0 0 -1 +$EndComp +$Comp +L d_and U7 +U 1 1 685BC6D6 +P 6400 4250 +F 0 "U7" H 6400 4250 60 0000 C CNN +F 1 "d_and" H 6450 4350 60 0000 C CNN +F 2 "" H 6400 4250 60 0000 C CNN +F 3 "" H 6400 4250 60 0000 C CNN + 1 6400 4250 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U18 +U 1 1 685BC6DC +P 7500 4000 +F 0 "U18" H 7500 4000 60 0000 C CNN +F 1 "d_nor" H 7550 4100 60 0000 C CNN +F 2 "" H 7500 4000 60 0000 C CNN +F 3 "" H 7500 4000 60 0000 C CNN + 1 7500 4000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U22 +U 1 1 685BC6E2 +P 8400 3950 +F 0 "U22" H 8400 3850 60 0000 C CNN +F 1 "d_inverter" H 8400 4100 60 0000 C CNN +F 2 "" H 8450 3900 60 0000 C CNN +F 3 "" H 8450 3900 60 0000 C CNN + 1 8400 3950 + 1 0 0 -1 +$EndComp +$Comp +L sr_flipflop U14 +U 1 1 685BC6E8 +P 6800 5850 +F 0 "U14" H 9650 7650 60 0000 C CNN +F 1 "sr_flipflop" H 9650 7850 60 0000 C CNN +F 2 "" H 9650 7800 60 0000 C CNN +F 3 "" H 9650 7800 60 0000 C CNN + 1 6800 5850 + 1 0 0 -1 +$EndComp +$Comp +L d_and U12 +U 1 1 685BC86B +P 6500 5200 +F 0 "U12" H 6500 5200 60 0000 C CNN +F 1 "d_and" H 6550 5300 60 0000 C CNN +F 2 "" H 6500 5200 60 0000 C CNN +F 3 "" H 6500 5200 60 0000 C CNN + 1 6500 5200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U13 +U 1 1 685BC871 +P 6500 5650 +F 0 "U13" H 6500 5650 60 0000 C CNN +F 1 "d_and" H 6550 5750 60 0000 C CNN +F 2 "" H 6500 5650 60 0000 C CNN +F 3 "" H 6500 5650 60 0000 C CNN + 1 6500 5650 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U21 +U 1 1 685BC877 +P 7600 5400 +F 0 "U21" H 7600 5400 60 0000 C CNN +F 1 "d_nor" H 7650 5500 60 0000 C CNN +F 2 "" H 7600 5400 60 0000 C CNN +F 3 "" H 7600 5400 60 0000 C CNN + 1 7600 5400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U25 +U 1 1 685BC87D +P 8500 5350 +F 0 "U25" H 8500 5250 60 0000 C CNN +F 1 "d_inverter" H 8500 5500 60 0000 C CNN +F 2 "" H 8550 5300 60 0000 C CNN +F 3 "" H 8550 5300 60 0000 C CNN + 1 8500 5350 + 1 0 0 -1 +$EndComp +$Comp +L sr_flipflop U17 +U 1 1 685BC883 +P 6900 7250 +F 0 "U17" H 9750 9050 60 0000 C CNN +F 1 "sr_flipflop" H 9750 9250 60 0000 C CNN +F 2 "" H 9750 9200 60 0000 C CNN +F 3 "" H 9750 9200 60 0000 C CNN + 1 6900 7250 + 1 0 0 -1 +$EndComp +$Comp +L d_and U10 +U 1 1 685BC894 +P 6450 6750 +F 0 "U10" H 6450 6750 60 0000 C CNN +F 1 "d_and" H 6500 6850 60 0000 C CNN +F 2 "" H 6450 6750 60 0000 C CNN +F 3 "" H 6450 6750 60 0000 C CNN + 1 6450 6750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U11 +U 1 1 685BC89A +P 6450 7200 +F 0 "U11" H 6450 7200 60 0000 C CNN +F 1 "d_and" H 6500 7300 60 0000 C CNN +F 2 "" H 6450 7200 60 0000 C CNN +F 3 "" H 6450 7200 60 0000 C CNN + 1 6450 7200 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U20 +U 1 1 685BC8A0 +P 7550 6950 +F 0 "U20" H 7550 6950 60 0000 C CNN +F 1 "d_nor" H 7600 7050 60 0000 C CNN +F 2 "" H 7550 6950 60 0000 C CNN +F 3 "" H 7550 6950 60 0000 C CNN + 1 7550 6950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U24 +U 1 1 685BC8A6 +P 8450 6900 +F 0 "U24" H 8450 6800 60 0000 C CNN +F 1 "d_inverter" H 8450 7050 60 0000 C CNN +F 2 "" H 8500 6850 60 0000 C CNN +F 3 "" H 8500 6850 60 0000 C CNN + 1 8450 6900 + 1 0 0 -1 +$EndComp +$Comp +L sr_flipflop U16 +U 1 1 685BC8AC +P 6850 8800 +F 0 "U16" H 9700 10600 60 0000 C CNN +F 1 "sr_flipflop" H 9700 10800 60 0000 C CNN +F 2 "" H 9700 10750 60 0000 C CNN +F 3 "" H 9700 10750 60 0000 C CNN + 1 6850 8800 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 685BCDA9 +P 4950 2200 +F 0 "U5" H 4950 2100 60 0000 C CNN +F 1 "d_inverter" H 4950 2350 60 0000 C CNN +F 2 "" H 5000 2150 60 0000 C CNN +F 3 "" H 5000 2150 60 0000 C CNN + 1 4950 2200 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 685BCEFD +P 4900 2550 +F 0 "U4" H 4900 2450 60 0000 C CNN +F 1 "d_inverter" H 4900 2700 60 0000 C CNN +F 2 "" H 4950 2500 60 0000 C CNN +F 3 "" H 4950 2500 60 0000 C CNN + 1 4900 2550 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U27 +U 1 1 685BE3C3 +P 11850 2450 +F 0 "U27" H 11850 2450 60 0000 C CNN +F 1 "dac_bridge_1" H 11850 2600 60 0000 C CNN +F 2 "" H 11850 2450 60 0000 C CNN +F 3 "" H 11850 2450 60 0000 C CNN + 1 11850 2450 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U26 +U 1 1 685BE52F +P 11800 4000 +F 0 "U26" H 11800 4000 60 0000 C CNN +F 1 "dac_bridge_1" H 11800 4150 60 0000 C CNN +F 2 "" H 11800 4000 60 0000 C CNN +F 3 "" H 11800 4000 60 0000 C CNN + 1 11800 4000 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U28 +U 1 1 685BE621 +P 11850 5400 +F 0 "U28" H 11850 5400 60 0000 C CNN +F 1 "dac_bridge_1" H 11850 5550 60 0000 C CNN +F 2 "" H 11850 5400 60 0000 C CNN +F 3 "" H 11850 5400 60 0000 C CNN + 1 11850 5400 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U29 +U 1 1 685BE694 +P 11900 6950 +F 0 "U29" H 11900 6950 60 0000 C CNN +F 1 "dac_bridge_1" H 11900 7100 60 0000 C CNN +F 2 "" H 11900 6950 60 0000 C CNN +F 3 "" H 11900 6950 60 0000 C CNN + 1 11900 6950 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_8 U3 +U 1 1 685BF3AE +P 3600 3250 +F 0 "U3" H 3600 3250 60 0000 C CNN +F 1 "adc_bridge_8" H 3600 3400 60 0000 C CNN +F 2 "" H 3600 3250 60 0000 C CNN +F 3 "" H 3600 3250 60 0000 C CNN + 1 3600 3250 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_2 U2 +U 1 1 685BF616 +P 3400 6700 +F 0 "U2" H 3400 6700 60 0000 C CNN +F 1 "adc_bridge_2" H 3400 6850 60 0000 C CNN +F 2 "" H 3400 6700 60 0000 C CNN +F 3 "" H 3400 6700 60 0000 C CNN + 1 3400 6700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 685C07E2 +P 2500 6650 +F 0 "U1" H 2550 6750 30 0000 C CNN +F 1 "PORT" H 2500 6650 30 0000 C CNN +F 2 "" H 2500 6650 60 0000 C CNN +F 3 "" H 2500 6650 60 0000 C CNN + 7 2500 6650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 685C08EF +P 2700 3300 +F 0 "U1" H 2750 3400 30 0000 C CNN +F 1 "PORT" H 2700 3300 30 0000 C CNN +F 2 "" H 2700 3300 60 0000 C CNN +F 3 "" H 2700 3300 60 0000 C CNN + 2 2700 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 685C095E +P 13750 900 +F 0 "U1" H 13800 1000 30 0000 C CNN +F 1 "PORT" H 13750 900 30 0000 C CNN +F 2 "" H 13750 900 60 0000 C CNN +F 3 "" H 13750 900 60 0000 C CNN + 8 13750 900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 685C09D1 +P 2450 3400 +F 0 "U1" H 2500 3500 30 0000 C CNN +F 1 "PORT" H 2450 3400 30 0000 C CNN +F 2 "" H 2450 3400 60 0000 C CNN +F 3 "" H 2450 3400 60 0000 C CNN + 3 2450 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 685C0A4A +P 2450 3800 +F 0 "U1" H 2500 3900 30 0000 C CNN +F 1 "PORT" H 2450 3800 30 0000 C CNN +F 2 "" H 2450 3800 60 0000 C CNN +F 3 "" H 2450 3800 60 0000 C CNN + 9 2450 3800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 685C0AC3 +P 2450 3600 +F 0 "U1" H 2500 3700 30 0000 C CNN +F 1 "PORT" H 2450 3600 30 0000 C CNN +F 2 "" H 2450 3600 60 0000 C CNN +F 3 "" H 2450 3600 60 0000 C CNN + 4 2450 3600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 685C0B3E +P 2450 3200 +F 0 "U1" H 2500 3300 30 0000 C CNN +F 1 "PORT" H 2450 3200 30 0000 C CNN +F 2 "" H 2450 3200 60 0000 C CNN +F 3 "" H 2450 3200 60 0000 C CNN + 10 2450 3200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 685C0BBF +P 2700 3700 +F 0 "U1" H 2750 3800 30 0000 C CNN +F 1 "PORT" H 2700 3700 30 0000 C CNN +F 2 "" H 2700 3700 60 0000 C CNN +F 3 "" H 2700 3700 60 0000 C CNN + 5 2700 3700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 685C0D4F +P 2700 3900 +F 0 "U1" H 2750 4000 30 0000 C CNN +F 1 "PORT" H 2700 3900 30 0000 C CNN +F 2 "" H 2700 3900 60 0000 C CNN +F 3 "" H 2700 3900 60 0000 C CNN + 6 2700 3900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 15 1 685C108E +P 12900 2400 +F 0 "U1" H 12950 2500 30 0000 C CNN +F 1 "PORT" H 12900 2400 30 0000 C CNN +F 2 "" H 12900 2400 60 0000 C CNN +F 3 "" H 12900 2400 60 0000 C CNN + 15 12900 2400 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 685C132F +P 12750 5350 +F 0 "U1" H 12800 5450 30 0000 C CNN +F 1 "PORT" H 12750 5350 30 0000 C CNN +F 2 "" H 12750 5350 60 0000 C CNN +F 3 "" H 12750 5350 60 0000 C CNN + 13 12750 5350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 685C14E0 +P 12800 6900 +F 0 "U1" H 12850 7000 30 0000 C CNN +F 1 "PORT" H 12800 6900 30 0000 C CNN +F 2 "" H 12800 6900 60 0000 C CNN +F 3 "" H 12800 6900 60 0000 C CNN + 12 12800 6900 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 685C154B +P 12800 3950 +F 0 "U1" H 12850 4050 30 0000 C CNN +F 1 "PORT" H 12800 3950 30 0000 C CNN +F 2 "" H 12800 3950 60 0000 C CNN +F 3 "" H 12800 3950 60 0000 C CNN + 14 12800 3950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 685C15CA +P 2250 6750 +F 0 "U1" H 2300 6850 30 0000 C CNN +F 1 "PORT" H 2250 6750 30 0000 C CNN +F 2 "" H 2250 6750 60 0000 C CNN +F 3 "" H 2250 6750 60 0000 C CNN + 11 2250 6750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 685C1657 +P 13750 1150 +F 0 "U1" H 13800 1250 30 0000 C CNN +F 1 "PORT" H 13750 1150 30 0000 C CNN +F 2 "" H 13750 1150 60 0000 C CNN +F 3 "" H 13750 1150 60 0000 C CNN + 16 13750 1150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6900 2200 7100 2200 +Wire Wire Line + 7100 2200 7100 2350 +Wire Wire Line + 7100 2450 7100 2650 +Wire Wire Line + 7100 2650 6900 2650 +Wire Wire Line + 8000 2400 8150 2400 +Wire Wire Line + 8750 2400 8850 2400 +Wire Wire Line + 8850 2400 8850 2500 +Wire Wire Line + 8850 2500 9000 2500 +Wire Wire Line + 9000 2600 8100 2600 +Wire Wire Line + 8100 2600 8100 2400 +Connection ~ 8100 2400 +Wire Wire Line + 6850 3750 7050 3750 +Wire Wire Line + 7050 3750 7050 3900 +Wire Wire Line + 7050 4000 7050 4200 +Wire Wire Line + 7050 4200 6850 4200 +Wire Wire Line + 7950 3950 8100 3950 +Wire Wire Line + 8700 3950 8800 3950 +Wire Wire Line + 8800 3950 8800 4050 +Wire Wire Line + 8800 4050 8950 4050 +Wire Wire Line + 8950 4150 8050 4150 +Wire Wire Line + 8050 4150 8050 3950 +Connection ~ 8050 3950 +Wire Wire Line + 6950 5150 7150 5150 +Wire Wire Line + 7150 5150 7150 5300 +Wire Wire Line + 7150 5400 7150 5600 +Wire Wire Line + 7150 5600 6950 5600 +Wire Wire Line + 8050 5350 8200 5350 +Wire Wire Line + 8800 5350 8900 5350 +Wire Wire Line + 8900 5350 8900 5450 +Wire Wire Line + 8900 5450 9050 5450 +Wire Wire Line + 9050 5550 8150 5550 +Wire Wire Line + 8150 5550 8150 5350 +Connection ~ 8150 5350 +Wire Wire Line + 6900 6700 7100 6700 +Wire Wire Line + 7100 6700 7100 6850 +Wire Wire Line + 7100 6950 7100 7150 +Wire Wire Line + 7100 7150 6900 7150 +Wire Wire Line + 8000 6900 8150 6900 +Wire Wire Line + 8750 6900 8850 6900 +Wire Wire Line + 8850 6900 8850 7000 +Wire Wire Line + 8850 7000 9000 7000 +Wire Wire Line + 9000 7100 8100 7100 +Wire Wire Line + 8100 7100 8100 6900 +Connection ~ 8100 6900 +Wire Wire Line + 5250 2200 6000 2200 +Wire Wire Line + 6000 2200 6000 2250 +Wire Wire Line + 5200 2550 6000 2550 +Wire Wire Line + 6000 2550 6000 2600 +Wire Wire Line + 5800 2200 5800 6750 +Wire Wire Line + 5800 6750 6000 6750 +Connection ~ 5800 2200 +Wire Wire Line + 5700 2550 5700 7100 +Wire Wire Line + 5700 7100 6000 7100 +Connection ~ 5700 2550 +Wire Wire Line + 5950 3800 5800 3800 +Connection ~ 5800 3800 +Wire Wire Line + 5950 4150 5700 4150 +Connection ~ 5700 4150 +Wire Wire Line + 6050 5200 5800 5200 +Connection ~ 5800 5200 +Wire Wire Line + 6050 5550 5700 5550 +Connection ~ 5700 5550 +Wire Wire Line + 9000 2400 8900 2400 +Wire Wire Line + 8900 2400 8900 5250 +Wire Wire Line + 8900 5250 8950 5250 +Wire Wire Line + 8950 5250 8950 7450 +Wire Wire Line + 8950 6900 9000 6900 +Wire Wire Line + 9050 5350 8950 5350 +Connection ~ 8950 5350 +Wire Wire Line + 8950 3950 8900 3950 +Connection ~ 8900 3950 +Wire Wire Line + 10400 2400 10550 2400 +Wire Wire Line + 10500 3950 10350 3950 +Wire Wire Line + 10450 5350 10550 5350 +Wire Wire Line + 10400 6900 10600 6900 +Wire Wire Line + 4650 2200 4150 2200 +Wire Wire Line + 4150 2200 4150 3200 +Wire Wire Line + 4250 3300 4150 3300 +Wire Wire Line + 4150 3400 5500 3400 +Wire Wire Line + 6000 2700 5500 2700 +Wire Wire Line + 4150 3500 5950 3500 +Wire Wire Line + 4950 3600 4950 4250 +Wire Wire Line + 4950 3600 4150 3600 +Wire Wire Line + 4150 3700 4850 3700 +Wire Wire Line + 4850 3700 4850 5100 +Wire Wire Line + 4150 3800 4700 3800 +Wire Wire Line + 4700 3800 4700 5650 +Wire Wire Line + 4500 3900 4500 6650 +Wire Wire Line + 4500 3900 4150 3900 +Wire Wire Line + 3950 6750 3950 7550 +Wire Wire Line + 5300 2200 5300 2450 +Wire Wire Line + 5300 2450 4550 2450 +Wire Wire Line + 4550 2450 4550 2550 +Wire Wire Line + 4550 2550 4600 2550 +Connection ~ 5300 2200 +Wire Wire Line + 6000 2150 5400 2150 +Wire Wire Line + 5400 2150 5400 2700 +Wire Wire Line + 5400 2700 4250 2700 +Wire Wire Line + 4250 2700 4250 3300 +Wire Wire Line + 5500 2700 5500 3400 +Wire Wire Line + 5950 3500 5950 3700 +Wire Wire Line + 4950 4250 5950 4250 +Wire Wire Line + 4850 5100 6050 5100 +Wire Wire Line + 4700 5650 6050 5650 +Wire Wire Line + 4500 6650 6000 6650 +Wire Wire Line + 3950 6650 4400 6650 +Wire Wire Line + 4400 6650 4400 7200 +Wire Wire Line + 4400 7200 6000 7200 +Connection ~ 8950 6900 +$Comp +L PORT U1 +U 1 1 685C7AA8 +P 2700 3500 +F 0 "U1" H 2750 3600 30 0000 C CNN +F 1 "PORT" H 2700 3500 30 0000 C CNN +F 2 "" H 2700 3500 60 0000 C CNN +F 3 "" H 2700 3500 60 0000 C CNN + 1 2700 3500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2700 3200 3000 3200 +Wire Wire Line + 3000 3300 2950 3300 +Wire Wire Line + 2700 3400 3000 3400 +Wire Wire Line + 3000 3500 2950 3500 +Wire Wire Line + 2700 3600 3000 3600 +Wire Wire Line + 2950 3700 3000 3700 +Wire Wire Line + 3000 3800 2700 3800 +Wire Wire Line + 2950 3900 3000 3900 +Wire Wire Line + 2750 6650 2800 6650 +Wire Wire Line + 2800 6750 2500 6750 +Wire Wire Line + 12400 2400 12650 2400 +Wire Wire Line + 12350 3950 12550 3950 +Wire Wire Line + 12400 5350 12500 5350 +Wire Wire Line + 12450 6900 12550 6900 +NoConn ~ 14000 900 +NoConn ~ 14000 1150 +$Comp +L d_inverter U30 +U 1 1 685BD322 +P 5750 7550 +F 0 "U30" H 5750 7450 60 0000 C CNN +F 1 "d_inverter" H 5750 7700 60 0000 C CNN +F 2 "" H 5800 7500 60 0000 C CNN +F 3 "" H 5800 7500 60 0000 C CNN + 1 5750 7550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3950 7550 5450 7550 +Wire Wire Line + 8950 7450 6150 7450 +Wire Wire Line + 6150 7450 6150 7550 +Wire Wire Line + 6150 7550 6050 7550 +$Comp +L d_inverter U32 +U 1 1 685BE5B2 +P 10850 2400 +F 0 "U32" H 10850 2300 60 0000 C CNN +F 1 "d_inverter" H 10850 2550 60 0000 C CNN +F 2 "" H 10900 2350 60 0000 C CNN +F 3 "" H 10900 2350 60 0000 C CNN + 1 10850 2400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U31 +U 1 1 685BE816 +P 10800 3950 +F 0 "U31" H 10800 3850 60 0000 C CNN +F 1 "d_inverter" H 10800 4100 60 0000 C CNN +F 2 "" H 10850 3900 60 0000 C CNN +F 3 "" H 10850 3900 60 0000 C CNN + 1 10800 3950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U33 +U 1 1 685BEA5B +P 10850 5350 +F 0 "U33" H 10850 5250 60 0000 C CNN +F 1 "d_inverter" H 10850 5500 60 0000 C CNN +F 2 "" H 10900 5300 60 0000 C CNN +F 3 "" H 10900 5300 60 0000 C CNN + 1 10850 5350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U34 +U 1 1 685BECDF +P 10900 6900 +F 0 "U34" H 10900 6800 60 0000 C CNN +F 1 "d_inverter" H 10900 7050 60 0000 C CNN +F 2 "" H 10950 6850 60 0000 C CNN +F 3 "" H 10950 6850 60 0000 C CNN + 1 10900 6900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 11200 6900 11300 6900 +Wire Wire Line + 11150 5350 11250 5350 +Wire Wire Line + 11100 3950 11200 3950 +Wire Wire Line + 11150 2400 11250 2400 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS298/SN74LS298.sub b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS298/SN74LS298.sub new file mode 100644 index 000000000..d1877e925 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS298/SN74LS298.sub @@ -0,0 +1,138 @@ +* Subcircuit SN74LS298 +.subckt SN74LS298 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\sn74ls298\sn74ls298.cir +* u8 net-_u3-pad10_ net-_u10-pad2_ net-_u19-pad1_ d_and +* u9 net-_u11-pad1_ net-_u3-pad11_ net-_u19-pad2_ d_and +* u19 net-_u19-pad1_ net-_u19-pad2_ net-_u15-pad3_ d_nor +* u23 net-_u15-pad3_ net-_u15-pad2_ d_inverter +* u15 net-_u14-pad1_ net-_u15-pad2_ net-_u15-pad3_ net-_u15-pad4_ sr_flipflop +* u6 net-_u3-pad12_ net-_u10-pad2_ net-_u18-pad1_ d_and +* u7 net-_u11-pad1_ net-_u3-pad13_ net-_u18-pad2_ d_and +* u18 net-_u18-pad1_ net-_u18-pad2_ net-_u14-pad3_ d_nor +* u22 net-_u14-pad3_ net-_u14-pad2_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ net-_u14-pad4_ sr_flipflop +* u12 net-_u12-pad1_ net-_u10-pad2_ net-_u12-pad3_ d_and +* u13 net-_u11-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_and +* u21 net-_u12-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_nor +* u25 net-_u17-pad3_ net-_u17-pad2_ d_inverter +* u17 net-_u14-pad1_ net-_u17-pad2_ net-_u17-pad3_ net-_u17-pad4_ sr_flipflop +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and +* u20 net-_u10-pad3_ net-_u11-pad3_ net-_u16-pad3_ d_nor +* u24 net-_u16-pad3_ net-_u16-pad2_ d_inverter +* u16 net-_u14-pad1_ net-_u16-pad2_ net-_u16-pad3_ net-_u16-pad4_ sr_flipflop +* u5 net-_u3-pad9_ net-_u10-pad2_ d_inverter +* u4 net-_u10-pad2_ net-_u11-pad1_ d_inverter +* u27 net-_u27-pad1_ net-_u1-pad15_ dac_bridge_1 +* u26 net-_u26-pad1_ net-_u1-pad14_ dac_bridge_1 +* u28 net-_u28-pad1_ net-_u1-pad13_ dac_bridge_1 +* u29 net-_u29-pad1_ net-_u1-pad12_ dac_bridge_1 +* u3 net-_u1-pad10_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad9_ net-_u1-pad6_ net-_u3-pad9_ net-_u3-pad10_ net-_u3-pad11_ net-_u3-pad12_ net-_u3-pad13_ net-_u12-pad1_ net-_u13-pad2_ net-_u10-pad1_ adc_bridge_8 +* u2 net-_u1-pad7_ net-_u1-pad11_ net-_u11-pad2_ net-_u2-pad4_ adc_bridge_2 +* u30 net-_u2-pad4_ net-_u14-pad1_ d_inverter +* u32 net-_u15-pad4_ net-_u27-pad1_ d_inverter +* u31 net-_u14-pad4_ net-_u26-pad1_ d_inverter +* u33 net-_u17-pad4_ net-_u28-pad1_ d_inverter +* u34 net-_u16-pad4_ net-_u29-pad1_ d_inverter +a1 [net-_u3-pad10_ net-_u10-pad2_ ] net-_u19-pad1_ u8 +a2 [net-_u11-pad1_ net-_u3-pad11_ ] net-_u19-pad2_ u9 +a3 [net-_u19-pad1_ net-_u19-pad2_ ] net-_u15-pad3_ u19 +a4 net-_u15-pad3_ net-_u15-pad2_ u23 +a5 [net-_u14-pad1_ ] [net-_u15-pad2_ ] [net-_u15-pad3_ ] [net-_u15-pad4_ ] u15 +a6 [net-_u3-pad12_ net-_u10-pad2_ ] net-_u18-pad1_ u6 +a7 [net-_u11-pad1_ net-_u3-pad13_ ] net-_u18-pad2_ u7 +a8 [net-_u18-pad1_ net-_u18-pad2_ ] net-_u14-pad3_ u18 +a9 net-_u14-pad3_ net-_u14-pad2_ u22 +a10 [net-_u14-pad1_ ] [net-_u14-pad2_ ] [net-_u14-pad3_ ] [net-_u14-pad4_ ] u14 +a11 [net-_u12-pad1_ net-_u10-pad2_ ] net-_u12-pad3_ u12 +a12 [net-_u11-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a13 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u21 +a14 net-_u17-pad3_ net-_u17-pad2_ u25 +a15 [net-_u14-pad1_ ] [net-_u17-pad2_ ] [net-_u17-pad3_ ] [net-_u17-pad4_ ] u17 +a16 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a17 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a18 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u16-pad3_ u20 +a19 net-_u16-pad3_ net-_u16-pad2_ u24 +a20 [net-_u14-pad1_ ] [net-_u16-pad2_ ] [net-_u16-pad3_ ] [net-_u16-pad4_ ] u16 +a21 net-_u3-pad9_ net-_u10-pad2_ u5 +a22 net-_u10-pad2_ net-_u11-pad1_ u4 +a23 [net-_u27-pad1_ ] [net-_u1-pad15_ ] u27 +a24 [net-_u26-pad1_ ] [net-_u1-pad14_ ] u26 +a25 [net-_u28-pad1_ ] [net-_u1-pad13_ ] u28 +a26 [net-_u29-pad1_ ] [net-_u1-pad12_ ] u29 +a27 [net-_u1-pad10_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad9_ net-_u1-pad6_ ] [net-_u3-pad9_ net-_u3-pad10_ net-_u3-pad11_ net-_u3-pad12_ net-_u3-pad13_ net-_u12-pad1_ net-_u13-pad2_ net-_u10-pad1_ ] u3 +a28 [net-_u1-pad7_ net-_u1-pad11_ ] [net-_u11-pad2_ net-_u2-pad4_ ] u2 +a29 net-_u2-pad4_ net-_u14-pad1_ u30 +a30 net-_u15-pad4_ net-_u27-pad1_ u32 +a31 net-_u14-pad4_ net-_u26-pad1_ u31 +a32 net-_u17-pad4_ net-_u28-pad1_ u33 +a33 net-_u16-pad4_ net-_u29-pad1_ u34 +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u19 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: sr_flipflop, NgSpice Name: sr_flipflop +.model u15 sr_flipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u18 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: sr_flipflop, NgSpice Name: sr_flipflop +.model u14 sr_flipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u21 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: sr_flipflop, NgSpice Name: sr_flipflop +.model u17 sr_flipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u20 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: sr_flipflop, NgSpice Name: sr_flipflop +.model u16 sr_flipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u27 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u26 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u28 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u29 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_8, NgSpice Name: adc_bridge +.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SN74LS298 \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS298/SN74LS298_Previous_Values.xml b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS298/SN74LS298_Previous_Values.xml new file mode 100644 index 000000000..9485f655d --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS298/SN74LS298_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andd_nord_invertersr_flipflopd_andd_andd_nord_invertersr_flipflopd_andd_andd_nord_invertersr_flipflopd_andd_andd_nord_invertersr_flipflopd_inverterd_inverterdac_bridgedac_bridgedac_bridgedac_bridgeadc_bridgeadc_bridged_inverterd_inverterd_inverterd_inverterd_invertertruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS298/analysis b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS298/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS298/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/3_and-cache.lib b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/3_and-cache.lib new file mode 100644 index 000000000..af0586415 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/3_and.cir b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/3_and.cir new file mode 100644 index 000000000..ba296cf01 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/3_and.cir.out b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/3_and.cir.out new file mode 100644 index 000000000..d7cf79a07 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/3_and.pro b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/3_and.pro new file mode 100644 index 000000000..00597a5ad --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/3_and.sch b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/3_and.sch new file mode 100644 index 000000000..d6ac89f95 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/3_and.sub b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/3_and.sub new file mode 100644 index 000000000..3d9120bb6 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/3_and_Previous_Values.xml b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/3_and_Previous_Values.xml new file mode 100644 index 000000000..abc5faaae --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/4_OR-cache.lib b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/4_OR-cache.lib new file mode 100644 index 000000000..155f5e601 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/4_OR-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/4_OR.cir b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/4_OR.cir new file mode 100644 index 000000000..b338b7b5f --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/4_OR.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or +U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or +U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/4_OR.cir.out b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/4_OR.cir.out new file mode 100644 index 000000000..adb6b01be --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/4_OR.cir.out @@ -0,0 +1,24 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/4_OR.pro b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/4_OR.pro new file mode 100644 index 000000000..881563ebd --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/4_OR.pro @@ -0,0 +1,44 @@ +update=06/01/19 12:36:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_User +LibName10=eSim_Sources +LibName11=eSim_Subckt diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/4_OR.sch b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/4_OR.sch new file mode 100644 index 000000000..118968656 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/4_OR.sch @@ -0,0 +1,150 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U2 +U 1 1 5C9D00E1 +P 4300 2950 +F 0 "U2" H 4300 2950 60 0000 C CNN +F 1 "d_or" H 4300 3050 60 0000 C CNN +F 2 "" H 4300 2950 60 0000 C CNN +F 3 "" H 4300 2950 60 0000 C CNN + 1 4300 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_or U3 +U 1 1 5C9D011F +P 4300 3350 +F 0 "U3" H 4300 3350 60 0000 C CNN +F 1 "d_or" H 4300 3450 60 0000 C CNN +F 2 "" H 4300 3350 60 0000 C CNN +F 3 "" H 4300 3350 60 0000 C CNN + 1 4300 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U4 +U 1 1 5C9D0141 +P 5250 3150 +F 0 "U4" H 5250 3150 60 0000 C CNN +F 1 "d_or" H 5250 3250 60 0000 C CNN +F 2 "" H 5250 3150 60 0000 C CNN +F 3 "" H 5250 3150 60 0000 C CNN + 1 5250 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4800 3050 4800 2900 +Wire Wire Line + 4800 2900 4750 2900 +Wire Wire Line + 4800 3150 4800 3300 +Wire Wire Line + 4800 3300 4750 3300 +Wire Wire Line + 3350 2850 3850 2850 +Wire Wire Line + 3850 2950 3600 2950 +Wire Wire Line + 3850 3250 3350 3250 +Wire Wire Line + 3600 2950 3600 3000 +Wire Wire Line + 3600 3000 3350 3000 +Wire Wire Line + 3850 3350 3850 3400 +Wire Wire Line + 3850 3400 3350 3400 +Wire Wire Line + 5700 3100 6200 3100 +$Comp +L PORT U1 +U 1 1 5C9D01F4 +P 3100 2850 +F 0 "U1" H 3150 2950 30 0000 C CNN +F 1 "PORT" H 3100 2850 30 0000 C CNN +F 2 "" H 3100 2850 60 0000 C CNN +F 3 "" H 3100 2850 60 0000 C CNN + 1 3100 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9D022F +P 3100 3000 +F 0 "U1" H 3150 3100 30 0000 C CNN +F 1 "PORT" H 3100 3000 30 0000 C CNN +F 2 "" H 3100 3000 60 0000 C CNN +F 3 "" H 3100 3000 60 0000 C CNN + 2 3100 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9D0271 +P 3100 3250 +F 0 "U1" H 3150 3350 30 0000 C CNN +F 1 "PORT" H 3100 3250 30 0000 C CNN +F 2 "" H 3100 3250 60 0000 C CNN +F 3 "" H 3100 3250 60 0000 C CNN + 3 3100 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9D0299 +P 3100 3400 +F 0 "U1" H 3150 3500 30 0000 C CNN +F 1 "PORT" H 3100 3400 30 0000 C CNN +F 2 "" H 3100 3400 60 0000 C CNN +F 3 "" H 3100 3400 60 0000 C CNN + 4 3100 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9D02C2 +P 6450 3100 +F 0 "U1" H 6500 3200 30 0000 C CNN +F 1 "PORT" H 6450 3100 30 0000 C CNN +F 2 "" H 6450 3100 60 0000 C CNN +F 3 "" H 6450 3100 60 0000 C CNN + 5 6450 3100 + -1 0 0 1 +$EndComp +Text Notes 3450 2850 0 60 ~ 12 +in1 +Text Notes 3450 3000 0 60 ~ 12 +in2 +Text Notes 3450 3250 0 60 ~ 12 +in3 +Text Notes 3450 3400 0 60 ~ 12 +in4 +Text Notes 5800 3100 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/4_OR.sub b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/4_OR.sub new file mode 100644 index 000000000..d1fd3a241 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/4_OR.sub @@ -0,0 +1,18 @@ +* Subcircuit 4_OR +.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_OR \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/4_OR_Previous_Values.xml b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/4_OR_Previous_Values.xml new file mode 100644 index 000000000..0683d9eb6 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/4_OR_Previous_Values.xml @@ -0,0 +1 @@ +d_ord_ord_ortruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/SN74LS299-cache.lib b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/SN74LS299-cache.lib new file mode 100644 index 000000000..6303687dd --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/SN74LS299-cache.lib @@ -0,0 +1,146 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# buffer_test +# +DEF buffer_test U 0 40 Y Y 1 F N +F0 "U" 2850 1800 60 H V C CNN +F1 "buffer_test" 2850 2000 60 H V C CNN +F2 "" 2850 1950 60 H V C CNN +F3 "" 2850 1950 60 H V C CNN +DRAW +S 2350 2100 3350 1600 0 1 0 N +X A0 1 2150 1900 200 R 50 50 1 1 I +X EN0 2 2150 1800 200 R 50 50 1 1 I +X Y0 3 3550 1900 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_flip_flop +# +DEF d_flip_flop U 0 40 Y Y 1 F N +F0 "U" 2850 1800 60 H V C CNN +F1 "d_flip_flop" 2850 2000 60 H V C CNN +F2 "" 2850 1950 60 H V C CNN +F3 "" 2850 1950 60 H V C CNN +DRAW +S 2350 2100 3350 1500 0 1 0 N +X clk0 1 2150 1900 200 R 50 50 1 1 I +X d0 2 2150 1800 200 R 50 50 1 1 I +X reset0 3 2150 1700 200 R 50 50 1 1 I +X q0 4 3550 1900 200 L 50 50 1 1 O +X q_bar0 5 3550 1800 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/SN74LS299.cir b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/SN74LS299.cir new file mode 100644 index 000000000..b0e629f10 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/SN74LS299.cir @@ -0,0 +1,77 @@ +* C:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\SN74LS299\SN74LS299.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/05/25 16:04:03 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X2 Net-_U8-Pad2_ Net-_U12-Pad2_ Net-_U1-Pad7_ Net-_X2-Pad4_ 3_and +X3 Net-_U13-Pad4_ Net-_U11-Pad2_ Net-_U9-Pad2_ Net-_X3-Pad4_ 3_and +X5 Net-_U1-Pad9_ Net-_U12-Pad2_ Net-_U9-Pad2_ Net-_X4-Pad2_ 3_and +X6 Net-_U1-Pad8_ Net-_U11-Pad2_ Net-_U8-Pad2_ Net-_X4-Pad1_ 3_and +X4 Net-_X4-Pad1_ Net-_X4-Pad2_ Net-_X3-Pad4_ Net-_X2-Pad4_ Net-_U2-Pad2_ 4_OR +U2 Net-_U1-Pad3_ Net-_U2-Pad2_ Net-_U13-Pad3_ Net-_U1-Pad8_ ? d_flip_flop +U3 Net-_U1-Pad8_ Net-_U14-Pad2_ Net-_U1-Pad9_ buffer_test +U8 Net-_U1-Pad2_ Net-_U8-Pad2_ d_inverter +U9 Net-_U8-Pad2_ Net-_U9-Pad2_ d_inverter +U11 Net-_U1-Pad1_ Net-_U11-Pad2_ d_inverter +U12 Net-_U11-Pad2_ Net-_U12-Pad2_ d_inverter +X7 Net-_U8-Pad2_ Net-_U12-Pad2_ Net-_U1-Pad8_ Net-_X7-Pad4_ 3_and +X8 Net-_U15-Pad4_ Net-_U11-Pad2_ Net-_U9-Pad2_ Net-_X8-Pad4_ 3_and +X10 Net-_U1-Pad10_ Net-_U12-Pad2_ Net-_U9-Pad2_ Net-_X10-Pad4_ 3_and +X11 Net-_U13-Pad4_ Net-_U11-Pad2_ Net-_U8-Pad2_ Net-_X11-Pad4_ 3_and +X9 Net-_X11-Pad4_ Net-_X10-Pad4_ Net-_X8-Pad4_ Net-_X7-Pad4_ Net-_U13-Pad2_ 4_OR +U13 Net-_U1-Pad3_ Net-_U13-Pad2_ Net-_U13-Pad3_ Net-_U13-Pad4_ ? d_flip_flop +U14 Net-_U13-Pad4_ Net-_U14-Pad2_ Net-_U1-Pad10_ buffer_test +X12 Net-_U8-Pad2_ Net-_U12-Pad2_ Net-_U13-Pad4_ Net-_X12-Pad4_ 3_and +X13 Net-_U17-Pad4_ Net-_U11-Pad2_ Net-_U9-Pad2_ Net-_X13-Pad4_ 3_and +X15 Net-_U1-Pad11_ Net-_U12-Pad2_ Net-_U9-Pad2_ Net-_X14-Pad2_ 3_and +X16 Net-_U15-Pad4_ Net-_U11-Pad2_ Net-_U8-Pad2_ Net-_X14-Pad1_ 3_and +X14 Net-_X14-Pad1_ Net-_X14-Pad2_ Net-_X13-Pad4_ Net-_X12-Pad4_ Net-_U15-Pad2_ 4_OR +U15 Net-_U1-Pad3_ Net-_U15-Pad2_ Net-_U13-Pad3_ Net-_U15-Pad4_ ? d_flip_flop +U16 Net-_U15-Pad4_ Net-_U14-Pad2_ Net-_U1-Pad11_ buffer_test +X17 Net-_U8-Pad2_ Net-_U12-Pad2_ Net-_U15-Pad4_ Net-_X17-Pad4_ 3_and +X18 Net-_U19-Pad4_ Net-_U11-Pad2_ Net-_U9-Pad2_ Net-_X18-Pad4_ 3_and +X20 Net-_U1-Pad12_ Net-_U12-Pad2_ Net-_U9-Pad2_ Net-_X19-Pad2_ 3_and +X21 Net-_U17-Pad4_ Net-_U11-Pad2_ Net-_U8-Pad2_ Net-_X19-Pad1_ 3_and +X19 Net-_X19-Pad1_ Net-_X19-Pad2_ Net-_X18-Pad4_ Net-_X17-Pad4_ Net-_U17-Pad2_ 4_OR +U17 Net-_U1-Pad3_ Net-_U17-Pad2_ Net-_U13-Pad3_ Net-_U17-Pad4_ ? d_flip_flop +U18 Net-_U17-Pad4_ Net-_U14-Pad2_ Net-_U1-Pad12_ buffer_test +X22 Net-_U8-Pad2_ Net-_U12-Pad2_ Net-_U17-Pad4_ Net-_X22-Pad4_ 3_and +X23 Net-_U21-Pad4_ Net-_U11-Pad2_ Net-_U9-Pad2_ Net-_X23-Pad4_ 3_and +X25 Net-_U1-Pad13_ Net-_U12-Pad2_ Net-_U9-Pad2_ Net-_X24-Pad2_ 3_and +X26 Net-_U19-Pad4_ Net-_U11-Pad2_ Net-_U8-Pad2_ Net-_X24-Pad1_ 3_and +X24 Net-_X24-Pad1_ Net-_X24-Pad2_ Net-_X23-Pad4_ Net-_X22-Pad4_ Net-_U19-Pad2_ 4_OR +U19 Net-_U1-Pad3_ Net-_U19-Pad2_ Net-_U13-Pad3_ Net-_U19-Pad4_ ? d_flip_flop +U20 Net-_U19-Pad4_ Net-_U14-Pad2_ Net-_U1-Pad13_ buffer_test +X27 Net-_U8-Pad2_ Net-_U12-Pad2_ Net-_U19-Pad4_ Net-_X27-Pad4_ 3_and +X28 Net-_U23-Pad4_ Net-_U11-Pad2_ Net-_U9-Pad2_ Net-_X28-Pad4_ 3_and +X30 Net-_U1-Pad14_ Net-_U12-Pad2_ Net-_U9-Pad2_ Net-_X29-Pad2_ 3_and +X31 Net-_U21-Pad4_ Net-_U11-Pad2_ Net-_U8-Pad2_ Net-_X29-Pad1_ 3_and +X29 Net-_X29-Pad1_ Net-_X29-Pad2_ Net-_X28-Pad4_ Net-_X27-Pad4_ Net-_U21-Pad2_ 4_OR +U21 Net-_U1-Pad3_ Net-_U21-Pad2_ Net-_U13-Pad3_ Net-_U21-Pad4_ ? d_flip_flop +U22 Net-_U21-Pad4_ Net-_U14-Pad2_ Net-_U1-Pad14_ buffer_test +X32 Net-_U8-Pad2_ Net-_U12-Pad2_ Net-_U21-Pad4_ Net-_X32-Pad4_ 3_and +X33 Net-_U1-Pad17_ Net-_U11-Pad2_ Net-_U9-Pad2_ Net-_X33-Pad4_ 3_and +X35 Net-_U1-Pad15_ Net-_U12-Pad2_ Net-_U9-Pad2_ Net-_X34-Pad2_ 3_and +X36 Net-_U23-Pad4_ Net-_U11-Pad2_ Net-_U8-Pad2_ Net-_X34-Pad1_ 3_and +X34 Net-_X34-Pad1_ Net-_X34-Pad2_ Net-_X33-Pad4_ Net-_X32-Pad4_ Net-_U23-Pad2_ 4_OR +U23 Net-_U1-Pad3_ Net-_U23-Pad2_ Net-_U13-Pad3_ Net-_U23-Pad4_ ? d_flip_flop +U24 Net-_U23-Pad4_ Net-_U14-Pad2_ Net-_U1-Pad15_ buffer_test +X37 Net-_U8-Pad2_ Net-_U12-Pad2_ Net-_U23-Pad4_ Net-_X37-Pad4_ 3_and +X38 Net-_U1-Pad18_ Net-_U11-Pad2_ Net-_U9-Pad2_ Net-_X38-Pad4_ 3_and +X40 Net-_U1-Pad16_ Net-_U12-Pad2_ Net-_U9-Pad2_ Net-_X39-Pad2_ 3_and +X41 Net-_U1-Pad17_ Net-_U11-Pad2_ Net-_U8-Pad2_ Net-_X39-Pad1_ 3_and +X39 Net-_X39-Pad1_ Net-_X39-Pad2_ Net-_X38-Pad4_ Net-_X37-Pad4_ Net-_U25-Pad2_ 4_OR +U25 Net-_U1-Pad3_ Net-_U25-Pad2_ Net-_U13-Pad3_ Net-_U1-Pad17_ ? d_flip_flop +U26 Net-_U1-Pad17_ Net-_U14-Pad2_ Net-_U1-Pad16_ buffer_test +U7 Net-_U1-Pad6_ Net-_U13-Pad3_ d_inverter +X1 Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U6-Pad2_ Net-_U14-Pad2_ 3_and +U6 Net-_U1-Pad5_ Net-_U6-Pad2_ d_inverter +U5 Net-_U1-Pad4_ Net-_U5-Pad2_ d_inverter +U4 Net-_U10-Pad3_ Net-_U4-Pad2_ d_inverter +U10 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U10-Pad3_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ PORT + +.end diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/SN74LS299.cir.out b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/SN74LS299.cir.out new file mode 100644 index 000000000..212a75ac1 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/SN74LS299.cir.out @@ -0,0 +1,155 @@ +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\sn74ls299\sn74ls299.cir + +.include 3_and.sub +.include 4_OR.sub +x2 net-_u8-pad2_ net-_u12-pad2_ net-_u1-pad7_ net-_x2-pad4_ 3_and +x3 net-_u13-pad4_ net-_u11-pad2_ net-_u9-pad2_ net-_x3-pad4_ 3_and +x5 net-_u1-pad9_ net-_u12-pad2_ net-_u9-pad2_ net-_x4-pad2_ 3_and +x6 net-_u1-pad8_ net-_u11-pad2_ net-_u8-pad2_ net-_x4-pad1_ 3_and +x4 net-_x4-pad1_ net-_x4-pad2_ net-_x3-pad4_ net-_x2-pad4_ net-_u2-pad2_ 4_OR +* u2 net-_u1-pad3_ net-_u2-pad2_ net-_u13-pad3_ net-_u1-pad8_ ? d_flip_flop +* u3 net-_u1-pad8_ net-_u14-pad2_ net-_u1-pad9_ buffer_test +* u8 net-_u1-pad2_ net-_u8-pad2_ d_inverter +* u9 net-_u8-pad2_ net-_u9-pad2_ d_inverter +* u11 net-_u1-pad1_ net-_u11-pad2_ d_inverter +* u12 net-_u11-pad2_ net-_u12-pad2_ d_inverter +x7 net-_u8-pad2_ net-_u12-pad2_ net-_u1-pad8_ net-_x7-pad4_ 3_and +x8 net-_u15-pad4_ net-_u11-pad2_ net-_u9-pad2_ net-_x8-pad4_ 3_and +x10 net-_u1-pad10_ net-_u12-pad2_ net-_u9-pad2_ net-_x10-pad4_ 3_and +x11 net-_u13-pad4_ net-_u11-pad2_ net-_u8-pad2_ net-_x11-pad4_ 3_and +x9 net-_x11-pad4_ net-_x10-pad4_ net-_x8-pad4_ net-_x7-pad4_ net-_u13-pad2_ 4_OR +* u13 net-_u1-pad3_ net-_u13-pad2_ net-_u13-pad3_ net-_u13-pad4_ ? d_flip_flop +* u14 net-_u13-pad4_ net-_u14-pad2_ net-_u1-pad10_ buffer_test +x12 net-_u8-pad2_ net-_u12-pad2_ net-_u13-pad4_ net-_x12-pad4_ 3_and +x13 net-_u17-pad4_ net-_u11-pad2_ net-_u9-pad2_ net-_x13-pad4_ 3_and +x15 net-_u1-pad11_ net-_u12-pad2_ net-_u9-pad2_ net-_x14-pad2_ 3_and +x16 net-_u15-pad4_ net-_u11-pad2_ net-_u8-pad2_ net-_x14-pad1_ 3_and +x14 net-_x14-pad1_ net-_x14-pad2_ net-_x13-pad4_ net-_x12-pad4_ net-_u15-pad2_ 4_OR +* u15 net-_u1-pad3_ net-_u15-pad2_ net-_u13-pad3_ net-_u15-pad4_ ? d_flip_flop +* u16 net-_u15-pad4_ net-_u14-pad2_ net-_u1-pad11_ buffer_test +x17 net-_u8-pad2_ net-_u12-pad2_ net-_u15-pad4_ net-_x17-pad4_ 3_and +x18 net-_u19-pad4_ net-_u11-pad2_ net-_u9-pad2_ net-_x18-pad4_ 3_and +x20 net-_u1-pad12_ net-_u12-pad2_ net-_u9-pad2_ net-_x19-pad2_ 3_and +x21 net-_u17-pad4_ net-_u11-pad2_ net-_u8-pad2_ net-_x19-pad1_ 3_and +x19 net-_x19-pad1_ net-_x19-pad2_ net-_x18-pad4_ net-_x17-pad4_ net-_u17-pad2_ 4_OR +* u17 net-_u1-pad3_ net-_u17-pad2_ net-_u13-pad3_ net-_u17-pad4_ ? d_flip_flop +* u18 net-_u17-pad4_ net-_u14-pad2_ net-_u1-pad12_ buffer_test +x22 net-_u8-pad2_ net-_u12-pad2_ net-_u17-pad4_ net-_x22-pad4_ 3_and +x23 net-_u21-pad4_ net-_u11-pad2_ net-_u9-pad2_ net-_x23-pad4_ 3_and +x25 net-_u1-pad13_ net-_u12-pad2_ net-_u9-pad2_ net-_x24-pad2_ 3_and +x26 net-_u19-pad4_ net-_u11-pad2_ net-_u8-pad2_ net-_x24-pad1_ 3_and +x24 net-_x24-pad1_ net-_x24-pad2_ net-_x23-pad4_ net-_x22-pad4_ net-_u19-pad2_ 4_OR +* u19 net-_u1-pad3_ net-_u19-pad2_ net-_u13-pad3_ net-_u19-pad4_ ? d_flip_flop +* u20 net-_u19-pad4_ net-_u14-pad2_ net-_u1-pad13_ buffer_test +x27 net-_u8-pad2_ net-_u12-pad2_ net-_u19-pad4_ net-_x27-pad4_ 3_and +x28 net-_u23-pad4_ net-_u11-pad2_ net-_u9-pad2_ net-_x28-pad4_ 3_and +x30 net-_u1-pad14_ net-_u12-pad2_ net-_u9-pad2_ net-_x29-pad2_ 3_and +x31 net-_u21-pad4_ net-_u11-pad2_ net-_u8-pad2_ net-_x29-pad1_ 3_and +x29 net-_x29-pad1_ net-_x29-pad2_ net-_x28-pad4_ net-_x27-pad4_ net-_u21-pad2_ 4_OR +* u21 net-_u1-pad3_ net-_u21-pad2_ net-_u13-pad3_ net-_u21-pad4_ ? d_flip_flop +* u22 net-_u21-pad4_ net-_u14-pad2_ net-_u1-pad14_ buffer_test +x32 net-_u8-pad2_ net-_u12-pad2_ net-_u21-pad4_ net-_x32-pad4_ 3_and +x33 net-_u1-pad17_ net-_u11-pad2_ net-_u9-pad2_ net-_x33-pad4_ 3_and +x35 net-_u1-pad15_ net-_u12-pad2_ net-_u9-pad2_ net-_x34-pad2_ 3_and +x36 net-_u23-pad4_ net-_u11-pad2_ net-_u8-pad2_ net-_x34-pad1_ 3_and +x34 net-_x34-pad1_ net-_x34-pad2_ net-_x33-pad4_ net-_x32-pad4_ net-_u23-pad2_ 4_OR +* u23 net-_u1-pad3_ net-_u23-pad2_ net-_u13-pad3_ net-_u23-pad4_ ? d_flip_flop +* u24 net-_u23-pad4_ net-_u14-pad2_ net-_u1-pad15_ buffer_test +x37 net-_u8-pad2_ net-_u12-pad2_ net-_u23-pad4_ net-_x37-pad4_ 3_and +x38 net-_u1-pad18_ net-_u11-pad2_ net-_u9-pad2_ net-_x38-pad4_ 3_and +x40 net-_u1-pad16_ net-_u12-pad2_ net-_u9-pad2_ net-_x39-pad2_ 3_and +x41 net-_u1-pad17_ net-_u11-pad2_ net-_u8-pad2_ net-_x39-pad1_ 3_and +x39 net-_x39-pad1_ net-_x39-pad2_ net-_x38-pad4_ net-_x37-pad4_ net-_u25-pad2_ 4_OR +* u25 net-_u1-pad3_ net-_u25-pad2_ net-_u13-pad3_ net-_u1-pad17_ ? d_flip_flop +* u26 net-_u1-pad17_ net-_u14-pad2_ net-_u1-pad16_ buffer_test +* u7 net-_u1-pad6_ net-_u13-pad3_ d_inverter +x1 net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u14-pad2_ 3_and +* u6 net-_u1-pad5_ net-_u6-pad2_ d_inverter +* u5 net-_u1-pad4_ net-_u5-pad2_ d_inverter +* u4 net-_u10-pad3_ net-_u4-pad2_ d_inverter +* u10 net-_u1-pad1_ net-_u1-pad2_ net-_u10-pad3_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ port +a1 [net-_u1-pad3_ ] [net-_u2-pad2_ ] [net-_u13-pad3_ ] [net-_u1-pad8_ ] [? ] u2 +a2 [net-_u1-pad8_ ] [net-_u14-pad2_ ] [net-_u1-pad9_ ] u3 +a3 net-_u1-pad2_ net-_u8-pad2_ u8 +a4 net-_u8-pad2_ net-_u9-pad2_ u9 +a5 net-_u1-pad1_ net-_u11-pad2_ u11 +a6 net-_u11-pad2_ net-_u12-pad2_ u12 +a7 [net-_u1-pad3_ ] [net-_u13-pad2_ ] [net-_u13-pad3_ ] [net-_u13-pad4_ ] [? ] u13 +a8 [net-_u13-pad4_ ] [net-_u14-pad2_ ] [net-_u1-pad10_ ] u14 +a9 [net-_u1-pad3_ ] [net-_u15-pad2_ ] [net-_u13-pad3_ ] [net-_u15-pad4_ ] [? ] u15 +a10 [net-_u15-pad4_ ] [net-_u14-pad2_ ] [net-_u1-pad11_ ] u16 +a11 [net-_u1-pad3_ ] [net-_u17-pad2_ ] [net-_u13-pad3_ ] [net-_u17-pad4_ ] [? ] u17 +a12 [net-_u17-pad4_ ] [net-_u14-pad2_ ] [net-_u1-pad12_ ] u18 +a13 [net-_u1-pad3_ ] [net-_u19-pad2_ ] [net-_u13-pad3_ ] [net-_u19-pad4_ ] [? ] u19 +a14 [net-_u19-pad4_ ] [net-_u14-pad2_ ] [net-_u1-pad13_ ] u20 +a15 [net-_u1-pad3_ ] [net-_u21-pad2_ ] [net-_u13-pad3_ ] [net-_u21-pad4_ ] [? ] u21 +a16 [net-_u21-pad4_ ] [net-_u14-pad2_ ] [net-_u1-pad14_ ] u22 +a17 [net-_u1-pad3_ ] [net-_u23-pad2_ ] [net-_u13-pad3_ ] [net-_u23-pad4_ ] [? ] u23 +a18 [net-_u23-pad4_ ] [net-_u14-pad2_ ] [net-_u1-pad15_ ] u24 +a19 [net-_u1-pad3_ ] [net-_u25-pad2_ ] [net-_u13-pad3_ ] [net-_u1-pad17_ ] [? ] u25 +a20 [net-_u1-pad17_ ] [net-_u14-pad2_ ] [net-_u1-pad16_ ] u26 +a21 net-_u1-pad6_ net-_u13-pad3_ u7 +a22 net-_u1-pad5_ net-_u6-pad2_ u6 +a23 net-_u1-pad4_ net-_u5-pad2_ u5 +a24 net-_u10-pad3_ net-_u4-pad2_ u4 +a25 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u10-pad3_ u10 +* Schematic Name: d_flip_flop, NgSpice Name: d_flip_flop +.model u2 d_flip_flop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: buffer_test, NgSpice Name: buffer_test +.model u3 buffer_test(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_flip_flop, NgSpice Name: d_flip_flop +.model u13 d_flip_flop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: buffer_test, NgSpice Name: buffer_test +.model u14 buffer_test(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_flip_flop, NgSpice Name: d_flip_flop +.model u15 d_flip_flop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: buffer_test, NgSpice Name: buffer_test +.model u16 buffer_test(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_flip_flop, NgSpice Name: d_flip_flop +.model u17 d_flip_flop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: buffer_test, NgSpice Name: buffer_test +.model u18 buffer_test(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_flip_flop, NgSpice Name: d_flip_flop +.model u19 d_flip_flop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: buffer_test, NgSpice Name: buffer_test +.model u20 buffer_test(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_flip_flop, NgSpice Name: d_flip_flop +.model u21 d_flip_flop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: buffer_test, NgSpice Name: buffer_test +.model u22 buffer_test(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_flip_flop, NgSpice Name: d_flip_flop +.model u23 d_flip_flop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: buffer_test, NgSpice Name: buffer_test +.model u24 buffer_test(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_flip_flop, NgSpice Name: d_flip_flop +.model u25 d_flip_flop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: buffer_test, NgSpice Name: buffer_test +.model u26 buffer_test(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/SN74LS299.pro b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/SN74LS299.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/SN74LS299.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/SN74LS299.sch b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/SN74LS299.sch new file mode 100644 index 000000000..2b27ed698 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/SN74LS299.sch @@ -0,0 +1,1941 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X2 +U 1 1 68415E95 +P 2000 2350 +F 0 "X2" H 2100 2300 60 0000 C CNN +F 1 "3_and" H 2150 2500 60 0000 C CNN +F 2 "" H 2000 2350 60 0000 C CNN +F 3 "" H 2000 2350 60 0000 C CNN + 1 2000 2350 + 0 1 1 0 +$EndComp +$Comp +L 3_and X3 +U 1 1 68415F1F +P 2400 2350 +F 0 "X3" H 2500 2300 60 0000 C CNN +F 1 "3_and" H 2550 2500 60 0000 C CNN +F 2 "" H 2400 2350 60 0000 C CNN +F 3 "" H 2400 2350 60 0000 C CNN + 1 2400 2350 + 0 1 1 0 +$EndComp +$Comp +L 3_and X5 +U 1 1 68415F3F +P 2800 2350 +F 0 "X5" H 2900 2300 60 0000 C CNN +F 1 "3_and" H 2950 2500 60 0000 C CNN +F 2 "" H 2800 2350 60 0000 C CNN +F 3 "" H 2800 2350 60 0000 C CNN + 1 2800 2350 + 0 1 1 0 +$EndComp +$Comp +L 3_and X6 +U 1 1 68415F66 +P 3200 2350 +F 0 "X6" H 3300 2300 60 0000 C CNN +F 1 "3_and" H 3350 2500 60 0000 C CNN +F 2 "" H 3200 2350 60 0000 C CNN +F 3 "" H 3200 2350 60 0000 C CNN + 1 3200 2350 + 0 1 1 0 +$EndComp +$Comp +L 4_OR X4 +U 1 1 68415FB0 +P 2650 3550 +F 0 "X4" H 2800 3450 60 0000 C CNN +F 1 "4_OR" H 2800 3650 60 0000 C CNN +F 2 "" H 2650 3550 60 0000 C CNN +F 3 "" H 2650 3550 60 0000 C CNN + 1 2650 3550 + 0 1 1 0 +$EndComp +$Comp +L d_flip_flop U2 +U 1 1 6841603D +P -150 6450 +F 0 "U2" H 2700 8250 60 0000 C CNN +F 1 "d_flip_flop" H 2700 8450 60 0000 C CNN +F 2 "" H 2700 8400 60 0000 C CNN +F 3 "" H 2700 8400 60 0000 C CNN + 1 -150 6450 + 1 0 0 -1 +$EndComp +$Comp +L buffer_test U3 +U 1 1 68416248 +P -150 7300 +F 0 "U3" H 2700 9100 60 0000 C CNN +F 1 "buffer_test" H 2700 9300 60 0000 C CNN +F 2 "" H 2700 9250 60 0000 C CNN +F 3 "" H 2700 9250 60 0000 C CNN + 1 -150 7300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U8 +U 1 1 6841639D +P 900 650 +F 0 "U8" H 900 550 60 0000 C CNN +F 1 "d_inverter" H 900 800 60 0000 C CNN +F 2 "" H 950 600 60 0000 C CNN +F 3 "" H 950 600 60 0000 C CNN + 1 900 650 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U9 +U 1 1 68416406 +P 900 1400 +F 0 "U9" H 900 1300 60 0000 C CNN +F 1 "d_inverter" H 900 1550 60 0000 C CNN +F 2 "" H 950 1350 60 0000 C CNN +F 3 "" H 950 1350 60 0000 C CNN + 1 900 1400 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U11 +U 1 1 68416449 +P 1250 450 +F 0 "U11" H 1250 350 60 0000 C CNN +F 1 "d_inverter" H 1250 600 60 0000 C CNN +F 2 "" H 1300 400 60 0000 C CNN +F 3 "" H 1300 400 60 0000 C CNN + 1 1250 450 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U12 +U 1 1 6841647D +P 1250 1200 +F 0 "U12" H 1250 1100 60 0000 C CNN +F 1 "d_inverter" H 1250 1350 60 0000 C CNN +F 2 "" H 1300 1150 60 0000 C CNN +F 3 "" H 1300 1150 60 0000 C CNN + 1 1250 1200 + 0 1 1 0 +$EndComp +$Comp +L 3_and X7 +U 1 1 684172FC +P 4250 2350 +F 0 "X7" H 4350 2300 60 0000 C CNN +F 1 "3_and" H 4400 2500 60 0000 C CNN +F 2 "" H 4250 2350 60 0000 C CNN +F 3 "" H 4250 2350 60 0000 C CNN + 1 4250 2350 + 0 1 1 0 +$EndComp +$Comp +L 3_and X8 +U 1 1 68417302 +P 4650 2350 +F 0 "X8" H 4750 2300 60 0000 C CNN +F 1 "3_and" H 4800 2500 60 0000 C CNN +F 2 "" H 4650 2350 60 0000 C CNN +F 3 "" H 4650 2350 60 0000 C CNN + 1 4650 2350 + 0 1 1 0 +$EndComp +$Comp +L 3_and X10 +U 1 1 68417308 +P 5050 2350 +F 0 "X10" H 5150 2300 60 0000 C CNN +F 1 "3_and" H 5200 2500 60 0000 C CNN +F 2 "" H 5050 2350 60 0000 C CNN +F 3 "" H 5050 2350 60 0000 C CNN + 1 5050 2350 + 0 1 1 0 +$EndComp +$Comp +L 3_and X11 +U 1 1 6841730E +P 5450 2350 +F 0 "X11" H 5550 2300 60 0000 C CNN +F 1 "3_and" H 5600 2500 60 0000 C CNN +F 2 "" H 5450 2350 60 0000 C CNN +F 3 "" H 5450 2350 60 0000 C CNN + 1 5450 2350 + 0 1 1 0 +$EndComp +$Comp +L 4_OR X9 +U 1 1 68417314 +P 4900 3550 +F 0 "X9" H 5050 3450 60 0000 C CNN +F 1 "4_OR" H 5050 3650 60 0000 C CNN +F 2 "" H 4900 3550 60 0000 C CNN +F 3 "" H 4900 3550 60 0000 C CNN + 1 4900 3550 + 0 1 1 0 +$EndComp +$Comp +L d_flip_flop U13 +U 1 1 6841731A +P 2100 6450 +F 0 "U13" H 4950 8250 60 0000 C CNN +F 1 "d_flip_flop" H 4950 8450 60 0000 C CNN +F 2 "" H 4950 8400 60 0000 C CNN +F 3 "" H 4950 8400 60 0000 C CNN + 1 2100 6450 + 1 0 0 -1 +$EndComp +$Comp +L buffer_test U14 +U 1 1 68417320 +P 2100 7300 +F 0 "U14" H 4950 9100 60 0000 C CNN +F 1 "buffer_test" H 4950 9300 60 0000 C CNN +F 2 "" H 4950 9250 60 0000 C CNN +F 3 "" H 4950 9250 60 0000 C CNN + 1 2100 7300 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X12 +U 1 1 68417FCD +P 6650 2350 +F 0 "X12" H 6750 2300 60 0000 C CNN +F 1 "3_and" H 6800 2500 60 0000 C CNN +F 2 "" H 6650 2350 60 0000 C CNN +F 3 "" H 6650 2350 60 0000 C CNN + 1 6650 2350 + 0 1 1 0 +$EndComp +$Comp +L 3_and X13 +U 1 1 68417FD3 +P 7050 2350 +F 0 "X13" H 7150 2300 60 0000 C CNN +F 1 "3_and" H 7200 2500 60 0000 C CNN +F 2 "" H 7050 2350 60 0000 C CNN +F 3 "" H 7050 2350 60 0000 C CNN + 1 7050 2350 + 0 1 1 0 +$EndComp +$Comp +L 3_and X15 +U 1 1 68417FD9 +P 7450 2350 +F 0 "X15" H 7550 2300 60 0000 C CNN +F 1 "3_and" H 7600 2500 60 0000 C CNN +F 2 "" H 7450 2350 60 0000 C CNN +F 3 "" H 7450 2350 60 0000 C CNN + 1 7450 2350 + 0 1 1 0 +$EndComp +$Comp +L 3_and X16 +U 1 1 68417FDF +P 7850 2350 +F 0 "X16" H 7950 2300 60 0000 C CNN +F 1 "3_and" H 8000 2500 60 0000 C CNN +F 2 "" H 7850 2350 60 0000 C CNN +F 3 "" H 7850 2350 60 0000 C CNN + 1 7850 2350 + 0 1 1 0 +$EndComp +$Comp +L 4_OR X14 +U 1 1 68417FE5 +P 7300 3550 +F 0 "X14" H 7450 3450 60 0000 C CNN +F 1 "4_OR" H 7450 3650 60 0000 C CNN +F 2 "" H 7300 3550 60 0000 C CNN +F 3 "" H 7300 3550 60 0000 C CNN + 1 7300 3550 + 0 1 1 0 +$EndComp +$Comp +L d_flip_flop U15 +U 1 1 68417FEB +P 4500 6450 +F 0 "U15" H 7350 8250 60 0000 C CNN +F 1 "d_flip_flop" H 7350 8450 60 0000 C CNN +F 2 "" H 7350 8400 60 0000 C CNN +F 3 "" H 7350 8400 60 0000 C CNN + 1 4500 6450 + 1 0 0 -1 +$EndComp +$Comp +L buffer_test U16 +U 1 1 68417FF1 +P 4500 7300 +F 0 "U16" H 7350 9100 60 0000 C CNN +F 1 "buffer_test" H 7350 9300 60 0000 C CNN +F 2 "" H 7350 9250 60 0000 C CNN +F 3 "" H 7350 9250 60 0000 C CNN + 1 4500 7300 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X17 +U 1 1 68418027 +P 8900 2350 +F 0 "X17" H 9000 2300 60 0000 C CNN +F 1 "3_and" H 9050 2500 60 0000 C CNN +F 2 "" H 8900 2350 60 0000 C CNN +F 3 "" H 8900 2350 60 0000 C CNN + 1 8900 2350 + 0 1 1 0 +$EndComp +$Comp +L 3_and X18 +U 1 1 6841802D +P 9300 2350 +F 0 "X18" H 9400 2300 60 0000 C CNN +F 1 "3_and" H 9450 2500 60 0000 C CNN +F 2 "" H 9300 2350 60 0000 C CNN +F 3 "" H 9300 2350 60 0000 C CNN + 1 9300 2350 + 0 1 1 0 +$EndComp +$Comp +L 3_and X20 +U 1 1 68418033 +P 9700 2350 +F 0 "X20" H 9800 2300 60 0000 C CNN +F 1 "3_and" H 9850 2500 60 0000 C CNN +F 2 "" H 9700 2350 60 0000 C CNN +F 3 "" H 9700 2350 60 0000 C CNN + 1 9700 2350 + 0 1 1 0 +$EndComp +$Comp +L 3_and X21 +U 1 1 68418039 +P 10100 2350 +F 0 "X21" H 10200 2300 60 0000 C CNN +F 1 "3_and" H 10250 2500 60 0000 C CNN +F 2 "" H 10100 2350 60 0000 C CNN +F 3 "" H 10100 2350 60 0000 C CNN + 1 10100 2350 + 0 1 1 0 +$EndComp +$Comp +L 4_OR X19 +U 1 1 6841803F +P 9550 3550 +F 0 "X19" H 9700 3450 60 0000 C CNN +F 1 "4_OR" H 9700 3650 60 0000 C CNN +F 2 "" H 9550 3550 60 0000 C CNN +F 3 "" H 9550 3550 60 0000 C CNN + 1 9550 3550 + 0 1 1 0 +$EndComp +$Comp +L d_flip_flop U17 +U 1 1 68418045 +P 6750 6450 +F 0 "U17" H 9600 8250 60 0000 C CNN +F 1 "d_flip_flop" H 9600 8450 60 0000 C CNN +F 2 "" H 9600 8400 60 0000 C CNN +F 3 "" H 9600 8400 60 0000 C CNN + 1 6750 6450 + 1 0 0 -1 +$EndComp +$Comp +L buffer_test U18 +U 1 1 6841804B +P 6750 7300 +F 0 "U18" H 9600 9100 60 0000 C CNN +F 1 "buffer_test" H 9600 9300 60 0000 C CNN +F 2 "" H 9600 9250 60 0000 C CNN +F 3 "" H 9600 9250 60 0000 C CNN + 1 6750 7300 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X22 +U 1 1 68419061 +P 11300 2350 +F 0 "X22" H 11400 2300 60 0000 C CNN +F 1 "3_and" H 11450 2500 60 0000 C CNN +F 2 "" H 11300 2350 60 0000 C CNN +F 3 "" H 11300 2350 60 0000 C CNN + 1 11300 2350 + 0 1 1 0 +$EndComp +$Comp +L 3_and X23 +U 1 1 68419067 +P 11700 2350 +F 0 "X23" H 11800 2300 60 0000 C CNN +F 1 "3_and" H 11850 2500 60 0000 C CNN +F 2 "" H 11700 2350 60 0000 C CNN +F 3 "" H 11700 2350 60 0000 C CNN + 1 11700 2350 + 0 1 1 0 +$EndComp +$Comp +L 3_and X25 +U 1 1 6841906D +P 12100 2350 +F 0 "X25" H 12200 2300 60 0000 C CNN +F 1 "3_and" H 12250 2500 60 0000 C CNN +F 2 "" H 12100 2350 60 0000 C CNN +F 3 "" H 12100 2350 60 0000 C CNN + 1 12100 2350 + 0 1 1 0 +$EndComp +$Comp +L 3_and X26 +U 1 1 68419073 +P 12500 2350 +F 0 "X26" H 12600 2300 60 0000 C CNN +F 1 "3_and" H 12650 2500 60 0000 C CNN +F 2 "" H 12500 2350 60 0000 C CNN +F 3 "" H 12500 2350 60 0000 C CNN + 1 12500 2350 + 0 1 1 0 +$EndComp +$Comp +L 4_OR X24 +U 1 1 68419079 +P 11950 3550 +F 0 "X24" H 12100 3450 60 0000 C CNN +F 1 "4_OR" H 12100 3650 60 0000 C CNN +F 2 "" H 11950 3550 60 0000 C CNN +F 3 "" H 11950 3550 60 0000 C CNN + 1 11950 3550 + 0 1 1 0 +$EndComp +$Comp +L d_flip_flop U19 +U 1 1 6841907F +P 9150 6450 +F 0 "U19" H 12000 8250 60 0000 C CNN +F 1 "d_flip_flop" H 12000 8450 60 0000 C CNN +F 2 "" H 12000 8400 60 0000 C CNN +F 3 "" H 12000 8400 60 0000 C CNN + 1 9150 6450 + 1 0 0 -1 +$EndComp +$Comp +L buffer_test U20 +U 1 1 68419085 +P 9150 7300 +F 0 "U20" H 12000 9100 60 0000 C CNN +F 1 "buffer_test" H 12000 9300 60 0000 C CNN +F 2 "" H 12000 9250 60 0000 C CNN +F 3 "" H 12000 9250 60 0000 C CNN + 1 9150 7300 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X27 +U 1 1 684190BB +P 13550 2350 +F 0 "X27" H 13650 2300 60 0000 C CNN +F 1 "3_and" H 13700 2500 60 0000 C CNN +F 2 "" H 13550 2350 60 0000 C CNN +F 3 "" H 13550 2350 60 0000 C CNN + 1 13550 2350 + 0 1 1 0 +$EndComp +$Comp +L 3_and X28 +U 1 1 684190C1 +P 13950 2350 +F 0 "X28" H 14050 2300 60 0000 C CNN +F 1 "3_and" H 14100 2500 60 0000 C CNN +F 2 "" H 13950 2350 60 0000 C CNN +F 3 "" H 13950 2350 60 0000 C CNN + 1 13950 2350 + 0 1 1 0 +$EndComp +$Comp +L 3_and X30 +U 1 1 684190C7 +P 14350 2350 +F 0 "X30" H 14450 2300 60 0000 C CNN +F 1 "3_and" H 14500 2500 60 0000 C CNN +F 2 "" H 14350 2350 60 0000 C CNN +F 3 "" H 14350 2350 60 0000 C CNN + 1 14350 2350 + 0 1 1 0 +$EndComp +$Comp +L 3_and X31 +U 1 1 684190CD +P 14750 2350 +F 0 "X31" H 14850 2300 60 0000 C CNN +F 1 "3_and" H 14900 2500 60 0000 C CNN +F 2 "" H 14750 2350 60 0000 C CNN +F 3 "" H 14750 2350 60 0000 C CNN + 1 14750 2350 + 0 1 1 0 +$EndComp +$Comp +L 4_OR X29 +U 1 1 684190D3 +P 14200 3550 +F 0 "X29" H 14350 3450 60 0000 C CNN +F 1 "4_OR" H 14350 3650 60 0000 C CNN +F 2 "" H 14200 3550 60 0000 C CNN +F 3 "" H 14200 3550 60 0000 C CNN + 1 14200 3550 + 0 1 1 0 +$EndComp +$Comp +L d_flip_flop U21 +U 1 1 684190D9 +P 11400 6450 +F 0 "U21" H 14250 8250 60 0000 C CNN +F 1 "d_flip_flop" H 14250 8450 60 0000 C CNN +F 2 "" H 14250 8400 60 0000 C CNN +F 3 "" H 14250 8400 60 0000 C CNN + 1 11400 6450 + 1 0 0 -1 +$EndComp +$Comp +L buffer_test U22 +U 1 1 684190DF +P 11400 7300 +F 0 "U22" H 14250 9100 60 0000 C CNN +F 1 "buffer_test" H 14250 9300 60 0000 C CNN +F 2 "" H 14250 9250 60 0000 C CNN +F 3 "" H 14250 9250 60 0000 C CNN + 1 11400 7300 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X32 +U 1 1 68419115 +P 15950 2350 +F 0 "X32" H 16050 2300 60 0000 C CNN +F 1 "3_and" H 16100 2500 60 0000 C CNN +F 2 "" H 15950 2350 60 0000 C CNN +F 3 "" H 15950 2350 60 0000 C CNN + 1 15950 2350 + 0 1 1 0 +$EndComp +$Comp +L 3_and X33 +U 1 1 6841911B +P 16350 2350 +F 0 "X33" H 16450 2300 60 0000 C CNN +F 1 "3_and" H 16500 2500 60 0000 C CNN +F 2 "" H 16350 2350 60 0000 C CNN +F 3 "" H 16350 2350 60 0000 C CNN + 1 16350 2350 + 0 1 1 0 +$EndComp +$Comp +L 3_and X35 +U 1 1 68419121 +P 16750 2350 +F 0 "X35" H 16850 2300 60 0000 C CNN +F 1 "3_and" H 16900 2500 60 0000 C CNN +F 2 "" H 16750 2350 60 0000 C CNN +F 3 "" H 16750 2350 60 0000 C CNN + 1 16750 2350 + 0 1 1 0 +$EndComp +$Comp +L 3_and X36 +U 1 1 68419127 +P 17150 2350 +F 0 "X36" H 17250 2300 60 0000 C CNN +F 1 "3_and" H 17300 2500 60 0000 C CNN +F 2 "" H 17150 2350 60 0000 C CNN +F 3 "" H 17150 2350 60 0000 C CNN + 1 17150 2350 + 0 1 1 0 +$EndComp +$Comp +L 4_OR X34 +U 1 1 6841912D +P 16600 3550 +F 0 "X34" H 16750 3450 60 0000 C CNN +F 1 "4_OR" H 16750 3650 60 0000 C CNN +F 2 "" H 16600 3550 60 0000 C CNN +F 3 "" H 16600 3550 60 0000 C CNN + 1 16600 3550 + 0 1 1 0 +$EndComp +$Comp +L d_flip_flop U23 +U 1 1 68419133 +P 13800 6450 +F 0 "U23" H 16650 8250 60 0000 C CNN +F 1 "d_flip_flop" H 16650 8450 60 0000 C CNN +F 2 "" H 16650 8400 60 0000 C CNN +F 3 "" H 16650 8400 60 0000 C CNN + 1 13800 6450 + 1 0 0 -1 +$EndComp +$Comp +L buffer_test U24 +U 1 1 68419139 +P 13800 7300 +F 0 "U24" H 16650 9100 60 0000 C CNN +F 1 "buffer_test" H 16650 9300 60 0000 C CNN +F 2 "" H 16650 9250 60 0000 C CNN +F 3 "" H 16650 9250 60 0000 C CNN + 1 13800 7300 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X37 +U 1 1 6841916F +P 18200 2350 +F 0 "X37" H 18300 2300 60 0000 C CNN +F 1 "3_and" H 18350 2500 60 0000 C CNN +F 2 "" H 18200 2350 60 0000 C CNN +F 3 "" H 18200 2350 60 0000 C CNN + 1 18200 2350 + 0 1 1 0 +$EndComp +$Comp +L 3_and X38 +U 1 1 68419175 +P 18600 2350 +F 0 "X38" H 18700 2300 60 0000 C CNN +F 1 "3_and" H 18750 2500 60 0000 C CNN +F 2 "" H 18600 2350 60 0000 C CNN +F 3 "" H 18600 2350 60 0000 C CNN + 1 18600 2350 + 0 1 1 0 +$EndComp +$Comp +L 3_and X40 +U 1 1 6841917B +P 19000 2350 +F 0 "X40" H 19100 2300 60 0000 C CNN +F 1 "3_and" H 19150 2500 60 0000 C CNN +F 2 "" H 19000 2350 60 0000 C CNN +F 3 "" H 19000 2350 60 0000 C CNN + 1 19000 2350 + 0 1 1 0 +$EndComp +$Comp +L 3_and X41 +U 1 1 68419181 +P 19400 2350 +F 0 "X41" H 19500 2300 60 0000 C CNN +F 1 "3_and" H 19550 2500 60 0000 C CNN +F 2 "" H 19400 2350 60 0000 C CNN +F 3 "" H 19400 2350 60 0000 C CNN + 1 19400 2350 + 0 1 1 0 +$EndComp +$Comp +L 4_OR X39 +U 1 1 68419187 +P 18850 3550 +F 0 "X39" H 19000 3450 60 0000 C CNN +F 1 "4_OR" H 19000 3650 60 0000 C CNN +F 2 "" H 18850 3550 60 0000 C CNN +F 3 "" H 18850 3550 60 0000 C CNN + 1 18850 3550 + 0 1 1 0 +$EndComp +$Comp +L d_flip_flop U25 +U 1 1 6841918D +P 16050 6450 +F 0 "U25" H 18900 8250 60 0000 C CNN +F 1 "d_flip_flop" H 18900 8450 60 0000 C CNN +F 2 "" H 18900 8400 60 0000 C CNN +F 3 "" H 18900 8400 60 0000 C CNN + 1 16050 6450 + 1 0 0 -1 +$EndComp +$Comp +L buffer_test U26 +U 1 1 68419193 +P 16050 7300 +F 0 "U26" H 18900 9100 60 0000 C CNN +F 1 "buffer_test" H 18900 9300 60 0000 C CNN +F 2 "" H 18900 9250 60 0000 C CNN +F 3 "" H 18900 9250 60 0000 C CNN + 1 16050 7300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 6842AEF1 +P 850 5050 +F 0 "U7" H 850 4950 60 0000 C CNN +F 1 "d_inverter" H 850 5200 60 0000 C CNN +F 2 "" H 900 5000 60 0000 C CNN +F 3 "" H 900 5000 60 0000 C CNN + 1 850 5050 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X1 +U 1 1 6842E7FE +P 1400 6250 +F 0 "X1" H 1500 6200 60 0000 C CNN +F 1 "3_and" H 1550 6400 60 0000 C CNN +F 2 "" H 1400 6250 60 0000 C CNN +F 3 "" H 1400 6250 60 0000 C CNN + 1 1400 6250 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 6842EA4B +P 650 6300 +F 0 "U6" H 650 6200 60 0000 C CNN +F 1 "d_inverter" H 650 6450 60 0000 C CNN +F 2 "" H 700 6250 60 0000 C CNN +F 3 "" H 700 6250 60 0000 C CNN + 1 650 6300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 6842EB38 +P 650 6200 +F 0 "U5" H 650 6100 60 0000 C CNN +F 1 "d_inverter" H 650 6350 60 0000 C CNN +F 2 "" H 700 6150 60 0000 C CNN +F 3 "" H 700 6150 60 0000 C CNN + 1 650 6200 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 6842EC0C +P 650 6100 +F 0 "U4" H 650 6000 60 0000 C CNN +F 1 "d_inverter" H 650 6250 60 0000 C CNN +F 2 "" H 700 6050 60 0000 C CNN +F 3 "" H 700 6050 60 0000 C CNN + 1 650 6100 + 1 0 0 -1 +$EndComp +$Comp +L d_and U10 +U 1 1 68430CCA +P 1100 2300 +F 0 "U10" H 1100 2300 60 0000 C CNN +F 1 "d_and" H 1150 2400 60 0000 C CNN +F 2 "" H 1100 2300 60 0000 C CNN +F 3 "" H 1100 2300 60 0000 C CNN + 1 1100 2300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1250 750 1250 900 +Wire Wire Line + 900 950 900 1100 +Wire Wire Line + 1250 1500 19050 1500 +Wire Wire Line + 1250 850 1550 850 +Wire Wire Line + 1550 850 1550 1600 +Wire Wire Line + 1550 1600 19450 1600 +Connection ~ 1250 850 +Wire Wire Line + 900 1050 1100 1050 +Wire Wire Line + 1100 1050 1100 1700 +Wire Wire Line + 1100 1700 19350 1700 +Connection ~ 900 1050 +Wire Wire Line + 900 1700 900 1800 +Wire Wire Line + 900 1800 18950 1800 +Wire Wire Line + 2050 2850 2050 3150 +Wire Wire Line + 2050 3150 2500 3150 +Wire Wire Line + 2500 3150 2500 3200 +Wire Wire Line + 2450 2850 2450 3000 +Wire Wire Line + 2450 3000 2600 3000 +Wire Wire Line + 2600 3000 2600 3200 +Wire Wire Line + 2700 3200 2700 2950 +Wire Wire Line + 2700 2950 2850 2950 +Wire Wire Line + 2850 2950 2850 2850 +Wire Wire Line + 2800 3200 3250 3200 +Wire Wire Line + 3250 3200 3250 2850 +Wire Wire Line + 2050 2000 2050 1500 +Connection ~ 2050 1500 +Wire Wire Line + 2150 2000 2150 1700 +Connection ~ 2150 1700 +Wire Wire Line + 2350 2000 2350 1800 +Connection ~ 2350 1800 +Wire Wire Line + 2450 2000 2450 1600 +Connection ~ 2450 1600 +Wire Wire Line + 2750 2000 2750 1800 +Connection ~ 2750 1800 +Wire Wire Line + 2850 2000 2850 1500 +Connection ~ 2850 1500 +Wire Wire Line + 3150 2000 3150 1700 +Connection ~ 3150 1700 +Wire Wire Line + 3250 2000 3250 1600 +Connection ~ 3250 1600 +Wire Wire Line + 2650 4100 1800 4100 +Wire Wire Line + 1800 4100 1800 4650 +Wire Wire Line + 1800 4650 2000 4650 +Wire Wire Line + 3400 5400 3550 5400 +Wire Wire Line + 3550 5400 3550 6050 +Wire Wire Line + 3550 6050 2600 6050 +Wire Wire Line + 2600 6050 2600 6600 +Wire Wire Line + 2950 2000 2950 1900 +Wire Wire Line + 2950 1900 3700 1900 +Wire Wire Line + 3700 1900 3700 5750 +Wire Wire Line + 3700 5750 3550 5750 +Connection ~ 3550 5750 +Wire Wire Line + 3400 4550 3550 4550 +Wire Wire Line + 3550 4550 3550 5100 +Wire Wire Line + 3550 5100 1950 5100 +Wire Wire Line + 1950 5100 1950 5400 +Wire Wire Line + 1950 5400 2000 5400 +Wire Wire Line + 4300 2850 4300 3150 +Wire Wire Line + 4300 3150 4750 3150 +Wire Wire Line + 4750 3150 4750 3200 +Wire Wire Line + 4700 2850 4700 3000 +Wire Wire Line + 4700 3000 4850 3000 +Wire Wire Line + 4850 3000 4850 3200 +Wire Wire Line + 4950 3200 4950 2950 +Wire Wire Line + 4950 2950 5100 2950 +Wire Wire Line + 5100 2950 5100 2850 +Wire Wire Line + 5050 3200 5500 3200 +Wire Wire Line + 5500 3200 5500 2850 +Wire Wire Line + 4300 2000 4300 1500 +Connection ~ 4300 1500 +Wire Wire Line + 4400 2000 4400 1700 +Connection ~ 4400 1700 +Wire Wire Line + 4600 2000 4600 1800 +Connection ~ 4600 1800 +Wire Wire Line + 4700 2000 4700 1600 +Connection ~ 4700 1600 +Wire Wire Line + 5000 2000 5000 1800 +Connection ~ 5000 1800 +Wire Wire Line + 5100 2000 5100 1500 +Connection ~ 5100 1500 +Wire Wire Line + 5400 2000 5400 1700 +Connection ~ 5400 1700 +Wire Wire Line + 5500 2000 5500 1600 +Connection ~ 5500 1600 +Wire Wire Line + 4900 4100 4050 4100 +Wire Wire Line + 4050 4650 4250 4650 +Wire Wire Line + 5650 5400 5800 5400 +Wire Wire Line + 5800 5400 5800 6050 +Wire Wire Line + 5800 6050 4850 6050 +Wire Wire Line + 4850 6050 4850 6600 +Wire Wire Line + 5200 2000 5200 1900 +Wire Wire Line + 5200 1900 5950 1900 +Wire Wire Line + 5950 1900 5950 5750 +Wire Wire Line + 5950 5750 5800 5750 +Connection ~ 5800 5750 +Wire Wire Line + 5650 4550 5800 4550 +Wire Wire Line + 5800 5100 4200 5100 +Wire Wire Line + 4200 5100 4200 5400 +Wire Wire Line + 4200 5400 4250 5400 +Wire Wire Line + 4050 4100 4050 4650 +Wire Wire Line + 6700 2850 6700 3150 +Wire Wire Line + 6700 3150 7150 3150 +Wire Wire Line + 7150 3150 7150 3200 +Wire Wire Line + 7100 2850 7100 3000 +Wire Wire Line + 7100 3000 7250 3000 +Wire Wire Line + 7250 3000 7250 3200 +Wire Wire Line + 7350 3200 7350 2950 +Wire Wire Line + 7350 2950 7500 2950 +Wire Wire Line + 7500 2950 7500 2850 +Wire Wire Line + 7450 3200 7900 3200 +Wire Wire Line + 7900 3200 7900 2850 +Wire Wire Line + 6700 2000 6700 1500 +Connection ~ 6700 1500 +Wire Wire Line + 6800 2000 6800 1700 +Connection ~ 6800 1700 +Wire Wire Line + 7000 2000 7000 1800 +Connection ~ 7000 1800 +Wire Wire Line + 7100 2000 7100 1600 +Connection ~ 7100 1600 +Wire Wire Line + 7400 2000 7400 1800 +Connection ~ 7400 1800 +Wire Wire Line + 7500 2000 7500 1500 +Connection ~ 7500 1500 +Wire Wire Line + 7800 2000 7800 1700 +Connection ~ 7800 1700 +Wire Wire Line + 7900 2000 7900 1600 +Connection ~ 7900 1600 +Wire Wire Line + 7300 4100 6450 4100 +Wire Wire Line + 6450 4100 6450 4650 +Wire Wire Line + 6450 4650 6650 4650 +Wire Wire Line + 8050 5400 8200 5400 +Wire Wire Line + 8200 5400 8200 6050 +Wire Wire Line + 8200 6050 7250 6050 +Wire Wire Line + 7250 6050 7250 6600 +Wire Wire Line + 7600 2000 7600 1900 +Wire Wire Line + 7600 1900 8350 1900 +Wire Wire Line + 8350 1900 8350 5750 +Wire Wire Line + 8350 5750 8200 5750 +Connection ~ 8200 5750 +Wire Wire Line + 8050 4550 8200 4550 +Wire Wire Line + 8200 4550 8200 5100 +Wire Wire Line + 8200 5100 6600 5100 +Wire Wire Line + 6600 5100 6600 5400 +Wire Wire Line + 6600 5400 6650 5400 +Wire Wire Line + 8950 2850 8950 3150 +Wire Wire Line + 8950 3150 9400 3150 +Wire Wire Line + 9400 3150 9400 3200 +Wire Wire Line + 9350 2850 9350 3000 +Wire Wire Line + 9350 3000 9500 3000 +Wire Wire Line + 9500 3000 9500 3200 +Wire Wire Line + 9600 3200 9600 2950 +Wire Wire Line + 9600 2950 9750 2950 +Wire Wire Line + 9750 2950 9750 2850 +Wire Wire Line + 9700 3200 10150 3200 +Wire Wire Line + 10150 3200 10150 2850 +Wire Wire Line + 8950 2000 8950 1500 +Connection ~ 8950 1500 +Wire Wire Line + 9050 2000 9050 1700 +Connection ~ 9050 1700 +Wire Wire Line + 9250 2000 9250 1800 +Connection ~ 9250 1800 +Wire Wire Line + 9350 2000 9350 1600 +Connection ~ 9350 1600 +Wire Wire Line + 9650 2000 9650 1800 +Connection ~ 9650 1800 +Wire Wire Line + 9750 2000 9750 1500 +Connection ~ 9750 1500 +Wire Wire Line + 10050 2000 10050 1700 +Connection ~ 10050 1700 +Wire Wire Line + 10150 2000 10150 1600 +Connection ~ 10150 1600 +Wire Wire Line + 9550 4100 8700 4100 +Wire Wire Line + 8700 4650 8900 4650 +Wire Wire Line + 10300 5400 10450 5400 +Wire Wire Line + 10450 5400 10450 6050 +Wire Wire Line + 10450 6050 9500 6050 +Wire Wire Line + 9500 6050 9500 6600 +Wire Wire Line + 9850 2000 9850 1900 +Wire Wire Line + 9850 1900 10600 1900 +Wire Wire Line + 10600 1900 10600 5750 +Wire Wire Line + 10600 5750 10450 5750 +Connection ~ 10450 5750 +Wire Wire Line + 10300 4550 10450 4550 +Wire Wire Line + 10450 4550 10450 5100 +Wire Wire Line + 10450 5100 8850 5100 +Wire Wire Line + 8850 5100 8850 5400 +Wire Wire Line + 8850 5400 8900 5400 +Wire Wire Line + 8700 4100 8700 4650 +Wire Wire Line + 11350 2850 11350 3150 +Wire Wire Line + 11350 3150 11800 3150 +Wire Wire Line + 11800 3150 11800 3200 +Wire Wire Line + 11750 2850 11750 3000 +Wire Wire Line + 11750 3000 11900 3000 +Wire Wire Line + 11900 3000 11900 3200 +Wire Wire Line + 12000 3200 12000 2950 +Wire Wire Line + 12000 2950 12150 2950 +Wire Wire Line + 12150 2950 12150 2850 +Wire Wire Line + 12100 3200 12550 3200 +Wire Wire Line + 12550 3200 12550 2850 +Wire Wire Line + 11350 2000 11350 1500 +Connection ~ 11350 1500 +Wire Wire Line + 11450 2000 11450 1700 +Connection ~ 11450 1700 +Wire Wire Line + 11650 2000 11650 1800 +Connection ~ 11650 1800 +Wire Wire Line + 11750 2000 11750 1600 +Connection ~ 11750 1600 +Wire Wire Line + 12050 2000 12050 1800 +Connection ~ 12050 1800 +Wire Wire Line + 12150 2000 12150 1500 +Connection ~ 12150 1500 +Wire Wire Line + 12450 2000 12450 1700 +Connection ~ 12450 1700 +Wire Wire Line + 12550 2000 12550 1600 +Connection ~ 12550 1600 +Wire Wire Line + 11950 4100 11100 4100 +Wire Wire Line + 11100 4100 11100 4650 +Wire Wire Line + 11100 4650 11300 4650 +Wire Wire Line + 12700 5400 12850 5400 +Wire Wire Line + 12850 5400 12850 6050 +Wire Wire Line + 12850 6050 11900 6050 +Wire Wire Line + 11900 6050 11900 6600 +Wire Wire Line + 12250 2000 12250 1900 +Wire Wire Line + 12250 1900 13000 1900 +Wire Wire Line + 13000 1900 13000 5750 +Wire Wire Line + 13000 5750 12850 5750 +Connection ~ 12850 5750 +Wire Wire Line + 12700 4550 12850 4550 +Wire Wire Line + 12850 4550 12850 5100 +Wire Wire Line + 12850 5100 11250 5100 +Wire Wire Line + 11250 5100 11250 5400 +Wire Wire Line + 11250 5400 11300 5400 +Wire Wire Line + 13600 2850 13600 3150 +Wire Wire Line + 13600 3150 14050 3150 +Wire Wire Line + 14050 3150 14050 3200 +Wire Wire Line + 14000 2850 14000 3000 +Wire Wire Line + 14000 3000 14150 3000 +Wire Wire Line + 14150 3000 14150 3200 +Wire Wire Line + 14250 3200 14250 2950 +Wire Wire Line + 14250 2950 14400 2950 +Wire Wire Line + 14400 2950 14400 2850 +Wire Wire Line + 14350 3200 14800 3200 +Wire Wire Line + 14800 3200 14800 2850 +Wire Wire Line + 13600 2000 13600 1500 +Connection ~ 13600 1500 +Wire Wire Line + 13700 2000 13700 1700 +Connection ~ 13700 1700 +Wire Wire Line + 13900 2000 13900 1800 +Connection ~ 13900 1800 +Wire Wire Line + 14000 2000 14000 1600 +Connection ~ 14000 1600 +Wire Wire Line + 14300 2000 14300 1800 +Connection ~ 14300 1800 +Wire Wire Line + 14400 2000 14400 1500 +Connection ~ 14400 1500 +Wire Wire Line + 14700 2000 14700 1700 +Connection ~ 14700 1700 +Wire Wire Line + 14800 2000 14800 1600 +Connection ~ 14800 1600 +Wire Wire Line + 14200 4100 13350 4100 +Wire Wire Line + 13350 4650 13550 4650 +Wire Wire Line + 14950 5400 15100 5400 +Wire Wire Line + 15100 5400 15100 6050 +Wire Wire Line + 15100 6050 14150 6050 +Wire Wire Line + 14150 6050 14150 6600 +Wire Wire Line + 14500 2000 14500 1900 +Wire Wire Line + 14500 1900 15250 1900 +Wire Wire Line + 15250 1900 15250 5750 +Wire Wire Line + 15250 5750 15100 5750 +Connection ~ 15100 5750 +Wire Wire Line + 14950 4550 15100 4550 +Wire Wire Line + 15100 4550 15100 5100 +Wire Wire Line + 15100 5100 13500 5100 +Wire Wire Line + 13500 5100 13500 5400 +Wire Wire Line + 13500 5400 13550 5400 +Wire Wire Line + 13350 4100 13350 4650 +Wire Wire Line + 16000 2850 16000 3150 +Wire Wire Line + 16000 3150 16450 3150 +Wire Wire Line + 16450 3150 16450 3200 +Wire Wire Line + 16400 2850 16400 3000 +Wire Wire Line + 16400 3000 16550 3000 +Wire Wire Line + 16550 3000 16550 3200 +Wire Wire Line + 16650 3200 16650 2950 +Wire Wire Line + 16650 2950 16800 2950 +Wire Wire Line + 16800 2950 16800 2850 +Wire Wire Line + 16750 3200 17200 3200 +Wire Wire Line + 17200 3200 17200 2850 +Wire Wire Line + 16000 2000 16000 1500 +Connection ~ 16000 1500 +Wire Wire Line + 16100 2000 16100 1700 +Connection ~ 16100 1700 +Wire Wire Line + 16300 2000 16300 1800 +Connection ~ 16300 1800 +Wire Wire Line + 16400 2000 16400 1600 +Connection ~ 16400 1600 +Wire Wire Line + 16700 2000 16700 1800 +Connection ~ 16700 1800 +Wire Wire Line + 16800 2000 16800 1500 +Connection ~ 16800 1500 +Wire Wire Line + 17100 2000 17100 1700 +Connection ~ 17100 1700 +Wire Wire Line + 17200 2000 17200 1600 +Connection ~ 17200 1600 +Wire Wire Line + 16600 4100 15750 4100 +Wire Wire Line + 15750 4100 15750 4650 +Wire Wire Line + 15750 4650 15950 4650 +Wire Wire Line + 17350 5400 17500 5400 +Wire Wire Line + 17500 5400 17500 6050 +Wire Wire Line + 17500 6050 16550 6050 +Wire Wire Line + 16550 6050 16550 6600 +Wire Wire Line + 16900 2000 16900 1900 +Wire Wire Line + 16900 1900 17650 1900 +Wire Wire Line + 17650 1900 17650 5750 +Wire Wire Line + 17650 5750 17500 5750 +Connection ~ 17500 5750 +Wire Wire Line + 17350 4550 17500 4550 +Wire Wire Line + 17500 4550 17500 5100 +Wire Wire Line + 17500 5100 15900 5100 +Wire Wire Line + 15900 5100 15900 5400 +Wire Wire Line + 15900 5400 15950 5400 +Wire Wire Line + 18250 2850 18250 3150 +Wire Wire Line + 18250 3150 18700 3150 +Wire Wire Line + 18700 3150 18700 3200 +Wire Wire Line + 18650 2850 18650 3000 +Wire Wire Line + 18650 3000 18800 3000 +Wire Wire Line + 18800 3000 18800 3200 +Wire Wire Line + 18900 3200 18900 2950 +Wire Wire Line + 18900 2950 19050 2950 +Wire Wire Line + 19050 2950 19050 2850 +Wire Wire Line + 19000 3200 19450 3200 +Wire Wire Line + 19450 3200 19450 2850 +Wire Wire Line + 18350 2000 18350 1700 +Connection ~ 18350 1700 +Wire Wire Line + 18550 2000 18550 1800 +Connection ~ 18550 1800 +Wire Wire Line + 18950 1800 18950 2000 +Wire Wire Line + 19050 1500 19050 2000 +Wire Wire Line + 19350 1700 19350 2000 +Wire Wire Line + 19450 1600 19450 2000 +Wire Wire Line + 18850 4100 18000 4100 +Wire Wire Line + 18000 4650 18200 4650 +Wire Wire Line + 19600 5400 19750 5400 +Wire Wire Line + 19750 5400 19750 6050 +Wire Wire Line + 19750 6050 18800 6050 +Wire Wire Line + 18800 6050 18800 6600 +Wire Wire Line + 19150 2000 19150 1900 +Wire Wire Line + 19150 1900 19900 1900 +Wire Wire Line + 19900 1900 19900 5750 +Wire Wire Line + 19900 5750 19750 5750 +Connection ~ 19750 5750 +Wire Wire Line + 19600 4550 19750 4550 +Wire Wire Line + 19750 4550 19750 5100 +Wire Wire Line + 19750 5100 18150 5100 +Wire Wire Line + 18150 5100 18150 5400 +Wire Wire Line + 18150 5400 18200 5400 +Wire Wire Line + 18000 4100 18000 4650 +Wire Wire Line + 18250 2000 18250 1500 +Connection ~ 18250 1500 +Wire Wire Line + 18650 2000 18650 1600 +Connection ~ 18650 1600 +Wire Wire Line + 3350 2000 3350 1950 +Wire Wire Line + 3350 1950 4200 1950 +Wire Wire Line + 4200 1950 4200 2000 +Wire Wire Line + 5600 2000 5600 1950 +Wire Wire Line + 5600 1950 6600 1950 +Wire Wire Line + 6600 1950 6600 2000 +Wire Wire Line + 8000 2000 8000 1950 +Wire Wire Line + 8000 1950 8850 1950 +Wire Wire Line + 8850 1950 8850 2000 +Wire Wire Line + 10250 2000 10250 1950 +Wire Wire Line + 10250 1950 11250 1950 +Wire Wire Line + 11250 1950 11250 2000 +Wire Wire Line + 12650 2000 12650 1950 +Wire Wire Line + 12650 1950 13500 1950 +Wire Wire Line + 13500 1950 13500 2000 +Wire Wire Line + 14900 2000 14900 1950 +Wire Wire Line + 14900 1950 15900 1950 +Wire Wire Line + 15900 1950 15900 2000 +Wire Wire Line + 17300 2000 17300 1950 +Wire Wire Line + 17300 1950 18150 1950 +Wire Wire Line + 18150 1950 18150 2000 +Wire Wire Line + 2550 2000 2550 1850 +Wire Wire Line + 2550 1850 3800 1850 +Wire Wire Line + 3800 1850 3800 5000 +Wire Wire Line + 3800 5000 6100 5000 +Wire Wire Line + 6100 5000 6100 1950 +Connection ~ 6100 1950 +Wire Wire Line + 5800 4550 5800 5100 +Connection ~ 5800 5000 +Wire Wire Line + 4800 2000 4800 1850 +Wire Wire Line + 4800 1850 6250 1850 +Wire Wire Line + 6250 1850 6250 5000 +Wire Wire Line + 10700 5000 10700 1950 +Connection ~ 10700 1950 +Wire Wire Line + 9450 1850 9450 2000 +Wire Wire Line + 9450 1850 10900 1850 +Wire Wire Line + 10900 1850 10900 5050 +Wire Wire Line + 10900 5050 13150 5050 +Wire Wire Line + 13150 5050 13150 1950 +Connection ~ 13150 1950 +Wire Wire Line + 11850 2000 11850 1850 +Wire Wire Line + 11850 1850 13250 1850 +Wire Wire Line + 13250 1850 13250 5050 +Wire Wire Line + 13250 5050 15400 5050 +Wire Wire Line + 15400 5050 15400 1950 +Connection ~ 15400 1950 +Wire Wire Line + 14100 2000 14100 1850 +Wire Wire Line + 14100 1850 15600 1850 +Wire Wire Line + 15600 1850 15600 5050 +Wire Wire Line + 15600 5050 17800 5050 +Wire Wire Line + 17800 5050 17800 1950 +Connection ~ 17800 1950 +Wire Wire Line + 18750 2000 18750 1850 +Wire Wire Line + 18750 1850 20450 1850 +Wire Wire Line + 16500 2000 16500 1850 +Wire Wire Line + 16500 1850 17900 1850 +Wire Wire Line + 17900 1850 17900 5000 +Wire Wire Line + 17900 5000 20400 5000 +Wire Wire Line + 19550 2000 19550 1950 +Wire Wire Line + 19550 1950 19800 1950 +Wire Wire Line + 19800 1950 19800 5000 +Connection ~ 19800 5000 +Connection ~ 8200 5000 +Connection ~ 10450 5000 +Connection ~ 12850 5050 +Connection ~ 15100 5050 +Connection ~ 17500 5050 +Connection ~ 19750 5000 +Wire Wire Line + 100 4200 18200 4200 +Wire Wire Line + 18200 4200 18200 4550 +Wire Wire Line + 15950 4550 15850 4550 +Wire Wire Line + 15850 4550 15850 4200 +Connection ~ 15850 4200 +Wire Wire Line + 13550 4550 13450 4550 +Wire Wire Line + 13450 4550 13450 4200 +Connection ~ 13450 4200 +Wire Wire Line + 11300 4550 11250 4550 +Wire Wire Line + 11250 4550 11250 4200 +Connection ~ 11250 4200 +Wire Wire Line + 8900 4550 8800 4550 +Wire Wire Line + 8800 4550 8800 4200 +Connection ~ 8800 4200 +Wire Wire Line + 6650 4550 6550 4550 +Wire Wire Line + 6550 4550 6550 4200 +Connection ~ 6550 4200 +Wire Wire Line + 4250 4550 4150 4550 +Wire Wire Line + 4150 4550 4150 4200 +Connection ~ 4150 4200 +Wire Wire Line + 2000 4550 1950 4550 +Wire Wire Line + 1950 4550 1950 4200 +Connection ~ 1950 4200 +Wire Wire Line + 550 5050 150 5050 +Wire Wire Line + 1150 5050 10800 5050 +Wire Wire Line + 10800 5050 10800 5150 +Wire Wire Line + 10800 5150 18050 5150 +Wire Wire Line + 18050 5150 18050 4750 +Wire Wire Line + 18050 4750 18200 4750 +Wire Wire Line + 15950 4750 15750 4750 +Wire Wire Line + 15750 4750 15750 5150 +Connection ~ 15750 5150 +Wire Wire Line + 13550 4750 13350 4750 +Wire Wire Line + 13350 4750 13350 5150 +Connection ~ 13350 5150 +Wire Wire Line + 11300 4750 11050 4750 +Wire Wire Line + 11050 4750 11050 5150 +Connection ~ 11050 5150 +Wire Wire Line + 8900 4750 8700 4750 +Wire Wire Line + 8700 4750 8700 5050 +Connection ~ 8700 5050 +Wire Wire Line + 6650 4750 6400 4750 +Wire Wire Line + 6400 4750 6400 5050 +Connection ~ 6400 5050 +Wire Wire Line + 4250 4750 4050 4750 +Wire Wire Line + 4050 4750 4050 5050 +Connection ~ 4050 5050 +Wire Wire Line + 2000 4750 1850 4750 +Wire Wire Line + 1850 4750 1850 5050 +Connection ~ 1850 5050 +Wire Wire Line + 1950 2000 -400 2000 +Wire Wire Line + 950 6100 1050 6100 +Wire Wire Line + 1050 6200 950 6200 +Wire Wire Line + 950 6300 1050 6300 +Wire Wire Line + 900 350 900 -50 +Wire Wire Line + 1250 150 1250 -50 +Wire Wire Line + 650 2300 300 2300 +Wire Wire Line + 300 2300 300 200 +Wire Wire Line + 300 200 900 200 +Connection ~ 900 200 +Wire Wire Line + 650 2200 650 50 +Wire Wire Line + 650 50 1250 50 +Connection ~ 1250 50 +Wire Wire Line + 350 6100 100 6100 +Wire Wire Line + 100 6100 100 5450 +Wire Wire Line + 100 5450 1550 5450 +Wire Wire Line + 1550 5450 1550 2250 +Wire Wire Line + 350 6200 -350 6200 +Wire Wire Line + 350 6300 -350 6300 +Wire Wire Line + 1900 6200 18200 6200 +Wire Wire Line + 18200 6200 18200 5500 +Wire Wire Line + 15950 5500 15950 6200 +Connection ~ 15950 6200 +Wire Wire Line + 13550 5500 13550 6200 +Connection ~ 13550 6200 +Wire Wire Line + 11300 5500 11150 5500 +Wire Wire Line + 11150 5500 11150 6200 +Connection ~ 11150 6200 +Wire Wire Line + 8900 5500 8700 5500 +Wire Wire Line + 8700 5500 8700 6200 +Connection ~ 8700 6200 +Wire Wire Line + 6650 5500 6450 5500 +Wire Wire Line + 6450 5500 6450 6200 +Connection ~ 6450 6200 +Wire Wire Line + 4250 5500 4100 5500 +Wire Wire Line + 4100 5500 4100 6200 +Connection ~ 4100 6200 +Wire Wire Line + 2000 5500 2000 6200 +Connection ~ 2000 6200 +Wire Wire Line + 3600 1950 3600 5000 +Wire Wire Line + 3600 5000 1250 5000 +Wire Wire Line + 1250 5000 1250 4800 +Wire Wire Line + 1250 4800 150 4800 +Connection ~ 3600 1950 +Connection ~ 3550 5000 +NoConn ~ 3400 4650 +NoConn ~ 5650 4650 +NoConn ~ 8050 4650 +NoConn ~ 10300 4650 +NoConn ~ 12700 4650 +NoConn ~ 14950 4650 +NoConn ~ 17350 4650 +NoConn ~ 19600 4650 +$Comp +L PORT U1 +U 7 1 6843B39D +P -650 2000 +F 0 "U1" H -600 2100 30 0000 C CNN +F 1 "PORT" H -650 2000 30 0000 C CNN +F 2 "" H -650 2000 60 0000 C CNN +F 3 "" H -650 2000 60 0000 C CNN + 7 -650 2000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 6843B5FF +P -100 4800 +F 0 "U1" H -50 4900 30 0000 C CNN +F 1 "PORT" H -100 4800 30 0000 C CNN +F 2 "" H -100 4800 60 0000 C CNN +F 3 "" H -100 4800 60 0000 C CNN + 8 -100 4800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 6843BA70 +P 1250 -300 +F 0 "U1" H 1300 -200 30 0000 C CNN +F 1 "PORT" H 1250 -300 30 0000 C CNN +F 2 "" H 1250 -300 60 0000 C CNN +F 3 "" H 1250 -300 60 0000 C CNN + 1 1250 -300 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 6843BF71 +P -600 6200 +F 0 "U1" H -550 6300 30 0000 C CNN +F 1 "PORT" H -600 6200 30 0000 C CNN +F 2 "" H -600 6200 60 0000 C CNN +F 3 "" H -600 6200 60 0000 C CNN + 4 -600 6200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 6843C06A +P -600 6400 +F 0 "U1" H -550 6500 30 0000 C CNN +F 1 "PORT" H -600 6400 30 0000 C CNN +F 2 "" H -600 6400 60 0000 C CNN +F 3 "" H -600 6400 60 0000 C CNN + 5 -600 6400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 6843C25F +P -100 5050 +F 0 "U1" H -50 5150 30 0000 C CNN +F 1 "PORT" H -100 5050 30 0000 C CNN +F 2 "" H -100 5050 60 0000 C CNN +F 3 "" H -100 5050 60 0000 C CNN + 6 -100 5050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 6843C504 +P 900 -300 +F 0 "U1" H 950 -200 30 0000 C CNN +F 1 "PORT" H 900 -300 30 0000 C CNN +F 2 "" H 900 -300 60 0000 C CNN +F 3 "" H 900 -300 60 0000 C CNN + 2 900 -300 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 6843C5BD +P -150 4200 +F 0 "U1" H -100 4300 30 0000 C CNN +F 1 "PORT" H -150 4200 30 0000 C CNN +F 2 "" H -150 4200 60 0000 C CNN +F 3 "" H -150 4200 60 0000 C CNN + 3 -150 4200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 6843CDA8 +P 2600 6850 +F 0 "U1" H 2650 6950 30 0000 C CNN +F 1 "PORT" H 2600 6850 30 0000 C CNN +F 2 "" H 2600 6850 60 0000 C CNN +F 3 "" H 2600 6850 60 0000 C CNN + 9 2600 6850 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 10 1 6843CE63 +P 4850 6850 +F 0 "U1" H 4900 6950 30 0000 C CNN +F 1 "PORT" H 4850 6850 30 0000 C CNN +F 2 "" H 4850 6850 60 0000 C CNN +F 3 "" H 4850 6850 60 0000 C CNN + 10 4850 6850 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 11 1 6843D1F8 +P 7250 6850 +F 0 "U1" H 7300 6950 30 0000 C CNN +F 1 "PORT" H 7250 6850 30 0000 C CNN +F 2 "" H 7250 6850 60 0000 C CNN +F 3 "" H 7250 6850 60 0000 C CNN + 11 7250 6850 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 12 1 6843D8C1 +P 9500 6850 +F 0 "U1" H 9550 6950 30 0000 C CNN +F 1 "PORT" H 9500 6850 30 0000 C CNN +F 2 "" H 9500 6850 60 0000 C CNN +F 3 "" H 9500 6850 60 0000 C CNN + 12 9500 6850 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 13 1 6843DCDE +P 11900 6850 +F 0 "U1" H 11950 6950 30 0000 C CNN +F 1 "PORT" H 11900 6850 30 0000 C CNN +F 2 "" H 11900 6850 60 0000 C CNN +F 3 "" H 11900 6850 60 0000 C CNN + 13 11900 6850 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 14 1 6843DF2A +P 14150 6850 +F 0 "U1" H 14200 6950 30 0000 C CNN +F 1 "PORT" H 14150 6850 30 0000 C CNN +F 2 "" H 14150 6850 60 0000 C CNN +F 3 "" H 14150 6850 60 0000 C CNN + 14 14150 6850 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 15 1 6843E181 +P 16550 6850 +F 0 "U1" H 16600 6950 30 0000 C CNN +F 1 "PORT" H 16550 6850 30 0000 C CNN +F 2 "" H 16550 6850 60 0000 C CNN +F 3 "" H 16550 6850 60 0000 C CNN + 15 16550 6850 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 16 1 6843E333 +P 18800 6850 +F 0 "U1" H 18850 6950 30 0000 C CNN +F 1 "PORT" H 18800 6850 30 0000 C CNN +F 2 "" H 18800 6850 60 0000 C CNN +F 3 "" H 18800 6850 60 0000 C CNN + 16 18800 6850 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 17 1 6843E74E +P 20650 5000 +F 0 "U1" H 20700 5100 30 0000 C CNN +F 1 "PORT" H 20650 5000 30 0000 C CNN +F 2 "" H 20650 5000 60 0000 C CNN +F 3 "" H 20650 5000 60 0000 C CNN + 17 20650 5000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 18 1 6843EE3A +P 20700 1850 +F 0 "U1" H 20750 1950 30 0000 C CNN +F 1 "PORT" H 20700 1850 30 0000 C CNN +F 2 "" H 20700 1850 60 0000 C CNN +F 3 "" H 20700 1850 60 0000 C CNN + 18 20700 1850 + -1 0 0 1 +$EndComp +Wire Wire Line + -350 6300 -350 6400 +Wire Wire Line + 6250 5000 8450 5000 +Wire Wire Line + 8450 5000 8450 1950 +Connection ~ 8450 1950 +Wire Wire Line + 7200 1850 8550 1850 +Wire Wire Line + 8550 1850 8550 5000 +Wire Wire Line + 8550 5000 10700 5000 +Wire Wire Line + 7200 2000 7200 1850 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/SN74LS299.sub b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/SN74LS299.sub new file mode 100644 index 000000000..e3cf980ae --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/SN74LS299.sub @@ -0,0 +1,149 @@ +* Subcircuit SN74LS299 +.subckt SN74LS299 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\sn74ls299\sn74ls299.cir +.include 3_and.sub +.include 4_OR.sub +x2 net-_u8-pad2_ net-_u12-pad2_ net-_u1-pad7_ net-_x2-pad4_ 3_and +x3 net-_u13-pad4_ net-_u11-pad2_ net-_u9-pad2_ net-_x3-pad4_ 3_and +x5 net-_u1-pad9_ net-_u12-pad2_ net-_u9-pad2_ net-_x4-pad2_ 3_and +x6 net-_u1-pad8_ net-_u11-pad2_ net-_u8-pad2_ net-_x4-pad1_ 3_and +x4 net-_x4-pad1_ net-_x4-pad2_ net-_x3-pad4_ net-_x2-pad4_ net-_u2-pad2_ 4_OR +* u2 net-_u1-pad3_ net-_u2-pad2_ net-_u13-pad3_ net-_u1-pad8_ ? d_flip_flop +* u3 net-_u1-pad8_ net-_u14-pad2_ net-_u1-pad9_ buffer_test +* u8 net-_u1-pad2_ net-_u8-pad2_ d_inverter +* u9 net-_u8-pad2_ net-_u9-pad2_ d_inverter +* u11 net-_u1-pad1_ net-_u11-pad2_ d_inverter +* u12 net-_u11-pad2_ net-_u12-pad2_ d_inverter +x7 net-_u8-pad2_ net-_u12-pad2_ net-_u1-pad8_ net-_x7-pad4_ 3_and +x8 net-_u15-pad4_ net-_u11-pad2_ net-_u9-pad2_ net-_x8-pad4_ 3_and +x10 net-_u1-pad10_ net-_u12-pad2_ net-_u9-pad2_ net-_x10-pad4_ 3_and +x11 net-_u13-pad4_ net-_u11-pad2_ net-_u8-pad2_ net-_x11-pad4_ 3_and +x9 net-_x11-pad4_ net-_x10-pad4_ net-_x8-pad4_ net-_x7-pad4_ net-_u13-pad2_ 4_OR +* u13 net-_u1-pad3_ net-_u13-pad2_ net-_u13-pad3_ net-_u13-pad4_ ? d_flip_flop +* u14 net-_u13-pad4_ net-_u14-pad2_ net-_u1-pad10_ buffer_test +x12 net-_u8-pad2_ net-_u12-pad2_ net-_u13-pad4_ net-_x12-pad4_ 3_and +x13 net-_u17-pad4_ net-_u11-pad2_ net-_u9-pad2_ net-_x13-pad4_ 3_and +x15 net-_u1-pad11_ net-_u12-pad2_ net-_u9-pad2_ net-_x14-pad2_ 3_and +x16 net-_u15-pad4_ net-_u11-pad2_ net-_u8-pad2_ net-_x14-pad1_ 3_and +x14 net-_x14-pad1_ net-_x14-pad2_ net-_x13-pad4_ net-_x12-pad4_ net-_u15-pad2_ 4_OR +* u15 net-_u1-pad3_ net-_u15-pad2_ net-_u13-pad3_ net-_u15-pad4_ ? d_flip_flop +* u16 net-_u15-pad4_ net-_u14-pad2_ net-_u1-pad11_ buffer_test +x17 net-_u8-pad2_ net-_u12-pad2_ net-_u15-pad4_ net-_x17-pad4_ 3_and +x18 net-_u19-pad4_ net-_u11-pad2_ net-_u9-pad2_ net-_x18-pad4_ 3_and +x20 net-_u1-pad12_ net-_u12-pad2_ net-_u9-pad2_ net-_x19-pad2_ 3_and +x21 net-_u17-pad4_ net-_u11-pad2_ net-_u8-pad2_ net-_x19-pad1_ 3_and +x19 net-_x19-pad1_ net-_x19-pad2_ net-_x18-pad4_ net-_x17-pad4_ net-_u17-pad2_ 4_OR +* u17 net-_u1-pad3_ net-_u17-pad2_ net-_u13-pad3_ net-_u17-pad4_ ? d_flip_flop +* u18 net-_u17-pad4_ net-_u14-pad2_ net-_u1-pad12_ buffer_test +x22 net-_u8-pad2_ net-_u12-pad2_ net-_u17-pad4_ net-_x22-pad4_ 3_and +x23 net-_u21-pad4_ net-_u11-pad2_ net-_u9-pad2_ net-_x23-pad4_ 3_and +x25 net-_u1-pad13_ net-_u12-pad2_ net-_u9-pad2_ net-_x24-pad2_ 3_and +x26 net-_u19-pad4_ net-_u11-pad2_ net-_u8-pad2_ net-_x24-pad1_ 3_and +x24 net-_x24-pad1_ net-_x24-pad2_ net-_x23-pad4_ net-_x22-pad4_ net-_u19-pad2_ 4_OR +* u19 net-_u1-pad3_ net-_u19-pad2_ net-_u13-pad3_ net-_u19-pad4_ ? d_flip_flop +* u20 net-_u19-pad4_ net-_u14-pad2_ net-_u1-pad13_ buffer_test +x27 net-_u8-pad2_ net-_u12-pad2_ net-_u19-pad4_ net-_x27-pad4_ 3_and +x28 net-_u23-pad4_ net-_u11-pad2_ net-_u9-pad2_ net-_x28-pad4_ 3_and +x30 net-_u1-pad14_ net-_u12-pad2_ net-_u9-pad2_ net-_x29-pad2_ 3_and +x31 net-_u21-pad4_ net-_u11-pad2_ net-_u8-pad2_ net-_x29-pad1_ 3_and +x29 net-_x29-pad1_ net-_x29-pad2_ net-_x28-pad4_ net-_x27-pad4_ net-_u21-pad2_ 4_OR +* u21 net-_u1-pad3_ net-_u21-pad2_ net-_u13-pad3_ net-_u21-pad4_ ? d_flip_flop +* u22 net-_u21-pad4_ net-_u14-pad2_ net-_u1-pad14_ buffer_test +x32 net-_u8-pad2_ net-_u12-pad2_ net-_u21-pad4_ net-_x32-pad4_ 3_and +x33 net-_u1-pad17_ net-_u11-pad2_ net-_u9-pad2_ net-_x33-pad4_ 3_and +x35 net-_u1-pad15_ net-_u12-pad2_ net-_u9-pad2_ net-_x34-pad2_ 3_and +x36 net-_u23-pad4_ net-_u11-pad2_ net-_u8-pad2_ net-_x34-pad1_ 3_and +x34 net-_x34-pad1_ net-_x34-pad2_ net-_x33-pad4_ net-_x32-pad4_ net-_u23-pad2_ 4_OR +* u23 net-_u1-pad3_ net-_u23-pad2_ net-_u13-pad3_ net-_u23-pad4_ ? d_flip_flop +* u24 net-_u23-pad4_ net-_u14-pad2_ net-_u1-pad15_ buffer_test +x37 net-_u8-pad2_ net-_u12-pad2_ net-_u23-pad4_ net-_x37-pad4_ 3_and +x38 net-_u1-pad18_ net-_u11-pad2_ net-_u9-pad2_ net-_x38-pad4_ 3_and +x40 net-_u1-pad16_ net-_u12-pad2_ net-_u9-pad2_ net-_x39-pad2_ 3_and +x41 net-_u1-pad17_ net-_u11-pad2_ net-_u8-pad2_ net-_x39-pad1_ 3_and +x39 net-_x39-pad1_ net-_x39-pad2_ net-_x38-pad4_ net-_x37-pad4_ net-_u25-pad2_ 4_OR +* u25 net-_u1-pad3_ net-_u25-pad2_ net-_u13-pad3_ net-_u1-pad17_ ? d_flip_flop +* u26 net-_u1-pad17_ net-_u14-pad2_ net-_u1-pad16_ buffer_test +* u7 net-_u1-pad6_ net-_u13-pad3_ d_inverter +x1 net-_u4-pad2_ net-_u5-pad2_ net-_u6-pad2_ net-_u14-pad2_ 3_and +* u6 net-_u1-pad5_ net-_u6-pad2_ d_inverter +* u5 net-_u1-pad4_ net-_u5-pad2_ d_inverter +* u4 net-_u10-pad3_ net-_u4-pad2_ d_inverter +* u10 net-_u1-pad1_ net-_u1-pad2_ net-_u10-pad3_ d_and +a1 [net-_u1-pad3_ ] [net-_u2-pad2_ ] [net-_u13-pad3_ ] [net-_u1-pad8_ ] [? ] u2 +a2 [net-_u1-pad8_ ] [net-_u14-pad2_ ] [net-_u1-pad9_ ] u3 +a3 net-_u1-pad2_ net-_u8-pad2_ u8 +a4 net-_u8-pad2_ net-_u9-pad2_ u9 +a5 net-_u1-pad1_ net-_u11-pad2_ u11 +a6 net-_u11-pad2_ net-_u12-pad2_ u12 +a7 [net-_u1-pad3_ ] [net-_u13-pad2_ ] [net-_u13-pad3_ ] [net-_u13-pad4_ ] [? ] u13 +a8 [net-_u13-pad4_ ] [net-_u14-pad2_ ] [net-_u1-pad10_ ] u14 +a9 [net-_u1-pad3_ ] [net-_u15-pad2_ ] [net-_u13-pad3_ ] [net-_u15-pad4_ ] [? ] u15 +a10 [net-_u15-pad4_ ] [net-_u14-pad2_ ] [net-_u1-pad11_ ] u16 +a11 [net-_u1-pad3_ ] [net-_u17-pad2_ ] [net-_u13-pad3_ ] [net-_u17-pad4_ ] [? ] u17 +a12 [net-_u17-pad4_ ] [net-_u14-pad2_ ] [net-_u1-pad12_ ] u18 +a13 [net-_u1-pad3_ ] [net-_u19-pad2_ ] [net-_u13-pad3_ ] [net-_u19-pad4_ ] [? ] u19 +a14 [net-_u19-pad4_ ] [net-_u14-pad2_ ] [net-_u1-pad13_ ] u20 +a15 [net-_u1-pad3_ ] [net-_u21-pad2_ ] [net-_u13-pad3_ ] [net-_u21-pad4_ ] [? ] u21 +a16 [net-_u21-pad4_ ] [net-_u14-pad2_ ] [net-_u1-pad14_ ] u22 +a17 [net-_u1-pad3_ ] [net-_u23-pad2_ ] [net-_u13-pad3_ ] [net-_u23-pad4_ ] [? ] u23 +a18 [net-_u23-pad4_ ] [net-_u14-pad2_ ] [net-_u1-pad15_ ] u24 +a19 [net-_u1-pad3_ ] [net-_u25-pad2_ ] [net-_u13-pad3_ ] [net-_u1-pad17_ ] [? ] u25 +a20 [net-_u1-pad17_ ] [net-_u14-pad2_ ] [net-_u1-pad16_ ] u26 +a21 net-_u1-pad6_ net-_u13-pad3_ u7 +a22 net-_u1-pad5_ net-_u6-pad2_ u6 +a23 net-_u1-pad4_ net-_u5-pad2_ u5 +a24 net-_u10-pad3_ net-_u4-pad2_ u4 +a25 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u10-pad3_ u10 +* Schematic Name: d_flip_flop, NgSpice Name: d_flip_flop +.model u2 d_flip_flop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: buffer_test, NgSpice Name: buffer_test +.model u3 buffer_test(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_flip_flop, NgSpice Name: d_flip_flop +.model u13 d_flip_flop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: buffer_test, NgSpice Name: buffer_test +.model u14 buffer_test(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_flip_flop, NgSpice Name: d_flip_flop +.model u15 d_flip_flop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: buffer_test, NgSpice Name: buffer_test +.model u16 buffer_test(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_flip_flop, NgSpice Name: d_flip_flop +.model u17 d_flip_flop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: buffer_test, NgSpice Name: buffer_test +.model u18 buffer_test(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_flip_flop, NgSpice Name: d_flip_flop +.model u19 d_flip_flop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: buffer_test, NgSpice Name: buffer_test +.model u20 buffer_test(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_flip_flop, NgSpice Name: d_flip_flop +.model u21 d_flip_flop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: buffer_test, NgSpice Name: buffer_test +.model u22 buffer_test(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_flip_flop, NgSpice Name: d_flip_flop +.model u23 d_flip_flop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: buffer_test, NgSpice Name: buffer_test +.model u24 buffer_test(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_flip_flop, NgSpice Name: d_flip_flop +.model u25 d_flip_flop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: buffer_test, NgSpice Name: buffer_test +.model u26 buffer_test(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SN74LS299 \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/SN74LS299_Previous_Values.xml b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/SN74LS299_Previous_Values.xml new file mode 100644 index 000000000..fc7d628df --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/SN74LS299_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_flip_flopbuffer_testd_inverterd_inverterd_inverterd_inverterd_flip_flopbuffer_testd_flip_flopbuffer_testd_flip_flopbuffer_testd_flip_flopbuffer_testd_flip_flopbuffer_testd_flip_flopbuffer_testd_flip_flopbuffer_testd_inverterd_inverterd_inverterd_inverterd_andC:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\4_ORC:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\4_ORC:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\4_ORC:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\4_ORC:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\4_ORC:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\4_ORC:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\4_ORC:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\4_ORC:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\3_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/analysis b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS299/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS38/D.lib b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS38/D.lib new file mode 100644 index 000000000..f53bf3e03 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS38/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS38/NPN.lib b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS38/NPN.lib new file mode 100644 index 000000000..be5f3073a --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS38/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS38/SN74LS38-cache.lib b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS38/SN74LS38-cache.lib new file mode 100644 index 000000000..7e9c6731b --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS38/SN74LS38-cache.lib @@ -0,0 +1,107 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS38/SN74LS38.cir b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS38/SN74LS38.cir new file mode 100644 index 000000000..a9e8da68a --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS38/SN74LS38.cir @@ -0,0 +1,51 @@ +* C:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\SN74LS38\SN74LS38.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/24/25 14:45:38 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q3 Net-_Q11-Pad2_ Net-_Q3-Pad2_ Net-_D3-Pad2_ eSim_NPN +Q7 Net-_Q11-Pad2_ Net-_Q3-Pad2_ Net-_D7-Pad2_ eSim_NPN +D3 GND Net-_D3-Pad2_ eSim_Diode +D7 GND Net-_D7-Pad2_ eSim_Diode +Q11 Net-_Q11-Pad1_ Net-_Q11-Pad2_ Net-_Q11-Pad3_ eSim_NPN +Q15 Net-_Q15-Pad1_ Net-_Q11-Pad3_ GND eSim_NPN +R9 VCC Net-_Q11-Pad1_ 600 +R15 VCC Net-_Q15-Pad1_ 1k +R10 Net-_Q11-Pad3_ GND 400 +R3 VCC Net-_Q3-Pad2_ 4k +Q4 Net-_Q12-Pad2_ Net-_Q4-Pad2_ Net-_D4-Pad2_ eSim_NPN +Q8 Net-_Q12-Pad2_ Net-_Q4-Pad2_ Net-_D8-Pad2_ eSim_NPN +D4 GND Net-_D4-Pad2_ eSim_Diode +D8 GND Net-_D8-Pad2_ eSim_Diode +Q12 Net-_Q12-Pad1_ Net-_Q12-Pad2_ Net-_Q12-Pad3_ eSim_NPN +Q16 Net-_Q16-Pad1_ Net-_Q12-Pad3_ GND eSim_NPN +R11 VCC Net-_Q12-Pad1_ 600 +R16 VCC Net-_Q16-Pad1_ 1k +R12 Net-_Q12-Pad3_ GND 400 +R4 VCC Net-_Q4-Pad2_ 4k +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_D1-Pad2_ eSim_NPN +Q5 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_D5-Pad2_ eSim_NPN +D1 GND Net-_D1-Pad2_ eSim_Diode +D5 GND Net-_D5-Pad2_ eSim_Diode +Q9 Net-_Q9-Pad1_ Net-_Q1-Pad1_ Net-_Q13-Pad2_ eSim_NPN +Q13 Net-_Q13-Pad1_ Net-_Q13-Pad2_ GND eSim_NPN +R5 VCC Net-_Q9-Pad1_ 600 +R13 VCC Net-_Q13-Pad1_ 1k +R6 Net-_Q13-Pad2_ GND 400 +R1 VCC Net-_Q1-Pad2_ 4k +Q2 Net-_Q10-Pad2_ Net-_Q2-Pad2_ Net-_D2-Pad2_ eSim_NPN +Q6 Net-_Q10-Pad2_ Net-_Q2-Pad2_ Net-_D6-Pad2_ eSim_NPN +D2 GND Net-_D2-Pad2_ eSim_Diode +D6 GND Net-_D6-Pad2_ eSim_Diode +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN +Q14 Net-_Q14-Pad1_ Net-_Q10-Pad3_ GND eSim_NPN +R7 VCC Net-_Q10-Pad1_ 600 +R14 VCC Net-_Q14-Pad1_ 600 +R8 Net-_Q10-Pad3_ GND 400 +R2 VCC Net-_Q2-Pad2_ 4k +U1 Net-_D7-Pad2_ Net-_D3-Pad2_ Net-_Q15-Pad1_ Net-_D8-Pad2_ Net-_D4-Pad2_ Net-_Q16-Pad1_ GND Net-_D5-Pad2_ Net-_D1-Pad2_ Net-_Q13-Pad1_ Net-_D6-Pad2_ Net-_D2-Pad2_ Net-_Q14-Pad1_ VCC PORT + +.end diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS38/SN74LS38.cir.out b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS38/SN74LS38.cir.out new file mode 100644 index 000000000..86ba88e0a --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS38/SN74LS38.cir.out @@ -0,0 +1,54 @@ +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\sn74ls38\sn74ls38.cir + +.include NPN.lib +.include D.lib +q3 net-_q11-pad2_ net-_q3-pad2_ net-_d3-pad2_ Q2N2222 +q7 net-_q11-pad2_ net-_q3-pad2_ net-_d7-pad2_ Q2N2222 +d3 gnd net-_d3-pad2_ 1N4148 +d7 gnd net-_d7-pad2_ 1N4148 +q11 net-_q11-pad1_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222 +q15 net-_q15-pad1_ net-_q11-pad3_ gnd Q2N2222 +r9 vcc net-_q11-pad1_ 600 +r15 vcc net-_q15-pad1_ 1k +r10 net-_q11-pad3_ gnd 400 +r3 vcc net-_q3-pad2_ 4k +q4 net-_q12-pad2_ net-_q4-pad2_ net-_d4-pad2_ Q2N2222 +q8 net-_q12-pad2_ net-_q4-pad2_ net-_d8-pad2_ Q2N2222 +d4 gnd net-_d4-pad2_ 1N4148 +d8 gnd net-_d8-pad2_ 1N4148 +q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222 +q16 net-_q16-pad1_ net-_q12-pad3_ gnd Q2N2222 +r11 vcc net-_q12-pad1_ 600 +r16 vcc net-_q16-pad1_ 1k +r12 net-_q12-pad3_ gnd 400 +r4 vcc net-_q4-pad2_ 4k +q1 net-_q1-pad1_ net-_q1-pad2_ net-_d1-pad2_ Q2N2222 +q5 net-_q1-pad1_ net-_q1-pad2_ net-_d5-pad2_ Q2N2222 +d1 gnd net-_d1-pad2_ 1N4148 +d5 gnd net-_d5-pad2_ 1N4148 +q9 net-_q9-pad1_ net-_q1-pad1_ net-_q13-pad2_ Q2N2222 +q13 net-_q13-pad1_ net-_q13-pad2_ gnd Q2N2222 +r5 vcc net-_q9-pad1_ 600 +r13 vcc net-_q13-pad1_ 1k +r6 net-_q13-pad2_ gnd 400 +r1 vcc net-_q1-pad2_ 4k +q2 net-_q10-pad2_ net-_q2-pad2_ net-_d2-pad2_ Q2N2222 +q6 net-_q10-pad2_ net-_q2-pad2_ net-_d6-pad2_ Q2N2222 +d2 gnd net-_d2-pad2_ 1N4148 +d6 gnd net-_d6-pad2_ 1N4148 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q14 net-_q14-pad1_ net-_q10-pad3_ gnd Q2N2222 +r7 vcc net-_q10-pad1_ 600 +r14 vcc net-_q14-pad1_ 600 +r8 net-_q10-pad3_ gnd 400 +r2 vcc net-_q2-pad2_ 4k +* u1 net-_d7-pad2_ net-_d3-pad2_ net-_q15-pad1_ net-_d8-pad2_ net-_d4-pad2_ net-_q16-pad1_ gnd net-_d5-pad2_ net-_d1-pad2_ net-_q13-pad1_ net-_d6-pad2_ net-_d2-pad2_ net-_q14-pad1_ vcc port +.tran 0e-12 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS38/SN74LS38.pro b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS38/SN74LS38.pro new file mode 100644 index 000000000..7557d7229 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS38/SN74LS38.pro @@ -0,0 +1,83 @@ +update=06/23/25 18:25:08 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName= +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName= +SpiceForceRefPrefix=0 +SpiceUseNetNumbers=0 +LabSize=60 diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS38/SN74LS38.sch b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS38/SN74LS38.sch new file mode 100644 index 000000000..ad5872ed1 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS38/SN74LS38.sch @@ -0,0 +1,975 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN74LS38-cache +EELAYER 25 0 +EELAYER END +$Descr A3 16535 11693 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q3 +U 1 1 685A3B37 +P 5950 1650 +F 0 "Q3" H 5850 1700 50 0000 R CNN +F 1 "eSim_NPN" H 5900 1800 50 0000 R CNN +F 2 "" H 6150 1750 29 0000 C CNN +F 3 "" H 5950 1650 60 0000 C CNN + 1 5950 1650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q7 +U 1 1 685A3BA0 +P 6900 1650 +F 0 "Q7" H 6800 1700 50 0000 R CNN +F 1 "eSim_NPN" H 6850 1800 50 0000 R CNN +F 2 "" H 7100 1750 29 0000 C CNN +F 3 "" H 6900 1650 60 0000 C CNN + 1 6900 1650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D3 +U 1 1 685A3BDA +P 6050 2200 +F 0 "D3" H 6050 2300 50 0000 C CNN +F 1 "eSim_Diode" H 6050 2100 50 0000 C CNN +F 2 "" H 6050 2200 60 0000 C CNN +F 3 "" H 6050 2200 60 0000 C CNN + 1 6050 2200 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Diode D7 +U 1 1 685A3C51 +P 7000 2150 +F 0 "D7" H 7000 2250 50 0000 C CNN +F 1 "eSim_Diode" H 7000 2050 50 0000 C CNN +F 2 "" H 7000 2150 60 0000 C CNN +F 3 "" H 7000 2150 60 0000 C CNN + 1 7000 2150 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_NPN Q11 +U 1 1 685A3C8D +P 8300 1650 +F 0 "Q11" H 8200 1700 50 0000 R CNN +F 1 "eSim_NPN" H 8250 1800 50 0000 R CNN +F 2 "" H 8500 1750 29 0000 C CNN +F 3 "" H 8300 1650 60 0000 C CNN + 1 8300 1650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q15 +U 1 1 685A3D03 +P 9050 1950 +F 0 "Q15" H 8950 2000 50 0000 R CNN +F 1 "eSim_NPN" H 9000 2100 50 0000 R CNN +F 2 "" H 9250 2050 29 0000 C CNN +F 3 "" H 9050 1950 60 0000 C CNN + 1 9050 1950 + 1 0 0 -1 +$EndComp +$Comp +L resistor R9 +U 1 1 685A3D5D +P 8350 1150 +F 0 "R9" H 8400 1280 50 0000 C CNN +F 1 "600" H 8400 1100 50 0000 C CNN +F 2 "" H 8400 1130 30 0000 C CNN +F 3 "" V 8400 1200 30 0000 C CNN + 1 8350 1150 + 0 1 1 0 +$EndComp +$Comp +L resistor R15 +U 1 1 685A3E4A +P 9100 1150 +F 0 "R15" H 9150 1280 50 0000 C CNN +F 1 "1k" H 9150 1100 50 0000 C CNN +F 2 "" H 9150 1130 30 0000 C CNN +F 3 "" V 9150 1200 30 0000 C CNN + 1 9100 1150 + 0 1 1 0 +$EndComp +$Comp +L resistor R10 +U 1 1 685A3F1C +P 8350 2100 +F 0 "R10" H 8400 2230 50 0000 C CNN +F 1 "400" H 8400 2050 50 0000 C CNN +F 2 "" H 8400 2080 30 0000 C CNN +F 3 "" V 8400 2150 30 0000 C CNN + 1 8350 2100 + 0 1 1 0 +$EndComp +$Comp +L resistor R3 +U 1 1 685A4051 +P 5400 950 +F 0 "R3" H 5450 1080 50 0000 C CNN +F 1 "4k" H 5450 900 50 0000 C CNN +F 2 "" H 5450 930 30 0000 C CNN +F 3 "" V 5450 1000 30 0000 C CNN + 1 5400 950 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 685A7C7D +P 5950 3850 +F 0 "Q4" H 5850 3900 50 0000 R CNN +F 1 "eSim_NPN" H 5900 4000 50 0000 R CNN +F 2 "" H 6150 3950 29 0000 C CNN +F 3 "" H 5950 3850 60 0000 C CNN + 1 5950 3850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 685A7C83 +P 6900 3850 +F 0 "Q8" H 6800 3900 50 0000 R CNN +F 1 "eSim_NPN" H 6850 4000 50 0000 R CNN +F 2 "" H 7100 3950 29 0000 C CNN +F 3 "" H 6900 3850 60 0000 C CNN + 1 6900 3850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D4 +U 1 1 685A7C89 +P 6050 4400 +F 0 "D4" H 6050 4500 50 0000 C CNN +F 1 "eSim_Diode" H 6050 4300 50 0000 C CNN +F 2 "" H 6050 4400 60 0000 C CNN +F 3 "" H 6050 4400 60 0000 C CNN + 1 6050 4400 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Diode D8 +U 1 1 685A7C8F +P 7000 4350 +F 0 "D8" H 7000 4450 50 0000 C CNN +F 1 "eSim_Diode" H 7000 4250 50 0000 C CNN +F 2 "" H 7000 4350 60 0000 C CNN +F 3 "" H 7000 4350 60 0000 C CNN + 1 7000 4350 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_NPN Q12 +U 1 1 685A7C95 +P 8300 3850 +F 0 "Q12" H 8200 3900 50 0000 R CNN +F 1 "eSim_NPN" H 8250 4000 50 0000 R CNN +F 2 "" H 8500 3950 29 0000 C CNN +F 3 "" H 8300 3850 60 0000 C CNN + 1 8300 3850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q16 +U 1 1 685A7C9B +P 9050 4150 +F 0 "Q16" H 8950 4200 50 0000 R CNN +F 1 "eSim_NPN" H 9000 4300 50 0000 R CNN +F 2 "" H 9250 4250 29 0000 C CNN +F 3 "" H 9050 4150 60 0000 C CNN + 1 9050 4150 + 1 0 0 -1 +$EndComp +$Comp +L resistor R11 +U 1 1 685A7CA1 +P 8350 3350 +F 0 "R11" H 8400 3480 50 0000 C CNN +F 1 "600" H 8400 3300 50 0000 C CNN +F 2 "" H 8400 3330 30 0000 C CNN +F 3 "" V 8400 3400 30 0000 C CNN + 1 8350 3350 + 0 1 1 0 +$EndComp +$Comp +L resistor R16 +U 1 1 685A7CA7 +P 9100 3350 +F 0 "R16" H 9150 3480 50 0000 C CNN +F 1 "1k" H 9150 3300 50 0000 C CNN +F 2 "" H 9150 3330 30 0000 C CNN +F 3 "" V 9150 3400 30 0000 C CNN + 1 9100 3350 + 0 1 1 0 +$EndComp +$Comp +L resistor R12 +U 1 1 685A7CAD +P 8350 4300 +F 0 "R12" H 8400 4430 50 0000 C CNN +F 1 "400" H 8400 4250 50 0000 C CNN +F 2 "" H 8400 4280 30 0000 C CNN +F 3 "" V 8400 4350 30 0000 C CNN + 1 8350 4300 + 0 1 1 0 +$EndComp +$Comp +L resistor R4 +U 1 1 685A7CB3 +P 5400 3150 +F 0 "R4" H 5450 3280 50 0000 C CNN +F 1 "4k" H 5450 3100 50 0000 C CNN +F 2 "" H 5450 3130 30 0000 C CNN +F 3 "" V 5450 3200 30 0000 C CNN + 1 5400 3150 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 685A7F78 +P 5900 6100 +F 0 "Q1" H 5800 6150 50 0000 R CNN +F 1 "eSim_NPN" H 5850 6250 50 0000 R CNN +F 2 "" H 6100 6200 29 0000 C CNN +F 3 "" H 5900 6100 60 0000 C CNN + 1 5900 6100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 685A7F7E +P 6850 6100 +F 0 "Q5" H 6750 6150 50 0000 R CNN +F 1 "eSim_NPN" H 6800 6250 50 0000 R CNN +F 2 "" H 7050 6200 29 0000 C CNN +F 3 "" H 6850 6100 60 0000 C CNN + 1 6850 6100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 685A7F84 +P 6000 6650 +F 0 "D1" H 6000 6750 50 0000 C CNN +F 1 "eSim_Diode" H 6000 6550 50 0000 C CNN +F 2 "" H 6000 6650 60 0000 C CNN +F 3 "" H 6000 6650 60 0000 C CNN + 1 6000 6650 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Diode D5 +U 1 1 685A7F8A +P 6950 6600 +F 0 "D5" H 6950 6700 50 0000 C CNN +F 1 "eSim_Diode" H 6950 6500 50 0000 C CNN +F 2 "" H 6950 6600 60 0000 C CNN +F 3 "" H 6950 6600 60 0000 C CNN + 1 6950 6600 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_NPN Q9 +U 1 1 685A7F90 +P 8250 6100 +F 0 "Q9" H 8150 6150 50 0000 R CNN +F 1 "eSim_NPN" H 8200 6250 50 0000 R CNN +F 2 "" H 8450 6200 29 0000 C CNN +F 3 "" H 8250 6100 60 0000 C CNN + 1 8250 6100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q13 +U 1 1 685A7F96 +P 9000 6400 +F 0 "Q13" H 8900 6450 50 0000 R CNN +F 1 "eSim_NPN" H 8950 6550 50 0000 R CNN +F 2 "" H 9200 6500 29 0000 C CNN +F 3 "" H 9000 6400 60 0000 C CNN + 1 9000 6400 + 1 0 0 -1 +$EndComp +$Comp +L resistor R5 +U 1 1 685A7F9C +P 8300 5600 +F 0 "R5" H 8350 5730 50 0000 C CNN +F 1 "600" H 8350 5550 50 0000 C CNN +F 2 "" H 8350 5580 30 0000 C CNN +F 3 "" V 8350 5650 30 0000 C CNN + 1 8300 5600 + 0 1 1 0 +$EndComp +$Comp +L resistor R13 +U 1 1 685A7FA2 +P 9050 5600 +F 0 "R13" H 9100 5730 50 0000 C CNN +F 1 "1k" H 9100 5550 50 0000 C CNN +F 2 "" H 9100 5580 30 0000 C CNN +F 3 "" V 9100 5650 30 0000 C CNN + 1 9050 5600 + 0 1 1 0 +$EndComp +$Comp +L resistor R6 +U 1 1 685A7FA8 +P 8300 6550 +F 0 "R6" H 8350 6680 50 0000 C CNN +F 1 "400" H 8350 6500 50 0000 C CNN +F 2 "" H 8350 6530 30 0000 C CNN +F 3 "" V 8350 6600 30 0000 C CNN + 1 8300 6550 + 0 1 1 0 +$EndComp +$Comp +L resistor R1 +U 1 1 685A7FAE +P 5350 5400 +F 0 "R1" H 5400 5530 50 0000 C CNN +F 1 "4k" H 5400 5350 50 0000 C CNN +F 2 "" H 5400 5380 30 0000 C CNN +F 3 "" V 5400 5450 30 0000 C CNN + 1 5350 5400 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 685A7FDF +P 5900 8300 +F 0 "Q2" H 5800 8350 50 0000 R CNN +F 1 "eSim_NPN" H 5850 8450 50 0000 R CNN +F 2 "" H 6100 8400 29 0000 C CNN +F 3 "" H 5900 8300 60 0000 C CNN + 1 5900 8300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q6 +U 1 1 685A7FE5 +P 6850 8300 +F 0 "Q6" H 6750 8350 50 0000 R CNN +F 1 "eSim_NPN" H 6800 8450 50 0000 R CNN +F 2 "" H 7050 8400 29 0000 C CNN +F 3 "" H 6850 8300 60 0000 C CNN + 1 6850 8300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 685A7FEB +P 6000 8850 +F 0 "D2" H 6000 8950 50 0000 C CNN +F 1 "eSim_Diode" H 6000 8750 50 0000 C CNN +F 2 "" H 6000 8850 60 0000 C CNN +F 3 "" H 6000 8850 60 0000 C CNN + 1 6000 8850 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Diode D6 +U 1 1 685A7FF1 +P 6950 8800 +F 0 "D6" H 6950 8900 50 0000 C CNN +F 1 "eSim_Diode" H 6950 8700 50 0000 C CNN +F 2 "" H 6950 8800 60 0000 C CNN +F 3 "" H 6950 8800 60 0000 C CNN + 1 6950 8800 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_NPN Q10 +U 1 1 685A7FF7 +P 8250 8300 +F 0 "Q10" H 8150 8350 50 0000 R CNN +F 1 "eSim_NPN" H 8200 8450 50 0000 R CNN +F 2 "" H 8450 8400 29 0000 C CNN +F 3 "" H 8250 8300 60 0000 C CNN + 1 8250 8300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q14 +U 1 1 685A7FFD +P 9000 8600 +F 0 "Q14" H 8900 8650 50 0000 R CNN +F 1 "eSim_NPN" H 8950 8750 50 0000 R CNN +F 2 "" H 9200 8700 29 0000 C CNN +F 3 "" H 9000 8600 60 0000 C CNN + 1 9000 8600 + 1 0 0 -1 +$EndComp +$Comp +L resistor R7 +U 1 1 685A8003 +P 8300 7800 +F 0 "R7" H 8350 7930 50 0000 C CNN +F 1 "600" H 8350 7750 50 0000 C CNN +F 2 "" H 8350 7780 30 0000 C CNN +F 3 "" V 8350 7850 30 0000 C CNN + 1 8300 7800 + 0 1 1 0 +$EndComp +$Comp +L resistor R14 +U 1 1 685A8009 +P 9050 7800 +F 0 "R14" H 9100 7930 50 0000 C CNN +F 1 "600" H 9100 7750 50 0000 C CNN +F 2 "" H 9100 7780 30 0000 C CNN +F 3 "" V 9100 7850 30 0000 C CNN + 1 9050 7800 + 0 1 1 0 +$EndComp +$Comp +L resistor R8 +U 1 1 685A800F +P 8300 8750 +F 0 "R8" H 8350 8880 50 0000 C CNN +F 1 "400" H 8350 8700 50 0000 C CNN +F 2 "" H 8350 8730 30 0000 C CNN +F 3 "" V 8350 8800 30 0000 C CNN + 1 8300 8750 + 0 1 1 0 +$EndComp +$Comp +L resistor R2 +U 1 1 685A8015 +P 5350 7600 +F 0 "R2" H 5400 7730 50 0000 C CNN +F 1 "4k" H 5400 7550 50 0000 C CNN +F 2 "" H 5400 7580 30 0000 C CNN +F 3 "" V 5400 7650 30 0000 C CNN + 1 5350 7600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 685A82F0 +P 10200 3800 +F 0 "U1" H 10250 3900 30 0000 C CNN +F 1 "PORT" H 10200 3800 30 0000 C CNN +F 2 "" H 10200 3800 60 0000 C CNN +F 3 "" H 10200 3800 60 0000 C CNN + 6 10200 3800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 685A851F +P 4650 6450 +F 0 "U1" H 4700 6550 30 0000 C CNN +F 1 "PORT" H 4650 6450 30 0000 C CNN +F 2 "" H 4650 6450 60 0000 C CNN +F 3 "" H 4650 6450 60 0000 C CNN + 9 4650 6450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 685A87EA +P 10150 8250 +F 0 "U1" H 10200 8350 30 0000 C CNN +F 1 "PORT" H 10150 8250 30 0000 C CNN +F 2 "" H 10150 8250 60 0000 C CNN +F 3 "" H 10150 8250 60 0000 C CNN + 13 10150 8250 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 685A89B5 +P 3500 7200 +F 0 "U1" H 3550 7300 30 0000 C CNN +F 1 "PORT" H 3500 7200 30 0000 C CNN +F 2 "" H 3500 7200 60 0000 C CNN +F 3 "" H 3500 7200 60 0000 C CNN + 7 3500 7200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 685A8BE2 +P 10150 6050 +F 0 "U1" H 10200 6150 30 0000 C CNN +F 1 "PORT" H 10150 6050 30 0000 C CNN +F 2 "" H 10150 6050 60 0000 C CNN +F 3 "" H 10150 6050 60 0000 C CNN + 10 10150 6050 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 685A8E84 +P 3500 6850 +F 0 "U1" H 3550 6950 30 0000 C CNN +F 1 "PORT" H 3500 6850 30 0000 C CNN +F 2 "" H 3500 6850 60 0000 C CNN +F 3 "" H 3500 6850 60 0000 C CNN + 14 3500 6850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 685A927F +P 5300 4100 +F 0 "U1" H 5350 4200 30 0000 C CNN +F 1 "PORT" H 5300 4100 30 0000 C CNN +F 2 "" H 5300 4100 60 0000 C CNN +F 3 "" H 5300 4100 60 0000 C CNN + 4 5300 4100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 685A93E6 +P 10200 1600 +F 0 "U1" H 10250 1700 30 0000 C CNN +F 1 "PORT" H 10200 1600 30 0000 C CNN +F 2 "" H 10200 1600 60 0000 C CNN +F 3 "" H 10200 1600 60 0000 C CNN + 3 10200 1600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 685A9543 +P 5250 8550 +F 0 "U1" H 5300 8650 30 0000 C CNN +F 1 "PORT" H 5250 8550 30 0000 C CNN +F 2 "" H 5250 8550 60 0000 C CNN +F 3 "" H 5250 8550 60 0000 C CNN + 11 5250 8550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 685A97BA +P 5550 4450 +F 0 "U1" H 5600 4550 30 0000 C CNN +F 1 "PORT" H 5550 4450 30 0000 C CNN +F 2 "" H 5550 4450 60 0000 C CNN +F 3 "" H 5550 4450 60 0000 C CNN + 5 5550 4450 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 8 1 685A9AA5 +P 5250 6350 +F 0 "U1" H 5300 6450 30 0000 C CNN +F 1 "PORT" H 5250 6350 30 0000 C CNN +F 2 "" H 5250 6350 60 0000 C CNN +F 3 "" H 5250 6350 60 0000 C CNN + 8 5250 6350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 685A9C93 +P 5500 8900 +F 0 "U1" H 5550 9000 30 0000 C CNN +F 1 "PORT" H 5500 8900 30 0000 C CNN +F 2 "" H 5500 8900 60 0000 C CNN +F 3 "" H 5500 8900 60 0000 C CNN + 12 5500 8900 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 1 1 685A9E5E +P 5300 1900 +F 0 "U1" H 5350 2000 30 0000 C CNN +F 1 "PORT" H 5300 1900 30 0000 C CNN +F 2 "" H 5300 1900 60 0000 C CNN +F 3 "" H 5300 1900 60 0000 C CNN + 1 5300 1900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 685AA0EF +P 5550 2250 +F 0 "U1" H 5600 2350 30 0000 C CNN +F 1 "PORT" H 5550 2250 30 0000 C CNN +F 2 "" H 5550 2250 60 0000 C CNN +F 3 "" H 5550 2250 60 0000 C CNN + 2 5550 2250 + 0 -1 -1 0 +$EndComp +Text GLabel 4150 6850 2 60 Input ~ 0 +VCC +Text GLabel 4150 7200 2 60 Input ~ 0 +GND +Text GLabel 9500 7650 2 60 Input ~ 0 +VCC +Text GLabel 9500 5450 2 60 Input ~ 0 +VCC +Text GLabel 9550 3200 2 60 Input ~ 0 +VCC +Text GLabel 9550 1000 2 60 Input ~ 0 +VCC +Text GLabel 7650 9350 3 60 Input ~ 0 +GND +Text GLabel 7650 7150 3 60 Input ~ 0 +GND +Text GLabel 7700 4900 3 60 Input ~ 0 +GND +Text GLabel 7700 2700 3 60 Input ~ 0 +GND +Wire Wire Line + 6400 1650 6700 1650 +Connection ~ 5250 1650 +Wire Wire Line + 7650 1650 8100 1650 +Wire Wire Line + 9150 1350 9150 1750 +Wire Wire Line + 6400 1650 6400 1400 +Wire Wire Line + 6400 1400 5250 1400 +Wire Wire Line + 5250 1400 5250 1650 +Wire Wire Line + 6050 1450 6050 1350 +Wire Wire Line + 6050 1350 7000 1350 +Wire Wire Line + 7000 1350 7000 1450 +Wire Wire Line + 7650 1650 7650 1250 +Wire Wire Line + 7650 1250 6700 1250 +Wire Wire Line + 6700 1250 6700 1350 +Connection ~ 6700 1350 +Wire Wire Line + 5750 1650 4900 1650 +Wire Wire Line + 5200 1000 4900 1000 +Wire Wire Line + 4900 1000 4900 1650 +Wire Wire Line + 5500 1000 9550 1000 +Wire Wire Line + 8400 1050 8400 1000 +Connection ~ 8400 1000 +Wire Wire Line + 8400 1350 8400 1450 +Wire Wire Line + 9150 1050 9150 1000 +Connection ~ 9150 1000 +Wire Wire Line + 6050 1850 6050 2050 +Wire Wire Line + 7000 1850 7000 2000 +Wire Wire Line + 8400 1850 8400 2000 +Wire Wire Line + 8400 1950 8850 1950 +Connection ~ 8400 1950 +Wire Wire Line + 9150 2150 9150 2550 +Wire Wire Line + 9150 2550 6050 2550 +Wire Wire Line + 6050 2550 6050 2350 +Wire Wire Line + 7000 2300 7000 2550 +Connection ~ 7000 2550 +Wire Wire Line + 8400 2300 8400 2550 +Connection ~ 8400 2550 +Wire Wire Line + 7000 1900 5550 1900 +Connection ~ 7000 1900 +Wire Wire Line + 6050 2000 5550 2000 +Connection ~ 6050 2000 +Connection ~ 9150 1600 +Wire Wire Line + 7700 2550 7700 2700 +Connection ~ 7700 2550 +Wire Wire Line + 6400 3850 6700 3850 +Connection ~ 5250 3850 +Wire Wire Line + 7650 3850 8100 3850 +Wire Wire Line + 9150 3550 9150 3950 +Wire Wire Line + 6400 3850 6400 3600 +Wire Wire Line + 6400 3600 5250 3600 +Wire Wire Line + 5250 3600 5250 3850 +Wire Wire Line + 6050 3650 6050 3550 +Wire Wire Line + 6050 3550 7000 3550 +Wire Wire Line + 7000 3550 7000 3650 +Wire Wire Line + 7650 3850 7650 3450 +Wire Wire Line + 7650 3450 6700 3450 +Wire Wire Line + 6700 3450 6700 3550 +Connection ~ 6700 3550 +Wire Wire Line + 5750 3850 4900 3850 +Wire Wire Line + 5200 3200 4900 3200 +Wire Wire Line + 4900 3200 4900 3850 +Wire Wire Line + 5500 3200 9550 3200 +Wire Wire Line + 8400 3250 8400 3200 +Connection ~ 8400 3200 +Wire Wire Line + 8400 3550 8400 3650 +Wire Wire Line + 9150 3250 9150 3200 +Connection ~ 9150 3200 +Wire Wire Line + 6050 4050 6050 4250 +Wire Wire Line + 7000 4050 7000 4200 +Wire Wire Line + 8400 4050 8400 4200 +Wire Wire Line + 8400 4150 8850 4150 +Connection ~ 8400 4150 +Wire Wire Line + 9150 4350 9150 4750 +Wire Wire Line + 9150 4750 6050 4750 +Wire Wire Line + 6050 4750 6050 4550 +Wire Wire Line + 7000 4500 7000 4750 +Connection ~ 7000 4750 +Wire Wire Line + 8400 4500 8400 4750 +Connection ~ 8400 4750 +Wire Wire Line + 7000 4100 5550 4100 +Connection ~ 7000 4100 +Wire Wire Line + 6050 4200 5550 4200 +Connection ~ 6050 4200 +Connection ~ 9150 3800 +Wire Wire Line + 7700 4750 7700 4900 +Connection ~ 7700 4750 +Wire Wire Line + 6350 6100 6650 6100 +Connection ~ 5200 6100 +Wire Wire Line + 7600 6100 8050 6100 +Wire Wire Line + 9100 5800 9100 6200 +Wire Wire Line + 6350 6100 6350 5850 +Wire Wire Line + 6350 5850 5200 5850 +Wire Wire Line + 5200 5850 5200 6100 +Wire Wire Line + 6000 5900 6000 5800 +Wire Wire Line + 6000 5800 6950 5800 +Wire Wire Line + 6950 5800 6950 5900 +Wire Wire Line + 7600 6100 7600 5700 +Wire Wire Line + 7600 5700 6650 5700 +Wire Wire Line + 6650 5700 6650 5800 +Connection ~ 6650 5800 +Wire Wire Line + 5700 6100 4850 6100 +Wire Wire Line + 5150 5450 4850 5450 +Wire Wire Line + 4850 5450 4850 6100 +Wire Wire Line + 5450 5450 9500 5450 +Wire Wire Line + 8350 5500 8350 5450 +Connection ~ 8350 5450 +Wire Wire Line + 8350 5800 8350 5900 +Wire Wire Line + 9100 5500 9100 5450 +Connection ~ 9100 5450 +Wire Wire Line + 6000 6300 6000 6500 +Wire Wire Line + 6950 6300 6950 6450 +Wire Wire Line + 8350 6300 8350 6450 +Wire Wire Line + 8350 6400 8800 6400 +Connection ~ 8350 6400 +Wire Wire Line + 9100 6600 9100 7000 +Wire Wire Line + 9100 7000 6000 7000 +Wire Wire Line + 6000 7000 6000 6800 +Wire Wire Line + 6950 6750 6950 7000 +Connection ~ 6950 7000 +Wire Wire Line + 8350 6750 8350 7000 +Connection ~ 8350 7000 +Wire Wire Line + 6950 6350 5500 6350 +Connection ~ 6950 6350 +Wire Wire Line + 4900 6450 6000 6450 +Connection ~ 6000 6450 +Connection ~ 9100 6050 +Wire Wire Line + 7650 7000 7650 7150 +Connection ~ 7650 7000 +Wire Wire Line + 6350 8300 6650 8300 +Connection ~ 5200 8300 +Wire Wire Line + 7600 8300 8050 8300 +Wire Wire Line + 9100 8000 9100 8400 +Wire Wire Line + 6350 8300 6350 8050 +Wire Wire Line + 6350 8050 5200 8050 +Wire Wire Line + 5200 8050 5200 8300 +Wire Wire Line + 6000 8100 6000 8000 +Wire Wire Line + 6000 8000 6950 8000 +Wire Wire Line + 6950 8000 6950 8100 +Wire Wire Line + 7600 8300 7600 7900 +Wire Wire Line + 7600 7900 6650 7900 +Wire Wire Line + 6650 7900 6650 8000 +Connection ~ 6650 8000 +Wire Wire Line + 5700 8300 4850 8300 +Wire Wire Line + 5150 7650 4850 7650 +Wire Wire Line + 4850 7650 4850 8300 +Wire Wire Line + 5450 7650 9500 7650 +Wire Wire Line + 8350 7700 8350 7650 +Connection ~ 8350 7650 +Wire Wire Line + 8350 8000 8350 8100 +Wire Wire Line + 9100 7700 9100 7650 +Connection ~ 9100 7650 +Wire Wire Line + 6000 8500 6000 8700 +Wire Wire Line + 6950 8500 6950 8650 +Wire Wire Line + 8350 8500 8350 8650 +Wire Wire Line + 8350 8600 8800 8600 +Connection ~ 8350 8600 +Wire Wire Line + 9100 8800 9100 9200 +Wire Wire Line + 9100 9200 6000 9200 +Wire Wire Line + 6000 9200 6000 9000 +Wire Wire Line + 6950 8950 6950 9200 +Connection ~ 6950 9200 +Wire Wire Line + 8350 8950 8350 9200 +Connection ~ 8350 9200 +Wire Wire Line + 6950 8550 5500 8550 +Connection ~ 6950 8550 +Wire Wire Line + 6000 8650 5500 8650 +Connection ~ 6000 8650 +Connection ~ 9100 8250 +Wire Wire Line + 7650 9200 7650 9350 +Connection ~ 7650 9200 +Wire Wire Line + 3750 6850 4150 6850 +Wire Wire Line + 4150 7200 3750 7200 +Wire Wire Line + 9100 8250 9900 8250 +Wire Wire Line + 9100 6050 9900 6050 +Wire Wire Line + 9150 3800 9950 3800 +Wire Wire Line + 9150 1600 9950 1600 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS38/SN74LS38.sub b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS38/SN74LS38.sub new file mode 100644 index 000000000..a3aadf789 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS38/SN74LS38.sub @@ -0,0 +1,48 @@ +* Subcircuit SN74LS38 +.subckt SN74LS38 net-_d7-pad2_ net-_d3-pad2_ net-_q15-pad1_ net-_d8-pad2_ net-_d4-pad2_ net-_q16-pad1_ gnd net-_d5-pad2_ net-_d1-pad2_ net-_q13-pad1_ net-_d6-pad2_ net-_d2-pad2_ net-_q14-pad1_ vcc +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\sn74ls38\sn74ls38.cir +.include NPN.lib +.include D.lib +q3 net-_q11-pad2_ net-_q3-pad2_ net-_d3-pad2_ Q2N2222 +q7 net-_q11-pad2_ net-_q3-pad2_ net-_d7-pad2_ Q2N2222 +d3 gnd net-_d3-pad2_ 1N4148 +d7 gnd net-_d7-pad2_ 1N4148 +q11 net-_q11-pad1_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222 +q15 net-_q15-pad1_ net-_q11-pad3_ gnd Q2N2222 +r9 vcc net-_q11-pad1_ 600 +r15 vcc net-_q15-pad1_ 1k +r10 net-_q11-pad3_ gnd 400 +r3 vcc net-_q3-pad2_ 4k +q4 net-_q12-pad2_ net-_q4-pad2_ net-_d4-pad2_ Q2N2222 +q8 net-_q12-pad2_ net-_q4-pad2_ net-_d8-pad2_ Q2N2222 +d4 gnd net-_d4-pad2_ 1N4148 +d8 gnd net-_d8-pad2_ 1N4148 +q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222 +q16 net-_q16-pad1_ net-_q12-pad3_ gnd Q2N2222 +r11 vcc net-_q12-pad1_ 600 +r16 vcc net-_q16-pad1_ 1k +r12 net-_q12-pad3_ gnd 400 +r4 vcc net-_q4-pad2_ 4k +q1 net-_q1-pad1_ net-_q1-pad2_ net-_d1-pad2_ Q2N2222 +q5 net-_q1-pad1_ net-_q1-pad2_ net-_d5-pad2_ Q2N2222 +d1 gnd net-_d1-pad2_ 1N4148 +d5 gnd net-_d5-pad2_ 1N4148 +q9 net-_q9-pad1_ net-_q1-pad1_ net-_q13-pad2_ Q2N2222 +q13 net-_q13-pad1_ net-_q13-pad2_ gnd Q2N2222 +r5 vcc net-_q9-pad1_ 600 +r13 vcc net-_q13-pad1_ 1k +r6 net-_q13-pad2_ gnd 400 +r1 vcc net-_q1-pad2_ 4k +q2 net-_q10-pad2_ net-_q2-pad2_ net-_d2-pad2_ Q2N2222 +q6 net-_q10-pad2_ net-_q2-pad2_ net-_d6-pad2_ Q2N2222 +d2 gnd net-_d2-pad2_ 1N4148 +d6 gnd net-_d6-pad2_ 1N4148 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q14 net-_q14-pad1_ net-_q10-pad3_ gnd Q2N2222 +r7 vcc net-_q10-pad1_ 600 +r14 vcc net-_q14-pad1_ 600 +r8 net-_q10-pad3_ gnd 400 +r2 vcc net-_q2-pad2_ 4k +* Control Statements + +.ends SN74LS38 \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS38/SN74LS38_Previous_Values.xml b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS38/SN74LS38_Previous_Values.xml new file mode 100644 index 000000000..7678244f4 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS38/SN74LS38_Previous_Values.xml @@ -0,0 +1 @@ +adc_bridged_bufferdac_bridgeadc_bridged_bufferdac_bridgeadc_bridged_bufferdac_bridgeadc_bridged_bufferdac_bridgeC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\esim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecpssec \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS38/analysis b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS38/analysis new file mode 100644 index 000000000..687c71ec1 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS38/analysis @@ -0,0 +1 @@ +.tran 0e-12 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS606/SN74LS606-cache.lib b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS606/SN74LS606-cache.lib new file mode 100644 index 000000000..9af73b115 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS606/SN74LS606-cache.lib @@ -0,0 +1,106 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# risingedge_dflipflop +# +DEF risingedge_dflipflop U 0 40 Y Y 1 F N +F0 "U" 2850 1800 60 H V C CNN +F1 "risingedge_dflipflop" 2850 2000 60 H V C CNN +F2 "" 2850 1950 60 H V C CNN +F3 "" 2850 1950 60 H V C CNN +DRAW +S 2350 2100 3350 1600 0 1 0 N +X D0 1 2150 1900 200 R 50 50 1 1 I +X clk0 2 2150 1800 200 R 50 50 1 1 I +X Q0 3 3550 1900 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# tristate_nor +# +DEF tristate_nor U 0 40 Y Y 1 F N +F0 "U" 2850 1800 60 H V C CNN +F1 "tristate_nor" 2850 2000 60 H V C CNN +F2 "" 2850 1950 60 H V C CNN +F3 "" 2850 1950 60 H V C CNN +DRAW +S 2350 2100 3350 1500 0 1 0 N +X A0 1 2150 1900 200 R 50 50 1 1 I +X B0 2 2150 1800 200 R 50 50 1 1 I +X EN0 3 2150 1700 200 R 50 50 1 1 I +X Y0 4 3550 1900 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS606/SN74LS606.cir b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS606/SN74LS606.cir new file mode 100644 index 000000000..ea9637dc5 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS606/SN74LS606.cir @@ -0,0 +1,79 @@ +* C:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\SN74LS606\SN74LS606.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/23/25 17:57:07 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U26 Net-_U1-Pad1_ Net-_U26-Pad2_ d_inverter +U28 Net-_U26-Pad2_ Net-_U28-Pad2_ d_inverter +U18 Net-_U1-Pad3_ Net-_U18-Pad2_ Net-_U18-Pad3_ risingedge_dflipflop +U27 Net-_U1-Pad2_ Net-_U10-Pad1_ d_inverter +U30 Net-_U10-Pad1_ Net-_U30-Pad2_ d_inverter +U46 Net-_U46-Pad1_ Net-_U26-Pad2_ Net-_U38-Pad1_ d_and +U47 Net-_U2-Pad3_ Net-_U28-Pad2_ Net-_U38-Pad2_ d_and +U38 Net-_U38-Pad1_ Net-_U38-Pad2_ Net-_U30-Pad2_ Net-_U1-Pad19_ tristate_nor +U2 Net-_U1-Pad4_ Net-_U10-Pad2_ Net-_U2-Pad3_ risingedge_dflipflop +U29 Net-_U10-Pad1_ Net-_U18-Pad2_ d_inverter +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter +U19 Net-_U1-Pad5_ Net-_U19-Pad2_ Net-_U19-Pad3_ risingedge_dflipflop +U48 Net-_U48-Pad1_ Net-_U26-Pad2_ ? d_and +U49 Net-_U3-Pad3_ Net-_U28-Pad2_ Net-_U39-Pad2_ d_and +U39 ? Net-_U39-Pad2_ Net-_U30-Pad2_ Net-_U1-Pad20_ tristate_nor +U3 Net-_U1-Pad6_ Net-_U11-Pad2_ Net-_U3-Pad3_ risingedge_dflipflop +U31 Net-_U10-Pad1_ Net-_U19-Pad2_ d_inverter +U11 Net-_U10-Pad1_ Net-_U11-Pad2_ d_inverter +U20 Net-_U1-Pad7_ Net-_U20-Pad2_ Net-_U20-Pad3_ risingedge_dflipflop +U50 Net-_U50-Pad1_ Net-_U26-Pad2_ Net-_U40-Pad1_ d_and +U51 Net-_U4-Pad3_ Net-_U28-Pad2_ Net-_U40-Pad2_ d_and +U40 Net-_U40-Pad1_ Net-_U40-Pad2_ Net-_U30-Pad2_ Net-_U1-Pad21_ tristate_nor +U4 Net-_U1-Pad8_ Net-_U12-Pad2_ Net-_U4-Pad3_ risingedge_dflipflop +U32 Net-_U10-Pad1_ Net-_U20-Pad2_ d_inverter +U12 Net-_U10-Pad1_ Net-_U12-Pad2_ d_inverter +U22 Net-_U1-Pad9_ Net-_U22-Pad2_ Net-_U22-Pad3_ risingedge_dflipflop +U54 Net-_U54-Pad1_ Net-_U26-Pad2_ Net-_U42-Pad1_ d_and +U55 Net-_U55-Pad1_ Net-_U28-Pad2_ Net-_U42-Pad2_ d_and +U42 Net-_U42-Pad1_ Net-_U42-Pad2_ Net-_U30-Pad2_ Net-_U1-Pad22_ tristate_nor +U6 Net-_U1-Pad10_ Net-_U14-Pad2_ Net-_U55-Pad1_ risingedge_dflipflop +U34 Net-_U10-Pad1_ Net-_U22-Pad2_ d_inverter +U14 Net-_U10-Pad1_ Net-_U14-Pad2_ d_inverter +U21 Net-_U1-Pad11_ Net-_U21-Pad2_ Net-_U21-Pad3_ risingedge_dflipflop +U52 Net-_U52-Pad1_ Net-_U26-Pad2_ Net-_U41-Pad1_ d_and +U53 Net-_U5-Pad3_ Net-_U28-Pad2_ Net-_U41-Pad2_ d_and +U41 Net-_U41-Pad1_ Net-_U41-Pad2_ Net-_U30-Pad2_ Net-_U1-Pad23_ tristate_nor +U5 Net-_U1-Pad12_ Net-_U13-Pad2_ Net-_U5-Pad3_ risingedge_dflipflop +U33 Net-_U10-Pad1_ Net-_U21-Pad2_ d_inverter +U13 Net-_U10-Pad1_ Net-_U13-Pad2_ d_inverter +U23 Net-_U1-Pad13_ Net-_U23-Pad2_ Net-_U23-Pad3_ risingedge_dflipflop +U56 Net-_U56-Pad1_ Net-_U26-Pad2_ Net-_U43-Pad1_ d_and +U57 Net-_U57-Pad1_ Net-_U28-Pad2_ Net-_U43-Pad2_ d_and +U43 Net-_U43-Pad1_ Net-_U43-Pad2_ Net-_U30-Pad2_ Net-_U1-Pad24_ tristate_nor +U7 Net-_U1-Pad14_ Net-_U15-Pad2_ Net-_U57-Pad1_ risingedge_dflipflop +U35 Net-_U10-Pad1_ Net-_U23-Pad2_ d_inverter +U15 Net-_U10-Pad1_ Net-_U15-Pad2_ d_inverter +U24 Net-_U1-Pad15_ Net-_U24-Pad2_ Net-_U24-Pad3_ risingedge_dflipflop +U58 Net-_U58-Pad1_ Net-_U26-Pad2_ Net-_U44-Pad1_ d_and +U59 Net-_U59-Pad1_ Net-_U28-Pad2_ Net-_U44-Pad2_ d_and +U44 Net-_U44-Pad1_ Net-_U44-Pad2_ Net-_U30-Pad2_ Net-_U1-Pad25_ tristate_nor +U8 Net-_U1-Pad16_ Net-_U16-Pad2_ Net-_U59-Pad1_ risingedge_dflipflop +U36 Net-_U10-Pad1_ Net-_U24-Pad2_ d_inverter +U16 Net-_U10-Pad1_ Net-_U16-Pad2_ d_inverter +U25 Net-_U1-Pad17_ Net-_U25-Pad2_ Net-_U25-Pad3_ risingedge_dflipflop +U60 Net-_U60-Pad1_ Net-_U26-Pad2_ Net-_U45-Pad1_ d_and +U61 Net-_U61-Pad1_ Net-_U28-Pad2_ Net-_U45-Pad2_ d_and +U45 Net-_U45-Pad1_ Net-_U45-Pad2_ Net-_U30-Pad2_ Net-_U1-Pad26_ tristate_nor +U9 Net-_U1-Pad18_ Net-_U17-Pad2_ Net-_U61-Pad1_ risingedge_dflipflop +U37 Net-_U10-Pad1_ Net-_U25-Pad2_ d_inverter +U17 Net-_U10-Pad1_ Net-_U17-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ Net-_U1-Pad19_ Net-_U1-Pad20_ Net-_U1-Pad21_ Net-_U1-Pad22_ Net-_U1-Pad23_ Net-_U1-Pad24_ Net-_U1-Pad25_ Net-_U1-Pad26_ PORT +U62 Net-_U18-Pad3_ Net-_U46-Pad1_ d_inverter +U63 Net-_U19-Pad3_ Net-_U48-Pad1_ d_inverter +U64 Net-_U20-Pad3_ Net-_U50-Pad1_ d_inverter +U65 Net-_U21-Pad3_ Net-_U52-Pad1_ d_inverter +U66 Net-_U22-Pad3_ Net-_U54-Pad1_ d_inverter +U67 Net-_U23-Pad3_ Net-_U56-Pad1_ d_inverter +U68 Net-_U24-Pad3_ Net-_U58-Pad1_ d_inverter +U69 Net-_U25-Pad3_ Net-_U60-Pad1_ d_inverter + +.end diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS606/SN74LS606.cir.out b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS606/SN74LS606.cir.out new file mode 100644 index 000000000..74636cf35 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS606/SN74LS606.cir.out @@ -0,0 +1,284 @@ +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\sn74ls606\sn74ls606.cir + +* u26 net-_u1-pad1_ net-_u26-pad2_ d_inverter +* u28 net-_u26-pad2_ net-_u28-pad2_ d_inverter +* u18 net-_u1-pad3_ net-_u18-pad2_ net-_u18-pad3_ risingedge_dflipflop +* u27 net-_u1-pad2_ net-_u10-pad1_ d_inverter +* u30 net-_u10-pad1_ net-_u30-pad2_ d_inverter +* u46 net-_u46-pad1_ net-_u26-pad2_ net-_u38-pad1_ d_and +* u47 net-_u2-pad3_ net-_u28-pad2_ net-_u38-pad2_ d_and +* u38 net-_u38-pad1_ net-_u38-pad2_ net-_u30-pad2_ net-_u1-pad19_ tristate_nor +* u2 net-_u1-pad4_ net-_u10-pad2_ net-_u2-pad3_ risingedge_dflipflop +* u29 net-_u10-pad1_ net-_u18-pad2_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u19 net-_u1-pad5_ net-_u19-pad2_ net-_u19-pad3_ risingedge_dflipflop +* u48 net-_u48-pad1_ net-_u26-pad2_ ? d_and +* u49 net-_u3-pad3_ net-_u28-pad2_ net-_u39-pad2_ d_and +* u39 ? net-_u39-pad2_ net-_u30-pad2_ net-_u1-pad20_ tristate_nor +* u3 net-_u1-pad6_ net-_u11-pad2_ net-_u3-pad3_ risingedge_dflipflop +* u31 net-_u10-pad1_ net-_u19-pad2_ d_inverter +* u11 net-_u10-pad1_ net-_u11-pad2_ d_inverter +* u20 net-_u1-pad7_ net-_u20-pad2_ net-_u20-pad3_ risingedge_dflipflop +* u50 net-_u50-pad1_ net-_u26-pad2_ net-_u40-pad1_ d_and +* u51 net-_u4-pad3_ net-_u28-pad2_ net-_u40-pad2_ d_and +* u40 net-_u40-pad1_ net-_u40-pad2_ net-_u30-pad2_ net-_u1-pad21_ tristate_nor +* u4 net-_u1-pad8_ net-_u12-pad2_ net-_u4-pad3_ risingedge_dflipflop +* u32 net-_u10-pad1_ net-_u20-pad2_ d_inverter +* u12 net-_u10-pad1_ net-_u12-pad2_ d_inverter +* u22 net-_u1-pad9_ net-_u22-pad2_ net-_u22-pad3_ risingedge_dflipflop +* u54 net-_u54-pad1_ net-_u26-pad2_ net-_u42-pad1_ d_and +* u55 net-_u55-pad1_ net-_u28-pad2_ net-_u42-pad2_ d_and +* u42 net-_u42-pad1_ net-_u42-pad2_ net-_u30-pad2_ net-_u1-pad22_ tristate_nor +* u6 net-_u1-pad10_ net-_u14-pad2_ net-_u55-pad1_ risingedge_dflipflop +* u34 net-_u10-pad1_ net-_u22-pad2_ d_inverter +* u14 net-_u10-pad1_ net-_u14-pad2_ d_inverter +* u21 net-_u1-pad11_ net-_u21-pad2_ net-_u21-pad3_ risingedge_dflipflop +* u52 net-_u52-pad1_ net-_u26-pad2_ net-_u41-pad1_ d_and +* u53 net-_u5-pad3_ net-_u28-pad2_ net-_u41-pad2_ d_and +* u41 net-_u41-pad1_ net-_u41-pad2_ net-_u30-pad2_ net-_u1-pad23_ tristate_nor +* u5 net-_u1-pad12_ net-_u13-pad2_ net-_u5-pad3_ risingedge_dflipflop +* u33 net-_u10-pad1_ net-_u21-pad2_ d_inverter +* u13 net-_u10-pad1_ net-_u13-pad2_ d_inverter +* u23 net-_u1-pad13_ net-_u23-pad2_ net-_u23-pad3_ risingedge_dflipflop +* u56 net-_u56-pad1_ net-_u26-pad2_ net-_u43-pad1_ d_and +* u57 net-_u57-pad1_ net-_u28-pad2_ net-_u43-pad2_ d_and +* u43 net-_u43-pad1_ net-_u43-pad2_ net-_u30-pad2_ net-_u1-pad24_ tristate_nor +* u7 net-_u1-pad14_ net-_u15-pad2_ net-_u57-pad1_ risingedge_dflipflop +* u35 net-_u10-pad1_ net-_u23-pad2_ d_inverter +* u15 net-_u10-pad1_ net-_u15-pad2_ d_inverter +* u24 net-_u1-pad15_ net-_u24-pad2_ net-_u24-pad3_ risingedge_dflipflop +* u58 net-_u58-pad1_ net-_u26-pad2_ net-_u44-pad1_ d_and +* u59 net-_u59-pad1_ net-_u28-pad2_ net-_u44-pad2_ d_and +* u44 net-_u44-pad1_ net-_u44-pad2_ net-_u30-pad2_ net-_u1-pad25_ tristate_nor +* u8 net-_u1-pad16_ net-_u16-pad2_ net-_u59-pad1_ risingedge_dflipflop +* u36 net-_u10-pad1_ net-_u24-pad2_ d_inverter +* u16 net-_u10-pad1_ net-_u16-pad2_ d_inverter +* u25 net-_u1-pad17_ net-_u25-pad2_ net-_u25-pad3_ risingedge_dflipflop +* u60 net-_u60-pad1_ net-_u26-pad2_ net-_u45-pad1_ d_and +* u61 net-_u61-pad1_ net-_u28-pad2_ net-_u45-pad2_ d_and +* u45 net-_u45-pad1_ net-_u45-pad2_ net-_u30-pad2_ net-_u1-pad26_ tristate_nor +* u9 net-_u1-pad18_ net-_u17-pad2_ net-_u61-pad1_ risingedge_dflipflop +* u37 net-_u10-pad1_ net-_u25-pad2_ d_inverter +* u17 net-_u10-pad1_ net-_u17-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ net-_u1-pad24_ net-_u1-pad25_ net-_u1-pad26_ port +* u62 net-_u18-pad3_ net-_u46-pad1_ d_inverter +* u63 net-_u19-pad3_ net-_u48-pad1_ d_inverter +* u64 net-_u20-pad3_ net-_u50-pad1_ d_inverter +* u65 net-_u21-pad3_ net-_u52-pad1_ d_inverter +* u66 net-_u22-pad3_ net-_u54-pad1_ d_inverter +* u67 net-_u23-pad3_ net-_u56-pad1_ d_inverter +* u68 net-_u24-pad3_ net-_u58-pad1_ d_inverter +* u69 net-_u25-pad3_ net-_u60-pad1_ d_inverter +a1 net-_u1-pad1_ net-_u26-pad2_ u26 +a2 net-_u26-pad2_ net-_u28-pad2_ u28 +a3 [net-_u1-pad3_ ] [net-_u18-pad2_ ] [net-_u18-pad3_ ] u18 +a4 net-_u1-pad2_ net-_u10-pad1_ u27 +a5 net-_u10-pad1_ net-_u30-pad2_ u30 +a6 [net-_u46-pad1_ net-_u26-pad2_ ] net-_u38-pad1_ u46 +a7 [net-_u2-pad3_ net-_u28-pad2_ ] net-_u38-pad2_ u47 +a8 [net-_u38-pad1_ ] [net-_u38-pad2_ ] [net-_u30-pad2_ ] [net-_u1-pad19_ ] u38 +a9 [net-_u1-pad4_ ] [net-_u10-pad2_ ] [net-_u2-pad3_ ] u2 +a10 net-_u10-pad1_ net-_u18-pad2_ u29 +a11 net-_u10-pad1_ net-_u10-pad2_ u10 +a12 [net-_u1-pad5_ ] [net-_u19-pad2_ ] [net-_u19-pad3_ ] u19 +a13 [net-_u48-pad1_ net-_u26-pad2_ ] ? u48 +a14 [net-_u3-pad3_ net-_u28-pad2_ ] net-_u39-pad2_ u49 +a15 [? ] [net-_u39-pad2_ ] [net-_u30-pad2_ ] [net-_u1-pad20_ ] u39 +a16 [net-_u1-pad6_ ] [net-_u11-pad2_ ] [net-_u3-pad3_ ] u3 +a17 net-_u10-pad1_ net-_u19-pad2_ u31 +a18 net-_u10-pad1_ net-_u11-pad2_ u11 +a19 [net-_u1-pad7_ ] [net-_u20-pad2_ ] [net-_u20-pad3_ ] u20 +a20 [net-_u50-pad1_ net-_u26-pad2_ ] net-_u40-pad1_ u50 +a21 [net-_u4-pad3_ net-_u28-pad2_ ] net-_u40-pad2_ u51 +a22 [net-_u40-pad1_ ] [net-_u40-pad2_ ] [net-_u30-pad2_ ] [net-_u1-pad21_ ] u40 +a23 [net-_u1-pad8_ ] [net-_u12-pad2_ ] [net-_u4-pad3_ ] u4 +a24 net-_u10-pad1_ net-_u20-pad2_ u32 +a25 net-_u10-pad1_ net-_u12-pad2_ u12 +a26 [net-_u1-pad9_ ] [net-_u22-pad2_ ] [net-_u22-pad3_ ] u22 +a27 [net-_u54-pad1_ net-_u26-pad2_ ] net-_u42-pad1_ u54 +a28 [net-_u55-pad1_ net-_u28-pad2_ ] net-_u42-pad2_ u55 +a29 [net-_u42-pad1_ ] [net-_u42-pad2_ ] [net-_u30-pad2_ ] [net-_u1-pad22_ ] u42 +a30 [net-_u1-pad10_ ] [net-_u14-pad2_ ] [net-_u55-pad1_ ] u6 +a31 net-_u10-pad1_ net-_u22-pad2_ u34 +a32 net-_u10-pad1_ net-_u14-pad2_ u14 +a33 [net-_u1-pad11_ ] [net-_u21-pad2_ ] [net-_u21-pad3_ ] u21 +a34 [net-_u52-pad1_ net-_u26-pad2_ ] net-_u41-pad1_ u52 +a35 [net-_u5-pad3_ net-_u28-pad2_ ] net-_u41-pad2_ u53 +a36 [net-_u41-pad1_ ] [net-_u41-pad2_ ] [net-_u30-pad2_ ] [net-_u1-pad23_ ] u41 +a37 [net-_u1-pad12_ ] [net-_u13-pad2_ ] [net-_u5-pad3_ ] u5 +a38 net-_u10-pad1_ net-_u21-pad2_ u33 +a39 net-_u10-pad1_ net-_u13-pad2_ u13 +a40 [net-_u1-pad13_ ] [net-_u23-pad2_ ] [net-_u23-pad3_ ] u23 +a41 [net-_u56-pad1_ net-_u26-pad2_ ] net-_u43-pad1_ u56 +a42 [net-_u57-pad1_ net-_u28-pad2_ ] net-_u43-pad2_ u57 +a43 [net-_u43-pad1_ ] [net-_u43-pad2_ ] [net-_u30-pad2_ ] [net-_u1-pad24_ ] u43 +a44 [net-_u1-pad14_ ] [net-_u15-pad2_ ] [net-_u57-pad1_ ] u7 +a45 net-_u10-pad1_ net-_u23-pad2_ u35 +a46 net-_u10-pad1_ net-_u15-pad2_ u15 +a47 [net-_u1-pad15_ ] [net-_u24-pad2_ ] [net-_u24-pad3_ ] u24 +a48 [net-_u58-pad1_ net-_u26-pad2_ ] net-_u44-pad1_ u58 +a49 [net-_u59-pad1_ net-_u28-pad2_ ] net-_u44-pad2_ u59 +a50 [net-_u44-pad1_ ] [net-_u44-pad2_ ] [net-_u30-pad2_ ] [net-_u1-pad25_ ] u44 +a51 [net-_u1-pad16_ ] [net-_u16-pad2_ ] [net-_u59-pad1_ ] u8 +a52 net-_u10-pad1_ net-_u24-pad2_ u36 +a53 net-_u10-pad1_ net-_u16-pad2_ u16 +a54 [net-_u1-pad17_ ] [net-_u25-pad2_ ] [net-_u25-pad3_ ] u25 +a55 [net-_u60-pad1_ net-_u26-pad2_ ] net-_u45-pad1_ u60 +a56 [net-_u61-pad1_ net-_u28-pad2_ ] net-_u45-pad2_ u61 +a57 [net-_u45-pad1_ ] [net-_u45-pad2_ ] [net-_u30-pad2_ ] [net-_u1-pad26_ ] u45 +a58 [net-_u1-pad18_ ] [net-_u17-pad2_ ] [net-_u61-pad1_ ] u9 +a59 net-_u10-pad1_ net-_u25-pad2_ u37 +a60 net-_u10-pad1_ net-_u17-pad2_ u17 +a61 net-_u18-pad3_ net-_u46-pad1_ u62 +a62 net-_u19-pad3_ net-_u48-pad1_ u63 +a63 net-_u20-pad3_ net-_u50-pad1_ u64 +a64 net-_u21-pad3_ net-_u52-pad1_ u65 +a65 net-_u22-pad3_ net-_u54-pad1_ u66 +a66 net-_u23-pad3_ net-_u56-pad1_ u67 +a67 net-_u24-pad3_ net-_u58-pad1_ u68 +a68 net-_u25-pad3_ net-_u60-pad1_ u69 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u18 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u46 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u47 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: tristate_nor, NgSpice Name: tristate_nor +.model u38 tristate_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u2 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u19 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u48 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u49 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: tristate_nor, NgSpice Name: tristate_nor +.model u39 tristate_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u3 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u20 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u50 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u51 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: tristate_nor, NgSpice Name: tristate_nor +.model u40 tristate_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u4 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u22 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u54 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u55 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: tristate_nor, NgSpice Name: tristate_nor +.model u42 tristate_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u6 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u21 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u52 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u53 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: tristate_nor, NgSpice Name: tristate_nor +.model u41 tristate_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u5 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u23 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u56 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u57 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: tristate_nor, NgSpice Name: tristate_nor +.model u43 tristate_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u7 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u24 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u58 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u59 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: tristate_nor, NgSpice Name: tristate_nor +.model u44 tristate_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u8 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u25 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u60 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u61 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: tristate_nor, NgSpice Name: tristate_nor +.model u45 tristate_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u9 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u62 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u63 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u64 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u65 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u66 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u67 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u68 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u69 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS606/SN74LS606.pro b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS606/SN74LS606.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS606/SN74LS606.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS606/SN74LS606.sch b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS606/SN74LS606.sch new file mode 100644 index 000000000..6dc6a9331 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS606/SN74LS606.sch @@ -0,0 +1,1518 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A1 33110 23386 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U26 +U 1 1 68591BCD +P 10100 3500 +F 0 "U26" H 10100 3400 60 0000 C CNN +F 1 "d_inverter" H 10100 3650 60 0000 C CNN +F 2 "" H 10150 3450 60 0000 C CNN +F 3 "" H 10150 3450 60 0000 C CNN + 1 10100 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U28 +U 1 1 68591C8E +P 11400 3500 +F 0 "U28" H 11400 3400 60 0000 C CNN +F 1 "d_inverter" H 11400 3650 60 0000 C CNN +F 2 "" H 11450 3450 60 0000 C CNN +F 3 "" H 11450 3450 60 0000 C CNN + 1 11400 3500 + 1 0 0 -1 +$EndComp +$Comp +L risingedge_dflipflop U18 +U 1 1 68591CD8 +P 9600 7050 +F 0 "U18" H 12450 8850 60 0000 C CNN +F 1 "risingedge_dflipflop" H 12450 9050 60 0000 C CNN +F 2 "" H 12450 9000 60 0000 C CNN +F 3 "" H 12450 9000 60 0000 C CNN + 1 9600 7050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U27 +U 1 1 68591DF6 +P 10150 4150 +F 0 "U27" H 10150 4050 60 0000 C CNN +F 1 "d_inverter" H 10150 4300 60 0000 C CNN +F 2 "" H 10200 4100 60 0000 C CNN +F 3 "" H 10200 4100 60 0000 C CNN + 1 10150 4150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U30 +U 1 1 68591DFC +P 11450 4150 +F 0 "U30" H 11450 4050 60 0000 C CNN +F 1 "d_inverter" H 11450 4300 60 0000 C CNN +F 2 "" H 11500 4100 60 0000 C CNN +F 3 "" H 11500 4100 60 0000 C CNN + 1 11450 4150 + 1 0 0 -1 +$EndComp +$Comp +L d_and U46 +U 1 1 68591E2C +P 14400 5200 +F 0 "U46" H 14400 5200 60 0000 C CNN +F 1 "d_and" H 14450 5300 60 0000 C CNN +F 2 "" H 14400 5200 60 0000 C CNN +F 3 "" H 14400 5200 60 0000 C CNN + 1 14400 5200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U47 +U 1 1 68591E97 +P 14000 5600 +F 0 "U47" H 14000 5600 60 0000 C CNN +F 1 "d_and" H 14050 5700 60 0000 C CNN +F 2 "" H 14000 5600 60 0000 C CNN +F 3 "" H 14000 5600 60 0000 C CNN + 1 14000 5600 + 1 0 0 -1 +$EndComp +$Comp +L tristate_nor U38 +U 1 1 68591F62 +P 12900 7150 +F 0 "U38" H 15750 8950 60 0000 C CNN +F 1 "tristate_nor" H 15750 9150 60 0000 C CNN +F 2 "" H 15750 9100 60 0000 C CNN +F 3 "" H 15750 9100 60 0000 C CNN + 1 12900 7150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 15050 5150 15050 5250 +Wire Wire Line + 15050 5350 14550 5350 +Wire Wire Line + 14550 5350 14550 5550 +Wire Wire Line + 14550 5550 14450 5550 +$Comp +L risingedge_dflipflop U2 +U 1 1 68592230 +P 6900 7750 +F 0 "U2" H 9750 9550 60 0000 C CNN +F 1 "risingedge_dflipflop" H 9750 9750 60 0000 C CNN +F 2 "" H 9750 9700 60 0000 C CNN +F 3 "" H 9750 9700 60 0000 C CNN + 1 6900 7750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10400 3500 11100 3500 +Wire Wire Line + 11150 4150 10450 4150 +Wire Wire Line + 9050 5850 7100 5850 +$Comp +L d_inverter U29 +U 1 1 685924C3 +P 11400 5250 +F 0 "U29" H 11400 5150 60 0000 C CNN +F 1 "d_inverter" H 11400 5400 60 0000 C CNN +F 2 "" H 11450 5200 60 0000 C CNN +F 3 "" H 11450 5200 60 0000 C CNN + 1 11400 5250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 11700 5250 11750 5250 +$Comp +L d_inverter U10 +U 1 1 68592BCD +P 8700 5950 +F 0 "U10" H 8700 5850 60 0000 C CNN +F 1 "d_inverter" H 8700 6100 60 0000 C CNN +F 2 "" H 8750 5900 60 0000 C CNN +F 3 "" H 8750 5900 60 0000 C CNN + 1 8700 5950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9000 5950 9050 5950 +$Comp +L risingedge_dflipflop U19 +U 1 1 68592EC2 +P 9650 8550 +F 0 "U19" H 12500 10350 60 0000 C CNN +F 1 "risingedge_dflipflop" H 12500 10550 60 0000 C CNN +F 2 "" H 12500 10500 60 0000 C CNN +F 3 "" H 12500 10500 60 0000 C CNN + 1 9650 8550 + 1 0 0 -1 +$EndComp +$Comp +L d_and U48 +U 1 1 68592EC8 +P 14550 6750 +F 0 "U48" H 14550 6750 60 0000 C CNN +F 1 "d_and" H 14600 6850 60 0000 C CNN +F 2 "" H 14550 6750 60 0000 C CNN +F 3 "" H 14550 6750 60 0000 C CNN + 1 14550 6750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U49 +U 1 1 68592ECE +P 14050 7100 +F 0 "U49" H 14050 7100 60 0000 C CNN +F 1 "d_and" H 14100 7200 60 0000 C CNN +F 2 "" H 14050 7100 60 0000 C CNN +F 3 "" H 14050 7100 60 0000 C CNN + 1 14050 7100 + 1 0 0 -1 +$EndComp +$Comp +L tristate_nor U39 +U 1 1 68592ED4 +P 12950 8650 +F 0 "U39" H 15800 10450 60 0000 C CNN +F 1 "tristate_nor" H 15800 10650 60 0000 C CNN +F 2 "" H 15800 10600 60 0000 C CNN +F 3 "" H 15800 10600 60 0000 C CNN + 1 12950 8650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 15100 6700 15100 6750 +Wire Wire Line + 15100 6850 14600 6850 +Wire Wire Line + 14600 6850 14600 7050 +Wire Wire Line + 14600 7050 14500 7050 +$Comp +L risingedge_dflipflop U3 +U 1 1 68592EDF +P 6950 9250 +F 0 "U3" H 9800 11050 60 0000 C CNN +F 1 "risingedge_dflipflop" H 9800 11250 60 0000 C CNN +F 2 "" H 9800 11200 60 0000 C CNN +F 3 "" H 9800 11200 60 0000 C CNN + 1 6950 9250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9100 7350 7150 7350 +$Comp +L d_inverter U31 +U 1 1 68592EE6 +P 11450 6750 +F 0 "U31" H 11450 6650 60 0000 C CNN +F 1 "d_inverter" H 11450 6900 60 0000 C CNN +F 2 "" H 11500 6700 60 0000 C CNN +F 3 "" H 11500 6700 60 0000 C CNN + 1 11450 6750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 11750 6750 11800 6750 +Wire Wire Line + 13200 6650 13600 6650 +$Comp +L d_inverter U11 +U 1 1 68592EEE +P 8750 7450 +F 0 "U11" H 8750 7350 60 0000 C CNN +F 1 "d_inverter" H 8750 7600 60 0000 C CNN +F 2 "" H 8800 7400 60 0000 C CNN +F 3 "" H 8800 7400 60 0000 C CNN + 1 8750 7450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9050 7450 9100 7450 +$Comp +L risingedge_dflipflop U20 +U 1 1 68593189 +P 9700 10000 +F 0 "U20" H 12550 11800 60 0000 C CNN +F 1 "risingedge_dflipflop" H 12550 12000 60 0000 C CNN +F 2 "" H 12550 11950 60 0000 C CNN +F 3 "" H 12550 11950 60 0000 C CNN + 1 9700 10000 + 1 0 0 -1 +$EndComp +$Comp +L d_and U50 +U 1 1 6859318F +P 14700 8200 +F 0 "U50" H 14700 8200 60 0000 C CNN +F 1 "d_and" H 14750 8300 60 0000 C CNN +F 2 "" H 14700 8200 60 0000 C CNN +F 3 "" H 14700 8200 60 0000 C CNN + 1 14700 8200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U51 +U 1 1 68593195 +P 14100 8550 +F 0 "U51" H 14100 8550 60 0000 C CNN +F 1 "d_and" H 14150 8650 60 0000 C CNN +F 2 "" H 14100 8550 60 0000 C CNN +F 3 "" H 14100 8550 60 0000 C CNN + 1 14100 8550 + 1 0 0 -1 +$EndComp +$Comp +L tristate_nor U40 +U 1 1 6859319B +P 13000 10100 +F 0 "U40" H 15850 11900 60 0000 C CNN +F 1 "tristate_nor" H 15850 12100 60 0000 C CNN +F 2 "" H 15850 12050 60 0000 C CNN +F 3 "" H 15850 12050 60 0000 C CNN + 1 13000 10100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 15150 8150 15150 8200 +Wire Wire Line + 15150 8300 14650 8300 +Wire Wire Line + 14650 8300 14650 8500 +Wire Wire Line + 14650 8500 14550 8500 +$Comp +L risingedge_dflipflop U4 +U 1 1 685931A6 +P 7000 10700 +F 0 "U4" H 9850 12500 60 0000 C CNN +F 1 "risingedge_dflipflop" H 9850 12700 60 0000 C CNN +F 2 "" H 9850 12650 60 0000 C CNN +F 3 "" H 9850 12650 60 0000 C CNN + 1 7000 10700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9150 8800 7200 8800 +$Comp +L d_inverter U32 +U 1 1 685931AD +P 11500 8200 +F 0 "U32" H 11500 8100 60 0000 C CNN +F 1 "d_inverter" H 11500 8350 60 0000 C CNN +F 2 "" H 11550 8150 60 0000 C CNN +F 3 "" H 11550 8150 60 0000 C CNN + 1 11500 8200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 11800 8200 11850 8200 +Wire Wire Line + 13250 8100 13650 8100 +$Comp +L d_inverter U12 +U 1 1 685931B5 +P 8800 8900 +F 0 "U12" H 8800 8800 60 0000 C CNN +F 1 "d_inverter" H 8800 9050 60 0000 C CNN +F 2 "" H 8850 8850 60 0000 C CNN +F 3 "" H 8850 8850 60 0000 C CNN + 1 8800 8900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9100 8900 9150 8900 +$Comp +L risingedge_dflipflop U22 +U 1 1 685931BC +P 9750 11500 +F 0 "U22" H 12600 13300 60 0000 C CNN +F 1 "risingedge_dflipflop" H 12600 13500 60 0000 C CNN +F 2 "" H 12600 13450 60 0000 C CNN +F 3 "" H 12600 13450 60 0000 C CNN + 1 9750 11500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U54 +U 1 1 685931C2 +P 14750 9700 +F 0 "U54" H 14750 9700 60 0000 C CNN +F 1 "d_and" H 14800 9800 60 0000 C CNN +F 2 "" H 14750 9700 60 0000 C CNN +F 3 "" H 14750 9700 60 0000 C CNN + 1 14750 9700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U55 +U 1 1 685931C8 +P 14150 10050 +F 0 "U55" H 14150 10050 60 0000 C CNN +F 1 "d_and" H 14200 10150 60 0000 C CNN +F 2 "" H 14150 10050 60 0000 C CNN +F 3 "" H 14150 10050 60 0000 C CNN + 1 14150 10050 + 1 0 0 -1 +$EndComp +$Comp +L tristate_nor U42 +U 1 1 685931CE +P 13050 11600 +F 0 "U42" H 15900 13400 60 0000 C CNN +F 1 "tristate_nor" H 15900 13600 60 0000 C CNN +F 2 "" H 15900 13550 60 0000 C CNN +F 3 "" H 15900 13550 60 0000 C CNN + 1 13050 11600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 15200 9650 15200 9700 +Wire Wire Line + 15200 9800 14700 9800 +Wire Wire Line + 14700 9800 14700 10000 +Wire Wire Line + 14700 10000 14600 10000 +$Comp +L risingedge_dflipflop U6 +U 1 1 685931D9 +P 7050 12200 +F 0 "U6" H 9900 14000 60 0000 C CNN +F 1 "risingedge_dflipflop" H 9900 14200 60 0000 C CNN +F 2 "" H 9900 14150 60 0000 C CNN +F 3 "" H 9900 14150 60 0000 C CNN + 1 7050 12200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9200 10300 7250 10300 +$Comp +L d_inverter U34 +U 1 1 685931E0 +P 11550 9700 +F 0 "U34" H 11550 9600 60 0000 C CNN +F 1 "d_inverter" H 11550 9850 60 0000 C CNN +F 2 "" H 11600 9650 60 0000 C CNN +F 3 "" H 11600 9650 60 0000 C CNN + 1 11550 9700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 11850 9700 11900 9700 +Wire Wire Line + 13300 9600 13700 9600 +$Comp +L d_inverter U14 +U 1 1 685931E8 +P 8850 10400 +F 0 "U14" H 8850 10300 60 0000 C CNN +F 1 "d_inverter" H 8850 10550 60 0000 C CNN +F 2 "" H 8900 10350 60 0000 C CNN +F 3 "" H 8900 10350 60 0000 C CNN + 1 8850 10400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9150 10400 9200 10400 +$Comp +L risingedge_dflipflop U21 +U 1 1 68593713 +P 9700 13150 +F 0 "U21" H 12550 14950 60 0000 C CNN +F 1 "risingedge_dflipflop" H 12550 15150 60 0000 C CNN +F 2 "" H 12550 15100 60 0000 C CNN +F 3 "" H 12550 15100 60 0000 C CNN + 1 9700 13150 + 1 0 0 -1 +$EndComp +$Comp +L d_and U52 +U 1 1 68593719 +P 14700 11350 +F 0 "U52" H 14700 11350 60 0000 C CNN +F 1 "d_and" H 14750 11450 60 0000 C CNN +F 2 "" H 14700 11350 60 0000 C CNN +F 3 "" H 14700 11350 60 0000 C CNN + 1 14700 11350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U53 +U 1 1 6859371F +P 14100 11700 +F 0 "U53" H 14100 11700 60 0000 C CNN +F 1 "d_and" H 14150 11800 60 0000 C CNN +F 2 "" H 14100 11700 60 0000 C CNN +F 3 "" H 14100 11700 60 0000 C CNN + 1 14100 11700 + 1 0 0 -1 +$EndComp +$Comp +L tristate_nor U41 +U 1 1 68593725 +P 13000 13250 +F 0 "U41" H 15850 15050 60 0000 C CNN +F 1 "tristate_nor" H 15850 15250 60 0000 C CNN +F 2 "" H 15850 15200 60 0000 C CNN +F 3 "" H 15850 15200 60 0000 C CNN + 1 13000 13250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 15150 11300 15150 11350 +Wire Wire Line + 15150 11450 14650 11450 +Wire Wire Line + 14650 11450 14650 11650 +Wire Wire Line + 14650 11650 14550 11650 +$Comp +L risingedge_dflipflop U5 +U 1 1 68593730 +P 7000 13850 +F 0 "U5" H 9850 15650 60 0000 C CNN +F 1 "risingedge_dflipflop" H 9850 15850 60 0000 C CNN +F 2 "" H 9850 15800 60 0000 C CNN +F 3 "" H 9850 15800 60 0000 C CNN + 1 7000 13850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9150 11950 7200 11950 +$Comp +L d_inverter U33 +U 1 1 68593737 +P 11500 11350 +F 0 "U33" H 11500 11250 60 0000 C CNN +F 1 "d_inverter" H 11500 11500 60 0000 C CNN +F 2 "" H 11550 11300 60 0000 C CNN +F 3 "" H 11550 11300 60 0000 C CNN + 1 11500 11350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 11800 11350 11850 11350 +Wire Wire Line + 13250 11250 13650 11250 +$Comp +L d_inverter U13 +U 1 1 6859373F +P 8800 12050 +F 0 "U13" H 8800 11950 60 0000 C CNN +F 1 "d_inverter" H 8800 12200 60 0000 C CNN +F 2 "" H 8850 12000 60 0000 C CNN +F 3 "" H 8850 12000 60 0000 C CNN + 1 8800 12050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9100 12050 9150 12050 +$Comp +L risingedge_dflipflop U23 +U 1 1 68593746 +P 9750 14650 +F 0 "U23" H 12600 16450 60 0000 C CNN +F 1 "risingedge_dflipflop" H 12600 16650 60 0000 C CNN +F 2 "" H 12600 16600 60 0000 C CNN +F 3 "" H 12600 16600 60 0000 C CNN + 1 9750 14650 + 1 0 0 -1 +$EndComp +$Comp +L d_and U56 +U 1 1 6859374C +P 14750 12850 +F 0 "U56" H 14750 12850 60 0000 C CNN +F 1 "d_and" H 14800 12950 60 0000 C CNN +F 2 "" H 14750 12850 60 0000 C CNN +F 3 "" H 14750 12850 60 0000 C CNN + 1 14750 12850 + 1 0 0 -1 +$EndComp +$Comp +L d_and U57 +U 1 1 68593752 +P 14150 13200 +F 0 "U57" H 14150 13200 60 0000 C CNN +F 1 "d_and" H 14200 13300 60 0000 C CNN +F 2 "" H 14150 13200 60 0000 C CNN +F 3 "" H 14150 13200 60 0000 C CNN + 1 14150 13200 + 1 0 0 -1 +$EndComp +$Comp +L tristate_nor U43 +U 1 1 68593758 +P 13050 14750 +F 0 "U43" H 15900 16550 60 0000 C CNN +F 1 "tristate_nor" H 15900 16750 60 0000 C CNN +F 2 "" H 15900 16700 60 0000 C CNN +F 3 "" H 15900 16700 60 0000 C CNN + 1 13050 14750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 15200 12800 15200 12850 +Wire Wire Line + 15200 12950 14700 12950 +Wire Wire Line + 14700 12950 14700 13150 +Wire Wire Line + 14700 13150 14600 13150 +$Comp +L risingedge_dflipflop U7 +U 1 1 68593763 +P 7050 15350 +F 0 "U7" H 9900 17150 60 0000 C CNN +F 1 "risingedge_dflipflop" H 9900 17350 60 0000 C CNN +F 2 "" H 9900 17300 60 0000 C CNN +F 3 "" H 9900 17300 60 0000 C CNN + 1 7050 15350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9200 13450 7250 13450 +$Comp +L d_inverter U35 +U 1 1 6859376A +P 11550 12850 +F 0 "U35" H 11550 12750 60 0000 C CNN +F 1 "d_inverter" H 11550 13000 60 0000 C CNN +F 2 "" H 11600 12800 60 0000 C CNN +F 3 "" H 11600 12800 60 0000 C CNN + 1 11550 12850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 11850 12850 11900 12850 +Wire Wire Line + 13300 12750 13700 12750 +$Comp +L d_inverter U15 +U 1 1 68593772 +P 8850 13550 +F 0 "U15" H 8850 13450 60 0000 C CNN +F 1 "d_inverter" H 8850 13700 60 0000 C CNN +F 2 "" H 8900 13500 60 0000 C CNN +F 3 "" H 8900 13500 60 0000 C CNN + 1 8850 13550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9150 13550 9200 13550 +$Comp +L risingedge_dflipflop U24 +U 1 1 68593779 +P 9800 16100 +F 0 "U24" H 12650 17900 60 0000 C CNN +F 1 "risingedge_dflipflop" H 12650 18100 60 0000 C CNN +F 2 "" H 12650 18050 60 0000 C CNN +F 3 "" H 12650 18050 60 0000 C CNN + 1 9800 16100 + 1 0 0 -1 +$EndComp +$Comp +L d_and U58 +U 1 1 6859377F +P 14800 14300 +F 0 "U58" H 14800 14300 60 0000 C CNN +F 1 "d_and" H 14850 14400 60 0000 C CNN +F 2 "" H 14800 14300 60 0000 C CNN +F 3 "" H 14800 14300 60 0000 C CNN + 1 14800 14300 + 1 0 0 -1 +$EndComp +$Comp +L d_and U59 +U 1 1 68593785 +P 14200 14650 +F 0 "U59" H 14200 14650 60 0000 C CNN +F 1 "d_and" H 14250 14750 60 0000 C CNN +F 2 "" H 14200 14650 60 0000 C CNN +F 3 "" H 14200 14650 60 0000 C CNN + 1 14200 14650 + 1 0 0 -1 +$EndComp +$Comp +L tristate_nor U44 +U 1 1 6859378B +P 13100 16200 +F 0 "U44" H 15950 18000 60 0000 C CNN +F 1 "tristate_nor" H 15950 18200 60 0000 C CNN +F 2 "" H 15950 18150 60 0000 C CNN +F 3 "" H 15950 18150 60 0000 C CNN + 1 13100 16200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 15250 14250 15250 14300 +Wire Wire Line + 15250 14400 14750 14400 +Wire Wire Line + 14750 14400 14750 14600 +Wire Wire Line + 14750 14600 14650 14600 +$Comp +L risingedge_dflipflop U8 +U 1 1 68593796 +P 7100 16800 +F 0 "U8" H 9950 18600 60 0000 C CNN +F 1 "risingedge_dflipflop" H 9950 18800 60 0000 C CNN +F 2 "" H 9950 18750 60 0000 C CNN +F 3 "" H 9950 18750 60 0000 C CNN + 1 7100 16800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9250 14900 7300 14900 +$Comp +L d_inverter U36 +U 1 1 6859379D +P 11600 14300 +F 0 "U36" H 11600 14200 60 0000 C CNN +F 1 "d_inverter" H 11600 14450 60 0000 C CNN +F 2 "" H 11650 14250 60 0000 C CNN +F 3 "" H 11650 14250 60 0000 C CNN + 1 11600 14300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 11900 14300 11950 14300 +Wire Wire Line + 13350 14200 13800 14200 +$Comp +L d_inverter U16 +U 1 1 685937A5 +P 8900 15000 +F 0 "U16" H 8900 14900 60 0000 C CNN +F 1 "d_inverter" H 8900 15150 60 0000 C CNN +F 2 "" H 8950 14950 60 0000 C CNN +F 3 "" H 8950 14950 60 0000 C CNN + 1 8900 15000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9200 15000 9250 15000 +$Comp +L risingedge_dflipflop U25 +U 1 1 685937AC +P 9850 17600 +F 0 "U25" H 12700 19400 60 0000 C CNN +F 1 "risingedge_dflipflop" H 12700 19600 60 0000 C CNN +F 2 "" H 12700 19550 60 0000 C CNN +F 3 "" H 12700 19550 60 0000 C CNN + 1 9850 17600 + 1 0 0 -1 +$EndComp +$Comp +L d_and U60 +U 1 1 685937B2 +P 14850 15800 +F 0 "U60" H 14850 15800 60 0000 C CNN +F 1 "d_and" H 14900 15900 60 0000 C CNN +F 2 "" H 14850 15800 60 0000 C CNN +F 3 "" H 14850 15800 60 0000 C CNN + 1 14850 15800 + 1 0 0 -1 +$EndComp +$Comp +L d_and U61 +U 1 1 685937B8 +P 14250 16150 +F 0 "U61" H 14250 16150 60 0000 C CNN +F 1 "d_and" H 14300 16250 60 0000 C CNN +F 2 "" H 14250 16150 60 0000 C CNN +F 3 "" H 14250 16150 60 0000 C CNN + 1 14250 16150 + 1 0 0 -1 +$EndComp +$Comp +L tristate_nor U45 +U 1 1 685937BE +P 13150 17700 +F 0 "U45" H 16000 19500 60 0000 C CNN +F 1 "tristate_nor" H 16000 19700 60 0000 C CNN +F 2 "" H 16000 19650 60 0000 C CNN +F 3 "" H 16000 19650 60 0000 C CNN + 1 13150 17700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 15300 15750 15300 15800 +Wire Wire Line + 15300 15900 14800 15900 +Wire Wire Line + 14800 15900 14800 16100 +Wire Wire Line + 14800 16100 14700 16100 +$Comp +L risingedge_dflipflop U9 +U 1 1 685937C9 +P 7150 18300 +F 0 "U9" H 10000 20100 60 0000 C CNN +F 1 "risingedge_dflipflop" H 10000 20300 60 0000 C CNN +F 2 "" H 10000 20250 60 0000 C CNN +F 3 "" H 10000 20250 60 0000 C CNN + 1 7150 18300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9300 16400 7350 16400 +$Comp +L d_inverter U37 +U 1 1 685937D0 +P 11650 15800 +F 0 "U37" H 11650 15700 60 0000 C CNN +F 1 "d_inverter" H 11650 15950 60 0000 C CNN +F 2 "" H 11700 15750 60 0000 C CNN +F 3 "" H 11700 15750 60 0000 C CNN + 1 11650 15800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 11950 15800 12000 15800 +Wire Wire Line + 13400 15700 13800 15700 +$Comp +L d_inverter U17 +U 1 1 685937D8 +P 8950 16500 +F 0 "U17" H 8950 16400 60 0000 C CNN +F 1 "d_inverter" H 8950 16650 60 0000 C CNN +F 2 "" H 9000 16450 60 0000 C CNN +F 3 "" H 9000 16450 60 0000 C CNN + 1 8950 16500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9250 16500 9300 16500 +Wire Wire Line + 10800 4150 10800 4900 +Wire Wire Line + 10800 4900 10950 4900 +Wire Wire Line + 10950 4900 10950 15800 +Wire Wire Line + 10950 15800 11350 15800 +Connection ~ 10800 4150 +Wire Wire Line + 10950 5500 8300 5500 +Wire Wire Line + 8300 5500 8300 16500 +Wire Wire Line + 8300 16500 8650 16500 +Connection ~ 10950 5500 +Wire Wire Line + 8600 15000 8300 15000 +Connection ~ 8300 15000 +Wire Wire Line + 8550 13550 8300 13550 +Connection ~ 8300 13550 +Wire Wire Line + 8500 12050 8300 12050 +Connection ~ 8300 12050 +Wire Wire Line + 8550 10400 8300 10400 +Connection ~ 8300 10400 +Wire Wire Line + 8500 8900 8300 8900 +Connection ~ 8300 8900 +Wire Wire Line + 8450 7450 8300 7450 +Connection ~ 8300 7450 +Wire Wire Line + 8400 5950 8300 5950 +Connection ~ 8300 5950 +Wire Wire Line + 11750 4150 14750 4150 +Wire Wire Line + 14750 4150 14750 6600 +Wire Wire Line + 14750 6600 14900 6600 +Wire Wire Line + 14900 6600 14900 16000 +Wire Wire Line + 14900 16000 15300 16000 +Wire Wire Line + 11700 3500 13450 3500 +Wire Wire Line + 13450 3500 13450 9200 +Wire Wire Line + 13450 9200 13550 9200 +Wire Wire Line + 13550 9200 13550 16150 +Wire Wire Line + 13550 16150 13800 16150 +Wire Wire Line + 10750 3500 10750 3850 +Wire Wire Line + 10750 3850 13250 3850 +Wire Wire Line + 13250 3850 13250 8050 +Wire Wire Line + 13250 8050 13350 8050 +Wire Wire Line + 13350 8050 13350 14100 +Wire Wire Line + 13350 14100 13450 14100 +Wire Wire Line + 13450 14100 13450 15800 +Wire Wire Line + 13450 15800 14400 15800 +Connection ~ 10750 3500 +Wire Wire Line + 13550 5500 13000 5500 +Wire Wire Line + 13000 5500 13000 5850 +Wire Wire Line + 13000 5850 10450 5850 +Wire Wire Line + 13600 7000 12950 7000 +Wire Wire Line + 12950 7000 12950 7350 +Wire Wire Line + 12950 7350 10500 7350 +Wire Wire Line + 13650 8450 13150 8450 +Wire Wire Line + 13150 8450 13150 8800 +Wire Wire Line + 13150 8800 10550 8800 +Wire Wire Line + 13700 9950 13200 9950 +Wire Wire Line + 13200 9950 13200 10300 +Wire Wire Line + 13200 10300 10600 10300 +Wire Wire Line + 13650 11600 13250 11600 +Wire Wire Line + 13250 11600 13250 11950 +Wire Wire Line + 13250 11950 10550 11950 +Wire Wire Line + 13700 13100 13250 13100 +Wire Wire Line + 13250 13100 13250 13450 +Wire Wire Line + 13250 13450 10600 13450 +Wire Wire Line + 13750 14550 13300 14550 +Wire Wire Line + 13300 14550 13300 14900 +Wire Wire Line + 13300 14900 10650 14900 +Wire Wire Line + 13800 16050 13300 16050 +Wire Wire Line + 13300 16050 13300 16400 +Wire Wire Line + 13300 16400 10700 16400 +Wire Wire Line + 13450 14300 14350 14300 +Connection ~ 13450 14300 +Wire Wire Line + 13750 14650 13550 14650 +Connection ~ 13550 14650 +Wire Wire Line + 13700 13200 13550 13200 +Connection ~ 13550 13200 +Wire Wire Line + 13350 12850 14300 12850 +Connection ~ 13350 12850 +Wire Wire Line + 13650 11700 13550 11700 +Connection ~ 13550 11700 +Wire Wire Line + 13350 11350 14250 11350 +Connection ~ 13350 11350 +Wire Wire Line + 13700 10050 13550 10050 +Connection ~ 13550 10050 +Wire Wire Line + 13350 9700 14300 9700 +Connection ~ 13350 9700 +Wire Wire Line + 13650 8550 13450 8550 +Connection ~ 13450 8550 +Wire Wire Line + 13350 8200 14250 8200 +Connection ~ 13350 8200 +Wire Wire Line + 13600 7100 13450 7100 +Connection ~ 13450 7100 +Wire Wire Line + 13250 6750 14100 6750 +Connection ~ 13250 6750 +Wire Wire Line + 13550 5600 13450 5600 +Connection ~ 13450 5600 +Wire Wire Line + 11100 5250 10950 5250 +Connection ~ 10950 5250 +Wire Wire Line + 11150 6750 10950 6750 +Connection ~ 10950 6750 +Wire Wire Line + 11200 8200 10950 8200 +Connection ~ 10950 8200 +Wire Wire Line + 11250 9700 10950 9700 +Connection ~ 10950 9700 +Wire Wire Line + 11200 11350 10950 11350 +Connection ~ 10950 11350 +Wire Wire Line + 11250 12850 10950 12850 +Connection ~ 10950 12850 +Wire Wire Line + 11300 14300 10950 14300 +Connection ~ 10950 14300 +Wire Wire Line + 11750 5150 7100 5150 +Wire Wire Line + 11800 6650 7100 6650 +Wire Wire Line + 11850 8100 7150 8100 +Wire Wire Line + 11900 9600 7200 9600 +Wire Wire Line + 11850 11250 7250 11250 +Wire Wire Line + 11900 12750 7250 12750 +Wire Wire Line + 11950 14200 7300 14200 +Wire Wire Line + 12000 15700 7300 15700 +Wire Wire Line + 16450 5250 17250 5250 +Wire Wire Line + 15050 5450 14750 5450 +Connection ~ 14750 5450 +Wire Wire Line + 15100 6950 14900 6950 +Connection ~ 14900 6950 +Wire Wire Line + 16500 6750 17250 6750 +Wire Wire Line + 15150 8400 14900 8400 +Connection ~ 14900 8400 +Wire Wire Line + 16550 8200 17300 8200 +Wire Wire Line + 15200 9900 14900 9900 +Connection ~ 14900 9900 +Wire Wire Line + 16600 9700 17250 9700 +Wire Wire Line + 15150 11550 14900 11550 +Connection ~ 14900 11550 +Wire Wire Line + 16550 11350 17250 11350 +Wire Wire Line + 15200 13050 14900 13050 +Connection ~ 14900 13050 +Wire Wire Line + 16600 12850 17250 12850 +Wire Wire Line + 15250 14500 14900 14500 +Connection ~ 14900 14500 +Wire Wire Line + 16650 14300 17350 14300 +Wire Wire Line + 16700 15800 17350 15800 +$Comp +L PORT U1 +U 19 1 685A8DEA +P 17500 5250 +F 0 "U1" H 17550 5350 30 0000 C CNN +F 1 "PORT" H 17500 5250 30 0000 C CNN +F 2 "" H 17500 5250 60 0000 C CNN +F 3 "" H 17500 5250 60 0000 C CNN + 19 17500 5250 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 17 1 685A92C1 +P 7050 15700 +F 0 "U1" H 7100 15800 30 0000 C CNN +F 1 "PORT" H 7050 15700 30 0000 C CNN +F 2 "" H 7050 15700 60 0000 C CNN +F 3 "" H 7050 15700 60 0000 C CNN + 17 7050 15700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9800 3500 9600 3500 +Wire Wire Line + 9850 4150 9650 4150 +$Comp +L PORT U1 +U 18 1 685A98E8 +P 7100 16400 +F 0 "U1" H 7150 16500 30 0000 C CNN +F 1 "PORT" H 7100 16400 30 0000 C CNN +F 2 "" H 7100 16400 60 0000 C CNN +F 3 "" H 7100 16400 60 0000 C CNN + 18 7100 16400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 685A9F36 +P 9350 3500 +F 0 "U1" H 9400 3600 30 0000 C CNN +F 1 "PORT" H 9350 3500 30 0000 C CNN +F 2 "" H 9350 3500 60 0000 C CNN +F 3 "" H 9350 3500 60 0000 C CNN + 1 9350 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 685AA22F +P 9400 4150 +F 0 "U1" H 9450 4250 30 0000 C CNN +F 1 "PORT" H 9400 4150 30 0000 C CNN +F 2 "" H 9400 4150 60 0000 C CNN +F 3 "" H 9400 4150 60 0000 C CNN + 2 9400 4150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 685AA649 +P 6850 5150 +F 0 "U1" H 6900 5250 30 0000 C CNN +F 1 "PORT" H 6850 5150 30 0000 C CNN +F 2 "" H 6850 5150 60 0000 C CNN +F 3 "" H 6850 5150 60 0000 C CNN + 3 6850 5150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 685AA89A +P 6850 5850 +F 0 "U1" H 6900 5950 30 0000 C CNN +F 1 "PORT" H 6850 5850 30 0000 C CNN +F 2 "" H 6850 5850 60 0000 C CNN +F 3 "" H 6850 5850 60 0000 C CNN + 4 6850 5850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 685AAD7B +P 6850 6650 +F 0 "U1" H 6900 6750 30 0000 C CNN +F 1 "PORT" H 6850 6650 30 0000 C CNN +F 2 "" H 6850 6650 60 0000 C CNN +F 3 "" H 6850 6650 60 0000 C CNN + 5 6850 6650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 685AB0E6 +P 6900 7350 +F 0 "U1" H 6950 7450 30 0000 C CNN +F 1 "PORT" H 6900 7350 30 0000 C CNN +F 2 "" H 6900 7350 60 0000 C CNN +F 3 "" H 6900 7350 60 0000 C CNN + 6 6900 7350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 685AB34B +P 6900 8100 +F 0 "U1" H 6950 8200 30 0000 C CNN +F 1 "PORT" H 6900 8100 30 0000 C CNN +F 2 "" H 6900 8100 60 0000 C CNN +F 3 "" H 6900 8100 60 0000 C CNN + 7 6900 8100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 685AB51E +P 6950 9600 +F 0 "U1" H 7000 9700 30 0000 C CNN +F 1 "PORT" H 6950 9600 30 0000 C CNN +F 2 "" H 6950 9600 60 0000 C CNN +F 3 "" H 6950 9600 60 0000 C CNN + 9 6950 9600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 685AB80D +P 7000 10300 +F 0 "U1" H 7050 10400 30 0000 C CNN +F 1 "PORT" H 7000 10300 30 0000 C CNN +F 2 "" H 7000 10300 60 0000 C CNN +F 3 "" H 7000 10300 60 0000 C CNN + 10 7000 10300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 685ABADC +P 6950 8800 +F 0 "U1" H 7000 8900 30 0000 C CNN +F 1 "PORT" H 6950 8800 30 0000 C CNN +F 2 "" H 6950 8800 60 0000 C CNN +F 3 "" H 6950 8800 60 0000 C CNN + 8 6950 8800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 685ABEB6 +P 7000 11250 +F 0 "U1" H 7050 11350 30 0000 C CNN +F 1 "PORT" H 7000 11250 30 0000 C CNN +F 2 "" H 7000 11250 60 0000 C CNN +F 3 "" H 7000 11250 60 0000 C CNN + 11 7000 11250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 685AC0EF +P 6950 11950 +F 0 "U1" H 7000 12050 30 0000 C CNN +F 1 "PORT" H 6950 11950 30 0000 C CNN +F 2 "" H 6950 11950 60 0000 C CNN +F 3 "" H 6950 11950 60 0000 C CNN + 12 6950 11950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 685AC534 +P 7000 12750 +F 0 "U1" H 7050 12850 30 0000 C CNN +F 1 "PORT" H 7000 12750 30 0000 C CNN +F 2 "" H 7000 12750 60 0000 C CNN +F 3 "" H 7000 12750 60 0000 C CNN + 13 7000 12750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 685AC8F3 +P 7000 13450 +F 0 "U1" H 7050 13550 30 0000 C CNN +F 1 "PORT" H 7000 13450 30 0000 C CNN +F 2 "" H 7000 13450 60 0000 C CNN +F 3 "" H 7000 13450 60 0000 C CNN + 14 7000 13450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 15 1 685ACCB2 +P 7050 14200 +F 0 "U1" H 7100 14300 30 0000 C CNN +F 1 "PORT" H 7050 14200 30 0000 C CNN +F 2 "" H 7050 14200 60 0000 C CNN +F 3 "" H 7050 14200 60 0000 C CNN + 15 7050 14200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 685ACD93 +P 7050 14900 +F 0 "U1" H 7100 15000 30 0000 C CNN +F 1 "PORT" H 7050 14900 30 0000 C CNN +F 2 "" H 7050 14900 60 0000 C CNN +F 3 "" H 7050 14900 60 0000 C CNN + 16 7050 14900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 20 1 685AD214 +P 17500 6750 +F 0 "U1" H 17550 6850 30 0000 C CNN +F 1 "PORT" H 17500 6750 30 0000 C CNN +F 2 "" H 17500 6750 60 0000 C CNN +F 3 "" H 17500 6750 60 0000 C CNN + 20 17500 6750 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 24 1 685AD3F5 +P 17500 12850 +F 0 "U1" H 17550 12950 30 0000 C CNN +F 1 "PORT" H 17500 12850 30 0000 C CNN +F 2 "" H 17500 12850 60 0000 C CNN +F 3 "" H 17500 12850 60 0000 C CNN + 24 17500 12850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 21 1 685AD87F +P 17550 8200 +F 0 "U1" H 17600 8300 30 0000 C CNN +F 1 "PORT" H 17550 8200 30 0000 C CNN +F 2 "" H 17550 8200 60 0000 C CNN +F 3 "" H 17550 8200 60 0000 C CNN + 21 17550 8200 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 22 1 685ADB94 +P 17500 9700 +F 0 "U1" H 17550 9800 30 0000 C CNN +F 1 "PORT" H 17500 9700 30 0000 C CNN +F 2 "" H 17500 9700 60 0000 C CNN +F 3 "" H 17500 9700 60 0000 C CNN + 22 17500 9700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 23 1 685AE05F +P 17500 11350 +F 0 "U1" H 17550 11450 30 0000 C CNN +F 1 "PORT" H 17500 11350 30 0000 C CNN +F 2 "" H 17500 11350 60 0000 C CNN +F 3 "" H 17500 11350 60 0000 C CNN + 23 17500 11350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 25 1 685AE422 +P 17600 14300 +F 0 "U1" H 17650 14400 30 0000 C CNN +F 1 "PORT" H 17600 14300 30 0000 C CNN +F 2 "" H 17600 14300 60 0000 C CNN +F 3 "" H 17600 14300 60 0000 C CNN + 25 17600 14300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 26 1 685AE5BF +P 17600 15800 +F 0 "U1" H 17650 15900 30 0000 C CNN +F 1 "PORT" H 17600 15800 30 0000 C CNN +F 2 "" H 17600 15800 60 0000 C CNN +F 3 "" H 17600 15800 60 0000 C CNN + 26 17600 15800 + -1 0 0 1 +$EndComp +$Comp +L d_inverter U62 +U 1 1 685C5668 +P 13600 5100 +F 0 "U62" H 13600 5000 60 0000 C CNN +F 1 "d_inverter" H 13600 5250 60 0000 C CNN +F 2 "" H 13650 5050 60 0000 C CNN +F 3 "" H 13650 5050 60 0000 C CNN + 1 13600 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 13150 5150 13150 5100 +Wire Wire Line + 13150 5100 13300 5100 +Wire Wire Line + 13900 5100 13950 5100 +Wire Wire Line + 14850 5150 15050 5150 +Wire Wire Line + 13950 5200 13250 5200 +Connection ~ 13250 5200 +$Comp +L d_inverter U63 +U 1 1 685C746C +P 13850 6500 +F 0 "U63" H 13850 6400 60 0000 C CNN +F 1 "d_inverter" H 13850 6650 60 0000 C CNN +F 2 "" H 13900 6450 60 0000 C CNN +F 3 "" H 13900 6450 60 0000 C CNN + 1 13850 6500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 13550 6500 13550 6600 +Wire Wire Line + 13550 6600 13600 6600 +Wire Wire Line + 13600 6600 13600 6650 +Wire Wire Line + 14150 6500 14150 6600 +Wire Wire Line + 14150 6600 14100 6600 +Wire Wire Line + 14100 6600 14100 6650 +$Comp +L d_inverter U64 +U 1 1 685C855C +P 13950 8000 +F 0 "U64" H 13950 7900 60 0000 C CNN +F 1 "d_inverter" H 13950 8150 60 0000 C CNN +F 2 "" H 14000 7950 60 0000 C CNN +F 3 "" H 14000 7950 60 0000 C CNN + 1 13950 8000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 13650 8100 13650 8000 +Wire Wire Line + 14250 8000 14250 8100 +$Comp +L d_inverter U65 +U 1 1 685CC782 +P 13950 11100 +F 0 "U65" H 13950 11000 60 0000 C CNN +F 1 "d_inverter" H 13950 11250 60 0000 C CNN +F 2 "" H 14000 11050 60 0000 C CNN +F 3 "" H 14000 11050 60 0000 C CNN + 1 13950 11100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 13650 11250 13650 11100 +Wire Wire Line + 14250 11100 14250 11250 +$Comp +L d_inverter U66 +U 1 1 685CDA09 +P 14000 9450 +F 0 "U66" H 14000 9350 60 0000 C CNN +F 1 "d_inverter" H 14000 9600 60 0000 C CNN +F 2 "" H 14050 9400 60 0000 C CNN +F 3 "" H 14050 9400 60 0000 C CNN + 1 14000 9450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 13700 9600 13700 9450 +Wire Wire Line + 14300 9450 14300 9600 +$Comp +L d_inverter U67 +U 1 1 685CEA2B +P 14000 12600 +F 0 "U67" H 14000 12500 60 0000 C CNN +F 1 "d_inverter" H 14000 12750 60 0000 C CNN +F 2 "" H 14050 12550 60 0000 C CNN +F 3 "" H 14050 12550 60 0000 C CNN + 1 14000 12600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 13700 12750 13700 12600 +Wire Wire Line + 14300 12600 14300 12750 +$Comp +L d_inverter U68 +U 1 1 685CF9AB +P 14100 14000 +F 0 "U68" H 14100 13900 60 0000 C CNN +F 1 "d_inverter" H 14100 14150 60 0000 C CNN +F 2 "" H 14150 13950 60 0000 C CNN +F 3 "" H 14150 13950 60 0000 C CNN + 1 14100 14000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 13800 14200 13800 14000 +Wire Wire Line + 14400 14000 14400 14150 +Wire Wire Line + 14400 14150 14350 14150 +Wire Wire Line + 14350 14150 14350 14200 +$Comp +L d_inverter U69 +U 1 1 685D0C3C +P 14150 15500 +F 0 "U69" H 14150 15400 60 0000 C CNN +F 1 "d_inverter" H 14150 15650 60 0000 C CNN +F 2 "" H 14200 15450 60 0000 C CNN +F 3 "" H 14200 15450 60 0000 C CNN + 1 14150 15500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 13800 15700 13800 15500 +Wire Wire Line + 13800 15500 13850 15500 +Wire Wire Line + 14450 15500 14450 15600 +Wire Wire Line + 14450 15600 14350 15600 +Wire Wire Line + 14350 15600 14350 15700 +Wire Wire Line + 14350 15700 14400 15700 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS606/SN74LS606.sub b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS606/SN74LS606.sub new file mode 100644 index 000000000..a06e2adee --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS606/SN74LS606.sub @@ -0,0 +1,278 @@ +* Subcircuit SN74LS606 +.subckt SN74LS606 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ net-_u1-pad24_ net-_u1-pad25_ net-_u1-pad26_ +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\sn74ls606\sn74ls606.cir +* u26 net-_u1-pad1_ net-_u26-pad2_ d_inverter +* u28 net-_u26-pad2_ net-_u28-pad2_ d_inverter +* u18 net-_u1-pad3_ net-_u18-pad2_ net-_u18-pad3_ risingedge_dflipflop +* u27 net-_u1-pad2_ net-_u10-pad1_ d_inverter +* u30 net-_u10-pad1_ net-_u30-pad2_ d_inverter +* u46 net-_u46-pad1_ net-_u26-pad2_ net-_u38-pad1_ d_and +* u47 net-_u2-pad3_ net-_u28-pad2_ net-_u38-pad2_ d_and +* u38 net-_u38-pad1_ net-_u38-pad2_ net-_u30-pad2_ net-_u1-pad19_ tristate_nor +* u2 net-_u1-pad4_ net-_u10-pad2_ net-_u2-pad3_ risingedge_dflipflop +* u29 net-_u10-pad1_ net-_u18-pad2_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u19 net-_u1-pad5_ net-_u19-pad2_ net-_u19-pad3_ risingedge_dflipflop +* u48 net-_u48-pad1_ net-_u26-pad2_ ? d_and +* u49 net-_u3-pad3_ net-_u28-pad2_ net-_u39-pad2_ d_and +* u39 ? net-_u39-pad2_ net-_u30-pad2_ net-_u1-pad20_ tristate_nor +* u3 net-_u1-pad6_ net-_u11-pad2_ net-_u3-pad3_ risingedge_dflipflop +* u31 net-_u10-pad1_ net-_u19-pad2_ d_inverter +* u11 net-_u10-pad1_ net-_u11-pad2_ d_inverter +* u20 net-_u1-pad7_ net-_u20-pad2_ net-_u20-pad3_ risingedge_dflipflop +* u50 net-_u50-pad1_ net-_u26-pad2_ net-_u40-pad1_ d_and +* u51 net-_u4-pad3_ net-_u28-pad2_ net-_u40-pad2_ d_and +* u40 net-_u40-pad1_ net-_u40-pad2_ net-_u30-pad2_ net-_u1-pad21_ tristate_nor +* u4 net-_u1-pad8_ net-_u12-pad2_ net-_u4-pad3_ risingedge_dflipflop +* u32 net-_u10-pad1_ net-_u20-pad2_ d_inverter +* u12 net-_u10-pad1_ net-_u12-pad2_ d_inverter +* u22 net-_u1-pad9_ net-_u22-pad2_ net-_u22-pad3_ risingedge_dflipflop +* u54 net-_u54-pad1_ net-_u26-pad2_ net-_u42-pad1_ d_and +* u55 net-_u55-pad1_ net-_u28-pad2_ net-_u42-pad2_ d_and +* u42 net-_u42-pad1_ net-_u42-pad2_ net-_u30-pad2_ net-_u1-pad22_ tristate_nor +* u6 net-_u1-pad10_ net-_u14-pad2_ net-_u55-pad1_ risingedge_dflipflop +* u34 net-_u10-pad1_ net-_u22-pad2_ d_inverter +* u14 net-_u10-pad1_ net-_u14-pad2_ d_inverter +* u21 net-_u1-pad11_ net-_u21-pad2_ net-_u21-pad3_ risingedge_dflipflop +* u52 net-_u52-pad1_ net-_u26-pad2_ net-_u41-pad1_ d_and +* u53 net-_u5-pad3_ net-_u28-pad2_ net-_u41-pad2_ d_and +* u41 net-_u41-pad1_ net-_u41-pad2_ net-_u30-pad2_ net-_u1-pad23_ tristate_nor +* u5 net-_u1-pad12_ net-_u13-pad2_ net-_u5-pad3_ risingedge_dflipflop +* u33 net-_u10-pad1_ net-_u21-pad2_ d_inverter +* u13 net-_u10-pad1_ net-_u13-pad2_ d_inverter +* u23 net-_u1-pad13_ net-_u23-pad2_ net-_u23-pad3_ risingedge_dflipflop +* u56 net-_u56-pad1_ net-_u26-pad2_ net-_u43-pad1_ d_and +* u57 net-_u57-pad1_ net-_u28-pad2_ net-_u43-pad2_ d_and +* u43 net-_u43-pad1_ net-_u43-pad2_ net-_u30-pad2_ net-_u1-pad24_ tristate_nor +* u7 net-_u1-pad14_ net-_u15-pad2_ net-_u57-pad1_ risingedge_dflipflop +* u35 net-_u10-pad1_ net-_u23-pad2_ d_inverter +* u15 net-_u10-pad1_ net-_u15-pad2_ d_inverter +* u24 net-_u1-pad15_ net-_u24-pad2_ net-_u24-pad3_ risingedge_dflipflop +* u58 net-_u58-pad1_ net-_u26-pad2_ net-_u44-pad1_ d_and +* u59 net-_u59-pad1_ net-_u28-pad2_ net-_u44-pad2_ d_and +* u44 net-_u44-pad1_ net-_u44-pad2_ net-_u30-pad2_ net-_u1-pad25_ tristate_nor +* u8 net-_u1-pad16_ net-_u16-pad2_ net-_u59-pad1_ risingedge_dflipflop +* u36 net-_u10-pad1_ net-_u24-pad2_ d_inverter +* u16 net-_u10-pad1_ net-_u16-pad2_ d_inverter +* u25 net-_u1-pad17_ net-_u25-pad2_ net-_u25-pad3_ risingedge_dflipflop +* u60 net-_u60-pad1_ net-_u26-pad2_ net-_u45-pad1_ d_and +* u61 net-_u61-pad1_ net-_u28-pad2_ net-_u45-pad2_ d_and +* u45 net-_u45-pad1_ net-_u45-pad2_ net-_u30-pad2_ net-_u1-pad26_ tristate_nor +* u9 net-_u1-pad18_ net-_u17-pad2_ net-_u61-pad1_ risingedge_dflipflop +* u37 net-_u10-pad1_ net-_u25-pad2_ d_inverter +* u17 net-_u10-pad1_ net-_u17-pad2_ d_inverter +* u62 net-_u18-pad3_ net-_u46-pad1_ d_inverter +* u63 net-_u19-pad3_ net-_u48-pad1_ d_inverter +* u64 net-_u20-pad3_ net-_u50-pad1_ d_inverter +* u65 net-_u21-pad3_ net-_u52-pad1_ d_inverter +* u66 net-_u22-pad3_ net-_u54-pad1_ d_inverter +* u67 net-_u23-pad3_ net-_u56-pad1_ d_inverter +* u68 net-_u24-pad3_ net-_u58-pad1_ d_inverter +* u69 net-_u25-pad3_ net-_u60-pad1_ d_inverter +a1 net-_u1-pad1_ net-_u26-pad2_ u26 +a2 net-_u26-pad2_ net-_u28-pad2_ u28 +a3 [net-_u1-pad3_ ] [net-_u18-pad2_ ] [net-_u18-pad3_ ] u18 +a4 net-_u1-pad2_ net-_u10-pad1_ u27 +a5 net-_u10-pad1_ net-_u30-pad2_ u30 +a6 [net-_u46-pad1_ net-_u26-pad2_ ] net-_u38-pad1_ u46 +a7 [net-_u2-pad3_ net-_u28-pad2_ ] net-_u38-pad2_ u47 +a8 [net-_u38-pad1_ ] [net-_u38-pad2_ ] [net-_u30-pad2_ ] [net-_u1-pad19_ ] u38 +a9 [net-_u1-pad4_ ] [net-_u10-pad2_ ] [net-_u2-pad3_ ] u2 +a10 net-_u10-pad1_ net-_u18-pad2_ u29 +a11 net-_u10-pad1_ net-_u10-pad2_ u10 +a12 [net-_u1-pad5_ ] [net-_u19-pad2_ ] [net-_u19-pad3_ ] u19 +a13 [net-_u48-pad1_ net-_u26-pad2_ ] ? u48 +a14 [net-_u3-pad3_ net-_u28-pad2_ ] net-_u39-pad2_ u49 +a15 [? ] [net-_u39-pad2_ ] [net-_u30-pad2_ ] [net-_u1-pad20_ ] u39 +a16 [net-_u1-pad6_ ] [net-_u11-pad2_ ] [net-_u3-pad3_ ] u3 +a17 net-_u10-pad1_ net-_u19-pad2_ u31 +a18 net-_u10-pad1_ net-_u11-pad2_ u11 +a19 [net-_u1-pad7_ ] [net-_u20-pad2_ ] [net-_u20-pad3_ ] u20 +a20 [net-_u50-pad1_ net-_u26-pad2_ ] net-_u40-pad1_ u50 +a21 [net-_u4-pad3_ net-_u28-pad2_ ] net-_u40-pad2_ u51 +a22 [net-_u40-pad1_ ] [net-_u40-pad2_ ] [net-_u30-pad2_ ] [net-_u1-pad21_ ] u40 +a23 [net-_u1-pad8_ ] [net-_u12-pad2_ ] [net-_u4-pad3_ ] u4 +a24 net-_u10-pad1_ net-_u20-pad2_ u32 +a25 net-_u10-pad1_ net-_u12-pad2_ u12 +a26 [net-_u1-pad9_ ] [net-_u22-pad2_ ] [net-_u22-pad3_ ] u22 +a27 [net-_u54-pad1_ net-_u26-pad2_ ] net-_u42-pad1_ u54 +a28 [net-_u55-pad1_ net-_u28-pad2_ ] net-_u42-pad2_ u55 +a29 [net-_u42-pad1_ ] [net-_u42-pad2_ ] [net-_u30-pad2_ ] [net-_u1-pad22_ ] u42 +a30 [net-_u1-pad10_ ] [net-_u14-pad2_ ] [net-_u55-pad1_ ] u6 +a31 net-_u10-pad1_ net-_u22-pad2_ u34 +a32 net-_u10-pad1_ net-_u14-pad2_ u14 +a33 [net-_u1-pad11_ ] [net-_u21-pad2_ ] [net-_u21-pad3_ ] u21 +a34 [net-_u52-pad1_ net-_u26-pad2_ ] net-_u41-pad1_ u52 +a35 [net-_u5-pad3_ net-_u28-pad2_ ] net-_u41-pad2_ u53 +a36 [net-_u41-pad1_ ] [net-_u41-pad2_ ] [net-_u30-pad2_ ] [net-_u1-pad23_ ] u41 +a37 [net-_u1-pad12_ ] [net-_u13-pad2_ ] [net-_u5-pad3_ ] u5 +a38 net-_u10-pad1_ net-_u21-pad2_ u33 +a39 net-_u10-pad1_ net-_u13-pad2_ u13 +a40 [net-_u1-pad13_ ] [net-_u23-pad2_ ] [net-_u23-pad3_ ] u23 +a41 [net-_u56-pad1_ net-_u26-pad2_ ] net-_u43-pad1_ u56 +a42 [net-_u57-pad1_ net-_u28-pad2_ ] net-_u43-pad2_ u57 +a43 [net-_u43-pad1_ ] [net-_u43-pad2_ ] [net-_u30-pad2_ ] [net-_u1-pad24_ ] u43 +a44 [net-_u1-pad14_ ] [net-_u15-pad2_ ] [net-_u57-pad1_ ] u7 +a45 net-_u10-pad1_ net-_u23-pad2_ u35 +a46 net-_u10-pad1_ net-_u15-pad2_ u15 +a47 [net-_u1-pad15_ ] [net-_u24-pad2_ ] [net-_u24-pad3_ ] u24 +a48 [net-_u58-pad1_ net-_u26-pad2_ ] net-_u44-pad1_ u58 +a49 [net-_u59-pad1_ net-_u28-pad2_ ] net-_u44-pad2_ u59 +a50 [net-_u44-pad1_ ] [net-_u44-pad2_ ] [net-_u30-pad2_ ] [net-_u1-pad25_ ] u44 +a51 [net-_u1-pad16_ ] [net-_u16-pad2_ ] [net-_u59-pad1_ ] u8 +a52 net-_u10-pad1_ net-_u24-pad2_ u36 +a53 net-_u10-pad1_ net-_u16-pad2_ u16 +a54 [net-_u1-pad17_ ] [net-_u25-pad2_ ] [net-_u25-pad3_ ] u25 +a55 [net-_u60-pad1_ net-_u26-pad2_ ] net-_u45-pad1_ u60 +a56 [net-_u61-pad1_ net-_u28-pad2_ ] net-_u45-pad2_ u61 +a57 [net-_u45-pad1_ ] [net-_u45-pad2_ ] [net-_u30-pad2_ ] [net-_u1-pad26_ ] u45 +a58 [net-_u1-pad18_ ] [net-_u17-pad2_ ] [net-_u61-pad1_ ] u9 +a59 net-_u10-pad1_ net-_u25-pad2_ u37 +a60 net-_u10-pad1_ net-_u17-pad2_ u17 +a61 net-_u18-pad3_ net-_u46-pad1_ u62 +a62 net-_u19-pad3_ net-_u48-pad1_ u63 +a63 net-_u20-pad3_ net-_u50-pad1_ u64 +a64 net-_u21-pad3_ net-_u52-pad1_ u65 +a65 net-_u22-pad3_ net-_u54-pad1_ u66 +a66 net-_u23-pad3_ net-_u56-pad1_ u67 +a67 net-_u24-pad3_ net-_u58-pad1_ u68 +a68 net-_u25-pad3_ net-_u60-pad1_ u69 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u18 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u46 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u47 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: tristate_nor, NgSpice Name: tristate_nor +.model u38 tristate_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u2 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u19 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u48 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u49 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: tristate_nor, NgSpice Name: tristate_nor +.model u39 tristate_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u3 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u20 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u50 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u51 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: tristate_nor, NgSpice Name: tristate_nor +.model u40 tristate_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u4 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u22 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u54 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u55 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: tristate_nor, NgSpice Name: tristate_nor +.model u42 tristate_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u6 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u21 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u52 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u53 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: tristate_nor, NgSpice Name: tristate_nor +.model u41 tristate_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u5 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u23 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u56 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u57 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: tristate_nor, NgSpice Name: tristate_nor +.model u43 tristate_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u7 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u24 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u58 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u59 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: tristate_nor, NgSpice Name: tristate_nor +.model u44 tristate_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u8 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u25 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u60 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u61 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: tristate_nor, NgSpice Name: tristate_nor +.model u45 tristate_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: risingedge_dflipflop, NgSpice Name: risingedge_dflipflop +.model u9 risingedge_dflipflop(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u62 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u63 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u64 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u65 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u66 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u67 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u68 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u69 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SN74LS606 \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS606/SN74LS606_Previous_Values.xml b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS606/SN74LS606_Previous_Values.xml new file mode 100644 index 000000000..341664468 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS606/SN74LS606_Previous_Values.xml @@ -0,0 +1 @@ +d_inverterd_inverterrisingedge_dflipflopd_inverterd_inverterd_andd_andtristate_norrisingedge_dflipflopd_inverterd_inverterrisingedge_dflipflopd_andd_andtristate_norrisingedge_dflipflopd_inverterd_inverterrisingedge_dflipflopd_andd_andtristate_norrisingedge_dflipflopd_inverterd_inverterrisingedge_dflipflopd_andd_andtristate_norrisingedge_dflipflopd_inverterd_inverterrisingedge_dflipflopd_andd_andtristate_norrisingedge_dflipflopd_inverterd_inverterrisingedge_dflipflopd_andd_andtristate_norrisingedge_dflipflopd_inverterd_inverterrisingedge_dflipflopd_andd_andtristate_norrisingedge_dflipflopd_inverterd_inverterrisingedge_dflipflopd_andd_andtristate_norrisingedge_dflipflopd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_invertertruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS606/analysis b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS606/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LS606/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LVC1T45/SN74LVC1T45-cache.lib b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LVC1T45/SN74LVC1T45-cache.lib new file mode 100644 index 000000000..1efc12931 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LVC1T45/SN74LVC1T45-cache.lib @@ -0,0 +1,115 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# adc_bridge_1 +# +DEF adc_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_buffer +# +DEF d_buffer U 0 40 Y Y 1 F N +F0 "U" 0 -50 60 H V C CNN +F1 "d_buffer" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N +X IN 1 -500 0 200 R 50 50 1 1 I +X OUT 2 650 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# dac_bridge_1 +# +DEF dac_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# one_input_tristate_buffer +# +DEF one_input_tristate_buffer U 0 40 Y Y 1 F N +F0 "U" 2850 1800 60 H V C CNN +F1 "one_input_tristate_buffer" 2850 2000 60 H V C CNN +F2 "" 2850 1950 60 H V C CNN +F3 "" 2850 1950 60 H V C CNN +DRAW +S 2350 2100 3350 1600 0 1 0 N +X A0 1 2150 1900 200 R 50 50 1 1 I +X EN0 2 2150 1800 200 R 50 50 1 1 I +X Y0 3 3550 1900 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LVC1T45/SN74LVC1T45.cir b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LVC1T45/SN74LVC1T45.cir new file mode 100644 index 000000000..13bd2b07b --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LVC1T45/SN74LVC1T45.cir @@ -0,0 +1,25 @@ +* C:\Users\chand\esim\FOSSEE\eSim\library\SubcircuitLibrary\SN74LVC1T45\SN74LVC1T45.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/06/25 08:32:59 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U11-Pad2_ Net-_U2-Pad2_ d_inverter +U6 Net-_U13-Pad2_ Net-_U3-Pad1_ d_inverter +U5 Net-_U2-Pad2_ Net-_U5-Pad2_ d_buffer +U8 Net-_U2-Pad2_ Net-_U4-Pad2_ d_inverter +U4 Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U14-Pad1_ one_input_tristate_buffer +U9 Net-_U7-Pad2_ Net-_U5-Pad2_ Net-_U12-Pad1_ one_input_tristate_buffer +U1 Net-_U1-Pad1_ ? Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT +U3 Net-_U3-Pad1_ Net-_U3-Pad2_ d_inverter +U7 Net-_U10-Pad2_ Net-_U7-Pad2_ d_inverter +U12 Net-_U12-Pad1_ Net-_U1-Pad1_ dac_bridge_1 +U14 Net-_U14-Pad1_ Net-_U1-Pad6_ dac_bridge_1 +U13 Net-_U1-Pad3_ Net-_U13-Pad2_ adc_bridge_1 +U15 Net-_U1-Pad4_ Net-_U10-Pad1_ adc_bridge_1 +U11 Net-_U1-Pad5_ Net-_U11-Pad2_ adc_bridge_1 +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter + +.end diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LVC1T45/SN74LVC1T45.cir.out b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LVC1T45/SN74LVC1T45.cir.out new file mode 100644 index 000000000..aff45cbba --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LVC1T45/SN74LVC1T45.cir.out @@ -0,0 +1,68 @@ +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\sn74lvc1t45\sn74lvc1t45.cir + +* u2 net-_u11-pad2_ net-_u2-pad2_ d_inverter +* u6 net-_u13-pad2_ net-_u3-pad1_ d_inverter +* u5 net-_u2-pad2_ net-_u5-pad2_ d_buffer +* u8 net-_u2-pad2_ net-_u4-pad2_ d_inverter +* u4 net-_u3-pad2_ net-_u4-pad2_ net-_u14-pad1_ one_input_tristate_buffer +* u9 net-_u7-pad2_ net-_u5-pad2_ net-_u12-pad1_ one_input_tristate_buffer +* u1 net-_u1-pad1_ ? net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port +* u3 net-_u3-pad1_ net-_u3-pad2_ d_inverter +* u7 net-_u10-pad2_ net-_u7-pad2_ d_inverter +* u12 net-_u12-pad1_ net-_u1-pad1_ dac_bridge_1 +* u14 net-_u14-pad1_ net-_u1-pad6_ dac_bridge_1 +* u13 net-_u1-pad3_ net-_u13-pad2_ adc_bridge_1 +* u15 net-_u1-pad4_ net-_u10-pad1_ adc_bridge_1 +* u11 net-_u1-pad5_ net-_u11-pad2_ adc_bridge_1 +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +a1 net-_u11-pad2_ net-_u2-pad2_ u2 +a2 net-_u13-pad2_ net-_u3-pad1_ u6 +a3 net-_u2-pad2_ net-_u5-pad2_ u5 +a4 net-_u2-pad2_ net-_u4-pad2_ u8 +a5 [net-_u3-pad2_ ] [net-_u4-pad2_ ] [net-_u14-pad1_ ] u4 +a6 [net-_u7-pad2_ ] [net-_u5-pad2_ ] [net-_u12-pad1_ ] u9 +a7 net-_u3-pad1_ net-_u3-pad2_ u3 +a8 net-_u10-pad2_ net-_u7-pad2_ u7 +a9 [net-_u12-pad1_ ] [net-_u1-pad1_ ] u12 +a10 [net-_u14-pad1_ ] [net-_u1-pad6_ ] u14 +a11 [net-_u1-pad3_ ] [net-_u13-pad2_ ] u13 +a12 [net-_u1-pad4_ ] [net-_u10-pad1_ ] u15 +a13 [net-_u1-pad5_ ] [net-_u11-pad2_ ] u11 +a14 net-_u10-pad1_ net-_u10-pad2_ u10 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u5 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: one_input_tristate_buffer, NgSpice Name: one_input_tristate_buffer +.model u4 one_input_tristate_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: one_input_tristate_buffer, NgSpice Name: one_input_tristate_buffer +.model u9 one_input_tristate_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u12 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u14 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u13 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u15 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u11 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LVC1T45/SN74LVC1T45.pro b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LVC1T45/SN74LVC1T45.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LVC1T45/SN74LVC1T45.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LVC1T45/SN74LVC1T45.sch b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LVC1T45/SN74LVC1T45.sch new file mode 100644 index 000000000..dfff64379 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LVC1T45/SN74LVC1T45.sch @@ -0,0 +1,341 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN74LVC1T45-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U2 +U 1 1 6868DDB3 +P 3200 2500 +F 0 "U2" H 3200 2400 60 0000 C CNN +F 1 "d_inverter" H 3200 2650 60 0000 C CNN +F 2 "" H 3250 2450 60 0000 C CNN +F 3 "" H 3250 2450 60 0000 C CNN + 1 3200 2500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 6868DDED +P 4350 3650 +F 0 "U6" H 4350 3550 60 0000 C CNN +F 1 "d_inverter" H 4350 3800 60 0000 C CNN +F 2 "" H 4400 3600 60 0000 C CNN +F 3 "" H 4400 3600 60 0000 C CNN + 1 4350 3650 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U5 +U 1 1 6868DE43 +P 4300 2500 +F 0 "U5" H 4300 2450 60 0000 C CNN +F 1 "d_buffer" H 4300 2550 60 0000 C CNN +F 2 "" H 4300 2500 60 0000 C CNN +F 3 "" H 4300 2500 60 0000 C CNN + 1 4300 2500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U8 +U 1 1 6868DEAE +P 6850 2500 +F 0 "U8" H 6850 2400 60 0000 C CNN +F 1 "d_inverter" H 6850 2650 60 0000 C CNN +F 2 "" H 6900 2450 60 0000 C CNN +F 3 "" H 6900 2450 60 0000 C CNN + 1 6850 2500 + -1 0 0 1 +$EndComp +$Comp +L one_input_tristate_buffer U4 +U 1 1 6868DFCC +P 4050 5400 +F 0 "U4" H 6900 7200 60 0000 C CNN +F 1 "one_input_tristate_buffer" H 6900 7400 60 0000 C CNN +F 2 "" H 6900 7350 60 0000 C CNN +F 3 "" H 6900 7350 60 0000 C CNN + 1 4050 5400 + 1 0 0 -1 +$EndComp +$Comp +L one_input_tristate_buffer U9 +U 1 1 6868E207 +P 7250 6500 +F 0 "U9" H 10100 8300 60 0000 C CNN +F 1 "one_input_tristate_buffer" H 10100 8500 60 0000 C CNN +F 2 "" H 10100 8450 60 0000 C CNN +F 3 "" H 10100 8450 60 0000 C CNN + 1 7250 6500 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 6868E5A7 +P 2050 4600 +F 0 "U1" H 2100 4700 30 0000 C CNN +F 1 "PORT" H 2050 4600 30 0000 C CNN +F 2 "" H 2050 4600 60 0000 C CNN +F 3 "" H 2050 4600 60 0000 C CNN + 1 2050 4600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 6868E654 +P 950 1250 +F 0 "U1" H 1000 1350 30 0000 C CNN +F 1 "PORT" H 950 1250 30 0000 C CNN +F 2 "" H 950 1250 60 0000 C CNN +F 3 "" H 950 1250 60 0000 C CNN + 2 950 1250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 6868E6BA +P 9550 4450 +F 0 "U1" H 9600 4550 30 0000 C CNN +F 1 "PORT" H 9550 4450 30 0000 C CNN +F 2 "" H 9550 4450 60 0000 C CNN +F 3 "" H 9550 4450 60 0000 C CNN + 4 9550 4450 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 6868E7C4 +P 7950 5000 +F 0 "U1" H 8000 5100 30 0000 C CNN +F 1 "PORT" H 7950 5000 30 0000 C CNN +F 2 "" H 7950 5000 60 0000 C CNN +F 3 "" H 7950 5000 60 0000 C CNN + 6 7950 5000 + 0 -1 -1 0 +$EndComp +NoConn ~ 1200 1250 +$Comp +L d_inverter U3 +U 1 1 68690591 +P 5550 3450 +F 0 "U3" H 5550 3350 60 0000 C CNN +F 1 "d_inverter" H 5550 3600 60 0000 C CNN +F 2 "" H 5600 3400 60 0000 C CNN +F 3 "" H 5600 3400 60 0000 C CNN + 1 5550 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 6868E689 +P 2250 3650 +F 0 "U1" H 2300 3750 30 0000 C CNN +F 1 "PORT" H 2250 3650 30 0000 C CNN +F 2 "" H 2250 3650 60 0000 C CNN +F 3 "" H 2250 3650 60 0000 C CNN + 3 2250 3650 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 6869E83C +P 6050 4450 +F 0 "U7" H 6050 4350 60 0000 C CNN +F 1 "d_inverter" H 6050 4600 60 0000 C CNN +F 2 "" H 6100 4400 60 0000 C CNN +F 3 "" H 6100 4400 60 0000 C CNN + 1 6050 4450 + -1 0 0 1 +$EndComp +$Comp +L dac_bridge_1 U12 +U 1 1 6869ECDE +P 2950 4650 +F 0 "U12" H 2950 4650 60 0000 C CNN +F 1 "dac_bridge_1" H 2950 4800 60 0000 C CNN +F 2 "" H 2950 4650 60 0000 C CNN +F 3 "" H 2950 4650 60 0000 C CNN + 1 2950 4650 + -1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U14 +U 1 1 6869F103 +P 8000 4050 +F 0 "U14" H 8000 4050 60 0000 C CNN +F 1 "dac_bridge_1" H 8000 4200 60 0000 C CNN +F 2 "" H 8000 4050 60 0000 C CNN +F 3 "" H 8000 4050 60 0000 C CNN + 1 8000 4050 + 0 -1 1 0 +$EndComp +$Comp +L adc_bridge_1 U13 +U 1 1 6869F41C +P 3350 3700 +F 0 "U13" H 3350 3700 60 0000 C CNN +F 1 "adc_bridge_1" H 3350 3850 60 0000 C CNN +F 2 "" H 3350 3700 60 0000 C CNN +F 3 "" H 3350 3700 60 0000 C CNN + 1 3350 3700 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_1 U15 +U 1 1 6869F7C3 +P 8650 4400 +F 0 "U15" H 8650 4400 60 0000 C CNN +F 1 "adc_bridge_1" H 8650 4550 60 0000 C CNN +F 2 "" H 8650 4400 60 0000 C CNN +F 3 "" H 8650 4400 60 0000 C CNN + 1 8650 4400 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 6868E73F +P 1350 2500 +F 0 "U1" H 1400 2600 30 0000 C CNN +F 1 "PORT" H 1350 2500 30 0000 C CNN +F 2 "" H 1350 2500 60 0000 C CNN +F 3 "" H 1350 2500 60 0000 C CNN + 5 1350 2500 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_1 U11 +U 1 1 686A0075 +P 2250 2550 +F 0 "U11" H 2250 2550 60 0000 C CNN +F 1 "adc_bridge_1" H 2250 2700 60 0000 C CNN +F 2 "" H 2250 2550 60 0000 C CNN +F 3 "" H 2250 2550 60 0000 C CNN + 1 2250 2550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3500 2500 3800 2500 +Wire Wire Line + 4950 2500 5400 2500 +Wire Wire Line + 5400 2500 5400 4700 +Wire Wire Line + 5400 4700 5100 4700 +Wire Wire Line + 4850 3650 4650 3650 +Wire Wire Line + 4850 3450 4850 3650 +Wire Wire Line + 6550 2500 5900 2500 +Wire Wire Line + 5900 2500 5900 3600 +Wire Wire Line + 5900 3600 6200 3600 +Wire Wire Line + 5100 4600 5100 4450 +Wire Wire Line + 3650 2500 3650 1950 +Wire Wire Line + 3650 1950 7350 1950 +Wire Wire Line + 7350 1950 7350 2500 +Wire Wire Line + 7350 2500 7150 2500 +Connection ~ 3650 2500 +Wire Wire Line + 4850 3450 5250 3450 +Wire Wire Line + 5850 3450 6200 3450 +Wire Wire Line + 6200 3450 6200 3500 +Wire Wire Line + 5100 4450 5750 4450 +Wire Wire Line + 6350 4450 7050 4450 +Wire Wire Line + 3550 4600 3700 4600 +Wire Wire Line + 2300 4600 2400 4600 +Wire Wire Line + 7950 4600 7950 4750 +Wire Wire Line + 2500 3650 2750 3650 +Wire Wire Line + 3900 3650 4050 3650 +Wire Wire Line + 7600 3500 7600 3350 +Wire Wire Line + 7600 3350 7950 3350 +Wire Wire Line + 7950 3350 7950 3450 +Wire Wire Line + 7650 4450 8100 4450 +Wire Wire Line + 9250 4450 9300 4450 +Wire Wire Line + 1600 2500 1650 2500 +Wire Wire Line + 2800 2500 2900 2500 +$Comp +L d_inverter U10 +U 1 1 6869E7BE +P 7350 4450 +F 0 "U10" H 7350 4350 60 0000 C CNN +F 1 "d_inverter" H 7350 4600 60 0000 C CNN +F 2 "" H 7400 4400 60 0000 C CNN +F 3 "" H 7400 4400 60 0000 C CNN + 1 7350 4450 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LVC1T45/SN74LVC1T45.sub b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LVC1T45/SN74LVC1T45.sub new file mode 100644 index 000000000..d0a80e0b1 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LVC1T45/SN74LVC1T45.sub @@ -0,0 +1,62 @@ +* Subcircuit SN74LVC1T45 +.subckt SN74LVC1T45 net-_u1-pad1_ ? net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\sn74lvc1t45\sn74lvc1t45.cir +* u2 net-_u11-pad2_ net-_u2-pad2_ d_inverter +* u6 net-_u13-pad2_ net-_u3-pad1_ d_inverter +* u5 net-_u2-pad2_ net-_u5-pad2_ d_buffer +* u8 net-_u2-pad2_ net-_u4-pad2_ d_inverter +* u4 net-_u3-pad2_ net-_u4-pad2_ net-_u14-pad1_ one_input_tristate_buffer +* u9 net-_u7-pad2_ net-_u5-pad2_ net-_u12-pad1_ one_input_tristate_buffer +* u3 net-_u3-pad1_ net-_u3-pad2_ d_inverter +* u7 net-_u10-pad2_ net-_u7-pad2_ d_inverter +* u12 net-_u12-pad1_ net-_u1-pad1_ dac_bridge_1 +* u14 net-_u14-pad1_ net-_u1-pad6_ dac_bridge_1 +* u13 net-_u1-pad3_ net-_u13-pad2_ adc_bridge_1 +* u15 net-_u1-pad4_ net-_u10-pad1_ adc_bridge_1 +* u11 net-_u1-pad5_ net-_u11-pad2_ adc_bridge_1 +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +a1 net-_u11-pad2_ net-_u2-pad2_ u2 +a2 net-_u13-pad2_ net-_u3-pad1_ u6 +a3 net-_u2-pad2_ net-_u5-pad2_ u5 +a4 net-_u2-pad2_ net-_u4-pad2_ u8 +a5 [net-_u3-pad2_ ] [net-_u4-pad2_ ] [net-_u14-pad1_ ] u4 +a6 [net-_u7-pad2_ ] [net-_u5-pad2_ ] [net-_u12-pad1_ ] u9 +a7 net-_u3-pad1_ net-_u3-pad2_ u3 +a8 net-_u10-pad2_ net-_u7-pad2_ u7 +a9 [net-_u12-pad1_ ] [net-_u1-pad1_ ] u12 +a10 [net-_u14-pad1_ ] [net-_u1-pad6_ ] u14 +a11 [net-_u1-pad3_ ] [net-_u13-pad2_ ] u13 +a12 [net-_u1-pad4_ ] [net-_u10-pad1_ ] u15 +a13 [net-_u1-pad5_ ] [net-_u11-pad2_ ] u11 +a14 net-_u10-pad1_ net-_u10-pad2_ u10 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u5 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: one_input_tristate_buffer, NgSpice Name: one_input_tristate_buffer +.model u4 one_input_tristate_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: one_input_tristate_buffer, NgSpice Name: one_input_tristate_buffer +.model u9 one_input_tristate_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u12 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u14 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u13 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u15 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u11 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SN74LVC1T45 \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LVC1T45/SN74LVC1T45_Previous_Values.xml b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LVC1T45/SN74LVC1T45_Previous_Values.xml new file mode 100644 index 000000000..f8839c562 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LVC1T45/SN74LVC1T45_Previous_Values.xml @@ -0,0 +1 @@ +d_inverterd_inverterd_bufferd_inverterd_inverterone_input_tristate_bufferd_inverterone_input_tristate_bufferd_inverterdac_bridgedac_bridgeadc_bridgeadc_bridgeadc_bridgetruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LVC1T45/analysis b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LVC1T45/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/Chandru_IC_Subcircuits/SN74LVC1T45/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file